L7250 5V & 12V SPINDLE AND VCM MOTORS DRIVER PRODUCT PREVIEW s s s
s
12V & 5V ( ±10%) OPERATION REGISTER BASED ARCHI ARCHITECTURE TECTURE 3 WIRE SERIAL COMMUNICATION INTERFACE UP TO 33 MHZ BCD TECHNOLOGY
Spindle Motor Controller Controller s INTERNAL POWER DEVICE 0.9 OHM MAX VALUE @ 125 °C (SINK+S (SINK+SOURCE) OURCE) s 2.5A PEAK CURRENT CAPABILITY CAPABILITY s ST SMOOTHDRIVE SINUSOIDAL PWM COMMUTATION s DEDICATED ADC FOR POWER SUPPLY VOLTAGE COMPENSA COMPENSATION TION s SPINDLE CURRENT LIMITING VIA FIXED FREQUENCY PWM OF SPINDLE POWER OUTPUTS AT THE SMOOTHDRIVE PWM RATE SYNCHRONOUS NOUS RECTIFICATIO RECTIFICATION N DURING s SYNCHRO PWM TO REDUCE POWER DISSIPATION s CURRENT SENSI SENSING NG VIA EXTER EXTERNAL NAL CURRENT SENSE RESISTOR RESISTOR INDUCTIVE IVE SENSE SENSE POS POSITI ITION ON START UP s INDUCT DRIVEN BY µPROCESSOR s SPINDLE BRAKING DURING POWER DOWN CONDITION Voice Coil Motor Drive Driverr with Ramp Ramp Load/Un Load/Unload s INTERNAL POWER DEVICE 0.9 OHM MAX VALUE @ 125 °C (SINK+S (SINK+SOURCE) OURCE) s 2A PEAK CURRENT CAPABILITY s 15 BIT LINEAR DAC FOR CURRENT COMMAND, WITH INTERNAL REFERENCE VOLTAGE s SENSE AMPLIFIER GAIN SWITCH s CLASS AB OUTPUT STAGE WITH ZERO DEAD-BAND DEAD-BA ND AND MINIMAL CROSSOVER CROSSOVER DISTORTION s RAMP LOAD AND UNLOAD CAPABILITY AS WELL AS CONSTANT VOLTAGE RETRACT s EXTERN EXTERNAL AL CURRENT SENSE RESISTOR RESISTOR IN SERIES WITH MOTOR. s HIGH CMRR (>70DB) AND PSRR (>60DB) SENSE AMP s EXTERNAL CURRENT CONTROL LOOP COMPENSATION s HIGH BANDWIDTH VCM CURRENT CONTROL LOOP C APAB APABILITY ILITY s HIGH PSRR, LOW OFFSET, LOW DRIFT GM LOOP
TQFP64 ORDERING NUMBER: L7250 s
s
VCM VOLTAGE MODE, CONTROLLED BY VCM DAC GM LOOP OFFSET CALIBRATION SCHEME INCLUDES A COMPARATOR ON THE ERROR AMP
Auxiliary Functio Functions ns s 3.3V AND 1.8V LINEAR REGULATOR CONTROLLER s NEGATIVE VOLTAGE R EGULATOR s INTERNAL ISOFET 0.1 OHM @125C s POWER MONITOR OF 12V, 5V, 3.3V AND 1.8V s SHOCK SENSOR CIRCUIT TAKES INPUTS FROM PIEZO OR CHARGING ELEMENT s 10 BIT ADC WITH 4 MUXED INPUTS s THER THERMAL MAL SENSE SENSE CIRC CIRCUIT UIT AND OVER TEMPERATURE SHUT DOWN s CHARGE PUMP BOOST VOLTAGE GENERATOR FOR HIGH SIDE GATE DRIVE s ANALOG PINS AVAILABLE TO ENTER SIGNALS TO BE CONVERTED BY THE INTERNAL ADC DESCRIPTION L7250 is a pow L7250 power er IC for driving driving the SPI SPINDL NDLE E and VCM motors, suitable for 5V & 12V application. The spindl spi ndle e syst system em incl include udes s inte integra grated ted pow power er FET FETs s which are driven using ST’s Smoothdrive pseudo-sinusoidal commutation technology. The voice coil motor (VCM) syste system m includes integrated integrated powe powerr FETs FETs,, as well as ramp load and unload unload capabilit capability. y. Linea Linearr 3.3V and1.8V and1.8V voltage regulators are included, included, as well as a negative regulator. Power monitoring of VCC5, VCC12, and of the two positive posit ive voltag voltage e regu regulator lators s is also includ included.L ed.L7 7250 uses a 3 wire serial interface: S_DATA, S_CLK and S_ENABLE
July 2001 This is preliminary information on a new product now in development. Details are subject to change without notice.
1/46
L7250 PIN CONNE CONNECTIO CTION N (Top view) 2 1 4 3 T H N N S C T U U T E E O S C T U U S S O O O O R R B P V C 4 3 2 6 6 6
2 1 e 2 1 3 4 V V V V 2 1 W W s T T T n e M M T U U C C U U s V V V V O O O O R
1 0 9 8 7 6 6 5 5 5
6 5
5 4 3 5 5 5
2 1 0 9 5 5 5 4
VCV1 VCV2 VCMP1 VCMP2
01
48
02
47
03
46
04
45
RSEN2 RSEN1 VCMN2 VCMN1
VCMGND1
05
44
VCMGND4
VCMGND2
06
43
VCMGND3
CPOSC
07
42
SNS_N
VCC5 DIG_GND
08
41
09
40
SNS_P SNS_OUT
N_DRV
10
39
ERR_OUT
N_FEED
11
38
ERR_IN
N_COMP
12
37
DAC_OUT
25_BASE
13
36
SCLK
25_FEED
14
35
SYSClk
33_BASE 33_FEED
15
34
SDATA
16
33
SEN
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3
5 R R E K D 2 C i n O O A N F P P R G E Z k S C N B A R V C
t i u n o F k k S S
t t 1 e r u u r s o o e a F D m o k k i l C S S T a C
F x M t u E s e a D B T A M C V
PIN DESCR DESCRIPTIO IPTION N N°
P in
V
1
VCV1
S12
1 2V p ower supply
2
VCV2
S12
1 2V p ower supply and POR sensing th re reshold
3
VCMP1
O 12
V CM positive out put
4
VCMP2
O 12
V CM positive out put
5
V CMGN D1
gn d
V CM power ground
6
V CMGN D2
gn d
V CM power ground
7
C POSC
O 12
C harge pump os cillator
8
VCC 5
S5
5 V power su pply
9
DIG DI G_GND
gnd
Dig Di gital & Switc tch hin ing g regu gullat ato or groun und d
10
N_DRV
O5
N eg Reg ext FE F ET gate d ri ver
11
N _FEED
I5
N eg Reg feedback
12
N _COMP
IO5
2/46
D escripti on
N eg Reg er ror output
L7250 PIN DESCR DESCRIPTIO IPTION N (continued) N°
P in
V
D escripti on
13
2 5_BASE
O5
14
2 5_FEED
I5
15
3 3_BASE
O5
R eg 3.3V ext NPN base
16
3 3_FEED
IO5
R eg 3.3 V feedback
17
C POR
IO5
P OR d elay ca ca pacit or
18
N POR
O5
P OR o utput signal
19
C BRAKE
IO5
S pi pindle brake capacitor
20
AGND
gn d
a n al og gn d
21
VREF 25
IO5
2 .5V reference
22
ZC
O5
S pindle zero cr ossing
23
Skin
I5
S hock sensor input
24
Skout
O5
S hock sensor 1st opamp o utput
25
SkFi n
I5
S hock sensor fil ter input
26
Sk Fout
O5
S hock sensor fil ter output
27
SkDout
O5
S hock sensor output
28
Timer 1
IO5
T im imer 1 for unload procedure
29
C al alCoarse
I5
V CM CM BEMF coarse calibration
30
ADaux
I5
a uxiliary input for the ADC
31
V CM CMBE MF MF
O5
V CM CM BEMF processor output
32
Test
IO5
u sed for te t esti ng po rpouse (* )
33
SEN
I5
34
S DATA
IO5
35
SYSClk
I5
S ystem clock
36
SCLK
I5
S er ial cl ock
37
DAC_OUT
O5
V CM DAC output
38
E RR_IN
I5
39
E RR_OUT
O5
V CM CM error o pamp outp ut
40
SNS_O UT
O5
V CM CM sense opamp ou tput
41
SNS_P
I1 2
V CM sense opamp po sitive input
42
SNS_ N
I1 2
V CM CM sense opamp ne gative input
43
V CMGN D3
gn d
V CM power ground
R eg 1.8V ext NPN base R eg 1.8V feedback
S e r i al en a b l e S e r i a l d a ta
V CM error o pamp input
3/46
L7250 PIN DESCR DESCRIPTIO IPTION N (continued) N°
P in
V
D escripti on
44
V CMGN D4
gn d
V CM power ground
45
VCMN 1
O 12
V CM negative ou tput
46
VCMN 2
O 12
V CM negative ou tput
47
RSEN 1
O 12 12
S pi pindle power se nsing resito r
48
RSEN 2
O 12 12
S pi pindle power se nsing resito r
49
R sense
I5
S pindle sensing resisto r input
50
OUTW 1
O 12
S pindle phase C output
51
OUTW 2
O 12
S pindle phase C output
52
VM1
IO 1 2
V moto r
53
VM2
IO 1 2
V moto r
54
VCV4
S12
1 2V p ower supply
55
VCV3
S12
1 2V p ower supply
56
OUTV 1
O 12
S pindle phase B output
57
OUTV 2
O 12
S pindle phase B output
58
RSEN 3
O 12 12
S pi pindle power se nsing resito r
59
RSEN 4
O 12 12
S pi pindle power se nsing resito r
60
OUT U1
O 12
S pindle phase A output
61
OUT U2
O 12
S pindle phase A output
62
CT
I1 2
S pindle central tap
63
CPO CP OSCH
IO2 O20 0
Char Ch arge ge pum ump p dio iode des s co con nnectio ion n
64
V BOOST
IO 20 20
C harge Pump voltage
(*) used also to set the IC power supply application. If this pin is pull-up externally the L7250 became a 5V application
S = Supply ; IO = Input/Output ; I = Input ; O = Output ; gnd = Ground.
4/46
L7250 ELECTRICAL CHARACTERISTCS ABSOLU ABSO LUTE TE MAXIM MAXIMUM UM RATIN RATING GS Symb ol
Parameter
Value
Unit
VCV1,V CV2, VCV3,VCV 4
14
V
VCC5 m aximum voltage
6
V
-1 V to 16
V
- 0.3 to V CC5
V
0 to 7 0
°C
-55 to 1 50
°C
OUTU1,OUTU2,OUTV1,OUTV2,OUTW1,OUTW2 VCMP1,VCMP2,VCMN1,VCMN2 VM1,VM2 Digital In put Voltage Operating free-ai r temperature Storage Temperature
ELECTRICAL CHARACTERISTCS POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol
±10%,
Parameter
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified) Test Condition
M in .
Typ.
M ax .
Unit
POWER MONITO MONITOR, R, SUPPL SUPPLY Y CURRE CURRENTS, NTS, ETC. Icc5
VCC5 Oper erat atin ing g cur urrrent
Spindl Spi dle e and VCM ena nab bled ed,, no load
9
mA
Ivcv Iv cv
VCV VC V + VR VRET ET Op Oper erat ating ing cur curre rent nt
Spindle Spindl e and VC VCM M ena enable bled, d, no load
44
mA
1 8 .5
V
1
M Hz MH
CHARGE PUMP VOLTAGE BOOSTER VBOOS T
Char Ch arge ge pu pump mp ou outp tput ut vo volt ltag age e
VBOOS Tfreq
Swi tching fr equency
VCV = 12 12V V Iload = 5mA
POWER MONITOR vt5
VCC5 thres hold
4. 0
4 .1 7 5
4. 35
V
vt12
VCC12 threshold
9
9 .5
10
V
hv5
VCC5 hysteresis
40
1 00
16 0
mV
hv12
VCC12 hysteresis
100
2 00
30 0
mV
vt33
V33 Thresh old
2. 7
2 .8
2 .9
V
hv33
V33 Hystere sis
20
40
60
mV
vt18
V18 Thresh old (a t pin 25_FEED) V1
1. 0 7
1 .1 2
1. 17
V
hv18
V18Hystere sis
25
50
75
mV
NPOR low
N POR low level o utput voltage
V CV > 4.5V Iol = 5mA
0 .7 5
V
5/46
L7250 ELECTRICAL CHARACTERISTCS (continued) POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol
Parameter
NPORpull
NPOR internal pull_up resistor to V33
±10%,
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified) Test Condition
M in .
Typ.
M ax .
Unit
6
Kohm
CPOR Ic
C POR charging c urrent
Vout = 0V
5
uA
CPOR low
C POR low level o utput voltage
V CV > 4.5V Iol = 1mA
50
mV
Vref2 5
2.5V r eference voltage
- 5%
2 .5
+5%
V
THERMAL WARNING AND THERMAL SHUTDOWN SHUTDOWN Twarn
Thermall warm Therma warming ing tempe temperat rature ure
Characte Chara cteriz rized, ed, tes tested ted by correlation.
13 0
1 40
15 0
°C
Tsoff Ts off
Thermal Ther mal Shu Shutd tdown own te temp mpera eratu ture re
Chara Cha ract cter eriz ized ed,, tes tested ted by correlation
15 0
1 65
18 0
°C
T hy hys
T he hermal Hy steresis
valid for b oth t em emperature thresholds
20
25
30
°C
0 .1
Ohm
2 .5
A
0 .9
Ω
- 500
µA
1
µA
1 .2
V
VM ISOLATION ISOLATION FET IsoR
R ds ON
IsoI
C ontinuous cu rrent
@ 1 25°C , I=2.5A
SPINDLE DRIVER SECTION POWER STAGE Rds(on) Rds (on) Idsx C Tlkg
Tota otall outpu outputt ON resistan resistance ce (Source + Sink) Outpu t leakage current
- 20 0
C entarl t ap leakage
D iodeFw C lamp diode forward voltage Sle w
@ 125°C, I=2. 5A
Outpu t slew rate
I f = 2.5 A
0 .6
O UTx 1 0% to 90% Reg04H ‘b7b6b5’ = 011
40
V /µS
BACK EMF COMP COMPARA ARATOR TOR Vie Vi e
Common Commo n mo mode de in inpu putt vo volt ltag age e range.
G uaranteed by design
0
VM
V
Vr
Input vo Input volt ltage age ra rang nge e whe where re out output put shall not invert.
G uaranteed by design
-1
VM+1
V
- 15
+1 5
mV
BE MFoff BEMF input offset
CT = 6 V
BEMFhy
CT = 6 V
BEMF hysteresys
50
mV
SPINDLE CURRENT LIMITING Ii n C URoff
6/46
R SENSE Input b ias current. C omparator o ffset
0 < V i n < 3 .3 V - 15
1
µA
+ 15
mV
L7250 ELECTRICAL CHARACTERISTCS (continued) POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol
±10%,
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified)
Parameter
Test Condition
M in .
CURdacr DAC resolution
Typ.
M ax .
Unit
3
bi t
CURdac_L
DAC output
R e g 0 4H ‘ b 4 b3 b 2’ = 0 0 0
2 50
mV
CURdac_H
DAC output
R e g 0 4H ‘ b 4 b3 b 2’ = 1 1 1
6 00
mV
CUR lin
DAC linearity
- 10
+ 10
mV
1
µA
-0.6
VM+1
V
- 12
12
mV
Cbrake Ic brake
VCbrake leakage
V Cbrake=5V
VCM SECTION CURRENT SENSE AMPLIFIER Vts Vt s
Common Comm on mod mode e in inpu putt vo volt ltag age e range.
G BD - not tested
Sns _voff Input offset voltage Sns_gain0
D ifferential Voltage G AIN0
R e g 09 H ‘ b 7’ = 0
- 5%
4. 5
+5%
Sns _gain1
D ifferential Voltage G AIN1
R e g 09 H ‘ b 7’ = 1
- 5%
16
+5%
Sns_low
VSENSE output satura saturation tion voltage
Iload=+/-1mA Vin_diff=+/-- 500mV Vin_diff=+/
Sns_high
25 0
mV
4.75
V
1
V/µs
sns_slew Outpu t slew rate
C l o a d = 5 0p F
Sns_band - 3dB Bandwidth
G uaranteed by design
20 0
sns _cmrr Com Commo mon n mode mode re rejec jectio tion n ratio ratio
f < 10 KHz KHz,, tes tested ted at DC onl only y CMRR=AV DIFF/AV DIFF/AV CM
70
dB
sns _svrr supply voltage rejection ratio VC V f < 10 K Hz, tested at D C only
60
dB
60
dB
4 00
kH z
ERROR SUMMING AMPLIFIER e rr _gain Voltage gain
n o l oa d
err _band U nity gain b andwidth
G uaranteed by design
err _slew Outpu t Slew Rate
C l oa d = 50 p F
4 1. 5
V /µ S
err _ibias Input bias c urrent
err _off
Input offset voltage
err _svrr
supply voltage rejection ratio
err _clamp Low output (cla mp) voltage low
- 10 f < 10 K Hz, tested at D C only Is ink = 1 mA, referred to Vref25
M Hz
0
1
µA
10
mV
60
dB T BD
V
7/46
L7250 ELECTRICAL CHARACTERISTCS (continued) POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol
±10%,
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified)
Parameter
err _clamp H igh output (clamp) voltage high
Test Condition
M in .
Is ource = 1mA, re ferred t o Vre f25
TBD
Typ.
M ax .
Unit V
VCM OUTPUT DRIVERS PWR_Gain
Power Po wer amp amplifi lifier er diff differen erential tial gain gain..
Io = ±1A, Rload = 8 Ω
Rds(on) Rds (on)
Total out output put ON resis resistanc tance e (Source + Sink)
@ 125°C, I=2A
PWR_Lkg
Outpu t leakage current
D iodeFw C lamp diode forward voltage
If = 2 A
THD
Total Harmo nic D istor tion To
ch aracterized n o tested
PWR_Slew
VCMN or VC MP slew rate
R L = 8 ohms
PWR_B and
Power Po wer Am Amp p -3 -3dB dB Ba Bandw ndwidt idth h
Drivin Dri ving g ERR ERROU OUT T = VD VDA ACRE CREF F, Guaranteed by design
Icross
Static Shoot-through c urrent
G uaranteed by design
14
15
0 .6
16
V/V
.9
Ω
60 0
uA
1 .2
V
1
%
1 25 0
V/us 5 00
kH z
0
mA
VCM CURRENT CONTROL LOOP STATIC STATIC AND DY DYNAMIC NAMIC CHARACTERISTICS CHARACTERISTICS I VCMo ff
Total offset current
DIVCMoff Total Total offset curren currentt drift temperature temperat ure coefficien coefficientt
R s=0.2
- 75
G uaranteed by design
G m_psrr Gm loop VS RR of VCV
-1
75
mA mA
.2
mA/ o C
1
mA/V
VCM LINEAR DAC DAC_res R esolution
15
DAC_out F ull Sc ale O utput Voltage
w r t VDACREF
0 .9 6
DAC_off
M id-Scale E rror
w r t VDACREF
- 12
DAC_DNL
Diffe Dif fere rent ntia iall No Non n li line near arit ity y
Guara Gua rant ntee eed d Mo Mono noto toni nici city ty
1
DAC_INL Integral Non Linearity
DAC_Co C onversion time nvT
9 0% from 3FFFh to 0020h
bi t 1. 04
V
12
mV mV
±1
LSB
±64
LSB
3
µs
VCM LOAD/UNL LOAD/UNLOAD OAD ADC ADC_res r esolution ADC_DNL
10
D ifferential N on Linearity
ADC_INL Integral No n Linearity
ADC_Co C onversion time nvT
8/46
40
bi t 1
LSB
3
LSB ADC Clock cycles
L7250 ELECTRICAL CHARACTERISTCS (continued) POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol
Parameter
±10%,
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified) Test Condition
M in .
Typ.
M ax .
Unit
ADC AUXILIARY INPUT AUX_ran Input range 0 ge0
R e g 0 6H ‘ b 3 ’ = 0 Referred to Vref25
±1
V
AUX_ran Input range 1 ge1
R e g 0 6H ‘ b 3 ’ = 1 Referred to Vref25
±2.25
V
AUX_Ibias
Inp u t b i a s
-100
10 0
µA
VCM VOLTAGE VOLTAGE AMPLIFIER Volt_gain Voltage gain
0 .1 65 - 15
V/V
Volt_off
Input offset
+15
mV
Volt _cmrr
Commo Com mon n mode mode re rejec jectio tion n ratio ratio
f < 10 KHz KHz,, tes tested ted at DC onl only y CMRR=AV DIFF/AV DIFF/AV CM
46
dB
Volt _svrr
supply voltage rejection ratio
f < 10 K Hz, tested at D C only
60
dB
BEMF proces processor sor amplif amplifier ier CalCoar seIn
C alcoarse voltage input range
Gain1
F irst stage gain
Gain2
Second stage gain
Offset Off set
Residual Resi dual inpu inputt offs offset et after calibration
Routt Rou
BEMF BE MF am amp p out output put res resis istan tance ce (pi (pin n 31)
0 .5 V control = 1 .25 V
Vcontrol = 1.25V (Measured between VCMN and SNS_P pins)
2
V
1. 9 1
V/V
16
V/V
-3
+3
mV
5 00
oh m
2. 5
V
2
µA
0. 2
V
ULOAD ULO AD @ POR Timer1_V T imer1 Charging Voltage
T imer1_I T imer1 Discharging Cu rrent Timer1_T T imer1 Low thr eshold
VOLTAGE VOLT AGE REGULATORS 1.8 AND 3.3 LINEAR REGULA REGULATOR TOR V18 feed 1.8V feedback Voltage
- 5%
1 .25
+ 5%
V
V33 OUT 3.3V O utput Voltage
- 5%
3. 3
+ 5%
V
9/46
L7250 ELECTRICAL CHARACTERISTCS (continued) POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol V18 IDRIVE V33 IDRIVE
Parameter
±10%,
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified) Test Condition
M in .
Typ.
Outpu t base current drive
M ax .
Unit
15
mA
NEGATIVE REGULATOR FREQ0
Osci llator fre quency
D efault c onfiguration
FREQ1
Oscil illa lattor freq eque uen ncy
TestRegi gis ster = ‘000 0001 010 001’ or = ‘00101001’
VoutH
H igh level ou tput voltage
VoutL
Low level o utput voltage
VNEerr OFFS
KHz
1
M Hz
TBD
Feedback in put offset
V
- 10
VNEGerr Feedback in put bias BIAS Vneg_err Com Commo mon n mode mode re rejec jectio tion n ratio ratio _cmrr
5 00
0
T BD
V
10
mV
1
µA
f < 10 KHz KHz,, tes tested ted at DC onl only y CMRR=AV DIFF/AV DIFF/AV CM
46
dB
Vneg_err supply voltage rejection ratio VC V f < 10 K Hz, tested at D C only _svrr
60
dB
SHOCK SENS SENSOR OR S kIgain0 Input OPAMP ga in0
R e g 02 H ‘ b 7’ = 0
10
V/V
S kIgain1 Input OPAMP ga in1
R e g 02 H ‘ b 7’ = 1
80
dB
SkIo ff
Input OPAMP off set
S kIinp ut
Input OPAMP in input impedance
SkFga in
F ilter OPAMP open loop gain
SkFband SkF band Filter OP OPAMP AMP unit unity y gain bandwidth S kFoff
- 15 R eg 0 2H ‘ b 7 ’ = 0
G uaranteed by design
F ilter OPAMP offs et voltage
+ 15
mV
10
Mohm
80
DB
5
M hz
- 10
+10
MV
SkOThH0 Output window compa comparator rator VthHigh
Referred to Vref25 ; Reg02H Reg02 H ‘b6’ = 0
2 00
mV
SkOThH1 Output window compa comparator rator VthHigh
Referred to Vref25 ; Reg02H Reg02 H ‘b6’ = 1
5 00
mV
SkOThL0 Output window compa comparator rator VthLow
Referred to Vref25; Reg02H Reg02 H ‘b6’ = 0
2 00
mV
SkOThL1 Output window compa comparator rator VthLow
Referred to Vref25; Reg02H Reg02 H ‘b6’ = 1
5 00
mV
10/46
L7250 ELECTRICAL CHARACTERISTCS (continued) POWER SUPPLY [VCC5 & VCV] VCC5 = 5V S ymb ol
±10%,
VCV = 12V ±10%. T amb = 25 °C (unless otherwise specified)
Parameter
Test Condition
M in .
Typ.
M ax .
Unit
SERIAL PORT
1
Voh
Logic Outpu t voltage high
Io h=1mA
Vol
Logic Outpu t voltage low
Io l = 1 m A
Vih
L o g i c i n pu t h i g h
Ii h = 1 u A
Vil
L o g i c i np u t l ow
Iil =-1uA
Ii h
Logi gic c hig igh h in inp put current
Int nte ernal Pul ullldo dow wn Res esiistor Vin = 3.3 3.3V V
I il
Logic low input curre nt
2. 7
V 0 .5
2 .2
V V
0 .5 33
V µA
-1. 00
µA
SERIAL POR ORT T
The serial port is a bidirectional three pin interface, using SDATA, SCLK and SEN to address and communicate with sixteen 8 bit regis registers ters in the L725 L7250. 0. Thes These e registers include include the s tatus register, register, Spindle Spindle c ontr ontrol ol registers, registers, VCM control registers, sinewave drive registers, and test mode register. These registers are cleared to zero at power up.
1.1 Defa Default ult comunication comunication modes modes setting setting (bit 7, Reg05 Reg05H H)= 0 After the SEN falling edge, the internal After internal stat state e m achin achine e is waiting for the first SCLK falling edge. This means that if the SCLK line starts from an high level the first falling edge, respecting the setup time Tefcf, is considered, and is used to read the R/W bit. During a writing process process the internal internal state machine must must see 16 SCLK falling falling edges to validate validate the operation operation.. The write mode is started started if the R/W bit is low on the first falling edge of SCLK. The read mode is started if the R/W bit is high on the first falling edge of SCLK. The ID, Address, and Data are all then subsequent subsequently ly read by the L7250 L7250 on the falling falling edges of SCLK. (See Figure Figure 1) The microcontroller has to read the data on the falling edge of the SCLK signal. After the hold time (Tedh) the data line switches to the next data without a tri-state phase.During a read mode the last address bit is read by L7250 on the eighth falling falling edge of SCLK. The internal internal state machine machine then turns the SDATA bit around for the L7250 to assume control control at the next SCLK rising edge (the first rising edge after the 8th SCLK falling edge). edge).
11/46
L7250 Figure 1. Defau Default lt serial port timing diagram diagram (bit 7, Reg05H Reg05H = 0) h e T
r e r c T
r e f c T
h d c T s d c T l c T h c T
c c T
f c f e T
N E S
0 D
0 D
1 D
1 D
2 D
2 D
3 D
3 D
4 D
4 D
5 D
5 D
6 D
6 D
7 D
7 D
0 A
0 A
1 A
1 A
2 A
2 A
2 A
2 A
2 D I
2 D I
2 D I
2 D I
2 D I
2 D I
W
K L C S
A T A D S
) e t i r w (
h d e T
y l d T
d d c T
l o r t n o c s u b s e k a t 0 5 2 7 L
R
A T A D S
) d a e r (
Note1: During writing proce Note1: process ss L7250 L7250 l atche atches s the data data on the SCLK falling falling edge edge (the ASIC is writing writing on the SCLK rising edge) Note2: During reading process L7250 takes the bus control on the next SCLK rising edge after the 8th SCLK falling edge The L7250 write the data on the SCLK falli falling ng edge respecting respecting the data hold time (Tedh (Tedh)) Note3: The ID number for the L7250 is ID1=ID2=ID3=1
12/46
L7250 1.2 Defa Default ult serial serial port timing timing Table Table Symb ol
Parameter
M in
M ax
Unit
T cc
Serial clock period
30
ns
Tch
Serial clock high time
13
ns
Tc l
Serial clock low time
13
ns
Tcds
Serial data s etup time t o clock falling edge (w rit e mode)
5
ns
Tcd h
Serial clock falling edge to se rial data hold time (wr ite m ode)
4
ns
Tedh
Serial clock falling edge to se rial data hold time (read mode)
5
ns
Tcd d
Serial data s etup time t o clock falling edge (re ad mode)
5
ns
Tel
Serial Enable low tim e
4 90
ns
Teh
Serial Enable high tim e
30
ns
Tefcf
Serial Enable falling edge to ser ial cl ock fa falling e dge
17
ns
Tcfer
Serial clock falling edge to Se rial enable rising edge
17
ns
Tdl y
SDATA tur n around delay time
0
ns
Note 1: All specifications specifications with respect respect to 50% of signal switching thresholds thresholds Note 2: Reading mode tested at Max 20Mhz
1.3 Inver Inverted ted clock comunicat comunication ion modes (bit (bit 7, Reg05H) Reg05H) = 1 To set the bit7, Reg05H to 1, entering this different comunication mode, a writing process using the default comunication protocol (see the above paragraph) must be used. After the SEN falling edge, the inter After internal nal state machine is waiting for the first SCLK SCLK rising edge. This means that if the SCLK line starts starts from a low leve levell the first rising edge, respecting respecting the setup time Tefcr, is c onsi onsidered dered,, and is used to read the R/W bit. The internal internal state machine machine must see 16 SCLK rising edges to validate validate the writ write e operation. The write mode is started if the R/W bit is low on the first rising edge of SCLK. The read mode is started start ed if the R/W bit is high high on the first rising rising edge of SCLK. The ID, ID, Address, Address, and Data are all then then subsequentsubsequently read by the L7250 on the rising edges of SCLK (See Figure 2). The microcontroller has to read (latch) the data on the falling edge of the SCLK signal. L7250 presents the data on the SCLK rising edge. During a read mode the last address bit is latched by the L7250 on the eighth rising edge of SCLK. The internal internal state machine then turns the SDATA bit around around for the L7250 L7250 to assume control control at the next SCLK falling edge (the first falling falling edge after the 8th SCLK rising edge).
13/46
L7250 Figure 2. Inverted Inverted cloc clock k seria seriall port timing diagram diagram (bit 7, Reg0 Reg05H 5H = 1)
h e T r e r c T
0 D
0 D
1 D
1 D
2 D
2 D
3 D
3 D
4 D
4 D
5 D
5 D
6 D
6 D l e T
l c T h c T c c T
r c f e T
N E S
7 D
7 D
h d c T s d c T
0 A
0 A
1 A
1 A
2 A
2 A
2 A
2 A
2 D I
2 D I
2 D I
2 D I
2 D I
2 D I
W
K L C S
A T A D S
h d e T
) e t i r w (
d l v T y l d T
l o r t n o c s u b s e k a t
0 5 2 7 L
R
A T A D S
) d a e r (
Note1: During writing process Note1: process L7250 latches latches the data on the SCLK rising rising edge (the (the ASIC is writing on the SCLK falling edge) Note2: During reading Note2: reading process L7250 takes the bus control on the next SCLK falling falling edge after the 8th SCLKrising edge The L7250 write the data data on the SCLK rising edge and it is expecting expecting the ASIC to latch latches es the data on the SCLK falling edge Note3: The ID number for the L7250 is ID1=ID2=ID3=1
14/46
L7250 1.4 Inver Inverted ted clock clock serial port timing timing Table Symb ol
Parameter
M in
M ax
Unit
T cc
Serial clock period
30
ns
Tch
Serial clock high time
13
ns
Tc l
Serial clock low time
13
ns
Tcds
Serial data s etup time t o clock falling edge (w rit e mode)
5
ns
Tcd h
Serial clock falling edge to se s e ria l data hold time (wr ite m ode)
4
ns
Tedh
Serial clock falling edge to se s e ria l data hold time (read mod e)
5
ns
Tvld Tvl d
Serial Ser ial clock clock risin rising g edge to SDATA sta stable ble tim time e (read (read mod mode) e) Cload=5pF (see Note2) Cload=5pF Cload=50pF (s ee Note2)
11 15
ns ns
Tel
Serial Enable low tim e
4 90
ns
Teh
Serial Enable high tim e
30
ns
Tefcr
Serial Enable falling edge to ser ial cl ock ri risi ng edge
17
ns
Tcre r
Serial clock ri sing e dge to Serial enable r ising edge
17
ns
Tdl y
SDATA tur n around delay time
0
ns
Note 1: All specifications specifications with respect respect to 50% of signal switching thresholds thresholds Note 2: In reading mode the clock f requenc requency y is limit ed by this parameter; in fact the min ‘serial clock high time’ is defined by (Tvld+Tasu) where Tasu = min ASIC setup time
15/46
L7250 Table 1. Regist R egister er Map mnemoni
addr
b7
b6
b5
b4
b3
b2
b1
b0
na me
00H 00 H
SPNC SP NCurr rrS Si gn
VCM VC McalOut O ut
ZCBa ZC Bad d
ThShutdown
ThWarn
rev2
rev1
rev0
SR
status
readonly
01H 01 H
RLvo RL volt lta age1 [1]
RLvoltage1 [0]
RLvoltage2 [1]
RLvoltage2 [0]
Rlti Rl tim mer[ r[2] 2]
Rlti Rl timer[ m er[1] 1]
Rlti Rl timer[ m er[0] 0]
NoBr No Bra ake
VCM VC M1
VCMRLr MRLreg eg
read re ad/w /wri rite te
02H 02 H
Sho Sh ock ckC Con onff
ShockT Shoc kTh[ h[0] 0]
RLToffBrake
RLToffBrake
Rlc Rl calib[3 i b[3]]
Rlca Rl cali lib[ b[2] 2]
Rlc Rl calib[1 i b[1]]
Rlc Rl calib[0 i b[0]]
VCM VC M2
VCMRL re reg g
read re ad/w /wri rite te
[1]
[0]
VCM VC MSta tate te1 1
VCMSt Stat ate0 e0
SPst SP sta ate te3 3
SPst SP sta ate te2 2
SPs SP sta tate te1 1
SPs SP sta tate te0 0
CTR1 CT R1
SP&VCMs Mstt
read/write
03H 03 H
Bemf Be mfOf OffC fCal al
VCMSt VCM Sta ate te2 2
c
attributes
ate 04H
SPslew2
SPslew1
SPslew0
Curdac2
Curdac1
Curdac0
PWMmask1 PWMm ask1
PWMmask PWMm ask0 0
CTR2
cont ro rol
read/write
05H
SPIprot
m3
m2
m1
m0
TSDen
VnegEn
Sken
CTR3
control
read/write
06H
w4
w3
w2
w1
w0
PREADC(1) PREA DC(1)
PREADC(0) PREA DC(0)
PREsmo
CTR4
control
read/write
07H
LoadCP
Advance
FFWEn
TO4
TO3
TO2
TO1
TO0
CTR5
control
read/write
08H
Kv7
Kv6
Kv5
Kv4
Kv3
Kv2
Kv1
Kv0
KVR
Kval
read/write
09H
GainSwitch
dac14
dac13
dac12
dac11
dac10
dac9
dac8
DAR1
DAC re reg 1
read/write re
0AH
dac7
dac6
dac5
dac4
dac3
dac2
dac1
dac0
DAR2
DAC reg 2
read/write
0BH 0B H
ADC_ AD C_D DATA (9)
ADC_DATA (8)
ADC_DATA (7)
ADC_DATA (6)
ADC_DATA (5)
ADC_DATA (4)
ADC_DATA (3)
ADC_DATA (2)
ADR
ADC re reg
readonly
0CH 0C H
ADC_ AD C_D DATA (1)
ADC_DATA (0)
ADC_RES _ADDR(1 R(1))
ADC_RES _ADDR(0) _ADDR( 0)
ADCRa AD CRange nge
ADC_CH_ ADC_C H_ ADDR(1)
ADC_CH_ ADDR(0)
ADC_START
ADR
ADC re reg
read/write
0DH
reserved
r es eserved
r es eserved
reserved re
r eserved re
reserved re
reserv ed re
reserved re
read/write
0EH
reserved
r es eserved
r es eserved
reserved re
r eserved re
reserved re
reserv ed re
reserved re
read/write
0FH
test7
test6
test5
test4
test3
test2
test1
16/46
test0
TEST
test
read/write
L7250 Table 2. Register map content description (continued) B it
S PI field name
C onten t
REGISTER SR, ADDRESS: 00H [2 : 0 ]
Rev[2:0]
R evision number of the device, set i nter nally
[3 ]
ThWarn
T hermal warning
[4 ]
ThShutdown
[5 ]
ZC bad
[6 ]
VCM calOut
[7 ]
S PN PNCurrSign
T hermal sh utdown Signals a p roblem wi th spindle s peed loop synch ronism VCM error output in ca libration mode Spindle current sign to implement adaptive t or orque optimizer control
REGISTER REGISTE R VCM1, ADDRESS: 01H [0 ]
NoBrake
0=VC M ac tive br brake ph ase e nabled 1= VCM active brake phase disabled
[3 : 1 ]
Rltimer[2:0]
[5:4]
Rlv lvo oltag age e2[1:0 :0]]
Selec ectts bet etwe wee en 4 valu lue es of un unlo loa ad voltag age e in Unlo loa ad2 ph phas ase: e: 00 = 1V 01 = 1.125V 10 = 1.250V 11 = 1.375V
[7:6]
Rlv lvo oltag age e1[1:0 :0]]
Selec ectts bet etwe wee en 4 valu lue es of un unlo loa ad voltag age e in Unlo loa ad1 ph phas ase: e: 00 = 0.375V 01 = 0.5V 10 = 0.625V 11 = 0.75V
000 = only Unload1 is enabled 001 = threshold set to 0.4V 010 = threshold set to 0.8V 011 = threshold set to 1.2V 100 = threshold set to 1.6V 101 = threshold set to 2V 110 = threshold set to 2.4V 111 = only Unload2 is enabled
REGISTER REGISTE R VCM2, ADDRESS: 02H [3 : 0 ]
Rlcalib[3:0]
0 11 1 = 29 . 4 % 0110 = 25.2% 0101 = 21% 0100 = 16.8% 0011 = 12.6% 0010 = 8.4% 0001 = 4.2% 0000 = 0% 1111 = -4.2% 1110 = -8.4% 1101 = -12.6% 1100 = -16. -16.8% 8% 1011 = -21% 1010 = -25.2% 1001 = -29.4% 1000 = -33. -33.6% 6%
17/46
L7250 Table 2. Register map content description (continued) B it
S PI field name
C onten t
[5:4]
RLTof offfBrake[1: 1:0 0]
[7 ]
SkockConf
Selects the Shock Sensor application 0 = piezo element 1 = charging element
[6 ]
SkockTh[0]
Selects the Shock Sensor threshold 0 = Vref +/- 200mV 200mV 1 = Vref +/- 500mV 500mV
Selec ectts the duratio ion n of Toff( ff(T Ton)ac n)acttive br brak ake e ph pha ase: 00 = 300usec 01 = 400usec 10 = 500usec 11 = 600usec
REGISTER REGISTE R CTR1, ADDRESS: 03H [3 : 0 ]
Spsta te[3:0]
[6 : 4 ]
V CMstate[2 :0]
[7 ]
Bemf OffCal
0000 = CL COAST 0001 = OLCOAST 0010 = OLSIX 0011 = OLSIN 0100 = OLBRAKE 0101 = INDSENSE 0110 = CLSIX 0111 = CLSIN 1000 = CLBRAKE Possible st ates for the VCM: 000 = Unload/Retract Unload/Retract 001 = tri-state 010 = brake 011 = enable current mode 100 = enable voltage mode 101 = offset calibration 110 = confirm the previous state 111 = confirm the previous state VCM BEMF processor offse t calibration
REGISTER REGISTE R CTR2, ADDRESS: 04H
18/46
[1 : 0 ]
P WM WMm as ask[1:0]
[4 : 2 ]
Currdac[2:0]
Selects the length of the mask over PWM ris in ing e dg dge: 00 = 2 us 01 = 4 us 10 = 6 us 11 = 8 us Selects the voltage threshold for the spindle c ur urrent limiter: 000 = 250mV 001 = 300mV 010 = 350mV 011 = 400mV 100 = 450mV 101 = 500mV 110 = 550mV 111 = 600mV
L7250 Table 2. Register map content description (continued) B it
S PI field name
[7 : 5 ]
Sp slew[2:0]
C onten t 0 0 0 = 1 0 V /u s 001 = 20 V/us 010 = 30 V/us 011 = 40 V/us 100 = 50 V/us 101 = 60 V/us 110 = 70 V/us 111 = 80 V/us
REGISTER REGISTE R CTR3, ADDRESS: 05H [0 ]
Sken
0 = sh ock sensor output n o latched 1 = shock sensor output latched (to clear the latched information a transition 1 -> 0 -> 1 is necessary)
[1 ]
Vnegen
0 = n egative regulator disabled 1 = negative regulator enabled
[2 ]
TSD en
0 = th erma l shutdown disabled 1 = thermal shutdown enabled
[6 : 3 ]
M[ 3: 3:0]
m asking while se nsing ZC, expressed in ter ms of half samples after window opening opening In terms of electrical degrees the single mask step is 3.75.
[7 ]
SP Iprot
0 = d efault p rotoc ol 1 = inverted SCLK protocol
REGISTER REGISTE R CTR4, ADDRESS: 06H [0 ]
PREsmo
[2 : 1 ]
PREA DC[1: 0]
[7 : 3 ]
W[4:0]
0 = spindle clock is i s system clock divided by tw t wo (F FW FWDADC cl c lock is system clock divided by 8) 1 = spindle clock is system clock clock (FFWDADC clock is system clock divided by 4) 00 = sleep mode 01 = ADC clock is system clock divide by 4 10 = ADC clock is system clock divide by 2 11 = ADC clock is system clock W in indowing wh ile s ensing ZC, expressed in ter m s o f half samp les before TO value In terms of electrical degrees the single window step is 3.75.
REGISTER REGISTE R CTR5, ADDRESS: 07H [4 : 0 ]
TO[4:0]
C oarse and fine sectio n of phase shift , applied for torque optimization. In terms of electrical degrees the Torque Optimizer single step is 0.937 electr electrical ical degrees.
[5 ]
FFWEn
0 = p ower su s upply com pensation for spindle d isabled 1 = power supply compensation compensation for spindle spindle enabled
[6 ]
A dvance
0->1 increments by o ne th e current s ample position
[7 ]
LoadCP
0->1 enables load of TO value as the cur rent sample position
REGISTER REGISTE R KVR, ADDRESS: 08H [7 : 0 ]
Kv[7:0]
KVAL factor for speed loop control
19/46
L7250 Table 2. Register map content description (continued) B it
S PI field name
C onten t
REGISTER REGISTE R DAR1, ADDRESS: 09H [6 : 0 ]
Dac[14:8]
[7 ]
GainSwitch
7 MS B for VCM dac 0 = g ain voltage of the VCM sense amplifier equal to 4 .5 .5 V/V 1 = gain volta voltage ge of the VCM sen sense se amplifier amplifier equal to 16 V/V
REGISTER REGISTE R DAR2, ADDRESS: 0AH [7 : 0 ]
D ac[7:0]
8 LSB for VC M dac
REGISTER REGISTE R ADR, ADDRESS: 0BH [7 : 0 ]
AD C_DATA[9:2]
8 MS B out put data from ADC co nversion
REGISTER REGISTE R ADR, ADDRESS: 0CH [0 ]
ADC START
[2:1]
ADC_ C_C CH_ADDR[1: 1:0 0]
[3 ]
ADC range
[5:4 [5 :4]]
ADC DC_R _RES ES_A _ADD DDR[ R[1: 1:0] 0]
0-> 1 star ts a new ADC conversion Cha Ch annel wh who ose con onv ver ers sion is requir ire ed 00 = VCM current sense amplifier output 01 = VCM voltage amplifier output 10 = VCM BEMF 11 = Auxiliary Channel (external pin) 0 = th e 4 s ignals enter directly (m aintaining the p roper dynamic range) the ADC block 1 = the 4 signals are scaled down to the ADC dynamic range Chan Ch anne nell wh whos ose e res esul ultt con onv ver ersi sion on is cu curr rren entl tly y pr pres esen entt in ADC_DATA
REGISTER REGISTE R ADR, ADDRESS: 0DH 0DH [7: 0]
r eserved
REGISTER REGISTE R ADR, ADDRESS: 0EH 0 E H [7 : 0 ]
r eserved
REGISTER REGISTE R ADR, ADDRESS: 0FH 0 F H [7 : 0 ]
20/46
Test[7:0]
Test re register
L7250 2
SPIN SP INDLE DLE MO MOTO TOR R CO CONTR NTROLL OLLER ER
Figure 3.
SUPPLY VOLTAGE COMPENSATION KVAL REGISTER
SMOOTHDRIVE RAW DUTYCYCLE
SMOOTHDRIVE ADC MODULATED DUTYCYCLE START-OF-COUNT
KVAL
VM
TIMEDOMAIN DUTYCYCLE SIGNALS
VM HGU
6 State or Sine Mode
SMOOTHDRIVE PROFILE MEMORY/ LOGIC
DIGI TAL MULTIPLIER
COUNTER & COMPARATORS
FET GATE DRIVE
MOTU
LGU
VM COARSE PHASE ADVANCE BITS
MEMORY ADDRESS COUNTER (N=48)
LOADCP BIT
HGV FET GATE DRIVE
WINDOW TRISTATE CMD
MOTV
LGV
FSCAN
VM
OLSIX/OLSIN OR CLSIX/CLS CLSIX/CLSIN IN ADVANCE BIT FINE PHASE ADVANCE BITS
HGW FET
FSCAN COUNTER
Tc
ZERO CROSSING PERIOD COUNTER 16+4 BIT
BEMF COMP.
WINDOW ZC
SPINDLE MOTOR
MOTW
GATE DRIVE
LGW
MASK xx
PWMMASK
CTAP
CURRENT LIMIT COMP.
SYSCLK 16.5MHZ
xx
MASK REGISTERS
SPSENH
CUR DAC
2.1 Spindl Spindle e Smoothdrive Smoothdrive Functiona Functionality lity L7250 utilizes ST’s propr proprietary ietary Smoothdriv Smoothdrive e commutat commutation ion algorithm. algorithm. Smoot Smoothdri hdrive ve is a volta voltage ge mode pseudopseudosinusoidal sinus oidal spind spindle le drive s chem cheme e where the duty c ycles of the three wind windings ings are modula modulated ted to form sinusoidal sinusoidal voltages volta ges across each winding. winding. The system determ determines ines the shape and amplitude amplitude of the drivi driving ng voltages in a completely digital manner.
2.2 SYS SYSCLK CLK The Smoothdrive system clock comes through the SYSCLK pin. The system expects either 33MHz or 16.5MHz on this pin, and needs needs 16.5MHz internally. A SYSCLK divide by two can be enabled by a SPI register bit PRESMO to accom accomodat odate e a 33MHz external external clock clock..
2.3 Smoot Smoothdrive hdrive Wave shape shape The basic Smooth drive wave shape is stored in digital memory. A voltage profile designed to reduce reduce switching losses and increase the voltage headroom headroom has been implemented. Essentially, two phases phases are PWM’ed, while the low side driver of the third third phase is on at 100% duty cycle. cycle. The PWM duty cycles are modula modulated ted in such a way as to resul resultt in sinus sinusoida oidall currents on all 3 m otor phases. phases. Driving in this manner, manner, as oppo opposed sed to driving driving true sinusoids on all three phases, phases, results r esults in improved headroom and efficiency, efficiency, approaching that of conventional 6 state commutation. The system system is phase locked to the motor motor by sensing sensing one one BEMF zero zero crossing crossing on one one windi winding, ng, once once per electr electrical ical 21/46
L7250 cycle. A window window is opened opened up in that winding, winding, and it is tri-stated tri-stated to allow sensing sensing of the zero crossing crossing.. The width of the window opening opening is programmab programmable, le, and can be made very small in steady state. A frequency frequency locked loop keeps the wave shape in sync with the motor speed. speed. The system is entirely digital, digital, requiring no external external components. The Smoothdrive Smoothdrive wave shape is sync with the motor. It divides the electrical electrical period, from one zero crossing crossing to the next, into 48 evenly evenly spaced sample sample periods. periods. For each sample sample period, period, the driving duty duty cycle is defined defined for each motor phase by a table in the Smoothdrive logic. The Memory Address Counter sequences the samples through throu gh the cycle, and is clocked N time times s per cycle. The following following describes describes how the frequency frequency locked loop system works: There are N sine wave samples samples per electrical electrical rev. N=48 for this design. design. Each electrical electrical period (from one ZC to the next) is measured by a time timerr w ith an effec effective tive frequency frequency of F sysclk/ 48, resulting resulting in a measu measured red zero crossing period period Tc. The timer does not actually actually run at Fsysclk/48 Fsysclk/48 - the reso reso-lution is more like Fsysclk/3. The FSCAN Count Counter er is a down counte counterr preloaded preloaded with Tc, and runni running ng at Fsysclk. The FSCAN FSCAN Counter puts puts out a pulse each time it hits zero, then it resets to Tc and counts counts down again. again. This cycle cycle occurs N (48) times per electrical electrical cycle. cycle. Thus, the FSCAN Count Counter er divides the electrical electrical cycle into N evenly evenly spaced samples based based on the previous Tc. The pulse signal out of this block, that occurs occurs 48 time times s per electrical electrical period, is called FSCAN. The Memory Address Counter counts FSCAN pulses, and tells the Profile Logic which full scale duty cycle values to use for each Smoothdrive sample period.
2.4 PWM rat rate e The PWM rate is unrelated to the Smoothdrive sample rate. The minimum PWM rate is 32.2kHz with 16.5MHz spindle spind le system clock, define defined d by (Fsys/512). (Fsys/512). The spin system system clock is SYSCL SYSCLK K or SYSCLK/2, SYSCLK/2, chosen via serial port (SYSCLK/2 (SYSCLK/2 is the default default at power up). 9 bits of resolutio resolution n define the duty cycle cycle at each sample period. period. The PWM counter is reset at the beginning of each electrical cycle (at the ZC). The PWM duty cycle is defined for each of the two chopping phases by comparing the appropriate duty cycle values value s to the counter. The duty cycle values are the result of multiplying multiplying values in the Smoothdrive Smoothdrive waveform table by the amplitude value KVAL coming from SPI.
2.5 Suppl Supply y Voltage Compensa Compensation tion via ADC The Smoothdrive Smoothdrive system is a volt voltage age mode drive scheme. scheme. Without compensatio compensation, n, the spindle drive amplit amplitude ude would be a proportion proportion of the motor supply voltage. L7250 implements implements a supply voltage compensation compensation scheme whereby the drive amplitude is indipendent on motor supply voltage. An inter internal nal 6 bit ADC read reads s the m otor supply voltage voltage variation variation (+/-10%), and the applied duty cycle is modifi modified ed to keep the applied applied voltag voltage e constant. constant. A side effect is that the PWM frequency will will be chang changed ed as well as the duty cycle. The ADC runs on a 4MHz clock derived from the SYSCLK (it is divided by 8 if the PRESMO bit is set to zero else it is divided divided by 4). The conversion conversion results results affects affects the PWM count counter er once per PWM cycle, nominally nominally 32 kHz.
2.6 BEMF comparat comparator or Hystere Hysteresis sis Since only one polarity ZC is detected, the BEMF comparator hysteresis no longer needs to contribute a time offset. offse t. The hyster hysteresis esis is zero on the signi significa ficant nt edge, and is engag engaged ed on the other edge. Thus, larger values of hysteresis can be used to provide noise immunity at low speed while coasting, without affecting ZC timing. Hysteresis of 50mV provides adeguate Hysteresis adeguate sensiti sensitivity vity for detecting detecting motion startup, startup, while improvin improving g noise immunity when the motor is moving very slow or is stationary stationary..
2.7 Sta Startup rtup Algorithm Algorithm Descript Description ion L7250’s spindle motor startup is controlled by firmware, and consists of four distinct phases: Inductive Position
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L7250 Sense, to determine rotor position, Open Loop Commutation, which accelerates the motor to build up BEMF, Synchronization , to measure motor speed and position, initializing the Smoothdrive Smoothdrive system, and Closed Loop Smoothdrive Commutation, the normal synchronous commutation mode to accelerate and run at speed.
2.7.1 Induct Inductive ive Position Position Sense Sense Inductive position sensing is achie Inductive achieved ved through a firm firmware ware r outi outine ne that measures the curr current ent rise time in each of the six possible states (six steps profile), and uses this information to determine the rotor position. The six steps profile still comes from the Profile Memory that contains 48 samples, but in this case there are only six different configuratio configuration, n, each of them repea repeated ted eight times; the linear scansion scansion of the memory one sample at a time gives a new six step configuratio configuration n every eight increments. increments. Before any operat Before operation ion can be done, the firmware routi routine ne must set the the KVAL value value present present in SPI to the maximum maximum value (*1) , to saturate the PWM signals given to the motor, and put the Memory Address Counter in a known position (*3); this is done keeping the motor in OLCOAST (*2) state and asserting a LoadCP command (*4) to load the content of the torque optimizer optimizer related SPI register into the Memory Address Counter. Counter. At this point, the present six steps configuration can be energized through the INDSENSE state (*5) , waiting for the curren currentt to reach the thresh threshold old programm programmable able via SPI (*6); the curre current nt limiting limiting comparat comparator or will be be trigger triggered ed by this condition, condition, and it’s output output will be visible at ZC pad. The current rise time will be measured measured and stored from the ASIC (*7) . The device automatically limits the PWM signals for the three phases to limit the current, but the currents in the windings windi ngs m ust be recirc recirculate ulated d from firmware firmware putti putting ng the motor in OLCOA OLCOAST ST (*8) state. A burst of eight ADVANCE signals signals (*9) must be asserted from SPI to reach the the next configurat configuration ion in the profile memory, then the procedure can be repeated. repeated. Each winding can c an be excited excited more than one time, to average average the measurements, and at the end of the sensing sequence the ASIC decides the rotor position.
Figure 4. Inductive Sense Routine START InductiveSense Routine Nadv=0, Nadv =0, Nph= Nph=0 0
(*2)
NO
Set OLCOAST WriteReg.03H Spstate[3:0] = 0001
Nph = 48
Comparethe Six Measured Rise Time Time to definethe ROTOR POSITION
YES
EXIT InductiveSense Routine
Nadv=0
YES (*1)
Set KVAL WriteReg.08H Kv[7:0] = 11111111
(*3)
Set Torque Torque Optim Optimizer izer WriteReg.07H TO[4:0] TO[4 :0] = 0000 00000 0
(*4)
Nadv=8
NO
IncNadv Inc Nph
SetADVANCE Write Reg.07H Advance= Adva nce= 1
Set Load Coarse Phase WriteReg.07H LoadCP= Load CP= 1
(*9)
Waitt for Wai CurrentDecay (*5)
Set INDUCTIVESENSE INDUCTIVESENSE WriteReg.03H Spstate[3:0] = 0101
Set OLCOAST WriteReg.03H Spstate[3:0] = 0001
(*8)
Store the measured CurrentRise Time & Nph associated
(*7)
(*6)
ZC=0
Measure Current Rise Time By rea readin ding g the ZC (pin 22)
ZC=1
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L7250 2.7.2 Open Loop Loop Commutation Commutation After position sense is complete, the microcontroller commutates the motor following a constant acceleration profile until sufficient BEMF is developed to reliably measure it. The starting position position of the open loop commutati commutation, on, determ determined ined by the position position sense routine, is set up by first initializi initi alizing ng the Memory Address Address Count Counter er usin using g LOAD LOADCP CP (*1), then clocking ADVANCE (*2) the app appropri ropriate ate number numb er of times (8 pulse pulses s per 6 state state positi position). on). The spindle spindle state will be OLCOA OLCOAST ST while setti setting ng the initial state state.. Then,, drivers are enabled Then enabled in either OL_SIX OL_SIX or OL_SIN OL_SIN modes (*3) , depe depending nding on whether whether 6 state or sine mode open loop commutation commutation is desired. Once the motor is accelerated accelerated up to an appropri appropriate ate speed (*4) (*4) , the motor is tri-s tri-stated tated by transitioning transitioning to the OLCOAST (*5) and then CLCOAS CLCOAST T state states, s, as described below, to synch synchroronize the Smoothdrive system to the motor.
Figure 5. Ope Open n Loop Commutation Commutation START Open Loop Commutation Commutation Nadv=0 Nad v=0 , i=0
Note1: Spstate[3:0] condition has been be en set set in OL OLCO COAS AST T by the Inductive Inductive Sens Sense e Routine (*1)
(*2)
EXIT Open Loop Commutation
Set Load Coars Coarse e Phase Phase Write Reg.07H LoadCP = 1
(*5)
Set ADVANCE Write Reg.07H Advance = 1
Set OLCOAST Write Reg.03H Spstate[3:0]=0001
(*4) i = RAMP_Steps Inc Nadv
Note2 Not e2:: Nalig Nalign n is received received from the Inductive Sense routine Indicating Indicati ng the rotor position alignement
(*3)
Inc i
Nadv=Nalign Wait the End of RAMP_DELAY[ i ]
Accelerate in Sine or Six
SIX
SINE
Set Ope Open n Loop Loop SIX Write Reg.03H Spstate[3:0] =0010
Set Open Loop Loop SINE SINE Write Reg.03H Spstate[3:0] =0011
Set ADVANCE Write Reg.07H Advance = 1
2.7.3 Sync Synchroniza hronization tion to Smoothd Smoothdrive rive Commutation Commutation When the open loop commutat commutation ion is complete, the drivers drivers are put in OLCO OLCOAST AST mode, and after a delay for setting the Bemf sampling period, CLCOAST is asserted, so that a ZC Period (Tc, the time between two BEMF zero crossings) can be detected and measured. The BEMF sampling sampling period is set in OLCOAST OLCOAST (*1) and after a delay delay (30 usec ) a Load CP (*2) is asserted. asserted. Afterr a delay of time Tc0 (300usec Afte (300usec suggested) suggested) anothe anotherr Load CP is asserted asserted (*3); this initializes initializes the electrical electrical period perio d for BEMF sampling. sampling. Once pregrammed pregrammed the transition transition to CLCOAST (*4) , the BEMF is sampled at the rate of Tc0 to look for two consecutive LOW readings (in anticipation of the LOW->HI zero crossing transition (*5) ). Afterr the first ZC rising edge, the BEMF sampling period is refreshed Afte refreshed to Tc0 value value.. If two c onse onsecuti cutive ve ZC edges are detected detected (*6), then after the last rising edge the Smoothdr Smoothdrive ive commu commutatio tation n is synchroniz synch ronized ed with the motor rotor position position and it i s ready to be prog programm rammed ed in closed loop commutatio commutation n . At least two ZCs must be observed observed befor before e transitioning transitioning to closed loop spinup (CLSIX or CLSIN) (*7a or *7b) . This ensures that the Smoothdrive circuitry is synchronized to the spindle motor.
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L7250 Figure 6. Synchronization to Smooth Drive Commutation
START Sync. To SmoothDrive SmoothDrive Commutation i=0
ZC_SamplingRoutine BEGIN
(*1)
Set OLCOAST Write Reg.03H Spstate[3:0]=0001 Spstate[3:0]=0001 CALL ZC_SamplingTime Routine ne
Wait Loop (30 usec)
(*2)
EXIT Sync. To Smoo Smooth th Drive Commutation
(*7a)
Set Closed Loop SIX SIX Write Reg.03H Spstate[3:0] =0110
Set Load Coarse Coarse Phase Write Reg.07H LoadCP = 1
SIX
(*7b)
Set Closed Loop SINE SINE Write Reg.03H Spstate[3:0]=0111
Motor Running in Sine or Six
SINE
Reset Time Out Wait Loop (300 usec)
NO (*3)
Set Load Coarse Coarse Phase Write Reg.07H LoadCP = 1
TimeOut Control
(*5) NO
YES (*4)
Set CLCOAST Write Reg.03H Spstate[3:0]=0000
YES (*6) i= 2
ZC_SamplingRoutine END
CALL ZC_SamplingTime Routine
Wait RisingEdge of ZC (pin 22)
START U P START FAILURE Exit
NO
Inc i
Reset Time Out
YES
2.7.4 Close Closed d Loop Commutatio Commutation n During closed loop commutation, the motor is driven following the smooth driver wave shape (or the traditional six step profile) profile).. To keep sync, each electrical electrical cycle a winding of the spind spindle le motor (phase U) is tri-sta tri-stated, ted, for a programmabl progr ammable e (via SPI) window (W), to sens sense e for the ZC occurrence; occurrence; to mask the c urren urrentt flyba flyback ck time a masking time is applied starting from the opened window for a certain number M of samples (settable via SPI). Due to the fact that the motor motor winding is driven in voltage voltage mode a contro controll of the phase shift between between the applied applied voltage and the Bemf is required in order to optimize the system efficiency (the loss in efficiency is related to the cosine of the angle between Bemf and current). Via the SPI it is possible to set an appropriate Torque Optimizer (TO) value based on the application characteristics (Rm, Lm, Speed). When a ZC is detec detected ted the circuit circuit starts starts scanni scanning ng the store stored d smooth drive wave shape shape (or the tradition traditional al six step profile) from the number of sample pointed by the TO register; the tri-stated window is opened a certain number of samples before. In the following following table the relation between between the TO regis register ter cont contents ents and the window and masking time position and duration: start
sto p
window
TO-W
At ZC detection
m ask
TO-W
TO-W+M
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L7250 2.8 Spindl Spindle e PWM Curren Currentt Limiting Limiting Peak motor current is limited with a fixed frequency PWM scheme that works in conjunction with the Smoothdrive PWM rate. When the current limit threshold is reached the motor is put in brake condition, and it is reenabled enabl ed at the begin beginning ning of the next PWM c ycle if the curren currentt limiting condition condition is false. false. Spindle current is sensed via an external resistor connected from the low side driver sources to ground. This sense voltage is compared to an internal internal programmable voltage reference (Reg04H Currdac[2:0]). There is a built in digital filter, generating a SYSCLK derived delay (20 * SYSCLK period) from the over current event.. This delay appears event appears on both edges of the current limiting limiting comparator. comparator.
2.9 Slew Rate Contr Control ol Closed loop Voltag Voltage e Slew rate control control is provided on both edges edges for the high and low side driver drivers. s. The slew rate value can be set with three bits in in the serial serial port (Reg04H (Reg04H Spslew Spslew[2:0] [2:0]). ). Slew rates up to 80V/us 80V/us and down to 10V/us 10V/u s will be controllable controllable..
2.10 Synchronous rectification The appropr appropriate iate low-side driver driver is enabled enabled during the off-ti off-time me phase to condu conduct ct recirculation recirculation current current with a lower voltage drop than the low side driver body diode, reducing power losses. Crossover current protection is provided to prevent shoot-through currents.
2.11 Open loop and closed loop loop brake Spindle Spind le brakin braking g may be done while keep keeping ing the Smoothdrive Smoothdrive syst system em in sync with the m otor, or not. Closed Loop Braking Braking means means ZC’s are still being being detected detected in the same way as when norma normally lly comm commutati utating. ng. So, all 3 motor phases phases are driven low, but when the windo window w is norma normally lly opened opened to look for a ZC, MOTU is tri-stated. tri-stated. When the ZC occurs, MOTU is driven driven low as the other other motor phases, until the next next windo window w comes up. A motionless motor will wait for a ZC, keeping MOTU tri-stated and the other two phases low. Open loop braking means that that all 3 motor phases phases are driven driven low, and ZC’s are not detected. detected. Brakin Braking g caused by a power power fault is is always open loop braking. CBRK provides control voltage for brake circuitry after power fails. An external cap on this pin is charged to 5V, so that the cap stays charged after a power failure.
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L7250 3
VOICE VO ICE COI COIL L MO MOTO TOR R DRI DRIVER VER
The VCM driver is configured configured as a transc transcondu onductan ctance ce amp, with an n-cha n-channel nnel DMOS H -brid -bridge ge power output, output, currentt sense amp, error amp, and 15 bit linear DAC for comman curren command d input. The power stage is a clas class s AB volta voltage ge amp. The error amp closes the transconductance loop around the power amp, using feedback from the current sense sens e amp. The VCM block is shown below.
Figure 7. VCM Driver Block Diagram VCV 1/2/54/55 POR S1
Rc Cc
VM
VM/2
39
52/53
ErrorAmp
DACREF 38
VCMN 45/46
DACREF Gpow 43/44
Tristate
Rm
VM
VM/2
Rs
VCM GND
Lm S2
VCMP 3/4
DACREF
Ri 37
DAC 15
DACREF AGND
VCM GND
Gpow
5/6
SenseAmp
Rf 40
Gs
DACREF
42 41
Tristate
The current flowing into the voice coil is equa equall to: Rƒ 1 Icoil = – ------ ⋅ ----------------- ⋅ Vin Ri Rs ⋅ G s Where Gs is the sensing opamp gain (programmable via serial port Ω and Gs = 4.5V/V Considering Consideri ng a typica typicall applicati application on where Rf = 5.6k, Ri = 2.5k, Rs = 0.25 0.25Ω 4.5V/V we obta obtain in a maxim maximum um currentt equal to about 2A for 1V DAC output (Vin). The sense amplifier input range is abou curren aboutt 0.55 0.55V. V. The power stages assure this current requirement and they have a differential gain of 16. The loop is compensat compensated ed throu through gh the RC network network Rc and Cc that canc cancels els out the motor pole Lm/Rm. This graphic shows the theoretic Gloop Bode diagram and put in evidence the second pole of the loop that is strictly related to the error amplifier bandwidth.
Figure 8. Gloop A 0 ⋅ 2G po w ⋅ R s ⋅ Gs Ri ------------------------------------------------- ⋅ ----------------Rs + R m R i + R f
Ri A 0 ⋅ ----------------R i + R f
G loop
2 G po w ⋅ Rs ⋅ G s 1 -------------------------------------- ⋅ ---------------Rs + R m R f ⋅ Cc Fdt error closed loop
Rc -----Rf
Ri ωt ⋅ ----------------R i + Rf 1 ----------------Rc ⋅ C c
1 ---------------R f ⋅ C c
R f ⋅ R i -- ω t ⋅ --------------------------------Rc ⋅ ( R f + Ri )
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L7250 Considering a typica Considering typicall application with Rs = 0.25Ω, Lm = 0.75mH, Rm = 7.5Ω, Gs = 4. 4.5 5 Gpow = 8, Rf = 5.6K, Cc= 3.3nF,, Rc = 33k we will obtain 3.3nF obtain a bandwidth bandwidth about 20kHz. 20kHz. To increase increase the bandwidth bandwidth a different different values values of the external external component com ponents s c oul ould d be c alc alculated ulated follo followin wing g the above relation relation and taking taking in account the limitation limitation introd introduce uced d by the second pole due to the error amplifier bandwidth (ωt). This one has a typical value about about 4MHz.
3.1 VCM Operating Operating Modes Modes and and Control Control At power-on-reset power-on-reset the VCM r egis egister ter is clear cleared ed and the VCM is in Unload/Retract Unload/Retract m ode. Via serial port is possible to command the following modes: Unload/Retract, Tri-state (disable), Brake, Enable Current Mode, Enable Voltage Mode, Offset Calibration
3.2 VCM Power Power Driver Driver H-Bridg H-Bridge e The VCM driver is capable of high performance performance linear, linear, clas class-AB, s-AB, H -brid -bridge ge operation operation w ith all power devic devices es internal. terna l. The powe powerr amp stage is configured configured as a voltag voltage e amp with gain of 16. The H-bridge H-bridge consists of 4 N-ch N-chanannel DMOS power transistors. transistors. Powe Powerr is suppl supplied ied to the H-bridge through through the i ntern nternal al ISO-FET ISO-FET ( at pins VM 52,53), 52,53 ), and ground returned returned via four VCMGND pins (5,6,43,44). (5,6,43,44). Booste Boosted d gate drive for the high side drivers is provided provi ded by the charge pump circuitry, circuitry, with the boosted boosted volta voltage ge at the VCP pin.
3.3 VCM Current Current Command Command 15 bit DAC The VCM current command command is defined defined by an internal internal linear, 2’s complemen complement, t, 15 bit DAC. The mid scale referreference for the DAC, VREF25, is defined by an on-chip reference reference at 2.5V. VREF2 VREF25 5 is the referenc reference e for the sense amp and error amp in the VCM loop. Level shifting shifting from VREF25 to VM/2 will be done in the power stage. 0x3FFF Max current flowing 0x3FFF flowing from VCMN to VCMP (current mode operatio operation) n) 0x---0x0001 0x000 0x0 000 0 zero current current 0xFFFF 0x---0x4000 0x400 0 Max current flowing flowing from from VCMP to VCMN (current (current mode operati operation) on) To write the 15 bit DAC the two register REG09H [14:8] and REG0AH [7:0] have to be referred. At any time the MSB register is entered, to apply the modification also the LSB register must be write. Instead writing only the LSB register its conten contentt w ill be im media mediatly tly visible on the DAC stru structure cture.. Then a double write sequence sequence its necessary necessary if the [14:8] bit have to be modif modified ied while it is possible possible to move the DAC in a fine way (wri (write te of the [7:0] bit) with only one write sequen sequence. ce.
3.4 VCM Curre Current nt Sen Sense se Amp VCM current is sense sensed d by a diff amp that amplifies amplifies and level shifts the voltage drop across an external resistor in series with the VCM coil. The sense amp has a nominal differential voltage gain programmable through the serial port bit Reg09H bit 7, and the output, VSENSE, is relative to VREF25 (pin 21). The amp has been design to have high common mode rejection (over 70dB at DC), Power supply rejection over 60dB, and as low an input offset as possible.
3.5 VCM Current Current Loop Loop Error Amplifie Amplifierr The VCM error amp gain gains s up the difference difference betw between een the curren currentt comm command and voltage DAC_OUT and the current sense voltage VSENSE. VCM current loop compensation is implemented externally with an RC network connected necte d acro across ss ERR_ ERR_IN IN and ERR_OUT ERR_OUT.. The erro errorr amp outpu outputt is referred to VREF25.
3.6 Error Amp Output Clamp The error amp output swing is clamped in both directions (Vref25+/-3Vbe) to prevent wind-up of the integrating compensation components around the error amp in the event of saturation.
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L7250 3.6.1 Volta Voltage ge Mode Mode In Voltage Mode, the VCM power outputs will apply a voltage to the VCM motor commanded by the VCM DAC. This is impl impleme emente nted d by tri tristat stating ing the sen sense se amp and error amp out outpu puts, ts, and connecti connecting ng DAC_ DAC_OUT OUT to ERR_OUT with an internal switch (switch S2). Skipping the err_out amplifier the DAC command will enter the powerr section without any inversion, powe inversion, then the DAC codificatio codification n must be considered considered in oppo opposite site direction direction respect respect to the curren currentt mode operation. operation.
3.7 VCM Loop Offse Offsett Calibration Calibration Mode Mode The VCM Loop Calibration mode can be implemented following two different approach:
1) The VCM loop is enabled enabled (sense ( sense amp, error amp, DAC), DAC), but the VCM power stage is is tri-stated. Thus, the sense amp is guaranteed to be monitoring a zero current condition. To imp implem lement ent off offset set calibrati calibration, on, the current current comma command nd is swept through through zero by the controlle controllerr ASI ASIC. C. Since the Gm loop is open, the error amp output will be saturated saturated in one direct direction ion or the other depending depending on the current command (to configurate the error opamp as a comparator the external compensation network netw ork will be disc disconne onnecte cted d open openin ing g the switch switch S1) S1).. As the command command sweeps sweeps throu through gh the zero cur current rent command point, the error amp output will swing to the other extreme. The comparator senses the output swing of the error amp, and through the serial port (Reg. 00H -> b6) interrupts the ASIC. The appropriate propria te DAC value correspo corresponding nding to the trip point interrupt interrupt is the loop zero current offset. offset. Figure 9. VCM Curre Current nt Loop Offse Offsett Calibration 1 START VCM Current Loop Offset Calibration Routine
Set VCM Offset Calibra Calibration tion Write Reg.03H VCMState[2:0] = 101
DAC_VAL = 0 Flag1 Fla g1 = 0 , Flag2 = 0
Set SenseA SenseAmpl.Ga mpl.Gain in Write Reg.09H GainSW bit = 0
* DAC_VAL is in 2 complement complement forma formatt
Select Sense Amplifier Gain
4.5 V /V
Set SenseAmpl.Gain Write Reg.09H GainSW bit = 1
16 V/V
Flag1 Fla g1 = 1
UPDATE 15 Bit DAC Write Reg.09H dac[14:0]= DAC_VAL
Flag2 = 1
DAC_VAL = DAC_VAL +1
Read Error Ampl Output Read Reg.00H VCMcalOut bit value
DAC_VAL DAC_ VAL = DAC_VAL -1
NO Flag2 =1
NO NO
VCMcalOut = 0
YES
YE S
Flag1 = 1 YES
Store the DAC_VAL as the zero loop offset
EXIT VCM Current Loop Offset Calibration Routine
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L7250 2) A second approach is considering to have the VCM in stop position; to enable it in current mode configuration driving current in the right direction in order to be sure to mantain the stop position; to decrement the 15bit DAC value to reach the zero current condition using the 10bit ADC to measure the current value. In the following diagram a detailed flow chart is presented. Figure 10. VCM Current Loop Offset Calibration 2
START CurrentMode “ZeroIout Iout”” Calibration Routine
No
Iout
Yes
Polaritycheck ADC_DATA[9]= 0
Flag_A=0 DACvalue=1200( 0x4B0) Note1
Yes Flag_A=0
EXITwith Error Error 1 Calibrationnot performe Calibrationnot performed d Positiveoffset to big
No Flag_A=1 StoreDACvalue As referenc reference e for ZEROIout
Set VCMinTristate Write Reg.03 Reg.03H H VCMState[2:0]] = 001 VCMState[2:0
EXIT CurrentMode “ZeroIout” Calibration Routine
DACv alue-=1
Call IoutDigitalVal Routine Iout_Offset Iout _Offset = ADC_DATA[9: ADC_DATA[9:0] 0] Note2
Set 15BitDA 15BitDACto Cto haveVCM Curr Current ent withno motion WriteReg.09H& Reg.0 Reg.0Ah Ah Dac[14:0]= DACvalue SettheGainSwto Highor Low
Yes DA Cvalue<-1200
EXITwith Error Error 2 Calibrationnot performed Calibrationnot Negativeoffsetto Nega tiveoffsetto big
START IoutDigitalVal Routine
No START10Bit ADC Con START10Bit Conversi version on of the IoutChannel WriteReg.0CH ADC_CH_ADDR[1:0]=00 ADC_START=1 ADC_DATA[9:0] -= Iout_offset ( Subtractthe offset )
Set VCMin En.Current En.Current Mode Write Reg.03 Reg.03H H VCMState VCMStat e [2:0] = 011
Wait 20m 20msec sec Update Upda te the 15BitDA 15BitDAC C WriteReg.09H& Reg.0 Reg.0Ah Ah Dac[14:0] =DACvalue
Call IoutDigitalVal Routine
Read10Bit ADC ReadReg.0BH ADC_DATA[9:2] ReadReg.0CH ADC_DATA[1:0]
EXIT IoutDigitalVal Routine
Note 1 : once the VCM will be enabled enabled in curren currentt mode with the DAC value at 1200 the current will will keep the motor against the crash stop position position Note 2 : with the VCM VCM in tristate, tristate, the result of the digital digital conversion conversion of the Iout Channel has has to be used used as ZERO curren currentt offset value
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Wait Endof Conversion
YES
NO
L7250 3.8 VCM Ramp Load / Unload Unload Syst System em Figure 11.
VCM Predriver
+A
Rs VCMN
VCMP VCM
Offset calibration
-A
Gain Calibration Procedure _
VGA
_
+
5 MSB from ADC CalCoarse
29 Vcontrol
Fine calibration bit from Serial Port
Bemf
+
_
Voltage
+
ADC 10 bit
to Serial Port
+
_
Current
(Sense Ampl)
Sel&start
The Ramp Load system is designed to allow a microcontrolled assisted constant velocity for ramp loading and unloading. VCM Current-Voltage-Bemf monitor circuitry is integrated for the loading or unloading operation. VCM CurrentVoltage-Be Volta ge-Bemf mf are converted converted in digita digitall by a 10 bit AD conve converter rter and can be read through the serial port.
3.8.1 Load Load/Unload /Unload operation operation at power power good When both the 12V and 5V are present, the Load/Unload operation can be assisted by the microcontroller. The power stage can be driven in both current and voltage mode and the velocity of the Load/Unload operation is controlled by reading the internal registers that give information regarding the VCM current, voltage and the Bemf generated by the VCM motion. The VCM current measurements is done by sending to the AD converter the output of the VCM Current Sense Ampl. The VCM voltage is measured by connecting an operational amplifier, with a scaling factor, to the VCMP and VCMN of the power stage. The VCM Bemf dete detection ction is done using a first amplifie amplifier, r, havin having g a contr controlled olled gain, gain, follow followed ed by a second second opera opera-tional amplifier implementing the transfer function necessary to BEMF reconstruction. The programmable gain of the first operationa operationall amplif amplifier ier it is neces necessar sary y to consi consider der various coil resistance resistance values related to diffe different rent application. The BEMF information is carry out on pin VCMBEMF (31) for filtering pourpose (the output impedance is typically set to 500ohm). The conversion in digital of these parameters is used by the microcontroller as a feedback to close the velocity control loop during the ramp loading or unloading operation, and to perform calibrations. All these signals can enter directly the ADC block (ADCrange bit = 0) or can be scaled to adjust the dynamic range to the ADC one (ADCRange bit = 1). The scaling factor is set equa equall to 2.25 for the ‘Curr ‘Current’, ent’, ‘Voltage’, ‘Voltage’, ‘Auxi ‘Auxiliary’ liary’ input channels, channels, while is set to 1.25 for the ‘Bem ‘Bemf’ f’ input channel channel..
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L7250 3.8.2 Gain Calibration Calibration Proced Procedure ure The Bemf detector circuitry must be calibrated right before the beginning of any Load/Unload operation. Because the coil resistance Because resistance can vary up to 30% due to ther thermal mal effects, effects, it is neces necessa sary ry to calibr calibrate ate the gain of the first stage depending on the ratio between the operating coil resistance value and the sense resistance value. The output of t he Bemf detector detector circuir circuiry y is: Bemf = OutP - OutM - Rs*Ivcm ( 1+ Rm/Rs) where: Rm = motor resistance where: resistance Rs = sensing resistance If the Gain of the first stage is matching the ratio between the coil resistance at operating temperature and the sense sens e resist resistor, or, the Bemf measured is right the value generated generated by the VCM motion. The gain trimming is done w ith the VCM in a stop position position (no Bemf must be generated) generated) with a certain amount amount of current flowing into the coil; in this condition the gain must be adjusted in order to have zero voltage from the Bemf circuitry. The gain adjusting adjusting is splitted splitted in two phases. phases. A coarse calibration calibration is obtained obtained settin setting g the exter external nal resistor divide dividerr at the CalCoa CalCoarse rse pin (29) following following the relation: relation: Vcontrol Vcon trol = [0.21 + (Rm/Rs) / 28.8] Vcontrol Vcon trol max. range range = Vbg ±0.75V Where: Vbg = bandgap voltage (typ = 1.25) A fine calibration is obtained by writing the internal register 02H -> b[3:0]. The fine calibration is used to compensate the variation of the VCM coil resistance according with operating temperature condition. The calibration is implemented moving the Vcontrol voltage by a percentage indicated on the RLcal table at pag.17.
3.8.3 VCM Bemf Bemf offset trimming trimming Due to the high gain necessary to implement the BEMF reconstruction, the inpact of the offset on the output value is very high. For this reason dedicat dedicated ed circu circuitry, itry, using the 5 MSB of the AD conver converter, ter, has been integrated integrated in order to compensate this offset. The flow chart below reported are describing the method to implement the offset calibration.
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L7250 Figure 12. VCM Bemf Offset Calibration Calibration CLEAR Routin Routine e
START VCM Bemf offset calibration CLEAR CLEA R Routi Routine ne Set VCM in Trista Tristate te Write Reg.03H VCMState[2:0] = 001
Resett Rm/Rs FINE Calibr Rese Calibration ation Write Reg.02H Rlcalib[3:0] = 0000
Set PREADC PREADC in Slee Sleep p Write Reg.06H PREADC[1:0 PREA DC[1:0]] = 00
OPTIONAL
Read 10Bit ADC Read Reg.0BH ADC_DATA[9: ADC_D ATA[9:2] 2] =0000 =00000000 0000 (res (reset et value value)) Read Reg.0CH ADC_DATA[1:0] =00XXXXXX (reset value)
Latch Offset Compensation Write Reg.03H BemfOffCal = 1 then BemfOffCal = 0
Set ADC Clo Clock ck Write Reg.06H PREADC[1:0 PREA DC[1:0]] = 01
EXIT VCM Bemf offset calibration CLEAR CLEA R Routi Routine ne
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L7250 Figure 13. VCM Bemf Offset CALIBRATION Routine Routine START VCM B emf offset calibration calibration Routine
Set VCM in Tristate Tristate Write Reg.03H VCMState[2:0] VCMState[2 :0] = 001
Set ADC Clock Clock Write Reg.06H PREADC[1:0] = 01
START 10Bit ADC Conversion of the BEMF Channel Write Reg.0CH ADC_CH_ADD R[1:0 R[1:0]] =10 ADC_START=1
Wait End of Conversion OPTIONAL
Read 10Bit ADC Read Reg.0BH ADC_DATA[9:2] Read Reg.0CH ADC_DATA[1:0]
NO
YES
Latch Offset C ompensatio ompensation n Write Reg.03H BemfOffCal = 1 then BemfOffCal = 0
EXIT VCM Bemf offset calibration
To restart this routine is mandatory to start First the clear routine (see Fig. 10)
At the end of the calibration routine the analog value measured at pin 31 is rapresenting the VCM BEMF value at the zero motion (BEMF zero value). With the ADC it is poss possible ible to operate a new convertion convertion in order to memorize this value and to take in account of it during the load/unload procedure.
3.8.4 Pow Power er Off Unload - Active brake and constant constant voltage voltage unlo unload ad operation In case of power shut down, an unload procedure start automatically in order to take the heads over the ramp in the parking position (the same procedure can be also enabled, when the power is on, via serial port programming the unload/retract status of the VCM -> reg. 03H. In this case at the end of the unload phase the spindle motor is driven in tri-stat tri-state e condition). condition). The unload unload procedure doesn’t doesn’t start at power power off if the VCM status bit are set to 000 because because the system is considering sider ing t he heads already already in park position. position. No enter entering ing the unload procedure procedure also the spindle brake is not activated. The unload procedure procedure is done in two step step:: - active brake - constant voltage unload operation The unload procedure procedure take place only i f the VCM statu status s bit have moved from the 000 configurati configuration. on. Otherw Otherwise ise the unload procedure doesn’t start and in case of power shut down the spindle motor enter the brake condition. Active Activ e Brake : it is used to have a fast recovery of the VCM velocity down to the unload unload progr programm ammed ed velocity. If just before a power shut down a fast seek was commanded, it is necessary to recover the VCM velocity in
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L7250 order to avoid to rise the ramp or to meet the ID crash stop at high speed. The over velocity detector circuit circuit consist in a window comparator; in in case of power failure failure the VCM power stage is tristated (for a fixed time about 200µs) in order to detect the amplitude amplitude of the Bemf generate generated d by the VCM motion.
If the VCM Bemf is out of the window of the over velocity detector (this means that the heads are travelling at high speed versus the inner or outer outer posi position) tion),, the active active brak brake e routine is invoked invoked.. The voltage threshold ( = motor electrical constant * motor angular velocity), setting the over velocity detector window, is set internally to 1.1V (to 0.4V if 5V application is considered). At the contrary, if the VCM speed is inside the window (the heads where on track or moving slowly) the active brake is skipped and the constant unload operation is commanded. The active brake routine consist in a procedure that drive the VCM alternately with two steps: - first activating the diagonal of the power stage in order to drive current in the right direction to slow down the speed of the VCM for a time (RLTonBrak (RLTonBrake) e) that is half of the programmed programmed RLToffBrake RLToffBrake.. - then activating both the low side drivers of the power stage putting the VCM in short brake condition for a programmable time (RLToffBrake). With the VCM in short short brake the the current current into the coil is forced forced by the Bemf Bemf genera generated ted by the motion motion of the motor and the sense amplifier output is sensed in order order to detect indirectly indirectly the VCM speed. speed. The switch switch between between the active active brak brake e rout routine ine and the const constant ant voltage voltage unl unload oad operati operation on is done when the VCM curre current, nt, measured at the sense amplifier amplifier output during the short brake condition, condition, fall down to zero (VCM is stopped).
The RLToffBrake (and so the RLTonBrake) time can be programmed by writing the Reg. 02H. The active brake proc procedure edure can enabled/dis enabled/disabled abled by writing writing the Reg. 01H. In case the activ active e brake proce procedure dure is disabled, at powe powerr off the consta constant nt unloa unload d operation operation start immediately. immediately. Constant Voltage Unload Constant Unload oper operati ation on : a constant constant voltage (with a sink and and sourc source e capability) capability) is appli applied ed to the VCM in order to drive the heads over the ramp in the parking parking position. According with the contents of the registers REG. 01H it is possible to perform the unload operation in one or two steps and for each steps to select the voltage level applied to the VCM. The capacitor connected at the Timer1 (pin 28) define the total time of the unload operation ; during the unload operation this capacitor is discharged by un internal constant current generator. Programming the bit ‘b3b2b1’ of the REG. 01H it is possible to select different unload procedures: With these bit set to 000 the unload is done in one step with the voltage selected by the two bit RLvoltage1 of REG. 01H. With these bit set to 111 the unload is done in one step with the voltage selected by the two bit RLvoltage2 of REG. 01H. The spindle motor is tristated during the unload operation The other combinations of the bit ‘b3b2b1’ defines different threshold for the comparison with the discharging voltage of the capacitor at pin 21 . The timing for the first step is with the capacitor capacitor voltag voltage e greater then the progr programmed ammed threshold, threshold, the timing for the second step start when the capacitor voltage is below the threshold and end when the capacitor is discharged charg ed under the ’end unload threshold threshold’’ (0.2V typ) . In all the cases, when the capacitor at pin 21 is discharged under the ’end unload threshold’ the spindle motor is driven inbrake condition. The typical value of the retract procedure timing can be extimated using the following expression: T = Tstep1 + Tstep2 = 1.15 * C ext Where: Cext = Exter External nal capacitor capacitor at pin ‘Tim ‘Timer1’ er1’ (28) measured in uF
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L7250 Figure 14. Costant voltage retract operation at power down
C onstant V oltage Retract Operation
H igh
C heck N PO R Sta tu s Lo w S e t S p i n d le le P o w e r s in T RIST ATE
D is a b l e d
G e t R l t im im e r [ 2 : 0 ] R ead Reg.01H
Rltim er[2:0] = “0 0 0 ”
C heck V CM Active Brake Proc. Reg.01H-bit[0]
E n a b le d
S t a rt rt t h e V C M Active Brake Procedure
No
Rltim er[2:0] = “1 1 1 ”
No
Yes S t a r t O N L Y U n l oa oa d 1 with the selected Rlvoltage1
Start ON LY Unload2 w i t h t h e s e le le c t e d R lvoltage2
W a it it E N D o f R l ti ti m e r
S t a rt rt U n l o a d 1 + U n l o a d 2 with the selected R l v o l t a g e1 e 1 & R l v o l ta ta g e 2
S e t S p i n d le le P o w e r s in B R A K E
END
Figure 15. Two step unload tem temporiza porization tion Voltage Capacitor pin21
POR
Programming Threshold End Unload Threshold
Time S te p 1
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Step 2
(*)
L7250 3.8.5 Const Constant ant Voltage Unload Unload operatio operation n at POWER ON The same costant voltage retract operation can be activated via software (during a power on phase). In that case no actions are implemented to the spindle motor; the spindle motor will continue to mantain its running status. Again in power on condition if the bit ‘b3b2b1’ of the REG. 01H are set to 000 or 111 only one step costant voltage retract is activated as in power off condition with the difference that when the ‘End unload threshold’ is reached the retract voltage is mantained applied applied to the motor until a different different programmation is asserted via serial port by the microcontroller. In all the the others ‘b3b ‘b3b2b1 2b1’’ combina combination tion as the timer1 is elapsed the VCM is put in tristate tristate condition. condition. NOTE: In case of Hard Disk application with CSS operation (no Ramp Loading), the polarity of the VCM connection must be reversed. In this way the active brake and the constant constant voltage unload operations will force the the heads in the inner position of the disks.
3.9 10 bit AD conve converte rterr The L7250 device includes a 10 bit analog to digital converter (hereafter ADC). The ADC uses a two complement output code. The ADC converts one of four different channels on demand, through through SPI, and result of conversion can be read from SPI too. The uC tells the ADC which channel channel must be converted converted,, gives a start signal, signal, reads the conversion conversion result; all this happens through the SPI. The ADC convertion frequency, then its conversion time, could be changed using two bits into the serial port (Reg 06H 06H -> b1,b2) b1,b2).. Setting Setting these these two two bit to the the confi configur guratio ation n 00 the ADC can be disabl disabled ed entering entering a sleep mode status. Hereafter is listed the recommended sequence of operations to obtain a conversion from ADC: A) µC selec selects ts which channel channel must be converted, converted, writi writing ng the ADC_CH_ADDR ADC_CH_ADDR field in SPI (Reg 0CH -> b1,b2); b1,b2); µC selects the ADC input range writing the ADCRange bit (Reg 0CH -> b3); ADC_START ART bit (Reg 0CH ->b0) in SPI (end of require required d conversion conversion automaticall automatically y rese resets ts it); µC writes high the ADC_ST B) now µC can read the conversion result from the SPI registers; C) a new conversion can be required. The µC isn’t allowed to requir require e a conversion conversion start when the ADC is already running; running; the start bit can be writ written ten anyway, anyw ay, but ADC logic ignores it and continues continues the current conversi conversion. on. If the uC avoids modifies modifies over the ADC_START ADC_ST ART bit, it can be used as a flag to state the end of the conversion conversion.. The result of conversion is ten bits wide, larger than the 8 bits SPI registers, so it has been spanned over two registers; if allowed by the precision required for the application, only the 8 msbits can be read with a single SPI read operation, saving some time. A new conversion can be required after the end of the previous one but before the read-back of the result, i.e. swapping the order of (B) and (C) points listed before; working this way, it’s possible to convert values closer in time than with the previous sequence. SPI includes an additional read-only field (2bits) that contains the channel number related to the present conversion result.
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L7250 4
POWER POW ER MON MONITOR, ITOR, VO VOLTAG LTAGE E REGU REGULAT LATORS ORS AND SHO SHOCK CK SEN SENSOR SOR
4.1 NPO NPOR R - Power Power ON Reset Reset The Power On Reset circuit monitors 12V and 5V power supplies as well as 3.3V and 2.5V regulators. If any monitored voltage falls below its under voltage threshold, NPOR is latched low after an internal glitch filter delay. When the positiv positive e regulators regulators are in position, position, a delay time time is added, added, the POR delay, delay, before NPOR goes goes high and and the reset condition condition is c lear leared. ed. Duri During ng this delay time, any power power fault will reset the POR delay and s tart the process over again. TDelay = 0.5 0.520 20 * Cext Where : Cext = External capacitor capacitor on pin CPOR measure measured d in uF.
4.2 Linear Voltage Voltage Regulator Regulators:1 s:1.8V .8V & 3.3V The 3.3V linear use an external NPN transistor connected to the 5V power supply line, instead the 1.8V linear regulator regul ator use an external external NPN transistor transistor that could could be c onne onnected cted to the 3.3V line line or to the 5V power supply supply line. To fix the 1.8V regulator regulator volta voltage ge outpu outputt an exter external nal resistor divider divider as to be used. The regulated voltage could be varied around the 1.8V value (from 1.3V to 2V) choosing the external divider appropriately. The stability stability of the two regulator regulators s is guarantee guarantee by the external filter capacito capacitorr . The internal Vbg reference is trimmed at the wafer level.
Figure 16. Linear positive regulators VCC5
Vbg
3 3_ B ase
15
R2
3 3_ Fee d
3.3V output
16 R1
Cext
V CC 5
Vb g
2 5_Base
13
25_Feed
R 1ext
1.8V output
14
R 2ext
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C ex t
L7250 4.3 Negat Negative ive Voltage Regulator Regulator (flyback (flyback configuration) configuration) This is the default Negative Voltage Regulator configuration; programming the Test Register is possible to reconfigurate this regulator following the indication present on the next paragraph. The negative voltage regulator is a fixed frequency switcher intended to provide bias for the MR head preamp. The NVR consists of an internal internal triangular wave oscillator, an error amplifier, a comparator and a circuitry to soft start_up the regulator itself, in conjunction with an external PMOS power device, power diode, inductor, capacitor, feed feedback back resistors and compensatio compensation n netwo network rk (refer to the block diagram diagram of the negative negative volta voltage ge regulator regulator including also the external components). The error amp compares the external voltage feedback to the internal reference (Vbg = 1.25V). The voltage difference value is scaled by two external resistors. The ratio of these two resistors determines the nominal value of the regulated regulated negative voltage voltage (the internal reference reference is set to the bandgap bandgap voltage ~1.25V). ~1.25V). The error amplifier input is available at N_FEED pin and the amplifier output is available at N_COMP pin. The voltage error gain and the loop compensation can be adjusted by the external components across these two pins. The output of the error amplifier amplifier is comp compare ared d to an internal internal triangu triangular lar wave oscillator oscillator to determine determine the duty cycle of the external PMOS power switch. A voltage clamp is placed on the error amplifier output to limit the maximum duty cycle. The nominal valu value e of the trian triangula gularr wave oscillator oscillator frequency frequency is 500 kHz (programming (programming the test regi register ster Reg 0FH to ‘00001001 ‘00001001’’ it is possible to increm increment ent the switching frequen frequency cy to the nominal value of 1Mhz). During the ON portion of the duty cycle, the PMOS charges an external inductor. During the OFF phase, the inductor charges a capacitor through an external diode, in a voltage inverter configuration. This architecture avoids any negative negat ive volt voltage age on the L7250 IC pins. Under normal normal spec specified ified load conditions conditions and correct correct scaling of the externall components terna components the regulato regulatorr circuit should operates operates in a constant frequenc frequency y variable duty duty cycle switch mode withoutt any cycle slips. The NVR include also a digital soft start_up circuitry withou circuitry in order to limit the in rush current coming from the power supply supply when the regulator regulator is turned-on turned-on.. The NVR is controlled controlled via serial port port (usin (using g the Reg. 05H -> b1 the regulator regulator could be turn turned ed on and off). During the power-up power-up and power-down power-down phases phases the regulator regul ator is always off being being the serial port in reset status then the VnegEn VnegEn bit equal to zero. During During those phases the N_DRV output output driver is in tri-state condit condition ion then an extern external al pull-up to assure the Pch off condition condition must be considered.
Figure 17. Negative regulator (Flyback configuration) - default configuration
V CC 5 V RE F25
21
500Khz - 1Mhz 5K
R 1ext
N _D RV
Vbg
10
(typ 1.25)
M 1 ex t
R 2e x t
12 N _C OM P
Ccext C fext
11 N_ FE E D
Rcext
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L7250 4.4 Negat Negative ive Voltage Voltage Regulator (CUK configur configuration ation)) Programming the Test Register Reg 0FH to ‘00101001’ it is possible to re-configurate the negative regulator loop inverting its polarity. All the others test register (Reg0FH) configurations are resetting to the default negative voltage regulator loop polarity (take care to avoid the test register bits modification modification if the ‘CUK configuration’ configuration’ hardware is present and the negative regulator is enabled). The functionality of the regulator is the same descripted on the previous paragraph with the difference that the loop polarity is reversed to permit to drive the external external Nch component. component. During this operation operation the nominal value of the triangular triangular w ave oscillato oscillatorr frequ frequency ency i s always fixed to 1 MHz. The NVR is controlle controlled d v ia serial port (using the the Reg. 05H -> b1 the regulator regulator could be turned turned on and off). off). Take care to program correctly the Test Register to enter the CUK configuration before to enable the NVR. During the the powe power-up r-up and powerpower-down down phases phases the regul regulator ator is always always off being being the serial port in reset status status then then the VnegEn bit equal to zero. During those phases the N_DRV output driver is in tri-stat tri-state e condition condition then an externall pullterna pull-down down to assure the Nch off condition must be conside considered. red.
Figure 18. Negative regulator (CUK configuration) - Test register => 00101001
V CC 5
V R E F 25
21 R1ext
R2ext C 1ext
1Mhz N _DRV Vb g
10 (typ 1.25)
12 N _C O M P
C cext
11 N _F EE D
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R cext
5K
M 1ext
Cfext
L7250 4.5 Sho Shock ck Sen Sensor sor This block takes input from a piezoelectric or charging mode shock sensor element (selectable using the SPI bit ShockConf -> Reg02H, bit 7 ), and includes external filtering capability. A digital latched signal is available on SkDout pin if the Sken bit (from SPI) is set to 1 othe otherwise rwise the SkDout pin is transparent transparent to the shock signal. If the output signal has been latched, a pulse to zero of the Sken bit it is necessary to clear it. The shock sensor element will be conn connec ected ted to the Skin and VREF25.
Figure 19. Piezoelectric Shock Sensor typical application block diagram (Reg02H->bit7=0)
Vref25+VthH
9R
0
27
V ref25
R
V ref25
S
21
1
S kD out 1 0M
R
23
Vref25-VthL
2 5 S kF in
24 Sk O ut
S kin
26 Sk Fou t
C 1ex t
SkEn (from SPI)
C 2ext
R 1ext R 2ext
Figure 20. Charging Shock Sensor typical application block diagram (Reg02H->bit7=1)
V ref25+VthH 0
27
V ref25 Vref25
S
21
1
S kD ou t R
23
V ref25-VthL
2 5 S kF in
2 4 Sk Ou t
Sk in
S kF ou t
C S ext t x e 1 G R
R S ext
t x e 2 G R
Vref25
26
C 1ext
Sk E n (from SP I) I)
C 2ext
R1ex t R 2ext
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L7250 4.6 Over Temperat Temperature ure Protecti Protection on L7250 has a temperatu temperature re protection protection circuit consisti consisting ng of a temperature temperature sense circuit circuit and two compar comparators ators.. The temperatu temp erature re s ense circuit circuit generates generates a voltage proportiona proportionall to the absolute absolute die temperatur temperature. e. One comparator comparator trips when the die temperature exceeds 140 deg C, asserting the temperature warning signal in the status register (ThWarn in the Reg 00H -> b3). The thermal warning warning comparator comparator has nomin nominally ally 20 deg C hysteresis. hysteresis. The thermal Shutdown comparator trips when the die temperature exceeds 160 deg C, indicates an over temperature perat ure cond condition ition i n the statu status s regi register ster (ThShutdown (ThShutdown in the Reg00H -> b4). The status regis register ter is trans transpare parent nt to the therm thermal al shutdo shutdown wn information. information. If the ThShutdown bit is equal to zero only the flag on the status register is activated, else the L7250 is driven into thermal shutdown mode, which initiates Unload of the Voice Coil Motor (no actions on the Spindle motor has been taken). Hysteresis of 25 deg C on this comparator allows the die temperature to stabilize before it is re-enabled. Iif the ThShutdown bit is set to 1, the thermal Shutdown condition is latched, then to re-enable the function a reset cycle is needed (ThShutdown (ThShutdown bit must be prog programm rammed ed to 0, then set again to 1).
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L7250 Figure 21. 12V Application diagram P _ r M o C M t C o V V M
M _ M C V N K E L k A S C l S C T A S D Y S
R C 1 O T T P U Z S N O K E T C O H S
m h o 7 2 . 0
P M C V
m h o 2 2 . 0 F n 0 0 1
f u 7 4 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3
2 N E S R
t o m V
E r L o D t N o I P M S
W V U T C
F n 2 2
1 N E S R
2 N M C V
1 N M C V
4 D N G M C V
3 D N G M C V
N _ S N S
t u O _ R R E
t u O _ S N S
P _ S N S
n I _ R R E
t u x p u n A I
N t K k E u L l A T S O C C A _ S S Y D C S S A D
9 4
RS E NS E
0 5
OU T W1
1 5
OU T W2
2 5
V M1
3 5
V M2
T i me r 1
8 2
4 5
V CV 4
S k Do u t
7 2
5 5
V CV 3
S k f o u t
6 2
6 5
OU T V 1
7 5
OU T V 2
8 5
RS E N3
9 5
RS E N4
0 6
OU T U 1
1 6
OU T U 2
T e s t
A Da u x
4 6 P 0 F 1 x Q 0 T 1
0 3
S k f i n
5 2
S k o u t
4 2
S k i n
3 2
Z C
2 2
V R E F 2 5
1 2
A GN D C B RA K E
CT CP OS CH
NP OR
8 1
4 6
V B OOS T
CP OR
7 1
1
2 V C V
1 P M C V
2 P M C V
2
3 4
r k c o s o n h e S S
9 1
3 6
1 V C V
F n 0 0 1
0 2
2 6
F n 0 3 3
F n 2 2
9 2
C a l C o a r s e
0 5 2 7 L
2 3 1 3
V CM B e mf
F u 1
F n 0 2 2
1 D N G M C V
2 D N G M C V
C S O P C
5 C C V
D N G _ G I D
5
6
7
8
9
V R D _ N
D E E F _ N
P M O C _ N
E S A B _ 5 2
D E E F _ 5 2
E S A B _ 3 3
D E E F _ 3 3
0 1 2 3 4 5 6 1 1 1 1 1 1 1
P M C V
m h o 5 7 2
F n 0 0 1
K 5 V 5
F n 0 0 1
m h o 5 2 6 V 5
G S
V 5
D
F u 0 1
F u 0 1
F n 0 0 1
F n 0 0 1
F u 0 1 n o i t a r t u l u i g a f f e n o * D c
V 2 1
V 5
V 4 -
D N G
V 8 . 1
D N G
V 3 . 3
D N G
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L7250 Figure 22. 5V Application diagram P _ r M o C M t C o V V M
M _ M C V N K E L k A S C l S C T A S D Y S
R C 1 O T T P U Z S N O K E C T O H S
m h o 7 2 . 0
P M C V T S O O B V
m h o 2 2 . 0 F n 0 0 1
n e 5 K 0 R 2
f u 7 4 8 4
2 N E S R
t o m V
E r L o D t N o I P M S
W V U T C
7 6 5 4 3 2 1 0 9 8 7 6 4 4 4 4 4 4 4 4 3 3 3 3
1 N E S R
2 N M C V
t t 1 P t u n u N 4 3 N _ _ u O I O M D D S S O _ _ _ _ C N N N N R R C V G G S S S N R R A M M S E E D C C V V
2
k l C S Y S
t x u u p n A I
N A E T S A D S
RS E N S E
0 5
OU T W1
1 5
OU T W2
2 5
V M1
3 5
V M2
T i me r 1
8 2
4 5
V C V 4
S k Do u t
7 2
5 5
V C V 3
S k f o u t
6 2
6 5
OU T V 1
7 5
OU T V 2
8 5
RS E N 3
9 5
RS E N 4
0 6
OU T U1
1 6
OU T U2
2 6
CT
3 6
CP OS CH
4 6
T S O O B V
K L C S
3 3
9 4
T e s t
A D a u x
F n 0 3 3
4 6 P 0 F 1 x Q 0 T 1
5 2
S k o u t
4 2
S k i n
3 2
Z C
2 2
V R E F 2 5
1 2
C B RA K E
1 V C V 1
2 V C V
1 P M C V
2
3
2 P M C V 4
0 3
S k f i n
A GN D
V B O OS T
F n 2 2
9 2
Ca l C o a r s e
0 5 2 7 L
2 3 1 3
V C MB e m f
F n 2 2 F n 2 2
5 4 3 3
F n 0 0 1 r k o c s o n h e S S
0 2 9 1
NP OR
8 1
CP OR
7 1
F u 1
F n 0 2 2
1 D N G M C V
2 D N G M C V
C S O P C
D N V D E 5 G _ R E C G D F _ _ C I V D N N
5
6
7
8
9
P M O C _ N
E S A B _ 5 2
0 1 2 3 1 1 1 1
D E E F _ 5 2
E S A B _ 3 3
4 5 1 1
D E E F _ 3 3
6 1
1
P M C V
m h o 5 7 2
F n 0 0 1 K 5 F n 0 0 1
F u 7 . 4
V 5
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V 5
G S
V 5
D
n o i t a r t u l u i g a f f e n o * D c
V 5
m h o 5 2 6
V 4 -
D N G
V 8 . 1
F u 0 1
F u 0 1
F n 0 0 1
F n 0 0 1
D N G
V 3 . 3
D N G
L7250
mm
DIM. MIN.
inch
TYP.
M AX .
A
M IN .
TYP.
1.60
A1
0.05 0.
A2
1.35
B C
0.063
0.15
0.002
0.006
1.40
1.45
0.053 0 .0 .055 0 .0 .057
0.18
0.23
0.28
0.007 0 .0 .009 0 .0 .011
0.12
0.16
0.20
0.0047 0.0063 0.0079
D
12.00
0.472
D1
10.00
0.394
D3
7.50
0.295
e
0.50
0.0197
E
12.00
0.472
E1
10.00
0.394
E3
7.50
0.295
L
0.40
0.60
L1
0.75
0.0157 0.0236 0.0295
1.00
K
OUTLINE OUTLIN E AND MECHANICAL DATA
M AX .
0.0393
TQFP64
0°(min.), 7 °(max.)
D D1 A D3
A2 A1
48
33
49
32 0.10mm Seating Plane
B B
3 E
1 E
E
17
64 1
16 C
e 1 L
L
K TQFP64
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L7250
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