ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES ®
IPC/JEDEC-9702 Monotonic Bend Characterization of Board-Level Interconnects
IPC/JEDEC-9702 June 2004
A standard developed by IPC and JEDEC
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IPC/JEDEC-9702 ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES ®
Monotonic Bend Characterization of Board-Level Interconnects
Developed by the SMT Attachment Reliability Test Methods Task Group (6-10d) of the Product Reliability Committee (6-10) of IPC and the JEDEC Reliability Test Methods for Packaged Devices Committee (JC-14.1)
Users of this publication are encouraged to participate in the development of future revisions. Contact: IPC 2215 Sanders Road Northbrook, Illinois 60062-6135 Tel 847 509.9700 Fax 847 509.9798
JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, VA 22201-3834 Tel 703 907.7559 Fax 703 907.7583
This Page Intentionally Left Blank
June 2004
IPC/JEDEC-9702
Acknowledgment Members of the JEDEC Reliability Test Methods for Packaged Devices Committee (JC-14.1) and the SMT Attachment Reliability Test Methods Task Group (6-10d) of the Product Reliability Committee (6-10) have worked together to develop this document. We would like to thank them for their dedication to this effort. Any document involving a complex technology draws material from a vast number of sources. While the principal members of the SMT Attachment Reliability Test Methods Task Group are shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them, the members of the JEDEC and IPC extend their gratitude. Product Reliability Committee
JEDEC Reliability Test Methods for Packaged Devices Committee
Chair Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory
Chair Jack McCullen Intel Corporation
SMT Attachment Reliability Test Methods Task Group
Chair Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Vice-Chair Werner Engelmaier Engelmaier Associates, L.C.
Technical Liaisons of the IPC Board of Directors
Peter Bigelow IMI Inc. Sammy Yi Flextronics International SMT Attachment Reliability Test Methods Task Group
Mudasir Ahmad, Cisco Systems, Inc.
Denis Gignac, Nortel Networks
Patricia J. Amick, Boeing Aircraft & Missiles
Lavanya Gopalakrishnan, Ciena Corporation
Pierre Audette, Nortel Networks Jean Bobgan, Guidant Corporation
Michael R. Green, Lockheed Martin Space Systems Company
Dr. John Kirk Bonner, Jet Propulsion Laboratory
Samy Hanna, AT&S Austria Technologie & Systemtechnik
Mark Brillhart, Cisco Systems Inc.
Hana Hsu, Mitac International Corporation
Nicole Butel, Agilent Technologies Srinivas Chada, Ph.D., Jabil Circuit, Inc. Phillip Chen, Northrop Grumman Canada Corporation Beverley Christian, Ph.D., Research In Motion Limited Thomas Clifford, Lockheed Martin Space Systems Company Yves Desrochers, Nortel Networks Howard S. Feldmesser, Johns Hopkins University Jean-Yves Gagne, Nortel Networks Mahendra S. Gandhi, Northrop Grumman Phil Geng, Intel Corporation
Kim Hyland, Solectron Corp. Thomas E. Kemp, Rockwell Collins Vincent B. Kinol, Umicore America Inc. Gregg Klawson, General Dynamics C4 Systems Dennis Krizman, Celestica Kuan-Shaur Lei, Hewlett-Packard Company James F. Maguire, Intel Corporation Wesley R. Malewicz, Draeger Medical Systems, Inc. John Manock, Lucent Technologies, Inc. Susan S. Mansilla, Robisan Laboratory Inc.
Lei L. Mercado, Ph.D., P.E., Intel Corporation Frank Mortan, Texas Instruments Keith G. Newman, Sun Microsystems Inc. Bob Ogden, Raytheon Systems Company Deepak K. Pai, C.I.D.+, General Dynamics-Advanced Information Mel Parrish, Soldering Technology International Kumar Pavuluri, Texas Instruments Inc. Mike Pfeifer, Motorola Inc. Sundar Sethuraman, Solectron Corporation Rocky Shih, Hewlett-Packard Company Vern Solberg, Tessera Technologies, Inc. Vish Sundararaman, Ph.D., Texas Instruments Inc. Vasu S. Vasudevan, Intel Corporation Dewey Whittaker, Honeywell Inc. Greg Wood, ACI/EMPF iii
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June 2004
Table of Contents 1
FOREWORD ............................................................. 1
ANNEX A
...................................................................... 9
2
INTRODUCTION ....................................................... 1
ANNEX B
.................................................................... 12
3
SCOPE ...................................................................... 1
4
TERMS AND DEFINITIONS ..................................... 1
5
SYMBOLS AND ABBREVIATED TERMS ............... 2
6
SAMPLING ................................................................ 2
7
APPARATUS ............................................................. 2
Figures Figure 7-1
Universal Tester .................................................. 2
Figure 8-1
Test Board Layout ............................................... 4
Figure 8-2
Rectangular Package Orientation ....................... 5
Figure 8-3
Single Package Daisy-Chain Configuration (Example) ............................................................ 5
Figure 8-4
Strain Gage Placement ....................................... 7
7.1 7.2
Universal Tester ....................................................... 2 Strain Measurement Equipment .............................. 3
Figure 9-1
Interconnect Fracture Modes (Solder Ball Array Devices) .............................................. 8
7.3
Continuity Monitoring Equipment .......................... 3
Figure A.1
Example Configuration (PWB Thickness = 1.00 mm) .......................................................... 9
PROCEDURE ............................................................ 3
Figure A.2
Example Configuration (PWB Thickness = 1.55 mm) ........................................................ 10
Figure A.3
Example Configuration (PWB Thickness = 2.35 mm) ........................................................ 11
8
8.1 8.2 8.3 8.4
Component Sample ................................................. Test Board Material ................................................. Test Board Thickness and Metal Layer Count ....... Test Board Surface Finish .......................................
3 3 3 4
8.5 8.6 8.7
Test Board Land Pads ............................................. 4 Test Board Layout ................................................... 4 Test Board Daisy-Chain Links ................................ 4
8.8 8.9 8.10 8.11
Board Assembly ...................................................... Storage ..................................................................... Strain Gages ............................................................ Set-Up Test Board ...................................................
6 6 6 6
Tables Table 7-1
Universal Tester Requirements ............................ 2
Table 8-1
Recommended Test Board Thickness & Layer Count .......................... 3
Table 8-2
Test Board Layout Requirements ......................... 4
Table 8-3
Monotonic Bend Test Requirements .................... 7
Table B.1
Test Report Recommendations (Equipment & Materials) ..................................... 12
Table B.2
Test Report Recommendations (Board Assembly) ............................................... 12
Table B.3
Test Report Recommendations (Test Results) ..................................................... 12
8.12 Four-Point Bend Test .............................................. 6 9
iv
FAILURE CRITERIA AND ANALYSIS ..................... 7
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IPC/JEDEC-9702
Monotonic Bend Characterization of Board-Level Interconnects 1 FOREWORD
Strain:
This publication on monotonic bend testing is intended to characterize the fracture strength of a component’s boardlevel interconnects. The document is applicable to surface mount components attached to printed wiring boards using conventional solder reflow technologies. The monotonic bend characterization results provide a measure of fracture resistance to flexural loading that may occur during conventional non-cyclic board assembly and test operations, and supplements existing standards that address mechanical shock or impact during shipping, handling or field operation.
length)
Dimensionless unit, (change in length) ÷ (original
Change in strain divided by the time interval during which this change is measured Strain-Rate:
Planar copper foil pattern that is adhered to an underlying surface and exhibits a change in resistance when subjected to a strain
Strain Gage:
Strain Gage Element: Sensing area of strain gage defined by the serpentine copper grid pattern Uniaxial Strain Gage: Strain gage incorporating a single strain gage element, i.e., capable of detecting strain along a single axis
2 INTRODUCTION
Semiconductor devices are assembled in a variety of package configurations, and are used in a multitude of applications. Given the diversity of package constructions and end-use conditions, it is not feasible to establish a single qualification requirement relating to bend testing; however, definition of a uniform test methodology and a standard reliability characterization reporting process are increasingly necessary to ensure adequate product quality. 3 SCOPE
This publication specifies a common method of establishing the fracture resistance of board-level device interconnects to flexural loading during non-cyclic board assembly and test operations. Monotonic bend test qualification pass/ fail requirements are typically specific to each device application and are outside the scope of this document.
For the purposes of this standard, the selected terms and definitions listed below apply. General Terms
Packaged semiconductor device
Conductive element used for electrical interconnection, e.g., solder ball, lead, etc. Interconnect:
Monotonic Test:
Non-reversing, test to fail
Strain Related Terms Global PWB Strain: Four-point bending strain of uniform printed wiring board, ignoring any effects due to the package(s) 6
Dimensionless unit, 10 x (change in length) ÷ (original length) Microstrain:
Four-point assembly fixture support with a rounded contact surface
Anvil:
Crosshead Assembly: Clamping/attachment assembly of universal tester that moves relative to the base of the test equipment, and creates the forces necessary for specimen testing Four-Point Bending Fixture: Test assembly that supports a specimen on two anvils or rollers, and symmetrically loads the specimen on the opposite surface with two anvils or rollers Load Span: Distance between the two anvils or rollers
that load the test specimen Roller: Four-point assembly fixture support that incorporates a cylindrical bar as the contact surface
Distance between the two anvils or rollers that support the test specimen
Support Span:
4 TERMS AND DEFINITIONS
Component:
Mechanical Test Equipment Terms
Test equipment capable of tensile/ compressive loading using controlled linear motion of a crosshead assembly Universal Tester:
Electrical Test Terms Daisy-Chain: A conductive link that can be connected in series with other conductive links (like a chain of daisies) to form a continuous electrical net In-Situ Measurement: Measurement conducted during a test, i.e., in place, rather than during an interruption of the test condition
Failure Analysis Term
Dye exposure of package/board assembly followed by mechanical removal of the package Dye-and-Pry:
1
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5 SYMBOLS AND ABBREVIATED TERMS
Unit board thickness crosshead travel distance crosshead speed degree Celsius degree Fahrenheit Hertz load span microstrain second (time) strain strain-rate support span
Symbol t δ δ˙ °C °F Hz LL µε or µStrain s ε ε˙ LS
Term ball grid array chip scale (size) package intermetallic compound organic solderability preservative printed wiring board surface mount small outline package
Abbreviation BGA CSP IMC OSP PWB SMT SOP
6 SAMPLING
A statistically relevant sample size is required. It is recommended that several manufacturing lots be sampled to evaluate lot-to-lot variability. Depending on failure distribution, desired sensitivity, confidence limits, etc., sample quantities such as 23, 30, 45, etc., may be appropriate.
7 APPARATUS 7.1 Universal Tester A universal tensile tester incorporating a deflection measuring device shall be used to generate a controlled board deflection rate. The tester shall include a four-point bending fixture (see Figure 7-1) to apply a theoretically uniform bending moment across the load span.
Table 7-1 lists dimensional and operational requirements for the universal tester. Table 7-1
Universal Tester Requirements
Description
Requirement
Anvil/roller radius
3 mm [0.12 in.], min.
Anvil/roller length
> board width
Ambient temperature
23 °C ± 2 °C [73 °F ± 4 °F]
Non-standardized bend test methods in practice today often specify an applied load, span and/or crosshead travel distance to characterize mechanical resistance to failure of board-level device interconnects. Unfortunately, these parameters are not readily transferable to differing board thicknesses, package configurations or board layouts. The dimensionless unit of strain, ε, however, can be applied more broadly to differing board/package geometries and relates more directly to analytical and computational failure models.
IPC/JEDEC-9702-7-1
Figure 7-1
2
Universal Tester
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˙ The crosshead travel distance (δ) and crosshead speed (δ) of a universal tester are approximately proportional to the ˙ respectest board assembly strain (ε) and strain-rate (ε), tively. The relationship between these variables can be determined empirically by testing a mechanically representative package/board assembly (set-up test board); however, these relationships may prove non-constant or nondeterminant, depending on universal tester capability and board/ package configuration. This test method specifies use of the following simplified analytical relationships (see Equations 1 & 2) to establish the universal tester control settings for crosshead travel distance and crosshead speed, based upon global PWB strain and strain-rate input variables, respectively. These equations are derived from classic beam theory and ignore any effects due to the package(s), or to the Poisson’s ratio effect of a plate in bending. Equation 1
δ=
ε (LS − LL) (LS + 2LL) 6t
where δ ε LS LL t
= = = = =
crosshead travel distance global PWB strain support span load span (centered within support span) PWB thickness
Equation 2
ε˙ (LS − LL) (LS + 2LL) δ˙ = 6t where δ˙ = crosshead speed ε˙ = global PWB strain-rate LS = support span LL = load span (centered within support span) t = PWB thickness 7.2 Strain Measurement Equipment A strain measurement equipment scan frequency of 500 Hz (min.), and a data signal resolution of 16 bits (min.) are preferred for the short duration (<5 seconds, typ.) monotonic bend test.
Continuity monitoring is preferably performed by the same high scan frequency equipment used for strain measurements, allowing simultaneous recording of net resistance and strain.
examples. Discrete SMT devices, e.g., capacitors, resistors, etc., are outside the scope of this test method. The test component must contain daisy-chain connections to allow in-situ continuity monitoring of the device board-level interconnects during the bend test. It is likely that the same daisy-chain package construction may be used for both bend testing and thermal cycle testing. For bend testing of array-based packages; however, only the outermost package daisy-chain links need to be connected to a corresponding PWB daisy-chain link and electrically monitored. The daisy-chain package materials, dimensions, and construction must be representative of a typical production device. The layout of solder balls or leads for the daisychain package should represent a typical leadcount configuration expected for a production device of that package body size. As indicated previously, the monitored daisychain links on the package consist of the outer component interconnects. Each package daisy-chain link should consist of a pair of adjacent solder joints or leads. Functional devices may be used in lieu of a daisy-chain package if the electrical continuity monitoring requirements defined in this publication can be met. 8.2 Test Board Material The test board material should match the composition of the actual end-use PWB, typically FR4 epoxy/glass laminate. 8.3 Test Board Thickness and Metal Layer Count The test board thickness and metal layer count should match the actual end-use PWB. Definition of a ‘‘typical’’ printed wiring board is problematic given the expanding usage of alternative board constructions and materials, and the widening form-factor gap between handheld electronic devices and other application types. Table 8-1 provides a minimum recommended test board thickness and metal layer count if the device will be used in a variety of end-use applications, or if the actual PWB configuration is unknown. Finite element modelling suggests that the ratio between package/ solder interfacial strain and global PWB strain increases with increased board thickness and copper layer count. Consequently, use of a thicker test board or higher metal layer count than listed in Table 8-1 will typically lead to more conservative bend test results. Table 8-1 Recommended Test Board Thickness & Layer Count
7.3 Continuity Monitoring Equipment
Copper Layers, min.
Max. Package Body Dimension, X (mm) [in.]
PWB Thickness, min. (mm) [in.]
Small: X ≤15 [0.59]
1.00 [0.039]
4
8 PROCEDURE
Medium: 15 [0.59] < X <40 [1.58]
1.55 [0.062]
6
8.1 Component Sample This standard assumes a surface
Large: X ≥40 [1.58]
2.35 [0.093]
8
mount device; BGA, SOP and CSP are typical device
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The test board surface finish should match the actual end-use PWB surface finish. If the device will be used in a variety of applications, multiple surface finishes may need to be evaluated. 8.4 Test Board Surface Finish
8.5 Test Board Land Pads The test board land pads should match the configuration of the actual end-use PWB, typically non-solder mask defined (NSMD). If the end-use configuration is unknown, NSMD land pads should be used with exposed PWB land pad diameters that are 80-100% of the package solder-wetted pad diameters.
Finite element simulations support the testing of multiple packages on a test board (see Figure 8-1) given the specific test board layout requirements detailed in Table 8-2; however, variations in PWB and solder strain are typically greater for test boards with multiple components. 8.6 Test Board Layout
The lengthwise direction of rectangular packages should be aligned with the longitudinal direction of the test board as illustrated in Figure 8-2. 8.7 Test Board Daisy-Chain Links The combination of daisy-chain links on the package and those on the test board should result in completed daisy-chain nets after board assembly. 100% daisy-chain coverage of the outer package interconnects parallel to the anvils/rollers is required, but the coverage may extend to the entire package interconnect footprint. Each package must have at least
June 2004 Table 8-2
Test Board Layout Requirements
Description
Requirement
Package quantity per board
15 (3 row x 5 col.), max. - small* pkg 4 (2 row x 2 col), max. - medium* pkg 4 (2 row x 2 col), max. - large* pkg * Note: see Table 8-1 for package body size classifications
Distribution
Package sites must be uniformly distributed
Symmetry
Package sites must be symmetrical about both mid-span axis and PWB longitudinal centerline
Package-topackage separation (x-y directions)
5 mm [0.20 in.], min. (package edge to package edge)
Package-to-anvil separation
10 mm [0.39 in.], min. (package edge to inner anvil/roller centerline)
Package-to-board separation
8 mm [0.32 in.], min. (outermost package edge to board edge)
Package orientation
Package orthogonal to PWB & four-point bend fixture
Connector location
Outside support span anvils/rollers, including when PWB is bent in its max. condition
a single separately monitored daisy-chain net. See Figure 8-3 for an illustration of a test board daisy-chain configuration (single package). Test boards using functional devices may require a modified configuration to satisfy the electrical continuity monitoring requirements.
IPC/JEDEC-9702-8-1
Figure 8-1
4
Test Board Layout
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IPC/JEDEC-9702-8-2
Figure 8-2
Rectangular Package Orientation
IPC/JEDEC-9702-8-3
Figure 8-3
Single Package Daisy-Chain Configuration (Example)
5
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For array-based SMT packages, the solder connections at the package corner typically fail sooner during monotonic bend testing than the connections on the middle of the package edge. Consequently, separate daisy-chain nets for the package corners are recommended. Finite element analysis indicates that the package/solder interfacial strain at the package corner is most severe for the largest package body sizes, and for the largest array of test packages on a single test board. Electrical monitoring traces should be routed on internal PWB layers to reduce the likelihood of external trace contact damage during testing. Further, test board vias connecting internal electrical monitoring traces may fail prior to the monitored package interconnections. Consequently, it is recommended that any circuitry associated with continuity monitoring have redundant trace and via routing wherever possible. Outer layer traces required by PWB routing constraints should avoid anticipated strain gage locations. Probe pads are recommended for each component daisychain link, wherever possible, to facilitate fault isolation and failure analysis. 8.8 Board Assembly The solder paste printing process and thermal reflow profile should be optimized prior to mass reflow or rework assembly of the test boards. Optimization of solder paste volume and paste registration typically requires evaluation of printing speed, squeegee pressure, stencil separation speed, stencil thickness, stencil aperture geometries, etc. Similarily, optimization of solder wetting, solder ball/fillet shape and solder surface finish often involves evaluation of preheat temperature, peak solder/package/board temperatures, duration above solder liquidus temperature, cooling/heating ramp rates, etc. 8.9 Storage The measured fracture resistance of the board-level interconnects can be affected by storage conditions (temperature, humidity, atmosphere) and storage duration of the package/PWB assemblies prior to bend testing. A recommended duration between board assembly and bend test is eight hours, minimum, and 168 hours, maximum. 8.10 Strain Gages For the test configuration defined in this standard, finite element modelling indicates that the PWB principal strain angle is essentially coincident with the longitudinal board axis at all board locations. Therefore, the use of uniaxial strain gages for monitoring board strain and strain-rate is acceptable. A nominal strain gage element size of 1.5 mm x 1.5 mm [0.059 in. x 0.059 in.] is recommended.
The sensing direction of the uniaxial strain gage must be aligned with the longitudinal board direction. For test configurations meeting the specific requirements of this test 6
June 2004
method, analysis indicates that the PWB strain values are generally uniform from one package location to another, allowing for the requirement of only three strain gages per test board (see Figure 8-4). Additional strain gages at the opposite PWB diagonal can be used to verify symmetrical loading. Although PWB strain measurements from any single location in Figure 8-4 may prove more relevant to a particular end-use PWB assembly condition or application, all three strain gage locations relate to package interconnect strain and fracture resistance. Cumulatively, the PWB strain readings at these locations provide enhanced characterization of a device’s interconnect fracture resistance. Measurements using the strain gage mounted on the top of the test board as shown in Figure 8-4 approximate global PWB strain. PWB strain readings using the gage placed at the package center as shown in Figure 8-4 approximate minimum PWB strain and help quantify the localized stiffening effect of the test package. Finally, measurements using the strain gage coincident with the cornermost solder joint, or lead, approximate maximum PWB strain. The strain gages should be mounted to the test board using materials and procedures specified by the gage manufacturer, e.g., surface preparation, adhesive application, gage attachment, adhesive cure, leadwire attachment, etc. Although it is not preferred practice, strain gages may not be necessary on every test board if a documented database of past test results (using near-identical configurations) has established minimal statistical strain variation between one test board assembly and another, and the crosshead travel distance at interconnect failure can be accurately recorded. 8.11 Set-Up Test Board A set-up test board is recommended for verification of test parameter settings. Strain gage monitoring of the set-up board beyond the minimal requirements shown in Figure 8-4 is recommended to provide more complete characterization of the PWB strain distribution. 8.12 Four-Point Bend Test The test assembly should be oriented as shown in Figure 7-1 such that the component leads or solder joints are placed in tension during the fourpoint bend test. Empirical testing, supported by finite element analysis, indicates that board-level package solder connections are typically more susceptible to fracture with increased strain-rate (at comparable PWB strain levels). Testing conducted at crosshead speeds less than specified in Table 8-3 will tend to overstate fracture strength of a component’s board-level interconnects; hence, test equipment and test board configurations should be selected that meet the minimum crosshead speed shown below, wherever possible, to insure consistent, conservative reporting of interconnect strength.
A PWB pre-load is specified to ‘‘seat’’ the test board against all four anvils/rollers prior to start of the test. The
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IPC/JEDEC-9702-8-4
Figure 8-4
Strain Gage Placement
Table 8-3
Monotonic Bend Test Requirements
Parameter
Value
PWB pre-load, ε
100 µStrain, max.* * Note: pre-load is measured using strain gage mounted on the top of the test board as specified in Figure 8-4
Minimum crosshead speed, δ˙
Calculated value (see Equation 2), using nominal global PWB ˙ of 5,000 µStrain/s strain-rate, ε,
Maximum crosshead travel distance, δ
Electrical failure of all daisy-chain nets
actual monotonic bend test occurs at a constant crosshead speed corresponding to the nominal global PWB strain rate value specified in Table 8-3, terminating when all of the monitored daisy-chain nets have electrically failed. Although it should be avoided wherever possible, equipment and test configuration limitations may sometimes results in test termination before failure. Annex A provides example universal tester configurations that satisfy the four-point bend test requirements of Table 8-3, using the crosshead speed as calculated by Equation 2, and the PWB test board thicknesses referenced in Table 8-1. Strain gage readings should be calibrated and set to zero in the initial undeflected condition, prior to the specified preload. The test board strain gages should be continuously monitored at a recommended scan frequency of no less than 500 Hz, and recorded during the entire board deflection procedure.
Depending on board configuration and warpage, the preload level shown in Table 8-3 may not always result in proper seating of the PWB against the anvils/rollers. The test board assembly should be returned to an unloaded condition immediately upon conclusion of the test. In-situ monitoring of the daisy-chain nets is preferably conducted using the same equipment used to measure strain, with strain and net resistance recorded simultaneously. 9 FAILURE CRITERIA AND ANALYSIS
A recommended definition of electrical failure is a 20% increase in daisy-chain net resistance; however, a lower or higher threshold may be more appropriate, depending upon test equipment capability and specific daisy-chain design scheme. The clear goal of failure analysis is the ability to detect the location, mode and mechanism for the observed electrical failure. Failure analysis should verify that detected failures or resistance increases are not due to associated cabling, connectors, testboard or test apparatus. For bend tests stopped without electrical failure, failure analysis should be performed to insure that failures were not missed due to errors in daisy-chain design or test hardware. Non-destructive failure analysis tools that may be used include x-ray, coupled scanning acoustic microscopy (CSAM), and side view optical microscopy. Common methods and tools during destructive failure analysis include cross section, dye-and-pry, x-ray, CSAM, scanning 7
IPC/JEDEC-9702
electron microscope (SEM) and energy dispersive x-ray (EDX). The mechanical failure mode(s) of each component should be identified. Each observed failure mode shall be documented using cross-section (or other suitable analysis tech-
June 2004
nique) of one representative solder joint or lead, at a minmum. Example failure modes for solder ball array style packages are illustrated in Figure 9-1. Failure modes for leaded style packages include lead cracking, package body cracking, and cracking between the various lead, IMC, solder and PWB metal pad interfaces.
IPC/JEDEC-9702-9-1
Figure 9-1
8
Interconnect Fracture Modes (Solder Ball Array Devices)
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ANNEX A (Informative) - Example Universal Tester Configurations This annex provides example universal tester configurations that satisfy the four-point bend test requirements of Table 8-3, using Equation 2. The example configurations shown in Figures A.1 - A.3 represent a non-exhaustive summary of the possible options that satisfy this guideline’s requirements.
IPC/JEDEC-9702-a1
Figure A.1
Example Configuration (PWB Thickness = 1.00 mm)
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IPC/JEDEC-9702-a2
Figure A.2
10
Example Configuration (PWB Thickness = 1.55 mm)
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IPC/JEDEC-9702-a3
Figure A.3
Example Configuration (PWB Thickness = 2.35 mm)
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ANNEX B (Informative) Test Report Recommendations A test report including comprehensive documentation of the bend test is recommended (see Tables B.1 - B.3). Disclosure of the test report contents will depend on specific customer/supplier agreements. Table B.1
Test Report Recommendations (Equipment & Materials)
Category
Description
Equipment
Manufacturer, model number and operational conditions for the following: • universal tester • strain measurement equipment • continuity monitoring equipment
Four-point bend test fixture
• load span • support span • anvil/roller radius • anvil/roller length
Component
• package outline drawing or reference to JEDEC outline • die dimensions (width, length and thickness) and orientation (rectangular die) • daisy-chain connection map and/or net list • measured solder ball or lead coplanarity • solder ball shear values or lead pull strength, and associated failure modes (parts from same production lot as tested devices) • solder-wetted pad dimensions, if applicable • solder ball land pad type, if applicable (solder mask defined, etc.) • lead finish/pad metallization, including thicknesses of all layers and composition of solder, if applicable
Test board
• width, length and thickness • dielectric material • surface finish • external trace, pad and solder resist opening dimensions • measured board coplanarity
Strain gage
• manufacturer and part number • resistance • strain gage element size Table B.2
Test Report Recommendations (Board Assembly)
Category
Board assembly
Description
• preheat temperature, ramp rate, critical peak temperatures (solder, package surface, board, etc.) duration above solder liquidus temperature and cooling rate • solder composition • solder paste metal percentage, particle mesh size type and flux type • reflow atmosphere • nominal solder paste volume • nominal solder joint geometry • component/PWB storage and/or bake-out conditions prior to board assembly • storage conditions and duration following board assembly Table B.3
Test Report Recommendations (Test Results)
Category
Description
Set-up data
• strain rate vs. crosshead speed* • strain vs. crosshead travel distance* • force vs. crosshead travel distance
Strain data (each test board)
• strain vs. time* • strain-rate vs. time* • strain vs. strain-rate* • force vs. time
Resistance data (each test board)
• resistance vs. time
Failure distribution
• cumulative failure percentage vs. strain (2-parameter Weibull )
Failure mode
• failure mode histogram (all test packages) • time-zero cross-section of a single pkg/board test assembly • failure analysis of representative sample of each observed failure mode
* Note: Measurements at each strain gage location should be reported.
12
ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES ®
Standard Improvement Form The purpose of this form is to provide the Technical Committee of IPC with input from the industry regarding usage of the subject standard.
Individuals or companies are invited to submit comments to IPC. All comments will be collected and dispersed to the appropriate committee(s).
IPC/JEDEC-9702 If you can provide input, please complete this form and return to: IPC 2215 Sanders Road Northbrook, IL 60062-6135 Fax 847 509.9798 E-mail:
[email protected]
1. I recommend changes to the following: Requirement, paragraph number Test Method number
, paragraph number
The referenced paragraph number has proven to be: Unclear
Too Rigid
In Error
Other
2. Recommendations for correction:
3. Other suggestions for document improvement:
Submitted by: Name
Telephone
Company
E-mail
Address City/State/Zip
Date
