CHAPTER 9 SOLUTIONS 3/13/10
9-1)
0
1 1.83(10)6 rad / s LC
L 1.83 C I L t1 0 r 0.5 s V3 Z0
I 0 Z 0 2.35 s Vs C V (1 cos 0 (t2 t1 )) t3 t 2 r s 0.845 s I0 t2 t1
1 0
1 sin
t1 (t2 t1 ) (t3 t2 ) 5.17 V . 2
V0 Vs f s 9-2)
0
1 1.69(10)6 rad / s LC
L 0.845 C I L t1 0 r 0.083 s Vs Z0
t2 t1
1 0
I 0 Z 0 1.94 s Vs
1 sin
C V (1 cos 0 (t2 t1 )) t3 t 2 r s 8.36 s I0 f max 1/ t3 1/ (0.083 1.94 8.36) s 96.3 kHz t1 t2 t1 t3 t 2 17.9 V 2 for Vo 5V ,
Vo Vs f s
fs
V0 t Vs 1 (t2 t1 ) (t3 t2 ) 2
26.9 kHz
9-3) a ) 0
1 108 LC
L 1 C I L t1 0 r 1.39 ns Vs Z0
I 0 Z 0 32.8 ns Vs C V (1 cos 0 (t2 t1 )) t3 t 2 r s 143.3 ns I0 t2 t1
1 0
1 sin
t1 (t2 t1 ) (t3 t 2 ) 4.77 V . 2 V 36 b) I L , peak I o s 5 41 A. Z0 1
Vo Vs f s
VC , peak 2Vs 72 V . 12 1.89 MHz 4.77
c ) f s 750 kHz
9-4) I L , peak I o
Vs 50 3 9 A. Z 0 8.33 Z0 Z0
0
1 1 C L02 LC
Z0
L L L0 C 1/ L02
L
Z 0 8.33 0.833 H 0 107
C
1 12 nF L02
t1
I 0 Lr 50 ns Vs
1 1 I 0 Z 0 sin 366 ns 0 Vs C V (1 cos 0 (t2 t1 )) t3 t 2 r s 373 ns I0 t2 t1
fs
Vo t Vs 1 (t2 t1 ) (t3 t2 ) 2
945 kHz
9-5) For I o 0.5 A. f 0 503 kHz t1 0.05 s t2 t1 1.04 s t3 t 2 3.97 s fs
Vo t Vs 1 (t2 t1 ) (t3 t2 ) 2
99.2 kHz
For I o 3 a. t1 0.30 s t2 t1 1.388 s t3 t 2 0.439 s fs
Vo t Vs 1 (t2 t1 ) (t3 t2 ) 2
253 kHz
99.2 kHz f s 253 kHz 9-6) V 15 RL 5 2; o 0.5 Z 0 2.5 Vs 30 From Fig . 9 1g ,
0
fs 2 (200)(10)3 0.27 0 s 4.65(10) 6 rad / s f0 0.27 0.27
1 1 LC 2 0 LC
L L Z 02C C 1 1 1 LC Z 02C 2 2 C 0.086 F 0 Z 0 0 (2.5)(4.65)(10)6
Z0
L
1 0.538 H 02C
9-7) a) The circuit is shown with diode D2 added to make the switch unidirectional.
20 V(C) Average voltage (6.6839u,5.1605) I(L)
10
0
-10 0s
2.0us V(D1:2) I(L1)
4.0us V(S1:1)
6.0us 8.0us AVG(V(D1:2)) Time
10.0us
12.0us
(a) The average output (capacitor) voltage is 5.16 V, agreeing with the 5.17 V computed analytically. (b) Peak capacitor voltage= 20 V.; (c) Inductor currents: peak = 10.5 A.; average = 2.59 A.; rms = 4.54 A.
9-8) t Vo Vs 1 f s t3 1 2 1 Vo / Vs 1 15 / 20 fs 182 kHz t3 t1 / 2 1.46(10) 6 0.188(10) 6 9-9)
0
1 1 (10)8 rad / s 8 (10) Lr Cr
Z0
Lr 10 Cr
t1
Vs Cr 2 ns Io
Vs 1 1 sin t1 35.4 ns 0 I o Z 0 LI t3 r o [1 cos 0 (t2 t1 )] t2 134.4 s 0 t2
t Vo Vs 1 f s t3 1 14.7 V . 2 I L, peak I o 10 A. VC , peak Vs I o
L 114.7 V . C
9-10)
0
1 (10)7 rad / s Lr Cr
Z0
Lr 10 Cr
t1
Vs Cr 16.7 ns Io
t2
1 0
t3
Lr I o [1 cos 0 (t2 t1 )] t 2 1.54 s 0
Vs t1 348 ns I o Z 0
1 sin
t Vo Vs 1 f s t3 1 1.17 V . 2 1 Vo / Vs For Vo 2.5, f s 326 kHz. t3 t1 / 2
9-11)
0
1 1.414(10) 7 rad / s Lr Cr
Z0
Lr 7.07 Cr
t1
Vs Cr 12 ns Io
t2
1 0
t3
Lr I o [1 cos 0 (t2 t1 )] t2 1.07 s 0
Vs t1 246 ns I o Z 0
1 sin
t Vo Vs 1 f s t3 1 5.6 V . 2 For I o 8 A., t1 15 ns, t2 252 ns, t3 911 ns fs
1 Vo / Vs 394.1 kHz. t3 t1 / 2
For I o 15 A., t1 8 ns, t2 238 ns, t3 1.48 s f s 645.4 kHz 394.1 kHz f s 645.4 kHz
9-12) VC , peak Vs I o Z 0 Z 0 Z0
Lr Lr Z 02C Cr
0
1 1 Cr Lr02 Lr Cr
VC , peak Vs Io
40 15 6.25 4
Z 1 6.25 Lr 0 3.91 H 2 0 1.6(10)6 Lr0
Lr Z 02Cr Z 02 C
1 0.1 F . Lr02
t1
Vs Cr 0.375 s Io
t2
1 0
t3
Lr I o [1 cos 0 (t2 t1 )] t2 4.62 s Vs
fs
1 Vo / Vs 1 5 /15 150 kHz. t3 t1 / 2 (4.62 0.375 / 2)(10) 6
Io
Vo 15 3 A. RL 5
Vs t1 2.74 s I o Z 0
1 sin
9-13)
V 15 RL 5 0.2; o 0.5 Z 0 25 Vs 30 From Fig . 9 2 g ,
fs f 100 kHz 0.37 f 0 s 270 kHz. f0 0.37 0.37
0 2 f 0 1.70(10)6 rad / s Z0 Cr
1 Lr Cr
Z Lr 25 Lr 0 14.7 H Cr 0 1.70(10)6 Lr 23.5 nF . Z 02
9-14) A suitable circuit is shown. The values of the output filter components L1 and C2 are not critical. The load resistor is chosen to give 10 A. The switch must be open for an interval between t2 and t3; 50 ns is chosen.
400u Energy from source per period (149.500u,-72.676u) 0
SEL>> -400u S(W(V1)) (149.470u,120.125) 100V Capacitor 50V
Output 149.088u,14.578)
0V 149.0us 149.2us 149.4us V(INPUT,D3:2) V(R1:1)
149.6us Time
149.8us
150.0us
Results from Probe for steady-state output: a) Vo ≈ 14.6 V., b) VC,peak= 120 V., c) Integrate instantaneous power, giving 72.7 μJ per period (supplied). 9-15) V1 80 2 113 V . THD
4Vdc Vdc 88.9 V .
V3 V3 (0.05)(113) 5.66 V . V1
V1 113 37.7 V (input to filter ) 3 3 Vo,3 5.66 1 Q 2.47 2 Vi ,3 37.7 0 2 30 1 Q 0 30 1 C 13.4 F . Q0 R For a square wave, V3
L
1 11.8 mH . 02C
VC , peak
V1 V 113 280 V .; I L, peak 1 9.43 A. 0 RC R 12
9-16) V1 100 2 141 V . THD
4Vdc Vdc 111 V .
V3 V3 (0.1)(141) 14.1 V . V1
For a square wave, V3 Vo,3 Vi ,3
14.1 47
V1 141 47 V (input to filter ) 3 3
1 30 0 1 Q2 0 30
C
1 13.9 F . Q0 R
L
1 1.27 mH . 02C
2
Q 1.19
200
100
(10.416m,3.6212) 0
-100
-200 10.0ms V(V1:+)
10.4ms V(OUT)
10.8ms I(R1)
11.2ms
11.6ms
12.0ms
Time
The output file shows that the THD is 10.7%. Increase Q by increasing L, and adjust C accordingly. L=1.4 mH and C=12.6 µF gives THD=9.8%. Switching takes place when load (and switch) current is approximately 3.6 A.
9-17) P
V1,2rma R
V1,rms PR 500(15) 86.6 V .
V1 86.6 2 122.5 V . THD
4Vdc Vdc 96.2 V .
V3 V3 (0.1)(122.5) 12.25 V . V1
V1 122.5 40.8 V (input to filter ) 3 3 Vo,3 12.25 1 Q 1.19 2 Vi ,3 40.8 2 30 0 1 Q 0 30 1 C 17.8 F . Q0 R For a square wave, V3
L
1 5.68 mH . 02C
VC , peak
V1 122.5 146 V . 0 RC (2 500)(15)(17.8)(10) 6
I L, peak
V1 122.5 8.17 A. R 15
200
v(out) V(cap)
100 V(in)
(10.434m,8.1206) I(L)
0
-100
-200 10.0ms V(OUT)
10.4ms V(IN)
10.8ms V(L1:2,C1:2)
11.2ms I(L1) Time
11.6ms
From the output file, THD = 10.8%. From Probe: VC,peak=149 V.; IL,peak=8.12 A. 9-18) 2 839 kHz f3 f 0 Lr Cr
f 0 20
8 RL 8.11 2 s 2 f s 5.65(10)6 Re
X L s Lr 33.9 XC
1 29.5 s Cr
Vo
Vs 2
1
1 1 10 4.38 V . 2 2 2 33.9 29.5 X L X C 1 8.11 Re
12.0ms
9-19) 2 1.33 MHz f s f 0 Lr Cr
f 0 20
8 RL 4.05 2 s 2 f s 9.42(10)6 rad / s. Rs
X L s Lr 11.3 XC
1 8.84 s Cr
V Vo s 2
10.25 V . 2 X L XC Rs 1
1
9-20) Vo 6 0.3 Vs 18
s 1.2 Q 3 from Fig . 9 5d 0 2 (800, 000) 0 s s 4.19(10)6 rad / s 1.2 1.2 1.2 QRL 3(5) Lr 3.58 H 0 4.19(10)6 1 Cr 2 1.59(10) 8 15.9 nF . 0 Lr Let
A PSpice simulation using the circuit of Fig. 9-6(a) gives an output voltage of approximately 5.1 V.
9-21) Vo 18 0.36 Vs 50 Let
s 1.2 Q 2.1 from Fig . 9 5d 0
s s 2 (10)6 5.23(10)6 rad / s 1.2 1.2 1.2 QRL 2.1(9) Lr 3.61 H 0 5.23(10)6 1 Cr 2 10.1 nF . 0 Lr
0
9-22)
Vo 15 0.375 Vs 40 Let
s 1.2 Q 1.9 from Fig . 9 5d 0
s 2 (800, 000) 4.19(10)6 rad / s 1.2 1.2 QRL 1.9(5) Lr 2.27 H 0 4.19(10)6 1 Cr 2 25.1 nF . 0 Lr
0
A PSpice simulation using the circuit of Fig. 9-6a shows a steady-state output voltage of approximately 14.4 V, slightly less than the target value of 15 V. Note that the current in Lr and Cr is not quite sinusoidal.
9-23) Vo 55 0.367 Vs 150 Let
s 1.2 Q 2 from Fig. 9 5d 0
If f s 1 MHz , 0
s 2 1, 000, 000 5.23(10)6 rad / s 1.2 1.2
Lr
QRL 2(20) 7.64 H 0 5.23(10)6
Cr
1 4.77 nF . Lr 2 0
A PSpice simulation using the circuit of Fig. 9-6a shows a steady-state output voltage of approximately 53 V, slightly less than the target value of 55 V. Note that the current in Lr and Cr is not quite sinusoidal.
9-24) RL 2 10 2 12.3 8 8 1 0 2.53(10)6 rad / s Lr Cr Re
0 403 kHz. f s f 0 2 X L s Lr 4.08 1 XC 2.65 s Cr 4Vs Vo 9.60 V . 2 2 X XL 2 1 L X C R e f0
9-25) RL 2 15 2 18.5 8 8 1 0 5.66(10)6 rad / s Lr Cr Re
0 901 kHz. 2 X L s Lr 7.54 1 XC 6.12 s Cr 4Vs Vo 2 X L 2 1 X C f0
f s f0
X L R e
2
25.9
9-26) Vo 20 1.67 Vs 12 Let
f s s 2 500000 1.05 0 s 2.99(10)6 rad / s f 0 0 1.05 1.05
From Fig . 9 10c, Q 3.8 R 15 Lr L 1.32 H 0Q 2.99(10)6 (3.8) Cr
1 84.7 nF Lr 2 0
9-27)
Vo 36 0.8 Vs 45 Let
f s s 2 900000 1.1 0 s 5.14(10)6 rad / s f 0 0 1.1 1.1
From Fig . 9 10c, Q 1.9 R 20 Lr L 2.05 H 0Q 5.14(10)6 (1.9) Cr
1 18.5 nF Lr 2 0
9-28) Vo 60 1.2 Let f s 500 kHz Vs 50 Let
f s s 2 500000 6 1.1 0 s 2.86 10 rad / s f 0 0 1.1 1.1
From Fig . 9 10c, Q 3.4 R 25 Lr L 2.57 H 0Q 2.86(10)6 (3.4) Cr
1 47.6 nF Lr 2 0
9-29) Vs 100 V .; f s 500 kHz; RL 10 ; L 12 H ; Cs C p 12 F
2 2 Re RL (10) 12.3 8 8 s 2 f s 2 500000 3.14(10)6 4Vs Vo 2 Cp s L 1 2 2 1 s LC p Cs Re s ReC s
2
37.7 V .
9-30) Sample solution Vo 5 0.417 Vs 12 Let
f s s 1.2 Q 2.7 from Fig . 9 11c f 0 0
s 2 800000 6 4.19 10 rad / s 1.2 1.2 QRL 2.7(2) L 1.29 H . 0 4.19(10)6 1 Cs C p 2 44.2 nF . 0 L Check with Eq. 9 74 : Vo 4.97 V .
0
9-31) Sample solution Vo V 5 5 0.25; RL o 5 Vs 20 Io 1 Let
f s s 1.2 Q 5 from Fig . 9 11c f 0 0
s 2 750000 3.93(10)6 rad / s 1.2 1.2 QRL 5(5) L 6.37 H . 0 3.93(10)6 1 Cs C p 2 10.2 nF . 0 L Check with Eq. 9 74 : Vo 5.08 V .
0
9-32) Sample solution Vo 10 V 10 0.4; RL o 10 ; Let f s 100 kHz Vs 25 Io 1 Let
f s s 1.15 Q 3.3 from Fig. 9 11c f 0 0
s 2 100000 546 krad / s 1.15 1.15 QRL 3.3(10) L 60.4 H . 0 5.46(10)5 1 Cs C p 2 55.5 nF . 0 L Check with Eq. 9 74 : Vo 10.02 V .
0
Using a circuit based on Fig. 9-11a but with a square-wave source implemented with Vpulse (see Fig. 9-6a), the result is approximately 9.4 V.
9-33) (a) A PSpice simulation using the circuit shown reveals that the capacitor voltage returns to zero at 15.32 μs and the switch must remain closed for 5.58 μs for the inductor current to return to 12 A. Initial conditions for the inductor (12 A) and for the capacitor (0 V) must be applied. Ideal models for the switch and diode are used. b) Using the expression S(W(V1)) for energy (S is integration), 15.7 mJ are supplied by the voltage source in one period. c) Average power is 754 W, obtained by entering AVG(W(V1)). d) Average resistor power is 104 W. e) With R = 0, the capacitor voltage returns to zero at 15.44 μs and the switch must remain closed for 5.45 μs. The source power and energy are not changed significantly.
20
(20.901u,12.000) I(L)
15.318u,16.390m) 0
-20 14.71us 16.00us V(switch) V(cap)
18.00us
20.00us
21.53us
I(L1) Time
200 V(capacitor) 0
SEL>> -200 0s
4us V(SWITCH) V(CAP)
8us I(L1)
12us Time
16us
20us
24us
9-34)
o
1 1 2(10)5 rad / s 6 6 Lr Cr 250(10) 0.1(10)
R 1 2000 2 Lr 2(250)(10) 6
o2 2 0 vC (t ) Vs e t [ Vs cos ot o Lr ( I1 I o ) sin ot ] 75 e 2000 t [ 75cos(2(10)5 t ) 2(10)5 250(10) 6 (7 5)sin(2(10)5 t )] 75 e 2000 t [ 75cos(2(10)5 t ) 100sin(2(10)5 t )] vC (t x ) 0 t x 22.3 s V iL t I o e t ( I1 I o ) cos ot s sin ot o Lr 75 5 e 2000t (7 5(cos(2(10)5 t ) sin(2(10)5 t ) 5 6 2(10) 250(10) 2000 t 5 5 2 cos(2(10) t ) 1.5sin(2(10) t ) 5e iL (t x ) iL (22.3 s ) 3.14 A. t
iL Lr (7 3.14)250(10) 6 12.9 s Vs 75
o
1 1 3.65(10)5 rad / s 6 6 Lr Cr 150(10) 0.05(10)
R 0.5 1667 2 Lr 2(150)(10) 6
9-35)
o2 2 0