Synopsys’ HAPS ® FPGA-Based Prototyping Proto typing Solution Delivering Integrated Physical Prototyping `
Flexible use modes: mo des: Speed DUT review, system validation, early software development and regression testing
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Best of class reliability for maximum up-time and ROI
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Capacity range 4 million to 1.6 billion ASIC gates
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Support localized or enterprise-wide project deployments
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Up to 300 MHz system clock performance
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Wide catalog of I/O interfaces including gigabit PHYs
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Fast bring-up time – two week average for an 8-FPGA system
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Debug across FPGAs with gigabytes of integrated storage
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Easy to use API and host connectivity of up to 400MB/s
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Compatible with DesignWare Desig nWare® IP Prototyping Kits
Overview Next-generation consumer, wireless, and industrial products will rely on sophisticated semiconductors and software to deliver maximum utility, ease of use, and a power-performance profile tailored for their target market. In the near future a wave of innovative network-connected IoT products will integrate environmental sensors and rigorous security methods to provide more responsive technology while protecting user privacy. Physical prototypes for ASIC IP and SoC design are the most reliable and affordable way to confirm that new designs are compliant with a particular specification or standard but also satisfy customer needs. Synopsys’ HAPS® (High-Performance ASIC Prototyping System) Series of FPGA-based prototyping systems has been designed to deliver maximum system performance, and easy integration with physical interfaces. The HAPS Series unique fus ion of hardware, automation tools, and connectivity has resulted in it being chosen most often by design teams around the world and made it the market share leader in ASIC prototyping. The system’s scalability allows it to address block-level verification tasks up to full SoC integration prototyping scenarios with software stack execution. The latest HAPS Series, the HAPS-80, is the 4th generation of physical prototyping products by Synopsys. It incorporates the latest, high-capacity FPGAs tailored for ASIC prototyping, equipment modularity so that dozens of FPGAs to be joined reliably, and management tools to ma ke remote access and administration of systems as easy as possible. FPGA-based prototypes are known for delivering high-speed with a minimum of equipment. The combination of HAPS-80 systems and HAPS ProtoCompiler raises the benchmark in this category with proprietary high-speed time-domain multiplexing (HSTDM) and multi-gigabit time-domain multiplexing (MGTDM) technology that delivers maximum multi-FPGA performance with a minimum of devices. HAPS ProtoCompiler automatically selects the optimum mix of pin-multiplexing schemes to best match the design under test (DUT) timing objectives. HAPS-80 delivers performance of up to 300 MHz for single FPGA, global synchronous performance of 100 MHz for multiple FPGAs without chip-to-chip pin-sharing, and up to 30 MHz for multi-FPGA scenarios that do require pin-sharing. The increased system performance of the HAPS-80 systems enables OS booting to probe and initialize device hardware such as CPU, timers, UARTs and reach the command prompt in les s than a minute, increased regression execution throughput and at-speed operation of real world I/O. The new, highly scalable prototyping systems take advantage of the latest generation Xilinx UltraScal e VU440 FPGA devices to support a wide range of design sizes, from IP to systems-on-chip (SoCs) in excess of 1.6 billion ASIC gates.
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Reliability
A combination of extensive testing and strict product release criteria helps ensure that HAPS users enjoy the benefits of high availability, reliability, and functional consistency across units. Hardware characterization conducted by Synopsys includes application tests of i nterconnect cables, HapsTrak ® standard daughter boards, FPGA modules, and power supply modules. An integrated HAPS system supervisor provides real time power and temperature monitoring and system shut-down execution if a voltage or thermal excursion occurs. The supervisor manages boot sequencing, clock synchronization, and chaining of multiple FPGA modules. To maximize uptime and help avoid incorrect system assembly due to misplaced daughter boards and cabling, the HAPS system includes integrity checking utilities that will validate that a physical system matches the software model of the prototype design and that prototyping utility IP, like signal multiplexing between FPGA I/Os, introduced by the design flow, is electrically stable and passes data payload correctly. Each HAPS system shipped to an end-user site includes a HAPS System Production Test Certificate that provides a summary of the test results for the system assembly. To ensure a high standard of reliability and quality every HAPS system must pass the release criteria described by this document or else the system will not be released to an end-user. Each test certificate includes a serial number for the composite system and then a list of sub-system modules that are integrated. Each module will also have a serial number designation which allows Synopsys to trace and monitor production logistics, repair, and replacement of equipment under warranty service agreements. Flexibility for IP and SoC Prototyping
The HAPS Series is desig ned to provide an easy migration path for single-FPGA IP module to be integrated into a system of multi-FPGA SoC modules maximizing prototype reuse across engineering teams. The system enables a bottom-up ASIC-like design flow for high-capacity FPGA-based prototypes by allowing the project constraints and optimization options of a lower capacity HAPS system to be reused in the context of a higher capacity target. This modular approach is enabled by the mechanical symmetry of the PCB and connector layout of the HAPS system and project flows automated by HAPS ProtoCompiler. In both IP and SoC usage modes, the solution delivers unparalleled performance, ease of use, debug visibility, and system control. The HAPS-80, HAPS-70, and HAPS-DX Series are interoperable and compatible with HapsTrak 3/MGB accessory equipment to support assembly of multiple prototype projects.
Synopsys’ HAPS FPGA-Based Prototyping Solution
Independent IP Validation HAPS-DX
Integrated IP Validation
Example SoC Design 690T
MIPI
HAPS-80 S52
Graphics
VU440
HAPS-DX
Display
L1
MIPI
Display
Processor
L1
HDMI
L2 690T
Video
ICT SD controller
Sensor Peripherals processor
SIM card controller
Sensor processor
Audio processor
IP interface
HDMI
Memory controller
USB
Video
Power and clocks
VU440
HAPS-70 S12 USB
SoC
2000T
IP Interface
Figure 1: HAPS symmetrical system architecture for protot ype reuse enabled by HAPS ProtoCompiler
Worry-Free Setup
The HAPS System Configuration Soft ware provides GUI and command line access to the directly query and control the system configuration of a live system. Configuration projects may be applied from a host workstation or the on-system Flash memory device. The HAPS-80 Series offers a client/server model for remote access and control.
System Assembly and Data Integrity Checking
To ease the system bring-up phase and help ensure hassle free, stable and reliable operation the HAPS Series setup utilities provide a variety of assembly and integrity checks. `
Graphical user interface for ease of use and Tcl interface for scriptable configuration
` Automated
handling of clock and reset distribution
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Ensure cables, daughter boards, and system configuration setup match the prototyping design floorplan
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System performance analyzer profiles the physical connections on the system ensuring the desired cable connector or HSTDM connection performance is met.
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Real time data integrity checks of HSTDM links
HAPS ProtoCompiler
HAPS-80
HAPS-70
HAPS-DX
Synopsys HAPS ® Series
Figure 2: HAPS system configuration software Figure 3: HAPS ProtoCompiler
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Synopsys’ HAPS FPGA-Based Prototyping Solution
HAPS-80 Enterprise Support
HAPS-80’s native Ethernet connection enables global system accessibility via connection to a standard Ethernet hub with no additional hardware. In addition, HAPS-80 and HAPS ProtoCompiler support multi-design mode to enable execution of multiple designs simultaneously across HAPS systems, delivering the highest utilization of the prototype server farm and greater return on investment from multiple project usage. `
Client/Server system configuration software
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Remote access
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Multi-design
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Job queue
Figure 4: HAPS rack mount installation
Figure 5: HAPS-80 Series equipment portfolio
HAPS-80 Series
Number of FPGAs ASIC Ga te Capac ity I/O Connectors Ha psTrak 3 User Accessible I/O Resources High Speed I/O Transceivers FPGA Type
HAPS-80 S26 1-FPGA System
HAPS-80 S52 2-FPGA System
HAPS-80 S104 4-FPGA System
Custom Configurations
1
2
4
Up to 64
26 million
52 million
104 million
Up to 1.6 billion
24
48
96
Up to 1,536
1084
2465
5086
>81376
16
52
100
>1600
Virtex UltraSca le VU440 FLGA2892: ` 4,433K logic cells or ~26 million ASIC gates of capacity ` 88.6 Mbit of block RAM ` 2,880 DSP slices ` 6 PCI Express ® blocks ` 3 100G Ethernet resources ` 48 GTH 16 Gb/s transceivers ` 1,456 I/O pins ` I/O voltage support, High-performance (HP) I/O: 1.0V to 1.8V, High-range (HR): 1.2V to 3.3V
Routing Granularity
52 I/Os per connector
Clock Resources
2 PLLs, 2 external PLL inputs, 2x2 external PLL outputs, 2x6 clock input and outputs, frequency ranges: 0.16 - 350 MHz, 367 – 473.33 MHz, and 550 – 710 MHz, clock stopping support
Debug Storage Options
On-chip BRAM storage, on-FPGA module SDRAM, external SDRAM, or logic analyzer
Host Interface Option
USB or PCIe-over-cable UMRBus API
System Control Software
HAPS system configuration software
Configuration
Ethernet, JTAG, USB 2.0, SD card, UMRBus via Configuration and Data Exchange (CDE) interface
Encryption Key
Battery backup support
Power
110-240 AC, 12V
Compatibility
HAPS-70, HAPS-DX, DesignWare IP Prototyping Kits
HapsTrak 3 Daughter Boards
Breakout Board, LPDDR3, DDR3 SDRAM, DDR4 SDRAM, FMC Adapter, GPIO, HapsTrak II Adapter (Mobile SDRAM, NOR Flash PROM), Lab Board, Logic Analyzer Interface, SRAM
4HapsTrak MGB Daughter Boards
10/100/1000 Gigabit Ethernet, Serial ATA, PCI Express Gen 2/3, QSFP+ Synopsys’ HAPS FPGA-Based Prototyping Solution
About the HA PS-8 0 Series
The HAPS-80 Series integrates the Xilin x Virtex UltraScale VU440 device into its FPGA Module. This is the 6th generation of Xilinx FPGA devices that Synopsys has applied for ASIC prototyping solutions.
Multi-Gigabit SERDES PHY Interfaces
The HapsTrak Multi-Gigabit (MGB) interface connec tor provides access to the Virtex UltraScale GTH transceivers. It is a multigigabit capable electro-mechanical landing for a wide variety of accessory daughterboards.
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1, 2, or 4 FPGA module configurations
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Serial ATA
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Chain up to 64 FPGAs
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Gen 2/3 PCI Express
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10/100/1000 Gigabit Ethernet
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QSFP+ (SFP+ CX4, 40G/10G Ethernet)
` ASIC
gate capacity 26M to 1.6B
` VU440
GTH Transceivers at HapsTrak MGB connectors
` VU440
SelectIO at HapsTrak 3 connectors
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Use HapsTrak 3 for PHYs or chip-to-chip interconnect
The VU440 devices deliver a 2.2x increase in device density and 21 percent more I/O, which are ideally suited for multi-FPGA partitioning of complex SoCs prototyped with HAPS systems. The HAPS-80 is ideal for RTL review, system validation, and early software development. This is accomplished by an integrated system of soft ware, firmware, and hardware that is unmatched in the industry. In order to confirm operation of equipment compatibility in the validation role, Synopsys HAPS provides a deep catalog of HAPS Accessory daughter boards to interface to the physical world. Figure 7: PCIe HapsTrak MGB
>1Gbit PHY Interfaces
The HapsTrak 3 interface connector provides access to the Virtex UltraScale Sel ectIO. It is a >1Gbit capable ele ctro-mechanical landing for a wide variety of accessory daughterboards and chipto-chip connector cables. `
4GB/8GB DDR3 SDRAM
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Mobile SDRAM
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NOR Flash PROM
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SRAM, Flash, LPC/HPC FMC Adapter
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Prototyping Lab Board
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Logic Analyzer Connectorless Probe Interface
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GPIO (ARM Cortex Debug, Micro-USB, LCD)
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Basic I/O (LED & Push Buttons)
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FPGA Mezzanine Card (FMC) Adapter
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Chip-to-Chip Connector Cables
Figure 8: QSFP+ HapsTrak MGB
Synopsys SolvNet website provides hardware reference guidelines and example designs for each HapsTrak family daug hter board to ease integration and creation of prototyping scenarios. HAPS Connect Program
The HAPS Connect Program expands the choice of HapsTrak and HapsTrak MGB board design and service offerings available for HAPS systems. The program helps customers to:
Figure 6: GPIO HapsTrak 3
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Develop HAPS prototypes faster by leveraging compatible daughter boards from leading industry hardware vendors
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Reduce project risk by taking advantage of hardware and services from vendors with HAPS system expertise
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Save on prototype development costs and resources by using products and services tailored for HAPS systems
Visit Synopsys.com for a listing of current HAPS Connect Program members.
Synopsys’ HAPS FPGA-Based Prototyping Solution
FPGA Mezzanine Card (FMC) Support FMC is an ANSI standard that provides a standard mezzanine card form factor, connectors, and modular interface to an FPGA located on a carrier board like the HAPS Series FPGA module. Decoupling the I/O interfaces from the FPGA simplifies I/O interface module design while maximizing reuse of the prototype. FMC was developed by a consortium of companies ranging from FPGA vendors to end users. Key benefits of FMC include: `
Data throughput: Individual signaling speeds up to 10 Gb/s*
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Latency: Elimination of protocol overhead removes latency and ensures deterministic data delivery
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Design simplicity: Expertise in protocol standards is not required
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System overhead: Simplifying the system design reduces power consumption and material cost
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Design reuse: Promotes the ability to retarget carrier cards to new I/O
The Synopsys HapsTrak 3 to FMC adapter daughter boards allow FMC-standard boards to connect to the HAPS Series system to ADC/DAC devices from a variety of vendors including 4DSP, Analog Devices, and BittWare. Each adapter provides the interface to a High Pin Count (HPC) connector. Synopsys maintains an FMC Compatibility List at solvnet.synopsys.com. * Supported on HAPS-DX systems
About Synopsys DesignWare IP Prototyping Kits The interoperability of Syno psys HAPS extends to the DesignWare® IP Prototyping Kits available for a variety of popular interface IP including: USB, PCI Express, and DDR. DesignWare IP Prototyping Kits provide complete, out-of-the-box reference designs that consists of a validated IP configuration and necessary SoC integration logic such as clock, reset, power management, and test logic for a specific IP protocol, implemented on a HAPS-DX Series system. All kits include reference drivers, SoC integration logic, and application examples. With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. Synopsys offers support to merge multiple DesignWare IP’s into a subsystem with a HAPS-80 system as the integration point allowing teams to incorporate other major IP blocks with your proprietary design elements.
HAPS Series Comparison Table Feature ASIC Ga te Capac ity FPGA Modularity
HAPS-DX
HAPS-70
HAPS-80
4M
12M to 288M
26M to 1.6B
Virtex 7 690T
Virtex 7 2000T
Virtex UltraSca le VU440
Single
1 to 24 FPGAs
1 to 64+ FPGAs
HapsTrak 3 a nd HapsTrak MGB
Connector Standard
BRAM (Mbit) or SDRAM (GB)
Debug Storage
External PC
Network Interface Controller High-Speed TDM
6
n/a
Integrated SBC Differential
Single, Differential and Multi-Gigabit TDM
Synopsys’ HAPS FPGA-Based Prototyping Solution
HAPS UMRBus for Workstation Connectivity
Software Application(s) (host workstation)
The conventional usage of the FPGA-based prototype has been as a stand-alone, isolated system. Any data links to a workstation have been relegated to programming the FPGA devices via JTAG or in case s where an embedded CPU is included a JTAG debug port allows the embedded software debug environment to communicate with the prototype for memory monitoring and source code debug. JTAG is an excellent vehicle for occasional data access and is pervasive throughout the industry but it was not designed for high-bandwidth communication. Synopsys Universal Multi Resource Bus (UMRBus) solves the bandwidth and reliability problem with options for USB or PCIe physical connection and a robust API for software-driven communication with the physical prototype. `
Up to 400MB/s host connection to DUT
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C/C++/Tcl API for HAPS
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USB or PCIe host connection
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Optional AXI, AHB, APB protocol interface up to 130MB/s
The Synopsys UMRBus for the HAPS Series provides the hardware infrastructure, OS device drivers, and various APIs for configuration and data exchange with a Synopsys FPGA-based prototype. To maximize the versatility and application in a variety of roles the UMRBus was designed as a multi-point interface. The HAPS family supports 63 independently addressable interfaces per UMRBus chain. This deep hardware capacity allows the communication system to access various regions of the ASIC/ SoC design and commit a communication channel for a particular application of the bus. OS-specific APIs consist of functions for a host application to access client applications of the prototype.
User app 1
User app 2
User app N
Host application interface module
Host application interface
Software interface module
UMRBus communication
Hardware interface module
UMRBus
UMRBus
CAPIM
CAPIM
CAPIM
DUT part1
DUT part2
DUT part3
HAPS Series
Figure 9: User app-to-prototype communication
UMRBus connectivity to HAPS can be accomplished via USB 2.0 cable, PCIe-over-cable, or via Dire ct PCIe using HapsTrak MGB interface accessories depending on the interface speed required. Physical connection options for UMRBus include: `
UMRBus over USB: Up to 25MB/s transfer rate
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UMRBus Interface Kit: Up to 80MB/s transfer rate
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UMRBus Direct over PCIe: Over 400MB/s transfer rate
The Synopsys’ UMRBus host connectivity enabl es hybrid prototyping, global accessibility and prototype server farm use modes. The UMRBus provides the infrastructure for a seamless link between HAPS systems and Synopsys’ Virtualizer-based virtual prototypes to create an integrated hybrid prototyping environment for early software development and hardware/ software integration.
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Synopsys’ HAPS FPGA-Based Prototyping Solution
Popular Synopsys HAPS Series Use Models Speed-Up DUT Review The HAPS Series deliver s multi-megahert z operation to help speed the review of RTL blocks that require high-volumes of test patterns to confirm operation. There are two popular use models, one with me mory pre-load/readback of HapsTrak 3 memory daughter boards or direct streaming from the host workstation. The HAPS UMRBus supports both scenarios with a stable and high-performance physical link and APIs to ease integration between a host workstation and a HAPS system via a USB or PCIe connection. For DUT testing, preload and readback of on-board DDR3 SDRAM with test and result data is ideal for review of media codecs. The Synopsys SolvNet Catalog of HAPS Design Examples includes DUT test jigs that integrate DDR3 memory interface controller for the HapsTrak 3 8GB memory module. The UMRBus A PI for Tcl/C/C++ makes adoption into your test environment easy and HAPS’ superior modularity and reusability allows you to focus on new design and verification tasks instead of developing custom test equipment.
Host PC
PCIe or USB
S y n c r o n i z e r
S y n c r o n i z e r
DDR3
Syncronizer
Test jig DUT DUT
Accelerate PHY-to-Controller Integration and Driver Development With a wide variety of physical interfaces the HAPS Series serves as a platform to validate PHY-to-controller integration and software driver development target. Interface controller design for state-of-the-art interface standards like USB, PCIe, and SATA will often require tailoring for end-markets or special characteristics of the ASIC like low-power. Integration logic such as clock, reset, power management must also be accounted for in the testing. With up to 4 million ASIC gates of capacity and over 100 MHz clock speed the lowest capacity HAPS-DX system supports many PHY-to-controller prototyping scenarios within a single FPGA and makes early software bring-up feasible. The HapsTrak 3 and HapsTrak MGB daughter board catalog for the HAPS Series include the latest generation of DDR3/DDR4 SDRAM, SRAM, Flash memories, adapters for popular GPIO standards, Serial ATA, Gen 2/3 PCIe, and Gigabit Ethernet. HAPS users employ a variety of CPU hosting options to connect and control interface controllers including physical test chips, vendor evaluation boards, RTL, or even virtual SystemC/TLM implementations of popular CPUs.
1- n FPGAs
Memory
CPU
On-chip bus
Interface controller
Interface
Control & test
Interface PHY
Analog I/F
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Synopsys’ HAPS FPGA-Based Prototyping Solution
Highest Performance At the Lowest Cost Graphics applications using GPUs are found today in a variety of markets including broadcast, medical imaging, CAD/CAM, and entertainment. Tailoring a GPU design for a particular market will entail review of the quality of rendering, texture mapping, and special effects by a 2D/3D application. A high-performance FPGA-based prototype running at multiple megahertz makes imaging review quicker by providing high-capacity memory storage of test data along with a high-performance interface to a host workstation for control and data I/O. The HAPS Series in combination with HAPS ProtoCompiler is uniquely able to achieve high-performance with a minimum of FPGAs in order to keep prototype cost down. Because the RTL for large complex processing units like GPUs and Application Processors often exhibit highly interconnected architectures with thousands of signals woven between functional blocks, the partition algorithms for the prototype must account for both interconnect density and critical path delay to arrive at a feasible fit that will also provide maximum performance. The HAPS system employs proprietary high-speed time domain multiplexing fully integrated with the automated system routing feature and a comprehensive static timing analysis reporting that accounts for both post-route results of individual FPGAs and interconnect delay for a complete view of the system.
HAPS-80 Regression Farms Traditionally FPGA-based prototypes have not easily accommodated multiple independent designs to be hosted by a multi-FPGA PCB and then further sharing that board among several remote users. And those that have required extensive scripting to avoid resource conflicts and monitor run-time status. Prototypes tended to be physically distributed and inexpensive enough to be replicated for software development tasks. However as the scale of IP and SoC prototyping projects have grown so to has the cost and expense of multi-FPGA systems. To help maximize uptime and reduce deployment costs, ASIC prototypes are now often integrated as a shared IT resource and monitored like maximum up-time and utilization like other data center equipment.
Multi-d esign
S hare d usage
IP Subsystem SoC
In order to maximize the ROI and regression throughput the HAPS-80 incorporates sharing and management features to support both multi-design and remote shared usage scenarios. HAPS features allow multiple independent designs to be programmed onto a multi-FPGA system. This helps HAPS users to avoid idle FPGAs and maximize utilization of multi-FPGA systems and a more parallel work flow. Integrated Ethernet interface and a runtime management server allow remote clients to attach to the system to assign and run designs to one or more FPGAs. This allows runtime scenarios for individual IP blocks, subsystems, or full SoC designs to be run concurrently. HAPS ProtoCompiler’s ability to target a large design across a variety of HAPS Series systems maximizes the usage of current equipment while next generation systems can be integrated incrementally.
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Synopsys’ HAPS FPGA-Based Prototyping Solution
Enable Maximum Productivity
HAPS ProtoCompiler prototyping tool allows you to manage prototype board resources, enable debug, partition logic, and synthesize. High capacity, timing-driven partition and systemroute engines quickly solve the most difficult partition problems while optimizing for the fastest system clock performance. Logic synthesis for HAPS provides dedicated HDL compilers and optimization tuned to your objective whether it is the shortest bring-up time to highest system performance. Reuse is a best-practice not only for ASIC design but for prototypes as well. The modular nature of the HAPS hardware architecture coupled with the incremental and hierarchical project management features of HAPS ProtoCompiler accelerates bringup time by avoiding lengthy re-compile and place-and-route cycles. Prototype projects developed for HAPS-DX or HAPS-70 Series systems are directly compatible with the HAPS-80 and allow the prototyping team to integrate individual ASIC block or IP prototype projects into larger subsystems for full SoC validation scenarios.
The HAPS ProtoCompiler system awareness delivers an integrated flow which is easy to use and automates SoC RTL to FPGA-based prototype bring-up. Key features address the needs of the FPGA-based prototyping engineer including system definition of the target resources (FPGAs, memories, connectors, and other physical interfaces), ASIC clock conversion, design planning across multiple FPGAs, eliminating I/O congestion between FPGAs, library and IP conversion, FPGA implementation, and system-level static timing analysis. With its HAPS system awareness, HAPS ProtoCompiler is able to automate many of the steps that traditionally had to be completed manually. A high capacity, constraint-driven, partition engine solves the most difficult partition problems for ASIC designs that require multiple FPGAs to prototype. HAPS ProtoCompiler is able to generate a solution for a 100 million ASIC gate design in under 10 minutes. Debug Environment
HAPS ProtoCompiler
Static timing analysis across multiple FPGAs, interconnect, and pin-multiplexing methods provide an accurate view of performance prior to FPGA implementation. Design Environment
The automation features of HAPS ProtoCompiler help maximize your productivity and create prototypes with the best system performance. `
Less than 3 week typical bring-up of 8 FPGA projects
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Synopsys VCS compatible file/library scan
`
Constraint-driven partitioner
` Automatic
time-domain multiplexing of system routes
` Timing-driven `
Best of class logic synthesis with gated clock conversion
` Xilinx `
route of chip-to-chip connections
Vivado automation
HDL source
Timing constraints
RTL Compile
Pre-Partition Reports
Partition constraints
Target system specification Routing constraints
Partition
System route
Synthesis, place and route scripts
System generate
Pre-map 1
2
n
Map 1
2
n
Vivado P&R 1
2
n
Multi-FPGA system-level static timing analysis
Figure 10: Full ASIC design automation for HAPS
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Synopsys’ HAPS FPGA-Based Prototyping Solution
The debug and troubleshooting of FPGA-based prototypes has evolved from using external test equipment to fully integrated instrumentation and high-capacity storage with the ability to correlate signal-level events back to RT-level for troubleshooting. The HAPS ProtoCompiler’s debug features provide an array of debug capabilities which can be deployed at any stage of the ASIC prototyping project ensuring that the source of a design bug can be located as fast as possible. `
Simulator-like RTL instrumentation and debug
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Runtime debug trigger and sample controls
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Synopsys Formality compatible for logic equivalency checks
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Synopsys Verdi/Siloti compatible via FSDB
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Storage options: BRAM, DDR3, or a Logic Analyzer
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Seamless signal visibility across multiple FPGAs
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Up to 8 GB of sample storage
HAPS-80 systems deliver the latest generation of high-speed, nonintrusive, deep trace debugging features, HAPS DTD4. HAPS DTD4 has the ability to capture over 1,000 debug signal bits per FPGA and store results to on-board SDRAM resources without any HapsTrak connector consu mption. This non-invasive scheme allows for instrumentation changes far easier to implement since debug interconnect is independent of user I/O joining FPGAs. Debug storage memory, debug data acquisition logic, and dedicated debug routes are built into the HAPS-80 systems and are automatically deployed using HAPS ProtoCompiler to ensure that instrumentation and sample storage is readily available and has minimal impact on resource consumption. HAPS DTD4, in combination with Synopsys Verdi™ debug software, helps designers rapidly visualize complex design behavior in the context of the original RTL source for a simulator-like experience, reducing debug time by up to 50 percent. In addition, the HAPS prototyping integration with the Synopsys Verification Continuum’s Unified Compile technology enables seamless transition between Synopsys VCS, ZeBu and HAPS to save months of design time.
Built-in debug data storage
HAPS-80 S104
Debug hub
Set D
Set C
Set A
Set B
Debug chain
Figure 11: HAPS DTD4 integrated debug chains multiple FPGAs
Platform and System Support
HAPS ProtoCompiler design-in tools support 64-bit Linux operating systems. The runtime tools support 64-bit Windows 7 and Linux operating systems. HAPS ProtoCompiler supports HAPS-80, HAPS-70, and HAPS-DX Series systems. New HAPS Series systems are supported as they become available.
The creation of user defined bus monitors and protocol checkers is simplified by leveraging the automated flow, non-intrusive and zero pin overhead of the Universal Multi-Resource Bus (UMRBus) Client Application Interface Modules (CAPIMs). These UMRBus RTL building block modules provide the basis of user defined debug to stimulate and monitor modules that enable the user to interact with a HAPS system through the provided UMRBus application programming interface (API). This API enables design interaction via simple TCL or the building of more complex analysis tools via the C++ documented interface.
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Synopsys’ HAPS FPGA-Based Prototyping Solution
Report navigator provides easy access to result and analysis reports Design database processing with easy task navigation Visualize RTL and IP des ign hierarchy and interconnect
Design database view shows each major process stage and makes output variations easy Tcl Console: scripting environment for project automation
Figure 12: HAPS ProtoCompiler User Interface
RTL source view: Allows you to easily instrument RTL elements and view live hardware state Design hierarchy view: Allows selection of context for RTL source code view
Tcl Console: scripting environment for debug project automation
Figure 13: Debugger GUI allows you to quickly navigate t hrough your design and to deb ug the RTL source code
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Synopsys’ HAPS FPGA-Based Prototyping Solution
HAPS ProtoCompiler Features
Benefits
Prototype Logic Synthesis Industry-leading HDL support
Take advantage of the latest language features in Verilog, SystemVerilog, VHDL and VHDL-2008.
Automat ic infe rence of memor ies and D SP
High quality of results.
Automat ic fini te stat e machi ne extr acti on
Ensures optimal implementation of state machines.
Automat ic comp ile po ints fo r multiprocessing
Automatically par titions design for multip rocessing with mul ticore computing pl atforms.
Unified Power Format (UPF) support
Automatic inference of system state and power island s.
Continue-on-error
Reduces iterations required for board bring-up by identifying multiple errors in one synthesis run.
Automat ic gate d/gene rated c lock conversion
Easier implementation of the ASIC design in an FPGA. Automatically convert gated clocks into FPGA clock for efficient implementation in flat or block-based flows.
DesignWare Library support
Easy ASIC code migration into an FPGA for prototyping.
Fast synthesis mode
Rapid analysis and reporting to reduce RTL/IP migration time.
Fast diagnostic compiler
Quickly trap and isolate HDL code problems that delay bring-up.
Time-to-First-Prototype (TTFP) compiler
Optimized compiler to reduce prototype bring-up time.
FPGA project encapsulation
Post-partition results with per FPGA project creation.
Multi-threading with Automated Compile Points (ACP)
Fast FPGA synthesis support for multicore processor workstations - 4 per license.
Multi-processing over a network
Fast FPGA synthesis support for multi-processor/node network resources - 4 per license.
System Planning HDL Analyst
Quickly analyze RTL code, identify critical paths and cross-probe to HDL source.
Prototype hardware planning for non-FPGA resources (i.e. memory, traces, etc.)
Manage connectivity and target logic to non-FPGA HAPS hardware resources.
Modular and incremental project build
Assemble subsystems or full SoC valid ation scenario s based on individu al HAPS prototype projects of individual ASIC blocks. Incremental builds avoid long synthesis and place and route processes.
Constraint-driven, multi-FPGA partition engine
Rapidly solves the toughest partition problems.
Automat ic hig h-spe ed pin m ulti plexin g
Produces the highest performance prototype.
System level timing analysis
Quickly assess clock and I/O performance to characterize prototype target performance.
Debug and Bring-Up Instrument design in RTL source code
Ability to select sig nals and code branc hes for sampling and /or triggering easily and qu ickly.
Debug design in RTL source code
Rapid debug of results and the ability to get useful data with less debug logic for heavily utilized FPGAs.
Implement state machine style triggers
Useful for creating complex triggering conditions.
Data exchange with Synopsys Verdi and Siloti
Quickly import verification views and apply root cause analysis.
Logic equivalency checks with Synopsys Formality
Confirm logic equivalence between original RTL and design post-processed for prototype implementation.
Low latency control and debug via UMRBus
High-bandwidth reliable connectivity between HAPS and workstation.
Memory daughter boards debug sample storage
More signal visibility and high-capacity sample storage.
External logic analyzer support
Sophisticated triggering and high capacity sample storage with popular Agilent or Tektronix logic analyzers.
Seamless multi-FPGA support
Add debug logic to par titioned desi gns across multiple FPGAs.
Transactor Based Validation UMRBus automation AMBA tra nsacto rs
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Automatic chaining of UMRBus clie nt-interface modul e (CAPIM) instances and memor y address management across FPGA system controllers. Enables hybrid prototypes that combine virtual and FPGA-based prototyping environments for earlier prototype availability.
Synopsys’ HAPS FPGA-Based Prototyping Solution
Synopsys Virtualizer Development Kit (VDK) SystemC/TLM-based virtual prototype Data exchange
Generic interrupt controller Cortex-A15 MPCore
Cortex-A7 MPCore
L2 cache controller
HAPS® FPGA-based ASIC prototype
Reference SW Stack
AMBA
Interconnect UARTs GPIOs RTC
Embedded memories
Timers Watchdog interface
Generic battery
Color LCD controller
DesignWare USB 3.0
Keyboard/ mouse interface
DesignWare Ethernet
UMRBus
VDK Analyz er
Start software development before hardware is available
Validate HW/SW operation at near real-time speed
Figure 14: Synopsys Hybrid Prototyping solution seamlessly integrates Virtualizer virtual prototyping and HAPS FPGA-based prototyping
Hybrid Prototypes for Faster Availability The Synopsys Hybrid Prototyping solutio n for HAPS Series combines virtual prototyping and FPGA-based prototyping to accelerate the development of SoC prototypes. By using Virtuali zer™ virtual prototyping for new design functions and HAPS® FPGA-based prototyping for reused logic and new RTL, designers can start software development up to 12 months earlier in the design cycle. In addition, Synopsys’ hybrid prototyping solution enables designers to accelerate hardware/software integration and full system validation, thus reducing the overall product design cycle. Synopsys’ Hybrid Prototyping solution enhances software stack validation through high-speed processor execution using abstract SystemC models. It allows connection to real-world I/O model interfaces via analog PHYs or test equipment attached to a HAPS FPGA-based prototype. In addition, designers can leverage new and existing RTL or IP in the FPGA-based prototype and pre-RTL portions of the design in SystemC transaction-level models (TLM), which are faster to implement and available much sooner in a project lifecycle. The Synopsys Hybrid Prototyping solutio n for HAPS delivers these key benefits: `
Integrates virtual and FPGA-based prototypes
`
Start multicore SoC prototyping earlier
` Achieve
high-performa nce execution of system-level models with real-world interface connectivity of hardware
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Partition SoC design to maximize overall performance
` Accelerate
system prototype bring-up
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Improve software debug visibility
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Easily integrate ARM Cortex Processor models, AMBA protocol transactors and DesignWare IP into a single hybrid prototype
A hybrid prototype requires both a logical and physical link to combine the virtual and FPGA-based prototypes. For the logical link, the Synopsys Transactor Library for the ARM ® AMBA ® protocol enables the data exchange between SystemC/TLM models executed by Synopsys’ Virtualizer virtual prototyping and a HAPS Series FPGA-based prototyping system. In addition, a general purpose C++ transactor library with an application programming interface (API) is available for data streaming applications or integration between a HAPS Series system and custom C++ environments. The Synopsys transactor librar y supports a variety of ARM AMBA protocols, including AMBA 2.0 AHB™ /APB™, AXI3™, AXI4™ and AXI4-Lite™. The ARM AMBA master components can initiate a transaction from either the Virtualizer virtual prototyping or HAPS FPGA-based prototyping environments. In the virtual environment, the software API provides send, receive, and callback functions to communicate with the hardware domai n. In the hardware context, the IP blocks communicate through the slave and master ports connected to the u ser IP. The HAPS ProtoCompiler transactor librar y for AMBA is the interface that facilitates the data exchange between a loosely timed transaction-level model (TLM) and a cycle-accurate FPGA hardware implementation. The transactors give designers the flexibility to partition the SoC design between the SystemC/TLM virtual and FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. Build your own HAPS-80 system online! Visit http://www. synopsys.com/apps/haps80ssb/#/. For more information about S ynopsys FPGA-based prototyping products, support services or t raining, visit us on the web at: www.synopsys.com/FPGA-basedprototyping, contact your local sales representat ive.
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•
www.synopsys.com
©2016 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is available at http://www.synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners. 02/16.RP.CS6904.
