Gopi 1Lab Manual

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BTL Institute of Technology EEE Dept.

B T L INSTITUTE OF TECHNOLOGY & MANAGEMENT No.259/B, Bommasandhra Industrial Area , Hosur Road, Bangalore- 560 099 Ph: 080- 27832379, (EEE Dept)

A LAB MANUAL ON

ELECTRONICS LABORATORY (Analog & Digital) Subject Code: 15EEL37 (As per VTU Syllabus CBCS )

PREPERAED BY

GOPINATH.B.L

APPROVED BY

HOD EEE Dept.

15EEL 34 Electronics Laboratory Manual

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INDEX Sl No 1. 2. 3. 4. 5. 6. 7.

Contents INTRODUCTION INSTRUCTION TO STUDENTS LAB CYCLES DESIGN AND TESTING OF FULL WAVE – CENTER TAPPED TRANSFORMER TYPE. DETERMINATION OF RIPPLE FACTOR, REGULATION AND EFFICIENCY. BRIDGE TYPE RECTIFIER CIRCUITS WITH AND WITHOUT CAPACITOR FILTER DETERMINATION OF RIPPLE FACTOR, REGULATION AND EFFICIENCY.

CHARACTERISTICS OF CE CONFIGURATION DETERMINATION OF H PARAMETERS.

CHARACTERISTICS OF CB CONFIGURATION DETERMINATION OF H PARAMETERS.

Page No 4 5 6 7 13 19 25

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FREQUENCY RESPONSE OF SINGLE STAGE BJT RC COUPLED AMPLIFIER AND DETERMINATION OF HALF POWER POINTS, BANDWIDTH, INPUT AND OUTPUT IMPEDANCES

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FREQUENCY RESPONSE OF SINGLE STAGE FET RC COUPLED AMPLIFIER AND DETERMINATION OF HALF POWER POINTS, BANDWIDTH, INPUT AND OUTPUT IMPEDANCES

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10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

DETERMINATION OF GAIN, INPUT AND OUTPUT IMPEDANCE OF BJT DARLINGTON EMITTER FOLLOWER WITH AND WITHOUT BOOTSTRAPPING. SIMPLIFICATION, REALIZATION OF BOOLEAN EXPRESSIONS USING LOGIC GATES/UNIVERSAL GATES. REALIZATION OF HALF/FULL ADDER AND HALF/FULL SUB TRACTORS USING LOGIC GATES. REALIZATION OF PARALLEL ADDER/SUB TRACTORS USING 7483 CHIP- BCD TO EXCESS-3 CODE CONVERSION & VICE VERSA. REALIZATION OF BINARY TO GRAY CODE CONVERSION AND VICE VERSA. DESIGN AND TESTING RING COUNTER/JOHNSON COUNTER. DESIGN AND TESTING OF SEQUENCE GENERATOR. REALIZATION OF 3 BIT COUNTERS AS A SEQUENTIAL CIRCUIT AND MOD – N COUNTER DESIGN USING 7476, 7490, 74192, 74193.

VIVA QUESTIONS APPENDIX I (SYMBOLS, VARIABLES) APPENDIX II(RATING OF TRANSISTOR) APPENDIX III(COMPONENT VALUE IDENTIFICATION)


47 53 59 63 67 72 74 75 92 97 99 102

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INTRODUCTION “A practical approach is probably the best approach to mastering a subject and gaining a clear insight.” Analog Circuits and Digital Circuits Practical session covers those practical oriented electronic circuits that are very essential for the students to solidify their theoretical concepts. This workbook provides a communication bridge between the theory and practical world of the Electronic Laboratory. The knowledge of these practical are very essential for the engineering students. All of these practical are arranged on the modern electronic trainer boards.

This practical session comprises of two sections. The first section consists of Analog circuits. Some of the very useful electronic circuits are discussed in this section. The second section consists of Digital circuits. Each and every practical provides a great in depth practical concepts.


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INSTRUCTIONS TO THE STUDENTS 1. Write Experiment number , Experiment name, Experiment date in the rough record 2. Keep your rough record/ Fare record neat and clean. 3. Draw circuit diagram neatly with HB pencil in the rough record as per circuit given in the lab manual/available in your laboratory. 4. Wire the circuit using electronic components available in the lab. 5. Write the readings in the observation table in the given format in the lab manual. 6. Draw waveforms in the given space. 7. Prepare for vive based on the experiment that you are going to do in a day. 8. The viva questions are included in the semester hand book as well as lab manual 9. Use text book, reference book or internet to find out answers of the questions. 10. Every student must complete your rough record get sign from the faculty on the same day of your lab or the very next day itself. 11. Fare record must be completed and submitted in the next lab. 12. Keep the work place neat and clean.


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15EEL34


ELECTRONICS LABARATORY LAB CYCLES

Cycle 1 1. Design and Testing of Full wave – center tapped transformer type and Bridge type rectifier circuits with and without Capacitor filter. Determination of ripple factor, regulation and efficiency

2. Static Transistor characteristics for CE, CB and CC modes and determination of h parameters... 3. Frequency response of single stage BJT and FET RC coupled amplifier and determination of half power points, bandwidth, input and output impedances 4. Design and testing of BJT - RC phase shift oscillator for given frequency of oscillation.

5. Determination of gain, input and output impedance of BJT Darlington emitter follower with and without bootstrapping

Cycle 2 1. Simplification, realization of Boolean expressions using logic gates/Universal gates 2. Realization of half/Full adder and Half/Full Sub tractors using logic gates 3. Realization of parallel adder/Sub tractors using 7483 chip- BCD to Excess-3 code Conversion & Vice Versa 4. Realization of Binary to Gray code conversion and vice versa

5. Design and testing Ring counter/Johnson counter 6. Design and testing of Sequence generator 7. Realization of 3 bit counters as a sequential circuit and MOD – N counter design using 7476, 7490, 74192, 74193.

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EXPERIMENT NO. 1 DESIGN AND TESTING OF FULL WAVE – CENTER TAPPED TRANSFORMER TYPE AND BRIDGE TYPE RECTIFIER CIRCUITS WITH AND WITHOUT CAPACITOR FILTER. DETERMINATION OF RIPPLE FACTOR, REGULATION AND EFFICIENCY Full Wave – Center Tapped Transformer Type

AIM: To observe waveform at the output of full wave rectifier with and without filter capacitor. To measure DC voltage, DC current, ripple factor with and without filter capacitor. Introduction: Full wave rectifier utilizes both the cycle of input AC voltage. Two or four diodes are used in full wave rectifier. If full wave rectifier is designed using four diodes it is known as full wave bridge rectifier. Full wave rectifier using two diodes without capacitor is shown in the following figure. Center tapped transformer is used in this full wave rectifier. During the positive cycle diode D1 conducts and it is available at the output. During negative cycle diode D1 remains OFF but diode D2 is in forward bias hence it conducts and negative cycle is available as a positive cycle at the output as shown in the following figure. Note that direction of current in the load resistance is same during both the cycles hence output is only positive cycles.


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Advantages of full wave rectifier over half wave rectifier: 1. The rectification efficiency is double than half wave rectifier 2. Ripple factor is less and ripple frequency is double hence easy to filter out. 3. DC output voltage and current is higher hence output power is higher. 4. Better transformer utilization factor 5. There is no DC saturation of core in transformer because the DC currents in two halves of secondary flow in opposite directions. Disadvantages: 1. Requires center tap transformer 2. Requires two diodes compared to one diode in half wave rectifier. Practical Circuit diagram:

List of components: 1. Transformer (center tapped) 12-0-12 V AC, 500 mA 2. Diode 1N4007 ---- 2 No. 3. Resistor 10K 4. Capacitor 1000μF 5. Toggle Switch Experiment Procedure: 1. Construct circuit on the general board. 2. Keep toggle switch OFF to perform practical of full wave rectifier without filter capacitor and ON to connect filter capacitor. WORKSHEET Waveforms: Without filter capacitor: Input Waveform at secondary of transformer:


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Output waveform:

With filter capacitor: Input Waveform at secondary of transformer:

Output waveform:



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Observations: Peak Voltage, Vm =

(From CRO for FWR with and without filter) (From Voltmeter/ Multimeter for FWR with and without DC Voltage, VDC(full load) = filter) (From Voltmeter/ Multimeter for FWR with and without No Load DC Voltage, VDC(No load) = filter) Ripple Voltage, Vr = (From CRO for FWR with filter) Calculations:

Without filter:

Ripple factor (Theoretical) =

Ripple Factor (Practical) With filter:


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Ripple factor (Theoretical) Where f = 50Hz, R =1K , C = 1000 F.

Ripple Factor

Percentage Regulation =

%

VNL = DC voltage at the load without connecting the load (Minimum current). VFL = DC voltage at the load with load connected.

Efficiency

%u200B

PAC = V2rms / RL PDC = Vdc / RL Conclusion:

Important Viva Questions 1. What is the frequency of AC component at the output of full wave rectifier? Give reason. 2. What is the difference in DC output voltage in half wave and full wave rectifier for the same AC input? 3. What is the PIV necessary for the diode if transformer of 24-0-24 V is used ? 4. What is the mathematical relationship between rms input AC voltage and DC output voltage in half wave rectifier with and without filter capacitor? 5. What is filter? Ans: Electronic filters are electronic circuits which perform signal processing functions, specifically to remove unwanted frequency components from the signal. 6. Give some rectifications technologies? 15EEL 34 Electronics Laboratory Manual

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Ans: Synchronous rectifier, Vibrator, Motor-generator set , Electrolytic ,Mercury arc, and Argon gas electron tube. 7. What is the efficiency of bridge rectifier?

Ans: % 8. What is the value of PIV of a center tapped FWR? Ans: 2Vm. 9. In filters capacitor is always connected in parallel, why? Ans: Capacitor allows AC and blocks DC signal.in rectifier for converting AC to DC, capacitor placed in parallel with output, where output is capacitor blocked voltage.If capacitance value increases its capacity also increases which increases efficiency of rectifier. 10. What is the purpose of Center Tapped transformer? 11. What is Regulation? 12. What is the location of poles of filter in S-plane? 13. What is the output of FWR with filter? Is it unidirectional? 14. What are the advantages and disadvantages of center tapped full-wave rectifiers compared with Bridge rectifiers? 15. Define Ripple factor „γ‟ and its values for the three types of rectifiers. 16. What is the value of No load voltage for all the three types of the rectifiers? 17. What are the different types of filters used for the rectifiers?

Conclusion:

Result The Full wave rectifier circuit was done and the wave forms with and without filter capacitor are noted. The DC voltage, DC current, ripple factor with and without filter capacitor is noted.


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EXPERIMENT NO. 2 BRIDGE RECTIFIER AIM: To observe waveform at the output of bridge rectifier with and without filter capacitor. To measure DC voltage, DC current, ripple factor with and without filter capacitor. Introduction: The Bridge rectifier is a circuit, which converts an ac voltage to dc voltage using both half cycles of the input ac voltage. The Bridge rectifier circuit is shown in the following figure.

The circuit has four diodes connected to form a bridge. The ac input voltage is applied to the diagonally opposite ends of the bridge. The load resistance is connected between the other two ends of the bridge. For the positive half cycle of the input ac voltage, diodes D1 and D2 conduct, whereas diodes D3 and D4 remain in the OFF state. The conducting diodes will be in series with the load resistance RL and hence the load current flows through RL. For the negative half cycle of the input ac voltage, diodes D3 and D4 conduct whereas, D1 and D2 remain OFF. The conducting diodes D3 and D4 will be in series with the 15EEL 34 Electronics Laboratory Manual

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load resistance RL and hence the current flows through RL in the same direction as in the previous half cycle. Thus a bi-directional wave is converted into a unidirectional wave. The circuit diagram of the bridge rectifier with filter capacitor is shown in the following figure. When capacitor charges during the first cycle, surge current flows because initially capacitor acts like a short circuit. Thus, surge current is very large. If surge current exceeds rated current capacity of the diode it can damage the diode. To limit surge current surge resistance is used in series as shown in the figure. Similar surge resistance can be used in half wave as well as center-tapped full wave rectifier also.

Bridge rectifier package (combination of four diodes in form of bridge) is easily available in the market for various current capacities ranging from 500 mA to 30A. For laboratory purpose you can use 1A package. Advantages of bridge rectifier: 1. No center tap is required in the transformer secondary hence transformer design is simple. 2. If stepping up and stepping down not required than transformer can be eliminated. (In SMPS used in TV and computer, 230V is directly applied to the input of bridge rectifier). 3. The PIV of the diode is half than in center tap full wave rectifier 4. Transformer utilization factor is higher than in center tapped full wave rectifier 5. Smaller size transformer required for given capacity because transformer is utilized effectively during both AC cycles. Disadvantages of bridge rectifier: 1. Requires Four diodes (But package is low cost) 2. Forward voltage drop across two diodes. This will reduce efficiency particularly when low voltage (less than 5V) is required. 3. Load resistance and supply source have no common point which may be earthed.


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Practical circuit diagram:

List of components: 1. Transformer 12 V AC, 500 mA 2. Diode 1N4007 ---- 4 No. or 1 A bridge rectifier package 3. Resistor 10K [4] Capacitor 1000μF [5] Toggle Switch Experiment Procedure: 1.

Construct circuit on the bread board.

2.

Keep toggle switch OFF to perform practical of full wave rectifier without filter and ON to connect filter capacitor. WORKSHEET

Waveforms: Without filter capacitor: Input Waveform at secondary of transformer:


capacitor

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Output waveform:

With filter capacitor: Input Waveform at secondary of transformer:

Output waveform:



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Observations: Peak Voltage, Vm =

(From CRO for FWR with and without filter) (From Voltmeter/ Multimeter for FWR with and without DC Voltage, VDC(full load) = filter) (From Voltmeter/ Multimeter for FWR with and without No Load DC Voltage, VDC(No load) = filter) Ripple Voltage, Vr = (From CRO for FWR with filter) Calculations: Without filter:

Ripple factor (Theoretical) =

Ripple Factor (Practical) With filter:

Ripple factor (Theoretical) Where f = 50Hz, R =1K , C = 1000 F.

Ripple Factor

Percentage Regulation =

%

VNL = DC voltage at the load without connecting the load (Minimum current). 15EEL 34 Electronics Laboratory Manual

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VFL = DC voltage at the load with load connected.

Efficiency

%u200B

PAC = V2rms / RL PDC = Vdc / RL Conclusion:

Result The Bridge rectifier circuit was done and the wave forms with and without filter capacitor are noted. The DC voltage, DC current, ripple factor with and without filter capacitor is noted.


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EXPERIMENT NO. 3 CHARACTERISTICS OF CE CONFIGURATION AIM: To obtain common emitter characteristics of NPN transistor Introduction: Transistor is three terminal active device having terminals collector, base and emitter. Transistor is widely used in amplifier, oscillator, electronic switch and so many other electronics circuits for variety of applications. To understand operation of the transistor, we use three configurations common emitter, common base and common collector. In this practical, we will understand common emitter configuration. As the name suggest, emitter is common between input and output. Input is applied to base and output is taken from collector.

We will obtain input characteristics and output characteristics of common emitter (CE) configuration. We will connect variable DC power supply at VBB and VCC to obtain characteristics. Input voltage in CE configuration is base-emitter voltage Vbe and input current is base current Ib. Output voltage in CE configuration is collector to emitter voltage VCE and output current is collector current Ic. We will use multi-meter to measure these voltages and currents for different characteristics. Collector to emitter junction is reverse biased and base to emitter junction is forward biased. The CE configuration is widely used in amplifier circuits because it provides voltage gain as well as current gain. In CB configuration current gain is less than unity. In CC configuration voltage gain is less than unity. Input resistance of CE configuration is less than CC configuration and more than CB configuration. Output resistance of CE configuration is more than CC configuration and less than CB configuration.


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Circuit setup for input characteristics

Experiment Procedure: 1. Connect circuit as shown in the circuit diagram for input characteristics 2. Connect variable power supply 0-30V at base circuit and collector circuit. 3. Keep Vcc fix at 0V (Or do not connect Vcc) 4. Increase VBB from 0V to 20V, note down readings of base current Ib and base to emitter voltage Vbe in the observation table. 5. Repeat above procedure for Vcc = +5V and Vcc = +10V 6. Draw input characteristics curve. Plot Vbe on X axis and Ib on Y axis. Observation table Transistor: __________


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Input Characteristics

Circuit setup for output characteristics

Experiment Procedure: 1. Connect circuit as shown in the circuit diagram for output characteristics 2. Connect variable power supply 0-30V at base circuit and collector circuit. 3. Keep base current fix (Initially 0) 4. Increase VCC from 0V to 30V, note down readings of collector current Ic and collector to emitter voltage Vce in the observation table. 5. Repeat above procedure for base currents Ib = 5μA, 50 μA, 100 μA. Increase base current by increasing VBB. 6. Draw output characteristics curve. Plot Vce on X axis and Ic on Y axis.


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Observation table: Transistor: __________

Output Characteristics

1. Graph: Input Characteristics



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Calculations from Graph: 1. Input Characteristics: To obtain input resistance find of the input characteristics.

VBE and

Input impedance = hie = Ri =

VBE /

IB (VCE is constant)

Reverse voltage gain = hre =

VEB /

VCE (IB = constant)

2. Output Characteristics: To obtain output resistance find Output admittance 1/hoe = Ro = Forward current gain = hfe =

IC /

IC /

IC and

IB for a constant VCE on one

VCB at a constant IB.

VCE (IB is constant)

IB (VCE = constant)

Inference: 1. Medium input and output resistances. 2. Smaller values if VCE, lower the cut-in-voltage. 3. Increase in the value of IE causes saturation of the transistor of an earlier voltage. Precautions: 1. While performing the experiment do not exceed the ratings of the transistor. This may lead to damage the transistor. 2. Connect voltmeter and ammeter in correct polarities as shown in the circuit diagram. 3. Do not switch ON the power supply unless you have checked the circuit connections as per the circuit diagram. 4. Make sure while selecting the emitter, base and collector terminals of the transistor. Result: Input and Output characteristics of a Transistor in Common Emitter Configuration are studied. The h-parameters for a transistor in CE configuration are: a. b. c. d.

The Input Resistance (hie) The Reverse Voltage Gain (hre) The Output Conductance (hoe) The Forward Current Gain (hfe)

_______________Ohms. _______________. _______________ Mhos. _______________.

Outcomes: Students are able to 1. Analyze the characteristics of BJT in Common Emitter and configuration. 2. Calculate h-parameters from the characteristics obtained. Conclusion


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Result CE Transistor configuration was set up, I/P and O/P characteristics were plotted. Important Viva Questions 1. How to check transistor with help of multimeter? 2. How to check type of transistor (NPN or PNP) with help of multimeter? 3. Define current gain of the transistor in CE configuration. What is the DC current gain you obtain in this practical? 4. Can transistor be replaced by two back to back connected diodes? Ans: No, because the doping levels of emitter(heavily doped), base(lightly doped) and collector(doping level greater than base and less than emitter) terminals are different from p and n terminals in diode. 5. For amplification CE is preferred, why? Ans: Because amplification factor beta is usually ranges from 20-500 hence this configuration gives appreciable current gain as well as voltage gain at its output on the other hand in the Common Collector configuration has very high input resistance(~750K ) & very low output resistance(~25 ) so the voltage gain is always less than one & its most important application is for impedance matching for driving from low impedance load to high impedance source. 6. To operate a transistor as amplifier, emitter junction is forward biased and collector junction is reverse biased. Why? Ans: Voltage is directly proportional to Resistance. Forward bias resistance is very less compared to reverse bias. In amplifier input forward biased and output reverse biased so voltage at output increases with reverse bias resistance. 7. Which transistor configuration provides a phase reversal between the input and output signals? Ans: Common emitter configuration. 8. 5. What is the range β of a BJT? Ans: Beta is usually ranges from 20 - 500. 9. List the current components of BJT in CE configuration 10. What is Early Effect? 11. Why the doping of collector is less compared to emitter? 12. What do you mean by “reverse active”? 13. What is the difference between CE and Emitter follower circuit? 14. What are the input and output impedances of CE configuration? 15. Identify various regions in the output characteristics? 16. What is the relation between α, β and γ? 17. Define current gain in CE configuration? 18. Why CE configuration is preferred for amplification? 19. What is the phase relation between input and output? 20. 17. Draw diagram of CE configuration for PNP transistor? 21. 18. What is the power gain of CE configuration? 22. 19. What are the applications of CE configuration?


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EXPERIMENT NO. 4 CHARACTERISTICS OF CB CONFIGURATION AIM: To obtain common base characteristics of NPN transistor Introduction: In a common base configuration, base terminal is common between input and output. The output is taken from collector and the input voltage is applied between emitter and base. The base is grounded because it is common. To obtain output characteristics, we wil l measure collector current for different value of collector to base voltage (VCB). Input current is emitter current Ie and input voltage is Veb. To plot input characteristics we wi ll plot Veb versus Ie . Current gain for CB configuration is less than unity. CB configuration is used in common base amplifier to obtain voltage gain. Output impedance of common base configuration is very high. CB amplifier is used in multi-stage amplifier where impedance matching is required between different stages.

Circuit diagram to obtain input characteristics:

Circuit diagram to obtain output characteristics


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Experiment Procedure to obtain input characteristics: 1. Connect circuit as shown in the circuit diagram for input characteristics 2. Connect variable power supply 0-30V (VEE) at emitter base circuit and another power supply 030V at collector base circuit (Vcc). 3. Keep Vcc fix at 0V (Or do not connect Vcc) 4. Increase VEE from 0V to 20V, note down readings of emitter current Ie and emitter to base voltage Veb in the observation table. 5. Repeat above procedure for Vcc = +5V and Vcc = +10V 6. Draw input characteristics curve. Plot Veb on X axis and Ie on Y axis.

Experiment Procedure to obtain output characteristics: 1. Connect circuit as shown in the circuit diagram for output characteristics 2. Connect variable power supply 0-30V at emitter circuit and collector circuit. 3. Keep emitter current fix (Initially 0) 4. Increase VCC from 0V to 30V, note down readings of collector current Ic and collector to base voltage Vcb in the observation table. 5. Repeat above procedure for base currents Ie = 1mA, 5 mA and 10mA. Increase emitter current by increasing VEE. 6. Draw output characteristics curve. Plot Vcb on X axis and Ic on Y axis. Observation table for input characteristics: Transistor: __________

Input Characteristics


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Observation table for output characteristics: Transistor: __________




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Model Graph: Input characteristics:

Output characteristics:

1. Plot the input characteristics for different values of VCB by taking VEE on X-axis and IE on Y-axis taking VCB as constant parameter. 2. Plot the output characteristics by taking VCB on X-axis and taking IC on Y-axis taking IE as a constant parameter. Calculations from Graph: The h-parameters are to be calculated from the following formulae: 1. Input Characteristics: To obtain input resistance, find of the input characteristics.

VEE and

Input impedance = hib = Ri =

VEE /

IE (VCB = constant)

Reverse voltage gain = hrb =

VEB /

VCB (IE = constant)

2. Output Characteristics: To obtain output resistance, find Output admitance = hob = 1/Ro = Forward current gain = hfb =

IC /

IC /

IC and

IE for a constant VCB on one

VCB at a constant IE.

VCB (IE = constant)

IE (VCB = constant)

Inference: 1. Input resistance is in the order of tens of ohms since Emitter-Base Junction is forward biased. 2. Output resistance is in order of hundreds of kilo-ohms since Collector-Base Junction is reverse biased. 3. Higher is the value of VCB, smaller is the cut in voltage. 4. Increase in the value of IB causes saturation of transistor at small voltages. Precautions: 1. While performing the experiment do not exceed the ratings of the transistor. This may lead to damage the transistor. 2. Connect voltmeter and ammeter in correct polarities as shown in the circuit diagram. 15EEL 34 Electronics Laboratory Manual

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3. Do not switch ON the power supply unless you have checked the circuit connections as per the circuit diagram. 4. Make sure while selecting the emitter, base and collector terminals of the transistor. Result: Input and Output characteristics of a Transistor in Common Base Configuration are studied. The h-parameters for a transistor in CB configuration are: a. b. c. d.

The Input resistance (hib) __________________ Ohms. The Reverse Voltage Transfer Ratio (hrb) __________________. The Output Admittance (hob) __________________ Mhos. The Forward Current gain (hfb) __________________.

Outcomes: Students are able to 1. analyze the characteristics of BJT in Common Base Configuration. 2. calculate h-parameters from the characteristics obtained.

Discussion/Viva Questions: 1. What is transistor? Ans: A transistor is a semiconductor device used to amplify and switch electronic signals and electrical power. It is composed of semiconductor material with at least three terminals for connection to an external circuit. The term transistor was coined by John R. Pierce as a portmanteau of the term "transfer resistor". 2. Write the relation between and ? Ans: 3. Define (alpha)? What is the range of ? Ans: The important parameter is the common-base current gain, . The common-base current gain is approximately the gain of current from emitter to collector in the forward-active region. This ratio usually has a value close to unity; between 0.98 and 0.998. 4. Why is less than unity? Ans: It is less than unity due to recombination of charge carriers as they cross the base region. 5. Input and output impedance equations for CB configuration? Ans: hib = VBE / IE, 1 / hoe = VCE / IC 6. What is carrier lifetime? 7. What is the importance of Fermi level? 8. Can the junction less transistors be realized? 9. What is the doping level of E, B and C layers? 10. List the various current components in BJT. 11. Draw the input and output characteristics of the transistor in CB configuration? 12. Identify various regions in output characteristics? 13. What are the applications of CB configuration? 14. What are the input and output impedances of CB configuration? 15. What is EARLY effect? 16. Draw diagram of CB configuration for PNP transistor? 17. What is the power gain of CB configuration? Conclusion 15EEL 34 Electronics Laboratory Manual

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Result CB Transistor configuration was set up, I/P and O/P characteristics were plotted. Important Viva Questions 1. What is early effect? Have you observed early effect in your experiment? 2. Compare common base and common emitter configuration 3. Justify the statement: Common base amplifier is used as buffer 4. What is the value of phase shift between input and output signal in common base and common emitter amplifier?


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EXPERIMENT NO. 5 RC COUPLED CE AMPLIFIER

AIM: To observe input-output waveforms of common emitter (CE) amplifier. To measure gain of amplifier at different frequencies and plot frequency response Introduction: Common emitter amplifier is used to amplify weak signal. It utilizes energy from DC power supply to amplify input AC signal. Biasing of transistor is done to tie Q point at the middle of the load line. In the circuit shown, voltage divider bias is formed using resistors 10K and 2.2K. During positive cycle, forward bias of base-emitter junction increases and base current increases. Q point moves in upward direction on load line and collector current increases β times than base current. (β is current gain). Collector resistor drop Ic*Rc increases due to increase in collector current Ic. This will reduce collector voltage. Thus during positive input cycle, we get negative output cycle. When input is negative cycle, forward bias of baseemitter junction and base current will reduce. Collector current reduces (Q point moves downside). Due to decrease in collector current, collector resistance voltage drop IcRc reduces and collector voltage increases. Change in collector voltage is much higher than applied base voltage because less base current variation causes large collector current variation due to current gain B. This large collector current further multiplied by collector resistance Rc which provides large voltage output. Thus CE amplifier provides voltage gain and amplifies the input signal. Without emitter resistance gain of amplifier is highest but it is not stable. Emitter resistance is used to provide stability. To compensate effect of emitter resistance emitter bypass capacitor is used which provides AC ground to the emitter. This will increase gain of amplifier. CE amplifier does not provide constant voltage gain at all frequencies. Due to emitter bypass and coupling capacitors reduces gain of amplifier at low frequency. Reactance of capacitor is high at low frequency, hence emitter bypass capacitor does not provide perfect AC ground (Emitter impedance is high). There is voltage drop across coupling capacitor at low frequency because of high reactance at low frequencies. Gain of CE amplifier also reduces at very high frequency because of stray capacitances. Audio frequency transistors like AC127, AC128 works for audio frequency range. It does not provide large voltage gain for frequency greater than 20 KHz. Medium frequency transistors are BC147/BC148/BC547/BC548 provides voltage gain up to 500 KHz. High frequency transistors like BF194/BF594/BF200 provides gain at radio frequencies in the MHz range. If we apply large signal at the input of CE amplifier, transistor driven into saturation region during positive peak and cut-off region during negative peak (Q point reaches to saturation and cut-off points). Due to this clipping occurs in amplified signal. So we have to apply small signal at the input and ensure that transistor operates in active region. 15EEL 34 Electronics Laboratory Manual

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Circuit diagram



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Experimental procedure: 1. Connect function generator at the input of the amplifier circuit. 2. Set input voltage 10 mV and frequency 100 Hz. 3. Connect CRO at the output of the amplifier circuit. 4. Observe amplified signal and measure output voltage 5. Increase frequency from the function generator and repeat above step 6. Note down readings of output voltage in the observation table for frequency range from 100 Hz to 10 MHz 7. Calculate voltage gain for different frequencies and gain in dB. Plot frequency response. Observation table Input voltage: Vi = 10 Mv


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Conclusion 1. Design and set up an ampli_er for the speci_cations: gain = -50, output voltage = 10 VPP ; fL = 50 Hz and calculate Zi. 2. Set up an RC coupled ampli_er and measure its input and output impedances Measurement of input resistance Method 1: Connect a known resistor (say 1 k) in series between the signal generator and the input of the circuit. Calculate the current though the resistor from the potential di_erence across it. Since this current also ows into the circuit, input resistance can be measured taking the ratio of the voltage at the right side of the resistor to the current. Method 2: Connect a pot in series between the signal source and the input of the circuit. Adjust the pot until the input voltage to the circuit is 50% of the signal generator voltage. Remove the pot from the circuit and measure its resistance using a multimeter. Measurement of output resistance Method 1: Measure the open circuit output voltage. This is the Thevenin voltage. Output resistance of the circuit is actually the Thevenin resistance in series with the Thevenin voltage. Connect a known value resistor, say 1 k and measure the voltage across it. A reduction in the output voltage can be observed. Calculate the current through the resistor. Since this current also ows trough the Thevenin resistance, output resistance is the ratio of the di_erence in the output voltage to the current. Method 2: Connect a pot at the output of the circuit. Adjust the pot until the voltage across it is 50% of the open circuit voltage. Remove the pot from the circuit and measure its resistance using a multimeter. 3. Differentiate between ac and dc load lines? 4. Explain their importance in ampli_er analysis. 5. Why is the center point of the active region chosen for dc biasing? 15EEL 34 Electronics Laboratory Manual

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6. What happens if extreme portions of the active region are chosen for dc biasing? 7. Draw the output characteristics of the ampli_er and mark the load-line on it. Also mark 8. the three regions of operation on the output characteristics. 9. Which are the di_erent forms of coupling used in multi-stage ampli_ers?

Important Viva Questions 1. What will be emitter current in the given circuit diagram in absence of input AC signal? 2. Draw DC load line of CE amplifier circuit. Show Q point on it. 3. Draw output waveform when inverted sine wave is applied at the CE amplifier circuit 4. What is bandwidth? What is the approximate bandwidth of CE amplifier that you have used during your practical. 5. What is the effect on gain of amplifier if value of Rc increases? 6. What are the different biasing methods? 7. What happens if emitter bypass capacitor is removed from the circuit? 8. MODEL GRAPH

9.


36

Result With CE: 1. Mid-band gain of the amplifier =: : : : : : 2. Bandwidth of the amplifier =: : : : : : Hz Without CE: 1. Mid-band gain of the amplifier = : : : : : : 2. Bandwidth of the amplifier = : : : : : :Hz



37


EXPERIMENT NO. 6

RC COUPLED SINGLE STAGE FET AMPLIFIER AIM To design RC coupled single stage FET amplifier and determine the gain, frequency response, input and output impedance. COMPONENTS REQUIRED Sl. No

Apparatus and components

Range

Quantity

1

Spring board

1

2

FET

BFW10/11

3

Resistors

2.7KΩ,1KΩ,2.2KΩ 1

4

Capacitors

0.1µF,.47 µF

2+2

5

VRPS

0-30Vdc 3A

1

6

Signal generator

10Hz to 1MHz

1

7

CRO

1

8

Probes, wires

2+15

9 10

DRB Digital Multimeter

0 to1Mohm

1

1 2

THEORY The field effect transistor (FET) has a capability to amplify a.c signals like a BJT. Depending upon the type of configuration, the FET amplifiers may be classified as: *Common source amplifier. *Common drain amplifier. *Common gate amplifier. The circuit diagram 2.5 illustrates a common source junction FET amplifier. It is quite similar to a common emitter amplifier .Here, the resistors R1 & R2 are used to bias the FET.The coupling capacitors (Cc1,Cc2) are used to couple the a.c. input voltage source and the output voltage respectively, these are known as coupling capacitors. The capacitor Cs keeps the source of the FET efficiently at a.c. ground and is known as bypass capacitor. The operation of the circuit may be understood from the assumption that when a small a.c. signal is made to apply to the gate, it produces variations in the gate to source voltage which in


38


turn,producs variations in the drain current.As the gate to source voltage increases, the drain current also increases because of this the voltage drop across the resistor Rd also increases. This causes the drain voltage to decrease. It means the positive half cycle of the output voltage produces the negative half cycle of the output voltage. In other words , there is a 180 degree phase shift between input and output amplifier. This phenomenon of phase inversion is similar to that exhibited by a common emitter bipolar transistor amplifier. CIRCUIT DIAGRAM

Fig 1(B).a Circuit to find the frequency response curve of FET amplifier

Fig 1(B).b Circuit to find the input impedance

Fig 1(B).c Circuit to find the output impedance


39


DESIGN Given: Idss = 8mA; Vp= -4V; gm=4m mhos; VDD=+15V; Let VGS =-2V; Id=Idss (1-VGS/VP)2 =2mA Vs =Id*RS( Assume Id =Is) Vs =Is*Rs Rs= Vs/ Is=-Vgs/ Is=2/2=1KΩ. Let gm=4m mhos AV=µ= gm* Rd Rd =10/4m=2.5KΩ≈2.7 KΩ Let Cc1= Cc2 =0.1µF Cs=47 µF Input impedance is high hence select R G=2.2MΩ

PROCEDURE 1. Rig up the circuit as shown in the circuit diagram and give VDD = +15V and without connecting signal generator check the biasing conditions i.e. VDS, VS and VGS. 2. Connect the signal generator and set the input voltage constant (say 200mV) at 10 KHz. 3. For different input frequencies note the corresponding output voltage. 4. Plot the frequency v/s decibel. 5. Find the figure of merit i.e. product of maximum gain and bandwidth. 6. Find the input and output impedance of the FET amplifier. 7. Connect the circuit as shown in Fig 2.b. 8. Set the DRB value to minimum initially and start increasing the resistance in the DRB from the minimum value until output voltage becomes half. When the output voltage becomes half of the initial value, the corresponding resistance in the DRB is the input impedance (Zi). 9. Connect the circuit as shown in Fig 2.c. 10. Set the DRB value to maximum initially and start decreasing the resistance in the DRB from the maximum value until output voltage becomes half. When the output voltage becomes half of the initial value, the corresponding resistance in the DRB is the output impedance (Zo).


40


EXPECTED GRAPH

Fig 1(B).d Frequency response curve of FET amplifier

TABULAR COLUMN

Frequency (Hz)

Output Voltage (VoP-P) Volts


Voltage Gain Vo / Vi

Gain (db)=20 log (Vo / Vi)

41


Table 1(B).a To record the observed values

RESULT The RC Coupled FET Amplifier was designed and the Bandwidth (BW), Input Resistance (Zi), Output Resistance (Zo) is Bandwidth (BW)

=

Input Resistance (Zi)

=

Output Resistance (Zo)

=

EXPECTED VIVA QUESTIONS 1. 2. 3. 4. 5. 6. 7. 8.

What happens to the gain when the amplifiers are connected in cascade? What is field effect transistor? Why FET is called unipolar device? Differentiate between FET and BJT. Mention the parameters of FET. Define drain resistance (rd). Define Trans-conductance. Define amplification factor.

OBSERVATION AND WORK SHEET

SEMILOG GRAPH SHEET HAS TO BE INSERTED


42


EXPERIMENT NO.7

RC PHASE SHIFT OSCILLATOR AIM To design and verify the performance of RC phase shift Oscillator for the given frequency. EQUIPMENTS REQUIRED Sl. No Apparatus and components 01 Bread Board 02 NPN transistor 03

Resistors

04

Capacitors

05 06 07 08 09

VRPS Potentiometer CRO for testing Probes, wires Digital multimeter

Range

Quantity 1 1

SL 100 220Ω,5.6KΩ,22KΩ,820 1+1+1+1+ Ω, 3 6.8KΩ 4.7µF,0.001 µF 2+3 0-30Vdc 3A 47kΩ

1 1 1 2+15 1

THEORY: RC phase shift Oscillator basically consists of an amplifier and feed back network consisting of resistors and capacitors in ladder fashion. The basic RC circuit is as shown below

Fig 3.a Phase lead network and Phasor diagram

The current I is in phase with Vo, whereas the capacitor voltage Vc lags the current I by φ (90®→Ideal value). OR the output voltage Vo leads the I/P voltage Vi by angle φ is adjusted in practice, equal to 60®.RC network is used in feedback path. In Oscillator, feedback network must introduce a phase shift of


43


180® to obtain total phase shift around a loop as 360®.Thus three Rc network each provide 60® phase shift is cascaded, so that it produces total 180® phase shift. The Oscillator circuit consisting amplifier and Rc feedback network is as shown below. CIRCUIT DIAGRAM:

Fig 3.b Circuit diagram of Phase Shift Oscillator


44



45


PROCEDURE: 1) Make the circuit connections as shown in Fig 3.b 2) The output Vo is obtained on CRO. The 10 KΩ pot is adjusted to get a stable output on the CRO. 3) The frequency of Oscillations is measured using CRO and then compared with the theoretical values. 4) With respect to output at point P, the waveforms at point Q, R and S are observed on the CRO. 5) We can see the phase shift at each point being 600, 1200 and 1800 respectively.

NOTE: The value of all three capacitors C is changed and the frequency of Oscillation can be changed to new value and is measured again. 15EEL 34 Electronics Laboratory Manual

46

Designed frequency 2 KHZ Actual frequency got 2KHZ Phase shift between P & Q P&R P&S


60 120 180

RESULTS : Theoretical frequency of oscillations =

KHz

Practical frequency of oscillations

KHz

=


47

BTL Institute of Technology EEE Dept. EXPERIMENT NO.8

BJT DARLINGTON EMITTER FOLLOWER AIM To design BJT Darlington emitter follower with and without bootstrapping and determine the Voltage gain, input impedance and output impedance. EQUIPMENTS REQUIRED: Sl. No

Apparatus and components

Range

Quantity

1

Bread board

1

2

NPN transistor

SL100

2

3

Resistors

560Ω, 480KΩ,800KΩ

1 each

4

Capacitors

0.47uF , 47uF

2+2

5

VRPS

0-30V DC, 3A

1

6

Signal generator

10Hz to 3MHz

1

7

CRO for testing

1

8

Probes, wires

2+15

9 10

DRB Digital multimeter

0 to 1MΩ

1 1

THEORY A Darlington connection is a very popular connection of two transistors for operation as one super beta transistor. The composite transistor acts as a single unit with a current gain equal to the product of the current gains of individual transistors. Sometimes ,the current gain and input impedance of an emitter followed are insufficient to meet the requirement. In order to increase the overall values of circuit current gain and input impedance, two transistors are connected together. The result is that emitter current of the first transistor is the base current of the second transistor. Therefore the current gain of the pair is equal to product of individual current gain that is β = β1*β2.

CIRCUIT DIAGRAM


48


Fig 2.a Darlington emitter follower

Fig 2.b Darlington emitter follower with bootstrapping

DESIGN


49 BTL Institute of Technology EEE Dept. Let VCE = 6V, ICQ≈IEQ=10mA (Q point of transistor Q2), ẞ=100 (SL 100) Then Vcc = 2VCE=2 x 6 =12 V IE = Ic = 10 mA VR3 = Vcc – VCE= 12 – 6 = 6V RE= VR3 / IE = 6V / (10 mA) = 0.6K =560Ω (Choose) VR2 –VBE1 - VBE2 – VR3 = 0 i.e , VR2 = VBE1 + VBE2 + VR3 = 0.6 + 0.6 + (IERE) = 1.2 + (10x0.6) = 7.2V Vcc = VR1 +VR2 VR1= Vcc – VR2 = 12 – 7.2 = 4.8 V IE1=IB2 ≈IE2 / ẞ=10mA/ 100= 0.1mA IB1=IE1 / hfe = 0.1mA / 100 = 1 μA R1 = VR1/ (10 (IB1)) = 4.8 / (10 x 1 μA) = 480 KΩ R2= VR2 / (9 IB1) = 7.2 / (9 x 1 μA) = 800kΩ To find Cc1 XcC1 Ri / 10 (Ri = R1|| R2 || hie = hie) Let fL=100Hz (Lower Cut-off Frequency) fL= 1 / (2π*(Ri / 10)*Cc1) Ri= R1 || R2 || hie For the above darlington pair hie≈βD*RE For SL100 β=150 and βD= β* β=22500 Ri≈290 KΩ So Cc1= 1 / 2π*(Ri/10)*fL= 1 / (2π*29KΩ*100) =0.05 uF So, Use Cc1 = 0.1 F or 0.47 To find Cc2

F.

Let fL=100Hz ( Lower Cut-off frequency ) ,RL=1KΩ fL= 1 / 2π*(Ro+RL)*CE But Ro=Re ≈ re

Here, re=VT / Ic

=26mV/10mA=2.6Ω Re ≈ re ≈3Ω 1/(2π*fL* CE )= Re => Therefore, CE=1/(2*π*100*(3+1KΩ)) CE =1.59 µF Use Cc2 ≈0.47 or 2 µF


50


PROCEDURE Rig up the circuit as in the case of biasing circuit for RC coupled BJT Amplifier (Exp 1(A)) without connecting signal generator and capacitors. Check the biasing conditions i.e. VCC =12V and check corresponding values of VCE,VBE,VE. 1. Connect the as in Fig 2.a (without bootstrapping)with signal generator and designed capacitor values and set the input voltage constant at 50mV(p-p) , 1KHz. 2. Now vary the input frequency starting from 100Hz to MHz range and note the corresponding output voltage(peak to peak). 3. Plot the graph of frequency v/s output voltage gain in decibel with frequency on Xaxis and dB gain on Y-axis and determine the bandwidth. 4. Repeat the procedure for circuit diagram in Fig 2.b (with bootstrapping) TO DETERMINE INPUT IMPEDANCE (Zi) AND OUTPUT IMPEDANCE (Zo) (a) INPUT IMPEADNCE (Zi)

Fig 2.c Circuit to find the input impedance

PROCEDURE 1. Connect the circuit as shown in the Fig 2.c to obtain input impedance and set the input frequency at say 10kHz(center frequency). 2. Set the DRB value to minimum initially and note the corresponding output voltage. Start increasing the resistance in the DRB from the minimum value until output voltage becomes half. when the output voltage becomes half of the initial value, the corresponding resistance in the DRB is the input impedance(Zi). 3. Repeat the procedure for circuit diagram in Fig 1.b (with bootstrapping)


51


b) OUTPUT IMPEDANCE (Zo)

Fig 2.d - Circuit to find the output impedance

PROCEDURE 1. Connect the circuit as shown in the diagram 2.d to obtain output impedance and set the input frequency at say 10kHz(center frequency). 2. Set the DRB value to maximum initially and note the corresponding output voltage. Start decreasing the resistance in the DRB from the maximum value until output voltage becomes half. When the output voltage becomes half of the initial value, the corresponding resistance in the DRB is the output impedance (Zo). Repeat the procedure for circuit diagram in Fig 1(A).b (with bootstrapping) 3. Repeat the procedure for circuit diagram in Fig 1.b (with bootstrapping)

EXPECTED GRAPH OF FREQUENCY RESPONSE

Fig 2.e Frequency response curve.


52


TABULAR COLUMN:

Frequency (Hz)

Output Voltage (VOP-P) Volts

Voltage Gain V / Vo

i

Gain(dB) =20 log (Vo / V) i

Table 2.a. To record the observed values

RESULT Midband Voltage Gain = With bootstrapping

Without bootstrapping

Input Resistance(Zi) Output Resistance(Zo) EXPECTED VIVA QUESTIONS 1. What is Darlington emitter follower? 2 .Why do you call it as Darlington emitter follower? 3. What is the difference between with and without bootstrapping? 4. Benefits of with and without bootstrapping? 5. What is the difference between Darlington emitter follower and FET amplifier? 6.Mention the application of emitter follower?

OBSERVATION AND WORK SHEET

SEMILOG GRAPH SHEET HAS TO BE INSERTED


53

BTL Institute of Technology EEE Dept. EXPERIMENT NO.9 Aim : Simplification, realization of Boolean expressions using logic gates/Universal gates. a) Verification of Logic gates. b) Realize the following expressions Using Logic gates and universal gates in i) SOP form ii) POS form Components required:SlNo

1)

NAME OF THE COMPONENT

IC NUMBER

QUANTITY

1

AND gate

7408

2

2

OR gate

7432

2

3 4

Not gate EXOR gate

7404 7486

2 2

5 6

NAND gate NOR gate

7400 7402

2 2

7 8 9

EX-NOR gate Patch chords Trainer Kit

4077

1

NOT GATE

2) OR GATE

2)

AND GATE SYMBOL

TRUTH TABLE

IC 7408

UNIVERSAL GATES 1)

NAND GATE SYMBOL

TRUTH TABLE


IC 7408

54

2)

NOR GATE SYMBOL

3)

TRUTH TABLE

IC 7408

XOR GATE SYMBOL

4)


TRUTH TABLE

IC 7408

EX-NOR GATE SYMBOL

TRUTH TABLE

IC 4077

IMPIMENTATION OF BASIC GATES USUNG UNIVERSAL GATES NAND GATE AS (a) LOGICDIAGRAM


TRUTH TABLE

55

(b)

(c)


OR GATE LOGICDIAGRAM

TRUTH TABLE

NOT GATE

LOGICDIAGRAM

(d)

(e)

TRUTH TABLE

NOR GATE LOGICDIAGRAM

TRUTH TABLE

EX-OR GATE LOGICDIAGRAM

TRUTH TABLE

(f) EX-NOR GATE LOGICDIAGRAM

TRUTH TABLE

NOR GATE AS


56 (a)

(b)

(c)

(d)

(e)

(f)

AND GATE LOGIC DIAGRAM

BTL Institute of Technology EEE Dept. TRUTH TABLE

OR GATE LOGIC DIAGRAM

TRUTH TABLE

NOT GATE LOGIC DIAGRAM

TRUTH TABLE

NAND GATE LOGIC DIAGRAM

TRUTH TABLE

EX-NOR GATE LOGIC DIAGRAM

TRUTH TABLE

EX-OR GATE LOGIC DIAGRAM


TRUTH TABLE

57


Realize the fallowing expressions in (1) SOP form (sum of product) (2) POS form (product of sum) SOP FORM F(A,B,C,D) = ∑(5,7,9,11,13,15) Simplification- SOP form

Using NAND gates

POS FORM F(A,B,C,D) =∏(0,1,2,3,4,6,8,10,12,14) Simplification- POS form

Using NAND gates


using basic gates

using NOR gates

Using basic gates

Using NOR gates

58

BTL Institute of Technology EEE Dept. Truth table:

Procedure: 1.Place the Ic in the socket of the trainer kit.*complex boolean Expression s are simplified by using Kmaps. 2.make the connections as shown in the circuit diagram. 3.Apply diff combinations of i/ps according to the truth table verify the o/p. 4.Repeat the above procedure for all the circuit diagrams.


A

B

C

D

Y=(A+B)D

0 0 0 0 0

0 0 0 0 1

0 0 1 1 0

0 1 0 1 0

0 0 0 0 0

0 0

1 1

0 1

1 0

1 0

0

1

1

1

1

1 1

0 0

0 0

0 1

0 1

1 1 1 1 1 1

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

0 1 0 1 0 1

59

BTL Institute of Technology EEE Dept. EXPERIMENT NO.10 Realization of half/Full adder and Half/Full Sub tractors using logic gates. Aim: (a) realization of half /full adder and (b)half/full subtractor using logic gates Components required :Sl.No

NAME OF THE COMPONENT 1 AND gate 2 OR gate 3 Not gate 4 EXOR gate 5 NAND gate 6 NOR gate 7 Patch chords 8 Trainer Kit (a) HALF ADDER USING BASIC GATES

IC NUMBER

QUANTITY

7408 7432 7404 7486 7400 7402

1 1 1 3 3 3

(b) HALF ADDER USING NAND GATES

FULL ADDER USING NAND GATES

USING NAND GATES Circuit Diagram


Truth table (Full adder)

60


USING NOR GATES

Procedure:-verify the truth table for half adder and full adder circuits using basic and universal gates. HALF SUBTRACTOR Truth Table

Circuit Diagram

A

B

Diff

Barrow

0

0

0

0

0

1

1

1

1

0

1

0

1

1

0

0

Using NAND gates

FULL SUBTRACTOR Truth Table A

B

Bin

Diff

Borrow

0

0

0

0

0

0

0

1

1

1


61


0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

Logic Diagram

USING NANAD GATES

USING NOR GATES


62 BTL Institute of Technology EEE Dept. Procedure:-verify the truth table for half subtractor and full subtractor circuits using basic and universal gates.


63

BTL Institute of Technology EEE Dept. EXPERIMENT NO11 REALIZATION OF PARALLEL ADDER/SUB TRACTORS USING 7483 CHIP- BCD TO EXCESS-3 CODE AIM: (1) REALISATION of Parallel adder/subtractor using 7483chip (2) BCD to XS3 code conversion and vice versa

Components required :-

Sl.No 1 2 3 4

NAME OF THE COMPONENT EXOR gate 4 bit parallel adder/subtractor Patch chords Trainer Kit

IC NUMBER

QUANTITY

7486 7483

1 1

Pin diagram:

LOGIC diagram

Block Diagram


64


Procedure: Make the connections as shown . For addition ,make Cin=0 and apply the 4 bits as i/p for A and aply another set of A bits to B. Observe the o/p at S3, S2 S1 S0 and carry generated at Cout. Repeat the above steps for different inputs and tabulate the result. 3.For subtration Cin is made equal to 1 and A-B format is used. First no second no. By Xor –ing the i/p bits of ‘B’ by 1 , is complement of ‘B’ is obtained. Further Cin ,which is 1 is added to the LSB of the Xor –ed bits. This generates 2’s complement of B. verify the difference and polarity of differences at S0, S1, S2, S3.and Cout. If Cout is 0 , diff is –ve and diff is 2’s complement form. If Cout is 1, diff is +ve . Repeate the above steps for different inputs. And tabulate the result. Readings:-

Cin

A3

A2

A1

A0

B3

B2

B1

B0

Cout

S3

S2

S1

S0

0

1

0

0

1

1

0

0

1

1

0

0

1

0

0

0

1

1

1

0

0

0

1

0

1

0

0

0

1

1

0

0

1

1

0

0

0

1

0

0

0

1

1

0

0

0

1

0

0

1

1

0

1

1

1

0

B4 0

BCD B3 B2 0 0

Truth table XS3 B1 0

X4 0

X3 0

X2 1

X1 1

0 0

0 0

0 1

1 0

0 0

1 1

0 0

0 1

0 0 0 0

0 1 1 1

1 0 0 1

1 0 1 0

0 0 1 1

1 1 0 0

1 0 0 0

0 0 0 1

0

1

1

1

1

0

1

0

1

0

0

0

1

0

1

1


65

BCD to

1

0

0

1

BTL Institute of Technology EEE Dept. 1 0 0 Ex-3

1

Ex-3 to BCD Truth table XS3

BCD

X4

X3

X2

X1

B4

B3

B2

B1

0

0

1

1

0

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

1

0

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0

1

0

0

0

0

1

0

1

1

0

0

1

0

1

1

0

1

0

1

0

0

1

1

1

1

0

1

1

1

0

0

0

1

1

0

0

1

0

0

1

Circuit Diagram

Procedure: BCD to XS-3 code conversion and vice-versa can be implemented using Ic 7483 along with 7486 Xor gates. The four i/p bits of ‘B’ ie B3, B2, B1, B0, are fixed as 0011. cin =0, performs addition and Cin =1 performs subtraction.




66 BTL Institute of Technology EEE Dept. For BCD to xs –3 code conversion 3 has to be added to i/p bits of A there for Cin =0.



For Xs-3 to BCD code conversion ‘3’ has to be subtarcated from the i/p of A therefor Cin =1.



Verify the truth table.


67

BTL Institute of Technology EEE Dept. Experinment -12 AIM : Realization of Binary to Gray code conversion and vice versa. Components required :-

Sl.No 1 2 3 4

NAME OF THE COMPONENT EXOR gate NAND gate Patch chords Trainer Kit

IC NUMBER

QUANTITY

7486 7400

1 4

Binary to Gray code converter

BINARY

GRAY CODE

B3

B2

B1

B0

G3

G2

G1

G0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

1

0

0

1

1

0

0

1

0

0

1

0

0

0

1

1

0

0

1

0

1

0

1

1

1

0

1

1

0

0

1

0

1

0

1

1

1

0

1

0

0

1

0

0

0

1

1

0

0

1

0

0

1

1

1

0

1

1

0

1

0

1

1

1

1

1

0

1

1

1

1

1

0

1

1

0

0

1

0

1

0

1

1

0

1

1

0

1

1

1

1

1

0

1

0

0

1

1

1

1

1

1

0

0

0

G3 = ∑(8,9,10,11,12,13,14,15)


G2 = ∑(4,5,6,7,8,9,10,11)

68


G3=B3

G2 = G1= ∑(2,3,4,5,10.,11,12,13)

USING XOR GATES ONLY

Using NAND Gates only


G0 = ∑(1,2,3,5,6,9,10,13,14)

69


GRAY TO BINARY

G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

GRAY CODE G2 G1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

G0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1


B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

BINARY CODE B2 B1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1

B0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

70

LOGIC DIAGRAM

USING NAND GATE



71


Procedure:1. place the Ic’s in the socket of the trainer kit. 2. make connections for the gate as shown in the circuit diagram. 3.Apply different combinations of the input according to the truth table and verify the corresponding o/ps shown on the truth table.


72

BTL Institute of Technology EEE Dept. EXPERIMENT-13 Ring counter/Johnson counter AIM –Design and testing of Ring counter/Johnson counter using IC-7495 RING COUNTER USING IC-7495 Components required :Sl.No

NAME OF THE

IC

COMPONENT

NUMBER

QUANTITY

1

Ring Counter

7495

1

2

NAND gate

7400

1

Patch chords Trainer Kit

TRUTH TABLE

CIRCUIT DIAGRAM

CP QA QB QC QD t0

1

0

0

0

t1

0

1

0

0

t2

0

0

1

0

t3

0

0

0

1

t4

1

0

0

0

Procedure(1). Rig up the circuit as shown in the diagram,DS is not given as input. (2). Load data parallely with clkp and M=1 (3). Then make M=0,Clks-cp (4). Verify the working of a ring counter. JHONSON COUNTER USING TRUTH TABLE


CIRCUIT DIAGRAM

73

CP

QA

QB

QC

QD

t0

1

0

0

0

t1

1

1

0

0

t2

1

1

1

0

t3

1

1

1

1

t4

0

1

1

1

t5

0

0

1

1

t6

0

0

1

1

t7

0

0

0

1

t8

1

0

0

0


Procedure(1). Rig up the circuit as shown in the diagram,DS is not given as input. (2). Load data parallely with clkp and M=1 (3). Then make M=0,Clks-cp (4). Verify the whether the ckt works as a Jhonoson counter or twisted ring counter.


74

BTL Institute of Technology EEE Dept. EXPERIMENT NO.14

SEQUENCE GENERATOR AIM: DESIGN A SEQUENCE GENERATOR Sequence: 100010011010111 Design: There are 15 bits, so there will be 15 states s=15. So at least 4 flip-flops are required. Components required :Sl.No 1 2 3 4

TRUTH TABLE QA QB 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 1

NAME OF THE COMPONENT Shift register Ex-OR NANDgate(3i/ps) Trainer Kit Patch Chords

IC NUMBER

QUANTITY

7495 7486 7410

1 1 1

SIMPLFICATION QC 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1

QD 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0

f 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1

Procedure(1).The sequence is written such that no state repeats itself.The binary sequence is repeated once in every 2N-1 clock cycles. (2). The Expression for (QA, QB, QC, QD) is got using K-maps. (3). Rig up the circuit as shown in the figure. (4). Intially let M = 1,clkp = cp, the intial state (A, B, C, D – 1110/1111) is losded. (5). Then make clks =Cp, M = 0, output is observed at MSB (QA). Note:-When we observe the sequence, which is to be generated, the LSB is a 1, following bit is a 0. If 0 has to be generated, then input to that particular D-FF must be a 0. There fore f(QA, QB, QC, QD) has its first entery as a 0.


75

BTL Institute of Technology EEE Dept. EXPERIMENT NO.15 COUNTERS Aim -Realization of 3-bit counters as a sequential circuit and mod-N counter design (7476,7490,74192,74193) a) Asynchrones type b) Synchronous type Components required:Sl.No

NAME OF THE COMPONENT 1 JK flip flop 2 NANDgate(3 pin) 3 AND gate 4 OR gate 5 Decade Counter 6 Decade Up/down Counter MOD 16 counter Patch chords Trainer Kit (A). ASYNCRONOUS COUNTERS

IC NUMBER 7476

QUANTITY

7408 7432 7490 74192

2 2 1 1 1 1

74193

1

(a) Realization of 3-bit binary counters using IC7476(MOD-8) PIN DIAGRAM

UP COUNT (MOD-8)

WAVE FORMS


76


TRUTH TABLE Number of clock pulses 0 1 2 3 4 5 6 7 8

Flip Flop outputs Qc Qb Qa 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0

DOWN COUNT

TRUTH TABLE Number of clock pulses


Flip Flop outputs Qc

Qb

Qa

77

BTL Institute of Technology EEE Dept. 1 1

0

1

1

1

1

0

2

1

0

1

3

1

0

0

4

0

1

1

5

0

1

0

6

0

0

1

7

0

0

0

8

1

1

1

MOD-N COUNTER (UP COUNTER) MOD-4 COUNTER – In MOD-4 counter TRUTH TABLE

1 0 0 (Qa, Qb, Qc) is Invalid state

Flip Flop outputs

Number of clock pulses

Qc

Qb

Qa

0

0

0

0

1

0

0

1

`2

0

1

0

3

0

1

1

Circuit diagram


78


WAVE FORMS

MOD-6 COUNTER

TRUTH TABLE

In MOD-6 counter 1 1 0 (QC, Qb, Qa) invalid state

Circuit diagram

WAVEFORMS


79


MOD-N COUNTERS (DOWN COUNTER) MOD-4 COUNTERInvalid state is from 1 0 0 to 1 1 1. Then sequence is 011(C, B, A), 010,001,000,011 TRUTH TABLE

WAVEFORMS


80


MOD-7 COUNTER In MOD-7 Counter the invalid state is 111, the data sequence will starts from 110 and should count down to 000 Ie. 110- 101-100-011-010-001-000-110 TRUTH TABLE

CIRCUIT DIAGRAM

WAVEFORMS


81


REALISATION OF 3 BIT UP/DOWN COUNTER

WAVEFORMS

SYNCHRONOUS COUNTERS UP COUNTER DESIGN AND REALIZATION OF 3 BIT SYNCHRONOUS COUNTER USING IC7476 Excitation table Present Next state State J K 15EEL 34 Electronics Laboratory Manual

82

output 0 0 1 1

PRESENT STATE Qc Qb Qa 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

NEXT STATE Qc Qb Qa 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0

simplifications


BTL Institute of Technology EEE Dept. output 0 0 X 1 1 X 0 X 1 1 X 0

JC 0 0 0 1 X X X X

KC X X X X 0 0 0 1

EXCITATION JB KB JA 0 X 1 1 X X X 0 1 X 1 X 0 X 1 1 X X X 0 1 X 1 X

KA X 1 X 1 X 1 X 1

83


CIRCUIT DIAGRAM PRESENT STATE Qc Qb Qa 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1

NEXT STATE Qc Qb Qa 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0

JC 0 0 0 1 X X

WAVE FORMS

MOD-6 COUNTER In MOD-6 counter invalid state is 110 simplifications


KC X X X X 0 1

EXCITATION JB KB 0 X 1 X X 0 X 1 0 X 0 X

JA 1 X 1 X 1 X

KA X 1 X 1 X 1

84


CIRCUIT DIAGRAM

WAVE FORMS

MOD-5 SYNCHRONOUS DOWN COUNTER PRESENT STATE

NEXT STATE

FLIP-FLOPS

Qc

Qb

Qa

Qc

Qb

Qa

Jc

Kc

Jb

Kb

Ja

Ka

1

0

0

0

1

1

X

1

1

X

1

X

0

1

1

0

1

0

0

X

X

0

X

1

0

1

0

0

0

1

0

X

X

1

1

X

0

0

1

0

0

0

0

X

0

X

X

1


85

0

0

0

1

0

0

BTL Institute of Technology EEE Dept. 1

X

0

X

0

X

SIMPLIFICATION

CIRCUIT DIAGRAM

MOD-8 DOWN COUNTER TRUTH TABLE PRESENT STATE Qc Qb Qa 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1

NEXT STATE Qc Qb Qa 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0


JC X X X X 0

KC 0 0 0 1 X

EXCITATION JB KB X 0 X 1 0 X 1 X X 0

JA X 1 X 1 X

KA 1 X 1 X 1

86

0 0 0

1 0 0

0 1 0

0 0 1

0 0 1

1 0 1

BTL Institute of Technology EEE Dept. 0 X X 1 1 X 0 X 0 X X 1 1 X 1 X 1 X

SIMPLIFICATIONS

CIRCUIT DIAGRAM

MOD-N COUNTERS To realize a MOD-N counter using IC-74193 with a given preset value, write down the expected function table Pin details of IC 74193(Synchronous counter) [MOD-16 UP/DOWN COUNTER]


87


FUNCTION TABLE

H L L L L

Load X L H H H

Up X X Cp H H

Down X X H Cp H

Qd 0 D

Qc Qb Qa 0 0 0 C B A COUNT UP COUNT DOWN NO CHANGE

Design a counter which counts from (6-

12) Invalid state 1101

WAVE FORMS


88


REALIZE A (15-6) COUNTER USING IC 74193

Invalid state---0101 Note:-Lo and Bo are used basically for cascading the counters To realize a MOD-N counter using IC-74193

PIN DIAGRAM

INTERNAL DIAGRAM


89

Functional Table R1 H H X L X

R2 H H L X L

S1 L X H L X

S2 X L H X L

7490 AS MOD-2 COUNTER






Qa L L 1

Qb Qc L L L L 0 0 MOD-2 COUNTER MOD-5 COUNTER

Qd L L 1

90



To realize a MOD-N counter using IC74192 with given preset value, write down the expected function table SYNCHRONOUS COUNTER PIN DETAILS OF IC-74192[ MOD-10 UP/DOWN COUNTER]

MOD-6 UP COUNTER:Invalid state o110


91


MOD-9 DOWN COUNTER:

DESIGN A COUNTER WHICH CAN COUNT FROM 7 TO 9

NOTE After 1001, out put becomes 0000


92

BTL Institute of Technology EEE Dept. VIVA QUESTION 1. Define minterm and maxterm? 2. Define minterm Canonical formula and maxterm canonical formula? 3. What does standard SOP and standard POS mean? 4. What are basic gates? disjunctive conjunctive. 5. What are universal gates? Why are they called so? 6. What does prime implicant, prime implicant and essential prime implicant mean? 7. What does the term subsume mean? 8. What are the different methods for solving Boolean expressions? 9. Among K-map, VEM technique & Quine-McCluskey, which is easier to use? 10. What is the other name given to K-map? 11. What is the other name given to VEM technique? 12. What is the other name given to Quine-McCluskey? 13. What is the difference between Combinational circuit and Sequential circuit? 14. What is a Parallel adder? 15. If 2 10-bit numbers have to be added using Parallel adder how many full adders are required? 16. What are the disadvantages of parallel adder? 17. What is a look ahead carry adder? 18. What is a serial adder? 19. Is a serial adder a sequential circuit or a combinational circuit? 20. What is a BCD adder? 21. Which is better when compared to a binary adder and BCD adder? 22. If 2 10-bit numbers have to be added using serial adder, how many full adders are required? 23. Which is fastest among parallel adder, serial adder and look ahead carry adder? 24. Which is called a reflecting code? 25. Is Gray code a weighted code? 26. Which is called a self complementing code? 27. Is EXESSES-3 code a weighted code? 28. What is an ASCII code? 29. What is an EBCDIC code? 30. What is parity checking? 31. What is the difference between encoder and priority encoder? 15EEL 34 Electronics Laboratory Manual

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BTL Institute of Technology EEE Dept. 32. Why Enable input is generally an active LOW signal? 33. What is the difference between de-multiplexer and decoder? 34. What is the role of a multiplexer? 35. Is it possible to realize 4-bit Binary to Gray using a 1:16 de-multiplexer? 36. What are PLD‟s? 37. What is the difference between PAL and PLA? 38. What is the difference between RAM and ROM? 39. Can a PROM be reprogrammed? 40. What is the difference between Static RAM and Dynamic RAM? 41. Is it possible to realize comparator using Multiplexer? 42. What is the difference between LCD and LED? 43. What is the input voltage to a Common Anode LED? 44. Why is a low frequency signal required for an LCD? 45. Why an ordinary decoder is cannot be used with displays? 46. What does RBI, RBO and BI mean? 47. What does a basic bi-stable element mean? 48. What is the forbidden state in SR latch? 49. How contact de-bouncing can be eliminated using SR latch? 50. What is the difference between a latch and a flip flop? 51. What is meant by race around condition? How is it eliminated? 52. How to convert a JK flip flop to a D flip flop? 53. How to convert a JK flip flop to a T flip flop? 54. How to convert a T flip flop to a D flip flop? 55. How to convert a D flip flop to a T flip flop? 56. Why is a D flip flop called as a transparent flip flop? 57. What are the two asynchronous inputs? Why are they called so? 58. What is the difference between synchronous PRESET and asynchronous PRESET? 59. Design a traffic light system where in RED and GREEN do not glow simultaneously. When RED glows GREEN is OFF and when RED glows GREEN is OFF. 60. What is MEALY sequential circuit? 61. What is MOORE sequential circuit? 62. Can a multiplexer be used to realize a JK flip flop? 63. What is the difference between a counter and a register? 64. What is the difference between a synchronous counter and asynchronous 15EEL 34 Electronics Laboratory Manual

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counter? 64. What type of flip flop is used to design a asynchronous counter? 65. In a mod-16 counter, each of the flip flop used has a delay of 20ns. To get an output at the MSB how long does it take in a synchronous counter and in a asynchronous counter? 66. Why is an asynchronous counter called as a ripple counter? 67. Define modulus of a counter. 68. What type of counter is 7490? 69. What type of counter is 74192 and 74193? 70. What type of flip flop is used to design a synchronous counter? 71. What is data lockout in a counter? 72. How is data lockout overcome? 73. Is the output of a counter always a square wave? 74. What is the difference between a shift register and register? 75. Is a shift register a synchronous circuit or an asynchronous circuit? 76. If a ADC is interfaced to a shift register, what type of shifting is preferred? 77. What are the features of a shift register? 78. Do we have a register which can perform all the basic shifting operation? 79. Name a combinational circuit which works similar to a PISO? 80. Name a combinational circuit which works similar to a SIPO? 81. What is a ring counter and a Johnson counter? 82. Is the output of a ring counter a square wave? 83. What is the difference between a self starting ring counter and a counter loaded initially with a parallel data? 84. What happens if 0000 is loaded into a ring counter, provided it is not self starting? 85. If there are 6 states in a ring counter, then how many flip flops are required? 86. If there are 7 states in a Johnson counter, then how many flip flops are required? 87. What is the use of ring counter and Johnson counter? 15EEL 34 Electronics Laboratory Manual

95

BTL Institute of Technology EEE Dept. 88. Is the ring counter a synchronous circuit or an asynchronous circuit? 89. What are the other names by which a Johnson counter is called? 90. Define SET-UP time and HOLD time? 91. If the maximum clock frequency of a JK flip flop is 45Mhz, what happens if 100 Mhz is given? 92. What is meant by active time or triggering time? 93. What is a sequence generator? What is its application? 94. What happens if the states repeat in a sequence generator? 95. Is the sequence generator periodic in nature? 96. What is the difference between a sequence generator and a ring counter? 97. What is the sequence generator made up of? 98. Is the sequence generator a synchronous circuit or an asynchronous circuit?

99. If the length of the sequence to be generated is specified, then what is the name given to such sequence generator? 100. Explain the working of a 555 timer? 101. What is the purpose of a monostable and astable? 102. Why is a monostable called so? 103. Why is a astable called so? 104. What is the use of the two diodes in a astable circuit? 105. Is a trigger input required for a astable? 106. Why doesn‟t triggering pulse affect a monostable output when the capacitor is still charging? 107. What is positive logic? 108. What is negative logic? 109. What are the output voltage ranges for a TTL gate? 110. What are the input voltage ranges for a TTL gate? 111. What is meant by current sourcing and current sinking? 112. Define Fan in? 113. Define Fan out? 15EEL 34 Electronics Laboratory Manual

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114. Define Speed Power product? 115. In the basic circuit of transistor as an inverter, why CE configuration is used? 116. Why Diode-Transistor Logic is not used? 117. What is the advantage of Totempole configuration? 118. What is the disadvantage of Totempole configuration? 119. What is Open Collector configuration? 120. What are the advantages and disadvantages of Open Collector configuration? 121. What are Schottky diodes and transistors? 122. What are the different TTL families? 123. What does 74LS series mean? 124. If the input or output voltages fall in the intermediate range, what happens? 125. What is the difference between FET and MOSFET? 126. What is the difference between FET and BJT? 127. What are the advantages of using MOSFET? 128. Why p-MOS is not used? 129. Why n-MOS is used? 130. Why c-MOS is used? 131. What is the range of voltages that can be given as a input to MOS devices? 132. What is the output range of voltage for a MOS device? 133. What is the application of FET in digital circuits? 134. Compare the performance of different TTL sub families? 135. What is wired AND gate? 136. What is the input impedance of FET? 137. What is the input impedance of MOSFET? 138. What is enhancement MOSFET? 139. What is depletioin mode MOSFET? 140. What is inversion layer in a MOSFET? 141. Why MOS devices are preferred in digital circuits? 142. Give some application of MOS devices in digital circuits.


97

BTL Institute of Technology EEE Dept. APPENDIX – I MAXIMUM RATINGS OF COMMONLY USED TRANSISTORS

BC107 Specifications: 1. Type : Si – NPN 2. operating point temp : 65o to 200oC 3. IC(max) : 100mA 4. hfe (min) = 110 : 100 5. hfe (max) : 450 6. VCE (max) : 45V 7. Ptot(max) : 300mW 8. Category(typical use) : Audio, low power 9. Possible substitutes :BC182, BC547


98

DIODE



99

BTL Institute of Technology EEE Dept. APPENDIX – II COMPONENT VALUE IDENTIFICATION RESISTOR VALUE IDENTIFICATION


100



101

BTL Institute of Technology EEE Dept. STANDARD CAPACITOR VALUES


102

BTL Institute of Technology EEE Dept. APPENDIX – III SYMBOLS

VARIABLES


Gopi 1Lab Manual

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