ENGG2410: Digital Design Lab 2: Xilinx Xilinx ISE Foundation oundation Tools Tools Schematic Schematic Capture: “A Tutorial” Tutorial” School of Engineering, University of Guelph Fall 2013
Start Start Date: Date: Week #3 2013 2013 Due Date: Date: Week #4 2013, In the lab
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Objec Objecti tiv ves: es:
The purpose of this lab is : •
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To learn the basics of the Xilinx ISE Foundation design software: design entry, simulation and automatic synthesis. To enter your design via schematic capture a function of four variables, verify the design via simulation. To get acquainted with large-scale programmable logic device (Field Programmable Gate Array (FPGA)), and learn how to download a circuit onto the device. To implement a function of four variables in hardware using: – SSI logic. – Digilent NEXYS 3 FPGA board.
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Test and debug your design and verify that the software simulation and hardware implementation are correct.
Intr Introdu oduct ctio ion n
The main components you will be using in the digital Design lab are the Xilinx the Xilinx ISE Foundation Software and SSI and SSI Logic. Logic. The lab is composed of several parts: 1. First you will go through through the tutorial tutorial (Design Entry “of Half Adder” using Schematic Schematic Capture (SOE)). (SOE)). You will need to go through this tutorial prior to the lab. (Make sure when you reach the point to map the design on the FPGA to use the (NEXYS 3 Pins UCF file on the web page!!)). page!!)). Let the TA assist you in understanding this file since you will be using it throughout the term. http : //deimos.eos.uoguelph.ca/sareibi/ //deimos.eos.uoguelph.ca/sareibi/T T EACHI NG dr/EN G241 html dr/outline F 2013/docs/LAB dr/LAB 2 dr/tutorials.html
2. Next, Next, you you will go throug through h the tutorial tutorial (Beha (Behavio vioura urall Simula Simulatio tion n of “Ha “Half lf Adder” Adder” Using Xilinx Xilinx iSim iSim (SOE)). This will teach you how to simulate the circuit prior to mapping the design onto an FPGA. This verification step is essential since it will display waveforms of the inputs and outputs of the designed circuit. http : //deimos.eos.uoguelph.ca/sareibi/ //deimos.eos.uoguelph.ca/sareibi/T T EACHI NG dr/EN G241 html dr/outline F 2013/docs/LAB dr/LAB 2 dr/tutorials.html
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3. After understanding the tutorial you will enter the schematic for a small digital circuit: E = (A + B )(AC + D) as shown in Figure 1, and simulate it to check that the circuit you have entered operates correctly. 4. After simulating successfully, you will then implement the hardware : •
Mapping the design onto an FPGA board.
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Verifying the functionality of the design.
5. Lastly, you will check that the hardware implementation functions correctly for Schematic Capture implementation. Xilinx ISE Foundation is a package that provides the designer with a wide variety of tools. These allow digital circuits to be designed and simulated before they are implemented in hardware. A B
A C D
Figure 1: A Simple Combinational Logic Circuit
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Preparation
Design, enter and simulate a circuit using schematic entry that implements the following logic function: E = (A + B )(AC + D ) were the output “E” is the above function of four input variables A,B,C and D. The procedure for implementing this function should be obvious once you have followed the tutorial. You should create, synthesize, download, and test your circuit using the same procedure as in the tutorial. Note: You do not need to perform any sort of hand optimization or logic minimization of the above expression. Xilinx ISE Foundation will perform such optimization automatically. 3.1
UCF File
The UCF file for your 4-input function is: NET NET NET NET NET
A B C D E
LOC LOC LOC LOC LOC
= = = = =
T10; // left most slide switch on the NEXYS 3 board T9; // second slide switch on the NEXYS 3 board V9; // third slide switch on the NEXYS 3 board M8; // fourth slide switch on the NEXYS 3 board U16; // left most LED (light emitting diode) on the NEXYS 3 board
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Requirements
Please read all necessary tutorials on using the Xilinx ISE Foundation Design Tools before starting the lab. These tutorials will attempt to familiarize you with the Xilinx Foundation Software by implementing a simple half adder and full adder using Schematic Capture. When completed, you will hand in the following deliverables, in this order: 1. Title Page. 2. Printed schematic of your function of four variables, with a properly formatted border. Your four inputs should be named A, B, C, D and your single output terminal should be named E. 3. Printed simulation waveform data, showing that the simulation coincides with the expected truth table of your function. 4. OPTIONAL: Printout of the “Map Report” from the Reports section of the Project Manager (check the contents of this file). 5. Final written report describing your results and the procedures used to test your circuit and any problems you encountered during the lab. 4.1
Report
Below is the general format of the report required: 1. Your Group #, and Names 2. Title Page 3. Explain how you implemented each circuit by providing the truth table and logic function. (a) Problem Statement, i. briefly describe the problem solved in the lab. (b) Assumptions and Constraints. i. constraints could be for example using only NAND gates or NOR gates in your design. (c) System Overview & Justification of Design i. Give an overview of the system to be designed. ii. Briefly explain how the system works and reasons behind the design. 4. Circuit Diagram (a) brief explanation of the hardware. (b) for each component give a brief overview, pin-out, pin description as required. (c) any required calculations for hardware components (i.e Resistor values, e.t.c). (d) complete wiring diagram for the system (multiple if necessary). (e) timing diagram if necessary. 5. Error Analysis (a) describe any problems with the system.
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(b) if no problems in the final system, describe problems/errors encountered during the development and how they were resolved. 6. Performance Analysis (a) assess performance of the system (how optimized it currently is, how fast it is, e.t.c). (b) suggest any desired improvements. 7. Any future recommendation for current lab will be appreciated.
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