Implementing the Elevator using VHDL or Verilog based design IP cores.Description complète
Implementing the Elevator using VHDL or Verilog based design IP cores.Full description
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Elevator Controller Implementation
By Abhishek Gupta Varun Aggarwala
Under the guidance of Dr. J.K Deka
Department of Computer Science and Engineering Indian Institute of Technology, Guwahati India December 20th, 2005
Acknowledgements
We are very grateful to our advisor, D. J.K Deka (Asst. Professor IITG), whose guidance has enabled us to understand the various facets of Elevator control and its HDL implementation. His ideas have been a constant source of inspiration and have deeply motivated us to think at a higher level.
Problem statement: To design an Elevator controller for any number of floors.
Algorithm: There are different algorithms that could be used for designing the elevator controller. The important one’s are: 1. elevator algorithm:: Serve the entire request in one direction and then reverse the direction. 2. shortest seek first Serve the request closest to the present floor 3. first come first serve Serve requests as they arrive.
We have used ELEVATOR ALGORITHM. Justification for using elevator algorithm
1. Disadvantages of shortest seek first: Irrespective of the time at which request is placed, it only caters to the request closest to the present floor. th e.g. If someone places a request for 100 floor there are lots of other requests for nearby floor as it is a busy place also if they keep coming . then that person’s request is not at all catered to for a long time . 2. Disadvantages of first come first serve basis e.g. Inefficient as far as power requirements are concerned also more time will be taken on an average to reach the required destination. The elevator algorithm takes care of these two shortcomings
by catering to the request in it’s direction then reverses direction when we reach top floor or there are no more request for the upper floors ;the same is repeated for the downward direction .
IMPLEMENTATION: Behavioral level description of elevator controller in Verilog HDL The behavioral level description of elevator co ntroller was based on elevator algorithm. The implementation was based on the A.S.M (algorithmic state machine) for the problem and its state diagram. The description was based on transfer of con trol from one state to another depending on the present floor of the elevator. We used the concept that the elevator initially checks what the present floor is and then depending on the value of the present floor it transfers the control to state T [2] (used by us in coding) if present floor is zero and to T [3] (used by us in coding) if present floor is the maximum. The control goes to T [4] if present floor is anywhere in between of the two limiting floors. If in state T [2] it caters to the request in upward direction and the opposite if in T [3]. The circuit checks in state T [2] if the present floor becomes destination floor .If it is true than it opens the door for appropriate time and then closes it again and unloads the corresponding value from the queue. The control then goes to T[4] or remains in T[2] depending if there is anymore request to cater to in the upward direction. The circuit checks in state T [3] if the present floor becomes destination floor .If it is true than it opens the door for appropriate time and then closes it again and unloads the corresponding value from the queue. The control then goes to T[4] or remains in T[3] depending if there is anymore request to cater to in the downward direction. The circuit in state T [4] checks: 1: If the direction is upwards of the elevator and if has catered to all the requests in the upward direction and also there is some requ est at a floor lower than the present floor then send the control to T[3] to serve for the request down the present floor. Also if there is no request in a floor lower to the present floor then it checks if some request has come in the floor above the present direction .If true the control is sent back to T[2] else T[1]. 2: If the direction is downwards of the elevator and if has catered to all the requests in the downward direction and also there is some request at a floor above the present floor then send the control to T[2] to serve for the request above the present floor.
Also if there is no request in a floor above the present floor then it checks if some request has come in some floor below the present floor. If true the control is sent back to T [3] else T [1]. Implementation of queue: Queue is defined as input to our main module and is defined as reg in test bench and the value is altered from the test bench.
Gate Level description of elevator controller in Verilog HDL Storing Mechanism: 1. Loading and unloading of the requests should be independent of clock hence a LATCH IS USED AS STORING MECHANISM 2. If we reach floor we should unload the request for that floor. 3. D_LATCH: Standard d-latch is used If control = 0, no change in output If control = 1, the value at input terminal of the latch is loaded The input of the latch is provided as (Floor loading request +the request in that floor)* & (unload request) 4. With two 3 * 8 decoders, load and unload decoders and the above D LATCH and also 1 latch per floor we implement Storing mechanism 5. Clear is uses to preset the value at the output terminal of latch to 0. so that an unknown value is not there at output terminal of the latch Control Circuit: 1. 1 hot assignment is used i.e. 1 flip flop per state is used at any time exactly one state was 1 and rest all were 0. 2. State transitions are synchronized with clock pulse 3. Time period of the clock pulse = time taken by lift to go from 1 floor to another. Inputs of the control circuit 1
2 3. 4.
Supply: If supply is 0 then no state transition takes place it denotes the fact that if Power goes of then lift remains at its present location and whenever we switch on the supply control resumes from the state where the control stopped originally. Clear: It is used to initially load the T [0] state to the flip flop outputs. It is also used to initialize direction of lift. Pfloor: value of the present floor. queue_op: stores the request of the unvisited floors.
Note: States are a direct consequence of state diagram, since we are using One hot assignment Output module T: The value of the states depending on the state as evaluated by control logic, the present floor is either incremented or decremented or remains same. Unload reachfloor: Depending on whether we have reached our destination or not, we unload that floor’s entry from the queue.
Other important variables: 1. xl: It is 1 denotes that there is at least one unattended request for a floor less than equal to it .It is 0 denotes that there is no request that is unattended at a floor less than equal to it .
2. xr: It is 1 denotes that there is at least one unattended request for a floor greater than equal to it . It is 0 denotes that there is no request that is unattended at a floor greater than equal to it. Other calculations: 1. Finding xr: Present floor value is saved in a temporary variable it is fed into a decoder these values are multiplied with the output of the queue .If this value is 0 then increment the value of temporary variable and repeat the process .This process stops only when output after the taking the product of bits of temporary variable comes out to be 1. Also we have to make sure that the value of temporary variable does not exceed 6 and if it reaches 6 it implies that there is no request in the queue above the current flloor. Hence value of xr is set to 0 if floor reaches 6.Else the value of xr is set to 1 if temporary variable does not reach 6 and is stopped in between. 2. Finding xl: Same circuit as above, instead of incrementor we put a decrementor.
Output module: Pfloor: The value of the present floor. Initially we have loaded the present floor value as zero. We have asynchronous clear to clear its value to zero. If supply goes off, then lift remains at the present floor and it starts its function as required the moment the supply is turned on again.
This module basically increments or decrements the value of the present floor depending on its current state at positive edge of the clock.
Comments The code can be made to work for any number of floors by using the appropriate decoder.
References:
rd
1:M. Morris Mano: Digital Design 3 edition: Prentice Hall of India. 2: Palnitkar, S: Verilog HDL: A Guide to Digital Design and Synthesis: SunSoft Press (A Prentice Hall Title) 3: Thomas D.E and P.R Moorby: The Verilog hardware Description Language: 4th edition: Kluwer Academic Publishers. 4: Enhanced Verilog Tutorial with applications from aldec.com
