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Computer Hardware and System Software Concepts Introduction to Computer Architecture

Course Objective To introduce fundamentals of Computer Architecture To introduce the concepts of System Software. To introduce the concepts of Operating Systems. To introduce the concepts of Computer Networks.

ER/CORP/CRS/OS09/003

Course Objective To introduce fundamentals of Computer Architecture To introduce the concepts of System Software. To introduce the concepts of Operating Systems. To introduce the concepts of Computer Networks.


References Andrew S. Tanenbaum: Structured Computer Organization , Organization , PHI, 3rd edition, 1991. Concepts , 4th Silbers Silberscha chatz tz and Galvin Galvin:: Operating System Concepts , edition, Addison-Wesley Pub, 1995. Andrew S. Tanenbaum: Computer Networks , PHI, 1991. Alfred V.Aho, Ravi Sethi, Jeffrey D.Ullman: Compilers - Principles, Techniques and Tools , Na Naro rosa sa Publ Publis ishi hing ng House, 1986. ER/CORP/CRS/OS09/003

Session Plan Day 1 – Crea Create te a bac backg kgro roun und d – Main Main compo componen nents ts o off comput computer er archi architec tectur ture e – Di Diff ffer eren entt addr addres essi sing ng mod modes es Day 2 – In Intr trod oduc uce e Sys Syste tem mS Sof oftw twar are e – Int Introd roduce uce Operat Operating ing Syste Systems/ ms/Mem Memory ory Manage Managemen mentt


Session Plan Day 3 – In Intro trodu duce ce Pro Proce cess ss Man Manag agem emen entt – In Intr trod oduc uce e Fil File e Man Manag agem emen entt Day 4 – In Intr trod oduc uce e Devi Device ce M Man anag agem emen entt – In Intro trodu duce ce Com Compu pute terr Netw Networ orks ks


Background What is a Computer? – Is an electronic device used to • Store • Retrieve and, • Process data. – To process data a set of instructions need to be given to the computer. What is a Program? – Is a set of instructions. ER/CORP/CRS/OS09/003

Computer Architecture Is concerned with the structure and behavior of the computer as seen by the user/programmer. It includes attributes such as – Instruction Formats – Addressing Modes – Instruction Sets – I/O Mechanisms


Computer Architecture Main components in a computer system Hardware Software Firmware


Organization of a simple computer

•Central Processing Unit (CPU) •Main Memory •Input / Output devices •Bus ER/CORP/CRS/OS09/003

CPU (Processor) What is it? Brain of the computer Function – Fetch instructions from memory – Examine – Execute Consists of 3 functional units – Control Unit (CU) – ALU – Registers ER/CORP/CRS/OS09/003

CPU – Functional Units CPU

Control Unit

 Fetches Instructions from memory  Interprets the instructions Performs arithmetic operations Performs Logical operations Very high speed memory units in the CPUfor storing very small amount of data.

ALU

Registers

Examples

•Program Counter (PC) •Instruction Register (IR) •Memory Address Register (MAR) •Memory Buffer Register (MBR) •Accumulator (A) ER/CORP/CRS/OS09/003

Examples of CPU (Processor) Intel Processors

Motorola Processors

8088

68000

80286

68020

80386

68030

80486 Pentium


Memory MEMORY

Internal

Main

Cache

Secondary

Memory

Memory

Memory

Memory

RAM

ROM

Internal

External

Cache

Cache


Memory – Internal Memory

In the form of Registers Registers are small memory units internally available within the CPU. Volatile/Non volatile Memory


Memory - Primary or main Memory Volatile/Non volatile Memory

Main Memory

l y n O r y d a m o e R e M

s s c e c A m o o r y d n R a M e m


Memory - Cache Memory A memory placed between CPU and main memory Contains a copy of the portion of main memory Processor when needs some information first checks cache If not found in cache, the block of memory containing the needed information is moved to the cache

CPU

Cache

Main Memory ER/CORP/CRS/OS09/003

Memory - Secondary memory devices Type

Hard disk

Floppy disk

CD ROM

CD Read/ Write

Description

These are placed separately along with the CPU (in the cabinet) and are usually not portable. The Floppy disks are portable. These come in smaller sizes compared to Hard Disk. Compact Disc, Read Only Memory (CD-ROMs) are portable. These are typically read-only, meaning they could be used only to read the contents. This is simillar to CD-ROMs except that it is also used to write the information on to the special CD-ROM which are of Read-Write type.

Readable

Writable

Typical size 40 GB 80 GB

Yes

Yes

Yes

Yes

1.44

Yes

No

650700MB

Yes

Yes

650-700 MB

MB


Comparison of different types of memory Storage type

Implementation Features

Con tents

Ex ample

Typical Siz e

Internal Memory

Very high speed devices, located within CPU(chip); expensive, and volatile. Very costly, hence limited in capacity.

Holds instructions under execution and associated data item.

Registers, Internal Cache memory

Registers will be few in number. The internal Cache could be 256 KB or 512 KB

Primary Memory

High speed devices (but slower than the internal CPU registers) located outside the CPU (on the motherboard), Less costlier compared to internal memory. Usually larger in capacity.

Entire (almost) program contents being executed; holds small volume of data.

RAM (volatile), ROM (Non volatile), External Cache Memory

256 MB 512 MB

Secondary Memory

Low speed, Nonvolatile, low cost. Huge in capacity.

Programs not currently being executed; holds large volume of data

Hard Disk, Compact Disks(CDs), Floppy disks

40GB 80 GB


Memory hierarchy


Bus Parallel wires that carry several bits at a time Carries instructions, data, addresses or commands Unidirectional or bi-directional Major Categories – Data bus – Address bus – Control bus

Bus width and Bus speed are the two major components for performance measure.


Different types of registers Categories:General Purpose Registers – are those which are used by the programmer to store data. – all CPUs will have one register called Accumulator.

Special Purpose Registers – The special purpose registers are used by the CPU for temporary storage of data for calculations and other purposes. – Ex.: •

MAR

•

MBR

•

IR

•

PC


Registers, CPU and the memory


Harvard Architecture

- Data & program stored separately.

The Advantages of this architecture is the clear separation of the data region and the code region. Also the separate data and program busses are used, hence speeding up the process. Disadvantages could be the separate mechanisms to fetch data and the programs. ER/CORP/CRS/OS09/003

Von Neumann architecture Data & Program, both stored in the same place.

The Advantages of this architecture is that it treats data and programs alike meaning the same mechanisms to fetch data and the programs. The disadvantage is the same bus used for both program as well the data leads to so called Von Neumann bottleneck. ER/CORP/CRS/OS09/003

Von Neumann architecture - characteristics One processor Use of stored programs Sequential processing of instructions Single Instruction, Single Data stream (SISD) mode


Execution of the Instructions The execution process of the instruction stored in the memory happens in three phases. Fetch Phase: In this phase the instructions retrieved picked from the memory. Decode Phase: Once the instructions are retrieved these are decoded by the CU. Execute Phase: Once the instructions are decoded, they are executed by the ALU (in case they are Arithmetic instructions).


Fetch-decode-execute cycle Memory

ADD R1,R2 CPU Control Unit

Instruction Decoder

Special Registers

5000

Program Counter MAR

R1

. . .

Instruction Register

ALU

R2

MBR

GPR R3

1A . . . . .

R4


Fetch-decode-execute cycle Fetch Phase Decode Phase Execute Phase


Fetch phase Contents of PC are transferred to MAR Main memory is accessed and current instruction is fetched into MBR Instruction is transferred from MBR to IR


Decode phase Opcode of the instruction is decoded Contents of PC are incremented by 1(in case of 1 byte instruction or equal to the no. of bytes of the instruction currently being executed.) Execution phase follows ( specific to the given instruction )


Execute phase Execute the instruction Store the results in the proper place (go to the fetch phase to begin executing the next instruction)


Fetch-decode-execute cycle-Example 2


Instruction categories Arithmetic Instructions –

Ex.: Add, Sub, Mul etc.

Logical instructions –

Instructions doing comparison operations.

Program Control instructions –

Ex.: Jump to some memory location where the code is place & return etc.

I/O instructions –

Ex.: In, Out

Data Transfer instructions –

Register-Memory / Memory-Register

–

Register-Register

–

Memory-Memory.


Instruction categories (Cont…)

Data Transfer instructions

Register-Memory / Memory-Register Central Processing Unit (CPU)

Register-Register

Control Unit

Memory-Memory. y o r e m m o t y r o m y e M o r

Arithmetic Logic Unit (ALU) From Memmory to Registers

e m M

From Registers to Memory

R1

R2

R3

R4

MAR

MBR

IR

PC

REGISTERS


Variations of CPU Architecture SISD SIMD MIMD MISD


I/O devices Why needed? O/P Devices:

Monitor

Printer


I/O devices Input Devices:-

Mouse

Keyboard


I/O devices Input/Output Devices


Measures of CPU performance MIPS - is a measure of the speed of the processor. Clock Speed – is another metric used to measure performance. FLOPS – is a measure of the speed of the Floating Point Unit (FPU) which is a co-processor unit.


Addressing A way of accessing memory locations which contain the data for processing Modes of addressing – Implied Addressing – Immediate Addressing – Direct or Absolute Addressing – Relative Addressing – Indirect addressing


Implied Addressing Operands are specified implicitly in the definition of the instruction Instruction specifies a fixed and unvarying address Example:- DEC (Decrement A register) 1. The CU decodes the instruction (fetch and decode phase) 2. The CU then fetches the contents of the register A 3. The value of the A will be transferred to the ALU 4. The ALU then decrements this value and updates the register A ER/CORP/CRS/OS09/003

Immediate addressing In it, data is a part of instruction itself. Example:- MOVE #100H, R1 • Here the data 100h is moved to R1. The following steps are involved in the execution of this instruction. – The CU decodes the instruction (fetch and decode phase) – The data 100H available with the instruction is sent to Register R1. R1 Control Unit 2 1

MOVE

#100H

R1


Direct (Absolute ) addressing The address where data is available is part of the instruction Ex.: MOVE 30A4, R1

Control Unit

3

R1

30A4

75

1

MOVE

30A4H

R1

2


Problem with Direct Addressing


Indirect Addressing Problem of direct addressing :the change in the location of the program is associated with the change in all absolute memory references. Solution : is to represent the address of the data indirectly. There are two ways to do it: – 1) Register Indirect Addressing : the address of the data is stored in a Register. – 2) Memory Indirect Addressing : the address of the data is stored in another memory location


1) Register Indirect Addressing : Ex.: MOVE [R2], R1 Memory

Control Unit

2

R2

3 30A4

75

1 4 MOVE

[R2]

R1

R1

The register R2 is assumed to be pre- loaded with a value of 30A4 ER/CORP/CRS/OS09/003

1) Memory Indirect Addressing : Ex:

MOVE [ 7010 ], R1


Problems with Indirect Addressing


Base - Indexed Addressing Ex.: MOVE [BX] + [Ri], R1.

3

Memory

4 +

3

ADDER (ALU)

3000

3000

20A4 20A4

Base Register (BX)

Index Register Ri

2

1 MOVE

hold the Base value of the program.

[BX]

holds the Offset (relative) address.

[Ri]

75

75

50A4

R1

5

R1 ER/CORP/CRS/OS09/003

Problem with usage of shared memory


Segment Register Addressing


Segment Register Addressing

4

3

3

+

1000

Segment Register (SR)

50000 1000

100

Base Register (BX)

Segment1 (code)

3

ADDER (ALU)

50000

Memory

51000

Index Register Ri

1

Segment2 (Data)

100

2

75

51100

0

Segment3

MOVE

[SR]

[BX]

[Ri]

R1

5

75 R1 ER/CORP/CRS/OS09/003

Summary Background Components of a computer system Von Neumann architecture Fetch Decode Execute Cycle Memory I/O devices Bus Addressing Modes


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