Pulse Width Modulator Circuit EEE 54 Design Problem 2
Leiko Armand L. Ravelo BS Computer Engineering University of the Philippines Diliman 2013-14856
—This is a documentation on the second design Abstract problem in EEE 54. We were tasked to create a PWM modulator circuit with sawtooth waveform generated by a free-running ramp as a sampling signal. Specifications regarding our circuit include sawtooth waveform frequency, minimum and maximum voltages.
I.
CALCULATIONS AND SIMULATION
The specifications assigned for the PWM modulator are shown below.
!"#$%&'( !"#$%&'( )! * +! ,-'./'012( 3456 * 78+456 The circuit comprises of different modules as shown below.
R 1 simulates the load being driven, which is the positive terminal of the comparator. R 2 is added to limit the current draw of the input due to the op-amp non-idealities. C 1 was set so that the discharge time due to loading would be negligible. When V- > V+, the op-amp output is negative which changes the bias of the diode from forward to reverse biased. The capacitor then discharges with a time constant of:
9 : ;< => : )8+? @ A8A)? CD E )AA56F Lastly, R 3 and R 4 set the appropriate DC value to raise the signal. Since V +=Vmin=1V:
!G : ) :
=H =H I = J
K)3
When R 4=1k , the equation above would yield R 3=11k . A simulation of the Clamper input and output is shown in the figure below.
Figure 1: PWM Circuit components
A high slew rate IC was used for the comparator while op amp circuits were used for the clamper and the free-running ramp generator. A. Clamper Figure 3: Clamper Simulation
Figure 2: Op-amp clamper circuit
B. Bootstrap Ramp Generator The next part of the circuit would be the free-running ramp, consisting of the bootstrap ramp generator and a Schmitt trigger in a feedback loop. The following figure shows the bootstrap ramp generator part of the circuit.
through the use of a 10k ! potentiometer. At that point, the frequency should be 2kHz.
) WL ) W<
:
:
3456 )
78+456
U: U: ):
)
: )VV8VVX?
)A8V! Y +AAX? C)A4 I =F Y ;L )A8V! Y )VVX?
+AA= )VV )A4Z I =
;L :
: +AAX?
)A8VK)VVX? V8V4ZKU
= Y ;L O = : V8[3V4Z \ ]8 ]^_ : )AV87`0, \ abbcd
;< : )A;L : aed Figure 4: Bootstrap ramp generator
A PNP transistor (Q1), connected to the Schmitt trigger output, was used to switch the ramp generator. A 120k ! resistor was used as a base resistance of the switching transistor.
C. Schmitt Trigger The Schmitt trigger part of the free-running ramp is shown below.
When transistor Q1 turns off, C1 would start charging u p C2 through R 6. In order to maintain the linearity of the ramp, the voltage across C1 must be kept constant as much as possible. This can be done by setting C1 to a value much greater than C2.
;< : )A;L Since the bootstrap ramp generator is designed to be part of a free-running ramp, its initial output then should be 1V. At that point, the Schmitt trigger would have switched-off Q1, constantly charging up C2 until 5V. The pertinent capacitor equation is shown below.
!:
) ;
M N$ O ! :
P$ ;L
:
!Q< $ =R ;L
!S * !T : + * ) : U! !Q< : )3 * A87 * ) : )A8V! The minimum value of R6 is R, which would give the maximum frequency (7.5kHz). R6 can be swept up to R+10k !
Figure 5: Schmitt Trigger
R3 and R4 set the V LTP of the circuit while R1 and R5 set the VUTP. The pertinent equations are shown below.
!>fg : !hTi : )!
The output of the free-running ramp, and the clamper will be connected to the inputs of a high slew-rate comparator. This part was no longer simulated.
!jfg : !hkl : +! !>fg I !m : )87! :
=H =H I = J
K)3
=H \ a8 no_ Cpqr8 stuF =J \ abo_ (std. val) !hkl : +! : +! :
=v =v I =< =v =v I =<
KC!wxy * !m F ))8V!
=v \ z8 ao_ Cpqr8 stuF =< \ {8 |o_ Cpqr8 stuF
Figure 8: Comparator circuit, V EE is grounded
II. ACTUAL CIRCUIT Changes were made on the resistance values used in the actual circuit to further fine-tune its output with the desired specifications. The changes can be seen in the figure below.
Upon simulating the free-running ramp, adjustments were made on the resistor values to compensate for the unaccounted non-idealities, like the voltage drop across the Schmitt trigger output due to the loading of the transistor Q1 and resistors R1 and R5. Figure 5 shows the actual resistor values used in the simulation. The simulation output is shown below.
Figure 9: Final free-running ramp used
The following ICs were used for certain parts of the circuit: -Clamper: LF353 -Bootstrap ramp generator: LF353 Figure 6: Bootstrap ramp and Schmitt Trigger output at R=13.3k
-Schmitt Trigger: LF353 -Comparator: LM393 Problems were encountered in the final output of the circuit as the comparator output produce d slew rate. As such, the PWM signal quality degrades at high (>90%) and low (<10%) duty cycles. The next images show the output of the final free-running ramp, as well as the PWM signal produced at the comparator output.
Figure 7: Bootstrap ramp and Schmitt Trigger output at R=3.3k
Figure 10: Free-running ramp output at 1.94kHz
Figure 12: PWM signal produced, shown in pink
R EFERENCES [1]
Figure 11: Free-running ramp output at 7.48kHz
Bell, David. (1976). Solid State Pulse Circuits, 1 st edition
