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DUAL-PORT MEMORY BLOCK DIAGRAM.pdf
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DUAL-PORT MEMORY BLOCK DIAGRAM.pdf
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DUAL-PORT MEMORY BLOCK DIAGRAM DATA
CPU
L
R
DATA I/O
DATA I/O
DATA
CPU
OR
OR
I/O
DEVICE ADDRESS
"L"
L ADDRESS DECODER
R/W
BUSY, INTERRUPT, SEMAPHORE
DUAL/PORT RAM MEMORY CELLS
CONTROL LOGIC
R
ADDRESS
ADDRESS DECODER R/W
I/O DEVICE
"R"
BUSY, INTERRUPT, SEMAPHORE
1
DUALL-PORT RAM CELL L SIDE WRITE DRIVERS
L SELECT (DECODED ADDRESS) L WRITE
E N I L T I B A T A D L
R SIDE WRITE DRIVERS
WR 1
WR 1
WR 0
WR 0
RD
R SELECT (DECODED ADDRESS) R WRITE
RD
E N I L T I B A T A D R
RAM CELL LATCH
L SIDE READ DRIVERS
R SIDE READ DRIVERS
2
DUALL-PORT RAM CELL - Read L SIDE WRITE DRIVERS
L SELECT (DECODED ADDRESS) L WRITE
E N I L T I B A T A D L
R SIDE WRITE DRIVERS
WR 1
WR 1
WR 0
WR 0
RD
R SELECT (DECODED ADDRESS) R WRITE
RD
E N I L T I B A T A D R
RAM CELL LATCH
L SIDE READ DRIVERS
R SIDE READ DRIVERS
3
DUALL-PORT RAM CELL - Write L SIDE WRITE DRIVERS
L SELECT (DECODED ADDRESS) L WRITE
E N I L T I B A T A D L
R SIDE WRITE DRIVERS
WR 1
WR 1
WR 0
WR 0
RD
R SELECT (DECODED ADDRESS) R WRITE
RD
E N I L T I B A T A D R
RAM CELL LATCH
L SIDE READ DRIVERS
R SIDE READ DRIVERS
4
DUALL-PORT RAM Interrupt Logic L SIDE WRITE INTERRUPT TO R SIDE
L SIDE ADDRESS
ADDRESS = 3FF ADDRESS = 3FE R SIDE READ
L SIDE READ ADDRESS = 3FF ADDRESS = 3FE
R SIDE ADDRESS
INTERRUPT TO L SIDE R SIDE WRITE
5
DUUALL-PORT RAM Busy Logic ADDRESS (L)
DELAY BUFFER DELAY BUFFER
ADDRESS EQUAL COMPARATOR
ADDRESS EQUAL COMPARATOR
CE (L)
BUSY (L)
ADDRESS (R)
CE (R)
L
R
A
B
WRITE INHIBIT (L)
BUSY (R)
WRITE INHIBIT (R)
6
DUAL-PORT RAM Semaphore Logic DATA
CPU
L
R
DATA I/O
DATA I/O
DATA
CPU
OR
OR
I/O DEVICE
"L"
ADDRESS
R/W
SEMAPHORE SELECT
L ADDRESS DECODER
DUAL/PORT RAM MEMORY CELLS SEMAPHORE CELLS
R ADDRESS DECODER
ADDRESS
I/O DEVICE
R/W
"R"
SEMAPHORE SELECT
7
DUAL-PORT RAM Semaphore Logic8cell L D-LATCH L REQUEST
R D-LATCH
D
1
1
Q
L WR SEMAPHORE
D
R REQUEST
E
R WR SEMAPHORE
Q
E
GRANT (L)
GRANT (R) SEMAPHORE ARBITRATION LATCH
8
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