RAGHU INSTITUTE OF TECHNOLOGY Dakamarri (vill), Bheemunipatnam Mandal, Visakhapatnam Dist, Andhra Pradesh, PIN- 531162 (Approved by AICTE, New Delhi, and Affiliated to Jawaharlal Nehru Technological University: Kakinada(AP)
st
2015-2016: III B.Tech ECE: 1 Semester
LABORATORY MANUAL
For
Digital System Design & DICA Laboratory Student Manual Prepared by BSSV RAMESH BABU, M.Tech
Associate Professor
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
RAGHU INSTITUTE OF TECHNOLOGY (Affiliated to JNTU-KAKINADA) Visakhapatnam-531162
CERTIFICATE
Name of the Laboratory
:
Digital System Design & DICA Laboratory
Name of the Faculty
:
Mr. B.S.S.V.Ramesh Babu
Department
:
Electronics and Communication Engineering
Program
:
B.Tech
Year
:
III Year
Semester
:
I Semester
IQAC Members
Name Signature(s)
: :
HOD - ECE
RAGHU INSTITUTE OF TECHNOLOGY (Affiliated to JNTU-KAKINADA) Visakhapatnam-531162
CERTIFICATE
Name of the Laboratory
:
Digital System Design & DICA Laboratory
Name of the Faculty
:
Mr. B.S.S.V.Ramesh Babu
Department
:
Electronics and Communication Engineering
Program
:
B.Tech
Year
:
III Year
Semester
:
I Semester
IQAC Members
Name Signature(s)
: :
HOD - ECE
CONTENTS S.NO
DESCRIPTION
PAGE NO
1.
Course Description
i
2.
General Instructions
v
3.
Additional Instructions
vi
4.
University Syllabus
vii
5.
List of Experiments
viii
6.
Cycle-Wise List of Experiment
ix
7.
Realization of Logic Gates
11
8.
3 to 8 Decoder-74138
23
9.
8X1 Multiplexer-74151 and 2X4 Dermultiplexer-74155
28
10.
4-Bit Comparator-7485
36
11.
D-Flip-Flop-7454
41
12.
Decade Counter-7490
45
13.
4-Bit Counter-7493
50
14.
Shift Register-7495
55
15.
Universal Shift Registers-74194/95
60
16.
RAM (16X4)-74189(Read and Operation)
65
17.
Stack and Queue implementation using RAM
68
18.
ALU design
71
ADDITIONAL EXPERIMENTS 19.
Adders (Half adder & Full adder)
76
20.
8 X 3 Encoder
83
21.
T-Flip-Flop
89
COURSE DESCRIPTION Course Context and Overview: The course consists of laboratory tasks dealing with Digital Circuits. This is a rigorous introductory laboratory course in Electronics and Communication Engineering. It is a credit based laboratory course designed as a supplement to the Digital IC Applications theory course. The software Xilinx is used to design any type of digital circuits and this laboratory will be helpful to do the front end design of digital circuits. After verifying the design in the software the designer will move to back end for production of physical device. Course Prerequisites: Digital IC Applications Literature Faculty Manual Books Recommended: Text Books: 1. John F. Wakerly., J. Bhasker. Weste and Eshraghian Reference Books: 1. Digital System Design Using VHDL – Charles H. Roth Jr., PWS Publications,1998.
2. Introduction to Logic Design – Alan B. Marcovitz,TMH,2nd Edition,2005. 3. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P. Uyemura, Thomson Learning. 4. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
Programme Educational Objectives
PEO No.
Programme Educational Objectives
PEO 1
Our graduates will be productive in the professional practice and obtain employment.
PEO 2
Our Graduates will function effectively as individual and within a team with good leadership qualities.
PEO 3
Our Graduates will recognize the need for continuous self-improvement and with good moral values.
Programme Outcomes PO No.
Programme Outcomes
a
An ability to apply knowledge of mathematics, science and engineering
b
An ability to design and conduct experiments, as well as to anal yze and interpret data
c
An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety
d
An ability to function on multidisciplinary teams
e
An ability to identify, formulate, and solve engineering problems
f
An ability to understanding of professional and ethical responsibility
g
An ability to communicate effectively
h
The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental, and societal context A recognition of the need for, and an ability to engage in life-l ong learning
i j
A knowledge of contemporary issues
k
An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice
l
An ability to implement MATLAB, Embedded systems design for electronics and communications engineering applications.
Course Objectives : To expose the students to basic principle of operation of Digital Circuits with experimental experience and also to impart industry oriented lea rning. Course Outcomes: S.No Course Outcomes 1
2
3 4
Student gains knowledge about simulation of design of logic gates using VHDL Programming Language on Xilinx Software Package Student gains Knowledge about simulation of design of 8 x 1 Multiplexer – 74151 and 2 x 4 de-multiplexer 74155 using VHDL Programming Language on Xilinx Software Package Student gains Knowledge about simulation of design of D-Flip Flop 7474 using VHDL Programming language on Xilinx Software package Student gains Knowledge about simulation of design of Shift registers using VHDL Programming language on Xilinx Software package
Mapping of Course Outcomes to Programme Outcomes and Programme Educational Objectives
S.No
Programme Outcomes
Course Outcomes
Student gains knowledge about simulation of design of logic gates using VHDL Programming Language on Xilinx Software Package Student gains Knowledge about simulation of design of 8 x 1 Multiplexer – 74151 and 2 x 4 de-multiplexer 74155 using VHDL Programming Language on Xilinx Software Package Student gains Knowledge about simulation of design of DFlip Flop 7474 using VHDL Programming language on Xilinx Software package Student gains Knowledge about simulation of design of Shift registers using VHDL Programming language on Xilinx Software package
1
2
3
4
Programme Educational Objectives
A
PEO I
B
PEO I
B
PEO I
A
PEO I
Assessment Strategy
A variety of learning strategies are used throughout the course. S.No
Teaching Learning and Assessment Strategy
2
Classroom Demonstration by Faculty In charge through Methodologies Extra Laboratory Session
3
Student- Faculty In charge Discussion
4
Collaborative and Co-operative learn
5
Independent student study and Practice
1
different Teaching
Evaluation of Marks for the Laboratory Exam Internal Marks - 25 For Laboratory courses there should be continuous evaluation during the semester for 25 Internal Marks. The distribution of Internal Marks is given below. Serial No 1 2 3
Criteria Day to Day Work
Marks 10
Record Internal Examination
5 10
External Lab Exam - 50 Each semester end lab Examination shall be evaluated by an External Examiner along with an Internal Examiner. Serial No 1
Criteria Pre practical
Marks 30
2 3
Practical Post practical
10 10
4
Viva
10
Total Marks
50
Total Lab Exam Marks - 75 Each semester Total Final lab Examination marks is the sum of marks obtained in both internal and external Exams. Serial No 1
Criteria Internal
Marks 25
2
External
50
Total Marks
75
GENERAL INSTRUCTIONS SAFETY: 1. When students are doing experiment they have to be very care full.
2. Students should have the prior knowledge about the lab they are doing. 3. If any kind of wrong thing happened while doing the experiment. Students have to immediately switch off power supply on the work table. 4. Wearing loose garments inside the lab is strictly prohibited .
ATTENDANCE:
1. Students have to come to the laboratory with proper dress code and ID Cards. 2. Students have to bring Observation note book , Record note book and calculators etc.. to the Laboratory. 3. Students have to sign in the log register after entering into the lab and before leaving the laboratory. 4. Students have to show their observations with results after completion of their experiments and they have to get is signed.
DOING EXPERIMENTS:
1. First write the code for the logic circuits what need to design. 2. After completing the code , check the syntax for finding the errors. 3. If errors are present, correct the code with proper syntax. 4. After correcting the code, output timing diagrams are observed by simulation. 5. RTL schematic diagram and look up tables is observed.
RECORD:
1. As the name Implies, it is a record: permanent record for reference. Write neatly; Draw circuit diagrams neatly and label correctly. 2. Complete the record before you come for next lab class. 3. Bring the record for submission during next lab class.
ADDITIONAL INSTRUCTIONS 1. Before entering into the laboratory class, you must be well prepared for the experiment that you are going to do on that day. 2. You must bring the related textbook, which may deal with the relevant experiment. 3. Get the circuit diagram approved with correct meter & fuse ratings 4. Get the reading verified. Then inform the technician so that supply to the worktable can be switched off. 5. You must get the observation note corrected within two days from the date of completion of experiment. 6. Write the answer for all the discussion questions in the observation note. If not, marks for concerned observation will be proportionately reduced. 7. If you miss any practical class due to unavoidable reasons, intimate the staff in charge and do the missed experiment in the repetition class. 8. Such of those students who fail to put in a minimum of 75% attendance in the laboratory class will run the risk of not being allowed for the University Practical Examination. They will have to repeat the lab course in subsequent semester after paying prescribed fee. 9. Girls should put their plait inside their overcoat. 10. Acquire a good knowledge of the surrounding of your worktable. Know where the various live points are situated in your table. 11. In case of any unwanted things happening, immediately switch off the mains in the worktable. The same must be done when there is a power break during the experiment being carried out. 12. Avoid carrying too many instruments at the same time. 13. Avoid using water hydrant for electrical fires. 14. Avoid wearing any loose metallic rings, straps or bangles, as they are likely to prove dangerous at times.
LIST OF EXPERIMENTS RECOMMENDED BY JNTU KAKINADA
JAWAHARLAL TECHNOLOGICAL UNIVERSITY KAKINADA ELECTRONICS AND COMMUNICATION ENGINEERING
III Year B.Tech ECE I Semester
T P C 0 3 2
DIGITAL SYSTEM DESIGN & DICA LABORATORY Simulate the internal structure of the following Digital ICs using VHDL and verify the operations of the Digital ICs(Hardware) in the Laboratory.
1.
Gates
2.
3-8 Decoder – 74138
3.
8X1 Multiplexer – 74151 and 2X4 Demultiplexer 74155
4.
4-Bit Comparator – 7485
5.
D- Flip-Flop - 7474
6.
Decade Counter – 7490
7.
4-Bit Counter – 7493
8.
Shift Register – 7495
9.
Universal Shift Registers – 74194/195
10.
RAM (16X4) – 74189 (Read and Write operations)
11.
Stack and Queue Implementation using RAM.
12.
ALU design
LIST OF SELECTED EXPERIMENTS FROM JNTUK RECOMMENDED
i.Introduction of ISE Quick Tutorial 1. Realization of Logic Gates 2. 3 to 8 Decoder-74138 3. 8X1 Multiplexer-74151 and 2X4 Dermultiplexer-74155 4. 4-Bit Comparator-7485 5. D-Flip-Flop-7454 6. Decade Counter-7490 7. 4-Bit Counter-7493 8. Shift Register-7495 9. Universal Shift Registers-74194/95 10. RAM (16X4)-74189(Read and Operation) 11. Stack and Queue implementation using RAM 12. ALU design LIST OF ADDITIONAL EXPERIMENTS DESIGNED
1. Adders (Half adder & Full adder) 2. 8 X 3 Encoder 3. T-Flip-Flop
CYCLE-WISE LIST OF EXPERIMENTS I – CYCLE
i.Introduction of ISE Quick Tutorial 1. Realization of Logic Gates 2. 3 to 8 Decoder-74138 3. 8X1 Multiplexer-74151 and 2X4 Dermultiplexer-74155 4. 4-Bit Comparator-7485 5. D-Flip-Flop-7454 6.
T-Flip-Flop
7. Adders (Half adder & Full adder)
II – CYCLE
8. Decade Counter-7490 9. 4-Bit Counter-7493 10. Shift Register-7495 11. Universal Shift Registers-74194/95 12. RAM (16X4)-74189(Read and Operation) 13. Stack and Queue implementation using RAM 14. ALU design 15. 8 X 3 Encoder
I .I ntroduction of I SE Quick Start Tutorial
Getting Started
For Windows users, start ISE from the Start menu by selecting: i. Start _ Programs _ Xilinx ISE 12.1 _ Project Navigator ii. The ISE Project Navigator opens. The Project Navigator lets you manage the sources and processes in your ISE project. iii. All of the tasks in the Quick Start Tutorial are man aged from within Project Navigator. Stopping and Restarting a Session i. At any point during this tutorial you can stop your session and continue at
a later time. ii. To stop the session: •
Save all source files you have opened in other applications.
•
Exit the software (ISE and other applications).
iii. The current status of the ISE project is maintained when exiting the software. iv. To restart your session, start the ISE software again. ISE displays the contents and state of your project with the last saved changes. Accessing Help
At any time during the tutorial, you can access online help for additional information about a variety of topics and procedures in the ISE software as well as related tools.
i. To open Help you may do either of the following: ii. Press F1 to view Help for the specific tool or function that you have selected or highlighted. iii. Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.
Creating a New Project in ISE
In this section, you will create a new ISE project. A project is a collection of all files necessary to create and to download a design to a selected FPGA or CPLD device.
To create a new project for this tutorial: 1. Select File > New Project. The New Project Wizard appears. 2. First, enter a location (directory path) for the new project. 3. Type tutoria l in the Project Name field. When you type tutorial in the Project 4. Name field, a tutorial subdirectory is created automatically in the directory path you selected. 5. Select HDL from the Top-Level Module Type list, indicating that the top-level file in your project will be HDL, rather than Schematic or EDIF. 6. Click Next to move to the project properties page. Fill in the properties in the table as shown below Device Family: Spartan 3E Device: XC3S500E Package: FG320 Speed Grade: .-5 Top-Level Module Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog)
Generated Simulation Language: VHDL or Verilog , depending on the language you want to use when running behavioral simulation.
When the table is complete, your project properties should look like the following:
Fig.i.1 Device Properties for new project
Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be created.
Creating an HDL Source
In this section, you will create a top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the
“Creating a VHDL Source” section below
Fig.i.2 selecting source type
This simple AND Gate design has two inputs: a and b. This design has one output called c 1. 2. 3. 4. 5. 6.
Click New Source in the New Project Wizard to add one new source to your project. Select VHDL Module as the source type in the New Source dialog box. Type in the file name and gate. Verify that the Add to project checkbox is selected. Click Next. Define the ports for your VHDL source.
“Creating a VHDL entities” section below
Fig.i.3 Entities defining
• • •
In the Port Name column, type the port names on three separate rows: a, b and c. In the Direction column, indicate whether each port is an input, output, or inout. For a, b select in from the list. For c select out from the list.
1. Click Next in the Define VHDL Source dialog box. 2. Click Finish in the New Source Information dialog box to complete the new source file template. 3. Click Next in the New Project Wizard. 4. Click Next again. 5. Click Finish in the New Project Information dialog box. 6. ISE creates and displays the new project in the Sources in Project window and adds the andgate.vhd file to the project. 7. Double-click on the andgate.vhd file in the Sources in Project window to open the VHDL file in the r. The andgate.vhd file contains: Header information. o Library declaration and use statements. o
Entity declaration for the counter and an empty architecture statement. 8. In the header section, fill in the following fields: Design Name: andgate.vhd Project Name: andgate Dependencies: None Note: It is good design practice to fill in the header section in all source files. o
9. Below the end process statement, enter the following line: C <= A and B; 10. Save the file by selecting File > Save. Checking the Syntax of the New Counter Module
When the source files are complete, the next step is to check the syntax of the design. Syntax errors and typos can be found using this step. a. Select the counter design source in the ISE Sources window to display the related processes in the Processes for Source window. b. Click the “+” next to the Synthesize-XST process to expand the hierarchy. c. Double-click the Check Syntax process. d. When an ISE process completes, you will see a status indicator next to the process name. • If the process completed successfully, a green check mark appears. • If there were errors and the process failed, a red X appears. • A yellow exclamation point means that the process completed successfully, but some warnings occurred. • An orange question mark means the process is out of date and should be run again. e. Look in the Console tab of the Transcript window and read the output and status messages produced by any process that you run. You must correct any errors found in your source files. If you continue without valid syntax, you will not be able to simulate or synthesize your design. Caution!
Fig.i.4 check syntax for VHDL program
After Completion Synthesize change the option Source for “Implementation” to Behavioral Simulation
Fig.i.5 Changing into Behavioral Simulation
•
Click on the Simulation button from menu bar and select the source name.
• •
Then below mentioned there will appear in process window select simulate behavioral model and click enter. Then ISIM window will open
Fig.i.6 ISIM Simulator
Change the Time period to low values and click on Run as shown in the fig
Fig.i.7 changing the values by forcing the constants
Force the constants for the selected signals
Fig.i.8 assigning i/p to a value
Assign the values and run the constants the output waveform is
Fig.i.9 Output Waveform
1. REALIZATION OF LOGIC GATES AIM:
To design and simulate logic gates using VHDL b ehavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and
one
output.
At
any
given
moment,
every
terminal
is
in
one
of
the
two binary conditions low (0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit processes data. In most logic gates, the low state is approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V). AND:
The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the same way as the logical "and" operator. OR :
The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive "or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then the output is "false." NOR :
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both inputs are "false." Otherwise, the output is "false."
PIN DIAGRAMS:
AND GATE Input
OR GATE
Output
Input
Output
A
b
c
a
B
c
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
AND GATE ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Step 2: Declare the Entities
Define the Ports with 2 Inputs and 1 outputs and operation Step 3: Declare the architecture
If two i/p’s are same then o/p=1 else o/p=0
Step 4: End
E T A G D N A F O M A R G A I D L A N R E T N I
OR GATE ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Step 2: Declare the Entities
Define the Ports with 2 Inputs and 1 outputs for or operation Step 3: Declare the architecture
If two i/p’s are same then o/p=0 else o/p=1 Step 4: End
E T A G R O F O M R A G A I D L A N R E T N I
NOT GATE ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Step 2: Declare the Entities
Define the Ports with 1 Input and 1 output for not operation Step 3: Declare the architecture
If i/p=1 then o/p=0 else o/p=1 Step 4: End
NOR GATE ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Step 2: Declare the Entities
Define the Ports with 2 Inputs and 1 outputs for or operation Step 3: Declare the architecture
If two i/p’s are same then o/p=1 else o/p=0 Step 4: End
E T A G R O N F O M A R G A I D L A N R E T N I
VIVA QUESTIONS :
1. Implement the following function using VHDL coding. (Try to minimize if you can). F(A,B,C,D)=(A′+B+C) . (A+B′+D′). (B+C′+D′) . (A+B+C+D) 2. What will be the no. of rows in the truth table of N variables? 3. What are the advantages of VHDL? 4. Design Ex-OR gate using behavioral model? 5. Implement the following function using VHDL code f=AB+CD. 6. What are the differences between half adder and full adder? 7. What are the advantages of minimizing the logical expressions? 8. What does a combinational circuit mean? 9. Implement the half adder using VHDL code? 10. Implement the full adder using two half adders and write VHDL program in structural model?
2. 3:8 DECODER - 74138 AIM:
To design and simulate 3:8 Decoder - 74138 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.
3:8 decoder
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs, NAND gates are used. It has 3 input lines and 8 output lines. It is also called as binary to octal decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs corresponding to that code. PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define the Ports with enable, selection lines as inputs and data lines as outputs
Step 3: Declare the architecture as
If en=0 or 1then If selection line is 000 then dataline 01111111 001 then dataline 10111111 010 then dataline 11011111 011 then dataline 11101111 100 then dataline 11110111 101 then dataline 11111011 110 then dataline 11111101 111 then dataline 11111110 Step 4: End
INTERNAL DIAGRAM OF 3x8 Decoder
VIVA QUESTIONS :
1. Write the behavioral code for the IC 74x138. 2. Write the VHDL code for the IC 74x138 using CASE statement. 3. Write the VHDL code for the IC 74x138 using WITH statement. 4. Write the VHDL code for the IC 74x138 using WHEN--ELSE statement. 5. Write the structural program for IC 74x138. 6. What does priority encoder mean? 7. How many decoders are needed to construct 4X16 decoder? 8. What is the difference between decoder and encoder? 9. Write the syntax for exit statement? 10. Explain briefly about next statement? 11. How to specify the delay in VHDL program? 12. Write the syntax for component declaration.
3. 8 X 1 MULTIPLEXER-74151 AND 2 X 4 DEMULTIPLEXER-74155
AIM:
To design and simulate MUX & DEMUX using VHDL b ehavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
Multiplexing is defined as the process of feeding several independent signals to a common load, one at a time. The device or switching circuitry used to select and connect one of these several signals to the load at any one time is known as a multiplexer. The reverse function of multiplexing, known as de-multiplexing, pertains to the process of feeding several independent loads with signals coming from a common signal source, one at a time. A device used for de-multiplexing is known as de-multiplexer. Multiplexing and de-multiplexing, therefore, allow the efficient use of common circuits to feed a common load with signals from several signal sources , and to feed several loads form a single, common signal source, respectively.
PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM FOR 8:1 MULTIPLEXER:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with en, selection lines, data line as i/p and 1 o/p Step 3: Declare the architecture as
If en = 0 then o/p = D0 when selection line 000 else o/p = D1 when selection line 001 else o/p = D2 when selection line 010 else o/p = D3 when selection line 011 else o/p = D4 when selection line 100 else o/p = D5 when selection line 101 else o/p = D6 when selection line 110 else o/p = D7 when selection line 111
If en =1 then o/p=0
Step 4: END
INTERNAL DIAGRAM OF 8 x 1 MULTIPLEXER
ALGORITHM FOR 1:8 DEMULTIPLEXER:
Step 1: Use the libraries
Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define the Ports with enable, selection lines ,c as i/p and datalines as o/p Step 3: Declare the architecture as
If en = 0, when selection line is 00 then y(0)=c else 01 then y(1)=c else 10 then y(2)=c else 11 then y(3)=c else Step 4: END
INTERNAL DIAGRAM OF 1 x 8 DE-MULTIPLEXER
VIVA QUESTIONS :
1. Write the behavioral code for the IC 74x151. 2. Write the VHDL code for the IC 74x151 using IF statement. 3. Write the VHDL code for the IC 74x151 using WITH statement. 4. Write the VHDL code for the IC 74x151 using WHEN--ELSE statement. 5. Write the structural program for IC 74x151. 6. What is meant by multiplexer? 7. What does demultiplexer mean? 8. How many 8X1 multiplexers are needed to construct 16X1 multiplexer? 9. Compare decoder with demultiplexer? 10. Design a full adder using 8X1 multiplexer? 11. What are the two kinds of subprograms? 12. What are the difference between function and procedure? 13. Explain briefly about subprogram overloading?
4. 4-BIT COMPARATOR - 7485 AIM:
To design and simulate 4 bit Comparator - 7485 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A comparator is a special combinational circuit designed primarily to compare the relative magnitudes of two binary numbers. If a comparator receives two n-bit numbers A and B as inputs and the outputs are A>B, A=B, A
PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with agtbin, aeqbin, altbin,a,b as i/p’s an d agtbout ,aeqbout altbout as o/p’s Step 3: Declare the architecture as
If a=b then aeqbout=1 else If ab then altbout=1 else Step 4: End
INTERNAL DIAGRAM OF COMPARATOR
OUTPUT WAVEFORM:
RESULT:
VIVA QUESTIONS:
1. Write the dataflow model for the IC 74x85. 2. Write the VHDL code for the IC 74x85 using CASE statement. 3. Write the VHDL code for the IC 74x85 using WITH statement. 4. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement. 5. Write the structural program for IC 74x85. 6. How many 4-bit comparators are needed to construct 12-bit comparator? 7. What does a digital comparator mean? 8. Design a 2-bit comparator using gates?
9. Explain the phases of a simulation? 10. Explain briefly about wait statement?
5. D - FLIP FLOP - 7474 AIM:
To design and simulate D- Flip Flops IC 7474 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
The D-flip flop has only a single data input .The data input is connected to the S input of an RSflip flop, while the inverse of D is connected to the R input. This prevents that the input combination ever occurs. To allow the flip flop to be in a holding state, a D-flip flop has a second input called “Enable.” The Enable-input is AND with the D-input, such that when Enable=0, the R & S of the RS-flip flop are 0 and the state is held. When the Enable-input is 1, the S input of the RS flip flop equals the D input and R is the inverse of D determines the value of the output Q when Enable is 1. When Enable returns to 0, the most recent input D is “remembered.”
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM FOR D-FLIP FLOP:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk,d as i/p’s and q, qbar as o/p’s Step 3: Declare the architecture as
If clk= 1 then q=d, qbar=not d Step 4: END
INTERNAL DIAGRAM OF D-FLIP FLOP
VIVA QUESTIONS :
1. Write the behavioral code for the IC 74x74. 2. Write the dataflow code for the IC 74x74. 3. What is the difference between sequential and co mbinational circuit? 4. What is a flip-flop? 5. Explain the functions of preset and clear inputs in flip-flop? 6. What is meant by a clocked flip-flop? 7. What is meant by excitation table? 8. What is the difference between flip-flop and latch? 9. What are the various methods used for triggering flip-flops? 10. Explain level triggered flip-flop? 11. Write the behavioral code for IC 74X74. 12. Write the syntax of IF statement?
6. DECADE COUNTER - 7490 AIM:
To design and simulate Decade counter IC7490 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, and so on down to the fourth cell. This produces a binary number equal to the number of cycles of the input clock signal. This device is sometimes called a ripple through counter. The same device is useful as a frequency divider, a BCD counter or decade counter can be constructed from a straight binary counter by terminating the ripple through counting when the count reaches decimal 9(binary 1001). Since the next toggle would set the two most significant bit, a NAND gate tied from those two outputs to the asynchronous clear line will start the count over after 9. A frequency divider can be constructed from J-K flip flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in second cell, so its output is at half the frequency of the first. The output of the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter.
PIN DIAGRAM:
\ PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk, en as i/p’s and count out as o/p’s Step 3: Declare the architecture as
Declare a temporary count initializing with 0 If en=1 and clk=1 then Temp count = temp count +1 Count out= temp count Step 4: END
R E T N U O C E D A C E D F O M A R G A I D L A N R E T N I
VIVA QUESTIONS:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
Write the behavioral code for IC 74x90. What is a sequential circuit? Differentiate between synchronous and asynchronous counter? How many no.of flip-flops are required for decade counter? What is meant by excitation table? What are the meanings of different types of value s in std_ulogic? What are the objects in VHDL? Write the syntax for a signal? Write the difference between signal and variable? Explain about enumeration types? If the modulus of a counter is 12 how many flip-flops are required?
7. 4 - BIT COUNTER - 7493
AIM:
To design and simulate MOD 16 counter (4-bit) using IC7490 in VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, and so on down to the fourth cell. This produces a binary number equal to the number of cycles of the input clock signal. This device is sometimes called a ripple through counter. The same device is useful as a frequency divider, a BCD counter or decade counter can be constructed from a straight binary counter by terminating the ripple through counting when the count reaches decimal 9(binary 1001). Since the next toggle would set the two most significant bit, a NAND gate tied from those two outputs to the asynchronous clear line will start the count over after 9. A frequency divider can be constructed from J-K flip flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in second cell, so its output is at half the frequency of the first. The output of the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter.
PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.]\
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk, dir as i/p’s and count out as o/p’s Step 3: Declare the architecture as
Declare a temporary count initializing with 0 If clk=1 and dir =1 Temp count=tempcnt+1 Count out = Temp count If clk=1 and dir =0 Temp count=tempcnt-1 Count out = Temp count Step 4:- END
R E T N U O C 6 1 D O M F O M A R G A I D L A N R E T N I
VIVA QUESTIONS:
1. Write the behavioral code for IC 74x93. 2. What is the difference between decade counter and 4 bit counter? 3. What is meant by a modulus of a counter? 4. Write the behavioral code for IC74X93? 5. Explain the operation of IC74X93? 6. Write the syntax for component instantiation? 7. What is netlist? 8. Briefly explain about generics? 9. Write the difference between sequential statement and concurrent statement? 10. Write the syntax for loop statements? 11. Write the syntax for generate statements? 12. Write the differences between loop and generate?
8. SHIFT REGISTER – 7495
AIM:
To design and simulate the right shift and parallel shift register using IC 74x 95 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
These 4-bit Registers feature parallel and serial inputs parallel outputs mode control and two clock inputs. The registers have 2 modes of operation parallel load& shift right. Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated Flip flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading the entry of serial data is inhibited. Shift right is accomplished on the high to low transition of clock 1 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous Flip flop and serial data is entered at input D. the clock input may be applied simultaneously to clock 1 and clock 2 if both modes can be clocked from the same source changes at the mode control input should normally be made while both clock inputs are low however conditions described in the last three lines of the truth table will also ensure that Register contents are protected DM7495’s datasheet is the same as DM7495 PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with rst,ldsh clk, d as i/p’s and q as o/p’s Step 3: Declare Architecture
Define temporary register Q=temp reg; If rst,ldsh =1 then Clk=1 then temp reg = d; Step 4: END
SHIFT RESIGTER - 7495
VIVA QUESTIONS:
1. Write the behavioral code for IC 74x95. 2. What is a shift register? 3. Write some applications of shift register? 4. Explain briefly about BLOCK? 5. Write the syntax for function? 6. Write the syntax for procedure? 7. How to define variable in VHDL? 8. Write the syntax for CASE statement? 9. What is the advantage of case statement over if-else statement? 10. Write the difference between with-select and when-else statement?
9. UNIVERSAL SHIFT REGISTER – 74194/95 AIM:
To design and simulate universal shift register using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
These 4-bit Registers feature parallel and serial inputs parallel outputs mode control and two clock inputs. The registers have 3 modes of operation parallel load, shift right and shift left. Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated Flip flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading the entry of serial data is inhibited. Shift right is accomplished on the high to low transition of clock 1 when the mode control is low shift left is accomplished on the high to low transition of clock 2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous Flip flop and serial data is entered at input D. the clock input may be applied simultaneously to clock 1 and clock 2 if both modes can be clocked from the same source changes at the mode control input should normally be made while both clock inputs are low however conditions described in the last three lines of the truth table will also ensure that Register contents are protected DM7495’s datasheet is the same as DM7495.
PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click on ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk, d ,s as i/p’s and q as o/p’s Step 3: Declare Architecture
If clk =1 then When s= 00 then q<=d else When s= 00 then q<=data rigt shift else When s= 00 then q<=data left shift else When s= 00 then q<=parallel load
Step 4:
END
5 9 1 4 7 / 4 9 1 4 7
–
R E T S W I G E R T F I H S L A S R E V I N U
VIVA QUESTIONS:
1. What is shift register. 2. What is the difference between universal shift register and shift register 3. Write the structural programming of universal shift register.
10. READ AND WRITE OPERATIONS OF RAM (IC 74X18)
AIM:To design and Simulate read and write operations of RAM.( IC 74X189) using VHDL
Code. APPARATUS:
Xilinx ISE Simulator V 12.1
BLOCK DIAGRAM:
TRUTH TABLE OF RAM
En_1
RW
Operation
0
0
Write
0
1
Read the Complemented Data
1
X
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with en, rd ,wr,d as i/p’s and q as o/p’s Step 3: Declare Architecture
If en=1 and rd =1 Then data will read from memory else o/p is zzzz If en=1 and wr =1 Then data will write into memory else o/p is zzzz Step 4: END
Inhibit
OUTUT WAVEFORMS:
RESULT:
VIVA QUESTIONS:
1. 2. 3. 4. 5. 6. 7. 8. 9.
Write the behavioral code for IC 74x189 without declaring the function. Explain about different types of RAMs? How to specify the memory size? Explain read and write operations? What are the differences between RAM and RAM? Explain the steps of a compilation process of a VHDL program? Why configurations are needed? What is binding? What is subprogram in vhdl
10. STACK AND QUEUE IMPLEMENTATION USING RAM AIM: To write a VHDL code and to Simulate Implementing Stack And Queue Using RAM. APPARATUS:
Xilinx ISE Simulator V 12.1 ALGORITHM OF STACK:Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk, d,en, push/pop as i/p’s and q as o/p’s Step 3: Declare Architecture
Define temp reg with initialize 0 If clk=1 and en=1 then Pusfpop=1 temp reg=temp reg+1 Stack pointer=temp reg If clk=1 and en=1 then Pusfpop=0 temp reg=temp reg-1 Stack pointer=temp reg
Step 4: END MODEL WAVEFORM OF STACK OPERATION:
ALGORITHM OF QUEUE:Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk, d,enr,enw, din as i/p’s and dout as o/p’s Step 3: Declare Architecture
Define temp reg with initialize 0 If clk=1 and en=1 and enr=1 then temp reg=temp reg+1 Dout=temp reg
If clk=1 and en=1 then temp reg=temp reg-1 dout=temp reg Step 4: END MODEL WAVEFORM OF QUEUE OPERATION:
Model waveform of QUEUE operation RESULT:VIVA QUESTIONS:
1. 2. 3. 4. 5. 6. 7. 8. 9.
Write the behavioral code for IC 74x189 without declaring the function. Explain about different types of RAMs? How to specify the memory size? Explain read and write operations? What are the differences between RAM and RAM? Explain the steps of a compilation process of a VHDL program? Why configurations are needed? What is binding? What is subprogram in vhdl
12. ARITHMETIC AND LOGIC UNIT
AIM:
To design and simulate 4 bit ALU operation using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY: Arithmetic and logic unit (ALU) is a digital circuit that performs integer arithmetic and
logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units ( GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs.
PIN DIAGRAM:
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click o n ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with clk, d,w,r as i/p’s and f as o/p’s Step 3: Declare Architecture
For different selection lines of d differner arthamatic and logical operations has be en occurred between the w and r and the output is saved in f; Step 4:-END
INTERNAL DIAGRAM OF ALU
VIVA QUESTIONS:
1. Explain the steps of a compilation process of a VHDL program? 2. Why configurations are needed? 3. What is subprogram in vhdl
ADD-ON EXPERIMENTS 13. HALF ADDER AND FULL ADDER
AIM:
To design and simulate the Half Adder, Full Adder using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
HALF ADDER: The half adder is an example of a simple, functional digital circuit built from two logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to two different gates. The inputs to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input to the AND gate receives the same voltage. FULL ADDER: The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is simply two half adders joined b y an OR.
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear o n console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click o n ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with a,b as i/p’s and Cout , S as o/p’s Step 3: Declare Architecture
Cout as a sum with xor operation of a and d, S will be the carry with AND operation of a and b; Step 4:-END RTL SCHEMATIC:
OUTPUT WAVEFORMS:
ALGORITHM: Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define ports with a,b Cin as i/p’s and Cout , Sum as o/p’s Step 3: Declare Architecture
Sum as a sum with xor operation of a ,b,Cin . carry with AND operation of a and b Cin. Step 4:-END RTL SCHEMATIC:
INTERNAL DIAGRAM OF FULL ADDER
OUTPUT WAVEFORMS:
RESULT:
VIVA QUESTIONS: 1. Write the truth table of half adder and full adder and explain. 2. What is the difference between half adder and full adder. 3. Write the program code in structural.
14. 8 x 3 ENCODER
AIM: To design and simulate 8 x 3 Encoder using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
An Encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has n
2 (or fewer ) input lines and output lines. In encoder the output lines generate the binary code corresponding to the input value. The figure shows the general structure of the encoder circuit. n
As Shown in the figure the decoded information is presented as 2 inputs producing n possible outputs. A Priority Encoder is a encoder Circuit that includes the priority Function. In Priority encoder , if two or more inputs are equal to 1 at the same time, the input having the highest Priority will take precedence.
Truth Table
Inputs
Outputs
D7
D6
D5
D4
D3
D2
D1
D0
A
B
C
X
X
X
X
X
X
X
1
0
0
0
X
X
X
X
X
X
1
0
0
0
1
X
X
X
X
X
1
0
0
0
1
0
X
X
X
X
1
0
0
0
0
1
1
X
X
X
1
0
0
0
0
1
0
0
X
X
1
0
0
0
0
0
1
0
1
X
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click o n ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED Step 2: Declare the entities
Define the Ports with enable, data lines as inputs a nd E_out as outputs Step 3: Declare the architecture as
If en=0 or 1then If the data line D(1) is 1 then the out put is 001 D(2) is 1 then the out put is 010 D(3) is 1 then the out put is 011 D(4) is 1 then the out put is 100 D(5) is 1 then the out put is 101 D(6) is 1 then the out put is 110 D(7) is 1 then the out put is 111 Step 4: End
RTL SCHEMATIC:
INTERNAL DIAGRAM OF (8 X 3) ENCODER
OUTPUT WAVEFORMS:
RESULT:.
VIVA QUESTIONS :
1. Write the VHDL code for the encoder using CASE statement. 2. Write the VHDL code for the encoder using WITH statement. 3. Write the VHDL code for the encoder WHEN--ELSE statement. 4. Write the structural program for encoder. 5. What does priority encoder mean? 6. How many encoders are needed to construct 16X4 encoder ? 7. What is the difference between decoder and encoder?
15. T - FLIP FLOP
AIM:
To design and simulate T- Flip Flops IC 7474 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation: (or, without benefit of the XOR operator, the equivalent:
) and can be described in a truth table: T Flip-Flop operation
Characteristic table
[1]
Excitation table
Comment
Comment
0 0
0
hold state(no clk) 0
0
0
No change
0 1
1
hold state(no clk) 1
1
0
No change
1 0
1
toggle
0
1
1 Complement
1 1
0
toggle
1
0
1 Complement
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This
'divide by' feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Q previous is connected to the D input through an XOR gate).
PROCEDURE:
Click on the Xilinx icon.
Go to file and click on new project.
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
In design window your file will appear, make sure it is detected.
Write architectural part and save it.
Go to process window, click on synthesizer and check syntax.
If any syntax errors occur they will appear on console window while compiling.
Go to simulation and select your file.
In process window click ISM simulator, now click on behavioral check syntax, simulate behavioral model.
Select your input & click on force constant. Enter value in ‘force clock’ to value.
By repeating above step for all input’s click o n ‘RUN’.
To view output for all combinations of inputs click on zoom view.
ALGORITHM FOR D-FLIP FLOP:
Step 1: Use the libraries
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with clk,T as i/p’s and q, qbar as o/p’s Step 3: Declare the architecture as
If clk= 1 then q= not T, qbar=not q Step 4: END
INTERNAL DIAGRAM OF T-FLIP FLOP