VLSI Design Interview Questions With Answers – Ebook Most frequently aske VLSI interview questions answere Answers to your VLSI Interview questions! "eature
Posted on July 13, 2012 Sign u# to re$eive "%EE answers to VLSI interview questions!
When you sign up you y ou will receive 25 questions answers to help you prepare for digital V!" design interviews# $ou $ou will get updates a%out new posts discussing various technical topics and interview questions# $ou $ou will occasionally receive product reco&&endations to help with interview preparations# Posted in 'eneral 'eneral ( ( eave a reply Dyna&i$ 'ates
Posted on )cto%er *, 2012 +yna&ic gates use cloc for their nor&al operation as opposed to the static gates, which don-t use clocs# +yna&ic gates use ./)! or P/)! logic# "t doesn-t use /)! logic lie regular static gates# ecause it uses either ./)! or P/)! logic and not /)! logic, it usually has fewer transistors co&pared to static gates# lthough there are etra transistors given that it uses clocs#
4igure ./)! pull down logic for .)6 gate#
7he figure shows the pull down ./)! logic for a .)6 gate# 7his pull down structure is used in the dyna&ic gates# 8ow dyna&ic gates wor "n static gates, inputs switch and after a finite input to output delay, output possi%ly switches to the epected state#
4igure +yna&ic .)6 gate# s you can see in the figure a%ove, dyna&ic gate is &ade using ./)! pull down logic along with cloc cloc transistors on %oth pull up and pull down paths# We now that cloc has two phases, the low phase and the high phase# +yna&ic gate has two operating phases %ased on the cloc phases# +uring the low cloc phase, %ecause of the p&os gate on the pull up networ, the output of dyna&ic gate is pre9charged to high phase# 7his is the pre9charge pre9charge state state of dyna&ic gate# When the cloc is at high phase, the output of dyna&ic gate &ay change %ased on the inputs, or it &ay stay pre9charged depending depending on the input# 7he phase of the dyna&ic gates, when the cloc is high, is called the evaluate phase# s it is essentially evaluating what the output should %e during this phase#
4igure +yna&ic .)6 wavefor&s when input :- is high# s seen in the wavefor&s a%ove, as soon as ; goes low, it pre9charges output node :)ut- high# While in the pre9charge state, .)6 input :- goes high# When ; goes high, and evaluation phase %egins, :)ut- is discharged to low as input :- is high# "nput :- is not shown in the wavefor& as it is not relevant to this case# "f %oth inputs :- and :- were to re&ain low, output node would %e held high during the pre9charge# 7his technique of always pri&ing or pre9charging output to %e with, is a way to &ini&i
7he %iggest %enefit of dyna&ic gates is that they can %e cascaded together and their pull down only property can %e leveraged to have a very fast delay through a chain of &ultiple stage dyna&ic gates# Posted in ircuits, /)! theory ( eave a reply (M)S an *M)S logi$
Posted on ugust 1=, 2012 /)! is the short for& for the o&ple&entary /etal )ide !e&iconductor# o&ple&entary stands for the fact that in /)! technology %ased logic, we use %oth p9 type devices and n9type devices# ogic circuits that use only p9type devices is referred to as P/)! logic and si&ilarly circuits only using n9type devices are called ./)! logic# efore /)! technology %eca&e prevalent, ./)! logic was widely used# P/)! logic had also found its use in specific applications# ets understand &ore how ./)! logic wors# s per the definition, we are only allowed to use the n > type device as %uilding %locs# .o p9type devices are allowed# ets tae an ea&ple to clarify this# 4ollowing is the truth ta%le for a .)6 gate#
4igure .)6 truth ta%le# We need to co&e up the a circuit for this .)6 gate, using n9&os only transistors# 4ro& our understanding of /)! logic, we can thin a%out the pull down tree, which is &ade up of only n9&os gates#
4igure .)6 pulldown logic# 8ere we can see that when either of the inputs :- or :- is high, the output is pulled down to the ground# ut this circuit only reflects the negative logic, or the partial functionality of .)6 gate when at least one of the inputs is high# 7his doesn-t represent the case where %oth input area low, the first row of the truth ta%le# 4or an equivalent /)! .)6 gate, there would %e pull up tree &ade up of p9&os devices# ut here we are referring to ./)! logic and we are not allowed to have p9&os devices# 8ow could we co&e up with the pull up logic for our .)6 gate ? 7he answer is a resistor# @ssentially when %oth n9&os transistor are turned off, we want :out- node to %e pulled up and held at V++# resistor tied %etween V++ and :out- node would achieve this# 7here could %e other possi%le ela%orate sche&es to achieve the sa&e using n9&os transistors for pulling up purpose, %ut an n9&os as a resistor is used to pull up the output node# )f course you see so&e i&&ediate draw%acs# $ou can see that when at least one of the pull down n9&os is on, there is a static %ias current flowing fro& V++ to the ground even in the steady state# Which is why such circuits dissipate al&ost an order of &agnitude &ore power co&pared to /)! equivalent# .ot only that, this type of circuit is very suscepti%le to the input noise glitches# ny n9&os device can %e &ade into a resistor %y &aing it per&anently on# .9&os device has inherent resistance and we can achieve the desired resistance %y &odulating the width of n9&os transistor#
4igure ./)! logic .)6 gate# 7he a%ove figure shows the .)6 gate &ade using ./)! logic# !i&ilarly any gate can also %e &ade using P/)! logic# Posted in /)! theory ( eave a reply Verilog %a$es
Posted on July 2A, 2012 "n Verilog certain type of assign&ents or epression are scheduled for eecution at the sa&e ti&e and order of their eecution is not guaranteed# 7his &eans they could %e eecuted in any order and the order could %e change fro& ti&e to ti&e# 7his non9 deter&inis& is called the race condition in Verilog# 4or the purpose of refreshing your &e&ory here is the Verilog eecution order again, which we had discussed in a prior post#
4igure Verilog eecution order# "f you loo at the active event queue, it has &ultiple types of state&ents and co&&ands with equal priority, which &eans they all are scheduled to %e eecuted together in any rando& order, which leads to &any of the races## ets loo at so&e of the co&&on race conditions that one &ay encounter# 1B 6ead9Write or Write96ead race condition# 7ae the following ea&ple always CDposedge clB E 2F
always CDposedge clB y E F oth assign&ents have sa&e sensitivity D posedge cl B, which &eans when cloc rises, %oth will %e scheduled to get eecuted at the sa&e ti&e# @ither first :- could %e assigned value -2G and then :y- could %e assigned :-, in which case :y- would end up with value -2G# )r it could %e other way around, :y- could %e assigned value of :- first, which could %e soðing other than -2G and then :- is assigned value of -2G# !o depending on the order final value of :y- could %e different# 8ow can you avoid this race ? "t depends on what your intention is# "f you wanted to have a specific order, put %oth of the state&ents in that order within a :%egin-H-end- %loc inside a single :always- %loc# et-s say you wanted :- value to %e updated first and then :y- you can do following# 6e&e&%er %locing assign&ents within a :%egin- ## :end- %loc are eecuted in the order they appear# always CDposedge clB %egin E 2F y E F end 2B Write9Write race condition# always CDposedge clB E 2F always CDposedge clB E IF 8ere again %oth %locing assign&ents have sa&e sensitivity, which &eans they %oth get scheduled to %e eecuted at the sa&e ti&e in :active event- queue, in any order# +epending on the order you could get final value of :- to %e either -2G or -IG# "f you wanted a specific order, you can follow the ea&ple in previous race condition# 3B 6ace condition arising fro& a :for-H-oin- %loc# always CDposedge clB for E 2F y E F oin
Knlie :%egin-H-end- %loc where epressions are eecuted in the order they appear, epression within :for-H-oin- %loc are eecuted in parallel# 7his parallelis& can %e the source of the race condition as shown in a%ove ea&ple# oth %locing assign&ents are scheduled to eecute in parallel and depending upon the order of their eecution eventual value of :y- could %e either -2G or the previous value of :-, %ut it can not %e deter&ined %eforehand# *B 6ace condition %ecause of varia%le initiali
Posted in +igital +esign, Verilog ( eave a reply Ma+ "anout of a ,M)S 'ate
Posted on July 25, 2012 When it co&es to doing digital circuit design, one has to now how to si
driving gate can charge or discharge the load within reasona%le ti&e with reasona%le power dissipation# )ur ai& is to find out the no&inal fanout value which gives the %est speed with least possi%le power dissipation# 7o si&plify our analysis we can focus on the leaage power, which is proportional to the width or si
4igure 1# 6 and &odel of /)! inverter )ur &odel inverter has ./)! with width :W- and P/)! has width :2W-, with equal rise and fall delays# We now that gate capacitance is directly proportional to gate width#
ets also assu&e that for width :W-, the gate capacitance is :-# 7his &eans our ./)! gate capacitance is :- and our P/)! gate capacitance is :2-# gain for sae of si&plicity lets assu&e the diffusion capacitance of transistors to %e
4igure 2# Knit si
4igure 3# "nverter 6 N &odel
4or this 6 circuit, we can calculate the delay at the driver output node using @l&ore delay approi&ation# "f you can recall in @l&ore delay &odel one can find the total delay through &ultiple nodes in a circuit lie this !tart with the first node of interest and eep going downstrea& along the path where you want to find the delay# long the path stop at each node and find the total resistance fro& that node to V++LV!! and &ultiply that resistance with total apacitance on that node# !u& up such 6 and product for all nodes# "n our circuit, there is only one node of interest# 7hat is the driver inverter output, or the end of resistance 6# "n this case total resistance fro& the node to V++LV!! is :6- and total capacitance on the node is :aO2aE3a-# 8ence the delay can %e approi&ated to %e :6M3aE 3a6 .ow to find out the typical value of fanout :a-, we can %uild a circuit with chain of %ac to %ac inverters lie following circuit#
4igure *# hain of inverters# )%ective is to drive load with opti&u& delay through the chain of inverters# ets assu&e the input capacitance of first inverter is :- as shown in figure with unit width# 4anout %eing :a- net inverter width would :a- and so forth# 7he nu&%er of inverters along the path can %e represented as a function of and lie following# 7otal nu&%er of inverters along chain + E ogaDLB E lnDLBLlnDaB 7otal delay along the chain + E 7otal inverters along the chain M +elay of each inverter# @arlier we learned that for a %ac to %ac inverters where driver inverter input gate capacitance is :- and the fanout ration of :a-, the delay through driver inverter is 3a6 7otal delay along the chain + E lnDLBLlnDaB M 3a6
"f we want to find the &ini&u& value of total delay function for a specific value of fanout :a-, we need to tae the derivative of :total delay- with respect to :a- and &ae it
4igure 5# 7otal delay vLs 4anout graph s you can see in the graph, you get lowest delay through a chain of inverters around ratio of :e-# )f course we &ade si&plifying assu&ptions including the
)ne &ore thing to re&e&%er here is that, we assu&ed a chain of inverter# "n practice &any ti&es you would find a gate driving a long wire# 7he theory still applies, one ust have to find out the effective wire capacitance that the driving gate sees and use that to co&e up with the fanout ratio# 9!!# Posted in ircuits, /)! theory ( eave a reply Inverte -e&#erature De#enen$e!
Posted on July 21, 2012 "t is nown that with increase in te&perate, the resistivity of a &etal wireDconductorB increases# 7he reason for this pheno&enon is that with increase in te&perature, ther&al vi%rations in lattice increase# 7his gives rise to increased electron scattering# )ne can visuali VthD7BBT Where S E &o%ility
Vth E threshold voltage T E positive constant D s&all nu&%er B )ne can see that "d is dependent upon %oth &o%ility S and threshold voltage Vth# et ea&ine the dependence of &o%ility and threshold voltage upon te&perature# UD7B E UD300B D 300L7 B& VthD7B E VthD300B D7 300B here :300- is roo& te&perature in elvin# /o%ility and threshold voltage %oth decreases with te&perature# ut decrease in &o%ility &eans less drain current and slower device, whereas decrease in threshold voltage &eans increase in drain current and faster device# 7he final drain current is deter&ined %y which trend do&inates the drain current at a given voltage and te&perature pair# t high voltage &o%ility deter&ines the drain current where as at lower voltages threshold voltage do&inates the darin current# 7his is the reason, at higher voltages device delay increase with te&perature %ut at lower voltages, device delay increases with te&perature# 9!!# Posted in /)! theory, sta ( eave a reply Syn$hronous or Asyn$hronous resets .
Posted on July 1X, 2012 oth synchronous reset and asynchronous reset have advantages and disadvantages and %ased on their characteristics and the designers needs, one has to choose particular i&ple&entation# !ynchronous reset dvantages 9 7his is the o%vious advantage# synchronous reset confor&s to synchronous design guidelines hence it ensures your design is 100R synchronous# 7his &ay not %e a require&ent for everyone, %ut &any ti&es it is a require&ent that design %e 100R synchronous# "n such cases, it will %e %etter to go with synchronous reset i&ple&entation# 9 Protection against spurious glitches# !ynchronous reset has to set up to the active cloc edge in order to %e effective# 7his provides for protection against accidental glitches as
long these glitches don-t happen near the active cloc edges# "n that sense it is not 100R protection as rando& glitch could happen near the active cloc edge and &eet %oth setup and hold require&ents and can cause flops to reset, when they are not epected to %e reset# 7his type of rando& glitches are &ore liely to happen if reset is generated %y so&e internal conditions, which &ost of the ti&e &eans reset travels through so&e co&%inational logic %efore it finally gets distri%uted throughout the syste&#
4igure 'litch with synchronous reset s shown in the figure, 1 and 2 generate DresetB%ar# ecause of the way 1 and 2 transition during the first cloc cycle we get a glitch on reset signal, %ut %ecause reset is synchronous and %ecause glitch did not happen near the active cloc edge, it got filtered and we only saw reset tae effect later during the %eginning of *th cloc cycle, where it was epected# 9 )ne advantage that is touted for synchronous resets is s&aller flops or the area savings# 7his is really not that &uch of an advantage# "n ter&s of area savings it is really a wash %etween synchronous and asynchronous resets#
!ynchronous reset flops are s&aller as reset is ust and9ed outside the flop with data, %ut you need that etra and gate per flop to acco&&odate reset# While asynchronous reset flop has to factor reset inside the flop design, where typically one of the last inverters in the feed%ac loop of the slave device is converted into ..+ gate
4igure !ynchronous vLs synchronous reset flop co&parison# +isadvantages 9 Wide enough pulse of the reset signal# We saw that %eing synchronous, reset has to &eet the setup to the cloc# We saw earlier in the figure that spurious glitches gets filtered in synchronous design, %ut this very %ehavior could %e a pro%le&# )n the flip side when we do intend the reset to wor, the reset pulse has to %e wide enough such that it &eets setup to the active edge of the cloc for the all receivers sequentials on the reset distri%ution networ# 9 nother &aor issue with synchronous is cloc gating# +esigns are increasingly %eing cloc gated to save power# loc gating is the technique where cloc is passed through an and gate with an ena%le signal, which can turn off the cloc toggling when cloc is not used thus saving power# 7his is in direct conflict with reset# When chip powers up, initially the clocs are not active and they could %e gated %y the cloc ena%le, %ut right during the power up we need to force the chip into an nown set and we need to use reset to achieve that# !ynchronous reset will not tae into effect unless there is active edge and if cloc ena%le is off, there is no active edge of the cloc# +esigner has to carefully account for this situation and design reset and cloc ena%ling strategy which accounts for proper circuit operation# 9 Kse of tri9state structures# When tri9state devices are used, they need to %e disa%led at power9up# ecause, when inadvertently ena%led, tri9state device could crow%ar and ecessive current could flow through the& and it could da&age the chip# "f tri9state ena%le is driven %y a synchronous reset flop, the flop output could not %e low, until the active edge of the cloc arrives, and hence there is a potential to turn on tri9state device#
4igure 7ri9state @na%le# synchronous reset dvantages 9 4aster data path# synchronous reset sche&e re&oves that .+ gate at the input of the flop, thus saving one stage delay along the data path# When you are pushing the ti&ing li&its of the chip# 7his is very helpful# 9 "t has o%vious advantage of %eing a%le to reset flops without the need of a cloc# asically assertion of the reset doesn-t have to setup to cloc, it can co&e anyti&e and reset the flop# 7his could %e dou%le edged sword as we have seen earlier, %ut if your design per&its the use of asynchronous reset, this could %e an advantage# +isadvantages 9 iggest issue with asynchronous reset is reset de9assertion edge# 6e&e&%er that when we refer to reset as :asynchronous-, we are referring to only the assertion of reset# $ou can see in figure a%out synchronous and asynchronous reset co&parison, that one of the way asynchronous reset is i&ple&ented is through converting one the feed%ac loop inverters into ..+ gate# $ou can see that when reset input of the ..+ gate, goes low it forces the Y output to %e low irrespective of the input of the feed%ac loop# ut as soon as you deassert reset, that ..+ gate i&&ediately %eco&es an inverter and we are %ac to nor&al flop, which is suscepti%le to the setup and hold require&ents# 8ence de9 assertion of the reset could cause flop output to go &etasta%le depending upon the relative ti&ing %etween de9assertion and the cloc edge# 7his is also called reset recovery ti&e chec, which asynchronous reset have to &eet even if they are asynchronous Z $ou don-t have this pro%le& in synchronous reset, as you are eplicitly forced to chec %oth setup and hold on reset as well as data, as %oth are .+9ed and fed to the flop#
9 !purious glitches# With asynchronous reset, unintended glitches will cause circuit to go into reset state# Ksually a glitch filter has to %e introduced right at the reset input port# )r one &ay have to switch to synchronous reset# 9 "f reset is internally generated and is not co&ing directly fro& the chip input port, it has to %e ecluded for +47 purposes# 7he reason is that, in order for the 7P' test vectors to wor correctly, test progra& has to %e a%le to control all flop inputs, including data, cloc and all resets# +uring the test vector application, we can not have any flop get reset# "f reset is co&ing eternally, test progra& hold it at its inactive value# "f &aster asynchronous reset is co&ing eternally, test progra& also holds it at inactive state, %ut if asynchronous reset is generated internally, test progra& has no control on the final reset output and hence the asynchronous reset net has to %e re&oved for +47 purpose# )ne issue that is co&&on to %oth type of reset is that reset release has to happen within one cycle# "f reset release happen in different cloc cycles, then different flops will co&e out of reset in different cloc cycles and this will corrupt the state of your circuit# 7his could very well happen with large reset distri%ution trees, where %y so&e of receivers are closer to the &aster distri%ution point and others could %e farther away# 7hus reset tree distri%ution is non9trivial and al&ost as i&portant as cloc distri%ution# lthough you don-t have to &eet sew require&ents lie cloc, %ut the tree has to guarantee that all its %ranches are %alanced such that the difference %etween ti&e delay of any two %ranches is not &ore than a cloc cycle, thus guaranteeing that reset re&oval will happen within one cloc cycle and all flops in the design will co&e out of reset within one cloc cycle, &aintaining the coherent state of the design# 7o address this pro%le& with asynchronous reset, where it could %e &ore severe, the &aster asynchronous reset co&ing off chip, is synchroni
Posted on July 1X, 2012 1
4ollowing three ite&s are essential for getting to the %otto& of Verilog eecution order# 1B Verilog event queues# 2B +eter&inis& in Verilog# 3B .on deter&inis& in Verilog# Verilog event queues /
7o get a very good idea of the eecution order of different state&ents and assign&ents, especially the %locing and non9%locing assign&ents, one has to have a sound co&prehension of inner worings of Verilog# 7his is where Verilog event queues co&e into picture# !o&eti&e it is called stratified event queues of Verilog# "t is the standard "@@@ spec a%out syste& Verilog, as to how different events are organi
4igure !tratified Verilog @vent Yueues# s per standard the event queue is logically seg&ented into four different regions# 4or sae of si&plicity we-re showing the three &ain event queues# 7he ["nactive\ event queue has %een o&itted as ]0 delay events that it deals with is not a reco&&ended guideline# s you can see at the top there is :active- event queue# ccording to the "@@@ Verilog spec, events can %e scheduled to any of the event queues, %ut events can %e re&oved only fro& the [active\ event queue# s shown in the i&age, the :active- event queue holds %locing assign&ents, continuous assign&ents# pri&itive ") updates and ^write co&&ands# Within [active\ queue all events have sa&e priority, which is why they can get eecuted in any order and is the source of nondeter&inis& in Verilog# 7here is a separate queue for the 8! update for the non%locing assign&ents# s you
can see that 8! updates queue is taen up after [active\ events have %een ehausted, %ut 8! updates for the non%locing assign&ents could re9trigger active events# astly once the looping through the [active\ and non %locing 8! update queue has settled down and finished, the [postponed\ queue is taen up where ^stro%e and ^&onitor co&&ands are eecuted, again without any particular preference of order# t the end si&ulation ti&e is incre&ented and whole cycle repeats# Deter&inis& in Verilog!
ased on the event queue diagra& a%ove we can &ae so&e o%vious conclusions a%out the deter&inis&# 9 ^stro%e and ^&onitor co&&ands are eecuted after all the assign&ent updates for the current si&ulation unit ti&e have %een done, hence ^stro%e and ^&onitor co&&and would show the latest value of the varia%les at the end of the current si&ulation ti&e# 9 !tate&ents within a %eginHend %loc are evaluated sequentially# 7his &eans the state&ents within the %eginHend %loc are eecuted in the order they appear within the %loc# 7he current %loc eecution could get suspended for eecution of other active process %locs, %ut the eecution order of any %eing##end %loc does not change in any circu&stances# 7his is not to %e confused with the fact that non%locing assign&ent 8! update will always happen after the %locing assign&ents even if %locing assign&ent appears later in the %egin##end order# 7ae following ea&ple# initial y < end
E _E E
%egin 0 3 X
When we refer of eecution order of these three assign&ents# 1B 4irst %locing state&ent is eecuted along with other %locing state&ents which are active in other processes# 2B !econdly for the non%locing state&ent only 68! is evaluated, it is crucial to understand that the update to varia%le :y- %y value of -3G doesn-t happen yet# 6e&e&%er that non%locing state&ent eecution happens in two stages, first stage is the evaluation of the 68! and second step is update of 8!# @valuation of 68! of non%locing
state&ent has sa&e priority as %locing state&ent eecution in general# 8ence in our ea&ple here, second step is the evaluation of 68! of non%locing state&ent and 3B third step is eecution of the last %locing state&ent :< E XG# 7he last step here will %e the update to :y- for the non%locing state&ent# s you can see here the %egin ## end %loc &aintains the eecution order in so far as the within the sa&e priority events# *B last step would %e the update of the 8! for the non%locing assign&ent, where :ywill %e assigned value of 3# 9 )ne o%vious question that co&es to &ind, having gone through previous ea&ple is that what would %e the eecution order of the non%locing 8! udpate ZZ "n the previous ea&ple we only had one non%locing state&ent# What if we had &ore than one non%locing state&ent within the %egin##end %loc# We will loo at two variation of this pro%le&# )ne where two non%locing assign&ents are to two different varia%le and the two non%locing assign&ents to sa&e varia%le ZZ 4irst variation# initial %egin E0 y _E 3
E0 y _E 3
)ne has to loo at the active event queue in the Verilog event queues figure, to get an idea as to where the non9deter&inis& in Verilog ste&s fro&# $ou can see that within the active event queue, ite&s could %e eecuted in any order# 7his &eans that %locing assign&ents, continuous assign&ents, pri&itive output updates, and ^display co&&and, all could %e eecuted in any rando& order across all the active processes# .on9deter&inis& especially %its when race conditions occur# 4or ea&ple we now that %locing assign&ents across all the active processes will %e carried out in rando& order# 7his is dandy as long as %locing assign&ents are happening to different varia%les# s soon as one &ae %locing assign&ents to sa&e varia%le fro& different active processes one will run into issues and one can deter&ine the order of eecution# !i&ilarly if two active %locing assign&ents happen to read fro& and write to the sa&e varia%le, you-ve a read write race# We-ll loo at Verilog race conditions and overall good coding guidelines in a separate post# 9!!# Posted in +igital +esign, Verilog ( 1 6eply
Interview #re#aration for a VLSI esign #osition
Posted on June I, 2012 !o&e people %elieve that eplicitly preparing for o% interview questions and answers is futile# ecause when it co&es to i&portant &atter of o% interview, what counts is real nowledge of the field# "t is not an acade&ic ea&, where tet9%oo preparation &ight co&e handy# $ou ust have to now the real deal to survive a o% interview# lso it is not only a%out the technical epertise that gets tested during o% interview, %ut it is also a%out your overall aptitude, your social sill, your analytical sill and %unch of other things which are at stae# greed, that it is not as si&ple as preparing few specific technical questions will lend you the o%# ut author-s perspective is that, one should prepare specific interview questions as a supple&ent to the real deal# )ne has to have the funda&ental technical nowledge, the technical a%ility, %ut it doesn-t hurt to do so&e targeted preparations for o% interview# "t is &ore of a %rush up of things, revision of old nowledge, tacling of so&e well9 nown technical trics and &ore i&portantly %oosting your confidence in the process# 7here is no har& and it definitely helps a lot to do targeted preparation for interview# .ot only one should prepare for technical questions, %ut there is a &ost often ased %ehavioral questions set also availa%le# )ne would %e surprised, how &uch the preparation really helps# "t really depends on which position you are applying# hip design involves several different sill and a%ility area, including 67 design, synthesis, physical design, static ti&ing analysis, verification, +47 and lot &ore# )ne has to focus on the narrow field relevant to the position one is interviewing for# /ost of the o% positions tend to %e related to !" design or the digital design# 7here are a few position in the custo& design, circuit design, &e&ory design and analog or &ied signal design# What helps is having /)! funda&ental understanding# /ore than you &ight reali
Posted in 'eneral ( eave a reply Lat$h using a 2/1 M34
Posted on /ay 11, 2012 fter the previous post a%out `.)6 gate using 21 /K`, one &ight have thought that finally we ehausted the nu&%er of gates that we could &ae using 21 /K`# ut that is not entirely true ZZ 7here are still &ore devices that we can &ae using a 21 /K`# 7hese are so&e of the favorite static ti&ing analysis and logic design interview questions and they are a%out &aing &e&ory ele&ents using the 21 /K`# We now the equation of a /K` is )ut E ! M O D!B%ar M We also now that level sensitive latch equation is "f D loc B Y E + 7his &eans if loc is high Y follows + Q else Y E Y "f cloc is off, Y holds previous state Q We can rewrite this as following Y E loc M + O DlocB%ar M Y 7his &eans we can easily &ae a latch using 21 /K` lie following#
atch using a 21 /K` When ; is high it passes through + to ) and when ; is off, ) is fed %ac to +0 input of &u, hence ) appears %ac at the output, in other words, we retain the value of ) when ; is off# 7his is what eactly latch does# !o what else can we &ae now ? 9!!
