Sect-5

Section 5: Inverter Operation & Control

Chapter 1 - Inverter Operating Principles

1.1 Introduction ........................................ .............................................................. ............................................ ................................ .......... 5-1 1.2 Inverter operating principles – power block ........................ ............................................. ..................... 5-1 1.2.1 Inverter-phase ‘switch’ analogy ..................................... ................................................... .............. 5-1 1.2.2 DC-AC Conversion (Output (Output AC voltage production) production) ................. 5-2 1.2.3 Pulse-width control of inverter voltage ............................. ........................................ ........... 5-3 Generating a sine-wave 5-6 1.2.4 Pulse Width Modulation (PWM) (PWM) control principles .................... 5-8 1.2.5 Inverter PWM duty cycle ................................................. ........................................................... .......... 5-10 1.2.6 Output filtering .............................................. ..................................................................... ............................. ...... 5-13 1.3 Inverter output output detail .......................................... ................................................................. .................................... ............. 5-15 1.3.1 Separately derived sources sources ...................................................... ......................................................... ... 5-18 1.4 Inverter IGBT transistor operation ........................................ ......................................................... ................. 5-19 1.4.1 Inverter transistor switching requirements requirements ................................. ................................. 5-19 1.4.2 Insulated Gate Bipolar Bipolar Transistor (IBGT) device ...................... ...................... 5-20 1.4.3 IGBT Device protection .................................... .......................................................... ......................... ... 5-22 1.4.4 IGBT Circuit design considerations .............................. ........................................... ............. 5-23 1.5 Power Power Inverter Construction ...................................... ........................................................... ............................ ....... 5-26 1.6 Inverter control system ............................................... ..................................................................... ............................ ...... 5-28 1.6.1 Electronic control principle .......................................... ........................................................ .............. 5-28 1.6.2 Control Control system overview ............................................ ........................................................... ............... 5-29 1.6.3 Inverter voltage control control .......................................................... .............................................................. .... 5-31 1.6.4 Inverter frequency control ............................................ .......................................................... .............. 5-32 1.6.5 Current protection .......................................... ................................................................. ............................ ..... 5-32 1.6.6 Fault detection & Stop/Start control .......................................... .......................................... 5-33 1.6.7 Control Control power supplies ........................................... .............................................................. ................... 5-33 Chapter 2 - Inverter Logic Board (4530025 T)

2.1 Chapter Chapter overview overview ........................................ ............................................................. ........................................... ...................... 5-35 2.2 General description ...................................................... ............................................................................. ........................... .... 5-35 2.2.1 Circuit Circuit board functions ............................................. .............................................................. ................. 5-35 2.2.2 Input/Output connections connections ........................................................... ........................................................... 5-35 2.2.3 Block Diagram ...................................................... ........................................................................... ..................... 5-37 2.3 Detailed Detailed circuit description ........................................ .............................................................. ............................ ...... 5-39 2.3.1 Introduction .......................................................... ................................................................................ ...................... 5-39 2.3.2 Reference Reference voltage voltage generator generator ...................................... ...................................................... ................ 5-39 2.3.3 Volts error amplifier ...................................... ............................................................. ............................ ..... 5-45 2.3.4 PWM Modulator .......................................... ................................................................. .............................. ....... 5-47 2.3.5 Current sensing and and Current limit .............................................. .............................................. 5-48 2.3.6 Drive pulse generator generator .................................... ......................................................... ............................. ........ 5-49 2.3.7 Fault detection logic .................................................. ................................................................... ................. 5-50

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SECTION 5 - In v er t er Op er at i o n & Co n t r o l

7200 Ser i es UPS Ser v i c e Man u al

2.3.8 Start/stop Start/stop logic ......................................... ................................................................ .................................. ........... 5-51 2.3.9 Power supply ........................................ .............................................................. ...................................... ................ 5-52 2.4 Summary Summary Information ........................................ ............................................................... .................................... ............. 5-53 Chapter 3 - Inverter Logic Board (4530024 S)

3.1 Chapter overview ........................................ ............................................................. ........................................... ..........................55 ....55 3.2 General description ........................................ .............................................................. ............................................ .......................55 .55 3.2.1 Circuit board functions functions ............................................... ..................................................................55 ...................55 3.2.2 Input/Output connections .............................................. ...............................................................55 .................55 3.2.3 Block Diagram ......................................... ................................................................ ......................................57 ...............57 3.3 Detailed circuit description .......................................... ................................................................. ..............................59 .......59 3.3.1 Introduction ......................................... ................................................................ ...........................................59 ....................59 3.3.2 Reference voltage generator generator ...................................... ..........................................................59 ....................59 3.3.3 Volts error amplifier ...................................... ............................................................. ................................65 .........65 3.3.4 PWM Modulator ............................................ .................................................................... ................................67 ........67 3.3.5 Current sensing and Current Curr ent limit ............................................. ..................................................68 .....68 3.3.6 Drive pulse generator .................................... ......................................................... .................................69 ............69 3.3.7 Fault detection logic .......................................... ................................................................. .............................70 ......70 3.3.8 Start/stop logic ......................................... ................................................................ ......................................71 ...............71 3.3.9 Power supply ......................................... ................................................................. .........................................72 .................72 3.4 Summary Information ........................................ ............................................................... ........................................73 .................73 Chapter 4 - Inverter Gate Driver Board

4.1 Chapter Overview ....................................... ............................................................. ........................................... ....................... 5-75 4.2 General description ...................................................... ............................................................................. ........................... .... 5-75 4.2.1 Circuit Circuit board functions ............................................. .............................................................. ................. 5-75 4.2.2 Input/Output connections connections ........................................................... ........................................................... 5-76 4.3 Detailed Detailed circuit description ........................................ .............................................................. ............................ ...... 5-76 4.3.1 Power Power supplies ......................................... ............................................................... .................................. ............ 5-76 4.3.2 Gate drive signal control control logic ................................................... ................................................... 5-76 4.3.3 Turning the inverter inverter transistor ON ............................................. ............................................. 5-78 4.3.4 De-saturation detector .............................................. ................................................................ .................. 5-78 4.3.5 Power supply monitor ......................................... ............................................................... ........................ 5-80 4.3.6 Other Other connections connections ....................................... ............................................................. ............................... ......... 5-80

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Section 5:

Chapter 1 - Inverter Operating Principles

1.1

Introduction The UPS inverter section converts the DC busbar voltage into a well regulated, three-phase alternating voltage suitable for powering the critical load. As the DC busbar voltage can vary typically between 432Vdc (when the batteries batteries are on float charge) and 320Vdc (the battery ‘end of discharge’ voltage) the inverter must be controllable over this entire input voltage range to ensure that the critical load voltage remains at the UPS nominal output voltage. The inverter control method used in the 7200 Series UPS equipment is known as ‘pulse width modulation’ (PWM), and is described in simple terms in this chapter. Liebert manufacture two designs of PWM inverter for use in large three-phase UPS systems. In general, modules rated below 200kVA employ three independent, but identical, inverter phases operating at 120° with respect to each other to produce the three-phase UPS output. Modules rated at 200kVA 200kVA and above employ a total of six inverter phases, with each UPS output phase obtained from two inverter phases operating in a ‘push-pull-like’ manner. These two types of inverter configurations are described as being ‘single-ended’ and ‘double-ended’ respectively. Note: As the 7200 Series UPS range are currently all less than 200kVA they all use a single-ended inverter design; however the double-ended design is also described in this chapter for completeness of explanation. e xplanation.

1.2 1.2 1.2.1 1.2.1

Inverter operating pri ncip les – pow er blo ck Inverter-phase ‘sw itch ’ analogy Each inverter power block (also called an “inverter phase”) basically comprises two IGBT transistors connected in series across the DC busbar, as shown in Figure 5-1. 5-1. In this diagram the transistor connected to the positive DC busbar is identified as TRH (High) and the one connected to the negative DC busbar as TRL (Low). The inverter output is taken from the junction of the two transistors. Figure 5-1: Inverter phase switch switch analogy DC BUS positive Inverter power block Pos. Bus

TRH O/P

Gate drive waveforms 180° output of phase

TRL Neg. Bus

DC BUS negative

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5-1

SECTION 5 - In v er t er Op er at i o n & Co n t r o l CHAPTER 1 - Inverter Operating Principles


When this circuit is used as a switch it has two stable states of interest: 1. When When TRH TRH is turned turned ON and TRL is OFF, the inverter output is effectively connected to the positive DC busbar and is approximately equal to the positive busbar voltage. 2. Similarly Similarly,, when when TRH is turned turned OFF and TRL turned ON, the output is connected to the negative DC busbar and is equal to the negative busbar voltage. For this circuit to operate successfully as a switch, the transistors’ base drive signals must always be in anti-phase – i.e. one of the transistors must be OFF while the other is ON. If both transistors are turned ON simultaneously they effectively place a short circuit across the DC busbar and will cause the equipment to shutdown, and possibly fail, due to a DC overload condition. Basic inverter block output waveform

As the inverter power block operates as a switch, its output voltage takes the form of a square-wave with a peak-to-peak amplitude equal to the D C busbar voltage, and at a frequency determined directly by the transistors’ drive signal switching rate (i.e. from the control electronics). Note that the DC busbar is derived from the phase controlled rectifier and is in practice approximately equidistant equidistant from ground (neutral) – e.g. if the bus voltage is 450Vdc then the positive bus will be about +225Vdc with respect to neutral (ground), and the negative bus about -225Vdc. 1.2.2 1.2.2

DC-AC DC-AC Conversio n (Outpu (Outpu t AC volt age prod ucti on) The above description showed that the basic inverter power bl ock output takes the form of an alternating (square) waveform; however, a substantial amount of control and power processing is necessary to convert this into a regulated sinusoidal voltage suitable for presentation at the UPS output. Figure 5-2: DC-AC Conversion (Step 1)

+ve Bu s (450V) (450V)

Block B

Block A

ON

ON

ON TR3

TR1

OFF

OFF

ON

B

OFF

ON

ON

Output Transformer TR4

TR2 OFF

OFF

OFF

A

ON

ON

Output Filter

OFF

OFF

-ve Bus (0V) To Load

Figure 5-2 illustrates 5-2 illustrates two power inverter blocks connected together by a transformer: with inverter block A consisting TR1/TR2 and block B consisting TR3/ TR4. As described in paragraph 1.2.1, 1.2.1 , the drive signals to each pair of IGBTs within an inverter block are always at 180° with respect to each other; however the diagram in Figure 5-2 also 5-2 also shows that the relative polarity of the signals to the

5-2

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7200 Series UPS Service Manual

SECTION 5 - Inverter Operation & Control CHAPTER 1 - Inverter Operating Principles

two inverter blocks are also in anti-phase – i.e. the drive signals to the ‘high’ transistors of Block A (TR1) and Block B (TR3) are in anti-phase, as are the signals to the two remaining transistors (TR2 and TR4). At the instant in time highlighted in Figure 5-2, TR1 & TR4 are both turned ON and TR2 &TR3 are OFF. This leads to the left-hand side of the output transformer primary winding being connected the positive DC bus (+450V) and the right-hand side to the negative DC bus (0V), and current flows through the primary winding in the direction A-to-B. Although at first glance this circuit may appear to present a short-circuit across the DC busbar, the current flowing through the transformer is limited by the impedance presented by the primary winding – which comprises the impedance of the transformer itself, together with the reflected impedance of the output filter and load (when connected). When the control electronics reverse the transistor drive signals TR1 & TR4 turn OFF and TR2 & TR3 turn ON. This reverses the polarity across the output transformer primary and, in this case, current now flows through the transformer from B-to-A, as illustrated in Figure 5-3. Figure 5-3: AC-DC Conversion (Step 2) +ve Bus (450V) ON

Block B

Block A

ON

ON TR3

TR1

OFF

OFF

OFF

ON

ON TR2

OFF

OFF

B

A

ON

ON

Output Filter

TR4

OFF

OFF

ON

OFF

-ve Bus (0V) Output to Load

Thus, by controlling the switching sequence of the two inverter blocks in relation to each other it is possible to build-up a current flow through the transformer primary in either direction, which leads to an ‘alternating current’ being induced in the transformer secondary and the production of an (alternating) secondary voltage. In practice the (‘output’) transformer is of a step-up design and its secondary voltage represents the required UPS ‘output voltage’. The output amplitude is controlled by using the ‘pulse-width modulation’ techniques described below, working in conjunction with the output filter to obtain a good sinusoidal waveshape. The output filter comprises a capacitor network tuned with the output transformer inductance to effectively remove the high frequency switching com ponents from the output waveform. 1.2.3

Pulse-width con trol of inverter volt age Before discussing in depth the pulse-width modulation (PWM) methods em ployed to control the inverter output voltage, it is necessary to gain a basic understanding of the effects of varying the pulse-width of the inverter drive waveforms together with the fundamental principles of the output filter. These are described immediately below.

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5-3



Figure 5-4: Effects of varying drive signal M:S ratio Bus +ve 2:1 Mark-Space

TRH

66%

TRL

Bus -ve Bus +ve 1:1 Mark-Space

TRH

50% TRL

Bus -ve

Bus +ve

1:2 Mark-Space

TRH

33%

TRL

Bus -ve

Basic control principles are best understood by considering the effects on the output waveform of a single inverter power block when switching the inverter transistors at a constant rate (‘modulation frequency’) but at various mark-space ratios. This is illustrated in Figure 5-4 above, which shows the inverter output waveform when TRH:TRL are turned on at ratios of 2:1, 1:1, and 1:2 respectively. The top diagram illustrates the case where the inverter is operating at a constant 2:1 mark-to-space ratio – i.e. TRH ON period being twice that of TRL – which results in a ‘mean’ output voltage (with respect to the negative DC busbar) ap proximately equal to 66% of the DC busbar voltage. In the middle illustration the transistors are shown operating at a M :S of 1:1 (i.e. equal ON and OFF periods). In this example the inverter output is a true square wave and has a mean voltage approximately equal to 50% of the DC busbar voltage – once again with respect to the negative DC busbar. A M:S ratio of 1:2 is shown in the lower illustration to produce a mean voltage of approximately 33%. Notice that in the above examples the inverter switching frequency is constant in all three cases and the ‘mean’ output voltage is varied by changing the mark-tospace ratio of the drive signals only.

5-4

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Basic filter principles

In the above examples the ‘mean’ output voltages are obtained by filtering the variable m:s pulse waveforms. The filter works by absorbing energy (charging) when the pulse is present (i.e. during the ‘mark’ period) and returning it back to the circuit (discharging) when the pulse is absent (i.e. the ‘space’ period). This has the effect of averaging-out the energy provided by each pulse over the complete pulse period (e.g. P1, P2...), as shown below in Figure 5-5 – i.e. the ‘mean’ value is the integral of the pulse width (shown shaded) taken over each complete pulse period (P1, P2 ....). Figure 5-5: Basic filter action 2:1 m:s waveform

Positive bus

Mark

100%

Space

66%

Filter 0%

Negative bus P1

P2

P3

The above 2:1 m:s waveform shows 3 pulses of mark+space period ‘P’. The waveform to the right illustrates the effects of the filter on period 1 ( P1) and shows how part of the energy ( A) absorbed during the mark period is put back into the circuit during the space period, leading to the ‘mean’ voltage shown.

A

‘mean’ voltage A

B

P1

This waveform illustrates the same principles at a 1:2 mark:space ratio. In this case less energy is stored during the ‘mark’ period due to its shorter duration; therefore the ‘mean’ value is lower.

A

‘mean’ voltage B

A

P1 Note that in each of the above examples the ‘mean’ voltage produced is represented by the area of the waveform’s ‘mark’ pulse – i.e. proportional to the width of the voltage pulse.

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5-5


1.2.3.1 1.2.3.1


Generating a sin e-wave

From basic principles, a sine-wave can be developed by plotting the vertical com ponent of a vector as it is rotated rotated through a complete circle. Figure 5-6: Instantaneous value of a rotating vector (π/2 rads) 90°

A

rotation 1

180° (π rads)

θ1

V t1

0 360° (2π rads)

270° (2π/3 rads)

This is illustrated in Figure 5-6, 5-6, which shows that when vector ‘A’ is rotated anticlockwise for time ‘t 1’, its vertical component ‘V 1’ can be described in trigonometrical terms as: V 1 = A sinθ1 – where θ1 is the angle of rotation (Equation 1).

When considering an electrical voltage waveform, the length of vector A represents the peak voltage voltage and V 1 represents the instantaneous voltage at time t 1. The relationship between the angle ‘θ1’ and time ‘t 1’ is determined by the ‘angular velocity’ of the vector, which is usually represented in mathematical equations by the greek letter omega (ω), where:

ω = 2π f rads/s rads/s (radians/second) (Equation 2). – i.e. 2π is the number of radians travelled in one complete revolution, and f is is the frequency of rotation in revolutions-per-second (Hertz). For example: at 50Hz the angular velocity of the vector is 2 × π × 50 = 100 π radians per second. Once the angular velocity (ω) of the vector is known, the instantaneous value of θ1 at time t 1 can be found by calculating the product of ωt . Using the previous – 3 50Hz example; if time t 1=2ms then θ1 equals 2 × π × 50 × 2 × 10 = 0.2 π radians (or 36°). By substituting 0.2π for θ1 and solving equation 1, the instantaneous voltage ‘V 1’ can be calculated as Asin0.2π which equals 0.588A – i.e. in electrical terms, V1 = 0.588 x V peak . Using the above principles, the instantaneous voltage V can can be calculated at a particular time t using the general formula V=A sinωt where: where: V = = instantaneous voltage A = peak voltage (length of the vector) ω = the angular velocity – in radians/s (i.e. = 2π f ) t = = instantaneous time (in seconds)

5-6

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Figure 5-7: Plotting a sinusoidal waveshape 90°

0/ 360°

180° t8

t7

t6

t 5

t 4

t 3

t 2

t1

t0

t0

0°

t1

t 2

t 3

t 4

90°

t 5

t6

t7

t8

180°

270°

270°

360°

t 9 t10 t11 t12 t13 t14 t15 t16 t0

0°

t1

t 2

t 3

t 4

t 5

t6

t7 t8

90°

The upper diagram in Figure 5-7 shows 5-7 shows how a sinewave shape is developed by plotting the instantaneous voltage amplitude at regular intervals as the vector is rotated from 0° (t 0) to 180° (t 8 ) and transferring these values to a linear scale. The lower diagram illustrates the formation of one complete cycle, which is obtained by continuing with the plotted points from 180° (t 8 ) to 360° ( t 16 ) to provide the negative half cycle. For reasons of clarity, the sampled intervals in the above diagrams are quite large – i.e. only 16 samples are taken in the complete cycle. A much ‘cleaner’, more accurate, waveform is produced if the sampling rate is increased: and in the practical 7200 series PWM control circuit the sine-wave is generated using 48 reference points per-cycle as opposed to the 16 points shown here.

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5-7


1.2.4 1.2.4


Pulse Width Modulati on (PWM) (PWM) cont rol pri ncip les Pulse-width modulation entails generating rectilinear output voltage pulses at a repetition frequency considerably higher than the fundamental frequency (50Hz) and modulating their duration so that the integrated value of each pulse is proportional to the instantaneous value of the required fundamental component at the time of its occurrence: that is, the pulse duration is modulated ‘sinusoidally’. This is illustrated in Figure 5-8. 5-8. Figure 5-8A 5-8A is an expanded view of the positive half-wave sinewave plotted in Figure 5-7. 5-7. Note that the voltage sampling rate shown is the same as the pulse repetition rate and the instantaneous voltages at t 0 to t 8 coincide with the centre of each pulse period: for example, the instantaneous voltage at time t 1 coincides with the centre of the period allocated for pulse 2 ( P2). Figure 5-8B 5-8B shows the individual pulses P1-P9 superimposed on the instantaneous voltage plot and illustrates how varying pulse-widths are employed to ensure that the ‘mean’ value of the pulse equals the plotted instantaneous value for the particular pulse period. In each case the pulse amplitude is identical and compriscomprises a ‘shaded’ and ‘hatched’ area – where the ‘shaded’ portion resents the ‘mean’ amplitude. For example, the ‘mean’ value resulting from the mark:space ratio of the pulse during P3 equals the instantaneous voltage plotted at t 2. This is shown in more details in Figure 5-8C 5-8C where the hatched portion at the top of pulse P3 is shown to replace the space left at either side of the pulse – as described in the discussion of the basic filter principles Figure 5-5. 5-5. Note: to simplify explanation, the filter description in Figure 5-5 implied 5-5 implied that the drive pulse signal took the form of a mark followed followed by a space; however from the control electronics point of view this is not the case, as shown in Figure 5-8. 5-8. It is true that the pulse repetition rate is constant, but the ‘variable’ pulse-width is controlled by expanding and contracting the pulse about its centre point (known as “double pulse-width modulation”). This does not affect the way in which the output filter works, as the filter ‘sees’ only the presence or absence of pulses, and stores and restores energy to the output circuit as previously described – i.e. the output filter effectively ‘joins the dots’ by storing and shaping the pulse-width modulated waveform to make the output envelope as near as possible to a sinewave.

A representative complete output cycle is shown in Figure 5-12. 5-12. The practical modulating frequency

As will be explained later, there are several considerations to be taken into account when deciding upon a modulating frequency, as this affects such things as the generated output harmonics; inverter switching losses; and filter efficiency and size. In general, Liebert-designed PWM inverters employ modulating frequencies ranging from 2.4kHz to 9.6kHz. In the 7200 UPS equipment the modulating frequency is fixed at 2.4kHz, which therefore means that 48 switching pulses are used to produce each 50Hz (20ms) output cycle – i.e. the output waveform is corrected every 7.5° (0.13 rad), leading to a very accurate output waveform. The design specification is to produce a voltage sinewave with less that 5% THD for all rated input and load variations.

5-8

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Figure 5-8: PWM Control principles P1

P2

P3

P4

P5

P6

P7

P8

P9

t0

t1

t 2

t 3

t 4

t 5

t6

t7

t8

A

0°

90°

180°

P1

P2

P3

P4

P5

P6

P7

P8

P9

t 0

t1

t 2

t 3

t 4

t 5

t6

t7

t8

B

0°

90°

180°

P1

P2

P3

P4

P5

P6

P7

P8

P9

t 0

t1

t 2

t 3

t 4

t 5

t6

t7

t8

C

0°

90°

180°

P1

P2

P3

P4

P5

P6

P7

P8

P9

t 0

t1

t 2

t 3

t 4

t 5

t6

t7

t8

D

0°

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90°

180°

5-9


1.2.5


Inverter PWM dut y cycl e The power delivered to the load by the inverter can be described mathematically as the integral of the voltage & current (i.e.

π ⁄ 2

∫

VI d t ).

0

A PWM-controlled inverter provides load power each time it is turned on; therefore the power produced by the inverter during each output cycle is represented by total area of the pulses contained in that cycle. Thus, when dealing with a PWM waveform the integral equation above can be visualised by considering that “the area of the output sinewave is equal to the sum of the areas of the individual pulses used to generate the sinewave” (See Figure 5-9). Figure 5-9: Output power derivation

The total amount of time the inverter IGBT devices are turned ON and delivering load-power during each output cycle can be described in terms of the inverter’s ‘duty cycle’: and, as will be shown below, this varies in accordance with the available DC busbar voltage and the prevailing load current demand. Figure 5-10: Typical inverter output section Bus +ve R

(450Vdc – 320Vdc) S

O/P Transformer

T

O/P Filter

1:2 STEP-UP

R

R S

S

T

T

Critical load supply (400VL-L)

(200VL-L) N

Bus -ve

The effects of the DC Busbar voltage on the PWM Duty cycle

Figure 5-10 illustrates a typical UPS output section set to operate at the standard 400V output voltage. The output transformer has a 1:2 voltage step-up ratio, therefore the inverter must operate at 200VL-L. 200VL-L is equivalent to 115V L-N (i.e. 200 ⁄ ( 3 ) .) which is in turn equal to ap proximately 325V p-p (i.e. 2 × 115 × 2 ). The inverter cannot produce a peak-to peak output voltage greater than the DC busbar voltage, therefore the output waveform would clearly be clipped if the DC busbar falls below this 325V minimum level.

5-10

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Figure 5-11: Effects of falling DC busbar voltage on the PWM duty-cycle DC bus + (+225Vdc)

DC busbar 450Vdc

Combined area of pulses equals the area under output sine-wave

Inv output 326Vp-p

DC bus - (-225Vdc)

DC bus + (+225Vdc) Combined area of pulses still equals the area under output sine-wave DC busbar 360Vdc

Inv output 326Vp-p

DC bus - (-225Vdc)

In practice, the minimum DC busbar voltage is programmable and is usually set to 1.67V per battery cell. The number of batteries connected to the busbar varies according to the UPS working voltage. A standard 400V system employs 198 cells which leads to a minimum DC busbar voltage of 330V. Therefore, in a practical 400V system the DC busbar will vary between 450Vdc when the batteries are being float charged and 330Vdc at the ‘end-of-discharge’ voltage – at which point the inverter is shut-down and the load transferred to bypass (if available). Note 1: Diagrams in this manual may indicate a minimum DC busbar voltage of 320V. This is in fact the minimum DC voltage at which the inverters are fully rated and not necessarily the voltage at which the batteries are tripped off-line. Note 2: The battery end-of-discharge voltage is also load dependant (see paragraph 3.3.7 on page 7-29) .

It has already been shown that in each output cycle the area of the sine-wave is equal to the combined area of the associated PWM pulses; and also that the am plitude of the inverter pulses is equal to the DC busbar voltage. Therefore, when the batteries are on-load, and the DC busbar voltage discharges from 450V to 330V, the width of the PWM pulses must increase proportionally as their amplitude decreases in order to maintain a constant output voltage. This is illustrated in Figure 5-11 which shows the effects on the PWM pulse-width as the DC busbar reduces from 450V to 360V. Notice that this diagram shows that the peak, and therefore r.m.s., value of the inverter output remains constant as the bus voltage

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5-11



falls. Once again, for reasons of clarity the illustration in Figure 5-11 uses only 16 PWM pulses-per-cycle rather that the 48 pulses used in the practical 7200 series inverter. With regards to the duty cycle: when the inverter is off-load and the DC busbar is operating at its float charging voltage of around 450Vdc the sum of the inverter conduction pulses amount to approximately 75° of the possible 180° forming each half cycle a.c. conduction period. When the DC busbar is supported from the discharging batteries the duty cycle increases to approximately 105° when the batteries approach the end-of-discharge voltage of 330Vdc. The effects of the Load demand on the PWM Duty cycle

The PWM wave-form duty cycle is directly affected by variations in the demanded load current. For example, the previous paragraph illustrated that when operating off-load from the normal 450V busbar, the duty cycle is approximately 75°. However, if the inverter is loaded under these conditions it would require that the individual PWM pulse-widths are increased to maintain the output waveform whilst allowing more power through to the load. In practice, at a nominal 450V DC busbar the 7200 inverter duty cycle increases from 75° to approximately 80° over the fully rated load range. If the PWM duty cycle increase with falling DC busbar voltage and also with l oad then the worst case conditions obviously occur when the inverter i s operating near the end-of-discharge voltage and at full load. Under these conditions the duty cycle will increase to approximately 110°. Note: as the duty cycle from no-load to full-load increases from 75° to 80°; and the increase from float voltage to end-of-discharge voltage causes an increase of 70° to 105°, it can be seen that the duty cycle is affected more by changes in DC busbar voltage than changes in load demand.

5-12

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1.2.6


Output fil tering Figure 5-12: One cycle of PWM control pattern

c e s m 0

c e s m 5

c e s m 0 1

c e s m 5 1

c e s m 0 2

20 msec Bus +ve

TRH

0V TRL

Variable m:s over 20 msec

Bus -ve 50Hz sinewave obtained by filtering the output PWM pattern

Figure 5-12 illustrates the production of one PWM output cycle at 50Hz and shows that the positive half cycle is created by beginning with a 1:1 ratio and then increasing it to a higher ratio and back to 1:1 using a controlled pattern. The negative half cycle is produced in an identical manner; but in this case the ratio begins at 1:1 and is then reduced to a lower ratio before returning to 1:1. The sinusoidal output waveform is obtained be employing a filter which, in simple terms, averages out the modulated waveform on a pulse-by-pulse basis and thereby produces an output which rises and falls in a sinusoidal manner. In practice, this is achieved by a network of filter capacitors working in conjunction with the inductance of output transformer to bypass the inverter modulation frequency and its associated generated harmonics. Figure 5-13: Filter current characteristics

Filter currents

Filter charging

Filter discharging Output waveshape

s5-c1.f m5 - Issu e 2 Dated 21/08/97

5-13



Figure 5-13 illustrates the filter action in detail. The diagram represents four 2.4kHz pulses at the beginning of the output positive half-wave and shows the effects of the charging and discharging filter currents during the presence and absence of the PWM pulses – i.e. the filter capacitors charge-up whilst a pulse is present (storing energy) and then discharge when the pulse ceases (returning energy into the output circuit to maintain the general output voltage waveshape). As the PWM mark:space ratio gradually increases the resulting waveshape closely resembles the required sine-wave. Clearly, the charging and discharging filter currents are directly related to the number of PWM pulses contained in the output cycle – i.e. the modulating frequency. Where a fewer number of pulses are used per half-cycle, the overall pulse-widths must increase to allow the filter to store a larger current during the charge period in order to restore sufficient energy to the output circuit during the discharge period to maintain the sinusoidal output waveshape; thus requiring larger capacitors and inductors to handle the increased circulating power. However, although the required L-C components get smaller as the modulating is increased, the inverter switching losses also increase and the overall inverter conversion efficiency therefore reduces. The selected modulating frequency is therefore a compromise between these two conflicting factors. An acceptable mean is reached when using a frequency in the range 2.4kHz to 9.6kHz, and in the 7200 series UPS an optimal frequency of 2.4kHz is used.

5-14

s5-c1.f m5 - Issu e 2 Dated 21/08/97



Section 5:

1.3

Inverter outp ut detail Figure 5-14: Inverter output – basic block diagram

OUTPUT TRANSFORMER

POWER INVERTER

Bus +ve

R

1:2

+450Vdc

S T

0Vdc Bus -ve

OUTPUT FILTER

R

R

S

S

T

T

N

N

200Vac

400Vac

Bus +450Vdc

c d V 0 0 3

V 0 0 4

0 V 2 3

R o t a t i o n

c d V 5 2 2

Neutral c d V 5 2 2

DC Bus 0V

The inverter converts the DC primary source (nominal 450V DC busbar) to a balanced 3-phase vector system on the UPS output. The inverter output is steppedup by a factor of 1:2 by the output transformer, which also provides galvanic isolation; therefore an inverter output of 200V L-L is required to furnish the standard 400VL-L UPS output voltage – Figure 5-14 contains a block diagram of the inverter output stage and a vector diagram which shows the relationship between the DC primary source (DC bus) and the AC secondary objective (UPS output). The output neutral point is manufactured by the output transformer’s star-connected secondary and is positioned exactly at the mid-point of the DC primary source at all times – i.e. +225V or -225V with respect to the nominal 0V or 450V DC input rails respectively. The neutral is in fact floating about this mid-rail point and remains so as the busbar voltage decreases towards 320V when powered from the discharging batteries. As described earlier, (see "The effects of the DC Busbar voltage on the PWM Duty cycle" on page 5-10), the mark:space ratio of the PWM drive signals are varied to compensate for such DC busbar voltage fluctuations; however, as is evident from Figure 5-14, a stage is reached whereby the available DC primary source is inadequate to sustain the output objective (even though the PWM duty has gone to maximum). In the 7200 series equipment this occurs when the DC busbar falls

s5-c1b .fm5 - Iss ue 2 Dated 21/08/97

5-15



below 290V. When this point is reached the output transformer will saturate and cause flat-topping of the output voltage waveforms. Note that the inverter itself is not affected and does not mind running on low input DC sources. In practice, the inverter is turned off before the DC voltage reaches this absolute minimum level. In the case of a 400V operating system the “end-of-battery” discharge (DC undervoltage) threshold is set to approximately 330Vdc, as described earlier in this chapter (See Figure 5-11) . Figure 5-15: Single-ended inverter output stage

Bus +ve

Three inverter phases

(450Vdc – 320Vdc)

R

S

O/P Transformer

T

O/P Filter

1:2 STEP-UP

R

R S

S

T

T

Critical load supply (400VL-L)

(200VL-L) N

Bus -ve

Figure 5-16: ‘Double ended’ inverter output stage Bus +ve n i a M h p R

n i a M h p S

x u A h p R

x u A h p S

n i a M h p T

x u A h p T

Bus -ve

R

S

T

S

T

Output Transformer

R

Filter Capacitor s

N

R

S

T

To load via the Inverter-side static switch (contactor)

5-16

s5-c1b.fm5 - Issue 2 Dated 21/08/97



Figure 5-15 illustrates the single-ended inverter output design, as employed in the lower-rated 7200 Series product range, whereby the output transformer is connected in a standard delta-star configuration. The output filter capacitors are connected to the transformer secondary line-to-line and work in conjunction with the transformer’s natural impedance to remove all remnants of the modulation frequency from the output waveform and so leave a clean sinewave suitable for connecting to the load, via the inverter-side static switch (contactor). A double-ended inverter output section, as employed in larger modules, is shown in Figure 5-16. This design uses two power inverter blocks per output phase, known as the ‘main’ and ‘auxiliary’ inverters. The transistors in each ‘inverter pair’ are switched in anti-phase with respect to each other – i.e. when the top transistor is turned on in the ‘main’ inverter the bottom transistor is turned on in the ‘auxiliary’ inverter (and vice-versa). This enables more power to be delivered to the load, as described below. An alternative way of increasing the output power, for a given busbar voltage, is to use a number of IGBTs connected in parallel in each leg of the inverter power block; however, due to difficulties with device matching, the inverter MTBF is adversely affected as the number of parallel devices is increased. Using the double-ended inverter topography means that no more than two parallel-connected devices are needed for the highest power rating offered in the 7200 UPS range. As shown below, the power increase offered by a double-ended over a singleended inverter is equal to 3 – i.e. the relationship between a single-phase and three-phase system. Figure 5-17: ‘Single-ended’ versus ‘double-ended’ primary current path

Bus +ve

Bus +ve 2 x 400A IGBTs

2 x 400A IGBTs

800A 1 I

92kW

A 0 0 8

I 2

c a V 0 0 2

160kW

2 x 400A IGBTs

Bus -ve

Single-ended – closed delta pri mary


c a V 0 0 2

2 x 400A IGBTs

Bus -ve

Double-ended – singl e phase primary

5-17



Figure 5-17 shows the comparative primary current flows in the ‘single-ended’ and ‘double-ended’ inverter output transformers. In the ‘single-ended’ circuit the transformer primary windings effectively form a closed delta circuit, and the current supplied by one inverter power block is always shared between two windings. In the case of the ‘double-ended’ circuit the output transformer primaries are individually connected between the ‘main’ and ‘auxiliary’ power blocks of their respective phases, effectively acting as three single-phase windings; therefore the full current passes through each individual winding. 1.3.1

Separately derived sou rces The inverter itself can be considered analogous to a generator in its own right. Full noise rejection is achieved via the AC–DC–AC conversion, and the output transformer is double-wound, with isolation between primary and secondary. This im plies that there is no direct connection between the input mains and the inverter output – i.e. it offers a separately derived power source. Figure 5-18:

Bypass Mains Supply

To Load

Input Mains Supply

Rectifier

Inverter

Isolation Transformer

Static Switch

Battery

Perfectly balanced 3-phase bypass source

T

R 2 3 0

4 0 0

N

S

Potential difference between both neutrals (10V - 1000V)

R 2 3 0

T

4 0 0

N

S

Perfectly balanced 3-phase Inverter source

5-18




The bypass supply is an alternative supply to which the load is transferred if the inverter is switched off, or fails for any reason. A ‘no-break’ changeover is required during such transfers to ensure the load sees no interruption. The 3-phase voltage (live wires RST) manufactured by t he inverter are electronically linked to the bypass 3-phase supply voltage (live w ires RST) via the static switch. The inverter neutral point is developed in the output transformer wye (zigzag) secondary, and if this point is not tied to the bypass neutral than a potential difference may exist between the inverter and bypass power sources (it is possible for this to extend from 10V right up to 1,000V). To prevent this potential from appearing the output transformer neutral must be directly tied to the bypass neutral. If this is not done the potential difference between both sources would induce a spike in the neutral during load transfers which might damage the load equipment.

1.4 1.4.1

Inverter IGBT tr ansisto r operation Inverter transi stor swit chin g requir ements When used in a power inverter environment, the inverter transistor is basically acting as a power switch, and like all switches it ideally has two stable states: 1. When it acts as an ‘open switch’ the transistor is fully turned OFF and exhibits a high impedance. In this condition the collector current (Ic) is low (virtually zero) and the voltage across the collector and emitter (Vce) is very high (almost equal to the DC bus voltage). 2. When it acts as a ‘closed switch’ the transistor is turned ON and exhibits a low impedance. In this condition the transistor is in fact driven hard into saturation. Its collector current is therefore high (as determined by the prevailing load) and Vce low (equal to the saturation voltage of the device). Since power is calculated as the product of the current flowing through the device ( Ic ) and the voltage dropped across it ( Vce ), the transistor's power dissipation ( Ic x Vce ) is very low in both its steady states – because Ic is very small when the transistor is turned OFF, and Vce is very small when it is turned ON . When the transistor switches from one state to the other, however, its dissipated power rises to a peak and then returns to minimum as it traverses the linear region of its particular load characteristic. Transistors do not turn OFF and ON instantaneously; their turn ON and turn OFF times are determined both by their internal construction and external circuit influences. It is important, therefore, that transistors with fast switching times are used in power inverter applications and sufficient drive power is used to ensure the time taken to switch from one stable state to the other is as fast as possible, to prevent the power dissipation reaching destruction level. Note: as stated earlier, the 7200 series UPS uses a 2.4kHz switching frequency; that is, the power IGBTs are each individually switched off/on at 2.4kHz. Thus the IGBTs turn off and on 2400 times per second. Multiplying by minutes and hours, this equates to 207.36 million on/off transitions per day. Considering that there are 6 IGBT block (switching 300A @450Vdc) on smaller inverters, and increasing to 24 blocks (switching 800A @ 450Vdc) on larger modules. This leads to an enormous amount of power switching over the inverter’s design life (10Yrs): hence annual preventive maintenance is highly recommended.


5-19


1.4.2


Insulated Gate Bip olar Transis tor (IBGT) device The 7200 series inverters use Insulated Gate Bipolar Transistors (IBGTs), which combine the advantages of both FET and Bipolar transistor technologies to offer a fast switching, high current device with a high gate impedance and low Vce saturation voltage – these devices are described in detail below. The IGBT is a voltage-driven element, but to turn it ON and OFF requires charging and discharging currents for the input capacity (C IES) because the IGBT has a capacitance between adjacent terminals – as illustrated in Figure 5-19. Figure 5-19: IGBT details Collector

Collector

Gate Gate Emitter

RBE C

CCG

Emitter

Cies = CCG + CGE CCE

G

Coes = CCE + CCG Cres = CCG

E

CGE

Figure 5-20: IGBT high-speed switching surge voltages Ic Vce

High surge voltage (snubber required)

High critical rate-of-rise of collector currents (di/dt)

High critical rate-of-fall of collector currents (di/dt)

time t on

t of f

Comparison of typical bipolar/IGBT device switching times Parameter

5-20

Bipolar

IGBT

Turn on time (ton)

1 µsec

0.7 µsec

Turn off time (toff )

12 µsec

0.8 µsec




The IGBT is a high-speed switching element. As the IGBT switches on and off a large current at a high speed, the critical rate-of-rise (or fall) of collector currents (di/dt ) is considerably high and can result in the generation of high surge voltages – as illustrated in Figure 5-20. 1.4.2.1

IGBT Switching characteristics

Figure 5-21: IGBT Switching waveform GATE

EMITTER

+15V VGE

N°

P

+

N° N°

+

+

Rβ

+

+ +

+

+ - -

-15V

-

+

+

Ic

90%

P° 10% COLLECTOR

On-state electron/hole currents within IGBT structure

tdon tr ton

tdoff

tf toff

Figure 5-21 illustrates the IGBT switching characteristic. The upper waveform represents the idealised gate/emitter drive pulse (VGE); and the lower waveform depicts the resulting collector current (Ic). As can be seen from the lower waveform the total ‘turn-on’ time ( t on) is the time taken for the collector current to rise to 90%, and is made up of two components, t don + t r where: t don is the ‘tun-on delay time’ and is the time taken to attract electrons to the

region underneath the gate (i.e. holes migrate from the N-region to the Pregion) and is usually of the order of 250nsecs. t r is the ‘rise time’ and is the time required for the collector current to i ncrease

from 10% to 90% of its final value. This is directly proportional to the gate impedance (i.e. the gate construction and internal input capacitance) and is usually of the order of 500 nsecs. The total ‘turn-off’ time is the time taken for the collector current to fall to 10%, and is made up of two components, t doff + t f where: t doff is the device ‘turn-off delay time’ and is the time taken to remove the

electrons from the region beneath the gate. This is usually of the order of 350nsecs. t f is the device ‘fall time’ and is the time taken by the collector current to fall

to 10% of its initial value. This is the time taken to recombine the majority carriers (holes) back to the N-region and is usually of the order of 350nsecs. Propagation delay = t on + t off and is of the order of 1.5µs.


5-21


1.4.2.2


IGBT Gating requi rements

For ‘turn-on’ a positive gate voltage of 15V ±10% is recommended. This value is sufficiently high to fully saturate the IGBT and minimise the on-state losses, while it is sufficiently low to limit short-circuit current and its resulting stress. In no case should a gate drive outside the range of 12V-20V be used for turn-on. An IGBT will be off when its gate voltage is zero. However, in order to ensure that the IGBT stays in its off-state when dv/dt noise is present in the collector emitter voltage an off bias must be used. Use of reverse bias also decreases turnoff losses. For H-series IGBTs an off bias of -15V is recommended. 1.4.2.3

RG Series Gate Resistance

Selecting the proper series gate resistor is very important as it has a significant impact on the dynamic performance of the IGBT which is turned on and off by charging and discharging the gate capacitance. A smaller gate resistor will charge/discharge the gate capacitance faster, reducing the switching times and switching losses. However, under short-circuit, or during turn-off of the free-wheeling diode across the IGBT, t he dv/dt applied to the IGBT and its collector-to-gate capacitance can cause a current to flow in the gate circuit. And if this current is large enough, the voltage developed across the gate resistor can cause the IGBT to turn-on. Thus, while a smaller resistor offers enhanced ruggedness (rejection of dv/dt turn-on), they also provide less margin for gate noise and can lead to oscillation problems in conjunction with the gate-emitter capacitance and any parasitic inductance in the gate wiring. In addition, smaller gate resistors allow faster turn-on di/dt of the IGBT and may cause an increased surge voltage at forward recovery. Giving consideration to all the above effects, a resistor value between 1R - 10R is recommended for the series gate resistance. 1.4.3 1.4.3.1

IGBT Device pro tect io n Snubb er cir cui t

Figure 5-22: Turn-off surge voltage Ic

VCE

Surge voltage ∆V

Ed

t

A snubber circuit is connected across the IGBT’s collector-emitter to suppress any (potentially destructive) switching surge voltages which may otherwise occur when the IGBT is turned off. The surge voltage is due to l oad inductance and the recovery of the internal free-wheel diode, and its ra te if rise ( ∆V) depends on the turn-off speed. The snubber usually comprises a capacitor (or resistor/capacitor network) which is sized to keep the ∆V below the IGBT collector-emitter breakdown voltage. The snubber activates when the collector-emitter voltage exceeds the DC power source (i.e. Ed in the above diagram). The excess stored charge must be dissipated before the IGBT begins its next turn-off operation, either through a resistor or output circuit impedance.

5-22



1.4.3.2


Desaturatio n detecto r

The IGBTs saturation voltage (V CE(sat)) is the voltage drop across the IGBT collector-to-emitter when it is in the fully ON state. The saturation voltage is a function of the collector current (ICE), junction temperature (Tj) and gate-emitter voltage (VGE) and is typically 2.5V - 4.0V at +15V GE and full ICE at Tj = 125°. VCE(sat) increases proportionally with increases in I CE and Tj and is inversely pro portional to changes in VGE. IGBT protection is incorporated by monitoring the voltage drop across the device when it is ON and inhibiting the gate drive pulse if the monitored voltage rises the permissible saturation voltage range. This function is provided by the individual inverter Gate Driver Boards. 1.4.4 1.4.4.1

IGBT Circui t design cons ideration s Flywh eel dio de

Figure 5-23: Flywheel diode action 450V

Vsurge 800Vdc On

Conducted back to DC Caps via flywheel diode

R1

T1 (primary) 451V

450V

C1

R2 0V

0V

In the 7200 Series UPS inverter application, the IGBT is switching a PWM waveform into the output transformer primary. This primary is in fact a large inductor and due to its magnetic properties will cause overshoot on the leading edge as each pulse is applied. The size of the overshoot depends on both the transformer and load inductance. The IGBT’s internal flywheel diode will be forward biased once the overshoot exceeds the DC Busbar voltage by about 1V and, once it conducts, will pass the excess energy due to the overshoot back into the DC busbar smoothing capacitors. Since the diode has a fixed turn-on time, the surge voltage is suppressed by the snubber network until the diode becomes forward biased.


5-23


1.4.4.2


Device ratin gs Voltage rating

From a design point of view, the maximum voltage applied to the device comprises four elements: ( Input volts(dc) x 2 ) + regen volts + surge volts + safety margin From this it is desirable that the inverter input bus voltage should account for about 50% - 60% of the IGBT rated voltage. The internal flywheel diode has the same voltage rating as the IGBT. Current rating

For safe operation the IGBT peak current must not exceed the device rating. In general, the short-circuit rating of the inverter is set to 150%. Therefore, assuming maximum current flows in such an overload event the desired steady-state current should be approximately 50% - 60% of the maximum device rating. Inverter (kVA) × Overload rate The general formula is: I peak = --------------------------------------------------------------------------- × 2 × 1.2 AC Volts (rms) × 3

(where 1.2 is the ripple factor)

Example: Select devices for 60kVA, 380V unit with 150% overload capacity: 60, 000 × 1.5 Current =  -------------------------------  × ( 2 × 1.2) = 232 Amps  380 × 3  Voltage = 500 (max DC) × 2 = 1000V

Nearest device to fit these ratings is 300A x 1200V

Note: The internal free-wheel diode is designed on the premise that a very short current flows, so that steady state rating is regarded to be a pproximate half of that of the main IGBT. Junction temperature

IGBT power modules have a maximum rated junction temperature of 150°C. It is therefore desirable to run the device under steady state at no more than 70% of its maximum rating. Heat generated by the component is a mixture of both conduction and switching losses. Conduction losses (P ss) occur while the device is ON and conducting current. The total power dissipation during conduction is the product of the saturation voltage Vsat (approximately 4V) and the on-state current (Ic) (max 300A). Switching losses (P sw) is the power dissipated during the turn-on and turn-off switching transitions: Psw = F pwm x (Esw(on) + Esw(off)) Where: F pwm = Inverter switching frequency (2.4kHz) (Esw(on) + Esw(off) = switch ON/OFF energy in joules/pulse Total loss per device = P ss + Psw

5-24



1.4.4.3


Parallel devic es

In larger inverter power blocks two IGBTs may be connected in parallel in each arm of the inverter. Under such circumstances it is desirable that the current is shared between the two parallel-operating devices to within 10% of each other and it is necessary to match the devices such that their Vce (sat) values are within 0.3V of each other. To this end each device is ranked according to its Vce(sat) measurement, as shown in the table below. Table 5-4: IGBT Rankings Type

Vce (sat )

C

1.7 – 1.95

D

1.9 – 2.15

E

2.1 – 2.35

F

2.3 – 2.55

G

2.5 – 2.8

H

2.75 – 3.05

J

3.0 – 3.3

K

3.25 – 3.55

L

3.5 – 3.8

M

3.75 – 4.05

Note: IGBTs of different Vce(sat) values can be used in an inverter, but it is necessary to use ranked devices in any parallel arm, and preferably in the complete power block. Across power blocks, the output transformer inductance slows down any possible fault current. Further-more, the maximum current allowed is derated by 15% of both IGBT ratings (e.g. 2 x 300A = 600A x 0.85 = 510Amps).

Other influences on parallel device operation are: •

Inductance in the main circuit wiring – minimised by using low-inductance symmetrical wiring. • Driver wiring and differences in driver output impedance – minimised by using twisted-pair conductors of short lengths. • Equalisation of operating temperatures – temperature equalisation assisted by using equal device mounting and torque values.


5-25


1.5


Power Inverter Constr ucti on The power inverters are of modular design. The power components are mounted on a heatsink assembly which is then affixed to the UPS back-wall. The inverter modules fitted within the UPS are identical and interchangeable. That is, the R, S and T inverter phases may be swapped over for troubleshooting if necessary and an inverter module from any position in one UPS may be exchanged for any inverter module in another (provided that they are of the same power rating). All the inverter modules are similarly constructed: in that the module contains:• •

The inverter IGBTs (transistors) An overtemperature-sensing thermostat fitted to the power block heatsink – thermostats of all three (six) inverter phases are electrically connected in series to provide a normally-closed circuit. • Base Driver Board (See Chapter 4) The Base Driver Board sits above the snubber capacitor and is fitted to four mounting pillars. Connections between the base driver board and the inverter transistors are made by tagged flying leads which are colour coded as follows: Black = Collector White = Base Red = Emitter Flying leads are also used to connect the thermostat to Base Driver Board terminals S and T. Connection between the Base Driver Board and the Inverter Logic Board is made by a ribbon cable which fits into a keyed socket connector (CN1).

5-26




Figure 5-24: Power inverter construction (60kVA)


5-27


1.6


Inverter cont rol syst em

1.6.1

Electronic control princip le The following overview of the electronic control methodology is provided before the detailed explanation of the inverter control logic in order to bridge the gap between the previous description of the power objectives and the electronic control source. The control process used to manufacture the PWM waveform can be considered as the reverse of that used by the power section to convert the PWM waveform into a sinewave; as described in paragraph 1.2.3.1. Figure 5-25: PWM Signal production (2.4kHz) 416µs

Reference Waveform (V R)

Carrier Waveform (F c)

PWM Waveform 20ms (50Hz)

The control mechanism compares a sinusoidal reference waveform with a triwave carrier and produces a PWM pattern which changes state each time the reference waveform crosses the carrier, as shown in Figure 5-25. In the 7200 equipment the tri-wave carrier amplitude is fixed, and its frequency is governed at 2.4kHz. The reference waveform mimics the UPS output voltage and therefore has a 50/60Hz base frequency. As the above illustration shows, when the reference waveform (VR ) rises above the tri-wave (Fc) the output PWM pattern switches high, and vice-versa. Each PWM pulse-width is therefore directly proportional to the instantaneous mean value of the sinewave reference and is presented to the power IGBTs. The inverter output therefore replicates the reference sinewave, and changes in output voltage amplitude and frequency are achieved by altering the appropriate parameter of t he basic reference voltage waveshape (VR ). Carrier ratio (P)

The ratio of the carrier waveform frequency to the reference waveform frequency determines the number of PWM pulses present per output c ycle. In the 7200 series UPS this equates to 2400/50 = 48. Therefore the inverter output will comprise 24 pulses in each of its output positive and negative half cycles. Note: although the carrier frequency is said to be “fixed” it will in fact vary slightly with the UPS base frequency as it tracks the bypass frequency as part of its synchronisation control process. This results in 48 PWM pulses per cycle at all times.

5-28




Another consideration, is that the carrier frequency must be divisible by the number of output inverter phases (three in this case). This is necessary in order that all three phases may be maintained at exactly 120° with respect to each other. The selected carrier frequency (2.4kHz) also limits the size of the maximum pulse allowed in the PWM pattern: = 1--- therefore the maximum pulse width 1 = ------------ = 0.416 ms 2400

t

The smallest permissible pulse is a function of the IGBT propagation delay (See section 5 paragraph 1.4.2) and determined on the Base Driver Board. The delay is of the order of 4µs. 1.6.2

Contro l system overview Figure 5-26 shows the circuit boards associated with the inverter control system together with their major control signals. The Inverter Logic Board is central to the inverter control system and is the board ultimately responsible for generating the inverter IGBT gate drive signals at the appropriate pattern to effect the PWM control techniques described earlier in this chapter. At its heart is a complex, analogue voltage regulation circuit which uses the inverter voltage and inverter current sense signals within a series of closedcontrol loops to maintain the required inverter voltage. It also contains a digital based frequency control system which synchronises the inverter frequency to the bypass supply; and also maintains the inverter frequency at 50Hz (60Hz) when the bypass supply is unavailable. Note that whilst individual voltage regulation circuits are used for each phase, the frequency control logic applies to all three phases to ensure their correct phase relationships are observed at all times. The control system offers the following features, each of which is functionally described in the remainder of this chapter: • • • • •

Output voltage limits selectable from the Operator Control Panel. Individual voltage regulation and current limit control on each phase. Overload protection of each inverter power circuit IGBT. Output overvoltage and undervoltage fault detection. Output frequency, synchronising window, slew-rate selectable from the Operator Control Panel. • Controlled start/stop features. • Power supply monitor 1.6.2.1

Analogue contr ol signals Inverter voltage sense

The 3-phase inverter voltage is sensed at a point between the output transformer and inverter-side static switch (contactor), and should therefore be at the nominal UPS output voltage whenever the inverter is operating. The three independent line-to-neutral sense signals are attenuated to 1% on the High Voltage Interface Board and then passed to the Inverter Logic Board via the UPS Logic Board. On the Inverter Logic Board the sense signals take the form of ‘voltage feedback’ inputs to the voltage regulation control loops. On the UPS Logic Board, the sense voltage are converted to a digital form and monitored by the board’s microprocessor system.


5-29



Figure 5-26: Inverter control system Bypass-side Static Switch

Bypass Supply

Inverter Section

filter capacitors

DC Bus Pos 3 Phase Power Inverter

+

Inverter-side Contactor d a o L l a c i t i r C

Output Tfrmr

-

DC Bus Neg + Inverter Base Drive Bds.

Inverter Logic Board

e s n e s t n e r r u c r e t r e v n I

e s n e s e g a t l o v r e t r e v n I

e s n e s e g a t l o v s s a p y B

Alarm Interface Board (I/O Option) UPS Logic Board Operator Logic Board Remote Alarms

High Voltage Interface Board

1.6.2.2

Operator Control Panel

Analogue contr ol signals Inverter voltage sense

The 3-phase inverter voltage is sensed at a point between the output transformer and inverter-side static switch (contactor), and should therefore be at the nominal UPS output voltage whenever the inverter is operating. The three independent line-to-neutral sense signals are attenuated to 1% on the High Voltage Interface Board and then passed to the Inverter Logic Board via the UPS Logic Board. On the Inverter Logic Board the sense signals take the form of ‘voltage feedback’ inputs to the voltage regulation control loops. On the UPS Logic Board, the sense voltage are converted to a digital form and monitored by the board’s microprocessor system. Inverter current sense

The inverter output current is monitored by ‘Hall effect’ current sensors mounted on the inverter S and T phases. These sense signals are attenuated on the High Voltage Interface Board (by link selectable burden resistors) and then passed to the Inverter Logic Board via the UPS Logic Board.

5-30




Bypass voltage sense

The 3-phase bypass voltage is sensed at a point between the bypass isolator and the bypass-side static switch, and should therefore be at the nominal mains voltage whenever the bypass switch is closed. The three independent line-to-neutral sense signals are attenuated to 1% on the High Voltage Interface Board and t hen passed to the UPS Logic Board. On the UPS Logic Board, the bypass voltage sense signals are converted to a digital form and monitored by the board’s microprocessor system. 1.6.2.3

Digital contr ol signals

Various digital signals are passed between the UPS Logic Board and all the other boards connect to it. These can broadly be categorised as: •

alarm data generated on the Inverter Logic Board and UPS Logic Board which are passed to the Operator Control Panel via the Operator Logic Board – also to the Alarms Interface Board (for remote indication) where fitted. • inverter stop/start control signal generated on the UPS Logic Board in response to other ‘system’ control parameters and applied to the Inverter Logic Board as appropriate • control data entered at the Operator Control Panel which is stored by the UPS Logic Board – e.g. inverter voltage and frequency parameters. • external control options – e.g. remote stop, emergency shutdown, sync inhibit. 1.6.3

Inverter volt age con trol Working voltage selection and basic control loop

The inverter voltage is controlled by an analogue circuit on the Inverter Logic Board which instantaneously compares the inverter voltage sense signal with an on-board generated sinusoidal reference voltage (See paragraph 2.3.2) . Any error detected between these two signals is applied to the PWM pattern generator in such a manner as to make the inverter output waveform follow that of the reference sinusoid. This circuit therefore forms a closed-loop control mechanism which produces a tightly regulated output voltage (See paragraph 2.3.3). Independent circuits are employed for each of the output three phases; and potentiometers are included in the ‘S’ and ‘T’ phase inverter voltage sense (feedback) signals’ path to enable the voltage of all three phases to be manually balanced, if necessary, to overcome the effects of component tolerances or excessively unbalanced load distribution. The sinusoidal reference voltage amplitude can be selected to be one of three levels, equating to 200V/220V/240V, as calibrated by a single potentiometer on the Inverter Logic Board; however, the chosen level is selected by digital control signals generated on the UPS Logic Board in response to data entered via the Operator Control Panel (See Table 5-2). Voltage error detection

All three inverter voltage sense signals are applied to a full-wave rectifier on the UPS Logic Board and the resulting signal is digitised and monitored by software controlled undervoltage and overvoltage detection functions. These are once again programmable from the Operator Control Panel and are normally set to ±10%.


5-31



In the event of a voltage error occurrence the UPS Logic Board will: • • • 1.6.4

send a STOP signal to the Inverter Logic Board to turn off the inverter. transfer the load to the bypass supply through the static switch operation. initiate the appropriate alarm indications on the Operator Control Panel.

Inverter frequency cont rol Reference voltage generator

As explained above, the closed-loop inverter voltage control circuit operation (on the Inverter Logic Board) forces the inverter output to track the sinusoidal ‘reference voltage’. Therefore, the ‘reference voltage’ must also determine the inverter frequency in addition to voltage. The ‘reference voltage generator’ is a digital circuit which produces three synthesised sinusoidal 50Hz(60Hz) waveforms – one per inverter phase (See paragraph 2.3.2). Its frequency is determined by a frequency reference signal produced by the UPS Logic Board’s microprocessor system which is normally synchronised to the bypass supply and reverts to the ‘base’ frequency (50/60Hz) when the bypass supply is unavailable (See Figure 5-29) – note: synchronisation is maintained during normal operation to allow a ‘no-break’ load transfer to take place between the inverter and bypass if necessary. Although the actual reference voltage generator is situated on the Inverter Logic Board, the previous paragraph shows that the UPS Logic Board microprocessor provides the essential frequency control signals. The frequency control parameters are therefore entered into the UPS Logic Board’s memory via the Operator Control Panel. There include: • •

base frequency selection – i.e. 50Hz or 60Hz. bypass sync window (normally ±2%) – i.e. the frequency extremities to which the inverter is allowed to operate whilst tracking the bypass supply. • tracking slew-rate (normally ±0.10Hz/s) – i.e. the maximum permissible rate of change of inverter frequency whilst tracking the bypass supply. Note that if the bypass frequency changes faster than the programmed slew-rate then an “out of sync” error will be present during the periods of non-synchronises operation. External “Sync Inhibit”

In some installations a stand-by generator is used to provide an alternative input (bypass) supply when the normal mains supply is unavailable. If such a generator has unsuitable frequency regulation the inverter synchronisation function on the UPS Logic Board may be inhibited by an external inhibit signal applied via the one of the Remote Alarms Board options. This input would typically be slaved to auxiliary contacts of the generator line contactor. Note that a ‘sync error’ condition will be prevalent while the synchronisation circuit is overridden. 1.6.5

Current prot ection There are three forms of inverter current protection control: •

5-32

Inverter current limit – the inverter output current sense signals are applied to a current limit circuit on the Inverter Logic Board which restrict the current on an individual phase to approximately 150% of its nominal rating. If the phase current reaches this level the phase voltage will be reduced to a level which sustains this limit – i.e. if there is a short circuit on the critical bus then the




inverter PWM pattern will be reduced to a minimum and the inverter will deliver 150% current at a very low voltage in an attempt to clear the short (See paragraph 2.3.5) .

1.6.6

•

IGBT overload protection – Desaturation detection circuits built into each Inverter Gate Driver Board inform the Inverter Logic Board of an overload condition on any of the inverter IGBT devices which will then cause its internal start/stop control logic to shut down the inverter operation (and subsequently transfer the load to bypass).

•

Output overload – When the inverter is on-load the output current is monitored by the UPS Logic Board and a software-controlled timer function provides an inverse load/time shutdown facility which trips the inverter off-load – i.e. the larger the overload the faster the trip action. The load profile is: – 150% for 1 minute – 125% for 10 minutes – 110% for 1 hour – 101% for 10 hours

Fault detection & Stop/Start cont rol The inverter is stopped and started in a controlled manner by a Stop/Start circuit on the Inverter Logic Board which monitors the output from several on-board fault detection circuits together with a ‘system-controlled’ general Stop/Start command signal applied from the UPS Logic Board. The fault conditions monitored on the Inverter Logic Board include: •

IGBT overload (from desaturation detector circuits on the Inverter Gate Driver Boards) • Disconnected ribbon cable on cards associated with the inverter control circuits – as seen in Figure 5-26 • Inverter Logic Board power supply monitor The general Stop/Start command signal applied from the UPS Logic Board is controlled by various functions, such as: • • • • • 1.6.7

DC undervoltage (end of battery discharge) DC overvoltage Emergency stop Operator-selected start/stop commands from Operator Control Panel Inverter overvoltage

Contro l pow er supp lies The Inverter Logic Board and Gate Driver Boards are powered only from the DCDC Power Supply Board which is itself powered from the DC busbar. This means that the inverter control circuit is active only when the DC busbar is ‘live’ – i.e. if the power rectifier is operational or the battery circuit breaker is closed. The remaining circuit boards concerned with the inverter control function are powered from either the AC-DC Power Supply Board or the DC-DC Power Supply Board and are active when either supply is ‘live’.


5-33


5-34



Section 5: EP i.e. the larger

Chapter 2 - Inverter Logic Board (4530025 T)

Section 5:

2.1

Chapter overview This chapter contains a circuit description of the Inverter Logic Board Part N º 4530025-T, which is used across the whole 7200 Series UPS model range, and should be read in conjunction with circuit diagram SE-4530025-T (5 pages). This is a direct replacement for PCB Part Nº 4530024-S which may be fitted to modules manufactured prior to February 1997. Although there are only minor differences between the two PCBs a full description of the Inverter Logic Board Part Nº 4530024-S can be found in Section 18 Chapter 3. Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. [BLK-INV>.

2.2 2.2.1

General descri pti on Circuit board functio ns The Inverter Logic Board board is responsible for providing the drive signals for the inverter IGBT transistors at the appropriate PWM (pulse width modulated) pattern to produce the required inverter output voltage and frequency. In so doing, the board monitors the following UPS parameters vi a the High Voltage Interface Board and UPS Logic Board: • • • •

Inverter voltage – closed loop voltage regulation Inverter current – IGBT protection Bypass voltage – for inverter synchronisation System control signals from the UPS Logic Board micro (Run/Stop, Voltage/frequency selection, Current limit selection) • Soft-start – 10 cycles to energise the output magnetics on start-up As part of its control function, the board detects several abnormal operating conditions and provides the UPS Logic Board control system with the following error status signals: • • • • 2.2.2

Inverter overload Inverter On/Off status Control power supply failure IGBT failure

Input/Outpu t con nectio ns The Inverter Logic Board has six connectors, described below: • • • • • •

X1 – Output drive signals to Inverter Driver Board 4519015-H (R-phase) X2 – Output drive signals to Inverter Driver Board 4519015-H (S-phase) X3 – Output drive signals to Inverter Driver Board 4519015-H (T-phase) X4 – Control signals to/from UPS Logic Board (See Table 5-1) X5 – Power supply inputs from DC-DC Power Supply Board X6 – To Auxiliary Inverter Logic Board (used in large inverters only)

s5-c2.f m5 - Issu e 2 Dated 21/08/97

5-35

SECTION 5 - Inverter Operation & Control CHAPTER 2 - Invert er Logi c Board (4530025 T)


Table 5-1: connector X4 (to UPS Logic Board) pinout details PIN

I/O

1-4

I/O

0V power supply rail

5-8

I/O

+12V power supply rail

9 - 12

I/O

-12V power supply rail

13

I

Common – analogue feedback voltage ref

14

I


15

I

[VI_A> Bypass A-ph volts sense from HVI Board – 8Vp-p

16

I

[VI_B> Bypass B-ph volts sense from HVI Board – 8Vp-p

17

I

[VI_C> Bypass C-ph volts sense from HVI Board – 8Vp-p

18

I

[VIN_A> Inverter A-ph volts sense from HVI Board – 8Vp-p

19

I

[VIN_B> Inverter B-ph volts sense from HVI Board – 8Vp-p

20

I

[VIN_C> Inverter C-ph volts sense from HVI Board – 8Vp-p

21

I

[IINV_A> Inverter A-phase current sense from HVI Board

22

I

[IINV_B> Inverter B-phase current sense from HVI Board

23

I

[IINV_C> Inverter C-phase current sense from HVI Board

24

I

[XINV_OI> Mains error – load transfer to inverter = 1

25

I

[DREF> Output voltage adjustment - used in parallel modules

26

I

[DREF0> Output voltage adjustment - used in parallel modules

27

I

[DV-A> Load sharing input for parallel modules only

28

I

[DV-B> Load sharing input for parallel modules only

29

I

[DV-C> Load sharing input for parallel modules only

30

I

[DV-0> Load sharing input for parallel modules only (common)

31

I

[INV_L> ‘Inverter on load’ commanded on UPS logic Board – Load-on-inverter = 1

32

O

[OVL_INV> Inverter overload status to UPSLB micro (OVL = 0)

33

O

[BLK_INV> Inverter On/Off status to UPSLB micro (Off = 1)

34

O

[BACK> Frequency sync signal fed back to UPSLB micro – pulse

35

I

[SYNC> Reference frequency produced by UPSLB micro – pulse

36

I

[ON_INV> Inverter On/Off control from UPSLB micro (Off = 0)

37

I

[INV_F> from UPSLB micro (Inv Freq - used in ref w/form gen) – 50Hz = 0 and 60Hz = 1

38

I

[INV_A> from UPSLB micro - used in output volts selection

39

I

[INV_B> from UPSLB micro - used in output volts selection

40

O

Thermostats output to UPSLB (optional)

5-36

Function

s5-c2.f m5 - Issu e 2 Dated 21/08/97


2.2.3

SECTION 5 - Inverter Operation & Control CHAPTER 2 - Inverter Lo gic B oard (4530025 T)

Blo ck Diagram Figure 5-27 shows the Inverter Logic Board at its most basic functional block diagram level – the basic function of each of the blocks shown is described below, with a more detailed, component level description provided in the remainder of the chapter. Figure 5-27: Inverter Logic Board basic block diagram Inverter I sense (x3)

Inverter Current Sense

Inverter Volts F/B (x3) (actual)

Bypass Freq Output Volts Select

Bi-directional Control (UPSLB) (UPSLB) DC-DC Supply

PWM Modulator

Volts Error Amplifier

Frequency

Reference Control Voltage Tri-wave (x1) Generator Start/ Stop Logic Power Supply

Drive Pulse Generator

Inverter IGBT Drive Pulses

l ) o r 3 x t n ( o s C e g a C t l A o v

AC Reference voltages (x3)

Bypass Volts F/B (x3)

Overload (x3)

PWM (x3)

d r a w r o f d e e F

Parallel Current share (∆V Adj.)

Current Limit

e p n i o l t l S / o r t r t n a t o S c

Fault Detection Logic ±12V ±5V

Reference voltage generator

The ‘reference voltage generator’ produces three AC reference sine waves at 120° with respect to each other which act as voltage demand signals to the ‘volts error amplifier’. These signals dictate the amplitude, frequency and waveshape of the eventual inverter output voltage. Volts error amplifier

This block compares the AC reference signals with voltage feedback signals derived from the inverter output, and produces error signals proportional to any detected amplitude difference. Three individual error amplifiers are contained in this block, one for each phase, which means that each inverter phase is individually controlled. Note that the outputs from this block are annotated “ AC control” signals, as it is these signals that ultimately determine the adopted PWM pattern which in turn directly determines the inverter output three phase voltage.

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5-37



In a parallel module (1+1) installation an additional input is applied to the volts error amplifier to control the inter-module output current-sharing by effecting individual fine control over each inverter phase output voltage. The error signal is produced by the Parallel Logic Board (see paragraph 2.5 on page 8-31) and applied to the volts error amplifier as a ∆V adjustment. The maximum voltage correction from this signal is ±5% of nominal inverter output. Current limit

AC signals proportional to the inverter output current are processed by the ‘inverter current sense’ circuit and fed to the ‘current limit’ block where they apply a current limit function to the ‘drive pulse generator’ circuit if the current reaches 150%. Three independent circuits are contained in this block, one per phase, so each output phase is individually controlled. Modulator

This circuit modulates the AC control signals with a 2.4kHz tri-wave signal, produced by the ‘reference volts generator’, and generates three PWM waveforms. Once again three independent circuits are used, one per phase. Drive pulse generator

The ‘drive pulse generator’ converts the PWM signals into suitable IGBT base drive signals. This block contains interlocking logic to prevent the simultaneous triggering of both IGBTs in an inverter phase, a high frequency modulator, overload protection and general start/stop control of the output drive waveforms. Start/stop logic and Fault detection

Numerous fault detection circuits are contained on the board. These control the internal start/stop control lines to the ‘reference volts generator’ and ‘drive pulse generator’, and also provide status signalling to the UPS Logic Board micro for use by the system control logic. Signals from the UPS Logic Board to this (Inverter Logic) board also effect start/stop control in accordance with the system’s control logic demands. Power supply

The Inverter Logic Board is powered from the DC-DC Power Supply Board, which is live whenever the power rectifier is operational or the batteries are connected to the busbar via the battery circuit breaker. This power source provides ±12V d.c. power rails which are then diode blocked to the second supply source (from the AC-DC Power Supply board) the UPS Logic Board – hence the board will be powered only from the DC-DC Power Supply but once the mains fails (i.e. the AC-DC Power Supply is off) the DC-DC Power Supply will keep all the circuit boards energised. On-board 5V regulators, fed from the ±12V rails, provide stabilised ±5V power rails for those devices that require it.

5-38

s5-c2.f m5 - Issu e 2 Dated 21/08/97


2.3 2.3.1


Detailed cir cui t descrip tio n Introduction The Inverter Logic Board circuit diagram (SE-4530025-T) comprises 5 sheets. With reference to the block diagram in Figure 5-27, the drawings can broadly be described as follows: • • •

• •

2.3.2

Sheet 1 contains a ‘signal map’ showing the interconnection of the signals passing between the other four sheets. Sheet 2 contains the reference voltage generator circuit Sheet 3 contains the: – ‘volts error amplifier’ circuit – ‘current limit’ circuit – ‘PWM modulator’ circuit Sheet 4 contains the ‘current sense’ circuit and current limit detector Sheet 5 contains the: – ‘drive pulse generator’ circuit – ‘start/stop logic’ circuit – ‘fault detection logic’ circuit

Reference vol tage generat or (circuit diagram sheet 2) Figure 5-28: Reference voltage generator block diagram

volts adj (R242)

[INV_A> [INV_B>

Set Volts V-peak

[BLK> Stepped waveform

Resistor Ladder

[INV_F> [S_TRI>

Staircase Pattern Generator

Multiplexer

Filter

Multiplexer

Filter

AC Reference Voltage

[REF_A>

[REF_B>

φ Disp. adj (R247) [O_BACK> [O_SYNC>

Freq-reference

s5-c2.f m5 - Issu e 2 Dated 21/08/97

Phase Locked Loop

C Phase Reference Generator Tri wave Generator

[REF_C>

[TRI>

5-39



This circuit is responsible for producing three sinusoidal voltages, spaced at 120° with respect to each other, which are then connected to the ‘volts error amplifier’ in the form of AC reference voltages. The voltages produced by this circuit can thus be considered as ‘voltage demand’ signals, and represent the amplitude, frequency and wave-shape desired at the inverter output voltage. Multiplexer operation

The ‘reference voltage generator’ circuit’s operation is centred around D3 and D4. These are 8-channel multiplexers whose 8 data lines are connected to various points along a resistor ladder network (R1-R12), and whose 3 data-select lines are clocked by the ‘staircase pattern generator’, ASIC D1. Each multiplexer output (pin 3) is thus connected to one of 8 discrete voltage levels tapped along the resistor ladder depending on the state of the data-select inputs. In practice, the logic sequence of the signals to the three data-select inputs, from D1, are such that a stepped waveform is produced at the multiplexers’ outputs which takes the broad form of a full-wave rectified a.c. voltage – (See Figure 528).

Voltage control. As the voltages at each stage of the stepped waveforms equal the voltages present along the resistor chain, the stepped waveform peak voltage is determined by the voltage at the top of the chain – i.e. the voltage at buffer N2c pin 8. This is controlled by the circuit block annotated ‘set volts’ in Figure 5-28 and described in detail below. Waveshape control. The AC reference voltage waveshape is determined solely by the sequential logic within D1 and cannot be adjusted. Frequency control. The AC reference voltage frequency is determined by the clock frequency applied to the ‘staircase pattern generator’ (D1 pin 43), as this controls the rate at which the multiplexers step through their sequence. This is controlled by a phase locked loop which is normally synchronised to the bypass supply frequency – described later (See Figure 5-29). Set volts & Resistor ladder

As described above, the ‘set volts’ circuit (See Figure 5-28) provides a controlled voltage at the top of the resistor ladder which thereby determines the peak value of the AC reference voltages – and thus also the inverter output voltage. It is possible to select one of three output working voltages: 380V, 400V and 415V. This is achieved by two signals from the UPS Logic Board annotated [INV_A> and [INV_B> which are connected to the data-select inputs of D7, which is a dual 4-channel multiplexer. The inputs to the ‘X’ channel (‘1X’ to ‘4X’) of D7 are connected to regulated DC voltages which represent the various UPS working voltages. These are selected by the [INV_A> and [INV_B> to appear at the ‘X’ output as follows: Table 5-2: Working voltage selection (D7)

5-40

[INV_A>

[INV_B>

Channel

Volts

0

0

X1

380V

0

1

X2

400V

1

0

X3

415V

1

1

X4

Manual Set

s5-c2.f m5 - Issu e 2 Dated 21/08/97



The voltages applied to ‘1X’, ‘2X’ and ‘3X’ are produced by a resistor network connected across a variable regulated dc power rail which is itself connected between the 0V and -12V supply rails; the voltages are therefore of a negative polarity. In practice, R242 is adjusted to obtain approximately -4V across N4; this voltage is then divided by R54 - R57. The response of the inverter voltage control loop is such that the signal at D7 ‘X’ output has a sensitivity of approximately 92Vac/V – e.g. a voltage of approximately -4.5V is required to produce an inverter output voltage of 415Vac. R242 thus provides the means of calibrating the output voltage when the UPS is operating. Note: R242 adjusts the voltage of all three phases. Further resistors are provided which individually adjust the B and C phase line voltages and can be used to balance the output line voltages if necessary – described later (see page 5-45). The ‘manual’ mode is elected by the UPS Logic Board in response to the operator input and is designed to be used in a ‘test’ environment. When this mode is selected the output voltage can be varied by means of R243 (0-600Vac), which is connected between the -5V rail and ground, and whose wiper voltage is connected to D7 ‘X4’. The selected voltage at D7 output (pin 13) is inverted to a positive voltage by N3b and buffered by N2c before it is applied to the top of the resistor ladder network (this voltage can be monitored at test point X8-4 where it has a sensitivity of ap proximately 0.01Vdc/Vac output. e.g. a level of 4.1Vdc is equivalent to 400Vac on the inverter output). An output from the ‘start/stop logic’, annotated [BLK> on the circuit diagram, reduces N3b voltage to zero when the inverter is being commanded OFF . This reduces the voltage at the top of the resistor ladder to zero which thus results in a “zero voltage” demand to the inverter voltage regulation circuit. [BLK> goes

high when in the stop/start logic is in its ‘ STOP’ mode which clamps the input to N2 pin 10 to 0V via V41. When this signal switches to its ‘ START’ mode (low), V41 turns off but the voltage rise at N2 pin 10 is slugged by R50/C14 to restrict the rate of increase of the inverter demand voltage. This soft-start action takes approximately 10 cycles to complete and is designed to slowly energise the output magnetics and thus reduce the inverter start-up surge current. Note: The inputs to the ‘set volts’ circuit from X4 pins 25/26 and amplifier N3a are not used, and play no part in the stop/start function. Staircase pattern generator

The ‘staircase pattern generator’ is based on D1, which contains a complex series of synchronous logic gates and timers and produces two sets of signals which are connected to the multiplexer data-select inputs – e.g. output A1-C1 are connected to multiplexer D4 and outputs A2-C2 to multiplexer D3. The sequence of these outputs, which is determined solely by D1’s internal logic, produce stepped signals at the multiplexer outputs which resemble a full-wave rectified waveform. Two frequency-related signals are applied to D1. An input to D1 pin 44, annotated [INV-F>, controls one of D1’s internal dividers and sets the inverter nominal base frequency. This signal, which is logic high for 60Hz operation and low for 50Hz, is produced on the UPS Logic Board in response to inputs from the Operator Control Panel. The input to D1 pin 43 is a 288kHz clock signal, produced by a phase-locked-loop (PLL) circuit, which controls D1’s internal operation. Note: The PLL determines the inverter free running frequency and is normally synchronised to the bypass supply (See Figure 5-29).

s5-c2.f m5 - Issu e 2 Dated 21/08/97

5-41



In addition to the multiplexer data-select signals described above there are several other frequency-related outputs from D1. •

The outputs from pins 31 (D2) and 36 (D1) are square-waves at the nominal base frequency which determine the zero-crossover points of the inverter output and S phases respectively. These are connected to the filter section – described later (see page 5-44) . • The output from pin 40 is a 2.4kHz square-wave which is converted to a tri-wave by the ‘tri-wave generator, described below, for further use by the ‘PWM Modulator’ (See paragraph 2.3.4). The frequency of this signal is determined by the logic levels at pin 1 (S2) and pin 2 (S3), as selected by X-15 links 1 and 2 – detailed on sheet 1 of the circuit diagram. Table 5-3:

5-42

X15(0-1) S2

X15(0-2) S3

Frequency

Usage

Open (0)

Open (0)

1.2kHz

N/A

Closed (1)

Open (0)

2.4kHz

All models

Open (0)

Closed (1)

4.8kHz

N/A

Closed (1)

Closed (1)

9.6kHz

N/A

•

The output from D1 pin 28 (ST2), annotated [S_TRI>, is connected to the ‘drive pulse generator’ block where it modulates the ultimate output drive waveform (See paragraph 2.3.6) . Once again the frequency of this signal is controlled by links on X15. Normally, it is a 2.4kHz square-wave.

•

The output from D1 pin 27 (PLL), annotated [O_BACK> (test point X8-5) via D99, is connected to the UPS Logic Board via a variable resistor (R247) – shown on sheet 5 of the diagram (See Figure 5-29). This signal is a square-wave at the nominal base frequency coinciding with the zerocrossover point of the A-phase AC reference voltage (i.e. the actual inverter frequency at the moment). On the UPS Logic Board a phase-com parator function within the microcontroller compares this signal with a similar signal derived from the bypass supply R-phase and is thus able to detect an out-of-phase conditions. R247, located in the [O_BACK> line, allows any residual phase displacement between the inverter and bypass R-phase waveforms to be nulled once the two sync signals are phaselocked.

•

The output from D1 pin 21 [O_SYNC> is connected to one of the phase locked loop (PLL) phase comparators’ inputs. The square-wave signal at this point is a synchronizing frequency as selected by the PLL software routine on the UPS logic board. This can be at the bypass frequency, the previous frequency or base frequency as shown in Flow Chart 7-4 & Flow Chart 7-5 in Section 7 Chapter 7. Due to the phase locked loop action (described below) this signal is aligned with the A-phase inverter zerocrossover point.

s5-c2.f m5 - Issu e 2 Dated 21/08/97



Figure 5-29: Frequency synchronisation control X2 D42

62

15

D53

5

F-IN

Bypass supply R-phase voltage sensing

18

F-INM

X4

X3 63

4

16

BACK

BACKM

D17 R E L L O ) 2 R T T N R O O C P ( O R C I M

15

INV-F

34

34

37

37

[O_BACK>

INV-F

44

50 /60 Hz (Selected from Operator Panel)

DATA BUS

D1 Frequency Divider

27

Staircase Generator R247 phase align

43 K288kHz L C(nominal)

2-3 = Single 1-2 = Parallel

D59 14

4

X34 1

Phase Locked Loop

2 15 64

3

5

SYNCM Pulses proportional to phase error between Inverter & Bypass mains

SYNC

35

Master Freq reference for Inverter Osc

UPS Logic Board

35

D10 13

14 12

9 VCO

Phase Comparator

13

n o i t c e r r o C F

z H 0 6 / 0 5

D6 3 [I_SYNC> Phase error signal

Inverter Logi c Board

Phase locked loop (PLL)

A PLL (D6) provides the clock signal for the ‘staircase pattern generator’ and thereby has direct control over the inverter output frequency. This is a standard type 4046 i.c. which contains two types of phase comparators (only one of which is used) and a voltage controlled oscillator (VCO) centred at 288kHz. One of the phase comparator’s inputs (D6 pin 14) is driven by a square-wave frequency reference signal, annotated [SYNC>, which is produced by the UPS Logic Board microprocessor system. That is, this signal relates to the error between the inverter and bypass frequency, as calculated by the microprocessor, which then adds a percentage gain correction under its slew rate program. The signal is then presented to the PLL phase comparator – e.g. if there is an instant change to the bypass frequency from 50Hz to 51Hz, the microprocessor detects an error of 1Hz. This error is then divided by the slew rate e.g 0.1Hz/Sec, and the [SYNC> signal is modified from 50Hz to 51Hz in increments of 0.1 over a 10 second period. The other phase comparator input, to D6 pin 3) is driven by a 50/60Hz output from the ‘staircase pattern generator’ (D1 pin 26) which is described above. If the comparator’s input signals are out of phase the phase comparator output (D6 pin 13) will either add or subtract voltage to C2 (depending on the phase relationship) and apply an error correction signal to the VCO’s control input (D6 pin 9) – i.e. the VCO frequency is effectively made to track the frequency reference signal.

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For example – if the bypass frequency rises slightly, the following actions will take place: 1. The sync control function on the UPS Logic Board will increase the [SYNC> signal frequency by an appropriate amount, determined by the microprocessor under the control of the slew rate programme. 2. When the PLL compares the [SYNC> signal with the base frequency signal from the ‘staircase pattern generator’ it will detect that the [SYNC> signal is of a slightly higher frequency and the output from D6 pin 13 will exhibit logic high pulses equal to the periods of phase difference. 3. The pulses at D6 pin 13 are filtered and applied to the VCO control input at D6 pin 9 in the form of a dc correction voltage and will cause an increase in the VCO output at pin 4. Note: 2.5 volts at D6 pin 9 equates to a centre frequency of 288kHz, as set by C1, R33 and R34. An increase in voltage at pin 9 will cause the RC charge rate to increase, with as subsequent increase in VCO frequency. A decease in the voltage at pin 9 will cause the VCO frequency to reduce. 4. This increases the ‘staircase pattern generator’ clock rate which then increases the inverter frequency along with the base frequency signal produced at D1 pin 27. 5. When the base frequency signal at D1 pin 27 has risen to match that of the [SYNC> signal, the phase comparator within the PLL ceases to detect any phase error and the correction voltage at pin 13 will stop changing. The VCO control voltage will thus remain constant and the inverter will be maintained at its current frequency and in sync with the bypass supply. Filter & C-phase reference generator

The filter sections convert the full-wave rectified stepped waveforms produced by the ‘multiplexers’ into sinusoidal AC reference signals suitable for connecting to the ‘volts error amplifier’ – (See Figure 5-27) . Two filter sections are used; one processes the A-phase AC reference signal and the other for the B-phase. Considering the A-phase circuit: the stepped waveform produced by the A-phase multiplexer (D4) is buffered by N1a and connected to D5 pin 13. This signal is also inverted by N1d and connected to D5 pin 12. D5 is an electronic switch controlled by the output from D1 pin 36 – which was previously described as a squarewave signal at the nominal base frequency, coinciding with the A-phase zero crossing points. If D5 is switched by this signal then the signal at its output pin 14 will be a stepped sine-wave comprising both halves of the signals present at its pins 12 and 13. This stepped waveform is then filtered by N2a which produces a smooth sinusoidal AC reference voltage [REF_A> and can be monitored at test point X8-1 as an 8V peak-to-peak sinewave. The B-phase circuit operates in an identical manner but displaced by 120° – i.e. [REF_B> lags [REF_A> by 120°. The C-phase signal, [REF_C>, is produced by N2d which differentially sums the other two phases with 0V. Theoretically, in a three phase system the instantaneous sum of all three voltages equals zero: therefore by subtracting the A and B phase signals from 0V the output from N2 pin 14 is equivalent to the C-phase AC reference signal, [REF_C> – i.e. A + B + C = 0 ∴ C = -(A + B).

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Tri-wave generator

The square-wave signal from D1 pin 40 is connected to an integrator circuit (N3b/c) via adjustable resistor R241. This resistor allows the peak value of the triwave signal to be calibrated and is adjusted to obtain a 4V peak-to-peak triangular waveform at the left hand side of R2 (i.e. ±2V peak). The tri-wave output from N3 pin 8, annotated [TRI>, is connected to the ‘PWM modulator’ (diagram sheet 3). 2.3.3

Volt s error ampli fier (circuit diagram sheet 3) Figure 5-30: Volts error amplifier & modulator block diagram

line volts adj [VINV_X>

Inv volts F/B

AC Reference volts [REF_X> [VI_X> Bypass volts F/B

D8


[RIF>

Current Feed/fwd

[IINV_X>

AC Control volts [TRI> Tri-wave

PWM Modulator

PWM waveform to output driver [MOD_X>

Each block shown is triplicated – one block per inverter phase

Note: As an almost identical circuit is used for each phase the following description refers to the ‘A’ phase only, with any differences between this and the ‘B’ and ‘C’ phase highlighted.

The purpose of the ‘volts error amplifier’ is to compare the inverter output voltage feedback signal with the AC reference voltage created by the ‘reference volts generator’ (See paragraph 2.3.2) and provide an appropriate AC control signal to the ‘PWM modulator’ – i.e. if the ‘volts error amplifier’ detects an error between the inverter output voltage feedback signal and the AC reference voltage it modifies the AC control voltage to change the PWM pattern in such a way as to restore a balanced condition; therefore effectively making the inverter voltage closely track the AC reference voltage. Inverter voltage feedback signal

The inverter A-phase output feedback voltage is sensed at the output side of the output transformer (i.e. at nominal system output volts), attenuated to approximately 1% on the High Voltage Interface Board and connected to the Inverter Logic Board at X4-18. The signal ( [VINV_A>) is amplified slightly as it passes

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through N5a to N5b, which acts as the ‘error amplifier’, and can be measured at test point X9-8 as an ac voltage in the range 4.5V to 5.0V (about 14V p-p) depending on the system working voltage. Calibration resistor R246 allows for individual A-N line voltage adjustment. Note: Calibration resistors are also included in the ‘B’ phase and ‘C’ phase feed back inverter volts feedback signal paths which enables those two phases to be individually balanced to the ‘A’ phase during board set-up. R224 adjusts the B phase and R245 the C phase. AC Reference voltage signal

The A-phase AC reference signal is connected to the error amplifier (N5b) via an electronic switch comprising part of multiplexer D8. This switch is controlled by a signal annotated [RIF> which is normally ‘low’, leaving the switch in the position shown on the circuit diagram. When [RIF> goes high the switch changes over and replaces the AC reference voltage input into the error amplifier (N5b) with a signal derived from the R-phase bypass voltage [VI_A> connected to X4-14 which makes the inverter voltage track the voltage on the bypass supply line. Bypass voltage sense signal [VI_A> is connected via an attenuator circuit on the High Voltage Interface Board

which is identical to that connected in the inverter output feedback signal path. The bypass voltage sense signal at test point X9-5 therefore has the same sensitivity as the inverter feedback voltage at X9-8 (about 14V p-p). When the inverter is first started, [RIF> goes high and energises D8 which then connects the bypass voltage sense signal [VI_A> to the ‘volts error amplifier’ reference input – thereby replacing the AC reference voltage as the voltage demand signal. The inverter voltage will thus rise to equal the bypass voltage. Once the inverter voltage has stabilised at the ‘bypass’ level the output contactor will close to put the inverter on-load. At this point [RIF> reverts to a logic low and D8 deenergises to select the AC reference voltage as the voltage demand signal. This is done to prevent arcing across the inverter output contactor when it closes and therefore increases its operating life and reliability. Volts error amplifier

N5b sums the AC reference voltage and the inverter voltage feedback signal and its output takes the form of a sinusoidal voltage representing the reference signal superimposed with a signal representing any detected error. This is then filtered by N5c and connected to N5d where it is processed in conjunction with an A phase current-derived signal. Note: A third input to N5b from N9a is used only when the module is operating as part of a multi-module parallel system and provides a means for implementing load sharing control. In a ‘single module’ installation this circuit is not used and the inputs to X4 pins 27-30 are left open circuit. Current feed-forward

N5d sums the volts error amplifier output from N5c with a signal proportional to the output current, annotated [IMN_A>. This is a ‘feed-forward’ signal which calls for an increased inverter voltage as the current increases and improves the overall inverter voltage regulation characteristics. The output from N5d is connected to the ‘PWM modulator’ in the form of the AC control voltage, as depicted in Figure 5-27, where it directly controls the generated PWM pattern.

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All three AC control signals are summed by N9d and its output is connected back to the feed-forward amplifier in all three phases. As, in a t hree phase system, the sum of all three phase voltage should equate to 0V, this provides a virtual neutral reference point for all three amplifiers which prevents the AC control signals drifting with respect to each other and also ensures that no harmful dc voltages are generated in the output transformer windings. Note: In a module fitted with a double-ended (12-pulse) inverter (optional configuration generally reserved for larger modules) the AC control voltage is connected to the Auxiliary Inverter Logic Board via X6-9 and buffer N10a. In a standard module connector X6 is not used. 2.3.4

PWM Modu lato r The A-phase PWM pattern is generated by N11, which is configured as a differential comparator whose inverting input is driven by the variable (sinusoidal) AC control voltage and non-inverting input by a fixed frequency (2.4kHz), fixed voltage (±2V) tri-wave signal generated by the ‘reference voltage generator’. N11 generates the PWM pattern by detecting when the fixed tri-wave voltage is cut by the AC control voltage as illustrated below. Figure 5-31: PWM Pattern production N11

Tri-wave (fixed)

PWM pattern

AC control voltage (variable)

Tri-wave (fixed)

AC control signal (low) 3 PWM pattern 1

AC control signal (high) Tri-wave (fixed) 1 PWM pattern 3

The upper waveform diagram depicts the condition where the AC control voltage is low with respect to the tri-wave (equal to about 25% of the tri-wave peak voltage) and illustrates that this results in a PWM pattern with a mark-to-space (m:s)

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ratio of approximately 3:1. The lower diagrams shows the situation when the AC control signal is increased to about 75% of the tri-wave peak voltage and illustrates the output m:s now equals 1:3. This shows that the m:s ratio of the output waveform can be varied by varying the AC control signal; and if this signal is varied in a sinusoidal manner then the output waveform w ill represent a sinusoidally modulated PWM pattern. This pattern is processed by the ‘drive pulse generator’ and applied to the inverter IGBT transistors such that for each individual inverter phase the ‘high’ IGBT is turned on when the PWM signal is high – and vice versa. Note: if a 12-pulse inverter is fitted (option on larger modules only) the three AC control signals and tri-wave signal [TRI> are connected to the Auxiliary Inverter Logic Board via the four sections of N10 (buffers) and connections X6 pins 9 to 12 – i.e. the Auxiliary board contains its own ‘PWM modulator’ and ‘drive pulse generator’ stages.

2.3.5

Current sensin g and Current lim it (circuit diagram sheet 4) Current sensing

The inverter current is sensed by Hall-effect CT’s fitted between the inverter and output transformer. In modules above 200 kVA a CT is fitted to each phase but only two CTs are used in modules at or below this rating, fitted to the S and T phases only. In the latter case the phase current is calculated from the other two (monitored) phases. The CTs’ sense signals are calibrated by jumpers on the High Voltage Interface Board which determines the overall burden resistance (See section 7 paragraph 2.3.24) and then connected to X4 pins 21 to 23 on the Inverter Logic Board via the UPS Logic Board. In the lower-rated modules, where only two CTs are fitted, the A-phase current is calculated by N15a which sums the B and C phase current sense signal (via jumpers X16-1 and X16-2) with 0V. As in a three-phase circuit the instantaneous sum of all three currents equals zero then the output from N15a pin 1 represents the A phase current – i.e. A + B + C = 0 ∴ C = -(A + B). In installations using three CTs, X16 jumpers 1 and 2 should be ‘open’ and jumper 3 must be ‘made’. This connects the A-phase signal directly to N15a in the same manner employed by the other two phases. As all three phases are identical in operation the following description refers to the A-phase only. N15 effectively buffers the current sense signal and the output on N15a pin 1 (test point X10-1 shows approximately 0.2V p-p signal when the inverter is on no-load) is in-phase with the output phase current. From N15a this signal is inverted and amplified by N15b whose output [IMN-A> is connected to the ‘current feed-forward’ circuit in the AC control voltage line – described earlier. Current limit

The output from N15a is also rectified by N15c/N15d (zero gain) whose output pin 14 provides a positive full-wave rectified signal representing the inverter A phase current which is then applied to a comparator circuit comprising N18. The comparator’s operating threshold is set by R248 which is connected across a 4.7V zener regulator and adjusted to present +0.6Vdc at N18 non-inverting input –

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available at test point X10-4. This represents 150% of the rated inverter load current, and if the current sense signal to N18 inverting input exceeds this level then the output from N18 pin 7 ( [BLK_A>) will switch to a logic low level and apply an inhibiting input to the ‘drive pulse generator’ (described below) which prevents it from turning on the A-phase inverter transistors. This effectively limits the inverter peak current to the set 150% threshold. Note that the inverter is not shut down during the above event; but the current limit action will take place during each pulse of the 2.4kHz PWM drive signal – i.e. sub-cycle operation. This effectively reduces the PWM pattern and therefore the inverter output voltage will fall to the level necessary to restrict the current to its 150% level. Taken to its extreme, if there is a short-circuit on the critical bus then the inverter PWM pulses will be reduced to a minimum and the inverter will deliver full (150%) current at very low voltage in an attempt to clear the short. 2.3.6

Drive pul se generator (circuit diagram sheet 5) This circuit, which comprises a complex series of gated latches within D11 together with driver transistors V42 to V47, performs signal conditioning on the PWM pulsetrains produced by the ‘PWM modulators’ to make them suitable drive signals for the inverter IGBT transistors. Note: these signals are connected to the IGBTs via the Inverter Driver Boards (one per phase) which provide further signal conditioning. D11 internal gates

Those gates within D11 concerned with the ‘drive pulse generator’ function com prise three independent channels controlled by the PWM modul ated signals [MOD_A>, [MOD_B>, [MOD_C>, in conjunction with [STRI>. Taking the A-phase circuit as an example; the drive control inputs to D11 are [MOD_A> and [STRI> and the outputs from D11 are taken from pin 36 (drive to the A-phase inverter low IGBT [PAL>) and 37 ( high IGBT [PAH>). [PAL> switches

high, turning on the ‘low’ IGBT via V42, when [MOD_A> is low and [STRI> goes low. This condition is latched until [MOD_A> is high and [STRI> goes high, whereupon [PAL> returns low, turning off the ‘low’ IGBT, and [PAH> goes high, turning on the ‘high IGBT via V43. There are two means by which the drive pulse logic can be inhibited within D11. The first occurs if an overload is detected, in which case the [BLK_A>, BLK_B>, [BLK_C> signals described earlier will inhibit the particular channel being overloaded – (See paragraph 2.3.5) . The second is by means of a general ‘stop/start logic’ block within D11 which handles signals from the UPS Logic Board and from the local ‘fault detection logic’ and provides a controlled stop/start function – (See paragraph 2.3.8) .

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2.3.7


Fault detection log ic (circuit diagram sheet 5) Circuits on the Inverter Logic Board monitor the following faults: • • • • •

Inverter current limit Inverter overload (from desaturation detector on driver interface boards) Ribbon cable discontinuity Inverter stack thermostat overtemperature Power supply monitor

Each of these facilities are described below Inverter current limit

The ‘inverter current limit’ circuit is shown on the diagram sheet 4 and described in detail in paragraph 2.3.5. This circuit provides three inputs to D11 annotated [BLK_A>, [BLK_B> and [BLK_C> which go low if an overload is detected on the associated phase. In the event of a phase current rising to the current limit level the following occurs within D11: 1. The drive signals to the affected phase(s) are inhibited, as described above. 2. A summary current limit signal (logic low) is produced at D11 pin 21 if any one of the three phase currents reach the current limit level. This is inverted to a high by D10b and connected to the UPS Logic Board via X4-32 as an inverter overload status alarm signal [OVL_INV>, where it is used for display purposes only (code 33). From D10b pin 10 the signal is also passed back through D11 pins 20 to 19 and illuminates H14 to provide an on-board indication that the inverter overload circuit is activate. Note that the signal to D10b is slugged by V23/R300/R237/C141 on removal of the overload to allow the inverter conditions time to stabilise before the overload status is reset. 3. The [BLK_A>, [BLK_B> and [BLK_C> signals are buffered within D11 and out put at pins 31, 32 and 33 respectively. These are passed to the Auxiliary Inverter Logic Board in a 12-pulse inverter installation via connector X6 pins 13, 14 and 15 (used in large module only). Inverter Vce(sat) (from desaturation detector on driver interface boards)

A circuit on the Inverter Driver Board (See paragraph 4.3.4) detects an inverter IGBT fault (short or open circuit) by sensing when t he particular device is desaturated during its ‘ON’ period. These boards thus provide six fault signals back to the Inverter Logic Board via pins 3/4 and 13/14 of connectors X1 (A-phase) X2 (B-phase) and X3 (C-phase) respectively. The fault signal applied to these inputs take the form of a logic low on fault, but this is inverted to a high by a section of D9 and diode-coupled to a single input at D11 pin 8 [DIS> which is therefore high if a desaturation condition is detected on any inverter IGBT and drives the Start/ stop logic within D11 to its stop mode (see below). Note: the Vce(sat) signals produced by the various sections of D9 illuminate LEDs H5 to H10 to positively identify the location of the faulty IGBT transistor. Ribbon cable discontinuity

A system of verifying that the ribbon cables connecting the Inverter Logic Board to the three Inverter Driver Interface Boards is implemented by the connections to X1 to X3 pins 5/8. Pins 5 and 8 of the respective connectors are linked together on the Inverter Driver Interface Boards and so present a short-circuit which pulls

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D11 pin 9 ([COI>) low if the cables are all correctly in place. However, if one of the cables are disconnected while the inverter is operating [COI> will rise to a logic high and drive the Start/stop logic within D11 to its stop mode (see below). Note: this signal is buffered within D11 and produces a logic high output at D11 pin 18 which illuminates H13 if a fault occurs. X12 provides a means of overriding this circuit for test purpose only when it is made 0-2 – this jumper should always be OPEN during normal operation. Inverter stack thermostat overtemperature

A facility exists in which thermostats fitted to the power inverter heatsinks can provide an overtemperature status signal to the UPS Logic Board. The thermostats provide a normally-closed circuit between X1-5 and X3-8 and produce a logic low signal at X4-40, which is connected to the UPS Logic Board. If any thermostat opens (at a temperature above 90°C) then this chain is broken and X440 is pulled high via R100 and V24. Where this option is not used (standard), a jumper should be fitted to X12 position 0-1 to override the overtemperature fault signal which would otherwise appear. Reposition this jumper to OPEN when the option is used. 2.3.8

Start/stop log ic This circuit is based on a multi-input logic gate within D11 which monitors the ‘fault detection logic’ circuits described above, together with several control inputs from the UPS Logic Board, and either enables or disables the ‘drive pulse generator’ outputs (also within D11) in response to t he input signals’ status. Start/stop logic circuit outputs

Three ‘start/stop’ status outputs are also produced by D11, as described below: •

D11 pin 7 goes high on stop and is the source of the [BLK> signal to the ‘reference voltage generator’ circuit. When the ‘stop/start logic’ is in its stop mode this signal reduces the ‘reference voltage generator’ output to zero and thus demands zero output voltage. • D11 pin 28 goes high on stop and sends a status signal to the UPS Logic Board via X4 pin 33 to request the micro to disable the inverter run signal. • D11 pin 34 goes high on stop and sends a status signal to the Auxiliary Inverter Logic Board (12-pulse inverter only); thus ensuring that where this option is used both the main and auxiliary boards are stopped and started by a common control signal. Start/stop logic circuit inputs

The ‘start/stop logic’ within D11 is driven by the following D11 inputs: 1. Inverter Vce(sat) error (detected by desaturation detector on Inverter Driver Interface Boards) – logic high to D11 pin 8 forces the stop mode (See paragraph 2.3.7). 2. Connector discontinuity (led H13 illuminated) – logic high to D11 pin 9 forces the stop mode (See paragraph 2.3.7) . 3. A system start/stop control input to D11 pin 13 from the UPS Logic Board, via X4-36, which is low on stop and high on start , provides the means of allowing the UPS Logic Board to shut down the inverter in response to certain system events – e.g. DC overvoltage, low battery, OFF selected from the Operator Panel, emergency shutdown, etc. This input also drives led H12 via

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D11 pin 17 (inverts the signal at pin 13) and illuminates the led when the signal is demanding the inverter to be turned OFF. 4. If a 12-pulse inverter is installed (option) the output from the ‘start/stop’ circuit on the Auxiliary Inverter Logic Board is connected to D11 pin 14 via X6-18 and is logic high on stop. This ensures that both main and auxiliary Inverter Logic Boards react to a common ‘Start/stop’ line (see also the output from D11 pin 34 described above). 5. A power supply monitor circuit based on N22 applies a logic high input to D11 pin 16, placing the ‘stop/start’ circuit in its stop mode if the 12V supply rail falls below 10Vdc. This circuit also holds off the inverter operation when the UPS is first powered up until the 12V rail rises above this level to allow the power supply time to stabilise before initiating the PWM drive signals. Led H11 illuminates when this circuit is demanding a stopped condition. 6. The transfer to inverter command [INV_L> generated on the UPS Logic Board is connected to D11 pin 12. This is clocked through D11 to enable the [RIF> signal. This re-references the inverter voltage to the bypass voltage just before the inverter is about to take over the load, which prevents any voltage drop appearing across the output contactor when it is instructed to close (See paragraph 2.3.3). The inverter voltage is referenced to the bypass voltage level for approximately 220ms before is it switches back to its normal reverence voltage: this more than adequately covers the output contactor closure time, which is approximately 50ms. Note that this function is disabled by the ‘mains fail’ signal [MNS_KO> to D11 pin 11 in the event of a mains failure; thus if the load is transferred to the inverter when there is no bypass to the UPS, then the inverter will remain referenced to its normal reference voltage at all times. 2.3.9

Power supp ly (circuit diagram sheet 5) This board receives its control power supply from the DC-DC Power supply Board only, via connector X5. Pins 3, 4 and 5 carry regulated +12V, 0V and -12V power rails which form the Inverter Logic Board’s main supply inputs; and pins 1 and 2 carry an isolated 36Vac supply which is used by the Inverter Driver Interface Boards and connected via connectors X1, X2 and X3, as shown. A 5V regulator, N21, provides a regulated +5V rail from the +12 supply. The ±12V rails are diode-coupled to the ±12V rails on the UPS Logic Board via V14 and V15, as shown on sheet 5 of the diagram. Thus in the event of mains failure (i.e. the AC-DC Power Supply is inactive) the DC-DC Supply will maintain the control power to all the electronic circuit boards.

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2.4


Summary Inform ation Table 5-4: Inverter Logic Board configuration jumpers Link Position

Jumper

open

Function Enable thermostat detector (Standard)

0-1 closed open

Override thermostat detector (Test only) Enable disconnected cable detector (Standard)

0-2 closed

Override disconnected cable detector (Test only)

closed

Voltage select override

0-3 X12 0-4

Manual inv adj R243

0-5

Frequency select override

0-6

Force Inv ON => ignore all blocks

0-7

Ignore Inv ‘On Load’ signal

0-8

X15

Testing only Open = standard 6 links-override control inputs from UPS logic board as shown on main circuit diagram

0-5

1200Hz

0-1

2400 Hz (Standard)

0-2

4800Hz

0-1 0-2

9600Hz

0-1 0-2

C-phase current monitor signal selection (where only 2 CTs are fitted to the inverter phases – standard to 7200 range)

0-3

C-phase current monitor signal selection (where 3 CTs are fitted to the inverter phases – used in larger modules)

PWM modulating frequency selection

X16

Table 5-5: Inverter Logic Board potentiometer adjustments Potentiometer

Function

R241

Amplitude of triangle wave adjustment

R242

Inverter voltage reference setting

R243

Manual inverter voltage adjustment (0 to 500V)

R244

Phase B to Neutral adjustment

R245

Phase C to Neutral adjustment

R246

Phase A to Neutral adjustment

R247

Phase displacement adjustment Inverter to Bypass

R248

150% Inverter Current Limit

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Table 5-6: Inverter Logic Board LED indications LED

Colour

Function

H1

Green

380V operation

H2

Green

400V operation

H3

Green

415V operation

H4

Amber

H5 to H10

Red

Transistor saturation, (R+, R– : S+, S– : T+, T–.)

H11

Red

PCB power supply failure

H12

Red

Inverter off from UPS Logic Board

H13

Red

Ribbon cable monitor block

H14

Red

Inverter in 150% current limit (Active)

Manual operation Range 0 - 500 Volts ( wise = minimum)

Clock-

Table 5-7: Inverter Logic Board test points Test Point X8 X8 - 1

Inverter ref. A

(8Vp-p)

X8 - 2

Inverter ref. B

(8Vp-p)

X8 - 3

Inverter ref. C

(8Vp-p)

X8 - 4

Inverter DC ref.

X8 - 5

Inverter pulse for φ displacement

X8 - 6

φ displacement error pulse

Test Poin t X9 X9 - 8

Inverter feedback A

X9 - 7

Inverter feedback B

X9 - 6

Inverter feedback C

X9 - 5

Bypass A

8V p-p

X9 - 4

Bypass B

8V p-p

X9 - 3

Bypass C

8V p-p

X9 - 2 X9 - 1

Not Used

Test Point X10 X10 - 1

Current φ A (0.2V p - p No Load)

X10 - 2

Current φ B (0.2V p - p No Load)

X10 - 3

Current φ C (0.2V p - p No Load)

X10 - 4

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0.6V Current limit

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Section 18: EP i.e.the larger

Chapter 3 - Inverter Logic Board (4530024 S)

Section 18:

3.1

Chapter overview This chapter contains a circuit description of the Inverter Logic Board 4530024S, which was used across the whole 7200 Series UPS model range prior to February ‘97 when it was superceeded by 4530025T – see chapter 2. This chapter should be read in conjunction with circuit diagram SE-4530024-S (5 pages). Signal annotations shown on the circuit diagrams are shown in italics in the following text – e.g. [BLK-INV>.

3.2 3.2.1

General descri pti on Circuit board functio ns The Inverter Logic Board board is responsible for providing the drive signals for the inverter IGBT transistors at the appropriate PWM (pulse width modulated) pattern to produce the required inverter output voltage and frequency. In so doing, the board monitors the following UPS parameters vi a the High Voltage Interface Board and UPS Logic Board: • • • •

Inverter voltage – closed loop voltage regulation Inverter current – IGBT protection Bypass voltage – for inverter synchronisation System control signals from the UPS Logic Board micro (Run/Stop, Voltage/frequency selection, Current limit selection) • Soft-start – 10 cycles to energise the output magnetics on start-up As part of its control function, the board detects several abnormal operating conditions and provides the UPS Logic Board control system with the following error status signals: • • • • 3.2.2

Inverter overload Inverter On/Off status Control power supply failure IGBT failure

Input/Outpu t con nectio ns The Inverter Logic Board has six connectors, described below: • • • • • •

X1 – Output drive signals to Inverter Driver Board 4519015-H (R-phase) X2 – Output drive signals to Inverter Driver Board 4519015-H (S-phase) X3 – Output drive signals to Inverter Driver Board 4519015-H (T-phase) X4 – Control signals to/from UPS Logic Board (See Table 18-8) X5 – Power supply inputs from DC-DC Power Supply Board X6 – To Auxiliary Inverter Logic Board (used in large inverters only)

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18-241

SECTION 5 - Inverter Operation & Control CHAPTER 3 - Invert er Logi c Board (4530024 S)


Table 18-8: connector X4 (to UPS Logic Board) pinout details PIN

I/O

1-4

I/O

0V power supply rail

5-8

I/O

+12V power supply rail

9 - 12

I/O

-12V power supply rail

13

I


14

I


15

I

[VI_A> Bypass A-ph volts sense from HVI Board – 8Vp-p

16

I

[VI_B> Bypass B-ph volts sense from HVI Board – 8Vp-p

17

I

[VI_C> Bypass C-ph volts sense from HVI Board – 8Vp-p

18

I

[VIN_A> Inverter A-ph volts sense from HVI Board – 8Vp-p

19

I

[VIN_B> Inverter B-ph volts sense from HVI Board – 8Vp-p

20

I

[VIN_C> Inverter C-ph volts sense from HVI Board – 8Vp-p

21

I

[IINV_A> Inverter A-phase current sense from HVI Board

22

I

[IINV_B> Inverter B-phase current sense from HVI Board

23

I

[IINV_C> Inverter C-phase current sense from HVI Board

24

I

[XINV_OI> Mains error – load transfer to inverter = 1

25

I

[DREF> Output voltage adjustment - used in parallel modules

26

I

[DREF0> Output voltage adjustment - used in parallel modules

27

I

[DV-A> Load sharing input for parallel modules only

28

I

[DV-B> Load sharing input for parallel modules only

29

I

[DV-C> Load sharing input for parallel modules only

30

I

[DV-0> Load sharing input for parallel modules only (common)

31

I

[INV_L> ‘Inverter on load’ commanded on UPS logic Board – Load-on-inverter = 1

32

O

[OVL_INV> Inverter overload status to UPSLB micro (OVL = 0)

33

O

[BLK_INV> Inverter On/Off status to UPSLB micro (Off = 1)

34

O

[BACK> Frequency sync signal fed back to UPSLB micro – pulse

35

I

[SYNC> Reference frequency produced by UPSLB micro – pulse

36

I

[ON_INV> Inverter On/Off control from UPSLB micro (Off = 0)

37

I

[INV_F> from UPSLB micro (Inv Freq - used in ref w/form gen) – 50Hz = 0 and 60Hz = 1

38

I

[INV_A> from UPSLB micro - used in output volts selection

39

I

[INV_B> from UPSLB micro - used in output volts selection

40

O

Thermostats output to UPSLB (optional)

18-242

Function

s5-c2OLD.f m - Issu e 2 Dated 21/08/97


3.2.3

SECTION 5 - Inverter Operation & Control CHAPTER 3 - Inverter Lo gic B oard (4530024 S)

Blo ck Diagram Figure 18-32 shows the Inverter Logic Board at its most basic functional block diagram level – the basic function of each of the blocks shown is described below, with a more detailed, component level description provided in the remainder of the chapter. Figure 18-32: Inverter Logic Board basic block diagram Inverter I sense (x3)

Inverter Current Sense

Bypass Freq Output Volts Select

Bi-directional Control (UPSLB) (UPSLB) DC-DC Supply

PWM Modulator


Frequency

Reference Control Voltage Tri-wave (x1) Generator Start/ Stop Logic Power Supply

Drive Pulse Generator

Inverter IGBT Drive Pulses

l ) o r 3 x t n ( o s C e g a C t l A o v

AC Reference voltages (x3)

Bypass Volts F/B (x3)

Overload (x3)

PWM (x3)

d r a w r o f d e e F

Inverter Volts F/B (x3) (actual)

Current Limit

e p n i o l t l S / o r t r t n a t o S c

Fault Detection Logic ±12V ±5V

Reference voltage generator

The ‘reference voltage generator’ produces three AC reference sine waves at 120° with respect to each other which act as voltage demand signals to the ‘volts error amplifier’. These signals dictate the amplitude, frequency and waveshape of the eventual inverter output voltage. Volts error amplifier

This block compares the AC reference signals with voltage feedback signals derived from the inverter output, and produces error signals proportional to any detected amplitude difference. Three individual error amplifiers are contained in this block, one for each phase, which means that each inverter phase is individually controlled. Note that the outputs from this block are annotated “ AC control” signals, as it is these signals that ultimately determine the adopted PWM pattern which in turn directly determines the inverter output three phase voltage.


18-243



Current limit

AC signals proportional to the inverter output current are processed by the ‘inverter current sense’ circuit and fed to the ‘current limit’ block where they apply a current limit function to the ‘drive pulse generator’ circuit if the current reaches 150%. Three independent circuits are contained in this block, one per phase, so each output phase is individually controlled. Modulator

This circuit modulates the AC control signals with a 2.4kHz tri-wave signal, produced by the ‘reference volts generator’, and generates three PWM waveforms. Once again three independent circuits are used, one per phase. Drive pulse generator

The ‘drive pulse generator’ converts the PWM signals into suitable IGBT base drive signals. This block contains interlocking logic to prevent the simultaneous triggering of both IGBTs in an inverter phase, a high frequency modulator, overload protection and general start/stop control of the output drive waveforms. Start/stop logic and Fault detection

Numerous fault detection circuits are contained on the board. These control the internal start/stop control lines to the ‘reference volts generator’ and ‘drive pulse generator’, and also provide status signalling to the UPS Logic Board micro for use by the system control logic. Signals from the UPS Logic Board to this (Inverter Logic) board also effect start/stop control in accordance with the system’s control logic demands. Power supply

The Inverter Logic Board is powered from the DC-DC Power Supply Board, which is live whenever the power rectifier is operational or the batteries are connected to the busbar via the battery circuit breaker. This power source provides ±12V d.c. power rails which are then diode blocked to the second supply source (from the AC-DC Power Supply board) the UPS Logic Board – hence the board will be powered only from the DC-DC Power Supply but once the mains fails (i.e. the AC-DC Power Supply is off) the DC-DC Power Supply will keep all the circuit boards energised. On-board 5V regulators, fed from the ±12V rails, provide stabilised ±5V power rails for those devices that require it.

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3.3 3.3.1


Detailed cir cui t descrip tio n Introduction The Inverter Logic Board circuit diagram (SE-4530024-S) comprises 5 sheets. With reference to the block diagram in Figure 18-32, the drawings can broadly be described as follows: • • •

• •

3.3.2

Sheet 1 contains a ‘signal map’ showing the interconnection of the signals passing between the other four sheets. Sheet 2 contains the reference voltage generator circuit Sheet 3 contains the: – ‘volts error amplifier’ circuit – ‘current limit’ circuit – ‘PWM modulator’ circuit Sheet 4 contains the ‘current sense’ circuit and current limit detector Sheet 5 contains the: – ‘drive pulse generator’ circuit – ‘start/stop logic’ circuit – ‘fault detection logic’ circuit

Reference vol tage generat or (circuit diagram sheet 2) Figure 18-33: Reference voltage generator block diagram

volts adj (R242)

[INV_A> [INV_B>

Set Volts V-peak

[BLK> Stepped waveform

Resistor Ladder

[INV_F> [S_TRI> [FRFB>

Staircase Pattern Generator

[ISYNC>

Freq-reference


Phase Locked Loop

Multiplexer

Filter

Multiplexer

Filter

C Phase Reference Generator Tri wave Generator

AC Reference Voltage

[REF_A>

[REF_B>

[REF_C>

[TRI>

18-245



This circuit is responsible for producing three sinusoidal voltages, spaced at 120° with respect to each other, which are then connected to the ‘volts error amplifier’ in the form of AC reference voltages. The voltages produced by this circuit can thus be considered as ‘voltage demand’ signals, and represent the amplitude, frequency and wave-shape desired at the inverter output voltage. Multiplexer operation

The ‘reference voltage generator’ circuit’s operation is centred around D3 and D4. These are 8-channel multiplexers whose 8 data lines are connected to various points along a resistor ladder network (R1-R12), and whose 3 data-select lines are clocked by the ‘staircase pattern generator’, ASIC D1. Each multiplexer output (pin 3) is thus connected to one of 8 discrete voltage levels tapped along the resistor ladder depending on the state of the data-select inputs. In practice, the logic sequence of the signals to the three data-select inputs, from D1, are such that a stepped waveform is produced at the multiplexers’ outputs which takes the broad form of a full-wave rectified a.c. voltage – (See Figure 1833).

Voltage control. As the voltages at each stage of the stepped waveforms equal the voltages present along the resistor chain, the stepped waveform peak voltage is determined by the voltage at the top of the chain – i.e. the voltage at buffer N2c pin 8. This is controlled by the circuit block annotated ‘set volts’ in Figure 18-33 and described in detail below. Waveshape control. The AC reference voltage waveshape is determined solely by the sequential logic within D1 and cannot be adjusted. Frequency control. The AC reference voltage frequency is determined by the clock frequency applied to the ‘staircase pattern generator’ (D1 pin 43), as this controls the rate at which the multiplexers step through their sequence. This is controlled by a phase locked loop which is normally synchronised to the bypass supply frequency – described later (See Figure 18-34). Set volts & Resistor ladder

As described above, the ‘set volts’ circuit (See Figure 18-33) provides a controlled voltage at the top of the resistor ladder which thereby determines the peak value of the AC reference voltages – and thus also the inverter output voltage. It is possible to select one of three output working voltages: 380V, 400V and 415V. This is achieved by two signals from the UPS Logic Board annotated [INV_A> and [INV_B> which are connected to the data-select inputs of D7, which is a dual 4-channel multiplexer. The inputs to the ‘X’ channel (‘1X’ to ‘4X’) of D7 are connected to regulated DC voltages which represent the various UPS working voltages. These are selected by the [INV_A> and [INV_B> to appear at connected to the ‘X’ output as follows: Table 18-9: Working voltage selection (D7)

18-246

[INV_A>

[INV_B>

Channel

Volts

0

0

X1

380V

0

1

X2

400V

1

0

X3

415V

1

1

X4

Manual Set




The voltages applied to ‘1X’, ‘2X’ and ‘3X’ are produced by a resistor network connected across a variable regulated dc power rail which is itself connected between the 0V and -12V supply rails; the voltages are therefore of a negative polarity. In practice, R242 is adjusted to obtain approximately -4V across N4; this voltage is then divided by R54 - R57. The response of the inverter voltage control loop is such that the signal at D7 ‘X’ output has a sensitivity of approximately 92Vac/V – e.g. a voltage of approximately -4.5V is required to produce an inverter output voltage of 415Vac. R242 thus provides the means of calibrating the output voltage when the UPS is operating. Note: R242 adjusts the voltage of all three phases. Further resistors are provided which individually adjust the B and C phase line voltages and can be used to balance the output line voltages if necessary – described later (see page 18-251). The ‘manual’ mode is elected by the UPS Logic Board in response to the operator input and is designed to be used in a ‘test’ environment. When this mode is selected the output voltage can be varied by means of R243 (0-600Vac), which is connected between the -5V rail and ground, and whose wiper voltage is connected to D7 ‘X4’. The selected voltage at D7 output (pin 13) is inverted to a positive voltage by N3b and buffered by N2c before it is applied to the top of the resistor ladder network (this voltage can be monitored at test point X8-4 where it has a sensitivity of ap proximately 0.01Vdc/Vac output. e.g. a level of 4.1Vdc is equivalent to 400Vac on the inverter output). An output from the ‘start/stop logic’, annotated [BLK> on the circuit diagram, reduces N3b voltage to zero when the inverter is being commanded OFF . This reduces the voltage at the top of the resistor ladder to zero which thus results in a “zero voltage” demand to the inverter voltage regulation circuit. [BLK> goes

high when in the stop/start logic is in its ‘ STOP’ mode which clamps the input to N2 pin 10 to 0V via V41. When this signal switches to its ‘ START’ mode (low), V41 turns off but the voltage rise at N2 pin 10 is slugged by R50/C14 to restrict the rate of increase of the inverter demand voltage. This soft-start action takes approximately 10 cycles to complete and is designed to slowly energise the output magnetics and thus reduce the inverter start-up current. Note: the inputs to the ‘set volts’ circuit from X4 pins 25 / 26 and amplifier N3a are used in a multi-module parallel-operating system only and play no part in a single module installation. Staircase pattern generator

The ‘staircase pattern generator’ is based on D1, which contains a complex series of synchronous logic gates and timers and produces two sets of signals which are connected to the multiplexer data-select inputs – e.g. output A1-C1 are connected to multiplexer D4 and outputs A2-C2 to multiplexer D3. The sequence of these outputs, which is determined solely by D1’s internal logic, produce stepped signals at the multiplexer outputs which resemble a full-wave rectified waveform. Two frequency-related signals are applied to D1. An input to D1 pin 44, annotated [INV-F>, controls one of D1’s internal dividers and sets the inverter nominal base frequency. This signal, which is logic high for 60Hz operation and low for 50Hz, is produced on the UPS Logic Board in response to inputs from the Operator Control Panel. The input to D1 pin 43 is a 288kHz clock signal, produced by a phase-locked-loop (PLL) circuit, which controls D1’s internal operation. Note: The PLL determines the inverter free running frequency and is normally synchronised to the bypass supply (See Figure 18-34) .


18-247



In addition to the multiplexer data-select signals described above there are several other frequency-related outputs from D1. •

The outputs from pins 31 (D2) and 36 (D1) are square-waves at the nominal base frequency which determine the zero-crossover points of the inverter output and S phases respectively. These are connected to the filter section – described later (see page 18-250) . • The output from pin 40 is a 2.4kHz square-wave which is converted to a tri-wave by the ‘tri-wave generator, described below, for further use by the ‘PWM Modulator’ (See paragraph 3.3.4). The frequency of this signal is determined by the logic levels at pin 1 (S2) and pin 2 (S3), as selected by X-15 links 1 and 2 – detailed on sheet 1 of the circuit diagram. Table 18-10:

18-248

X15(0-1) S2

X15(0-2) S3

Frequency

Usage

Open (0)

Open (0)

1.2kHz

N/A

Closed (1)

Open (0)

2.4kHz

All models

Open (0)

Closed (1)

4.8kHz

N/A

Closed (1)

Closed (1)

9.6kHz

N/A

•

The output from D1 pin 28 (ST2), annotated [S_TRI>, is connected to the ‘drive pulse generator’ block where it modulates the ultimate output drive waveform (See paragraph 3.3.6) . Once again the frequency of this signal is controlled by links on X15. Normally, it is a 2.4kHz square-wave.

•

The output from D1 pin 27 (D3), annotated [FRFB> (test point X8-5), is connected to the UPS Logic Board via a variable resistor (R247) – shown on sheet 5 of the diagram (See Figure 18-34). This signal is a square-wave at the nominal base frequency coinciding with the zero-crossover point of the A-phase AC reference voltage. On the UPS Logic Board a phase-com parator function within the microcontroller compares this signal with a similar signal derived from the bypass supply R-phase and is thus able to detect an out-of-phase conditions. R247, located in the [FRFB> line, allows any residual phase displacement between the inverter and bypass R-phase waveforms to be nulled once the two sync signals are phase-locked.

•

The output from D1 pin 26 (D4) is connected to one of the phase locked loop (PLL) phase comparators’ inputs. The square-wave signal at this point is at the nominal base frequency and produced by dividing down the 288kHz clock signal at pin 13. Due to the phase locked loop action (described below) this signal is aligned with the A-phase inverter zerocrossover point.




Figure 18-34: Frequency synchronisation control X2 D42

62

15

D53

5

F-IN

Bypass supply R-phase voltage sensing

18

F-INM

X4

X3 63

4

16

BACK

BACKM

FRFB

34

R247

D17 R E L L O ) 2 R T T N R O O C P ( O R C I M

34

phase align

15

INV-F

37

37

INV-F

44

50 /60 Hz (Selected from Operator Panel)

DATA BUS

D1 27 26

Frequency Divider Staircase Generator 43

z H 0 6 / 0 5

K288kHz L C(nominal)

4

D59

64

5

SYNCM Pulses proportional to phase error between Inverter & Bypass mains

Phase Locked Loop 15

SYNC

Master Freq reference for Inverter Osc

14

35

UPS Logic Board

35

SYNC Phase error signal

9 VCO

Phase Comparator

13

n o i t c e r r o C F

D6 3

Inverter Logi c Board

Phase locked loop (PLL)

A PLL (D6) provides the clock signal for the ‘staircase pattern generator’ and thereby has direct control over the inverter output frequency. This is a standard type 4046 i.c. which contains two phase comparators (only one of which is used) and a voltage controlled oscillator (VCO). One of the phase comparator’s inputs (D6 pin 14) is driven by a square-wave frequency reference signal, annotated [SYNC>, which is synchronised to the bypass supply and produced on the UPS Logic Board; the other input is driven by a 50/60Hz output from the ‘staircase pattern generator’ (D1 pin 26) which is described above. If these two signals are out of phase the phase comparator output (D6 pin 13) will either switch high or low (depending on the phase relationship) and apply an error correction signal to the VCO’s control input (D6 pin 9) – i.e. the VCO frequency is effectively made to track the frequency reference signal. For example – if the bypass frequency rises slightly, the following actions will take place: 1. The sync control function on the UPS Logic Board will increase the [SYNC> signal frequency by an appropriate amount. 2. When the PLL compares the [SYNC> signal with the base frequency signal from the ‘staircase pattern generator’ it will detect that the [SYNC> signal is of a slightly higher frequency and the output from D6 pin 13 will exhibit logic high pulses equal to the periods of phase difference.


18-249



3. The pulses at D6 pin 13 are filtered and applied to the VCO control input at D6 pin 9 in the form of a dc correction voltage and will cause an increase in the VCO output at pin 4. 4. This increases the ‘staircase pattern generator’ clock rate which then increases the inverter frequency along with the base frequency signal produced at D1 pin 26. 5. When the base frequency signal at D1 pin 26 has risen to match that of the [SYNC> signal, the phase comparator within the PLL ceases to detect any phase error and the correction voltage at pin 13 will stop changing. The VCO control voltage will thus remain constant and the inverter will be maintained at its current frequency and in sync with the bypass supply. Filter & C-phase reference generator

The filter sections convert the full-wave rectified stepped waveforms produced by the ‘multiplexers’ into sinusoidal AC reference signals suitable for connecting to the ‘volts error amplifier’ – (See Figure 18-32). Two filter sections are used; one processes the A-phase AC reference signal and the other for the B-phase. Considering the A-phase circuit: the stepped waveform produced by the A-phase multiplexer (D4) is buffered by N1a and connected to D5 pin 13. This signal is also inverted by N1d and connected to D5 pin 12. D5 is an electronic switch controlled by the output from D1 pin 36 – which was previously described as a squarewave signal at the nominal base frequency, coinciding with the A-phase zero crossing points. If D5 is switched by this signal then the signal at its output pin 14 will be a stepped sine-wave comprising both halves of the signals present at its pins 12 and 13. This stepped waveform is then filtered by N2a which produces a smooth sinusoidal AC reference voltage [REF_A> and can be monitored at test point X8-1 as an 8V peak-to-peak sinewave. The B-phase circuit operates in an identical manner but displaced by 120° – i.e. [REF_B> lags [REF_A> by 120°. The C-phase signal, [REF_C>, is produced by N2d which differentially sums the other two phases with 0V. Theoretically, in a three phase system the instantaneous sum of all three voltages equals zero: therefore by subtracting the and B phase signals from 0V the output from N2 pin 14 is equivalent to the C-phase AC reference signal, [REF_C> – i.e. A + B + C = 0 ∴ C = -(A + B). Tri-wave generator

The square-wave signal from D1 pin 40 is connected to an integrator circuit (N3b/c) via adjustable resistor R241. This resistor allows the peak value of the triwave signal to be calibrated and is adjusted to obtain a 4V peak-to-peak triangular waveform at the left hand side of R2 (i.e. ±2V peak). The tri-wave output from N3 pin 8, annotated [TRI>, is connected to the ‘PWM modulator’ (diagram sheet 3).

18-250



3.3.3


Volt s error ampli fier (circuit diagram sheet 3) Figure 18-35: Volts error amplifier & modulator block diagram

line volts adj [VINV_X>

Inv volts F/B

AC Reference volts [REF_X> [VI_X> Bypass volts F/B

D8


[RIF>

Current Feed/fwd

[IINV_X>

AC Control volts [TRI> Tri-wave

PWM Modulator

PWM waveform to output driver [MOD_X>

Each block shown is triplicated – one block per inverter phase

Note: As an almost identical circuit is used for each phase the following description refers to the ‘A’ phase only, with any differences between this and the ‘B’ and ‘C’ phase highlighted.

The purpose of the ‘volts error amplifier’ is to compare the inverter output voltage feedback signal with the AC reference voltage created by the ‘reference volts generator’ (See paragraph 3.3.2) and provide an appropriate AC control signal to the ‘PWM modulator’ – i.e. if the ‘volts error amplifier’ detects an error between the inverter output voltage feedback signal and the AC reference voltage it modifies the AC control voltage to change the PWM pattern in such a way as to restore a balanced condition; therefore effectively making the inverter voltage closely track the AC reference voltage. Inverter voltage feedback signal

The inverter A-phase output feedback voltage is sensed at the output side of the output transformer (i.e. at nominal system output volts), attenuated to approximately 1% on the High Voltage Interface Board and connected to the Inverter Logic Board at X4-18. The signal ( [VINV_R>) is amplified slightly as it passes through N5a to N5b, which acts as the ‘error amplifier’, and can be measured at test point X9-1 as an ac voltage in the range 4.5V to 5.0V (about 14V p-p) depending on the system working voltage. Note: Calibration resistors are included in the ‘B’ phase and ‘C’ phase feedback inverter volts feedback signal paths which enables those two phases to be individually balanced to the ‘A’ phase during board set-up. R224 adjusts the B phase and R245 the C phase.


18-251



AC Reference voltage signal

The A-phase AC reference signal is connected to the error amplifier (N5b) via an electronic switch comprising part of multiplexer D8. This switch is controlled by a signal annotated [RIF> which is normally ‘low’, leaving the switch in the position shown on the circuit diagram. When [RIF> goes high the switch changes over and replaces the AC reference voltage input into the error amplifier (N5b) with a signal derived from the R-phase bypass voltage [VI_A> connected to X4-14 which makes the inverter voltage track the voltage on the bypass supply line. Bypass voltage sense signal [VI_A> is connected via an attenuator circuit on the High Voltage Interface Board

which is identical to that connected in the inverter output feedback signal path. The bypass voltage sense signal at test point X9-4 therefore has the same sensitivity as the inverter feedback voltage at X9-1 (about 14V p-p). When the inverter is first started, [RIF> goes high and energises D8 which then connects the bypass voltage sense signal [VI_A> to the ‘volts error amplifier’ reference input – thereby replacing the AC reference voltage as the voltage demand signal. The inverter voltage will thus rise to equal the bypass voltage. Once the inverter voltage has stabilised at the ‘bypass’ level the output contactor will close to put the inverter on-load. At this point [RIF> reverts to a logic low and D8 deenergises to select the AC reference voltage as the voltage demand signal. This is done to prevent arcing across the inverter output contactor when it closes and therefore increases its operating life and reliability. Volts error amplifier

N5b sums the AC reference voltage and the inverter voltage feedback signal and its output takes the form of a sinusoidal voltage representing the reference signal superimposed with a signal representing any detected error. This is then filtered by N5c and connected to N5d where it is processed in conjunction with an A phase current-derived signal. Note: A third input to N5b from N9a is used only when the module is operating as part of a multi-module parallel system and provides a means for implementing load sharing control. In a ‘single module’ installation this circuit is not used and the inputs to X4 pins 27-30 are left open circuit. Current feed-forward

N5d sums the volts error amplifier output from N5c with a signal proportional to the output current, annotated [INV_A>. This is a ‘feed-forward’ signal which calls for an increased inverter voltage as the current increases and improves the overall inverter voltage regulation characteristics. The output from N5d is connected to the ‘PWM modulator’ in the form of the AC control voltage, as depicted in Figure 18-32, where it directly controls the generated PWM pattern. All three AC control signals are summed by N9d and its output is connected back to the feed-forward amplifier in all three phases. As, in a t hree phase system, the sum of all three phase voltage should equate to 0V, this provides a virtual neutral reference point for all three amplifiers which prevents the AC control signals drifting with respect to each other and also ensures that no harmful dc voltages are generated in the output transformer windings. Note: In a module fitted with a double-ended (12-pulse) inverter (optional configuration generally reserved for larger modules) the AC control voltage is connected to the Auxiliary Inverter Logic Board via X6-9 and buffer N10a. In a standard module connector X6 is not used.

18-252



3.3.4


PWM Modu lato r The A-phase PWM pattern is generated by N11, which is configured as a differential comparator whose inverting input is driven by the variable (sinusoidal) AC control voltage and non-inverting input by a fixed frequency (2.4kHz), fixed voltage (±2V) tri-wave signal generated by the ‘reference voltage generator’. N11 generates the PWM pattern by detecting when the fixed tri-wave voltage is cut by the AC control voltage as illustrated below. Figure 18-36: PWM Pattern production N11

Tri-wave (fixed)

PWM pattern

AC control voltage (variable)

Tri-wave (fixed)

AC control signal (low) 3 PWM pattern 1

AC control signal (high) Tri-wave (fixed) 1 PWM pattern 3

The upper waveform diagram depicts the condition where the AC control voltage is low with respect to the tri-wave (equal to about 25% of the tri-wave peak voltage) and illustrates that this results in a PWM pattern with a mark-to-space (m:s) ratio of approximately 3:1. The lower diagrams shows the situation when the AC control signal is increased to about 75% of the tri-wave peak voltage and illustrates the output m:s now equals 1:3. This shows that the m:s ratio of the output waveform can be varied by varying the AC control signal; and if this signal is varied in a sinusoidal manner then the output waveform w ill represent a sinusoidally modulated PWM pattern. This pattern is processed by the ‘drive pulse generator’ and applied to the inverter IGBT transistors such that for each individual inverter phase the ‘high’ IGBT is turned on when the PWM signal is high – and vice versa.


18-253



Note: if a 12-pulse inverter is fitted (option on larger modules only) the three AC control signals and tri-wave signal [TRI> are connected to the Auxiliary Inverter Logic Board via the four sections of N10 (buffers) and connections X6 pins 9 to 12 – i.e. the Auxiliary board contains its own ‘PWM modulator’ and ‘drive pulse generator’ stages.

3.3.5

Current sensin g and Current lim it (circuit diagram sheet 4) Current sensing

The inverter current is sensed by Hall-effect CT’s fitted between the inverter and output transformer. In modules above 60 kVA a CT is fitted to each phase but only two CTs are used in modules at or below this rating, fitted to the S and T phases only. In the latter case the phase current is calculated from the other two (monitored) phases. The CTs’ sense signals are calibrated by jumpers on the High Voltage Interface Board which determines the overall burden resistance (See section 7 paragraph 2.3.24) and then connected to X4 pins 21 to 23 on the Inverter Logic Board via the UPS Logic Board. In the lower-rated modules, where only two CTs are fitted, the A-phase current is calculated by N15a which sums the B and C phase current sense signal (via jumpers X16-1 and X16-2) with 0V. As in a three-phase circuit the instantaneous sum of all three currents equals zero then the output from N15a pin 1 represents the A phase current – i.e. A + B + C = 0 ∴ C = -(A + B). In installations using three CTs, X16 jumpers 1 and 2 should be ‘open’ and jumper 3 must be ‘made’. This connects the A-phase signal directly to N15a in the same manner employed by the other two phases. As all three phases are identical in operation the following description refers to the A-phase only. N15 effectively buffers the current sense signal and the output on N15a pin 1 (test point X10-1 shows approximately 0.2V p-p signal when the inverter is on no-load) is in-phase with the output phase current. From N15a this signal is inverted and amplified by N15b whose output [IINV-A> is connected to the ‘current feed-forward’ circuit in the AC control voltage line – described earlier. Current limit

The output from N15a is also rectified by N15c/N15d (zero gain) whose output pin 14 provides a positive full-wave rectified signal representing the inverter A phase current which is then applied to a comparator circuit comprising N18. The comparator’s operating threshold is set by R246 which is connected across a 4.7V zener regulator and adjusted to present +0.6Vdc at N18 non-inverting input – available at test point X10-4. This represents 150% of the rated inverter load current, and if the current sense signal to N18 inverting input exceeds this level then the output from N18 pin 7 ( [BLK_A>) will switch to a logic low level and apply an inhibiting input to the ‘drive pulse generator’ (described below) which prevents it from turning on the A-phase inverter transistors. This effectively limits the inverter peak current to the set 150% threshold. Note that the inverter is not shut down during the above event; but the current limit action will take place during each pulse of the 2.4kHz PWM drive signal – i.e. sub-cycle operation. This effectively reduces the PWM pattern and therefore the inverter output voltage will fall to the level necessary to restrict the current to

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its 150% level. Taken to its extreme, if there is a short-circuit on the critical bus then the inverter PWM pulses will be reduced to a minimum and the inverter will deliver full (150%) current at very low voltage in an attempt to clear the short. 3.3.6

Drive pul se generator (circuit diagram sheet 5) This circuit, which comprises a complex series of gated latches within D11 together with driver transistors V42 to V47, performs signal conditioning on the PWM pulsetrains produced by the ‘PWM modulators’ to make them suitable drive signals for the inverter IGBT transistors. Note: these signals are connected to the IGBTs via the Inverter Driver Boards (one per phase) which provide further signal conditioning. D11 internal gates

Those gates within D11 concerned with the ‘drive pulse generator’ function com prise three independent channels controlled by the PWM modul ated signals [MOD_A>, [MOD_B>, [MOD_C>, in conjunction with [STRI>. Taking the A-phase circuit as an example; the drive control inputs to D11 are [MOD_A> and [STRI> and the outputs from D11 are taken from pin 36 (drive to the A-phase inverter low IGBT [PAL>) and 37 ( high IGBT [PAH>). [PAL> switches

high, turning on the ‘low’ IGBT via V42, when [MOD_A> is low and [STRI> goes low. This condition is latched until [MOD_A> is high and [STRI> goes high, whereupon [PAL> returns low, turning off the “ ‘low’ IGBT, and [PAH> goes high, turning on the “high” IGBT via V43.


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The other two inverter phases are controlled in an identical manner with their respective drive signals shown annotated [MOD_B>, [PBL>, [PBH> for the B-phase and [MOD_C>, [PCL>, [PCH> for the C-phase. Note: [STRI> is common to all three phases. There are two means by which the drive pulse logic can be inhibited within D11. The first occurs if an overload is detected, in which case the [BLK_A>, BLK_B>, [BLK_C> signals described earlier will inhibit the particular channel being overloaded – (See paragraph 3.3.5) . The second is by means of a general ‘stop/start logic’ block within D11 which handles signals from the UPS Logic Board and from the local ‘fault detection logic’ and provides a controlled stop/start function – (See paragraph 3.3.8) .

3.3.7

Fault detection log ic (circuit diagram sheet 5) Circuits on the Inverter Logic Board monitor the following faults: • • • • •

Inverter current limit Inverter overload (from desaturation detector on driver interface boards) Ribbon cable discontinuity Inverter stack thermostat overtemperature Power supply monitor

Each of these facilities are described below Inverter current limit

The ‘inverter current limit’ circuit is shown on the diagram sheet 4 and described in detail in paragraph 3.3.5. This circuit provides three inputs to D11 annotated [BLK_A>, [BLK_B> and [BLK_C> which go low if an overload is detected on the associated phase. In the event of a phase current rising to the current limit level the following occurs within D11: 1. The drive signals to the affected phase(s) are inhibited, as described above. 2. A summary current limit signal (logic low) is produced at D11 pin 21 if any one of the three phase currents reach the current limit level. This is inverted to a high by D10b and connected to the UPS Logic Board via X4-32 as an inverter overload status alarm signal [OVL_INV>, where it is used for display purposes only (code 33). From D10b pin 10 the signal is also passed back through D11 pins 20 to 19 and illuminates H14 to provide an on-board indication that the inverter overload circuit is activate. Note that the signal to D10b is slugged by V23/R300/R237/C141 on removal of the overload to allow the inverter conditions time to stabilise before the overload status is reset. 3. The [BLK_A>, [BLK_B> and [BLK_C> signals are buffered within D11 and out put at pins 31, 32 and 33 respectively. These are passed to the Auxiliary Inverter Logic Board in a 12-pulse inverter installation via connector X6 pins 13, 14 and 15 (used in large module only). Inverter Vce(sat) (from desaturation detector on driver interface boards)

A circuit on the Inverter Driver Board (See paragraph 4.3.4) detects an inverter IGBT fault (short or open circuit) by sensing when t he particular device is desaturated during its ‘ON’ period. These boards thus provide six fault signals back to the Inverter Logic Board via pins 3/4 and 13/14 of connectors X1 (A-phase) X2

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(B-phase) and X3 (C-phase) respectively. The fault signal applied to these inputs take the form of a logic low on fault, but this is inverted to a high by a section of D9 and diode-coupled to a single input at D11 pin 8 [DIS> which is therefore high if a desaturation condition is detected on any inverter IGBT and drives the Start/ stop logic within D11 to its stop mode (see below). Note: the Vce(sat) signals produced by the various sections of D9 illuminate LEDs H5 to H10 to positively identify the location of the faulty IGBT transistor. Ribbon cable discontinuity

A system of verifying that the ribbon cables connecting the Inverter Logic Board to the three Inverter Driver Interface Boards is implemented by the connections to X1 to X3 pins 5/8. Pins 5 and 8 of the respective connectors are linked together on the Inverter Driver Interface Boards and so present a short-circuit which pulls D11 pin 9 ([COI>) low if the cables are all correctly in place. However, if one of the cables are disconnected while the inverter is operating [COI> will rise to a logic high and drive the Start/stop logic within D11 to its stop mode (see below). Note: this signal is buffered within D11 and produces a logic high output at D11 pin 18 which illuminates H13 if a fault occurs. X12 provides a means of overriding this circuit for test purpose only when it is made 2-3 – this jumper should always be position 1-2 during normal operation. Inverter stack thermostat overtemperature

A facility exists in which thermostats fitted to the power inverter heatsinks can provide an overtemperature status signal to the UPS Logic Board. The thermostats provide a normally-closed circuit between X1-5 and X3-8 and produce a logic low signal at X4-40, which is connected to the UPS Logic Board. If any thermostat opens (at a temperature above 90°C) then this chain is broken and X440 is pulled high via R100 and V24. Where this option is not used, a jumper should be fitted to X13 position 2-3 to override the overtemperature fault signal which would otherwise appear. Reposition this jumper to 1-2 when the option is used. 3.3.8

Start/stop log ic This circuit is based on a multi-input logic gate within D11 which monitors the ‘fault detection logic’ circuits described above, together with several control inputs from the UPS Logic Board, and either enables or disables the ‘drive pulse generator’ outputs (also within D11) in response to t he input signals’ status. Start/stop logic circuit outputs

Three ‘start/stop’ status outputs are also produced by D11, as described below: •

D11 pin 7 goes high on stop and is the source of the [BLK> signal to the ‘reference voltage generator’ circuit. When the ‘stop/start logic’ is in its stop mode this signal reduces the ‘reference voltage generator’ output to zero and thus demands zero output voltage. • D11 pin 28 goes high on stop and sends a status signal to the UPS Logic Board via X4 pin 33 to request the micro to disable the inverter run signal. • D11 pin 34 goes high on stop and sends a status signal to the Auxiliary Inverter Logic Board (12-pulse inverter only); thus ensuring that where this option is used both the main and auxiliary boards are stopped and started by a common control signal.


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Start/stop logic circuit inputs

The ‘start/stop logic’ within D11 is driven by the following D11 inputs: 1. Inverter Vce(sat) error (detected by desaturation detector on Inverter Driver Interface Boards) – logic high to D11 pin 8 forces the stop mode (See paragraph 3.3.7). 2. Connector discontinuity (led H13 illuminated) – logic high to D11 pin 9 forces the stop mode (See paragraph 3.3.7) . 3. A system start/stop control input to D11 pin 13 from the UPS Logic Board, via X4-26, which is low on stop and high on start , provides the means of allowing the UPS Logic Board to shut down the inverter in response to certain system events – e.g. DC overvoltage, low battery, OFF selected from the Operator Panel, emergency shutdown, etc. This input also drives led H12 via D11 pin 17 (inverts the signal at pin 13) and illuminates the led when the signal is demanding the inverter to be turned OFF. 4. If a 12-pulse inverter is installed (option) the output from the ‘start/stop’ circuit on the Auxiliary Inverter Logic Board is connected to D11 pin 14 via X6-18 and is logic high on stop. This ensures that both main and auxiliary Inverter Logic Boards react to a common ‘Start/stop’ line (see also the output from D11 pin 34 described above). 5. A power supply monitor circuit based on N22 applies a logic high input to D11 pin 16, placing the ‘stop/start’ circuit in its stop mode if the 12V supply rail falls below 10Vdc. This circuit also holds off the inverter operation when the UPS is first powered up until the 12V rail rises above this level to allow the power supply time to stabilise before initiating the PWM drive signals. Led H11 illuminates when this circuit is demanding a stopped condition. 6. The transfer to inverter command [INV_L> generated on the UPS Logic Board is connected to D11 pin 13. This is clocked through D11 to enable the [RIF> signal. This re-references the inverter voltage to the bypass voltage just before the inverter is about to take over the load, which prevents any voltage drop appearing across the output contactor when it is instructed to close (See paragraph 3.3.3). The inverter voltage is referenced to the bypass voltage level for approximately 220ms before is it switches back to its normal reverence voltage: this more than adequately covers the output contactor closure time, which is approximately 50ms. Note that this function is disabled by the ‘mains fail’ signal [MNS_KO> to D11 pin 11 in the event of a mains failure; thus if the load is transferred to the inverter when the mains have failed then t he inverter will remain referenced to its normal reference voltage at all times. 3.3.9

Power supp ly (circuit diagram sheet 5) This board receives its control power supply from the DC-DC Power supply Board only, via connector X5. Pins 3, 4 and 5 carry regulated +12V, 0V and -12V power rails which form the Inverter Logic Board’s main supply inputs; and pins 1 and 2 carry an isolated 36Vac supply which is used by the Inverter Driver Interface Boards and connected via connectors X1, X2 and X3, as shown. A 5V regulator, N21, provides a regulated +5V rail from the +12 supply.

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The ±12V rails are diode-coupled to the ±12V rails on the UPS Logic Board via V14 and V15, as shown on sheet 4 of the diagram. Thus in the event of mains failure (i.e. the AC-DC Power Supply is inactive) the DC-DC Supply will maintain the control power to all the electronic circuit boards.

3.4

Summary Inform ation Table 18-11: Inverter Logic Board configuration jumpers

Jumper

Link Position

Function

1 - 2

Enable disconnected cable detector (Standard)

2 - 3

Override disconnected cable detector (Test)

1 - 2

Enable thermostat detector (Standard)

2 - 3

Override thermostat detector (Test)

X12

X13 5 links – override control inputs from UPS Logic Board as shown on main circuit diagram

X14

X15

0-5

1200Hz

0-1

2400 Hz

0-2

4800Hz

0-1 0-2

9600Hz

1-2 0-2

C-phase current monitor signal selection (where only 2 CTs are fitted to the inverter phases – standard to 7200 range)

2-3

C-phase current monitor signal selection (where 3 CTs are fitted to the inverter phases – used in larger modules)

PWM modulating frequency selection

X16

Table 18-12: Inverter Logic Board potentiometer adjustments Potentiometer

Function

R241

Amplitude of triangle wave adjustment

R242

Inverter voltage reference setting

R243

Manual inverter voltage adjustment (0 to 500V)

R244

Phase B to Neutral adjustment

R245

Phase C to Neutral adjustment

R246

150% Inverter Current Limit

R247

Phase displacement adjustment Inverter to Bypass

Table 18-13: Inverter Logic Board LED indications LED

Colour

H1

Green

380V operation

H2

Green

400V operation

H3

Green

415V operation

H4

Amber


Function

Manual operation Range 0 - 500 Volts ( wise = minimum)

Clock-

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LED

Colour

Function

H5 to H10

Red

Transistor saturation, (R+, R– : S+, S– : T+, T–.)

H11

Red

PCB power supply failure

H12

Red

Inverter off from UPS Logic Board

H13

Red

Ribbon cable monitor block

H14

Red

Inverter in 150% current limit (Active)

Table 18-14: Inverter Logic Board test points Test Poin t X8 X8 - 1

Inverter ref. A

(8V p - p)

X8 - 2

Inverter ref. B

(8V p - p)

X8 - 3

Inverter ref. C

(8V p - p)

X8 - 4

Inverter DC ref.

X8 - 5

Inverter pulse for φ displacement

X8 - 6

φ displacement error pulse

Test Poin t X9 X9 - 1

Inverter feedback A

X9 - 2

Inverter feedback B

X9 - 3

Inverter feedback C

X9 - 4

Bypass A

8V p-p

X9 - 5

Bypass B

8V p-p

X9 - 6

Bypass C

8V p-p

Test Point X10 X10 - 1

Current φ A (0.2V p - p No Load)

X10 - 2

Current φ B (0.2V p - p No Load)

X10 - 3

Current φ C (0.2V p - p No Load)

X10 - 4

0.6V Current limit

Test Poi nt X11

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X11 - 1

Inverter pulse plus correction for UPS Logic PCB

X11 - 2

Block pulse A

X11 - 3

Block pulse B

X11 - 4

Block pulse C

X11 - 5

PWM A

X11 - 6

PWM B

X11 - 7

PWM C

X11 - 8

Square pulse enable


Section 5:

Chapter 4 - Inverter Gate Driver Board

4.1

Chapter Overvi ew This chapter contains a circuit description of the Inverter Gate Driver Board used across the whole 7200 UPS model range and should be read in conjunction with circuit diagram SE-4519015-H.

4.2

General descri pti on Details of the IGBT and its drive requirements are described on page 5-19.

4.2.1

Circuit board functio ns Figure 5-37: Inverter Gate Driver Board Block Diagram CN1

3 4

Desaturation Fault Signal Generator

1 2

Drive Signal Demodulator

Control Logic Chip IC2

Power Supply for High Transistor

Power Supply Monitor

9 10 19 20

Desaturation Monitor

C

Output Drive Pulses

G E

M1 S

Power Supply Transformer

Thermostat Connections T

11 12

13 14

Power Supply for High Transistor

Power Supply Monitor

Drive Signal Demodulator

Control Logic Chip IC52

Desaturation Fault Signal Generator

s5-c3.f m5 - Issu e 2 Dated 21/08/97

1 2 3

Output Drive Pulses

G E

Desaturation Monitor

C

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SECTION 5 - Inverter Operation & Control CHAPTER 4 - Invert er Gate Driv er Board


The Gate Driver Board is responsible for processing the modulated PWM transistor drive signals produced by the Inverter Logic Board, making them suitable for driving the inverter power transistors. It also provides galvanic isolation of the drive signals and power supply, which is necessary to keep the high voltage environment surrounding the power inverter transistors away from the low voltage environment of the electronic control boards. Three driver boards are used (one per power inverter phase) with each board containing two identical, but electrically separate, circuits to drive the two transistors contained in the inverter power block. These channels are easily observed on the circuit diagram and described in detail below (See Figure 5-37). 4.2.2

Input/Outpu t con nectio ns Each of the three driver boards is connected to the Inverter Logic Board by means of a ribbon cable to connector CN1. This cable carries the power supplies, drive signals and fault detection signals for both ‘high’ and ‘low’ transistors in the particular inverter phase. The connections between the Gate Driver Board and the inverter IGBTs are made by hard-wired terminations rather than being socketed – note that in each case the connections are colour-coded: • Black = Collector • White = Gate • Red = Emitter. Thermostats can be fitted to the inverter heatsinks as an optional facility. Where these are used, they are hard-wired to the Inverter Gate Driver Board terminals S and T; then connected to the control system via connector M1.

4.3

Detailed cir cui t descrip tio n

4.3.1

Power sup pli es Two independent (and isolated) sets of power supplies are produced on the Gate Driver Board – one for each inverter drive channel. The supplies are obtained from the 30Vp-p (20 kHz) output on the DC-DC Power Supply Board which is connected to T1 primary via CN1 pins 9/10 and 19/20. T1 has two isolated secondaries which are connected to identical power supply circuits. T1 secondary voltage is first rectified by a diode bridge to provide a raw +15V power rail which is then connected to a standard three-terminal +5V voltage regulator (IC4/IC54). Notice that the supply used by the circuit driving the inverter ‘high’ transistor is annotated ‘0VH’, ‘5VH’ and ‘15VH’, while the ‘low’ transistor channel is annotated ‘0VL’, ‘5VL’ and ‘15VL’.

4.3.2

Gate driv e sig nal con trol log ic At the heart of the gate drive circuit control is a purpose-designed integrated circuit – identified as IC2 in the ‘high’ transistor channel and IC52 in the ‘low’ channel. As both drive channels are identical in operation, the following description concentrates on the ‘high’ channel (IC2) only. The inverter transistor drive signals are produced at IC2 pins 12 and 13, and connected to the transistor via drivers TR1-TR4. The i nverter transistor is turned ON by making its gate positive with respect to its emitter, and turned OFF by reversing this polarity – note that just leaving the gate open circuit is insufficient to turn OFF the device.

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SECTION 5 - Inverter Operation & Control CHAPTER 4 - Invert er Gate Driver Boar d

The circuit diagram shows that the gate terminal is connected to the junction of driver transistors TR1 and TR3; and the emitter terminal is similarly connected to the junction of TR2 and TR4. TR1 to TR4 thus form a bridge across the 15V power rail. To turn ON the inverter transistor, drivers TR1 and TR4 must be turned ON, and to turn the inverter transistor OFF, drivers TR2 and TR3 must be turned ON. Regarding the control logic chip IC2, this means that IC2 pin 13 has to be logic high and pin 12 logic low in order to turn the inverter transistor ON with the opposite logic states being necessary to turn it OFF. Note: links CV2/3 and CV52/53 must remain OPEN when this board is fitted to the 7200 Series UPS range. Fitting these links increases the gate drive signal power which is necessary when the board is used with inverters of a higher power level. Figure 5-38: IC2 Internal Details 1 19

2

2

3 14

3 a b

4

6

c d

9

18

5 8

7 a b

8 13

c d

9 a b

10 12

c d

11 4 17

13 12 6

16

Figure 5-38 shows IC2's internal logic functions. The internal gates have been identified numerically as an aid to description (gate 1 to gate 13), although these are of course inaccessible. The Inverter Logic Board generates the required inverter PWM pattern and, in its output stage, modulates the resultant variable mark-to-space gate drive signals with a high frequency carrier signal (See paragraph 2.3.4) . This composite drive

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SECTION 5 - Inverter Operation & Control CHAPTER 4 - Invert er Gate Driv er Board


waveform is then connected to the Gate Driver Board at CN1 pins 1 and 2. As such, the signal can be interpreted that the inverter transistor is to be turned ON when the carrier signal is present and turned OFF when it is not. The first circuit that the drive signals meets on the Gate Driver Board is a demodulator, comprising D5-D8 and C10, which converts the drive signal back into its basic PWM logic pattern. This signal is isolated by opto-coupler OP1 and connected to IC2 pin 2. 4.3.3

Turni ng the inverter transi stor ON It has already been stated that IC2 pin 13 must be `high' and pin 12 `low' in order to turn ON the inverter transistor. Referring to Figure 5-38, this means that the four inputs to gates 8 and 10 must all be logic high. As will be shown later, the input to gates 8d and 10d from gate 12 is normally high, and will go low only if the Gate Driver Board 5V power supply fails. The input to gates 8a and 10a from gate 11 is also normally high and will go low if the ‘de-saturation’ monitor circuit detects an inverter transistor overload. Under normal circumstances therefore, the main control inputs of interest are those applied to gates 8 and 10 pins b and c. When the input drive signal demands the inverter transistor to be turned ON the output from OP1 applies a logic low to IC2 pin 2. This is inverted by gate 1 to a logic high at IC2 pin 19, and by gate 2 to a logic high at gates 8c and 10c. When IC2 pin 19 goes high it drives IC2 pin 3 high after a 4µs time delay which is due to R7/C6. This delay is designed to give the inverter low transistor sufficient time to turn OFF before the high transistor is eventually switched ON and is directly related to the IGBT propagation delay time (see paragraph 1.4.2.1 on page 5-21). When IC2 pin 3 goes high it places a high on gates 8b and 10b making IC2 pin 13 go high and pin 12 low –i.e. the conditions needed to turn ON the inverter high transistor.

4.3.4

De-saturatio n detector The de-saturation detector circuit monitors the voltage across the inverter transistor (Vce) during its turn ON period. This voltage is normally be very low (i.e. less than 4V); but will increase if the load current demand becomes excessive and makes the transistor de-saturate, or if the transistor is open circuit. The de-saturation circuit, shown in detail in Figure 5-39, comprises a fixed voltage divider chain (R2, R3, R4 and R6) connected to the +15VH power rail – the `hot' end of R6 is connected to IC2 pin 9, which is the ‘de-saturation’ input to the controller chip. The inverter transistor collector voltage is diode-coupled into the divider chain via D9 and R20 – i.e. D9 provides a means of clamping the junction of R2 and R3. Note that although the de-saturation circuit monitors the Vce of the inverter IGBT, the monitored signal is not connected directly to the transistor's emitter terminal. Instead, the detector uses the 0VH line which is connected to the inverter transistor emitter via TR4 when the transistor is turned ON – i.e. the de-saturation detector monitors the combined Vce of the inverter ‘high’ transistor and Vds of TR4. Under `normal' circumstances (i.e. when the inverter is not being overloaded) the monitored transistor collector voltage is sufficiently low to clamp the R2/R3 junction at a voltage seen as a logic low (<<0.8Vdc) by IC2 pin 9. The resistor values have been chosen means that this condition is satisfied when the monitored voltage is approximately 3.7V (assuming 0.7V drop across D9 when it is turned ON).

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SECTION 5 - Inverter Operation & Control CHAPTER 4 - Invert er Gate Driver Boar d

Figure 5-39: Desaturation detector DC BUS POSITIVE

+15VH R2 D9 R20

R?

IGBT

RES R3

Gate Driver B oard R4

INV OUT

desat

IC2

TR4

R6

0VH

DC BUS NEGATIVE

A fault is registered by IC2 when its pin 9 rises to logic high (>>2.0Vdc), which occurs if the monitored voltage rises above approximately 10.3Vdc. This is assumed to be the point at which the inverter transistor is operating in a potentially dangerous de-saturated condition. Another condition that has to be taken into consideration when monitoring for de-saturation is the transistor ‘turn-on’ time. A transistor does not change from being fully OFF to fully ON instantaneously; therefore, when the transistor is initially turned ON there is certain to be a brief interval where its collectoremitter voltage will exceed the level detected as a de-saturated condition. For this reason, the de-saturation monitor circuit allows the transistor 8µs to attain a saturated state after it has been instructed to turn ON (i.e. 12 µs from the application of the gate drive pulse to IC2 pin 2). The circuit works as follows:

Within IC2, gate 4 forms the de-saturation detector gate. Gate 4d is held permanently high due to IC8 pin 8 being pulled down to 0V by R5 (SH1 not fitted). Gate 4b goes high as soon as a gate drive signal is applied to IC2 pin 2 (low) and gate 4a goes high 4µ s later when IC2 pin 3 goes high. This means that a logic high output is produced at IC2 pin 18 if the input t o gate 4c, from IC2 pin 9, goes high. The input to IC2 pin 9 comes from the de-saturation detector circuit as previously described. Put another way, IC2 pin 18 goes high only when the inverter is receiving a gate drive signal and its collector-emitter voltage is greater than the saturation level. When IC2 pin 18 goes high it sets off an 8µs time delay effected by R10/C7; however, if the de-saturation signal to IC2 pin 9 returns to a l ogic low within 8µ s, then IC2 pin 18 will return to a logic low and reset the time delay circuit.

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Sect-5

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