Sect-13

Section 13: Appendices

Appendix A - Device specifications Appendix B - CAN Bus Appendix C - PCB Layout diagrams Appendix D - PCB Link selection details Appendix E - UPS Module General Specifiication

S-12.fm5 - Issu e 2 Dated 21/08/97 21/08/97

i

SECTION 13 - A p p en d i c es

ii

7200 Ser i es UPS Ser v i c e Man u al

S-12.fm5 - Issu e 2 Dated 21/08/97 21/08/97

A:

Appendix A : Device Specifications

A.1

74HCT245 – Octal Oct al 3-s tat e, no n-i nv ert in g b us tr anscei ans cei ver The HCT245 is a 3-state non-inverting transceiver that is used for 2-way asynchronous communication between data busses. The device has an active-low Output Enable pin, which is used to place the I/O ports into high-impedance states. The Direction control determines w hether data flows from A-to-B or from B-to-A. Figure A-1: 74HCT245 A0 A1 A2 A3 A4 A5 A6 A7

Direction Output Enable

2

18

3

17

4

16

5

15

6

14

7

13

8

12

9

11

B0 B1 B2 B3 B4 B5 B6 B7

Direction

1

20

Vcc (+5V)

A0

2

19

OE

A1

3

18

B0

A2

4

17

B1

A3

5

16

B2

A4

6

15

B3

A5

7

14

B4

A6

8

13

B5

A7

9

12

B6

Gnd

10

11

B7

1 19

CONTROL INPUTS Output Enable

Di r ec t i o n

L

L

Data transmitted from bus B to bus A

L

H

Data transmitted from bus A to bus B

H

X

Busses isolated – (Hi-impedance state)

Ap p-a.f m5 - Iss ue 2 Dated Dat ed 21/08/97

Op er at i o n

A-1

Ap pen di x A Device Device specificatio n

A.2

7200 Seri es UPS Serv Se rv ic e Manu al

74HCT273 Octal Oct al D-t ype yp e Fli p-Flo p- Flop p The HCT273 consists of eight D-type flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous (i.e. at any time) and active low. Figure A-2: 74HCT273 D0 D1 D2 D3 D4 D5 D6 D7

Clock Reset

2

3

4

5

7

6

8

9

13

12

14

15

17

16

18

19

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

1

20

Vcc

Q0

2

19

Q7

D0

3

18

D7

D1

4

17

D6

Q1

5

16

Q6

Q2

6

15

Q5

D2

7

14

D5

D3

8

13

D4

Q3

9

12

Q4

Gnd

10

11

Clock

11 1

INPUTS

OUTPUTS

Res et

Cl o c k

D

Q

L

X

X

L

H

H

H

H

L

L

X

No change

X

No change

H H

A-2

Reset

L

Ap p-a.f m5 - Iss ue 2 Dated Date d 21/08/97

7200 Ser i es UPS Ser v i c e Man u al

A.3

A p p en d i x A Device Device specificatio n

Typ e 4052 Dual 4-ch annel ann el Mu lt i pl exer The 4052 device contains two 4-way multiplexer switches controlled by two address (select) inputs. Each switch is identified as “X” or “Y”. An ‘inhibit’ input turns off both switches when set high. Figure A-3: A-3: 4052 Multiplexer Inhibit Select (A)

6

1Y

1

16

Vdd

10

3Y

2

15

3X

9

Y

3

14

2X

4Y

4

13

X

2Y

5

12

1X

Inhibit

6

11

4X

Vee

7

10

Sel (A)

Vss

8

9

Sel (B)

Select (B) 1X 2X 3X 4X

12 14

13

15

X

11 1

1Y

5

2Y

3

2

3Y

Y

4

4Y

INPUTS

OUTPUTS

In h i b i t

A

B

X

Y

L

L

L

1X

1Y

L

L

H

2X

2Y

L

H

L

3X

3Y

L

H

H

4X

4Y

H

X

X

None

None

Ap p-a.f m5 - Iss ue 2 Dated Dat ed 21/08/97

A-3

Ap pen di x A Device specificatio n

A.4

7200 Seri es UPS Serv ic e Manu al

74HC573 Octal D-t yp e Fli p-Fl op The 74HCT573 consists of eight D-type flip-flops with common Latch Enable and Output Enable inputs. Each flip-flop is loaded with a low-to-high transition of the Latch Enable input. Output Enable is asynchronous and active low. Figure A-4: 74HCT573 D0 D1 D2 D3 D4 D5 D6 D7

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

Latch Enable Output Enable

Q0

O/enable

1

20

Vcc

Q1

D0

2

19

Q0

Q2

D1

3

18

Q1

Q3

D2

4

17

Q2

Q4

D3

5

16

Q3

Q5

D4

6

15

Q4

Q6

D5

7

14

Q5

Q7

D6

8

13

Q6

D7

9

12

Q7

Gnd

10

11

Latch Enable

11 1

INPUTS

A-4

OUTPUTS

Output Enable

Latch Enable

D

Q

L

H

H

H

L

H

L

L

L

L

X

No change

H

X

X

Hi-Z

Ap p-a.f m5 - Iss ue 2 Dated 21/08/97

7200 Series UPS Service Manual

A.5

Appendix A Device specificatio n

SN75176A Diff erent ial Bu s Transc eiver The SN75176 differential bus transceiver is de signed for bi-directional data communication on multi-point bus transmission lines. It is designed for balanced transmission lines and meets EIA Standard RS-422A. Figure A-5: SN75176A DE

3

DI

4

RE

2

RD

1

Driver

6

DD/RI

7

DD/RI

RD

1

8

RE

2

7

DE

3

6

Vcc DD/RI DD/RI

DI

4

5

GND

BUS

Receiver

Function Table (Driver) INPUTS

OUTPUTS

Data In (DI)

Data Enable (DE)

DD/RI

DD/RI

H

H

H

L

L

H

L

H

X

L

Hi-Z

Hi-Z

Function Table (Receiver) DIFFERENTIAL INPUTS

OUTPUTS

A – B

RE

RD

VID > 0.2V

L

H

-0.2V < VID < 0.2V

L

?

VID < -0.2V

L

L

X

H

Hi-Z

The device combines a 3-state differential line driver and a differential-input line receiver, both of which operate from a single +5V power supply. The driver and receiver have active-high and active-low enables, (DE) and (RE) respectively, that can be externally connected together to function as direction control. The driver differential outputs and the receiver differential inputs are connected together internally to form a differential I/O bus port which is designed to offer minimum loading to the bus whenever the driver is disabled. The receiver operates on a differential input greater then 0.2mV, as shown in the above table. These ports feature good common-mode noise rejection when used on a balance line making them ideal for use over party-line applications.


A-5


A.6


SN75155 Line Dr iv er an d Rec eiv er The SN75155 is a line driver and receiver that is designed to satisfy the requirements of the standard interface between data terminal equipment (DT E) and data communication equipment (DCE) as defined by EIA standard RS232. A Response Control input (RTC) is provided for the receiver. A resistor, or resistor and bias voltage, can be connected between the Response Control input and ground to provide noise filtering. Figure A-6: SN75155

VccVcc+ DA

GND

RA RTC

A-6

1

Vcc-

1

8

8

DA

2

7

RY

3

6

Vcc+ DY RTC

GND

4

5

RA

7

2

4

5

DY

REFERENCE REGULATOR

3

RY

6



A.7


MAX232 Dual EIA -232 Dri ver /Recei ver The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply EIA-232 voltage levels from a single +5V supply. Each receiver converts the EIA-232 inputs to 5V TTL/CMOS levels. These receivers have a typical threshold of 1.3V and a typical hysteresis of 0.5V, and can accept ±30V inputs. Each driver converts TTL/CMOS input levels into EIA-232 levels. Figure A-7: MAX232 Vcc 16 C1+ C1C2+ C2-

T1IN T2IN R1OUT R2OUT

1 3 4 5

C1+ C1-

2Vcc -1.5V

C2+ -2Vcc +1.5V

2

6

VS+

VS-

C2-

11

14

10

7

T1OUT

C1+

1

16

Vcc

VS+

2

15

GND

C1-

3

14

T1OUT

C2+

4

13

R1IN

C2-

5

12

R1OUT

VS-

6

11

T1IN

T2OUT

7

10

T2IN

R2IN

8

9

R2OUT

T2OUT 12

13

9

8

R1IN R2IN

15 GND


A-7


A.8


8251A Prog ram mab le Co mm un ic atio ns in terf ace Figure A-8: 8251A

DB0....DB7

RST CLK C/D RD WR

Data Bus Buffer

Read/Write Control Logic

Transmit Buffer (P to S)

Transmit Control

TxD

TxRDY TxE TxC

CS

DSR DTR CTS

Modem Control

RTS Internal Data Bus

A.8.1

Receive Buffer (S to P)

Receive Control

RxD

RxRDY RxC SYNDET

D2

1

28

D1

D3

2

27

D0

RXD

3

26

Vcc(+5V)

GND(Vss)

4

25

RxC

D4

5

24

DTR

D5

6

23

RTS

D6

7

22

DSR

D7

8

21

RST

TxC

9

20

CLK

WR

10

19

TxD

CS

11

18

TxE

C/D

12

17

CTS

RD

13

16

SYNDET/BD

RxRDY

14

15

TxRDY

Int ro du ct io n The 8521A is a Universal Synchronous/Asynchronous Receiver/Transmitter (USART) designed for use with a wide range of microcomputers (CPUs). In a communication environment, the device converts parallel data on the system data bus into a serial format for transmission and also converts the incoming serial communication line data into parallel form acceptable to the data bus. In carrying out these transformations the 8251A also deletes or inserts ‘framing’ bits or characters that are required by the communication mode in use. Data is passed between the ‘transmit’ or ‘receive’ sections and the ‘data bus buffer’ by means of an internal 8-bit data bus, with the transfer between these sections being controlled by the ‘read/write control logic’ block at a rate determined by its clock input. However the serialised information is clocked into the ‘transmit buffer’ (from the internal bus) and ‘receive buffer’ (from communications line) by independent external clock signal – TxC and RxC respectively. Like other I/O devices in a microcomputer system, the 8251A functional configuration is programmed by the system’s software for maxim um flexibility. Thus in addition to the system data the 8251A also receives Mode/command words from the CPU which determines its operating parameters such as baud-rate, character length, number of start/stop bits, parity and synchronous/asynchronous mode of operation. The device differentiate between system data and Mode/command words by observing the state of its (C/D) input, as described below. The 8251A has facilities that allow the CPU to read the status of the device at any time during its functional operation – activated when (RD)=0 and (C/D) =1 (see table below). Some of the bits in the st atus register have identical meanings to external output pins, so that the 8251A can be used in a completely polled or interrupt-driven environment. The following information is available from the status register (described in more detail later):

A-8



• • • • • • • •

A.8.2


Transmitter section ready (TxRDY) (not identical to external TxRDY pin) Receiver section ready (RxRDY) Transmit buffer empty (TxE) Parity error Overrun error (CPU fails to read a character before the arrival of the next) Framing error (stop/start bit detection error) Synchronisation (SYNDET) Data Set Ready (DSR)

Fun ct io nal d esc ri pt ion Following is a description of the 8251A device based on the block diagram at the top of the previous page: Data Bus Buffer

This tri-state, bi-directional, 8-bit buffer interfaces the 8251A to the system data bus. All transmitted and received data passes though the buffer together with ‘control words’ and ‘command words’. Read/Write Control Logic

This functional block accepts inputs from the system control bus and generates control signals for the overall device operation. It contains the ‘control word’ and ‘command word’ registers that store the various control formats for the device’s functional definition. The control inputs are described below:

Chip Select (CS). This input allows the device to be individually selected from other devices within its address range, and is active low. When this input is high it is not possible to read from (or write to) to the device, and its data bus outputs are driven to a high impedance state.

Read (RD). This input is taken low when the associated processor wishes to read the data held in the 8251A’s Data Bus Buffer.

Write (WR). This input is taken low when the associated processor wishes to transfer data from the system data bus to the 8251A’s Data Bus Buffer.

Control/Data (C/D). This input, in conjunction with the (RD) and (WR) in puts, informs the 8251A that the word on the system data bus is either a ‘data character’ or a ‘control/status’ information. A logic high indicates ‘data’ and low indicates ‘control//status’ word. As the above four inputs all affect the Read/Write functions these are summarized in the table below: Table A-1: C/D

RD

WR

CS

0

0

1

0

CPU Reads Data from 8251A Data Bus Buffer

0

1

0

0

CPU Writes Data to 8251A Data Bus Buffer

1

0

1

0

CPU Reads Status Byte from 8251A Data Bus Buffer

1

1

0

0

CPU Writes Control Byte to 8251A Data Bus Buffer

X

1

1

0

Data Bus Buffer = High Z

X

X

X

1

Data Bus Buffer = High Z


DATA FLOW

A-9



Reset (RST). The 8251A assumes an idle state when this input is taken high. And when it returns low it remains i n this state until it receives a new ‘mode control’ instruction from the associated processor.

Clock (CLK). This input is used for internal timing within the 8251 and does not control the transmit or receive rate. Generally, it should be at least 30 times the transmit or receive rate. Transmit buffer

The ‘transmit buffer’ accepts parallel data from the ‘data bus buffer’, converts it to a serial bit-stream, inserts the appropriate characters or bits required by the communication protocol in use, and outputs a composite serial data-stream on the TxD output pin. Transmit control

The ‘transmit control’ block manages all the activities associated with the transmission of serial data. It accepts and issues signals both externally (described below) and internally to accomplish this function.

Transmit Clock (TxC). The serial data on TxD is clocked out on the falling edge of the TxC signal.

Transmitter Ready (TxRDY). This output goes high when data in the ‘data bus buffer’ has been shifted into the ‘transmit buffer’ and informs the CPU that the 8251A is ready to receive the next data character for transmissi on. TxRDY is automatically reset by the leading edge of the WR input when a data character is loaded from the CPU.

Transmitter Empty (TxE). The TxE output goes high when the transmitter section has transmitted its data and the ‘transmit buffer’ is empty. It will remain high until a new data byte is shifted into the ‘transmit buffer’. This line can be used to indicate the end of a transmission mode, so that the CPU “knows” when to “turn the line around” in the half-duplex operational mode. Receive buffer

The ‘receive buffer’ accepts serial data from the transmission line (RxD), converts it to a parallel format, checks for characters or bits required by the communication protocol in use, and sends an “assembled” character to the CPU via the ‘data bus buffer’. Receive control

The ‘receive control’ block manages all receiver-related activities, including ‘start’, ‘stop’ and ‘parity’ bit detection and the detection of several error states. The external signals associated with this block are:

Receiver Clock (RxC). The ‘receiver clock’ (RxD) controls the rate at which the character is to be received. In “synchronous” mode, the baud rate (1x) is equal to the actual frequency of (RxD). In “ asynchronous” mode the baud rate is a fraction of the actual (RxD) frequency as selected by the “mode” instruction. This can be set to 1/16th or 1/64th of (RxC).

Receiver Ready (RxRDY). This output indicates to the processor that data has been shifted into the receiver buffer from the receiver section and may now be read. The signal is active high and is reset when the buffer is read by the processor.

A-10




Sync Detect (SYN-DET). This signal is used only in the synchronous mode. It can be either an input or output depending on whether the program is set for internal or external synchronisation. As an output, a high level indicates when the sync character has been detected in the received data stream after the Internal Synchronisation mode has been programmed. SYN-DET is reset when the status buffer is read or when a reset signal is activated. SYN-DET performs as an input when the External Synchronisation mode is programmed. External logic can supply a positive-going signal to indicate to the 8251 that synchronisation has been attained. This will cause it to initialise the as sembly of characters on the next falling edge of RxC. To successfully achieve synchronisation, the SYN-DET signal should be maintained in a high condition for at least one full cycle of RxC. Modem control

The 8251A has a set of control inputs and outputs that can be used to simplify the interface to almost any modem. The modem control signals are general purpose in nature and can be used for functions other than modem control, if necessary.

Data Terminal Ready (DTR). This signal reflects the state of bit 1 in the Command Instruction. It is commonly used to signal to an associated modem that the 8251 is ready.

Data Set Ready (DSR). This input signal forms part of the status byte that may be read by the processor. DSR is generally used as a response to DTR, by the modem, to indicate that it too is ready. The signal acts only as a flag and does not control any internal logic.

Request To Send (RTS). This signal reflects the state of bit 5 in the command instruction. It is normally used to initiate a data transmission by requesting the modem to prepare to send.

Clear To Send (CTS). This input is generally used as a response to RTS by a modem, to indicate that transmission may begin.


A-11


A.9


UC3845 Curren t-mo de PWM Cont ro ll er Figure A-9: UC3845

Vcc

7

Type UC3845 Current Mode PWM controller

UVLO GND Vref

S/R

5 8

5V REF

7 2.5V

RT/CT

Vref GOOD LOGIC

4

OSCILLATOR Toggle

Vfb Comp Isense

A.9.1

1 2 3

V Error Amp

S

2R

T U 6 P T U O 5

R

R 1V

Current Sense Comparator

PWM Latch

Int ro du ct io n The UC3845 integrated circuit provides features necessary to i mplement off-line or dc-to-dc fixed-frequency current-mode control schemes with a minimum number of external components. Some of the internally implemented circuits are an ‘undervoltage lockout’ (UVLO) featuring a start-up current of less than 1 mA and a precision ‘voltage reference’ trimmed for accuracy at the error amplifier input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator (which also provides current-limit control), and a totem-pole output stage designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off state.

A.9.2

Fun ct io nal d esc ri pt ion Input supply

The device can be powered by a single supply rail of up to 30V (Vcc/Gnd); but when power is first applied the undervoltage lockout (UVLO) comparator holds off the circuit’s operation until Vcc rises above 8.4V. Conversely, on power-down UVLO turns off the device when Vcc falls below 7.6V. If Vcc falls within the permissible operating voltage limits, the UVLO ‘sets’ an S-R flip-flop which ‘enables’ a 5V reference voltage generator whose output is presented to the external circuitry via pin 8 (Vref). In practice this stable reference voltage can be used to bias the oscillator’s external frequency determining com ponents. Note that the 5V reference voltage is monitored by the ‘vref good logic’ block which inhibits the output gate if this voltage is in error. Vref is also divided by two, and the resulting 2.5V reference voltage is internally connected to the ‘voltage error amp’ non-inverting input. PWM Control

The output PWM signal at pin 6 is controlled by the PWM latch which is ‘set’ (pin 6 driven high) by the internal oscillator output going high. As the oscillator is of fixed frequency this means that the leading edge of the output PWM pulses appear at a regular interval irrespective of their adopted pulse-width.

A-12




The oscillator frequency is determined by external R-C components connected to pin 4 (RT/CT). Generally, the timing resistor is connected between pin 8 (Vref) and pin 4 (RT/CT); and the timing capacitor between pin 4 (RT/CT) and pin 5 (Gnd). The oscillator frequency is then calculated as: 1.72 F = ------------------ R T × C T

Note: In the UC3845 version of this device range the output PWM frequency is only half the oscillator frequency due to the implementation of an extra T (toggle) flip flop connected ahead of the output gate, which is included to limit the output mark-to-space to 2:1 (i.e. maximum 50% duty cycle).

The PWM latch is ‘reset’ (pin 6 driven low) by the ‘current sense comparator’ when the current sense signal applied to pin 3 exceeds t he level set by the ‘voltage error amp’ output. The ‘voltage error amp’ output is in turn determined by a voltage feedback signal applied to pin 1 (Vfb) and its gain is set by the value of an external resistor connected between pins 1 & 2. The Vfb signal therefore sets the threshold for the ‘current sense comparator’ which in then determines the PWM switching point. Start Stop Control

The ‘demand’ output from the ‘volts error amp’ to the ‘current sense comparator’ is connected via two diodes and a 2:1 resistive attenuator; and is limited by a zener to 1V at the comparator’s input. It is possible therefore to ‘stop’ the i.c’s internal operation by either making pin 1 less than two diode drops (<1.2V) with respect to ground, or by taking pin 3 greater than 1V. In the former case, the ‘current sense comparator’ is effectively ‘seeing’ zero demand from the ‘volts error amp’ and applies a permanent ‘reset’ to the ‘PWM latch’. In the latter case the current sense signal is permanently greater than the ‘demand’ signal from the ‘volts error amp’ and the ‘current sense comparator’ again permanently resets the ‘PWM latch’.


A-13


A.10


PCA82C250 CAN Con tr ol ler Int erf ace Figure A-10: PCA82C250 TxD

1

8

GND

2

7

Vcc

3

6

Rs(SI) CANH CANL

RxD

4

5

Vref Vcc 3

1

TxD

Protection

8

Rs

Driver

Slope/ Standby

7

CANH

4

RxD

6 CANL 5

Vref

C A N B U S

Reference Voltage

2 GND

Table A-2: Truth table of CAN transceiver. TxD

CANH

0

A.10.1

CANL CANH > (CANL+0.9V)

RxD 0

1 (or floating)

Floating

Floating

1

X

Floating

Floating

X

>0.75VCC

Floating

Floating

X

X

floating if VRs > 0.75VCC

floating if VRs > 0.75VCC

X

Int ro du ct ion The device combines a 3-state differential line driver and a differential-input line receiver, both of which operate from a single +5V power supply. The driver differential outputs and the receiver differential inputs are connected together internally to form a differential I/O bus port which is designed to offer minimum loading to the bus whenever the driver is disabled. The receiver operates on a differential input greater then 0.9V, as shown in the above table. These ports feature good common-mode noise rejection when used on a balance line making them ideal for use over party-line applications.

A-14



A.10.2


Fun ct io nal Desc ri pt io n The PCA82C250 is the interface between the CAN protocol controller and the physical bus. The device provides differential transmit capability to the bus and differential receive capability to the CAN controller. Pin 8 (Rs) allows three different modes of operation to be selected: high-speed, slope control or standby. For high-speed operation, the transmitter output transistors are simply switched on and off as fast as possible. In this m ode, no measures are taken to limit the rise and fall slope. Use of a shielded cable is recommended to avoid RFI problems. The high-speed mode is selected by connecting pin 8 to ground. For lower speeds or shorter bus length, an unshielded twisted pair or a parallel pair of wires can be used for the bus. To reduce RFI, the rise and fall slope should be limited. The rise and fall slope can be programmed with a resistor connected from pin 8 to ground. The slope is proportional to the current output at pin 8. If a HIGH level is applied to pin 8, the circuit enters a low current standby mode. In this mode, the transmitter is switched off and the receiver is switched to a low current. If dominant bits are detected (differential bus voltage >0.9 V), RxD will be switched to a LOW level. The microcontroller should react to this condition by switching the transceiver back to normal operation (via pin 8). Because the receiver is slow in standby mode, the first message will be lost. Table A-3: Rs Summary CONDITION FORCED AT Rs(SI)

MODE

RESULTING VOLTAGE OR CURRENT AT Rs(SI)

VRs > 0.75VCC

standby

IRs < |10µA|

10 mA < IRs < 200 µA

slope control

0.4VCC < VRs < 0.6VCC

VRs < 0.3VCC

highspeed

IRs < -500µA


A-15


A.11


80C166 Micro co nt rol ler

A.11.1

Int ro du ct ion The SAB 80C166 is the first representative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities; and offers the following major features: • • • • • • • •

High performance 16-bit CPU with 4-stage pipeline Up to 256 KBytes linear address space for code and data 1 KByte on-chip RAM 32 KBytes on-chip ROM (SAB 83C166 only) Programmable external bus characteristics for different address ranges Multiplexed or demultiplexed, 8-Bit or 1 6-Bit external data bus 512 Bytes on-chip special function register area Idle and power down modes 8-channel interrupt-driven single-cycle data transfer facilities via Peripheral Event Controller (PEC) 16-Priority-level interrupt system 10-Channel 10-bit A/D converter with 9.7µS conversion time Two multi-functional general purpose timer units with 5 timers Two serial channels (USARTs) Programmable watchdog timer Up to 76 general purpose I/O lines

• • • • • •

A.11.2

Fun ct io nal d esc ri pt ion Figure A-11: 80C166 Internal block diagram 16

Internal ROM Area

32

16

Internal RAM

CPU-Core

16 PEC

16

Interrupt Controller

XTAL

OSC

Watchdoog 16

16

2

A-16

Port 0

Port 4

Ext. Bus Control

10-Bit ADC

USART ASC0

GPT1

GPT2

CAPCOM

[T2] [T3] [T4]

[T5] [T6]

[T0] [T1]

USART ASC1

Port 1

Port 5

Port 3

Port 2

16

10

16

16



A.11.3


Memor y o rg ani zati on The memory space of the 80C166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same 256 KBytes linear address space. The entire memory space can be accessed byte wise or word wise. Particular portions of the on-chip memory have additionally been made directly bit addressable. 1 KByte of on-chip RAM is provided as a storage for user-defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RHO, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Registers, which are used for controlling and monitoring functions of the different on-chip units. To meet the needs of designs where more memory is required than is provided on chip, up to 256 KBytes of external RAM and/or RO M can be connected to the microcontroller.

A.11.4

Ext ern al B us Con tr ol ler All of the external memory accesses a re performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - 16-/18-bit Addresses,16-bit Data, Demultiplexed - 16-/18-bit Addresses, 16-bit Data, Multiplexed - 16-/18-bit Addresses, 8-bit Data, Multiplexed - 16-/18-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on Port 1 and data is input/ output on Port 0. In the multiplexed bus modes both addresses and data use Port 0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri- State Time, Read/Write Delay and Length of ALE, i.e. address setup/hold time with respect to ALE) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 64 KBytes of external memory space, a non-segmented memory model can be selected. In this case all memory locations can be addressed by 16 bits and Port 4 is not required to output the additional segment address lines. Semiconductor Group.

A.11.5

Cent ral Pro ces si ng Uni t (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the 80C166’s instructions can be executed in just one machine cycle which requires 100ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine


A-17



cycle independent of the number of bits to be s hifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycle s and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. A system stack of up to 512 bytes is provided as a storage for temporary data. This is allocated in the on-chip RAM area, and is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

A.11.6

Int err up t Sys tem With an interrupt response time within a range from just 250ns to 600ns (in case of internal program execution), the 80C166 is capable of reacting very fast to the occurrence of non- deterministic events. The 80C166 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The 80C166 has 8 PEC channels each of which offers such fast interruptdriven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit field exis ts for each of the possible interrupt services. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible i nterrupt sources has a dedicated vector location. The 80C166 also provides an excellent mechanism to identify and process exceptions or error conditions that arise during run-time; so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

A.11.7

Capt ur e/Com par e (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of 400ns (@ 20 MHz CPU clock). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.

A-18




Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/ compare register array. The input clock for the timers is programmable to several prescaled values of the CPU clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, an external count input for CAPCOM timer T0 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this resister. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.

A.11.8

Gener al Pur po se Ti mer (GPT) Uni t The GPT unit represents a very flexible multi-functional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, w hich are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement i s supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400ns (@ 20 MHz CPU clock). The count direction (up/down) for each timer is programmable by software. For timer T3 the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD). With its maximum resolution of 200ns (@ 20MHz), the GPT2 module provides precise event control and time measurement. It includes two timers T5, T6, both of which can be clocked with an input clock which is derived from the CPU clock


A-19



via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported.

A.11.9

A/D Con ver ter For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time adds up to 9.7 us @ 20MHz CPU clock. For applications which require less than 10 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter section supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a pre-specified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of pre-specified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer.

A.11.10

Parall el Por ts The 80C166 provides up to 76 I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high im pedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. Port 0 and Port 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A17/ A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2 is associated with the capture inputs or compare outputs of the CAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA, HOLD). Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR, BHE, READY) and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.

A.11.11

Seri al Chan nels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with identical functionality, Asynchronous/ Synchronous Serial Channels ASC0 and ASC1. They support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock. Two dedicated baud rate generators allow set up of all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception, 3 separate interrupt vectors are provided for each serial channel.

A-20




In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode one data byte is transmitted or received synchronously to a shift clock which is generated by the 80C166. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows recognition of data frames with missing stop bits.

A.11.12

Watchd og Tim er The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the end of initialization; t hus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25µ s and 420ms can be monitored (@ 20MHz CPU clock). The default Watchdog Timer interval after reset is 6.55 ms (@ 20MHz CPU clock).

A.11.13

Boo ts tr ap L oader The 80C166 provides a built-in bootstrap loader (BSL) which allows the execution of the start program outside its internal RAM. The program to be started is loaded via the serial interface ASC0 and does not require external memory or an internal ROM. The 80C166 enters BSL mode when ALE is sampled high at the end of a hardware reset and if NMI becomes active directly after the end of the internal reset sequence. BSL mode is entered independent of the selected bus mode. After entering BSL mode the 80C166 scans the RXD O line to receive a zero byte, i.e. one start bit, eight ‘0’ data bi ts and one stop bit. From the duration of this zero byte it calculates the corresponding baud rate factor with respect to the current CPU clock and initializes ASC0 accordingly. Using this baud rate, an acknowledge byte is returned to the host that provides the loaded data. The 80Cl66 exits BSL mode upon a software reset (ignores the ALE level) or a hardware reset (remove conditions for entering BSL mode before).


A-21


A-22



B:

Appendix B : Controller Area Networking (CAN)

B.1

Introduction The CAN (Controller Area Network) is an ISO defined serial communications bus that was originally developed during the late 1980’s for the automotive industry. Its basic design specification called for a high bit rate, high immunity to electrical interference and an ability to detect any errors produced. Not surprisingly, due to these features the CAN serial communications bus has become widely used throughout the automotive, manufacturing and aerospace industries.

B.2

CAN Arch itectu re The CAN communications protocol describes the method by which information is passed between devices. It conforms to the Open Systems Interconnection model which is defined in terms of layers (See Figure B-1) . Each layer in a device apparently communicates with the same layer in another device, but actual communication is between adjacent layers in each device and the devices are only connected by the physical medium via the physical layer of the model. In practice, the physical medium consists of a twisted-pair or optical coupling with appropriate termination. The CAN architecture defines the lowest two layers of the model – i.e. the data link and physical layers. The application levels are linked to the physical medium by the layers of various emerging protocols, dedicated to particular industry areas plus any number of propriety schemes defined by individual CAN users. Figure B-1: Open Systems Interconnection model

The 7200 Series UPS system uses a type 80C200 standalone CAN controller which directly interfaces to the microcontrollers, and the connection to the physical medium is implemented with the 82C250 integrated circuit.

app-b.fm 5 - Issue 2 Dated 21/08/97

B-1

Ap pen di x B Controller A rea networking (CAN)

B.3


Varieti es Of CAN CAN exists in two forms; ‘ Basic CAN’ and ‘Full CAN’. The difference between the two types of controller are mainly cost. Basic CAN is cheaper because it required less buffer space and CPU workload: Full CAN is less demanding on the work required by the CPU. ‘Basic CAN’

Basic CAN has a tight coupling between the CPU and the CAN controller, where all messages broadcast on the network have to be individually checked by the microcontroller. With Basic CAN , the messages are held in the CPU’s memory, and the CPU must do all the work in keeping track of messages. The CPU must also handshake with the 82C200 controller (using ‘message sent’ and ‘message arrived’ interrupt handlers) to send and receive messages. This results in the CPU being ‘tied up’ checking messages rather than processing them; all of which tends to limit the practicable baud rate to 250kBaud. ‘Full CAN’

With Full CAN , all the messages are held in the CAN controller (82C200) and accessed by the CPU as dual-ported RAM. A cceptance filters mask out the irrelevant messages, using identifiers (ID), and presents the CPU with only those messages that are of interest. The CPU therefore has little work to do in handling the messages. For example, the CAN protocol has a special type of message that means “whoever holds this message, please send it now”. With Full CAN , the controller automatically listens for these messages and sends them only if it ha ppens to contain the requested message: if the message Id is masked out then no action is taken. In the basic CAN specification, it has a transmission rate of up to 250 kbaud whilst full CAN runs at 1MBaud

B.4 B.4.1

CAN Bus protoco l CAN Add ressing There are no source and destination addresses in a CAN message. Message identifiers are used to tag a message type, and each node decides, using bit-masks, which messages it retrieves from the bus – this process is called acceptance filtering, and different controller chips provide different levels of filtering sophistication. The Full CAN protocol allows for two lengths of message identifiers: Part A (standard CAN) allows for 11 message identification bits, which yield 2,032 different identifiers, whilst extended CAN (Part B) has 29 identification bits, producing 536,870,912 separate identifiers. Part A devices such as the 82C200 can only transmit and receive standard CAN protocol. If used on an extended CAN system in which 29 bit IDs are present, the device will cause errors and crash the entire network. The data-link layer defines the format and timing protocol with which the messages are transmitted. There are two descriptor bytes and up to eight data bytes. The descriptor bytes are particularly important as they define the priority and type of message being transmitted.

B-2

app-b.fm5 - Issue 2 Dated 21/08/97


Appendix B Controll er Area networking (CAN)

Figure B-2:

Parity Bits

B.5

Priorities handling The identifier field contains 11 bits and is used to identify the message as well as determining its bus access priority. Bits 7-10 of the identifier field define the message priority, with the highest priority having for the smallest identifier binary value. This means that messages can have a priority number between 0 (high priority) and 15 (low priority). Allocation of message priorities is a feature of the CAN bus that makes it particularly attractive for use within a strongly real time control environment.

B.5.1

Coping with message collisio ns As has been said, a fundamental CAN characteristic is that the lower the mess age number, the higher its priority - an identifier consisting entirely of zeros is therefore deemed to be the highest possible priority message. A node can start transmitting at any time when the bus is silent (idle), with the first part of a message transmitted being the message identifier field – most significant bit first. The node constantly monitors the CAN bus and if it is the only node currently transmitting it will receive back the message bit-by-bit as it sends it. The bus has the property that if any node transmits a ‘0’ (called a dominant bit) then all nodes read back a zero. Thus if two nodes begin to transmit simultaneously, the first source to send a zero, when the other source attempts one, gets control of the CAN bus and goes on to complete its message. Thus if a transmitter ‘A’ is overruled by a source ‘B’ sending a higher priority message, the fact that the message read back by ‘A’ does not match the message it attempted to send means that it will temporarily halt. Another attempt will subsequently be made to send it once the bus is released and returns to an ‘idle’ state. Any collisions will always be resolved because the CAN protocol requires that message identifiers are unique (which is why there are so many priorities). This functionality is part of layer 1 and is contained entirely within the 82C200 CAN controller device and is therefore transparent to the CAN user.

B.5.2

Interactive Commu nicati on It is possible to send a request for data to a s pecified address, and the remote transmission request (RTR) bit defines whether the message sent is a request for data or the actual data itself. The data-length code tells the receptor how many data

app-b.fm 5 - Issue 2 Dated 21/08/97

B-3

Ap pen di x B Controller A rea networking (CAN)


bytes the message contains. In the case of data requests, no data bytes follow and therefore the data-length code has no direct relation to the number of data bytes. The maximum number of nodes on a CAN bus is 32. The limit of messages per second ranges from about 2000 to about 5000 on a bus with 250kbaud transmission rate, depending on the number of bytes per message.

B.6

The Physical Layer CAN can use a number of physical media such as twisted wi re-pairs, fibre-optics etc. The commonest method is the former. Signalling is carried out using differential voltages and it is from this that CAN derives much of its noise immunity and fault tolerance. The two signal lines are termed ‘CAN_H’ and ‘CAN_L’ and, in the quiescent state, sit at 2.5V. A logic high (1) is denoted by CAN_H being above CAN_L and as such is termed a ‘dominant’ bit; whilst a logic low (0) has CAN_L above CAN_H, yielding a ‘recessive’ bit. The use of voltage differentials allows CAN networks to function when one of the signalling lines is open, or in extremely noisy environments. With a simple twist ed pair, the differential CAN inputs effectively cancel out noise, provided it is within the common mode range.

B-4

app-b.fm5 - Issue 2 Dated 21/08/97

C:

Appendix C : PCB Layout diagrams

C.1

Overview This appendix contains layout diagrams for the major circuit boards fitted across the entire 7200 product range. The diagrams are highlighted to show the location of the configuration jumpers, indicator LEDs and variable resistors; the input/ output connectors are also identified.

Figure C-1 - Rectifier logic board Part Nº4520074A assembly Figure C-2 - Inverter logic board Part Nº 4530025T assembly (Post March 1997) Figure C-3 - Inverter logic board Part Nº 4530024S assembly (Post March 1997) Figure C-4 - UPS logic board Part Nº4550007H assembly (Post March 1997) Figure C-5 - UPS logic board Part Nº4550004E assembly (Pre March 1997) Figure C-6 - Static switch trigger PCB Part Nº 4542043Z (Post March 1997) Figure C-7 - Static switch trigger PCB Part Nº 4542041X (Pre March 1997) Figure C-8 - Operator Interface PCB Part Nº 4550005F assembly Figure C-9 - High voltage interface PCB Part Nº 4590054O assembly Figure C-5 - UPS logic board Part Nº4550004E assembly (Pre March 1997)

app-c.fm5 - Issue 3 Dated 09/11/98

C-1

Ap pen di x C PCB Layout Diagrams


Figure C-1: Rectifier logic board Part N º4520074A assembly R22 Manual DC voltage Adj (10-500V) R21 Battery float voltage Adj (200 - 500V) R20 Battery boost voltage Adj (200 - 500V) R19 Battery test voltage Adj (0 - 550V)

X7 = 2 - 3

X6 = 1 - 2

H9 (R) Input undervoltage (-20%)

H4 (A) Rectifier in manual mode

H10 (R) External rectifier off (UPS logic)

H3 (G) Rectifier in float mode H2 (G) Rectifier in boost mode

H8 (R) Incorrect phase rotation on rectifier input

H1 (A) Rectifier under battery test mode

H7 (R) PCB power supply failure

R17 Rectifier current limit Adjust H6 (R) Rectifier current limit active R18 Battery current limit Adjust H5 (G) Battery current limit active R121 Battery voltage compensation Adj. w.r.t. to temperature 2.98 volts at X5 pin1 = 25° C

X10 = 2 - 3

X5 = 1 - 2 X13 = 0v = gnd

X12 = 0v = gnd

C-2

X9 = 0 - 5

X8 = Test points

app-c.fm 5 - Issue 3 Dated 09/11/98


Appendix C PCB Layout Diagrams

Figure C-2: Inverter logic board Part Nº 4530025T assembly (Post March 1997) R241 Amplitude of Tri-wave

R27 Tri-wave Amplitude measurement

R247 φ displacement Adj Inv to Mains

R242 Inv 3ph volts adj.

R243 Man inv volts Adj. (clockwise = min.) H1(G) 380v operation

X15 0 - 1 2400 Hz switching

X6 Aux Inv Logic PCB

H2(G) 400v operation H3(G) 415v operation H4(A) Man operation H11(R) = PCB power supply fail H12(R) = Inv off µP

Test Point X8

H13(R) = Ribbon cable block H14(R) = Overload 150%

R248 150% Inv I Limit (0.6V @ X10 pin 4)

H5(R) = R + sat H6(R) = R – sat Test Point X10

H7(R) = S+ sat H8(R) = S– sat H9(R) = T + sat H10(R) = T – sat

X1 X2 X3 To Base Drive PCBs X18 OV = gnd X17 OV = gnd

R245 Volts C-N Adj

X16 0-1 0-2

= 6 pulse Inv I feedback

R244 Volts B-N Adj


Test Point X9

X4 To UPS Logic PCBs

X12 1-2 0-1(closed)=temp enable 0-2(open) =Ribbon cable enable

R246 Volts A - N adjustment

C-3



Figure C-3: Inverter logic board Part Nº 4530024S assembly (Post March 1997)

R241 Amplitude of Tri-wave

R246 150% Inv I limit (0.6v @ X10 pin4)

Test Point X11

R247 φ displacement Adj Inv to Mains

X15 0 - 1 2400 Hz switching

H5(R) = R + sat H6(R) = R – sat

Test Point X10

H7(R) = S+ sat H8(R) = S– sat Test Point X8

H11(R) = PCB power supply fail

Test Point X9

H12(R) = Inv off µP H13(R) = Ribbon cable block H14(R) = Overload 150% X13 2-3 Temp enable X12 1-2 Ribbon cable enable H9(R) = T + sat H10(R) = T – sat

R244 Volts B-N Adj

R242 Inv volts ref. set R243 Man inv volts Adj. (clockwise = min.)

R245 Volts C-N Adj

H1(G) 380v operation H2(G) 400v operation H3(G) 415v operation H4(A) Man operation X16 0-1 0-2

= 6 pulse Inv I feedback

C-4

X18 OV = gnd

X14 Not Used

X17 OV = gnd




Figure C-4: UPS logic board Part Nº4550007H assembly (Post March 1997) t t t t a a a a B B B B e n e n t t o o a a r m r m e m e m p o p o e e S C S C n 5 = = 6 = = o 3 2 3 i - - 3 2 - 3 y t r X 1 2 X 1 2 a a l e p p s o i d l e a 2 d 1 o m H C r o & r n o = 1 1 r r 1 H E 0

e r d r a a w d d r n a a t H S = t = d e s n e e e s o R p l c o 8 2 X

t 1 s u n j i p d a t 0 l 2 o V @ 5 9 0 2 R

l i a r y l t 5 s p 4 u p V j u d s e c e a r n d t e o l e r n o w f A V o e 5 P e r . @ 2 = s 2 P 1 5 2 - µ 2 4 1 R V 0 2 X

y l p p d u s l e r b e a w n o e P r o = t i n n e o p m o 9 2 X

y a l p s d i e D l = b a 2 - n 1 e 6 1 X

a t a d e v a s l i a f y l p p u s r e w o P = 3 2 = 7 1 X

F F O / N O t 3 c e Q R

d e t t i F s k n i L 2 1 O X N

3 2 = 5 2 X 3 2 = 5 1 X

F F O / N O 2 v n Q I

F F O / N O s s a 1 p y Q B

V 0 = 8 n i p 8 1 X l l e e l l u a r d a o P m e & l g 1 i n = + 1 S 4 2 3 3 - X 1 2

S . P 2 r - a 1 d = n e 3 l 3 a X C

: t n e r r u e r g N c a O e l v t T O o T : v U p r e B m v e O T t E r C S e v D E O ; R r O 1 o P S F E

d r a d n a t s = n e p o e d r d i a d r d r a n r e d t a n S v a o t r S = d o = d w e n s s e l o s p a P O C = = = 4 8 2 - - 1 3 7 = 6 2 X

r e g r a h c y r e t ) t r a e b b l ) m a e v A r i ( n t e c t 8 n A H I (

l a n r r e e t n g r i a e h l b c a y n r e e t = t a d b e 4 n e 1 k p n 1 3 i X o X L


d e l b a n e M A R = 3 3 1 X 2

d e l d b e a s n u e t o M n A = R n 9 e 1 = 1 p 2 3 X o X 2

d d e e l l b b a a n n e e M M O O R R P P E E = 3 = 2 2 2 - 2 3 X 1 X 2

d e l b a n e M A R = 4 3 : 4 2 2 X 1

d e l b a n e 5 8 4 S R = d e 2 k n 3 i X L

C-5



Figure C-5: UPS logic board Part Nº4550004E assembly (Pre March 1997) e r d r a a w d d n r a a H t S = t = d e s n e e e s o R p l c o 8 2 X

n o i t y a a r l e p s p i o d l e 2 d a 1 o m H C r o & r n o = 1 1 r r 1 H E 0

1 t s n j i u p d 0 a t 2 l X o V @ 5 9 0 2 R

l i a r y l 5 t p 4 s p u V j u d s e c e a r n d t e e o l r n o w f A V o e 5 P e r . @ 2 = s 2 P 1 5 2 2 4 1 µ R V 0 2 X

y l p p d u s l e r b e a w n o e P r o = t i n n e o p m o 9 2 X

y a l p s d i e D l b = a n 2 - e 1 6 1 X

a t a d e v a s l i a f y l p p u s r e w o P = 3 2 = 7 1 X 4 3 = 6 2 X

F F O / N O t c 3 e Q R

n o i t c e t o r p d r o w s s a P = 8 7

3 2 = 5 2 X F F O / N O 2 v n Q I

3 2 = 5 1 X

F F O / N O s s a 1 p y Q B

V 0 = 8 n i p 8 1 X

N ; O d t s T a l T l o o U r v r B e v e T O v o E ; C S p D E m ; R t e O 1 / o P S ( E

d e l n b e a p n e o 2 = 3 2 1 1 S X R

C-6

r e g r a h c y r e t t a b l ) a ) e n i v R ( r t e c 8 t n A H I (

l a n r e r e t n g r i a e h l b c a y n r e e t = t a d b e 1 k n 3 i X L

4 n 1 e p X o

d d e l e l b d b a e a n s n e u e t M o M A n A R = R = = 3 3 9 n e 1 - 1 p 1 3 2 X 2 X o X 2

d d e e l l b b a a n n e e M M O O R R P P E E = = 2 2 3 3 2 - 2 X 1 X 2

d e l b a n e M A R = 4 3 : 4 2 2 X 1

d e l b a n e 5 8 4 S R = d e 2 k n 3 i X L




C:

Figure C-6: Static switch trigger PCB Part Nº 4542043Z (Post March 1997)

SCR Trigger Leads

X14 = 0v = gnd

X11 = 0 - 3 closed = 0 - 5 closed

N/A

To UPS Logic X5

Contactor Aux Feedback

APP-C1.FM5 - Issue 2 Dated 21/08/97

DC To contactor K1 DC feed for contactor K1

C-7



Figure C-7: Static switch trigger PCB Part Nº 4542041X (Pre March 1997)

SCR Trigger Leads

X14 = 0v = gnd

X12 = 0 - 3

X11 = 1 - 2

N/A To contactor

To UPS Logic X5

Contactor Aux Feedback

C-8

DC feed for contactor




Figure C-8: Operator Interface PCB Part Nº 4550005F assembly n n e e p p o o = = 4 9 1 1 X X

3 2 = 3 2 X

2 1 = 5 1 X

3 2 = 2 1 X

3 2 = 8 1 X

n e p o = 6 2 X

3 2 = 3 1 X

A / N

K C O y A l / C p D p u ) l a s n G r r e ( e w 1 t n o H I p

A / N

n e p o = 1 1 X

4 3 : 2 1 = 7 1 X

3 2 = 6 1 X

r t o e n k i p c 9 o s 2 5 3 8 2 4 4 S S X R R

t s a r t n o C t = s u 1 j 2 d R A

2 1 = 5 2 X

y a l p s i d o T = 1 X

t e k c o s 2 i 3 n 2 p S 5 R 2 n = i 8 a X M

t u p n 4 i y X l c p i p g o u s l r S e P w U o o P t

2 1 = 4 2 X

c s i g u o b l S N P A U C o 6 T X


x u a s u b N A C A / N 3 X

3 2 = 1 2 X

3 2 = 2 2 X

2 1 = 0 2 X

t e k c 2 o 3 s 2 i n S p R 9 = x 5 u X A

C-9



Figure C-9: High voltage interface PCB Part Nº 4590054O assembly X13 : Inverter heat-sink 12 : Transformer ambient temperature x11 Output temperature x10 : Input temperature

X31 to X40 : CT burden setti

8 : Battery breaker & EPOx9 : Battery temperature

7 : Manual isolation 1 - Q4

x14: N/A x15 : Batt Fus

x16 : N/A x17 : N/A 6 : Bypass volts x18 : Rectifier

x19 : I out C 5 : Inverter volts x20 : I out B

x21 : I out A

x22 : I Batt

: Critical Bus volts

x23 : Inv A

ectifier input volts

x24 : Inv B

x25 : Inv C

: Battery volts x26 : IDC 1

x27 : IDC 2

x1 to UPS logic PCB

C-10




Figure C-10: Parallel logic PCB Part Nº 4520075B

2 8 3 - X 8 X @ t s @ j u t d s a u j d y a c n t e l u o v q 0 e r 0 . F 4 = = 8 0 1 2 R R

n n o i o i t t a r a r e e p p o o z z H H 0 0 6 5 = = 7 2 - 3 X 1 2

d n u o r g e u g o l a n A = 0 1 X

w ) w ) e c l e c l s e e t s S S / w z s a / z o F H l s H 1 . = 2 . = 0 d 0 ( ( e n e s e 1 o t 1 e p t l X o a r c a r

t s u j d a ( r o r r e l e l l 9 a 1 r a r R P ) V e V 0 0 w 9 . 2 . o 5 l 6 8 = = 6 V R V 0 r 0 8 0 o f 3 4

) r e w o l ( 8 6 R

) h g i h ( K O O C c V G t n y y n S i o l c p a n d e t u V n s n r u q e t e e 0 A o r T r 0 . / n = I F 4 N G 8 = = = = = X 1 2 3 4 5

d e s o l c 4 1 X 0

d n u o r g l a t i g 9 i X D

d d d e s e s e s o l o o l c c l c 5 1 - 2 - 3 X 0 0 0

e l u d o m r e h t o n o 2 X o T e l u d o m r e h t o n o 3 X o T

c i g o l S P U o T

) w o l ( ) w d l o e ( l b d ) a e l w n e o e l l l e a t ( r n p a r a i o h o l s p p o t r t i e i f s n n i e t e r T O r c u e = C C R 2 V 1 = = = X 1 2 3

C S C S S e y v r ) M S n i y e o t r t ) 1 i n M i c t i t t e + a t a 1 l r i n a t r u b o r e e y ( a t c y b d m e C ( c t p o t n i a o o a c l a t n r S C d r d r t r d m o n d c a a a a S a e t a t S n p m p d M S d d o s c n u a m e n m n n o e r T d c o s t a a a o o M c o t t e r = c = s N = s s N = n = = d = d = = d = = = d = d n e n e n e n n n e n e s n s e s e s e e s o e o e o e o e o p l p l p p l p p p l p l o c o c o o c o o o c o c 6 1 X 0

2 0

3 - 4 0 0

5 - 6 - 7 0 0 0


8 0

) f f O ( ) t c e l e s ( r o r r e l e ) l d l a e r r ( a 1 P H =

) f f O ( r o r r e e l b a c l e ) l d l a e r r ( a 2 P H =

) f f O ( e v i t c a e d ) o n m e e r e v g l a ( 3 S H =

n o m m o c n e e r c s l e l l a r a P = 3 3 1 X 2

C-11


C-12



D:

Appendix D : PCB link selection

D.1

Introduction The tables in this appendix provide details of the configuration jumpers fitted to the various control printed circuit boards, and indicates their “default” settings. Layout diagrams are provided in Appendix C which give details of the links’ exact location.

D.2

Rectif ier Logic PCB Part Nº 4520074A. 30 to 60kVA Table D-1: Rectifier logic board jumper link position

Jumper

Link Position

X5

1-2

Disable battery temperature/voltage compensation (Standard)

2 - 3

Enable battery temperature/voltage compensation

1-2

Increased DC regulation speed for units below 60kVA

2 - 3

Decreased DC regulation speed for units above 80kVA

1-2

Fast walk-in: 1 Second

2-3

Slow walk-in: 5 Seconds

0-1

open

0-2

open

0 - 1

closed

0-2

open

0 - 1

open

0-2

closed

0 - 1

closed

0-2

closed

0-3

closed

Reduced input current limit forced on

open

(Standard)

closed

Rectifier forced on - Ignore UPS Logic

open

UPS Logic control enabled (Standard)

open

Disable driver IC - D6

closed

Enable driver IC - D6 (Standard)

X6

X7

X9

Function

Rectifier in Auto mode (Standard)

Rectifier in Float mode

Rectifier in Boost mode

Rectifier in ‘Test’ mode

0-4

0-5

X10

Ap p-d .fm 5 - Iss ue 2 Dated 21/08/97

1-2

Enable rectifier temperature monitor

2-3

Disable rectifier temperature monitor (Standard)

D-1

Ap pen di x D PCB Link Selection

D.3


UPS Logi c PCB Part Nº4550007H. 30 - 60kVA Table D-2: UPS logic board jumper link positions Jumper

X12

Position

Function

Open

(Standard)

1 - 2

Not Required

3 - 4

Not Required

1 - 2

EPROM Enable

2-3

RAM Enable (Standard)

1 - 2

Not Required

3 - 4

Not Required

5-6

Not Required

7-8

Not Required

1-2

PLL option with

CAP IN

2-3

PLL option with

FIN AUX

Open

CAN Bus to display disabled

1-2

CAN Bus to display enabled (Standard)

1-2

ALE enable data save

2-3

Power supply fail enable data save (Standard)

1-2

EPROM II enable (not required)

2-3

RAM II enable (not required)

1-2

+5V PCB enables microprocessor ref. For VA calculations (Standard)

2-3

V ref. enables microprocessor ref. For VA calculations

1-2

Not Required

2-3

RAM enable (Standard)

1-2

EPROM enable (Standard)

2-3

Not Required

1-2

Not Required

2-3

EPROM enable (Standard)

3-4

Not Required

4-5

Not Required

X13

y n e l n p o o y g l n a i t s m e r o T n

X14

X15 (Standard)

X16

X17

X19

X20

X21

X22

X23

D-2



Jumper

Appendix D PCB Lin k Selection

Position

Function

1-2


2-3

EPROM enable (not required)

3-4


4-5

EPROM enable (not required)

1-2

Manual reset of output buffers

2-3

Microprocessor reset of output buffers (Standard)

1-2

OPEN = Inverter operation in ‘Auto’ mode (Standard) CLOSED = Inverter operation in ‘Manual’ mode

3-4

CLOSED = Inverter voltage error lockout (10s) enabled (Standard) OPEN = Inverter voltage error lockout (10s) disabled

5-6

CLOSED = Reset event history buffer to zero OPEN = Event history buffer enabled (Standard)

7-8

OPEN = Password security enabled CLOSED = Password security disabled (Standard)

Open

Power up reset enabled (Standard)

X24

X25

X26

X28 Closed

Power up reset disabled

Open

2.5V power supply monitor enabled (Standard)

1-2

2.5V power supply monitor disabled

Open

Internal battery disabled

1-2

Internal battery installed and charger enabled (Standard)

Open

RS485 port disabled

1-2

RS485 port enabled (Standard)

X29

X31

X32 1 -2

Calender IC supply from VRAM (Standard)

2 -3

Calender IC supply from internal battery

1 -2

G.V.C.O. to inverter logic = parallel module

2 -3

Micro V.C.O. to inverter logic = single module

1 -2

Seperate battery per module (parallel system)

2- 3

Common battery (parallel system)

1 -2

Seperate battery per module (parallel system)

2- 3

Common battery (parallel system)

X33

X34

X35

X36


D-3


D.4


Inverter Lo gi c PCB Part Nº4530025T. 30 - 60kVA Table D-3: Inverter logic board jumper link positions Jumper

X12

X15

X16

D.5

Position

Function

0 - 1

Open= Test inverter over-temperature sensors

0 - 1

Closed = Enable Inverter over-temperature sensors (Standard)

0 - 2

Open= Enable ribbon cable detector (Standard)

0-2

Closed = Disable ribbon cable detector

0 - 3 0-4

Closed = Voltage select override. Enables manual inverter volts Adj by R243

0-5

Frequency select override

0-6

Force the Inverter ON => ignore all blocks

0-7

Ignore Inverter ‘On Load’ signal

0 - 1

2400 Hz switching frequency (Standard)

0 - 2

4800 Hz switching frequency

0-1 0-2


0-5


0-1 0-2

6 pulse Inverter current feedback (Standard)

0-3

12 pulse Inverter current feedback

d r a y d l n n a O t g S n = i t s n e e T p O

Operator Lo gic Board Part Nº 4550005F 30-60 kVA Table D-4: Operator Logic Board jumper link position Jumper

Position Open

Function +5v enable main CPU (Standard)

X11 Closed

ALE enable main CPU

1 - 2

Main CPU enable EPROM

2-3

+5v enable EPROM (Standard)

1 - 2

Main CPU enable RAM

2-3

+5v enable RAM (Standard)

X12

X13

D-4



Jumper


Position

Function

1 - 2

Not Required

2-3

Not Required

1-2

Main CPU enable EPROM (Standard)

2-3

Not Required

1-2

Not Required

2-3

Main CPU enable EPROM (Standard)

3-4

Not Required

4-5

Not Required

1-2

Write to RAM enable (Standard)

2-3

Not Required

3-4

Main CPU enable RAM (Standard)

4-5

Not Required

1-2

Not Required

2-3

Main CPU enable RAM (Standard)

1-2

Not Required

2-3

Not Required

1-2

Read/Write RS232 enable (Standard)

2-3

Read/Write RS485 enable

1-2

Enable port x4 for RS485

2-3

Enable port x4 for RS232 (Standard)

1-2

Enable port x4 for RS485

2-3

Enable port x4 for RS232 (Standard)

1-2

Inhibit buzzer

2-3

Enable buzzer (Standard)

1-2

Enable CAN bus to UPS logic (Standard)

2-3

Disable CAN bus to UPS logic

1-2

Enable RS485 bus to port x4 (Standard)

2-3

Disable RS485 bus to port x4

Open

+5v power supply reset enabled (Standard)

X14

Testing Only Open = Standard

X15

X16

X17

X18

X19

RAM extension (Normally open)

X20

X21

X22

X23

X24

X25

X26 Closed


+5v power supply reset disabled

D-5


D.6


Static Switch Driver PCB Part Nº 4542043Z 30-60 kVA Table D-5: Static Switch Driver board jumper link position Jumper

x11

Position 0 - 1

open

0-1

closed

0 - 2

open

0-2

closed

0 - 3

open

0-3

closed

0-4

N/A

Not used

0-5

open

Test static switch temperature monitor

0-5

D.7

Function

closed

Enable load on inverter command (Standard) Disable load on inverter command Enable load on bypass command(Standard) Disable load on bypass command Disables bypass fire command Enable bypass fire command (Standard)

Inhibit static switch temperature monitor (standard)

High Vol tage Int erface PCB Part Nº 4590054O 30-60kVA Table D-6: High Voltage Interface Board jumper link position.

D.8

D-6

Jumper

Position

—

0-1

X31

0-2

X31: X32: X33: X34: X35: X37: X38: X39: X40

0-3

—

0-1

X31: X32: X33: X34

0-2

X35: X36: X37: X38: X39: X40

0-3

—

0-1

—

0-2

X31: X32: X33: X34: X35: X36: X37: X38: X39: X40

0-3

Function

30 kVA CT burden selection



Parallel Log ic PCB Part Nº 4520075B



Jumper

Position 0 - 1

X4

0 - 2 to 0-8 0 - 1 (1st Unit)

0 - 2 (2nd Unit)

X5

0 - 3 (3rd Unit)

0 - 4 (4th Unit)

0 - 5 (5th Unit)

0-1

0-2

0-3

X6

0-4

Priority selector disabled

closed

Priority selector enabled for ≥ 1 module (standard 1+1)

open

Priority selector for ≥ 2 modules (multi module only) Link combination sets logic for number of units required open = standard for 1+1

open closed (standard) open closed (standard) open closed (standard)

Link combination sets logic for number of units operating For 1+1 operation links 0 - 1, 0 - 2, 0 - 3 a re closed.

open (standard) closed open (standard) closed open

1 + 1 redundancy (standard)

closed

1 + 1 capacity

open

Common battery for all UPS modules

closed

Separate battery for each UPS module (standard)

open

Priority selector enables parallel shutdown (standard)

closed

Priority selector disables parallel shutdown

open

No MSSC installed (1 + 1) (standard)

closed

MSSC installed (enables control for multi modules)

0-6

N/A open

No contactor in MSSC (standard)

closed

Contactor in MSSC

open

Normal operation

closed

Test mode active

1-2

60 Hz operation

2-3

50 Hz operation (standard)

X11

X13

open

N/A

0-8

X7

Function

0-5

0-7


open

G.V.C.O. Slow slew rate = 0.1 Hz/Second (standard)

closed

G.V.C.O. Fast slew rate = 0.2 Hz/Second

1-2

Parallel cable screen earthed

2-3

Parallel cable screen not earthed (standard)


D-7


D.9


DC – DC power supp ly PCB Part Nº 4503028K Table D-7: DC-DC power Supply Board link position Soldered Link

D-8

Position

Function

CV1

Closed

Enables the input voltage 260V – 600V

CV2

Closed

Enables input under voltage protection


E:

Appendix E : Specification

MECHA NICA L CHA RA CTERISTICS

Model kVA Ratin g

UNITS 30

40

60

Height

mm

1400

Width

mm

710

Depth

mm

800

Weight

kg

Colour (2 tone)

–

RAL 7001

Protection grade

–

With enclosure open or shut = IP20

Ventilation

–

assisted by internal intake fans

480

m3/h

Airflow Cable entry

–

Environmental

480

9600

620

960

Βοττοµ

Model kVA Ratin g

UNITS 30

Operating temperature

540

40

60

°C

0 to +40

Maximum temperature for an 8 hour day

–

40°C derate by 1.5% per °C between +40° and +50°

Mean temperature for a 24 hour day

–

35°C max

Relative humidity

–

<90% at 20°C

Altitude

–

<1000m a.s.l. (derate by 1% per 100m between 1000m and 2000m)

Storage temperature

°C

-25 to +70

dBA

56.0

EMC Standard

–

Designed to meet EN 50091 part 2

Safety standard

–

Designed to meet EN 50091 part 1

Acoustic noise at rated load (taken 1m from the apparatus according to ISO3746)

Ap p-e.f m5 - Is su e 2 Dated 21/08/97

E-1

Ap pen di x E Specification


Model kVA Ratin g INPUT RATINGS

UNITS

Power consumption at rated load while float charging the battery (400V)

kVA

Power consumption at rated load while boost charging the battery (400)

kVA

Input current level normal running (400V) Input current level full battery recharge (400V) Line voltage

30

40

60

32,8

43,5

64,9

41,0

54,3

81,1

47,0

63,0

94,0

59,0

78,0

117,0

A A V a.c.

380 - 400 - 415 3Ph + N

Current rating of neutral cable

A

1,4 times rated current

Permissible input voltage variation

%

+10 –15

Frequency

Hz

50 or 60

Permissible input frequency variation

%

± 5

Power walk-in

—

Progressive over 10 seconds

cos Φ

0,8

Power factor at 380/400/415 V with optional input filter fitted

>0,9

Model kVA Rating SYSTEM DATA

UNITS

30

40

60

Efficiency at 50% load

%

92,0

92,6

93,1

Efficiency at 100% load

%

91,5

92,0

92,5

Losses at rated load

kW

2,2

2,8

3,9

Losses with battery on boost charge

kW

2,8

3,4

4,5

Losses with no load

kW

0,9

1,1

1,3

E-2

App -e.fm 5 - Iss ue 2 Dated 21/08/97


Appendix E Specification

Model kVA Rating OUTPUT RATINGS

UNITS 30

Voltage

40

60

V a.c.

380/400/415 (preset on commissioning) 3 Ph N

Frequency

Hz

50 or 60 (presettable)

Power at 0,8pf

kVA

30

40

60

Power at 1,0pf

kW

24

32

48

A

43

57

87

Normal current at 0.8pf Overload ability at 0,8pf3 φ

—

1φ Current limiting short circuit (inverter) 150% rated current (3 phase) for

110% for 60 minutes 125% for 10 minutes 150% for 1 minute 200% for 30 seconds

— 5 Seconds 5 Seconds

220% rated current (1 phase) for Maximum permissible non linear load

%

100 with 3 : 1 crest factor

Voltage stability — steady state

%

± 1

Voltage stability — transient state

%

±5

Reset time to within ± 1%

ms

20

Frequency stability — synchronised

—

The output will synchronise with the input supply within ±0.5 Hz of nominal frequency (adjustable to ±2 Hz)

Frequency stability — unsynchronised

—

± 0,1% when the input supply frequency

is outside the synchronising range Phase voltage asymmetry — balanced load

—

± 1%

Phase voltage dissymmetry — 100% unbalanced load

—

± 2 %

Voltage phase shift — with balanced load

Angle o

120 ± 1

Voltage phase shift — with unbalanced load

Angle o

120 ± 1

—

1% typical 2% max

—

≤ 5% max

Hz/sec

0,1 to 1,0

Synchronised transfer to bypass

ms

0 approximately

Unsynchronised transfer to bypass

ms

20 approximately

Overload on bypass (without fuses)

—

10 x rated current for 100 ms

Output voltage distortion — linear load Output voltage distortion — non–linear load (3:1 crest factor) Maximum frequency slew rate


E-3

Ap pen di x E Specification


Model kVA Rating INTERMEDIATE DC RATINGS

UNITS 30

40

Voltage limits of inverter operation for 380V minimum maximum

Vdc


Vdc


Vdc

Number of lead-acid cells UPS 380 V

Nº

192

UPS 400 V

Nº

198

UPS 415 V

Nº

204

V d.c.

432

UPS 400 V

V d.c.

446

UPS 415 V

V d.c.

459

V d.c.

460

UPS 400 V

V d.c.

475

UPS 415 V

V d.c.

490

V d.c.

320

UPS 400 V

V d.c.

330

UPS 415 V

V d.c.

340

Absolute maximum voltage (manual charge) UPS 380 V

V d.c.

480

UPS 400 V

V d.c.

495

UPS 415 V

V d.c.

510

Rectifier output current rating

A

75

Voltage stability with rectifier

—

± 1%

Residual alternating voltage

—

≤ 1%

Battery charging cycle

—

Float charge voltage UPS 380 V

Boost charge voltage UPS 380 V

End of discharge voltage UPS 380 V

E-4

60

320 460 330 475 340 490

Characteristics to DIN 41772 I-U, boost-tofloating charge switching, with current measuring criterion plus control of charging time

App -e.fm 5 - Iss ue 2 Dated 21/08/97


Appendix E Specification

Model kVA Ratin g INTERMEDIATE DC RATINGS Maximum boost charge duration Charging current

UNITS

30

40

hours

60

1 - 15 hours ( selectable )

A

3 - 15

5 - 20

6 - 30

kW

25,7

34,1

50,8

Input current to inverter at minimum voltage

A

78

103

154

Efficiency of inverter @50% load

%

93,8

94,4

94,8

Efficiency of inverter @100% load

%

93,3

93,8

94,4

Inverter power at rated load

Model kVA Rating STATIC SWITCH CIRCUIT

UNITS

Overload from stand-by supply

A

current rating of neutral cable

A


30

40

60

10 times the rated current for 100ms 1,4 time the rated current.

E-5

Sect-13

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