Choose the correct answer 1. In Synchronous data dat a Transfer type both Transmitter and Receiver will operate in a) Same Clock pulse b) Different Clock pulse c) None of the above 2. The term PSW Program Pro gram Status word refers a) Accumulator & Flag register b) H and L register c) Accumulator & Instruction register d) B and C register 3. In 8085 the t he MAR latches the address from the program counter. A bit later the MAR applies this address to the t he --------where a read operations performed a) Memory address, ROM b) Memory address, RAM c) Memory address, PROM d) Memory address EPROM 4. In micro processors like 8080 and the 8085, the______ cycle may have from one to five machine cycle a) micro instruction b) source program c) instruction d) fetch cycle 5. A ²² is used to isolate a bit, it does this because that t hat ANI sets all other bits to Zero a) subroutine b) flag c) label d) mask 6. Interaction between a CPU and a peripheral device that takes place during and input output operation is known as a) handshaking b) flagging c) relocating d) subroutine 7. Addressing in which the instructions instructions contains the address of the data to the o perated on is known as a) immediate addressing b) implied addressing c) register addressing d) direct addressing 8. Restart is a special type of o f CALL in which a) the address is programmed but not built built into the hardware b) the address is programmed built into the hardware c) the address is not programmed but built into the hardware d) None of the above 9. 8085 has ____software restarts and _____ hardware restarts a) 10, 5 b) 8,4 c) 7,5 d) 6,6 10. Serial input data of 8085 can be loaded into bit 7 of the accumulator by a) executing a RIM instruction b) executing RST1 c) using TRAP d) None of the above 11. The address to which a software or hardware restart branches is known as a) vector location b) SID c) SOD d) TRAP 12. TRAP is ______whereas RST 7.5, RST 6.5, RST 5.5 are_______ a) maskable, non maskable b) maskable, maskable maskable c) non maskable, maskable, non maskable d) non maskable, maskable, maskable 13. Micro processor with a 16 bit address bus is used in a linear memory memory selection select ion configuration. Address bus lines are directly used as chip select s of memory chips with four memory chips. T he
maximum addressable memory space is a) 64K b) 16 K c) 8K
d) 4K
14. How many outputs are there in the output of a 10-bit D/A converter? a) 1000 b) 1023 c) 1024 d) 1224 15. The stack is a specialized temporary ?? access memory during ?.. and ?? instructions a) random, store, load b) random, push, load c) sequential, store, pop d) sequential, push, pop 16. The memory address of the last location of a 1K byte memory chip is given as OFBFFH what will be the address of the first location? a) OF817H b) OF818H c) OF8OOH d) OF801H 17. What is the direction of address bus? a) Unidirectional into microprocessors b) Unidirectional out of microprocessors c) Bi directional d) mixed direction is when lines into micro processor and some other out of micro processes. 18. What is the purpose of using ALE signal high? a) To latch low order address from bus to separate A0 to A7 b) To latch data D0 to D7 from bus go separate data bus c) To disable data bus latch 19. What is the purpose of READY signal? a) It is used to indicate to user that microprocessor is working and ready to use b) It is used to provide for proper WAIT states when microprocessor is communicating with slow peripheral device. c) It is used to provide for proper showing down of fast peripheral devices so as to communicate at micro processors speed. 20. What is the addressing mode used in instruction MOV M, C? a) Direct b) Indirect c) Indexed d) Immediate 21. In 8085 the direction of address bus is a) bidirectional b) unidirectional out of MP c) unidirectional in to MP d) none of the above 22. In 8085 the hardware interrupts are a)TRAP,RST 6.5,RST 7.5, RST 5.5 and INTR c)both a & b
b)RST 0, RST 1, RST 7 d)none of the above
23. In the TRAP, RST 7.5, RST 6.5, RST 5.5, which is having top priority a)TRAP b)RST 7.5 c)RST 6.5 d)RST 5.5 24. In 8085 the no . of software interrupts are a) 8 b)7 c)5 d)4 25. In the following interrupts which is the no n-vectored interrupt a)TRAP b)INTR c)RST 7.5 d)RST 6.5
26. Vector address for the TRAP interrupt is a)0024 H b)003C H c)0034 H d)002C H 27. In the following interrupt which is non- maskable interrupt (a) RST7.5 b) RST 6.5 c) TRAP d) INTR 28. Vector location Address for RST 0 Instruction is ____ (a) ooooH b) ooo8H c) oo1oH d)oo18H 29. In 8085 the Interrupt Acknowledge is represented by _______ a) INTA b)INTA c) INTR d) none of the above 30. The maximum number of I\O devices can be interfaced with 8085 in the I\O mapped I\O technique are a) 128 b) 256 c) 64 d) 1024 31. The maximum number of I\O devices which can be interfaced in the memory mapped I\O technique are a) 256 b) 128 c) 65536 d) 32768 32. The Instructions used for data transfer in I\O mapped I\O are a) IN, OUT b) IN, LDA add c) STA add d) None of the above 33. Number of Address lines required to interface 1KB of memory are a) 10 b)11 c) 12 d) 13 34. During processing the instructions, data, intermediate and final results are held in a) CPU b) ALU c) Primary memory d) Secondary memory Fill in the blanks 35. The No. of control lines are ²²36. The length of A register is ²²- bits 37. The length of program counter is ²²± bits 38. The length of stack pointer is ²²± bits 39. The length of status word is ²²- bits 40. The length of temporary register ²²- bits 41. The length of Data buffer register ²²- bits 42. The No. of flags are ²²43. The No. of interrupts are ²²44. The memory word addressing capability is ²² K 45. The No. of input output ports can be accessed by direct method ²²46. The No. of input output ports can be accessed by memory mapped method ²² K 47. If instruction RST is written in a program the program will jump ²²- location. 48. When TRAP interrupt is triggered program control is transferred to ²²- location. 49. The RST 5.5 interrupt service routine start from ²²± location. 50. In x 86 processors, EIP used for _______. 51. ______ used to read data directly from disc into computer memory. 52. A modem is connected with PC through ____. 53. The interface chip for 8085 and 8 bit ADC is _____.
54. The size of the cache memory is about ______usually. 55. In 8085 microprocessor, the number of address lines required is _____ bits. 56. After the execution of CALL instruction in the following program, the SP and PC contains Memory address Instructions 2000 LXI SP, 100 2003 PUSH H 2004 PUSH D 2005 CALL 2050 2006 POP H 2007 HLT 57. A QP contains 2 MHz crystal. @ It takes ____ time to execute 1000 cycles. 58. An I/O processor controls the flow of information between _______. 59. In 8085, an instruction used to set carry is ____ and it belongs to ____ group. 60. IF CS = A15 A14 A13 is used as chip select logic of a 4KB RAM in 8085 system, its memory range is ______ to _______. 61. Temporary register in 8085 is ____ number of bits. 62. The data bus and the address bus of 8085 QP are multiplexed since _____. 63. Microprocessor 8085 has 16 address lines so that the maximum number of memory addressed is _____. 64. LXI B, 90FF H means B is loaded with ____and C is loaded with ____. 65. In DMA operations, ___ and ____ signals are used. 66. Direct addressing is also called as _____. 67. EU stands for ______. 68. BIU stands for ______. Say True or False. a) An address space is set o f all possible addresses which can be generated by a microprocessor. b) A QP is generally interfaced with several memor y chips and I/O devices c) Multiprocessing operation permits efficient parallel processing at several levels. d) 8085 QP has inbuilt crystal and on-chip oscillator. e) When an instruction is called from memory, t he opcode of instruction is stored in instruction register. f) In 8085 QP, DMA controller allows direct access to memory to speed up data transfer. g) In two byte instructions, the first byte is opcode and second byte is address. h) x86 processors have a segment and offset addressing scheme. i) The accumulator drives ALU. j) The inputs to ALU are from Accumulator and Temporary register. k) In 8085 the higher order address bus is multiplexed with data bus. l) In 8085, the are active high signals.
