MOSFET DC Circuits Analysis 1. 2. 3. 4. 5. 6.
Assume an operation region (usually the saturation saturation region) Apply KVL at the gate source loop to find V GS Use V GS from step 2 to calculate I D Apply KVL at the drain source loop and use I D from step 3 to find V DS Check the validity of operation region assumptions by comparing V DS to V DSat Change assumptions and analyze again if required.
NOTES : An enhancement-mode device with V DS = V GS is always in saturation If we have a source resistance, we need to solve the equations in steps 2 and 3 together to find ID and VGS. If we include channel length modulation or we are in the triode region, we will solve the equations in steps 3 and 4 together If we include channel length modulation or we are in the triode region and we have a source resistance, we will solve the equations in steps 2, 3, and 4 together
Bias Analysis: Example 1 Assumption: Transistor is saturated, I G =I B =0 Analysis: First, simplify circuit, split V DD into two equal-valued sources and apply Thevenin transformation to find V EQ and R EQ for gate-bias voltage Problem: Find the Q-pt (I D , V DS ) Given: V TN =1V, K n =25μ A/V2 Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region
Bias Analysis: Example 1 (contd.) V 2 + 0.05V − 7.21 = 0 GS GS
∴V GS = −2.71V,+2.66V Since V GS
= V GS + I D RS V EQ
KVL at G-S loop, I D
=
K n ⎛⎜V
2 ⎝
−V TN ⎞⎟⎠ GS
∴V EQ =V GS +
K R n S ⎛⎜V
2
⎝
2
V ⎞⎟ − GS TN ⎠
2
⎛ ⎞ − ⎞⎛ ⎜ 25×10 6 ⎟⎜ 39×103 ⎟ ⎜ ⎟⎜ ⎟ ⎞2 ⎠⎝ ⎠ ⎛V +⎝ 4 =V ⎜ GS −1⎟ ⎝ ⎠ GS 2
and I D = 34.4 μ A
KVL at D-S loop, V = I ( R + RS ) +V DS DD D D
∴V DS = 6.08V V DS >V GS -V TN . Hence saturation
region assumption is correct. Q-pt: (34.4 A, 6.08 V) with V GS = 2.66 V
Bias Analysis: Example 2 Find the Q-point for the shown circuit with body effect using 2 F=0.6 V, V TO=1V, and =0.5V 1/2:
V = I R = 22,000 I D SB D S V = V + γ ( V + 2φ − 2φ ) TN TO F F SB ∴V TN = 1+ 0.5( V + 0.6 − 0.6 ) SB ⎛ ⎞ ⎜ 25 ×10 − 6 ⎟ ⎜ ⎟ ⎞2 ⎠ ⎛ − ⎜⎜V I ' = ⎝ V ⎟⎟ D TN ⎠ ⎝ GS 2
Iterative solution can be found by following steps: Estimate value of I D and use it to find V GS and V SB Use V SB to calculate V TN Find I D ’ using above 2 steps If I D ’ is not same as original I D estimate, start again.
KVL at G-S loop, V = V − I R = 6 − 22,000 I D GS EQ D S
Bias Analysis: Example 2 (contd.) The iteration sequence leads to I D = 88.0 μ A V = V − I ( R + RS ) = 10 − 40,000 I D = 6.48V DS DD D D
V DS >V GS -V TN . Hence saturation region assumption is correct.
Q-pt: (88.0 A, 6.48 V)
Bias Analysis: Example 3 Find the Q-point for the shown circuit?
− V = V GS DD
K R n D ⎛ ⎜V −V ⎞⎟2 ⎜ ⎟ 2 ⎝ GS TN ⎠
⎛ ⎞⎛ ⎞ ⎜ 2.6 ×10− 4 ⎟⎜104 ⎟ 2 ⎜ ⎟⎜ ⎟ ⎠⎝ ⎠ ⎛ ∴V GS = 3.3 − ⎝ −1 ⎞⎟⎟ ⎜⎜V ⎝ GS ⎠ 2
∴V GS = −0.769V,+2.00V Since V GS V GS -V TN . Hence saturation is saturated (since V DS = V GS ) region assumption is correct. Analysis: Q-pt: (130 A, 2.00 V) V DS
=V GS =V DD − I D R D
Bias Analysis: Example 4 ( Biasing in Triode Region) Find the Q-point for the shown circuit?
KVL at D-S loop, V DD
= I D R D +V DS
∴4 = 1600 I D +V DS ∴V DS = 2.19V But V DS
V μA 4 −V = 1600* 250 (4 −1− DS )V DS DS 2 2 V
∴V DS = 2.3V and I D =1.06 mA V DS
Q-pt:(1.06 mA, 2.3 V)
Bias Analysis: Example 5 Find the Q-point for the shown circuit?
15V − (220k Ω) I
D
−V SG = 0 2
∴15V − (220k Ω) 50 μA ⎛⎜⎝V SG − 2 ⎞⎟⎠ −V 2 V2
SG
=0
∴V SG = 0.369V,3.45V Since V SG = 0.369 V is less than |VTP|= 2 V, ∴V SG = 3.45 V I D = 52.5 μ A and V SG = 3.45 V
Assumption: I G =I B =0, transistor is saturated (since V DS = V GS ) Analysis: KVL at G-S loop,
V > V − V SD SG TP
Hence saturation assumption is correct. Q-pt: (52.5 A, 3.45 V)
MOSFET Circuits At DC
Fig. Ex6
Fig. Ex7
Fig. Ex8
Example 6: Design the circuit of Fig. Ex6 so that the transistor operates at I D =0.3 mA and V D =+1V. The NMOS transistor has V t = 1V, μ n C ox =20 μ A/V2, L =1 μm, and W =30μm. Example 7: Design the circuit in Fig. Ex7 to obtain a current I D of 0.4 mA. Find the value required for R and find the DC voltage V D . The NMOS transistor has V t = 0.5V, μ n C ox =20 μ A/V2, L =1 μm, and W =40μm. Example 8: Design the circuit in Fig. Ex8 to establish a drain voltage of 0.1 V. What is the effective resistance between drain and source at this operating point? Let V t = 1V and k n = 1 mA/V2
MOSFET Circuits At DC (contd.)
Fig. Ex9
Fig. Ex10
Example 9: Analyze the circuit shown in Fig. Ex9 to determine the voltages at all nodes and the currents through all branches. Let V t = 1V and k n ’ (W/L) = 1 mA/V2 Example 10: Design the circuit in Fig. Ex10 for the shown currents and voltages (i.e find R, (W/L) for each transistor). Let Vt=1 V, μ n C ox =20 μ A/V2
MOSFET As A Current Source
Ideal current source gives fixed output current regardless of the voltage across it. MOSFET behaves as as an ideal current source if biased in the pinch-off region (output current depends on terminal voltage).
NMOS Current Mirror I REF
=
'
⎛ ⎞ n ⎜W ⎟ ⎛V ⎜ ⎟ ⎜⎝ GS1 −VTN ⎜ 2 ⎝ L ⎟⎠ 1
K
⎞ ⎞2 ⎛1+ λ V ⎟ ⎜ ⎟ DS1 ⎠ ⎠ ⎝
M
I
O
=
'
⎛ ⎞ n ⎜W ⎟ ⎛V ⎜ ⎟ ⎜⎝ GS2 −V TN ⎜ 2 ⎝ L ⎟⎠ 2
K
⎞ ⎞2 ⎛1+ λ V ⎟ ⎜ ⎟ DS2 ⎠ ⎠ ⎝
M
Assumption: M 1 and M 2 have identical V TN , K n ’ , λ and W/L and are in saturation.
But V GS2 =V GS1 ⎛W ⎞ ⎛ ⎞ ⎛W ⎞ ⎜ L ⎟ ⎜1+ λ V ⎟ ⎟ ⎜ L ⎠M 2 ⎝ ⎠ ⎝ DS2 ⎝ ⎠ 2 M ∴ IO = I ≅ I ⎛ ⎞ ⎛W ⎞ REF ⎛W ⎞ REF ⎜1+ λ V ⎟ ⎜ L ⎟ ⎝ DS1 ⎠ ⎜ L ⎟ ⎝ ⎠ M 1 ⎝ ⎠M 1 Thus, output current mirrors reference current if V DS1 =V DS2 or λ = 0, and both transistors have the same (W/L)
NMOS Current Mirror: Example 11 Find the output current and the minimum output voltage v o to maintain the given current mirror in proper operation. Given data: I REF = 50 μ A , V O = 12 V, V TN = 1 V , K n ’ = 75 μ A/V2, λ = 0 V-1, (W/L)M1 = 2, (W/L)M2=10
Analysis:
V
GS
=VTN +
⎛ W ⎞ ⎜ ⎟ ⎜ ⎟ ∴ I O = I REF ⎝ ⎛ L ⎠ ⎞ M 2 ⎜ W ⎟ ⎜ ⎟ ⎝ L ⎠ M 1
= 250μA
2 I μ REF = 1V + 2(50 A) ⎛W ⎞ μA ′ ⎟ (1+ λ V 2*75 ) K n ⎜⎜ DS 1 ⎜ L ⎟⎟ V2 ⎝ ⎠
Hence, V omin =VGS – VTN = 0.82 V.
= 1.82V