HW4

BR

Wil iley ey/R /Raz azav avi/ i/ Fundamentals of Microelectronics

[Raz [R azav avi. i.cl clss v. 20 2006 06]]

June Ju ne 30 30,, 20 2007 07 at 13 13:4 :42 2

312 31 2 (1 (1))

Chap. Cha p. 6

312

Phys Ph ysics ics of MO MOS S Tran ransis sistor tors s

the input voltage. The transconductance of MOSFETs can be expressed by one of three equations in terms of the bias voltages and currents. Operation across different regions and/or with large swings exemplifies “large-signal behavior.” If the signal swings are sufficiently small, the MOSFET can be represented by a small-signal model consisting of a linear volt voltage-de age-dependen pendentt curre current nt sourc sourcee and an output resistance. The small-signal model is derived by making a small change in the voltage difference between two terminals while the the other voltages remain constant. The small-signal models of NMOS and PMOS devices are identical. NMOS and PMOS transistors are fabricated on the same substrate to create CMOS technology.

Problems In the fol follo lowin wing g pro proble blems, ms, unl unless ess oth otherw erwise ise sta stated ted,, ass assume ume , and V for NMOS devices devices and devices.

, V for PMOS

1. Two identical MOSFETs are placed in series as shown in Fig. 6.36. If both devices operate

M 1

Figure 6.36

M 2

W

W

L

L

M eq

as resistors resistors,, explain explain intu intuiti itively vely why this combi combinatio nation n is equi equivale valent nt to a single transis transistor tor,, What are the width and length of ?

.

experiencing pinch-off near the drain. Equation Equation (6.4) indicates indicates that the 2. Consider a MOSFET experiencing charge density and carrier velocity must change in opposite directions if the current remains constant. How can this relationship be interpreted at the pinch-off point, where the charge density approaches zero? 3. Calculate the total charge stored in the channel of an NMOS device if m, m, and V. Assume .

,

, 4. Referring to Fig. 6.11 and assuming that (a) Sketch the electron density in the channel as a function of . (b) Sketch the local resistance of the channel (per unit length) as a function of . 5. Assuming is constant, solve Eq. (6.7) to obtain an expression for and as a function of for different values of or .

. Plot both

6. The drain current of a MOSFET in the triode region is expressed as (6.77) Suppose the values of and tities by applying different values of

are unknown. Is it possible to determine these these quanand and measuring ?

NMOS OS de devi vice ce ca carr rrie iess 1 mA wi with th V and1.6mA wi witth 7. An NM V. If the device operates in the triode region, calculate and .

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Wiley/Razavi/ Fundamentals of Microelectronics

Sec. 6.7

[Razavi.cls v. 2006]

June 30, 2007 at 13:42

313 (1)

Chapter Summary

313

8. Compute the transconductance of a MOSFET operating in the triode region. Define for a constant . Explain why for . 9. An NMOS device operating with a small drain-source voltage serves as a resistor. If the supply voltage is 1.8 V, what is the minimum on-resistance that can be achieved with ? 10. We wish to use an NMOS transistor as a variable resistor with and at V. Explain why this is not possible.

at

V

11. For a MOS transistor biased in the triode region, we can define an incremental drain-source resistance as (6.78) Derive an expression for this quantity. 12. It is possible to define an “intrinsic time constant” for a MOSFET operating as a resistor: (6.79) where . Obtain an expression for must do to minimize the time constant. 13. In the circuit of Fig. 6.37,

and explain what the circuit designer

serves as an electronic switch. If

, determine

V G

V in

M 1

V out R L

Figure 6.37

such that the circuit attenuates the signal by only

. Assume

V and

.

14. In the circuit of Fig. 6.37, the input is a small sinusoid superimposed on a dc level: , where is on the order of a few millivolts. (a) For , obtain in terms of and other parameters so that (b) Repeat part (a) for V. Compare the results. 15. For an NMOS device, plot

as a function of

for different values of

.

.

16. In Fig. 6.17, explain why the peaks of the parabolas lie on a parabola themselves. 17. Advanced MOS devices do not follow the square-law behavior expressed by Eq. (6.17). A somewhat better approximation is: (6.80) where

is less than 2. Determine the transconductance of such a device.

18. For MOS devices with very short channel lengths, the square-law behavior is not valid, and we may instead write: (6.81) where

is a relatively constant velocity. Determine the transconductance of such a device.

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June 30, 2007 at 13:42

314 (1)

Chap. 6

314

M 1

0.5 V

2V 1.5 V

0.5 V

(a)

2V

M 1

1.5 V

0.5 V

(b)

M 1

1.5 V

Physics of MOS Transistors

1.5 V

0.5 V

(d)

0.5 V

M 1

0.5 V

M 1

0.5 V

0.5 V

(f)

M 1

M 1

1V

0.5 V

(g)

0.5 V

(c)

(e)

M 1

M 1

0.5 V

0.5 V

(h)

(i)

Figure 6.38

19. Determine the region of operation of

in each of the circuits shown in Fig. 6.38.


in each of the circuits shown in Fig. 6.39.

M 1

M 1

1V

1V

(a)

1V

(b)

1V

M 1

0.2 V

0.2 V

M 1

0.2 V

(c)

0.7 V

(d)

Figure 6.39

, i.e., 21. Two current sources realized by identical MOSFETs (Fig. 6.40) match to within . If V and V, what is the maximum tolerable value of ? 22. Assume , compute of saturation.

of

in Fig. 6.41 such that the device operates at the edge

23. Using the value of found in Problem 22, explain what happens if the gate oxide thickness is doubled due to a manufacturing error. 24. In the Fig. 6.42, what is the minimum allowable value of

if

must not enter the

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Sec. 6.7


June 30, 2007 at 13:42

315 (1)

Chapter Summary

315

I D1

I D2

M 1

M 2

V B

Figure 6.40

V DD =

1.8 V

1 kΩ

R D

M 1

1V

Figure 6.41

V DD =

1.8 V

500 Ω

R D

M 1 W =10 0.18 L

1V

Figure 6.42

triode region? Assume

.

25. In Fig. 6.43, derive a relationship among the circuit parameters that guarantees

operates

V DD R D

M 1 W L

Figure 6.43

at the edge of saturation. Assume 26. Compute the value of

for

27. Calculate the bias current of as a function of 28. Sketch to V. Also, of operation. 29. Assuming in Fig. 6.47.

. in Fig. 6.44 for a bias current of

in Fig. 6.45 if

. Assume

.

.

for the circuits shown in Fig. 6.46. Assume goes from 0 . Determine at what value of the device changes its region , and

V, calculate the drain current of

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June 30, 2007 at 13:42

316 (1)

Chap. 6

316

V DD =


1.8 V

M 1 R S

Figure 6.44

V DD R D M 1 W L

Figure 6.45

I X

I X

V DD =

I X

1.8 V

M 1 M 1 V X

1V

M 1

1V

(a)

V X

M 1

(b)

V X

(c)

I X

V X

(d)

Figure 6.46 V DD

1 kΩ

R D

M 1

Figure 6.47

30. In the circuit of Fig. 6.48, transistor at the edge of saturation?

and V DD = R D

. What value of

places the

1.8 V

5 kΩ M 1

V B

Figure 6.48

31. An NMOS device operating in saturation with . (a) Determine if mA. (b) Determine if V. (c) Determine if V.

must provide a transconductance of

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Sec. 6.7


June 30, 2007 at 13:42

317 (1)

Chapter Summary

317

32. Determine how the transconductance of a MOSFET (operating in saturation) changes if (a) is doubled but remains constant. (b) is doubled but remains constant. (c) is doubled but remains constant. (d) is doubled but remains constant. 33. If and circuits shown in Fig. 6.49. V DD =

, construct the small-signal model of each of the

1.8 V

V DD =

100 Ω

R D

V DD =

5 kΩ

R D

M 1

1V

1.8 V

1 mA

M 1

(a)

M 1

(b) V DD =

1.8 V

(c)

1.8 V

V DD =

M 1

1.8 V

M 1

0.5 mA

2 kΩ

(d)

(e)

Figure 6.49

. Derive an 34. The “intrinsic gain” of a MOSFET operating in saturation is defined as expression for and plot the result as a function of . Assume is constant. 35. Assuming a constant (a) as a function of (b) as a function of

, plot the intrinsic gain, if is constant. if is constant.

36. An NMOS device with Determine the required value of 37. Repeat Problem 36 for

if

, of a MOSFET

must provide a mA.

of 20 with

V.

.

38. Construct the small-signal model of the circuits depicted in Fig. 6.50. Assume all transistors operate in saturation and . 39. Determine the region of operation of

in each circuit shown in Fig. 6.51.


in each circuit shown in Fig. 6.52.

41. If

, what value of

42. With the value of 43. If in Fig. 6.54.

places

at the edge of saturation in Fig. 6.53?

obtained in Problem 41, what happens if and

as a function of 44. Sketch to V. Also, of operation.

, determine the operating point of

changes to

V?

in each circuit depicted

for the circuits shown in Fig. 6.55. Assume goes from 0 . Determine at what value of the device changes its region

45. Construct the small-signal model of each circuit shown in Fig. 6.56 if all of the transistors operate in saturation and .

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June 30, 2007 at 13:42

318 (1)

Chap. 6

318 V DD


V DD

R D

V DD

R D V out

R D V out

V in

M 2

V out V in

M 1

M 1

V B V in

M 2

M 1

(a)

M 2

(b)

(c) V DD

V DD V in

R D V out

M 1 V out M 2

V B

M 1

V in M 2

(d)

(e)

Figure 6.50

2V

M 1

2V

M 1

0.3 V

(a) Figure 6.51

(b)

0.3 V

1V

M 1

0.3 V

M 1

0.6 V

(c)

(d)

and operate in saturation and exhibit 46. Consider the circuit depicted in Fig. 6.57, where channel-length modulation coefficients and , respectively. (a) Construct the small-signal equivalent circuit and explain why and appear in “parallel.” (b) Determine the small-signal voltage gain of the circuit.

SPICE Problems In the following problems, use the MOS models and source/drain dimensions given in Appendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and , respectively. 47. For the circuit shown in Fig. 6.58, plot as a function of the sharp change in as exceeds a certain value.

for

mA. Explain

48. Plot the input/output characteristic of the stage shown in Fig. 6.59 for what value of does the slope (gain) reach a maximum? 49. For the arrangements shown in Fig. 6.60, plot as a function of 1.8 V. Can we say these two arrangements are equivalent?

as

V. At varies from 0 to

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Sec. 6.7


June 30, 2007 at 13:42

319 (1)

Chapter Summary

319

M 1

M 1

1.5 V

0.9 V

0.9

0.5 V

(a)

(b)

M 1

M 1

0.9 V

0.4 V

1V

0.9 V 0.4 V

(c)

Figure 6.52

(d)

V DD =

1.8 V

M 1

1V

2 kΩ

Figure 6.53 V DD =

1.8 V

V DD =

M 1

1.8 V

V DD =

1 kΩ

M 1

500 Ω

1 kΩ

(a)

M 1

(b)

(c)

Figure 6.54 V DD =

1.8 V

V DD =

M 1 V X

M 1

1V

I X

I X

(a) V DD =

(c)

Figure 6.55

V X

(b)

1.8 V I X

M 1 I X

1.8 V

M 1 V X

(d)

V X

1.8 V

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June 30, 2007 at 13:42

320 (1)

Chap. 6

320

Physics of MOS Transistors V in

V DD

V DD

R S V in

V in

V b

M 1

V out V out

M 1

R 1

R D

V out R D

M 2

M 2

(a)

R D

(b)

(c)

V DD V in

V DD R 2

M 1

V out V in

V out

M 1

R D

R 1

M 2 R 1

M 2

(d)

(e)

Figure 6.56 V DD M 2 V in

V out M 1

Figure 6.57

M 1

0.9 V

2 0.18

V X

I X

Figure 6.58

V DD =

1.8 V

500 Ω M 1 V in

Figure 6.59

M 1

V out

10 0.18

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Sec. 6.7


June 30, 2007 at 13:42

321 (1)

Chapter Summary

321 I X

M 1

0.9 V

5 0.36

I X M 1 V X

0.9 V M 2

(a)

Figure 6.60

5 0.36 5 0.36

(b)

V X

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June 30, 2007 at 13:42

322 (1)

Chap. 6

322


as a function of for the arrangement depicted in Fig. 6.61 as 50. Plot to 1.8 V. Can you explain the behavior of the circuit? I X M 1

0.9 V

5 0.18

M 1

5 0.18

V X

Figure 6.61

51. Repeat Problem 50 for the circuit illustrated in Fig. 6.62. V DD = M 1

1.8 V

5 0.18 I X

M 1

Figure 6.62

5 0.18

V X

varies from 0

HW4

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