9.7 Let R2 be the resistance seen looking into the collector of Q2 . Rout = ro1 + (1 + gm1 ro1 ) (rπ1 k R2 ) Note that this expressoin is maximized as R2 → ∞. This gives us Rout,max = ro1 + (1 + gm1 ro1 ) rπ1
9.9 1 VA βVA VT (Eq. 9.9) IC1 VT VA + βVT 1 VA βVT = IC1 VT βVA = IC1
Rout ≈
= βro This resembles Eq. (9.12) because the assumption that VA ≫ βVT can be equivalently expressed as VT VA ≫β IC IC ro ≫ rπ This is the same assumption used in arriving at Eq. (9.12).
9.12 ID = 0.5 mA Rout = ro1 + (1 + gm1 ro1 ) ro2 ! r 1 1 1 W = + 1 + 2 µn Cox ID λID L λID λID ≥ 50 kΩ λ ≤ 0.558 V−1
9.15 (a) VD1 = VDD − ID RD = 1.3 V > VG1 − VT H = Vb1 − VT H Vb1 < 1.7 V (b) Vb1 = 1.7 V VGS1 = Vb1 − VX s = VT H +
= 0.824 V VX = 0.876 V
2I D µn Cox
W L 1
9.16 (a) Looking down from the source of M1 , we see an equivalent resistance of Rout = gm1 ro1
1 gm2
k ro2
1 gm2
k ro2 . Thus, we have
(b) Rout = gm1 ro1 ro2 (c) Putting two transistors in parallel, their transconductances will add and their output resistances will be in parallel (i.e., we can treat M1 and M3 as a single transistor with gm = gm1 + gm3 and ro = ro1 k ro3 ). This can be seen from the small-signal model. Rout = (gm1 + gm3 ) (ro1 k ro3 ) ro2 (d) Let’s draw the small-signal model and apply a test source to find Rout . +
+
vgs1
gm1 vgs1
ro1
−
vgs2 −
gm2 vgs2
+ it
vt −
ro2
vgs1 vgs2 + vgs1 = gm1 vgs1 + ro2 ro1 vgs1 = gm2 ro2 vt − it ro2 vt + gm2 ro2 vt − it ro2 it = gm1 (gm2 ro2 vt − it ro2 ) + ro1 ro2 1 + gm2 ro2 it 1 + gm1 ro2 + = vt gm1 gm2 ro2 + ro1 ro1 it = gm2 vgs2 −
it (gm1 ro1 ro2 ) = vt (gm1 gm2 ro1 ro2 ) Rout =
1 vt = it gm2
9.17 ID = 0.5 mA Rout = ro1 + (1 + gm1 ro1 ) ro2 s ! W 1 1 1 = µp Cox ID + 1+ 2 λID L 1 λID λID
W L
1
= 40 kΩ W = = 8 L 2
9.20 (a) Gm = gm1 Rout =
1
k ro1
gm2
Av = −gm1
1 gm2
k ro1
(b) Gm = −gm2 Rout =
1
k ro2 k ro1
gm2
Av = gm2
1 gm2
k ro2 k ro1
(c) Let’s draw the small-signal model to find Gm . iout vin
rπ1
+ vπ1
gm1 vπ1
− RE
ro1
vin − vπ1 vπ1 + rπ1 RE vπ1 = vin + (iout − gm1 vπ1 ) ro1 vπ1 (1 + gm1 ro1 ) = vin + iout ro1 vin + iout ro1 vπ1 = 1 + gm1 ro1 vin + iout ro1 vin vin + iout ro1 − + iout = − rπ1 (1 + gm1 ro1 ) RE RE (1 + gm1 ro1 ) ro1 1 1 ro1 1 iout 1 + = vin − + − rπ1 (1 + gm1 ro1 ) RE (1 + gm1 ro1 ) RE rπ1 (1 + gm1 ro1 ) RE (1 + gm1 ro1 ) rπ1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 rπ1 rπ1 (1 + gm1 ro1 ) − RE − rπ1 iout = vin rπ1 RE (1 + gm1 ro1 ) rπ1 RE (1 + gm1 ro1 ) iout [rπ1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 rπ1 ] = vin [rπ1 (1 + gm1 ro1 ) − RE − rπ1 ] iout Gm = vin iout = −
rπ1 (1 + gm1 ro1 ) − RE − rπ1 rπ1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 rπ1 gm1 (if rπ1 , ro1 are large) ≈ 1 + gm1 RE = ro2 k [ro1 + (1 + gm1 ro1 ) (rπ1 k RE )] =
Rout
Av = −
rπ1 RE (1 + gm1 ro1 ) − RE − rπ1 {ro2 k [ro1 + (1 + gm1 ro1 ) (rπ1 k RE )]} rπ1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 rπ1
(d) Gm = gm2 Rout = ro2 k [ro1 + (1 + gm1 ro1 ) (rπ1 k RE )] Av = −gm2 {ro2 k [ro1 + (1 + gm1 ro1 ) (rπ1 k RE )]} (e) Let’s draw the small-signal model to find Gm . iout + vgs1
gm1 vgs1
− RS
vin
ro1
Since the gate and drain are both at AC ground, the dependent current source looks like a resistor with value 1/gm1 . Thus, we have: Gm =
1 iout =− 1 vin k ro1 RS + gm1
=−
1
RS +
ro1 1+gm1 ro1
1 + gm1 ro1 ro1 + RS + gm1 ro1 RS gm1 ≈− (if ro1 is large) 1 + gm1 RS = [ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ] = −
Rout
Av =
1 + gm1 ro1 {[ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]} ro1 + RS + gm1 ro1 RS
(f) We can use the result from part (c) to find Gm here. If we simply let rπ → ∞ (and obviously we replace the subscripts as appropriate) in the expression for Gm from part (c), we’ll get the result we need here. rπ2 RE (2 + gm2 ro2 ) − RE − rπ2 rπ2 RE (2 + gm2 ro2 ) + ro2 RE + ro2 rπ2 gm2 ro2 = ro2 + RE + gm2 ro2 RE gm2 ≈ (if ro2 is large) 1 + gm2 RE = [ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]
Gm = lim
rπ2 →∞
Rout
Av = −
gm2 ro2 {[ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]} ro2 + RE + gm2 ro2 RE
(g) Once again, we can use the result from part (c) to find Gm here (replacing subscripts as appropriate). rπ2 RE (1 + gm2 ro2 ) − RE − rπ2 rπ2 RE (1 + gm2 ro2 ) + ro2 RE + ro2 rπ2 gm2 ≈ (if rπ2 , ro2 are large) 1 + gm2 RE = RC k [ro2 + (1 + gm2 ro2 ) (rπ2 k RE )]
Gm =
Rout
Av = −
rπ2 RE (1 + gm2 ro2 ) − RE − rπ2 {RC k [ro2 + (1 + gm2 ro2 ) (rπ2 k RE )]} rπ2 RE (1 + gm2 ro2 ) + ro2 RE + ro2 rπ2
9.22 Av = −gm1 [ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 )] IC1 ≈ IC2 = I1
VA1 = VA2 = VA I1 VA VA βVT VA Av ≈ − + 1+ k VT I1 VT I1 I1 = −500
VA1 = VA2 = 0.618 V−1
9.23 (a) Although the output resistance of this stage is the same as that of a cascode, the transconductance of this stage is lower than that of a cascode stage. A cascode has Gm = gm , where as this stage m2 has Gm = 1+ggm2 ro1 . (b) Gm =
gm2 1 + gm2 ro1
Rout = ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 ) Av = −Gm Rout = −
gm2 [ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 )] 1 + gm2 ro1
9.24 Gm = −gm1 Rout = ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 ) Av = gm1 [ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 )]
9.25 (a) Gm = gm2
RP k rπ1 gm1 + RP k rπ1 1
Rout = ro1 + (1 + gm1 ro1 ) (rπ1 k ro2 k RP ) Av = −gm2
RP k rπ1 [ro1 + (1 + gm1 ro1 ) (rπ1 k ro2 k RP )] gm1 + RP k rπ1 1
(b) Gm = gm2 Rout = ro1 k RP + [1 + gm1 (ro1 k RP )] (rπ1 k ro2 ) Av = −gm2 {ro1 k RP + [1 + gm1 (ro1 k RP )] (rπ1 k ro2 )} (c) gm2 1 + gm2 RE = ro1 + (1 + gm1 ro1 ) [rπ1 k (ro2 + (1 + gm2 ro2 ) (rπ2 k RE ))]
Gm = Rout
Av = −
gm2 {ro1 + (1 + gm1 ro1 ) [rπ1 k (ro2 + (1 + gm2 ro2 ) (rπ2 k RE ))]} 1 + gm2 RE
(d) Gm = gm2 Rout = ro1 + (1 + gm1 ro1 ) (rπ1 k ro2 k ro3 ) Av = −gm2 [ro1 + (1 + gm1 ro1 ) (rπ1 k ro2 k ro3 )]
9.26 Av = −gm1 {[ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 )] k [ro3 + (1 + gm3 ro3 ) (rπ3 k ro4 )]} IC VA,N VA,P VA,N βN VT VA,N VA,P βP VT VA,P =− k + 1+ k + 1+ k VT IC VT IC IC IC VT IC IC i h i h VA,P VA,N VA,N VA,P VA,P VA,N βN VT βP VT k IC k IC IC + 1 + VT IC IC + 1 + VT IC IC i h i h =− V V V VA,P βN VT βP VT VT VA,N + 1 + VA,N + IA,P k A,N + 1 + VA,P IC VT IC IC IC k IC C T #" # " βN VT VA,N βP VT VA,P VA,P VA,N VA,P VA,N ” ” “ “ V VA,P βN VT βP VT IC + 1 + VT IC + 1 + VT 2 2 IC IC + A,N IC IC IC + IC IC # " # " =− VT V β V V β V V V V V N T A,N P T A,P A,P A,N A,P A,N ” + ” “ “ VA,N VA,P βN VT βP VT IC + 1 + VT IC + 1 + VT 2 2 IC
h
IC
+
IC
IC
IC
+
IC
ih i V βN VT VA,N βP VT VA,P VA,P 1 VA,N + 1 + VA,N V + 1 + 2 A,P β V +V V β V +V IC IC T N T A,N T P T A,P h i h i =− VT 1 VA,N + 1 + VA,N βN VT VA,N + 1 VA,P + 1 + VA,P βP VT VA,P IC VT βN VT +VA,N IC VT βP VT +VA,P h ih i VA,N VA,P βN VT VA,N βP VT VA,P V + 1 + V + 1 + A,N A,P VT βN VT +VA,N VT βP VT +VA,P 1 h i h i = − VA,N VA,P βN VT VA,N βP VT VA,P VT V + 1 + + V + 1 + A,N A,P VT βN VT +VA,N VT βP VT +VA,P
The result does not depend on the bias current.
9.28
|Av |
Av ≈ −gm1 gm2 ro1 ro2 (Eq. 9.69) s s 2 W W 1 =− 2 µn Cox ID 2 µn Cox ID L 1 L 2 λID s 2 W 1 W = −2µn Cox ID L 1 L 2 λID s 1 1 W W = −2µn Cox 2 ID λ L 1 L 2
ID
9.30 From Problem 28, we have 1 1 Av = −2µn Cox ID λ2
s
W L
1
W L
2
If we increase the transistor widths by a factor of N , we will get a new voltage gain A′v : s W W 1 1 ′ 2 N Av = −2µn Cox ID λ2 L 1 L 2 s 1 1 W W = −2N µn Cox 2 ID λ L 1 L 2 = N Av Thus, the gain increases by a factor of N .
9.31 From Problem 28, we have 1 1 Av = −2µn Cox ID λ2
s
W L
1
W L
2
If we decrease the transistor widths by a factor of N , we will get a new voltage gain A′v : s W W 1 1 1 ′ Av = −2µn Cox ID λ2 N 2 L 1 L 2 s 1 W 1 1 W = −2 µn Cox 2 N ID λ L 1 L 2 =
1 Av N
Thus, the gain decreases by a factor of N .
9.32 Gm = −gm2 Rout = ro2 k [ro3 + (1 + gm3 ro3 ) ro4 ] Av = gm2 {ro2 k [ro3 + (1 + gm3 ro3 ) ro4 ]}
9.33 Av = −gm1 {[ro2 + (1 + gm2 ro3 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]} = −500 s W gm1 = gm2 = 2 µn Cox ID L s W µp Cox ID gm3 = gm4 = 2 L 1 λn ID 1 = λp ID
ro1 = ro1 = ro3 = ro4
ID = 1.15 mA
9.34 (a) Gm = gm1 Rout = [(ro2 k RP ) + (1 + gm2 (ro2 k RP )) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ] Av = −gm1 {[(ro2 k RP ) + (1 + gm2 (ro2 k RP )) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]} (b) Gm = gm1
ro1 k RP gm2 + ro1 k RP 1
Rout = [ro2 + (1 + gm2 ro2 ) (ro1 k RP )] k [ro3 + (1 + gm3 ro3 ) ro4 ] Av = −gm1
ro1 k RP {[ro2 + (1 + gm2 ro2 ) (ro1 k RP )] k [ro3 + (1 + gm3 ro3 ) ro4 ]} gm2 + ro1 k RP 1
(c) Gm = gm5 Rout = [ro2 + (1 + gm2 ro2 ) (ro1 k ro5 )] k [ro3 + (1 + gm3 ro3 ) ro4 ] Av = −gm5 {[ro2 + (1 + gm2 ro2 ) (ro1 k ro5 )] k [ro3 + (1 + gm3 ro3 ) ro4 ]} (d) Gm = gm5 Rout = [ro2 + (1 + gm2 ro2 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) (ro4 k ro5 )] Av = −gm5 {[ro2 + (1 + gm2 ro2 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) (ro4 k ro5 )]}
9.36 2 1 R2 W I1 = µn Cox (Eq. 9.85) VDD − VT H 2 L R1 + R2 ∂I1 R2 R2 W = VDD − VT H µn Cox ∂VDD L R1 + R2 R1 + R2 =
R2 gm R1 + R2
∂I1 . Since VGS is Intuitively, we know that gm is the derivative of I1 with respect to VGS , or gm = ∂V GS ∂VGS is a linearly dependent on VDD by the relationship established by the voltage divider (meaning ∂V DD ∂I1 ∂I1 ∂VGS ∂I1 ∂VGS constant), we’d expect ∂VDD to also be proportional to gm , since ∂VDD = ∂VDD · ∂VGS = ∂VDD gm .
9.37 2 R2 (Eq. 9.85) VDD − VT H R1 + R2 R2 W = −µn Cox VDD − VT H L R1 + R2
1 W I1 = µn Cox 2 L ∂I1 ∂VT H
The sensitivity of I1 to VT H becomes a more serious issue at low supply voltages because as VDD becomes smaller with respect to VT H , VT H has more control over the sensitivity. When VDD is large enough, it dominates the last term of the expression, reducing the control of VT H over the sensitivity.
9.38 As long as VREF > 0, the circuit operates in negative feedback, so that V+ = V− = 0 V. VREF IC1 = IS1 e−V1 /VT = R 1 VREF V1 = −VT ln = VBE2 R1 IS1 If VREF > R1 IS1 , then we have VBE2 < 0, and IX = 0. If VREF < R1 IS1 , then we have: IX = IS2 e
−VT ln
“
VREF R1 IS1
” /VT
“ ” V − ln REF
R1 IS1 = IS2 e R1 IS1 = IS2 VREF
Thus, if VREF > R1 IS1 (which will typically be true, since IS1 is typically very small), then we get no output, i.e., IX = 0. When VREF < R1 IS1 , we get an inverse relationship between IX and VREF .
9.39 As long as VREF > 0, the circuit operates in negative feedback, so that V+ = V− = 0 V. VREF IC1 = IS1 e−V1 /VT = R 1 VREF V1 = −VT ln = −VBE2 R1 IS1 If VREF < R1 IS1 , then we have VBE2 < 0, and IX = 0. If VREF > R1 IS1 , then we have: V ln
“
VREF
R1 IS1 IX = IS2 e T VREF = IS2 R1 IS1 IS2 VREF = IS1 R1 IS2 = IC1 IS1
” /VT
Thus, if VREF < R1 IS1 , then we get no output, i.e., IX = 0. When VREF > R1 IS1 (which will typically be true, since IS1 is typically very small), we get a current mirror relationship between Q1 and Q2 (ensured by the op-amp). (with IX copying IC1 ), where the reference current for Q1 is VREF R1
9.46 (a) Icopy = 5IC,REF IREF = IC,REF + IB,REF + IB1 IC,REF Icopy = IC,REF + + β β IC,REF 5IC,REF = IC,REF + + β β 5 1 = IC,REF 1 + + β β Icopy 6 + β = 5 β β Icopy = 5IREF 6+β
(b) IC,REF 5 = IC,REF + IB,REF + IB1 IC,REF Icopy = IC,REF + + β β IC,REF IC,REF + = IC,REF + β 5β 1 1 = IC,REF 1 + + β 5β 6 + 5β = 5Icopy 5β IREF 5β = 6 + 5β 5
Icopy = IREF
Icopy
(c) 3 IC,REF 2 5 I2 = IC,REF 2 IREF = IC,REF + IB,REF + IB1 + IB2 IC,REF Icopy I2 = IC,REF + + + β β β 3IC,REF 5IC,REF IC,REF + + = IC,REF + β 2β 2β 3 5 1 + = IC,REF 1 + + β 2β 2β 2 10 + 2β = Icopy 3 2β 3 2β IREF Icopy = 10 + 2β 2 Icopy =
9.49 VGS,REF = VT H +
s
2IREF µn Cox W L
VGS1 = VGS,REF − I1 RP s 2IREF − I1 RP = VT H + µn Cox W L s 2IREF IREF RP − = VT H + 2 µn Cox W L !2 s W IREF 1 2IREF RP − I1 = µn Cox 2 L 2 µn Cox W L IREF s2 IREF IREF RP = − 2 µn Cox W L s s IREF 2IREF IREF RP = − W 2 µn Cox W µ n Cox L L s √ IREF = 2−1 µn Cox W L √ 2 2−1 RP = q IREF µn Cox W L =
s
2IREF µn Cox W L
Given this choice of RP , I1 does not change if the threshold voltages of the transistors change by the same amount ∆V . Looking at the expression for I1 in the derivation above, we can see that it has no dependence on VT H (note that RP does not depend on VT H either).
9.54 IC1 = 1 mA 1 + βn IE1 RE = IC1 RE = 0.5 V βn RE == 0.5 V RE = 495.05 Ω Rout,a = ro1 + (1 + gm1 ro1 ) (rπ1 k RE ) Rout,b
= 85.49 kΩ = ro1 + (1 + gm1 ro1 ) (rπ1 k ro2 ) = 334.53 kΩ
The output impedance of the circuit in Fig. 9.72(b) is significantly larger than the output impedance of the circuit in Fig. 9.72(a) (by a factor of about 4).
9.56 (a) Rout = ro1 + (1 + gm1 ro1 ) ro2 = 200 kΩ 1 ro1 = ro2 = λID r W gm1 = gm2 = 2 µn Cox ID L W W = = 1.6 L 1 L 2 (b) Vb2 = VGS2 = VT H + = 2.9 V
s
W L
2ID µn Cox
9.57 (a) Assume IC1 ≈ IC2 , since β ≫ 1. Av = −gm1 [ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 )] I1 gm1 = gm2 = VT VA ro1 = ro2 = I1 VT rπ1 = rπ2 = β I " 1 # β VIT1 VIA1 VA I1 VA + 1+ Av = − VT I1 VT β VIT + VIA 1 1 1 VA βVT VA =− VA + 1 + VT VT βVT + VA = −500
VA = 0.618 V (b) Vin = VBE1 = VT ln
I1 IS1
= 714 mV (c) Vb1 = VBE2 + VCE1 = VBE2 + 500 mV I1 + 500 mV = VT ln IS2 = 1.214 V
9.58 Assume all of the collector currents are the same, since β ≫ 1. P = IC VCC = 2 mW IC = 0.8 mA IC Vin = VT ln = 726 mV IS
Vb1 = VBE2 + VCE1 IC = VT ln + VBE1 − VBC1 IS = 1.252 V Vb3 = VCC − VT ln
IC IS
= 1.774 V
Vb2 = VCC − VEC4 − VEB3 = VCC − (VEB4 − VCB4 ) − VT ln
IC IS
= 1.248 V Av = −gm1 {[ro2 + (1 + gm2 ro2 ) (rπ2 k ro1 )] k [ro3 + (1 + gm3 ro3 ) (rπ3 k ro4 )]} = 4887
9.62 Rout = RC = 500 Ω IC RC = 20 Av = gm2 RC = VT IC = 1.04 mA P = (IC + IREF ) VCC = 3 mW IREF = 0.16 mA AE1 IC = IREF AE,REF AE1 = 6.5
AE,REF
AE,REF = AE AE1 = 6.5AE
9.63 Icopy = nIC,REF IREF = IC,REF + IB,REF + IB1 IC,REF Icopy = IC,REF + + β β IC,REF nIC,REF = IC,REF + + β β n 1 = IC,REF 1 + + β β Icopy n + 1 + β = n β β nIREF Icopy = n+1+β β Since nIREF is the nominal value of Icopy , the error term, n+1+β , must be between 0.99 and 1.01 so that the actual value of Icopy is within 1 % of the nominal value. Since the upper constraint (that the error term must be less than 1.01) results in a negative value of n (meaning that we can only get less than the nominal current if we include the error term), we only care about the lower error bound.
β ≥ 0.99 n+1+β n ≤ 0.0101 IREF ≥ 50 mA We can see that in order to decrease the error term, we must use a smaller value for n (in the ideal β ). However, the smaller value of case, we have n approaching zero and the error term approaching 1+β n we use, the larger value we must use for IREF , meaning the more power we must consume. Thus, we have a direct trade-off between accuracy and power consumption.
9.64 IC,M =
AE,M IC,REF 1 AE,REF 1
IREF 1 = IC,REF 1 + IB,REF 1 + IB,M IC,REF 1 IC,M = IC,REF 1 + + βn βn AE,M IC,REF 1 IC,REF 1 + = IC,REF 1 + βn AE,REF 1 βn 1 AE,M = IC,REF 1 1 + + βn AE,REF 1 βn AE,REF 1 AE,REF 1 βn + AE,REF 1 + AE,M = IC,M AE,M AE,REF 1 βn AE,M AE,REF 1 βn IREF IC,M = AE,REF 1 βn + AE,REF 1 + AE,M AE,REF 1 Using a similar derivation to find IC2 , we have: AE2 AE,REF 2 βp IC,M IC1 = IC2 = AE,REF 2 βp + AE,REF 2 + AE2 AE,REF 2 AE2 AE,REF 2 βp AE,M AE,REF 1 βp · IREF = AE,REF 1 βp + AE,REF 1 + AE,M AE,REF 2 βp + AE,REF 2 + AE2 AE,REF 1 AE,REF 2 We want the error term to be between 0.90 and 1.10 so that IC2 is within 10 % of its nominal value. Since the error term cannot exceed 1 (since we only lose current through the base), we only have to worry about the lower bound. AE,REF 1 βn AE,REF 2 βp ≥ 0.90 AE,REF 1 βn + AE,REF 1 + AE,M AE,REF 2 βp + AE,REF 2 + AE2 Let’s let the reference transistors QREF 1 and QREF 2 have unit size AE . Then we have: ! ! βn βp > 0.90 A βp + 1 + AAE2 βn + 1 + AE,M E E
We can pick any AE,M and AE2 such that this constraint is satisfied. One valid solution is AE,M = AE , AE2 = 3.466AE , and IREF = 0.2885 mA. This gives a nominal value for IC2 of 1 mA with an error of 10 %. This solution is not unique (for example, another solution would be AE,M = AE2 = AE and IREF = 1 mA, which gives a nominal current of 1 mA and an error of 5.73 %).
9.68 Av = gm1 ro3 = gm1
1 = 20 λp ID1
1 k ro2 gm1 ro2 = 1 + gm1 ro2
Rin =
=
gm1
1 λn ID1
1 + gm1 λn 1ID1
= 50 Ω = 19.5 mS
ID1 = 4.88 mA s W ID1 gm1 = 2µn Cox L 1 W = 390 L 1 We need to size the rest of the transistors to ensure they provide the correct bias current to the amplifier and to ensure they are all in saturation. VG3 will be important in determining how we should bias VG5 , since in order for M5 to be in saturation, we require VG3 > VG5 − VT Hn , and VG3 is fixed by the previously calculated value of ID1 . ! s 2ID1 VG3 = VDD − VSG3 = VDD − |VT Hp | + µp Cox W L 3 = 0.363 V
Let’s let IREF = ID5 = 1 mA (which ensures we meet our power constraint, since P = (IREF + ID5 + ID1 ) VDD = 12.4 mW) and VGS,REF = VGS5 = 0.5 V (which ensures M5 operates in saturation). Then we have W 1 2 (VGS,REF − VT H ) IREF = µn Cox 2 L REF W W 360 = = L REF L 5 0.18 (W/L)3 ID3 = (W/L)4 ID4 8.2 W = L 4 0.18 (W/L)2 ID2 = (W/L)REF IREF W 1756 = L 2 0.18
