Checklist for physical design Please make sure that all the items are duly filled with reasonable explanation. Fill in the checklist with the data available as of the stage you are working on. For example, if you are working on floorplanning stage then mention the utilization of your design at floorplanning stage and not the final utilization. Project Name :
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Library Checklist : Item
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All logical, physical and rule information available for stdcell and macros? Library cells have good accessible pins? Library has antenna, RC and noise information available? Filler, Decap and Pads (for fullchip) available? MultiVT flow related information available? List out all the entity separation created. RTL Checklist : Item Lint check done on RTL? Parsing check done on RTL? Sparecells inserted in RTL? Clockgate inserted in RTL? MBIST inserted in RTL? DFT/ Scan Checklist :
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Top level IO pins defined for scan input, enable, output, clock? Pre scan insertion rule checks done? Passing? How many no. of scan chains defined? All scan chains balanced, if not why? Post scan insertion rule checks done? Passing? Fault coverage reports generated, what is the fault coverage value? Does MBIST included in the design? Have you added LBIST in the netlist? Have you added Boundary scan logic in the netlist? ATPG : Item
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Is there any DFT violation? If yes, Why not fixed at scan chain insertion? Is there any non scanable cells present in the design? If yes, how many? Why? Is there any feedback path present in the design? If yes, how many? What is the fault coverage numbers? How many patterns created? Have you check simulation with any simulator? Constraint Checklist : Item All clocks in the design are defined for freq., latency etc? What is the max frequency? Any timing exception defined? If yes, why? All IO and endpoints are constrained? Slew, skew, jitter, input driver and output load defined?
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Multiclock propagation on/off; if off constants defined to scan_en etc.? Multi mode constraints defined for different modes? If constraints in SDC, any warning/error in sdc_translation.tcl? Any discrepancies in check timing report? Logic Synthesis Checklist : Item
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What is the area of the design? what is the std cell count? What is the setup slack of the design? Are there any unconnected/floating inputs in the design? Are there any “assign” statement in the netlist? Formal verification done from RTL to netlist? Is “check model” clean? Buffers added near to all the input pins? Buffers added near to all the output pins? Floorplanning Checklist : Item High speed and analog IP blocks are placed according to guidelines? Shielding done for analog IP blocks? Mention dimension of floorplan. What's the utilization (total and cellrow)? Hard macro placement done according to guidelines? Proper blockages created over and around macros? Pins and pad placement done according to given constraints or flyline analysis? Powerplan Checklist :
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All power/ground supplies are defined separately? Mention layers and no. of power meshes and their width, mention core ring dimensions. Macro rings created? What's the topology? Stdcell placement blockage created below power meshes? Is power supply uniform in the corners? “Check route drc $m -power_only” clean? Placement Checklist : Item
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Power analysis done? Mention power consumption of the design in watts. What is the total drop in the design? If sparecells not coming from RTL, are they inserted through script? What's the amount of them? Regioning and/or clustering done for flops to achieve latency/skew? What is the congestion figure? Any blobs? CTS Checklist : Item Clock gating happening as expected? Any flops without gate clock? Why? Non default rules and shielding rules defined for clock nets? What are the rules? Hold slack fixes done? Only CLKBUF and CLKINV used in the tree? Proper skew groups and offsets defined for all clock domains? Noise rules sourced before CTS? What skew and latency is achieved after CTS?
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What is the worst slew in the design? Timing analysis with OCV and crosstalk done? Antenna diodes added to all the input pins for a block design? What is the setup slack? What is the hold slack? Final layout Checklist : Item EM, Antenna, crosstalk clean? DRC, LVS clean? Metal density, fillers and decaps inserted? Tiecells inserted? What is the final utilization (total and cellrow)? What is the final congestion figure? Any blobs? Power analysis done? Mention power consumption of the design in watts. IR drop analysis done? Which layers used for analysis? What is the total drop in the design? Timing checks done with SI, OCV at various corners? Hold clean in different modes? Formal verification clean between RTL and final netlist? Complete flow is automated and checked-in? GDSII, final netlist, SDF, SPEF, timing libraries exported? What skew and latency is achieved after routing? What is the worst slew in the design? What is the setup slack?
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Item What is the hold slack?
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