bafuchsan

Andrea Katharina Fuchs

Synchronous Rectification for a Permanent Magnet Brushless DC Motor

Studies on Mechatronics and Bachelor’s Thesis Systems and Control Centre Ecole des Mines (ENSM) Paris Measurement and Control Laboratory Swiss Federal Institute of Technology (ETH) Zurich

Supervision Philippe Martin Prof. Lino Guzzella

June 2008

Contents Abstract

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Acknowledgement

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Symbols

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I

1

Studies on Mechatronics

1 Introduction

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2 Brushless DC-Motor 2.1 Brushed DC-Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Brushless DC-Motor . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 2.2 .1 Perma Permanen nentt Mag Magnet net Brushl Brushless ess DC-Mot DC-Motor or (PMBLD (PMBLDC-M C-Moto otor) r) 2.3 2.3 Syst System em/A /Ana nato tom my of Perma ermane nen nt Ma Magn gnet et BL Mo Moto torr . . . . . . . . .

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3 Commutation 3.1 Power Bridge . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Six Step Mode . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Pulse Width Modu odulation (PWM) . . . . . . . . . . . . . . 3.4 3.4 Sche Scheme me A: PWM on High High Side Side,, 1 on Low Low Side Side . . . . . . 3.4.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Effects . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 3.5 Sche Scheme me B: PWM PWM Sim Simul ulta tane neou ouss on on Hig High h and and Lo Low w Sid Sidee . . 3.5.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Effects . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Schem Schemee C: C: PWM PWM on Hig High h Side Side,, NonNon-Sim Simult ultane aneous ous on Lo Low w 3.6.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Effects . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 3.7 Sche Scheme me SR: SR: Sync Synchr hroonous nous Rect ectific ificatio ation n . . . . . . . . . . . 3.7.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Effects . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . .

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4 Position Detection 4.1 Hall Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Sensorless: BE BEMF Detection . . . . . . . . . . . . . . . . . . . . 4.2.1 4.2 .1 Conve Convent ntion ional al B BEM EMF F Detec Detectio tion n with with Virt Virtual ual Neut Neutral ral Poin Pointt 4.2. 4.2.22 Dire Direct ct BEMF BEMF Dete Detect ctio ion n dur durin ingg PWM PWM Off Time Time . . . . . . 4.2. 4.2.33 Dire Direct ct BEMF BEMF Dete Detect ctio ion n dur durin ingg PWM PWM On Time Time . . . . . . i

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19 . . 19 . . 19 . . 20 . . 21 . . 22

II

Bachelor’s Thesis

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5 Simulation of Different Commutation Schemes 5.1 Simulation of Scheme A . . . . . . . . . . . . . . 5.1.1 Model . . . . . . . . . . . . . . . . . . . . 5.1.2 Results and Discussion . . . . . . . . . . . 5.2 Simulation of Scheme B . . . . . . . . . . . . . . 5.2.1 Model . . . . . . . . . . . . . . . . . . . . 5.2.2 Results and Discussion . . . . . . . . . . . 5.3 Simulation of Scheme C . . . . . . . . . . . . . . 5.3.1 Model . . . . . . . . . . . . . . . . . . . . 5.3.2 Results and Discussion . . . . . . . . . . . 5.4 Simulation of Synchronous Rectification . . . . . 5.4.1 Model . . . . . . . . . . . . . . . . . . . . 5.4.2 Results and Discussion . . . . . . . . . . . 5.5 Comparison of all four Schemes . . . . . . . . . . 6 Hardware 6.1 Microcontroller AT90PWM3B . . . . . . . 6.1.1 Generate PWM Signal . . . . . . . 6.2 AVR STK500 Evaluation Board . . . . . . 6.3 AVR STK520 . . . . . . . . . . . . . . . . 6.4 ATAVRMC100 . . . . . . . . . . . . . . . 6.5 Printed Circuit Board (PCB) . . . . . . . 6.5.1 Driver . . . . . . . . . . . . . . . . 6.5.2 MOSFET . . . . . . . . . . . . . . 6.5.3 Voltage Divider / Low Pass Filter 6.5.4 Testing . . . . . . . . . . . . . . . 7 Synchronous Rectification 7.1 Precedent Problem . . . 7.2 Implementation of SR . 7.2.1 Testprogram . . 7.2.2 PWM . . . . . . 7.2.3 Dead Time . . . 7.2.4 Position Control 7.2.5 Velocity Control 7.3 Results and Discussion . 7.3.1 Test 1 . . . . . . 7.3.2 Test 3 . . . . . .

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8 Sensorless Commutation 8.1 Direct BEMF Detection . . 8.1.1 During On Time . . 8.1.2 During Off Time . . 8.1.3 Commutation Filter 8.2 Final Implementation . . .

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9 Conclusions and Outlook

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27 28 28 28 29 29 29 30 30 30 31 31 31 32

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47 47 47 48 48 49 51

ii

A Photos and Schematics A.1 Photos . . . . . . . . . . . . . . . . . . . . . . . A.1.1 Permanent Magnet Brushless DC-Motor A.1.2 PCB . . . . . . . . . . . . . . . . . . . . A.2 Schematic Diagram of Card . . . . . . . . . . .

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52 52 52 53 54

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55 55 55 66 77 88 99 99 114

C AVR Butterfly C.1 C Programming for Microcontrollers . . . . . . . . . . . . . . . . . . C.2 AVR Butterfly kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.3 Personal Recommendation for Learning to Program Microcontrollers

129 129 129 129

Bibliography

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B Codes B.1 With Hall Sensors . . . . . . . . . . . . . . . . . . . B.1.1 Scheme A, 2 Ramp Mode, 1 directly on Low B.1.2 SR, 2 Ramp Mode, 15.6 kHz . . . . . . . . . B.1.3 SR, 2 Ramp Mode, 7.8 kHz . . . . . . . . . . B.1.4 SR, 2 Ramp Mode, 3.9 k Hz . . . . . . . . . . B.2 Sensorless . . . . . . . . . . . . . . . . . . . . . . . . B.2.1 Scheme A, Centre Aligned Mode . . . . . . . B.2.2 SR, Centre Aligned Mode . . . . . . . . . . .

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Abstract In this thesis an advanced control scheme called synchronous rectification is explained, analysed and implemented, and its application to motors driving quadrotors is discussed. These motors require high durability and low energy losses. To obtain the required durability, permanent magnet brushless DC motors are chosen, and the control functions preferably in a sensorless mode. The energy efficiency is improved with synchronous rectification by controlling the current flow through transistors instead of diodes. With the help of synchronous rectification, it is possible to change the direction much faster, enabling the motor to be more reactive and dynamic. In this project, synchronous rectification is effectively implemented in a motor system both ways with and without sensors. Also, the project’s implementation and necessary tools are described to support further research.

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Acknowledgement I would like to express my gratitude to all those who gave me the chance to do this thesis. I want to thank the staff of the MAVT department administration office, the student exchange office of the ETHZ and Pierre Baladi of the international affairs office at Ecole des Mines for their administrative organisation of my exchange semester. Furthermore, I have to thank my supervisor Philippe Martin who guided me throughout my project and always supported me. In the same way, I have to thank Prof. Lino Guzzella for his confidence and everlasting support. I am deeply indebted to my colleague in Paris, Caroline Claasen. She was very patient and helped me wherever she could. It was a pleasant collaboration and she motivated me to continue with my work. Additionally I have to thank my friends Eva Frommelt, Candy Brakewoo, Fdady Assassa, Fabian Ehrich and Lara Montini, who looked closely at the final version of the thesis for English style and grammar, correcting both and offering suggestions for improvement. Lastly, I thank my parents for funding and encouraging me during my exchange.

vii

viii

List of Figures 2.1 2.2

Equivalent Circuit Diagram of the Motor . . . . . . . . . . . . . . . Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Power Stage . . . . . . . . . . . . . . . . . . Signals for Six Step Mode . . . . . . . . . . Results of Six Step Mode . . . . . . . . . . Pulse Width Modulation . . . . . . . . . . . Pulse Width Modulation in Six Step Mode High side and low side closed . . . . . . . . High side open, low side closed . . . . . . . Duty cycle of PWM . . . . . . . . . . . . . High side and low side closed . . . . . . . . High side and low side open . . . . . . . . . D uty cycle of PWM . . . . . . . . . . . . . Non simultaneous with four states . . . . . High side and low side closed . . . . . . . . High side and low side open . . . . . . . . . Signals for Synchronous Rectification . . . . H A and LC closed . . . . . . . . . . . . . . HA open, LA and LC closed . . . . . . . . . Dead Time . . . . . . . . . . . . . . . . . .

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9 10 10 11 11 12 12 13 14 14 14 15 15 15 16 16 16 17

4.1 4.2 4.3 4.4 4.5

Sensorless Detection Techniques Overview . . . . BEMF in Phase with Current and Zero Crossing Model of Virtual Neutral Point . . . . . . . . . . Current during PWM off time . . . . . . . . . . . Current during PWM on time . . . . . . . . . . .

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5.1 5.2 5.3 5.4

Simulink Model for Simulation of PWM on High Side, 1 on Low Side 28 Current through Phase A . . . . . . . . . . . . . . . . . . . . . . . . 28 Zoomed Current Ripple . . . . . . . . . . . . . . . . . . . . . . . . . 28 Simulink Model for Simulation of PWM Simultaneous on High and Low Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current through Phase A . . . . . . . . . . . . . . . . . . . . . . . . 29 Zoomed Current Ripple . . . . . . . . . . . . . . . . . . . . . . . . . 29 Simulink Model for Simulation of PWM on High Side, Non-Simultaneous on Low Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Current through Phase A . . . . . . . . . . . . . . . . . . . . . . . . 30 Zoomed Current Ripple . . . . . . . . . . . . . . . . . . . . . . . . . 30 Simulink Model for Simulation of Synchronous Rectification . . . . . 31 Current through Phase A . . . . . . . . . . . . . . . . . . . . . . . . 31 Zoomed Current Ripple . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current of all four Schemes . . . . . . . . . . . . . . . . . . . . . . . 32

5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13

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6 7

5.14 Angular velocity of all four Schemes . . . . . . . . . . . . . . . . . .

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6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10

Experimental Setting . . . . . . . . . . . . . . . . Sensorless Setting . . . . . . . . . . . . . . . . . . 2 Ramp Mode . . . . . . . . . . . . . . . . . . . . Centre Aligned Mode . . . . . . . . . . . . . . . . ATMELs STK500 with STK520 . . . . . . . . . . Printed Circuit Board . . . . . . . . . . . . . . . Voltage Divider / Low Pass Filter . . . . . . . . AREF Voltage Divider / Low Pass Filter . . . . Testing Low and High Side Driver and MOSFET Oscilloscope Measurement . . . . . . . . . . . . .

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7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8

Voltage at Phase B . . . . . . . . . Experimental Set-Up . . . . . . . . Simple PWM . . . . . . . . . . . . Measurement . . . . . . . . . . . . Measurement . . . . . . . . . . . . PWM signals with a Duty Cycle of Phase A and Signal to HA . . . . . Phase A and Signal to HA . . . . .

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8.1 8.2 8.3 8.4

ZC Detection During On Time Negative Voltage . . . . . . . . ZC Detection During Off Time Experimental Setting . . . . . .

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A.1 Photo of the Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 Backside of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . A.3 VD/LPF on Phases . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Symbols Symbols ua , ub , uc ia , ib , ic ea , eb , ec LS RS λ θ J p ω T e T L D f

Phase voltages on stator Phase currents Phase back electromotive forces Inductor of the stator windings Resistor of the stator windings Flux induced into the stator through the permanent magnets of the rotor Rotor angle Combined inertia of rotor and load Number of pole pairs Angular velocity of the rotor Electromagnetic torque Shaft mechanical torque Duty cycle Cut-off frequency

Acronyme and Abbreviation PM BLDC-Motor µC PWM HA, HB, HC LA, LB, LC BEMF ZC SR PSC VD LPF PLL DAC ADC ISP RPM

Permanent Magnet Brushless Direct Current Motor Microcontroller Pulse Width Modulation High Side Driver and/or Transistor of Phase A, B, C Low Side Driver and/or Transistor of Phase A, B, C Back Electromotive Force Zero Crossing Synchronous Rectification Power Stage Controller Voltage Divider Low Pass filter Phase-locked Loop Analogue to Digital Converter Digital to Analogue Converter In-System-Programming Revolutions Per Minute

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Part I

Studies on Mechatronics

1

2

Chapter 1

Introduction This Bachelor’s thesis explains the function and the implementation of an advanced commutation scheme called synchronous rectification for a permanent magnet brushless DC motor. The motor is used for driving a quadrotor. The quadrotor is a helicopter driven by four fixed rotors on every end of the two axes. It moves by varying the induced torques resulting from the rotor speed. Therefore, each rotor needs to be controlled separately by motor. The first quadrotors were built in the early 1920’s and were designed to transport passengers. With the advancement of swashplates for normal helicopters, quadrotors fell into oblivion. In recent years, the control of unmanned quadrotors received more and more interest. Due to improvements of electronics and sensor systems, the quadrotor can achieve fast pitching moments, and its construction becomes less complicated. Each rotor of the quadrotor is driven by a permanent brushless DC motor. This motor is driven by a microcontroller, and the control system is designed to obtain high energy efficiency. Synchronous rectification is a control technique with the main purpose to lower the energy losses. Another benefit of the synchronous rectification is the possibility of fast velocity changes and turnarounds. The motor control is achieved by a power bridge. This power bridge generates a 3-phase voltage connected to the motor. To vary the supplied voltage on the motor, transitors on the power bridge are driven by pulse width modulation. By appliying synchronous rectification, the current flows through the transistors instead of the flyback diodes, which decreases the energy losses. The major topic of this thesis is the analysis of the feasibility of the synchronous rectification, and its implementation for the permament magnet brushless DC motor. The thesis consists of two parts, the studies on mechatronics and the Bachelor’s thesis. In the first part, chapters 2 - 4, the theory behind the motor, the commutation modes and the sensorless control is explained. The second part simulates and implements the synchronous rectification. In chapter 5, simulations of different commutation schemes in Matlab/Simulink are demonstrated and discussed. The necessary tools are illustrated in chapter 6. The implementation of synchronous rectification is explained in chapter 7 and the results are discussed. Chapter 8 explains the implementation of synchronous rectification in a sensorless control of a permanent magnet BLDC motor. A sensorless control advantageously simplifies the construction of the quadrotor, decreases the maintenance and reduces costs. Different sensorless techniques exist, the most applicable solutions are explained in chapter 4.

3

4

CHAPTER 1. INTRODUCTION

Chapter 2

Brushless DC-Motor An electric motor consists of a fixed stator and a moving rotor. Electrical energy is transformed into mechanical energy by the magnetic force that acts on the rotor. A synchronous motor is characterised by a synchronous turning of the rotor and the oscillating electromagnetic field or, for a permanent magnet rotor, the oscillating current in the stator. In general, DC motors need direct current to run. However, there are many DC motors that run with alternating current without any problems. The most common constructions of DC motors are the brushless and the brushed version. Both are discussed in this chapter. Additionally, the operating mode of the motor used in this project and its mathematical model is explained.

2.1

Brushed DC-Motor

The stator of a brushed DC-motor is made up of a constant magnetic field in which the rotor with one or several windings is placed. Due to the Lorentz force, a torque acts on the rotor. By continuously changing the poles of the rotor windings, the commutator keeps the current flowing through the rotor windings. This current is always perpendicular to the static magnetic field, which induces a Lorentz force on the rotor, and therefore it continues to rotate.

2.2

Brushless DC-Motor

The rotor and the stator of a brushless DC-motor function differently from the brushed one. The rotor consists of a constant magnetic field, provided by either a permanent or an electric magnet. The poles of the stator windings are electrically commutated, and therefore no brushes are required. This simplifies the maintenance and extends the life of the motor. One advantage of a brushless DC-motor is that it does not have any slip unlike normal induction motors. Compared to a brushed DC-motor, a brushless motor has a higher efficiency.

2.2.1

Permanent Magnet Brushless DC-Motor (PMBLDCMotor)

The rotor of the motor used in this project consists of a permanent magnet. A permanent magnet BLDC-motor requires a trapezoidal current to obtain a uniform flux profile in the rotor. While the rotor is turning, a back electromotive force is induced in the stator windings. This force also has a trapezoidal shape. Contrary to this, the permanent magnet synchronous motor (PMSM), which is constructed 5

6

CHAPTER 2. BRUSHLESS DC-MOTOR

similarly, is designed to have a sinusoidal BEMF and must therefore be driven sinusoidally. The motor used in this project has three windings on the stator and hence it works in 3-phase. These three phases can be modelled as three equivalent circuits in a starlike arrangement. Every phase consists of a winding, its resistance and the BEMF, as depicted in figure 2.1.

L

R + e e R

-

Vn

L

e

+ +

R L

Figure 2.1: Equivalent Circuit Diagram of the Motor

7

2.3. SYSTEM/ANATOMY OF PERMANENT MAGNET BL MOTOR

2.3

System/Anatomy of Permanent Magnet BL Motor

The models used in this chapter are based on the model of the Permanent Magnet BL DC-motor of SymPowersystem of Matlab/Simulink [8]. The equivalent circuit of the motor from figure 2.1 is arranged more clearly in 2.2. The voltage over each individual phase consists of the sum of the induced voltage plus the voltage change over the resistance plus the BEMF. Equations (2.1), (2.2) and (2.3) describe the voltages of Phase A, B and C. A

ua = R S · ia + LS ·

RS

-

+

ua

ib

eb

LS

dib + eb (2.2) dt

RS

-

+

ub

C

uc = R S · ic + LS ·

ea

LS

dia + ea (2.1) dt B

ub = R S · ib + LS ·

ia

ic

dic + ec (2.3) dt

ec

LS

RS

+

-

uc

Figure 2.2: Equivalent Circuit with ua , ub , uc ia , ib , ic ea , eb , ec LS RS

Phase voltages on stator Phase currents Phase back electromotive forces Inductance of the stator windings Resistance of the stator windings

The back electromotive force is proportional to the rotational speed of the rotor, and it is also a function of the rotor angle. For a permanent magnet BL DC Motor the BEMFs have a trapezoidal shape, and the phases are delayed 120 electrical degrees. Equations (2.4), (2.5) and (2.6) describe the BEMF. Function e(θ) is 2π -periodic and trapezoidal between -1 and 1, e (θ) ∈ [ −1, 1]. 

ea = λ · ω · ea = λ · ω · e(θ )



eb = λ · ω · eb = λ · ω · e(θ −



ec = λ · ω · ec = λ · ω · e(θ −

(2.4)

2π ) 3

(2.5)

4π ) 3

(2.6)

with λ θ

Flux induced into the stator through the permanent magnets of the rotor Rotor angle

8

CHAPTER 2. BRUSHLESS DC-MOTOR

The angular acceleration of the rotor is a function of the electromagnetic torque T e , the mechanical shaft torque T L and the combined inertia of the rotor and load J . When friction is neglected, the equation (2.7) depicts this correlation as 1 dω = (T e − T L ). dt J

(2.7)

The electromagnetic torque is related to the current through the phase and is defined as 





T e = p · λ · (ea · ia + eb · ib + ec · ic ).

(2.8)

By inserting the definition of the electromagnetic torque in equation (2.7), then the motor equation (2.9) results in

J

1 dω = (ia · ea + ib · eb + ic · ec ) − T L dt ω

with J p ω T e T L

Combined inertia of rotor and load Number of pole pairs Angular velocity of the rotor Electromagnetic torque Shaft mechanical torque

(2.9)

Chapter 3

Commutation The main objective of commutation is to obtain a constant torque. Therefore, the current through the stator windings needs the correct shape and has to be varied correctly. This chapter explains how to control the motor with different commutation modes and pulse width modulation to obtain a desired average voltage. An electrical rotation of the rotor is divided into six parts. When the rotor turns to the next part, the current has to be commutated. With advanced commutation schemes, energy can be saved and higher efficiency achieved.

3.1

Power Bridge

To obtain the required trapezoidal shape of the current, a power stage of three half bridges is used. Each half bridge consists of two transistors and two flyback diodes across them. Figure 3.1 shows the set-up of the power stage. Each of the three phases A, B and C of the motor is connected to a half bridge. The transistors connected to the voltage are called high side transistors (HA, HB, HC) and the others that are connected to the ground are called low side transistors (LA, LB, LC). The transistors are activated by digital signals. When receiving a 1, the transistor closes the connection and when receiving a 0, it opens. With these switches, the voltage connection on the motor can be changed. In each step, one phase is connected to the positive supply voltage by closing the high side transistor and one phase is connected to the negative by closing the low side transistor. The third phase is potential-free, while both transistors are open. Six commutation steps result from these voltage connections of the three phases. Although the motor acts in three phases, the power stage is fed with a DC voltage source and thus the motor is called DC motor.

HA

HB

HC

A

+

B C

-

LA

LB

LC

Figure 3.1: Power Stage

9

M

10

3.2

CHAPTER 3. COMMUTATION

Six Step Mode

A complete electrical revolution of the rotor is divided into six parts, each of them includes 60 electrical degrees. The number of pole pairs affects how many electrical rotations result in an angular rotation. For example, when the rotor has two pole pairs, two electrical revolution result in one physical rotation of the motor. In six step mode, every phase is connected to the voltage ground during 120 electrical degrees. During the next 120 electrical degrees, it remains floating, before connecting to the ground for the remaining 120 electrical degrees. Figure 3.2 shows the signals for the transistors in six step mode. During the first step, phase A has to be connected to the supply voltage, so the high side transistor HA has to be closed and receives a 1. Phase C has to be connected to the ground and consequently the low side transistor LC has to be closed by receiving a 1. The third phase is floating, so both transistors are open. The resulting behaviour of the rotor speed, the torque and the current through the stator windings are illustrated in figure 3.3. Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

HA

LA

HB

LB

HC

LC

Figure 3.2: Signals for Six Step Mode

Figure 3.3: Results of Six Step Mode

3.3

Pulse Width Modulation (PWM)

With pulse width modulation, a preset average value of the supply voltage can be obtained. Therefore, the connected voltage alternates between two values, usually, the supply voltage and zero. Compared to voltage dividers, a higher power efficiency can be achieved when using PWM. As voltage dividers reduce the voltage through

11

3.3. PULSE WIDTH MODULATION (PWM)

heat emission over resistors or capacitors, they cause high energy losses. In PWM mode, the transistors work only in full conduction or locking mode. Thus the energy losses are minimised as the power supply is not constantly connected to the motor. Due to this variation from a constant frequency, the overall power consumption can be described by an average value. This average value is a desired percentage of the maximum value. The duty cycle describes this percentage and affects the on and off time of the signal. With a duty cycle of 0.2, the signal is switched on for 20% of the time and switched off for 80%. This results in a overall power consumption of 20% of the maximum value. Three different duty cycles and their signals are illustrated in figure 3.4. 20%

off time average value

0.2 T

T

2T

T

2T

50%

0.5T

on time

90%

0.9T

T

2T PWM period

Figure 3.4: Pulse Width Modulation The average value of the connected voltage to the motor is proportional to the rotor speed. When a higher voltage is connected, a stronger current flows through the stator windings and induces a higher force on the rotor. With PWM, the desired average voltage on the motor and the resulting rotor speed can be achieved. While one phase is connected to the supply voltage, the high side transistor is activated with a PWM signal, and therefore the motor is connected with the resulting average voltage. In figure 3.5, the six step mode with PWM signals on the high side transistor is illustrated. Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

HA

LA

HB

LB

HC

LC

Figure 3.5: Pulse Width Modulation in Six Step Mode The frequency of the PWM should be much higher than the motor frequency. Thus the higher frequency can be filtered out, and the two frequencies do not influence each other. To obtain the desired PWM signal, a counter with the PWM frequency is compared with the value depending on the duty cycle. If the counter value corresponds with the reference value, the PWM signal changes. The specific application is described in chapter 6.1.1. One of the disadvantages of PWM is the high switching noise, which is even higher if multiple transistors switch at same the time.

12


3.4

Scheme A: PWM on High Side, 1 on Low Side

As this scheme is the most common and the simplest, it has been already described in the section before and is illustrated in 3.4.

3.4.1

Design

The temporary active high side transistor is driven by a PWM signal while the low side is permanently switched on during the active phases. When both transistors are closed, the current flows through two phases as pictured in figure 3.6. When the high side transistor is open, the current flow through the flyback diode and the low side transistor is closed, as shown in figure 3.7.

HA

HB

HA

HC

LS

i

A

RS

+

+

LS

B

RS

+

A

-

i

C

LS

RS

+

i

LS

RS

LS

RS

+

B

V

LB

C

-

i

LS

RS

-

+

BEMF

LA

LC

Figure 3.6: High side and low side closed

-

+

BEMF

-

BEMF

LA

-

+

BEMF

BEMF

-

HC

-

BEMF V

HB

LB

LC

Figure 3.7: High side open, low side closed

When both the high and low side transistors are closed, the following voltages are connected to the phase A and C: va = V = u a + vN

vc = 0 = u c + vN

(3.1)

(3.2)

Using equations (2.1) and (2.1), Voltage V results in V = u a

−

uc = R s · (ia

The current is constant, so

− ic

di dt =

ia = i

) + Ls · (

dia dt

−

dic ) + ea − ec . dt

(3.3)

0. It flows through the transistors HA and LC

(3.4)

ib = 0 ic =

(3.5)

−i

(3.6)

The BEMF is proportional to the angular speed multiplied by the induced flux of the magnet. 

ea = λ · ω · ea ec =

−λ ·



ω · ec

(3.7)

(3.8)

e is a trapezoidal function between 1 and -1. With equations (3.7), (3.8) and the 

currents of (3.4) and (3.5), the voltage in (3.3) can be written as V = 2 · Rs · i + 2 · λ · ω

(3.9)

3.4.. SCHEME 3.4 SCHEME A: PWM PWM ON HIGH SIDE, SIDE, 1 ON LOW SIDE

13

The current i can be calculated from the motor equation (2.9) by inserting the currents and BEMFs J

1 dω = 0 = (ia · ea + ib · eb + ic · ec ) − T L dt ω =

1 ω

(i · (λ · ω) + 0 + (−i) · (−λ · ω )) − T L (3.10)

The resulting current is then: i =

T L 2λ

(3.11)

The applied duty cycle of the PWM signal can be calculated with the source voltage U DC (3.9), which depends on the angular speed. DC and the average voltage V (3.9),

Figure 3.8: Duty cycle of PWM V · T = D · T · U DC DC

3.4. 3.4.2 2

⇒ D

=

V U DC DC

(3.12)

Effec Effects ts

The motor acts in 2-quadrants, which means that it can drive forwards and backwards. wards. This simple commutatio commutation n scheme scheme has high switching switching losses, but good cost efficiency and can be easily implemented.

14

CHAPTER 3. COMMUTA COMMUTATION

3.5 3.5

Scheme Sche me B: PWM PWM Simul Simulta tane neou ouss on High High and Low Side

3.5. 3.5.1 1

Desi Design gn

The low and high side transistors used for this design are controlled by the same PWM signal. signal. Therefore Therefore,, a new state results results when all transistors transistors are open and the curren currentt flows flows throug through h the flyback flyback diodes. diodes. As shown shown in figure figure 3.1 3.10, 0, the negativ negativee supply voltage is then connected to the motor.

HA

HB

HA

HC

A

LS

i

RS

+

+

B

RS

C

LS

RS

V

+

-

BEMF

-

i

+

HC

LS

RS

B

LS

RS

C

LS

RS

A

-

i

+ V

LB

-

+

-

i

+

-

BEMF

LA

LC

Figu Figure re 3.9: High High side and low low side side closed

-

BEMF

-

BEMF

LA

+

BEMF

BEMF LS

HB

LB

LC

Figure Figure 3.10: 3.10: Hig High h side side and low side open

The connected voltage varies between + U DC DC and −U DC DC , which is pictured in figure 3.11. Thus the duty cycle is defined as V · T = D · T · U DC DC + (1 − D ) · T · (−U DC DC )

⇒ D

=

V + U DC DC . 2 · U DC DC

(3.13)

Figure 3.11: Duty cycle of PWM

3.5. 3.5.2 2

Effec Effects ts

Unfort Unfortuna unatel tely y, the switc switchin hingg losses losses are high, high, but the motor motor can functi function on in 4quadra quadrant nt mode. Beside Beside operatin operatingg in both directi directions ons,, the motor motor can also break break from forward forward and reverse reverse.. Because Because the high and low side transisto transistorr switch switch at the same time, the switching noise is high.

3.6. 3.6. SCHE SCHEME ME C: PWM PWM ON HIGH HIGH SIDE, SIDE, NO NONN-SIM SIMUL ULT TAN ANEO EOUS US ON LO LOW W SIDE SIDE 1155

3.6

Scheme C: PWM on High Side, Non-Sim Scheme Non-Simultan ultaneous eous on Low Side

3.6. 3.6.1 1

Desi Design gn

The PWM signal on the low side transistor is delayed by half a PWM mode to the signal signal on the high side. Four connect connection ion states states result result of this this mode and are illustrated in 3.12.

HA

LC

I

II

II I II

IV

Figure 3.12: Non simultaneous with four states In state I, no voltage is connected to the motor what is pictured in figure 3.13. While discharging the inductances, the current flows through the closed high side transistor and the flyback diode on the high side of the other phase. State II is the same as before in 3.9. As it can be seen in figure 3.14, the current in state III flows through the closed transistor and the low side diode for unloading the inductances. In state IV, all transistors are open and the current flows just like in figure 3.10 with the reverse supply voltage connected to the motor.

HA

HB

HA

HC

A

LS

i

RS

+

LS

B

RS

+

-

V BEMF

C

i

LS

RS

+

HC

A

-

LB

+

B

Figure Figure 3.13: 3.13: Hig High h side side and low side closed

3.6. 3.6.2 2

RS

LS

RS

+

-

+

-

BEMF

C

-

LC

LS

V

i

LS

RS

+

-

BEMF

BEMF

LA

i

BEMF

BEMF

+

HB

LA

LB

LC

Figure Figure 3.14: 3.14: Hig High h side side and low side open

Effec Effects ts

Due to the four states during one PWM cycle, the connection is changed twice more than by the other commutation schemes. The switching noise is lower, because the transistors do not switch at the same time.

16


3.7

Scheme SR: Synchronous Rectification

3.7.1

Design

The low side transistor is activated in a manner opposite to the high side one. The low side transistor of the other active phase in this step is still closed. The command signals are illustrated in 3.15. The current flows through the closed low side transistor instead of the diode, which is pictured in figure 3.17. The duty cycle and the current can be similarly calculated as in section 3.4. Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

HA

LA

HB

LB

HC

LC

Figure 3.15: Signals for Synchronous Rectification

HA

HB

HC

HA

A

LS

i

RS

+

HB

HC

-

A

LS

i

RS

BEMF

+

LS

B

RS

+

-

BEMF

+

-

V

+

LS

B

RS

+

-

V BEMF

C

i

LS

RS

+

-

BEMF

C

BEMF

LA

LB

LC

Figure 3.16: HA and LC closed

3.7.2

i

LS

RS

+

-

BEMF

LA

LB

LC

Figure 3.17: HA open, LA and LC closed

Effects

The current flows through the transistors instead of the diodes. When the conduction losses through the transistors are less than through the diode, energy can be saved with this mode.

17

3.8. DEAD TIME

3.8

Dead Time

It is important to avoid a short circuit when driving the motor by a power stage. The high and low side transistors should never be closed at the same time, because this will result in a short circuit. Therefore a so-called dead time is implemented, if both transistors are driven after each other or by PWM. The dead time has to account for both the normal conduction time of a transistor as well as switch on and turn off time. It is also important to note that transistors usually require more time to turn off than to switch on. The figure 3.18 illustrates the synchronous rectification signal of the high and low side transistor by inserting the dead time.

high side

dead time

low side

Figure 3.18: Dead Time

dead time

18


Chapter 4

Position Detection The rotor position is necessary to control the motor. The motor works in a six step mode, and therefore the sole information required is the sector in which the rotor is located momentarily. This can be obtained by Hall sensors or by sensorless techniques. This chapter explains the different position detection techniques, especially BEMF detection. The BEMF detection will focus on the method used by Jianwen Shao [9].

4.1

Hall Sensors

Three Hall sensors are placed in the stator on the non-rotating end. The distance between two sensors can be 60 or 120 . When the N or the S pole of the rotor is passing by a sensor, a high or a low signal is transmitted. The sensor responds to the passing magnetic field of the rotor, which is rectangular to the current through the sensor. The three sensor signals detect the instantaneous rotor position. ◦

4.2

◦

Sensorless: BEMF Detection

There are two primary techniques of sensorless position control that are illustrated in the literature. The first method measures the back electromotive force induced in the stator windings. The second estimates the position using the motor parameters. Figure 4.1 shows a survey of the different sensorless detection modes. In this thesis, only the BEMF detection is discussed, as it is the most common sensorless application. The BEMF detection with a virtual neutral point and the direct detection are analysed. Some other BEMF detection techniques exist, (position detection based on the third harmonic of the voltage, BEMF integration etc.), but they are not further explained here. To obtain a high energy efficiency, the torque-to-current ratio should be optimal. Therefore current through the stator windings should be controlled such that it is in phase with the BEMF. The rotor position affects the commutation steps and the form of the BEMF. When the BEMF can be detected, the commutation can be set at the right moment. The BEMF detection consists of measuring the zero crossing of the BEMF, which occurs in the middle of a commutation step. In figure 4.2, the current in phase with the BEMF and the moment of the zero crossing is illustrated. 19

20

CHAPTER CHAPTER 4. POSITION POSITION DETECTION DETECTION

Sensorless

BEMF

Parameters

Virtual Neutral Point

Direct BEMF

others

PWM on time

PWM off time

Figure 4.1: Sensorless Detection Techniques Overview

BEMF Zero Crossing Current Step

Figure 4.2: BEMF in Phase with Current and Zero Crossing

4.2.1 4.2.1

Conve Convent ntion ional al BEMF BEMF Detect Detection ion with Virtua Virtuall Neutra Neutrall Point

The BEMF is applied to the undriven voltage phase, which can be measured if the voltage at the neutral point of the motor is known. Due to the inaccessibility of the neutral neutral point p oint,, a model is derived derived from three resistors resistors to estimate estimate the voltage voltage at the neutral point, as presented in figure 4.3. One clear disadvantage of this detection technique is the instability of the virtual

L

R + e e R

-

-

Vn L

e

+ +

R L

Figure 4.3: Model of Virtual Neutral Point neutral point as a consequence of the PWM drive. To measure a steady value, low pass filters and voltage dividers, which complicate the detection mode, are necessary.

21

4.2. SENSORLESS SENSORLESS:: BEMF DETECTION DETECTION

4.2.2 4.2.2

Direct Direct BEMF BEMF Dete Detectio ction n durin during g PWM Off Off Time Time

The advantage of this approach for BEMF detection is that measurements during the PWM off time avoid avoid the instability instability of the virtual virtual neutral point. When the high side transistor is driven by the PWM and the corresponding low side transistor is closed, closed, the voltage voltage at the floating phase can be measured. measured. For example, the first step step is examined examined when HA receiv receives es a PWM signal signal and LC is closed closed.. During During the PWM on time, the voltage is supplied at phase A and charges the inductors. During PWM off time, the transistor HA is open and the inductors can be discharged. That generates a current flowing through the phases A and C, as illustrated in figure 4.4. At the floating phase B, the phase voltage u b can be measured. VDC

HA

HB

HC LS

i

ua

RS

+

-

BEMF LS

ub

RS

+

-

vN

BEMF uc

LS

i

RS

+

-

BEMF Comparator LA

LB

LC VRef

Figure 4.4: Current during PWM off time During PWM off time, no current flows through phase B, and therefore the measured voltage ub consists of the BEMF of the phase B eb and the voltage at the neutral point v N : ub = e b + vN

(4.1)

Because phase A and C are connected to the ground, the voltage v N can be described through vd − RS · i − LS ·

di dt

−

ea

(4.2)

vN = 0 + vt + RS · i + LS ·

di dt

−

ec

(4.3)

vN = 0

−

and

with vt as the voltage over the transistor and v d as the voltage over the diode. When adding (4.2) and (4.3) and dividing by two, this results in 1 2

vN = − (ea + ec ) +

vt

2

−

vd

2

.

(4.4)

vt is the voltage over the transistor during conduction, which is very low and can be ignored. The voltage over the conducting diode vd is approximately 0.7 V. The

voltage at the neutral point is 1 2

vN = − (ea + ec ) −

vd

2

.

(4.5)

22

CHAPTER CHAPTER 4. POSITION POSITION DETECTION DETECTION

The three BEMFs build a 3-phase system and equation (4.6) describes the BEMF’s. ea + eb + ec = e 3

(4.6)

For further processing, processing, the third harmonics are always always ignored. ignored. Equation Equation (4.6) is therefore rewritten as ea + eb + ec = 0.

(4.7)

From equation (4.5) and (4.7), the voltage at the neutral point becomes vN =

eb

2

−

vd

2

.

(4.8)

By applying this result to equation (4.1), the measured voltage at phase B is ub = e b + vN =

3 vd . · eb − 2 2

(4.9)

For a general case and for simplification, the voltage over the diode is neglected. The measured voltage at phase B can be written ub =

3 · eb . 2

(4.10)

As it can be seen in equation (4.10), the measured voltage at the floating phase is directly directly proportional proportional to the BEMF. If the voltage voltage at the floating floating phase is detected, detected, the BEMF can be calculate calculated d directly directly.. As it has been shown, shown, the knowledg knowledgee of the voltage at the neutral point is not required when measuring during PWM off time. The zero crossing of the BEMF can be detected with a comparator that checks the measured voltage with respect to the reference value. This occurs in the middle of a step and with the information of the zero crossing time, the commutation can be set. The advantage of this type of BEMF detection is, as it has been shown before, that the voltage at the neutral point is not necessary. Because the BEMF is not induced at the beginning of the motor rotation, an additional start up process has to be programmed programmed.. This supplementa supplementary ry work is one of the disadvant disadvantages ages of the direct BEMF detection detection.. Another Another drawback drawback of this BEMF detection detection is that it runs only for low PWM duty cycles. So if the PWM off time for high velocities is too short, measurements are impossible.

4.2.3 4.2.3

Direct Direct BEMF BEMF Detec Detectio tion n during during PWM PWM On Time Time

To avoid the problem of a PWM off time that is too short or nonexistent, the BEMF is measured during during PWM on time. Therefore Therefore,, the first commutat commutation ion step is analysed again. During PWM on time, phase A is connected to the supply voltage and phase C to ground, as illustrated in figure 4.5. The voltage at the neutral point is the sum of the voltages at the phases, over the inductors and the resistors and the BEMF, with vt as the voltages over the two transistors. vN = v DC − vt

−

RS · i − LS ·

vN = 0 + vt + RS · i + LS ·

di dt

di dt −

−

ec

ea

(4.11) (4.12)

23

4.2. SENSORLESS: BEMF DETECTION

VDC

HA

HB

HC

i

ua ub

uc

LS

RS

LS

RS

LS

i

RS

+

-

BEMF

+

-

vN

BEMF

+

-

BEMF Comparator LA

LB

LC VRef

Figure 4.5: Current during PWM on time By adding (4.11) and (4.12) and dividing by two, v N becomes vN =

vDC

2

−

1 (ea + ec ) 2

(4.13)

As in the previous section, the third harmonics are neglected and the BEMF are 3-phase. ea + eb + ec = 0

(4.14)

The voltage at the neutral point results from equations (4.13) and (4.14): vN =

vDC

2

+

eb .

2

(4.15)

Applying this equation to (4.1), the measured voltage at phase B can be written as ub = e b + vN =

3 vDC · eb + . 2 2

(4.16)

The measured voltage at phase B consists of one and a half times the BEMF and half of the supply voltage. When comparing the voltage u b with half of the supply voltage, the zero crossing of the BEMF can be detected. This BEMF detection mode can be used for high velocities when the PWM off time is small or nonexistent. At high velocities, the BEMF amplitude is high, so the common mode voltage does not influence the BEMF too heavily. For low velocities, the BEMF detection during off time is preferred. The direct BEMF detection is easier to implement during on time, because the comparison with half of the supply voltage is more secure than with zero.

24

CHAPTER 4. POSITION DETECTION

Part II

Bachelor’s Thesis

25

26

Chapter 5

Simulation of Different Commutation Schemes For demonstration of the various effects, the commutation schemes described in section 3.4, 3.5, 3.6 and 3.7 have been simulated in Simulink. The models of the experimental setup are built with SimPowerSystems tools in Matlab/Simulink. This chapter shows the set-up of the simulation and discusses the results. The following values are used for all simulations: RS = 2.875Ω LS = 8.5 mH λ = 0.175 Wb T L = 1 Nm

120 J = 0.001 kg · m2 F = 0.01 Fms p = 1 U DC = 100V ◦

Stator resistance Stator inductance constant flux induced by magnets Mechanical Torque Back EMF flat area Inertia Friction factor Pairs of poles Supply Voltage

The permanent magnet synchronous machine of SimPowerSystems is used to simulate the motor. The flux distribution is set to trapezoidal shape and the mechanical input is torque. The DC Voltage Source is connected to the universal bridge, which generates the three phase voltage. The bridge receives the signal to open or close the transistors. This signal as well as the desired voltage is created differently in every mode. The frequency of the repeating sequence, which is used for generating the PWM signal, is 10kHz.

27

28CHAPTER 5. SIMULATION OF DIFFERENT COMMUTATION SCHEMES

5.1

Simulation of Scheme A

5.1.1

Model

Figure 5.1: Simulink Model for Simulation of PWM on High Side, 1 on Low Side For PWM on high side and 1 on low side mode, the model 5.1 is built in Simulink. The signalfunction block generates the signal by checking the instantaneous step with the measured rotor angle. This signal is a binary six digit and three of them are overlaid by the PWM signal. The desired duty cycle is calculated with equation (3.12) in the voltage block and sent to the PWM block. There, the signal is set to 1, when the value of the repeating sequence is higher than the duty cycle and to 0, if it is lower. With this PWM signal, the high side transistors are activated.

5.1.2

Results and Discussion PWM on High Side, 1 on Low Side, Zoom

PWM on High Side, 1 on Low Side

4.1

6

4 4.05

2 4 t n e r r u C

t n e r r u C

0

3.95 −2

3.9 −4

−6 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time

Figure 5.2: Current through Phase A

3.85 0.39

0.395

0.4

0.405

Time

Figure 5.3: Zoomed Current Ripple

The measured current during the first half of the simulation through phase A is pictured in figure 5.2. The percentage of the current ripple can be roughly estimated by measuring the value of the current and its ripple at any instant. In figure 5.3 the average value of the current ripple is measured and compared with the amplitude. The ripple is 4.03 % of the amplitude.

29

5.2. SIMULATION OF SCHEME B

5.2

Simulation of Scheme B

5.2.1

Model

Figure 5.4: Simulink Model for Simulation of PWM Simultaneous on High and Low Side For the simulation of the commutation mode with simultaneous PWM signal on high and low side, model 5.4 is built. Therefore, only the overlaid PWM signal and the calculated duty cycle differ from model 5.1. Both the high and low side transistors are now activated by the same PWM signal. The duty cycle is evaluated using equation (3.13).

5.2.2

Results and Discussion PWM Simultaneous on High and Low Side, Zoom

PWM Simultaneous on High and Low Side

3.85

6 5

3.8 4 3.75

3 2 t n e r r u C

t n e r r u C

1 0 −1

3.7

3.65

3.6

−2 3.55 −3 −4 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time


3.5 0.525

0.53

0.535

0.54

Time


The current ripple can be estimated out of the measurements in 5.5 and 5.6. The percentage current ripple for this commutation mode is 7.17 %. The current ripple is almost two times the current ripple of the commutation scheme from the previous section. As said in section 3.5.2, the main advantage of this mode is that the motor can drive in 4-quadrant mode. Unfortunately, the current ripple is high.


5.3

Simulation of Scheme C

5.3.1

Model

Figure 5.7: Simulink Model for Simulation of PWM on High Side, Non-Simultaneous on Low Side The model for PWM on high side and non-simultaneous on low side mode is illustrated in 5.7. For generating the non-simultaneous PWM signal on the low side transistors, a second repeating sequence is built and overlaid on the low side signal. Because this repeating sequence is delayed by half a PWM cycle, it has to be inverted. The PWM block sets the normal PWM signal on the high side signal and the delayed one on the low side. The duty cycle is calculated with equation (3.13).

5.3.2

Results and Discussion PWM on High Side, Non−simultaneous on Low Side

PWM on High Side, Non−simultaneous on Low Side, Zoom

5 4 3

3.7

2

t n e r r u C

1

t n e r r 3.65 u C

0 −1

3.6

−2 −3

−4 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Time


3.55 0.525

0.53

0.535

0.54

Time


The percentage current ripple can be again estimated from the current measurement 5.8. Figure 5.9 shows the current ripple, which is only 2.17 % of the amplitude. As described in section 3.6.2, the voltage connection on the motor changes two times more during one PWM cycle than with scheme A. Therefore, the frequency of the current ripple is twice the PWM frequency, which makes the current ripple smaller.

31

5.4. SIMULATION OF SYNCHRONOUS RECTIFICATION

5.4

Simulation of Synchronous Rectification

5.4.1

Model

Discrete , s = 5e-006 s powergui

fcn

y

Scope5

u

(rad)>

Scope2

high side

1/100 Gain v

AND

g

fcn triangle

Logical Operator

Scope1

PWM

Repeating Sequence

v

Scope7

g

fcn triangle

inverse PWM

Scope8

OR

AND

Logical Operator2

Logical Operator1

fcn

y

u

complementary

fcn

y

u

low side 1

g

Torque

+ A

A

B

B

Vabc

Scope3

Iabc

DC Voltage Source

Tm

Scope4_2

a

A m

-

b C

C

Universal Bridge

(N*m)>

B

c

Scope6

C
Permanent Magnet Synchronous Machine

Three-Phase V-I Measurement

velocity

(rad/s)>

60

omega v

Last

fcn

Scope tm

voltage

Figure 5.10: Simulink Model for Simulation of Synchronous Rectification The command to the power bridge in 5.10 is made up of three signals. The normal PWM signal is applied on the high side. At the same time, the low side is activated by the complementary PWM signal. The third signal closes the low side transistor during one step and therefore is set to 1. The duty cycle is evaluated using (3.12).

5.4.2

Results and Discussion Synchronous Rectification, Zoom

SynchronousRectification

4.1

6

4 4.05

2 4 t n e r r u C

t n e r r u C

0

3.95 −2

3.9 −4

−6 0

0.05

0.1

0.15

0.2 Time

0.25

0.3

0.35

0.4


3.85 0.39

0.395

0.4

0.405

Time


In figure 5.11 the measured current is illustrated, and figure 5.12 shows the current ripple. The percentage current ripple is 3.97 % of the amplitude. The current is almost the same as in scheme A, but the motor can act in 4-quadrant mode. Additionally, energy can be saved through the lower conduction losses of the transistors.


All four Commutation Modes 6

Scheme A Scheme B

5.5

Scheme C Scheme SR

5

4.5

4 t n e r r 3.5 u C

3

2.5

2

1.5

1 0.4

0.41

0.42

0.43

0.44

0.45

0.46

0.47

0.48

0.49

0.5

Time

Figure 5.13: Current of all four Schemes

5.5

Comparison of all four Schemes

In figure 5.13, the currents of the simulated commutation modes are pictured. It can be seen that modes A and SR have almost the same current profile. The duty cycle of the PWM are the same for both schemes and are calculated with equation (3.12). The other two modes, B and C, have similar current profiles. The sole difference between these two schemes is the lower current ripple in scheme C, which is caused by the double frequency of the current. As can be seen in figure 5.13, the period of the current in modes A and SR is shorter than the current in the other two modes. Therefore, the phases change faster, so the angular velocity of the rotor is higher. Figure 5.14 shows the speed of all four schemes. Speed of all four Commutation Modes 35

30

25

20 d e e 15 p S

10

5 Scheme A Scheme B Scheme C Scheme SR

0

−5 0

0.1

0.2

0.3

0.4

0.5 Time

0.6

0.7

0.8

0.9

1

Figure 5.14: Angular velocity of all four Schemes

Chapter 6

Hardware This chapter describes the different hardware tools that have been used for motor commutation. Every experimental setting includes a microcontroller, a power stage, including drivers and MOSFETs, and of course the motor. In figure 6.1 the setup with Hall sensors is illustrated. The computer programs the µC over a serial connection to the flash memory and interacts over the second serial connection. The µ C controls the MOSFETs by sending signals to the drivers. The power bridge controls the applied voltage on the motor. The instantaneous position of the rotor is detected by Hall sensors and sent back to the microcontroller. When using sensorless commutation, the µC determines the position from the BEMF. As it can be seen in figure 6.2, the sole difference to the senorless set-up is how the µC determines the rotor position. Different combinations of tools have been used for the experimental set-up. In this chapter only the tools that are important and useful for the commutation implementation are explained. Transitor Commands Flash Computer

Microcontroller

Transistor Commands

Voltage Power Bridge with Supply Voltage

Flash Motor

Computer

Microcontroller

Rotor Position

Motor

BEMF

Figure 6.1: Experimental Setting

6.1

Voltage

Power Bridge with Supply Voltage

Figure 6.2: Sensorless Setting

Microcontroller AT90PWM3B

The serial of ATMELs microcontroller AT90PWM is specially designed for motor control applications. The AT90PWM3B is used for all experiments in this project. It features 8 kilo bytes of flash memory and has ten channels with advanced PWM. As it is explained later in this chapter, it also includes three high speed power stage controllers, which are required for generating the desired PWM signal. Moreover, eleven ADC channels and one DAC are in the microcontroller.

6.1.1

Generate PWM Signal

There are several different modes for the power stage controller in AT90PWM3B to generate a PWM signal. Here only the two modes that are used in the project are discussed. The 2 ramp mode is used for the first implementation of synchronous rectification and the centre aligned mode for sensorless commutation. Each of the 33

34

CHAPTER 6. HARDWARE

three power stage controllers has a counter, which can count up and down. Additionally, four reference values can be stored. By comparing the reference value with the counter value, the two output signals and the countering can be changed. Since each of the three PSC has two outputs, it is perfectly made for driving three half bridges and a DC motor. 2 Ramp Mode In every power stage controller, four output compare register values can be set: OCRnSA, OCRnRA, OCRnSB, OCRnRB. The counter enumerates two times, first to the value of the output compare register RA and then to RB. The values SA and SB have to be set by considering the dead time. With SA and RA the high side transistor is activated and with SB and RB the low side is activated. One PSC cycle lasts for counting up to RA and RB. The 2 ramp mode is illustrated in figure 6.3. OCRnRA OCRnRB OCRnSA OCRnSB

PSCOUTn0

PSCOUTn1 dead time

dead time PSC Cycle

Figure 6.3: 2 Ramp Mode First, the PSC cycle and the on time of the high side transistor are defined. The duration of one counting step is set with the phase-lock loop (PLL) frequency. Depending on this frequency, the counting values are set. The compare registers are calculated as follows: OCRnSA = dead time OCRnSB = dead time OCRnRA = dead time + on time of high side OCRnRB = PSC cycle - (dead time + on time of high side) One of the big benefits of the 2 ramp mode is the guarantee that the two output signals are not switched on at the same time. When driving a low and a high transistor of a half bridge, this mode can be wisely used for new commutations and experiments. Centre Aligned Mode In centre aligned mode, the PSC counts from the set value RB down and up again. With the compare register SA, the on time of the first output can be set and with SB, the on time of the second output can be set. This mode is shown in figure 6.4. As the fourth compare register is not required, it can be used for adjusting the analogue to digital conversion (ADC) synchronisation (see 8.2).

35

6.2. AVR STK500 EVALUATION BOARD

OCRnRB

OCRnSB

OCRnSA

OCRnRA PSCOUTn0

On time 1 PSCOUTn1 On time 2

Figure 6.4: Centre Aligned Mode

6.2

AVR STK500 Evaluation Board

The AVR STK500 starter kit of ATMEL is a development system for different microcontrollers (figure 6.5). Six places for temporary microcontrollers are available. The STK500 can be practically used for tests and prototypes, as the microcontroller does not need to be brazed on the board. The flash memory can be programmed from the computer over the RS-232 interface, and it communicates over the second RS-232. The STK500 interacts over ISP with external devices on the board. PC

PC

STK 520

AT90PWM3B

Commands to Power Bridge

Figure 6.5: ATMELs STK500 with STK520

6.3

AVR STK520

The AVR STK520 is an additional module for the STK500 board. It can be placed on the STK500 as shown in 6.5. The STK520 board includes two places for microcontrollers and allows for the use of all advanced features of the AT90PWM series. The microcontroller is placed on one of the temporary station.

36

6.4

CHAPTER 6. HARDWARE

ATAVRMC100

The ATAVRMC100 board is an evaluation kit especially arranged for BL DC-motor control with hall sensors, or it is sensorless by detecting the BEMF. It includes a AT90PWM3 microcontroller, drivers and MOSFETs (3 half bridges). This device is used for testing the synchronous rectification program.

6.5

Printed Circuit Board (PCB)

A special PCB for driving the motor by itself is constructed. For more detailed information, its schematic diagram is illustrated in A.2 of the Appendix. It consists of a power bridge of three MOSFET half bridges driven by 6 drivers, an in-system programming (ISP) interface and a AT90PWM3B. In this project the board is used without the microcontroller. Instead of the microcontroller on the board, the AT90PWM3B is installed on the STK520. One possibility for further research would be to use the board with the microcontroller on it.

Figure 6.6: Printed Circuit Board

6.5.1

Driver

The IR2101S drivers from International Rectifier have been chosen, because the logic input voltage is in phase (non inverted), and the high and low side output channels work independently. When the input voltage is in phase, the driver closes the MOSFET by receiving a 1.

6.5.2

MOSFET

The selected MOSFETs are the IR8910 from International Rectifier with following characteristics: Turn-On Delay Time Rise Time 2 Turn-Off Delay Time 3 Fall Time

6.5.3

6.2 ns 10 ns 9.7 ns 4.1 ns

Voltage Divider / Low Pass Filter

The voltage divider and low pass filter has a common design. The desired output voltage and the cut-off frequency determines the values of the components. The

37

6.5. PRINTED CIRCUIT BOARD (PCB) U

in

R

1

U

out

R

C

2

1

C

2

Figure 6.7: Voltage Divider / Low Pass Filter capacitors filter out high frequencies and the resistors divide the voltage. The equivalent circuit is shown in figure 6.7. The cut-off frequency is given by the equation: f =

1 R1 + R2 2π R1 · R2 · (C 1 + C 2 )

(6.1)

At low frequencies, the circuit acts only as a voltage divider with the gain: U out R2 = U in R1 + R2

(6.2)

In the application note AVR444 [6], the sum of R1 and R2 are recommended as values from 10kΩ to 100kΩ. Voltage Divider / Low Pass Filter on Motor Terminal Voltages For sensorless commutation and its BEMF detection, the voltage at each motor phase has to be measured. This voltage has to be scaled down, and therefore, a VD/LPF as described before is used. The following values are chosen: R1 = 10k Ω, R2 = 5.6k Ω, C 1 + C 2 = 150 pF Voltage Divider / Low Pass Filter for ADC Reference Voltage The scaled down motor supply voltage is used as the reference voltage AREF, which is 5V. For lowering ripples of V DC , a low pass filter is required. On that account, the previously described VD/LPF is assembled, as illustrated in figure 6.8. The interior ADC input resistance of the AT90PWM3B is 30 k Ω and the input capacitor 10nF . So the values are set to R 1 = 10k Ω, R2 = 6.8k Ω, C = 2 .2nF . Uin

R1

Uout= AREF

R2

C

30kΩ

10nF ADC input capacitor

ADC input resistance

Figure 6.8: AREF Voltage Divider / Low Pass Filter

38

6.5.4

CHAPTER 6. HARDWARE

Testing

After composing the board as designed, the drivers and the MOSFETs need to be checked to guarantee that they are well connected and function as desired. Every Diver/MOSFET has to be tested alone, so six test runs are required. Therefore a load is connected to the relevant phase and some simple PWM signals (0V...5V) are transmitted to the driver as shown in figure 6.9. When testing the low side, the high side transistor is deactivated and a load is lying between the phase and a 12V Voltage. By sending signals to the lower transistor, the measured voltage of the phase should react inversely to the signal. When the high side transistor is tested, it receives signals while the load is connected to ground and the low side transistor is disabled. The measured voltage at the phase should react the same way as the sent signal. Different PWM signals are sent to the drivers to check them (different duty cycle and frequency). 12 V

12 V

Driver

Driver R

0V

V

12 V

5V

0V

0V

5V 0V

0V

Ground

R

V

12 V 0V

Ground

Figure 6.9: Testing Low and High Side Driver and MOSFET As an example, the high side driver/MOSFET of phase B is tested. In figure 6.10, the voltage measured with the oscilloscope is displayed. The PWM frequency is 15.6kHz with a the duty cycle of 100/256. The supply voltage is set to 12.02V and a current of 0.04A flows through the device.

Figure 6.10: Oscilloscope Measurement

Chapter 7

Synchronous Rectification The Synchronous Rectification is an advanced commutation mode to obtain a more refined control. The operating mode is described in section 3.7 and simulated in 5.4. The current flows through the MOSFETs instead of the diode when the high side transistor is open. As the MOSFETs generally have lower conduction losses than the flyback diode, the efficiency can be increased by using the synchronous rectification. Another advantage of SR is that it allows the current to change direction within a given PWM period. Therefore, the motor becomes more reactive and dynamic. This chapter explains the implementation of SR and its most important settings, such as PWM signals and dead time.

7.1

Precedent Problem

When driving the motor at low velocities and with a low PWM frequency, the following problem emerges. During the PWM off time, the voltage at the floating phase is not always zero. As pictured in figure 7.1, the voltage changes after a while, but it does not equal zero. To measure this, the PWM frequency is 3.9kHz and the duty cycle 50/256.

Figure 7.1: Voltage at Phase B This problem occurs because the inductor is discharged and the diode voltage is connected to the phase. When using synchronous rectification, this problem disappears because the phase is directly connected to the ground.

7.2

Implementation of SR

Some different commutations have been programmed and tested to study the influences of synchronous rectification. The drivers of the AVRMC100 board are used because they do not work inversely. So they close the MOSFET by receiving a 39

40

CHAPTER 7. SYNCHRONOUS RECTIFICATION

one. The microcontroller AT90PWM3B of the STK 520 evaluation board is used to generate the instruction signals for the drivers. The position is measured by three Hall sensors, which transmit the measurements to the STK500 evaluation board. This experimental setting is illustrated in 7.2. STK 500 #S232

MC 100 Po'er sta%e

STK 520

A

#&

B

T&

C

M

Drivers Brid%e #S232

AT90PWM3B AT90PWM3 (not used)

3 ha sensors !C "#$D

Figure 7.2: Experimental Set-Up

7.2.1

Testprogram

First, a simple PWM commutation is programmed to test the experimental set-up. Therefore, the two ramp mode is chosen. However, only the output compare registers OCRnSA and OCRnRA are used while OCRnSB and OCRnRB are set to zero. The construction of the signal is pictured in figure 7.3.

Figure 7.4: Measurement

Figure 7.3: Simple PWM After programming and activating the motor, the voltage on phase B is measured, and it is illustrated on the oscilloscope in figure 7.4. The duty cycle is set to 50/256. The measured ∆t is the on time of the transistor. A PWM cycle should be 64.1 µs, and the corresponding on time is 12.52 µs. The measurement is not precise, so the measured 12.80µs corresponds well to the theoretical value.

41

7.2. IMPLEMENTATION OF SR

7.2.2

PWM

Three programs with different PWM frequencies have been tested. When setting the counting value of PSC cycle to 2048, the clocks have been set as follows to achieve the different PWM frequencies: PLL

PSC input

PSC Prescaler

PWM Frequency

Test 1

32 MHz

PLL / 1 = 32 MHz

PSC / 1 = 32 MHz

32 MHz / 2048 = 15.625 kHz

Test 2

64 MHz

PLL / 1 = 64 MHz

PSC / 4 = 16 MHz

16 MHz / 2048 = 7.8125 kHz

Test 3

32 MHz

PLL / 1 = 32 MHz

PSC / 4 = 8 MHz

8 MHz / 2048 = 3.90625 kHz

The PWM signal is built with the 2 ramp mode, described in 6.1.1. One PWM Cycle lasts 1 / PWM frequency: Test Number 1 2 3

7.2.3

PWM Cycle 1 / 15.625 kHz = 1 / 7.8125 kHz = 1 / 3.90625 kHz =

64 µs 128 µs 256 µs

Dead Time

The MOSFETs on the ATAVRMC100 are SUD35N05-26L of Vishay with characterstics: Turn-On Delay Time Rise Time 2 Turn-Off Delay Time 3 Fall Time

8 ns 30 ns 30 ns 150 ns

This results in a dead time of 218 ns. To safely avoid a short circuit, the chosen dead time is 250 ns, which corresponds to a counting value of 8 for test 1, 4 for test 2, and 2 for test 3.

7.2.4

Position Control

An interrupt on the analog comparator output toggle is applied when the Hall sensors detect a sector change. The program enters a subroutine that reads the analog comparator output bits. During this subroutine, the bits in the PSC configuration register are set so that the PSC cycle cannot be disturbed. There are seven different cases that are implemented, six steps and one default case that stops the motor immediately. During one step the high and the low driver/MOSFET of one phase are activated to receive some signals. The low side transistor of the second phase is set to one, so it is closed. All the other transistors are deactivated.

7.2.5

Velocity Control

When a command on the RS-232 is received, the program enters a subroutine and tests eleven cases:

42


Comand r s 0 1 2 3 4 5 + default

Reaction run motor stop motor set duty cycle to 0/256 set duty cycle to 25/256 set duty cycle to 50/256 set duty cycle to 100/256 set duty cycle to 200/256 set duty cycle to 255/256 set old duty cycle + 1/256 set old duty cycle - 1/256 stop motor

The highest velocity is set to 255/256 to avoid complications when generating the PWM signal. By setting the velocity to the preferred value, the on times of both the high side and low side transistors are adjusted.

7.3

Results and Discussion

All three frequencies have been successfully tested, and the motor turned with different velocities. The phase voltages and the signals sent to the drivers have been measured and illustrated with an oscilloscope. Here, tests 1 and 3 are further analysed.

7.3.1

Test 1

As mentioned before, the PWM frequency is set to 15.6 kHz. Therefore, a PWM cycle lasts 64.1µs. In figure 7.5 the measured voltage on phase A and B with the oscilloscope is pictured when driving the motor with a duty cycle of 50/256.

Figure 7.5: Measurement The velocity of the rotor can be calculated from the duration of the steps. An electrical rotation includes 6 steps and lasts for the chosen duty cycle 11.2 ms. The rotor of the used motor consists of four pole pairs. Therefore, four electrical rotations build a mechanical revolution of the rotor. The corresponding revolutions per minute (RPM) is n =

1 . 4 · ∆t

(7.1)

43

7.3. RESULTS AND DISCUSSION For the example of a 50/256-duty cycle, the RPM becomes n50/256 =

1 = 1339.3 rpm. 4 · 11.2ms

(7.2)

The RPM for the different duty cycles are Command 1 2 3 4 5

Duty Cycle 25/256 50/256 100/256 200/256 255/256

Duration of 6 Steps 22.6 ms 11.2ms 5.52 ms 2.72 ms 2.13 ms

RPM 663.7 rpm 1339.3 rpm 2717.4 rpm 5514.7 rpm 7042.25 rpm

A quadrotor generally works around 3000 rpm. When zooming in the plot, the PWM signal can be viewed and analysed. For the example with the duty cycle of 50/256, the on time should last 6.26 µs and is illustrated in figure 7.6. On the bottom, the signal sent to the driver of power bridge is measured.

Figure 7.6: PWM signals with a Duty Cycle of 50/256 The following current values through the motor and on time of the PWM signals are measured: Command 1 2 3 4 5

Duty Cycle 25/256 50/256 100/256 200/256 255/256

Current 0.08 A 0.10 A 0.14 A 0.24 A 0.29 A

Theoretical On Time 6.26 µs 12.52 µ s 20.04 µ s 50 µs 64.4 µs

Measured On Time 6.4 µs 12.8 µ s 25.6 µ s 50.4 µ s 63.85 µ s

They cannot be measured very precisely with the oscilloscope, but the measured values correspond approximately to the theoretical values.

44

7.3.2


Test 3

Without synchronous rectification, the problem described in 7.1 occurs when driving the motor with low PWM frequencies and low velocities. The SR is tested by setting the PWM frequency to 3.9 kHz. A PWM cycle lasts 256 µ s. The measured voltage on phase A during 6 steps is pictured in figure 7.7. On the bottom, the signal sent to the high side driver of phase A is measured.

Figure 7.7: Phase A and Signal to HA By increasing the resolution of the oscilloscope plot, the PWM signals can be analysed. As it can be seen in the measurement 7.8 with a duty cycle of 50/256, the problem described in 7.1 is corrected. The signal stays at zero volts during the whole off time.

Figure 7.8: Phase A and Signal to HA The measured PWM cycle is 258 µ s. For the different velocities, the following current and off times are measured: Command 1 2 3 4 5

Duty Cycle 25/256 50/256 100/256 200/256 255/256

Current 0.08 A 0.11 A 0.16 A 0.25 A 0.31 A

Theoretical On Time 25 µs 50 µs 100 µs 200 µs 255 µs

Measured On Time 26 µs 52 µs 102 µs 202 µs 256 µs

The corresponding RPM can be calculated with equation (7.1). The RPM for the different duty cycles are

45

7.3. RESULTS AND DISCUSSION Command 1 2 3 4 5

Duty Cycle 25/256 50/256 100/256 200/256 255/256

Duration of 6 Steps 21.7 ms 11 ms 5.4 ms 2.62 ms 2.14 ms

RPM 694.4 rpm 1363.6 rpm 2777.8 rpm 5725.2 rpm 7009.3 rpm

46


Chapter 8

Sensorless Commutation This chapter describes the implementation of synchronous rectification into sensorless commutation. The direct BEMF detection during on time has been previously implemented by Caroline Claasen [1]. In this thesis, the SR implementation is integrated in this existing program.

8.1 8.1.1

Direct BEMF Detection During On Time

The floating phase is analysed and used for BEMF detection. The PWM signal is generated with the centre aligned mode described in section 6.1.1. Two additional compare matches (OCR1B and OCR1A) are required for counting the commutation moment. The fourth unused output compare register of the PSC starts the AD conversion. The converted signal is compared to half of the supply voltage. When the voltage achieves this value, the rotor is in the middle of a commutation step. The time since the last commutation occurred is filtered and set to OCR1B. The counter begins to enumerate again from zero to OSRB1B without disturbance. At the beginning of each step, the signal is not yet stable. Therefore, during counting up to the compare register OCRnA, the ZC is disabled during the first two PWM cycles. In figure 8.1, the operating mode of this implementation is illustrated. Next step

Zero crossing

OCR1B OCR1A hold off

Figure 8.1: ZC Detection During On Time 47

48

CHAPTER 8. SENSORLESS COMMUTATION

8.1.2

During Off Time

The differences between the implementation of the direct BEMF detection during off time and during on time are theoretically not strong. During off time, the measured value has to be compared to the zero voltage. Unfortunately, voltages around zero are always difficult to measure. As marked in figure 8.2, the voltage during off time is sometimes lower than zero. This measured voltage consists of the diode voltage between the ground and the measured phase. This can cause problems by AD conversion of the voltage because of the negative voltage.

0V < 0V

Figure 8.2: Negative Voltage Figure 8.3 shows the ZC detection during off time. The sole difference between the detection during on time is the value for comparison with the zero crossing.

Next step

Zero crossing

OCRnB OCRnA hold off

Figure 8.3: ZC Detection During Off Time

8.1.3

Commutation Filter

When measuring the time between commutation and zero crossing, the time can vary. To decrease the probability of an incorrect time measurement, a digital filter is implemented: tk + 3 · tk 

tk =

4

−1

(8.1)

49

8.2. FINAL IMPLEMENTATION tk is the measured time between commutation and ZC, tk

is the old time. This filter prevents the possibility of an incorrect measurement of the zero crossing, which destroys commutation. 

8.2

−1

Final Implementation

The synchronous rectification is implemented into BEMF detection during on time. The implementation is done with the AT90PWM3B on the STK520 and the power bridge of the board described in 6.5. The experimental set-up is illustrated in figure 8.4. STK 500 PCB Card RS-232

Power stage

STK 520 ISP

A B

RX

M

TX

C Drivers

AT90PWM3B B&M'

Bridge

2! "R#$%D

RS-232

AR&'

Figure 8.4: Experimental Setting The implementation is achieved with several sub-steps. The existing program is adjusted to the board with non-inversed drivers. Then, the synchronous rectification is implemented. The low side transistors are activated by two separately generated signals. To generate synchronous rectification, the opposing PWM signals of the high side transistors are sent to the power bridge. During the conduction steps, the low side transistors should close and receive a 1.

50

CHAPTER 8. SENSORLESS COMMUTATION

Chapter 9

Conclusions and Outlook In this thesis the functionality of the synchronous rectification was presented, and its implementation proved to be successful. The implementation was done for both modes with and without sensors. The synchronous rectification is therefore applicable for the control of the permanent brushless DC motors. For future research in the area of motor control, synchronous rectification can be implemented based on the explanations in this thesis. The next step for future projects would be the implementation with the microcontroller placed on the board. Therefore, the connections could be tested before using the µC. The implementation should be achieved stepwise to avoid possible malfunctions. More measurements could be done to achieve a better understanding of the system. For example, the energy losses avoided due to synchronous rectification could be studied precisely. Additionally, the current flow through the motor could be analysed more precisely to check the performance of the system during commutation.

51

Appendix A

Photos and Schematics A.1 A.1.1

Photos Permanent Magnet Brushless DC-Motor

Figure A.1: Photo of the Motor

52

53

A.1. PHOTOS

A.1.2

PCB

Figure A.2: Backside of the Board

Figure A.3: VD/LPF on Phases

54

A.2

APPENDIX A. PHOTOS AND SCHEMATICS

Schematic Diagram of Card

Appendix B

Codes B.1 B.1.1

1 2 3

With Hall Sensors Scheme A, 2 Ramp Mode, 1 directly on Low

/ / A n d r e a K a t h a r i na F u c h s //ENSMP_CAS //16.04.08

4

//

5 6 7 8

//====>>>> / / p o u r A T 90 P WM 3 B

9

/ / m o di f ie d v e rs i on o f B r u sh l e ss _ H al l _ B_ 1 5 _6 / / c h a n ge s : n o Z C d e t e c ti o n //

10 11 12 13

/ / 2 R am p M od e , w i th o ut S y nc h r on o u s R e ct i fi c at i on , P WM o n H ’ s , 1 on L’s / / W e d on ’ t n ee d t he O CR nS X a nd O CR nR X , s o w e h av e o nl y o ne r am p m od e , m ad e b y O CR nR A

14

15

16

/ / P W M f r eq u en c y o f 1 5. 6 k H z / / H a l l s e n s or s m o de

17 18 19 20 21 22 23 24 25 26 27 28 29

30 31

32

/* * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * ** ** Hall_A === > > ACMP0 == > PD7 = > pin 19 ** Hall_B === > > ACMP1 == > PC6 = > pin 26 ** Hall_C === > > ACMP2 == > PD5 = > pin 17 ** ** ** P ha se _A === > > Ha ut = > P SC 0_A (P SC OU T0 0) == > PD0 = > pin 1 ** Bas = > PSC0_B ( PSCOUT01 ) == > PB7 => pin 32 ** P ha se _B === > > Ha ut = > PS C1 _A (P SC OU T1 0) == > PC0 = > pin 2 ** Bas = > PSC1_B ( PSCOUT11 ) == > PB6 => pin 31

55

56

33

34 35 36 37 38 39

**

APPENDIX B. CODES

Ph as e_ C === > > H aut = > P SC 2_ A ( PS CO UT 20 ) == > PB0 = > pin 12 Bas = > PSC2_B ( PSCOUT21 ) == > PB1 = > pin 13

** ** ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * */

40 41 42 43 44 45

# i n c l u de # i n c l u de # i n c l u de # i n c l u de # i n c l u de

46 47

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Macros * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

48 49 50 51 52 53 54 55

56 57

58 59

60 61 62

63 64

65 66

/ / a c ti v at i o n a nd d e a ct i v at i o n o f p o we r s t ag e t r an s i st o r s : //activation: # d ef in e H _C _O n ( P SO C2 | = _ BV ( P OE N2 A ) ) // # de fi ne L_ C_ On ( PS OC 2 | = _ BV ( PO EN 2B ) ) # d ef in e H _B _O n ( P SO C1 | = _ BV ( P OE N1 A ) ) // # de fi ne L_ B_ On ( PS OC 1 | = _ BV ( PO EN 1B ) ) # d ef in e H _A _O n ( P SO C0 | = _ BV ( P OE N0 A ) ) // # de fi ne L_ A_ On ( PS OC 0 | = _ BV ( PO EN 0B ) ) //deactivation: # d e fi n e H _ C_ O ff ( P S OC 2 & = ~ _ B V ( P O EN 2 A ) ) / / # de fi ne L _ C_ Of f ( P SO C2 & = ~ _ BV ( P OE N2 B ) ) # d e fi n e H _ B_ O ff ( P S OC 1 & = ~ _ B V ( P O EN 1 A ) ) / / # de fi ne L _ B_ Of f ( P SO C1 & = ~ _ BV ( P OE N1 B ) ) # d e fi n e H _ A_ O ff ( P S OC 0 & = ~ _ B V ( P O EN 0 A ) ) / / # de fi ne L _ A_ Of f ( P SO C0 & = ~ _ BV ( P OE N0 B ) )

67 68 69 70 71

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Def inition of Cons tants * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

72 73 74 75 76

/ / _ _ _ _ _ _ _ _ __ _ V a l u es f o r P S C : _ _ _ _ _ _ _ _ __ # d e fi n e va l _ de a d _t i m e_ H a ut 4 # d ef in e v a l_ d ea d_ t im e_ b as 4 # define pe rio d_OC Rnr A 2048 // W e c ou nt up to 2 04 8

77 78

/ / _ _ __ _ _ __ _ b u ff e r s i ze s f or U A RT c o m mu n i ca t i on : _ _ _ _ __ _ _

79 80 81

# d e fi n e T X _ BU F _S I Z E 6 4 # d e fi n e R X _ BU F _S I Z E 1 6

82 83 84 85 86

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Dec larat ion of Variable s * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

87 88 89

c h a r v a r _ O C S A ; // d u ty c y cl e

B.1. WITH HALL SENSORS

57

90 91

/ / _ _ _ _ _ _ _ _ __ _ _ U A R T c o m m u n i c a t i o n : _ _ _ _ _ _ _ _ __ _ _ _

92 93 94 95 96

volatile volatile volatile volatile

uint8_t uint8_t uint8_t int32_t

tx_head ; tx_tail ; tx_buf [ TX _BUF_ SIZE ]; data [ RX_BU F_SIZ E];

97 98 99 100 101

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Decl arat ion of function prot otypes * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

102 103 104

/ / i n i t i a l i s a t i on s u b r o u ti n e void init(void);

105 106

107 108

109 110

111 112 113 114 115

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s R B w i t h P WM p e ri o d i n l i ne v o i d M A J _ O C R n SA ( c h a r ) ; / / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " v a l_ S A " / / i n l i ne v oi d M A J _O C R nS B ( c h ar ) ; w e d o nt n e ed i t / / s u br o u ti n e f or c o m mu t at i o n ( a t c h an g e o f H a ll s e ns o r signals) i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) ; / / s u br o ut i ne t o s t ar t m o to r i n li n e v o id r un ( v o id ) ; / / s u br o ut i ne t o s t o p m o to r i n li n e v o id s t op ( v o id ) ;

116 117 118 119

/ / s u b ro u ti n e s f or U A RT t r a ns m is s i on v oi d p u tc c ( u i nt 8 _t c ) ; v oi d U A RT _ p ri n ts t r ( c o ns t c ha r * s ) ;

120 121 122 123 124 125 126 127 128 129

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Interru pt Service Routines * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * / / / I n te r r up t o n A n al o g C o m pa r at o r [ 2 .. 1 ] o u tp u t t o gg l e / / = = h al l s en so r h as d et ec te d s ec to r c ha ng e ISR(ANALOG_COMP_2_vect) { AnaComp_Traitement(); }

130 131 132 133 134

ISR(ANALOG_COMP_1_vect) { AnaComp_Traitement(); }

135 136 137 138 139


140 141

/*****************************************************************************/

142 143 144

/ / I n te r r up t o n r e c ep t io n o f c h ar a ct e r v ia U A RT / / c al l ed w h en b u ff e r I D R 0 i s e m pt y

58

145 146 147 148 149 150

151 152 153 154 155 156 157 158

APPENDIX B. CODES

ISR(USART_UDRE_vect) { ui nt 8_ t t mp _t ai l; i f( t x_ he ad = = t x_ ta il ) { U C SR B & = ~ _ B V ( UD R IE ) ; / / d i s a bl e U S A R T _ U D RE _ v e c t interrupt return; } t mp _t ai l = t x_ ta il + 1 ; i f ( t m p_ t ai l > = T X _B U F _S I Z E ) t mp _t ai l = 0 ; t x _t a il = t m p_ t ai l ; U DR = t x _b u f [ t mp _ ta i l ] ; }

159 160 161 162 163 164 165

/*****************************************************************************/ / / " U S AR T0 , R x C o mp l et e " ISR(USART_RX_vect) { c ha r c ; c = UDR ;

166 167 168 169

switch(c) { case ’r ’:

170 171 172

run () ; U A R T _ p r in t s t r ( " \ n S t a r t m o t o r " ) ; //putcc(’r’); break;

173 174

c ase ’ s’:

175 176 177

st op () ; U A R T _ p r in t s t r ( " \ n S t o p m o t or " ) ; //putcc(’s’); break;

178 179

c as e ’ 0’ :

180 181 182

M AJ _O CR nS A (0 ); U A R T_ p r in t s tr ( " \ n D ut y c y cl e : 0 ( M I N )" ) ; //putcc(’0’); break;

183 184

c as e ’ 1’ :

185 186 187

M AJ _O CR nS A (2 5) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 2 5 / 2 56 " ) ; //putcc(’1’); break;

188 189

c as e ’ 2’ :

190 191 192

M AJ _O CR nS A (5 0) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 5 0 / 2 56 " ) ; //putcc(’2’); break;

193 194

c as e ’ 3 ’:

195 196 197

M AJ _O CR n SA ( 1 00 ) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 1 0 0 / 2 56 " ) ; //putcc(’3’); break;

198 199

c as e ’ 4 ’:

200 201

M AJ _O CR n SA ( 2 00 ) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 2 0 0 / 2 56 " ) ; //putcc(’4’);


202

59

break;

203

c as e ’ 5 ’:

204 205

206 207

M A J_ OC R nS A ( 25 5) ; U A R T _ p r in t s t r ( " \ n D u t y c y c l e : 2 5 5 / 2 56 (MAX)"); //putcc(’5’); break;

208

c as e ’ +’ :

209 210

211 212 213

M AJ _O CR nS A ( va r_ OC SA + 1 ); U A R T _ p r in t s t r ( " \ n D u t y c y c l e : " ) ; //putcc(’+’); putcc(var_OCSA); break;

214

c as e ’ -’ :

215 216

217 218 219

M AJ _O CR nS A ( va r_ OC SA - 1 ); U A R T _ p r in t s t r ( " \ n P u i s s a n c e m o t e ur : " ) ; //putcc(’-’); putcc(var_OCSA); break;

220

d ef au lt :

221 222

223 224

}

225 226

sto p() ; U A R T _ p r in t s t r ( " \ n M o t o r s t o p pe d : s w i t ch d e fa u lt : " ) ; putcc(c); break;

}

227 228 229 230 231

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Main Program * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

232 233 234 235 236 237 238 239 240 241 242 243 244

245 246 247 248 249 250

i nt m a in ( v o id ) { init(); / / a c t i v a te g l o b al i n t e r r up t s sei(); / / c h a r g e b o o t s tr a p c i r c ui t H_C_Off; H_B_Off; H_A_Off; / / L _ C_ O n ; / / L _ B_ O n ; / / L _ A_ O n ; P O R T B | = _ B V ( P O R T B1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ; // s et L _C , L _B , L _A t o 1 f or l oa di ng t he c a pa ci to r / / PC TL 0 |= _ BV ( P RU N0 ) ; // s ta rt P SC c o un te r _delay_ms(200); stop(); U A R T _ p r in t s t r ( " \ n B o o t s t r a p i n i t i a l i sa t i o n f i n i s he d . " ) ; / / M A J _ O C Rn R B ( ) ; D DR E = 0 x FF ;

251

252 253

while(1) {

254

}

255 256

}

60

APPENDIX B. CODES

257 258 259 260

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / S ubrou tines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

261 262 263 264 265 266 267 268 269 270 271 272 273 274 275

// Initialisation void init(void) { / / I / O d i r ec t io n s / / d ef in e p in s c on ne ct ed t o p ow er s t ag e as o u tp ut s //TXD,H_A, D D RD = 0 b 0 0 00 1 0 01 ; //H_B, D D RC = 0 b 0 0 00 0 0 01 ; / / L_ A , L _B , H _C , L _C D D RB = 0 b 1 1 00 0 0 11 ; D DR E = 0 x 00 ; / / d e fi n e s t an d ar d p o rt o u tp u ts : P OR TE = 0 x 00 ; P O RT D | = 0 x 0 0 ; P O RT C | = 0 x 0 0 ; P O RT B | = 0 x 0 0 ;

276 277 278

279 280 281 282

/ / _ _ _ _ _ _ _ __ I n i t i a li s e UART:_____________________________________ / / A c ti v at i o n of U A RT r e c ei v er a n d i nt e rr u pt o n U AR T r e ce i ve / /8 b it , n o p a ri ty , 1 s to p b it , U CP OL = 0 , 3 8 40 0 b a ud s U C SR B |= _B V ( R XC I E ) | _B V ( R XE N ) | _B V ( T XE N ) ; U BR R = 2 5;

283 284

285 286 287 288

289 290 291

/ / _ _ _ _ _ _ _ __ I n i t i a li s e A n a l og Comparators:_______________________ / / a n al o g co m p ar a to r s co n n ec t ed to Ha l l s e ns o rs / / e n ab l e c o mp a r at o r s / / n e ga t iv e i n pu t : " V r ef " / 2 . 13 / / i nt er r up t o n o u tp ut t og gl e ( a c ti va te d w h en t h e m ot or i s started) A C 2C O N | = _ BV ( A C 2E N ) | _ BV ( A C 2 M1 ) ; A C 1C O N | = _ BV ( A C 1E N ) | _ BV ( A C 1 M1 ) ; A C 0C O N | = _ BV ( A C 0E N ) | _ BV ( A C 0 M1 ) ;

292 293 294 295 296 297 298

/ / _ _ _ _ _ _ _ __ I n i t i a li s e D i g i ta l I n p ut R e g i s te r : _ _ _ _ _ _ _ _ _ _ / / di s ab l e di g it a l in p ut b u ff e r o n a n al o g pi n s / / t o r e du c e p o we r c o n su m pt i o n / / c or re s po n di n g pi n r eg is te r w il l a lw ay s r ea d as 0 D I DR 1 | = _ BV ( A C M P0 D ) | _ BV ( A D C 10 D ) ; D I DR 0 | = _ BV ( A D C2 D ) ;

299 300 301 302

/ / _ _ _ _ _ _ _ __ I n i t i a li s e P L L : _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ // F _P LL = 32 M Hz W he n PL LF i s cl ea r / / P L LC S R | = _ BV ( P L LF ) ;

303 304 305 306 307 308

309

/ / _ _ _ _ _ _ _ __ I n i t i a li s e P S C s : _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ / / PS C i np ut c l oc k : PL L = 32 M Hz ( P C LK SE Ln ) ( P LL / 1) / / 2 r am p m od e ( P MO DE n0 = 1) / / P SC o u tp u ts a c ti v e h ig h P CN F2 |= _ BV ( P CL KS EL 2 ) | _B V ( PM OD E2 0 ) | _B V ( PO P2 ) ; / / P O P2 = 1 - > a ct iv e h ig h P CN F1 |= _ BV ( P CL KS EL 1 ) | _B V ( PM OD E1 0 ) | _B V ( PO P1 ) ; / / P O P1 = 1 - > a ct iv e h ig h


61

P CN F0 |= _ BV ( P CL KS EL 0 ) | _B V ( PM OD E0 0 ) | _B V ( PO P0 ) ; / / P OP 0 = 1 - > a ct iv e h ig h

310

311

/ / P SC 0 co m pl e t es a cy c le b e fo r e ha lt o p e ra t i on w h en requested / / PS C 1 a nd P S C 2 s ta rt w i th P S C 0 ( s yn c hr o ni z at i on o f a ll 3 P SC s ) P C TL 2 | = _ BV ( P A R UN 2 ) ; P C TL 1 | = _ BV ( P A R UN 1 ) ; P C TL 0 | = _ BV ( P C C YC 0 ) ;

312

313

314 315 316 317 318 319 320 321 322

/ / s et O CR 2S B O CR 1S B O CR 0S B

co mp ar e r e gi s te r S B Z ER O = 0; = 0; = 0;

/ / s et O CR 2R B O CR 1R B O CR 0R B

co mp ar e r e gi s te r R B Z ER O = 0; = 0; = 0;

323 324 325 326 327 328

/ / i n i ti a l is a t io n o f c o mp a re r eg i st e r R A O C R2 R A = p e r io d _ OC R n rA ; O C R1 R A = p e r io d _ OC R n rA ; O C R0 R A = p e r io d _ OC R n rA ;

329 330 331 332 333 334 335 336 337

/ / up da te c o mp ar e r e gi st e rs S A ( wi th d u ty c y cl e 0 ) MAJ_OCRnSA(0); / / M A J _ O C Rn R B ( ) ; }

338 339

/*****************************************************************************/

340 341

342 343 344 345

346 347 348 349 350 351 352 353 354 355 356 357

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s R B w i t h P WM p e ri o d /* i n l i ne v o i d M A J _ O C R n RB ( v o i d ) { / / l o ck o u tp u t co m pa r e re g is t e rs t o w r it e w it h ou t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ; O C R2 R B = p e r io d _ OC R n rB ; O C R1 R B = p e r io d _ OC R n rB ; O C R0 R B = p e r io d _ OC R n rB ; / / re l ea s e o ut p ut c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ; } */

358 359

/*****************************************************************************/

360 361

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " v a l_ S A "

62

362 363 364

365 366 367 368 369 370 371 372 373 374 375 376

APPENDIX B. CODES

i n li n e v o id M A J _O C Rn S A ( c ha r v a l_ S A ) { / / l o ck o ut p ut c o mp a re r e gi s t er s to w ri t e wi t ho u t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ; O C R2 S A = 8 *( 2 56 - v a l_ S A ) ; O C R1 S A = 8 *( 2 56 - v a l_ S A ) ; O C R0 S A = 8 *( 2 56 - v a l_ S A ) ; v a r_ O CS A = v a l_ S A ; / / re l ea s e ou t pu t c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ; }

377 378

/*****************************************************************************/

379 380

381 382 383 384 385 386 387 388 389

/ / s u br o u ti n e c a ll e d b y i n te r ru p t o n t o gg l e o f a n al o g comparator / / = = c a ll e d w h e n h a ll s e ns o rs h av e d e te c te d s e ct o r c h an g e i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) { u n si g ne d c h ar h a ll C BA ; / / lo c k P SC s y nc h ro a nd o u tp u t c on f i gu r a ti o n r e gi s te r s / / t o w r it e wi t ho u t d i st u r bi n g P SC c yc l e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

390

// r ea d a na lo g c om pa ra to r o ut pu t b it s h al lC BA = ( A CS R & 0 x 07 ) ;

391 392

:

393 394 395 396 397 398 399

400 401 402 403 404 405

/ / c o mm u ta t e a c c or d in g t o d e te c te d s e ct o r : switch(hallCBA) { / / s te p 1 case 0b00000001: H_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_Off; //L_B_Off; H_A_On; //L_A_Off; break;

406 407 408 409 410 411 412

case 0b00000010:

413

414 415

/ / s te p 3 H_C_Off; //L_C_Off; H_B_On; //L_B_Off; H_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; / / c le ar L _C a nd L _B P O R T B | = _ B V ( P O R T B7 ) ; // s et L _A 1 break;

63

B.1.. WITH B.1 WITH HALL HALL SENSOR SENSORS S

416

case 0b00000011:

417 418 419

420

421 422 423 424 425

/ / s te te p 2 H_C_Off; P O R T B & = ~ ( _ B V ( P O R TB TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le l e ar a r L _B _B a nd nd L _A _A / / s et et L _C _C 1 P O R T B | = _ B V ( P O R T B1 B1 ) ; // H_B_On; //L_B_Off; H_A_Off; //L_A_Off; break;

426

case 0b00000100:

427 428 429 430 431

432

433 434 435

/ / s te te p 5 H_C_On; //L_C_Off; H_B_Off; P O R T B & = ~ ( _ B V ( P O R TB TB 1 ) | _ B V ( P O R T B 7 ) ) ; / / c le l e ar a r L _C _C a nd nd L _A _A / / s et et L _B _B 1 P O R T B | = _ B V ( P O R T B6 B6 ) ; // H_A_Off; //L_A_Off; break;

436

case 0b00000101:

437 438 439 440 441

442

443 444 445

/ / s te te p 6 H_C_Off; //L_C_Off; H_B_Off; P O R T B & = ~ ( _ B V ( P O R TB TB 1 ) | _ B V ( P O R T B 7 ) ) ; / / c le l e ar a r L _C _C a nd nd L _A _A / / s et et L _B _B 1 P O R T B | = _ B V ( P O R T B6 B6 ) ; // H_A_On; //L_A_Off; break;

446

case 0b00000110:

447 448 449 450 451 452 453

454

455

/ / s te te p 4 H_C_On; //L_C_Off; H_B_Off; //L_B_Off; H_A_Off; P O R T B & = ~ ( _ B V ( P O R TB TB 1 ) | _ B V ( P O R T B 6 ) ) ; / / c le l e ar a r L _C _C a nd nd L _B _B / / s et et L _A _A 1 P O R T B | = _ B V ( P O R T B7 B7 ) ; // break;

456

default :

457 458

459

stop () ; U A R T _ p r in in t s t r ( " S w i t c h d e f a u lt lt : H a l l s e n s or or o u t p ut ut s . " ) ; break;

460

}

461 462

/ / re r e l ea ea s e PS PS C s yn yn c hr h r o a nd nd o u tp tp u t c on on f i gu g u r a ti ti o n r eg e g i st st e r s t o u p da da t e t h em em : P C NF NF 2 & = ~ _ B V ( PL P L O CK CK 2 ) ; P C NF NF 1 & = ~ _ B V ( PL P L O CK CK 1 ) ; P C NF NF 0 & = ~ _ B V ( PL P L O CK CK 0 ) ;

463

464 465 466 467

}

64

APPENDIX APPENDIX B. CODES

468 469

/*****************************************************************************/

470 471 472 473 474 475 476 477 478 479 480 481 482

/ / s u b r o ut u t i ne ne t o s t a r t m o t o r i n li li n e v o i d r un u n ( v o id id ) { / / ac a c t iv i v a te t e i n t er e r r up u p t on o n a n al al o g co c o m p ar ar a to t o r o u tp tp u t to t o g gl gl e : A C 2C 2 C O N | = _ BV B V ( A C 2I 2I E ) ; A C 1C 1 C O N | = _ BV B V ( A C 1I 1I E ) ; A C 0C 0 C O N | = _ BV B V ( A C 0I 0I E ) ; / / s t ar ar t P SC S C c o un u n t er er s : P C TL TL 0 | = _ BV B V ( P R UN UN 0 ) ; / / C o mm m m u t at at e : AnaComp_Traitement(); }

483 484

/*****************************************************************************/

485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500

501 502 503

/ / s u b r o ut u t i ne n e t o s t o p m o to to r i n li l i n e v o id id s t op op ( v o id id ) { / / de d e a c ti ti v at a t e i n te t e r ru r u p t on on a n al al o g c om om p a ra ra t or o r o u t pu pu t t og o g g le le : A C 2C 2 C O N & = ~ _ BV B V ( A C 2 IE IE ) ; A C 1C 1 C O N & = ~ _ BV B V ( A C 1 IE IE ) ; A C 0C 0 C O N & = ~ _ BV B V ( A C 0 IE IE ) ; / / s wi w i tc t c h o ff ff al al l 6 tr t r an a n s is is to to r s : H_C_Off; //L_C_Off; H_B_Off; //L_B_Off; H_A_Off; //L_A_Off; et L _C _C , P O R T B & = ~ ( _ B V ( P O R TB TB 1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B7 B 7 ) ) ; / / s et L _B _B , L _A _A t o Z ER ER O / / s to t o p P SC SC c ou o u nt n t er er s : P C TL TL 0 & = ~ _ B V ( PR P R U N0 N0 ) ; }

504 505

/*****************************************************************************/

506 507 508

void putcc ( uint8_t {

c)

509

uint8_t tmp_head ; t mp m p _h _ h ea e a d = t x_ x _ he h e ad ad + 1 ; i f ( t m p_ p _ h ea e a d > = T X _B _ B U F _S _S I Z E ) t mp m p _h _ h ea ea d = 0 ;

510 511 512 513 514

i f( f ( t mp m p _h _ h ea e a d = = t x_ x _ ta t a il il ) return;

515 516 517

t x_ x _ bu b u f [ t x_ x _ he h e ad a d = t mp m p _h _ h ea ea d ] = c ;

518 519

U C SR SR B | = _ BV B V ( U D RI RI E ) ;

520 521

}

522 523 524

/*****************************************************************************/ v o id id U A R T_ T_ p r in in t s tr tr ( c o n st s t c ha ha r * s )

B.1.. WITH B.1 WITH HALL HALL SENSOR SENSORS S

525

{ w h il il e ( * s ) { i f ( *s * s = = ’ \n \n ’ ) putcc(’\r’); putcc(*s++); }

526 527 528 529 530 531 532

}

65

66

B.1.2

1 2 3

APPENDIX B. CODES

SR, 2 Ramp Mode, 15.6 kHz


4

//

5 6 7 8

//====>>>> / / f o r A T 90 P W M3 B

9

/ / m o di f ie d v e rs i on o f 2 _ r am p _ mo d e //

10 11 12

/ / 2 R a mp M od e , w it h S y n ch r o no u s R e c ti f i ca t i on // P WM o n H ’ s, o pp os ed P WM o n L ’ s, 1 o n L ’ s w h en L ow

13 14 15

/ / P W M f r eq u e nc y o f 1 5 . 6 k Hz / / H a l l s e n s or s m od e

16 17 18 19 20 21 22 23 24 25 26 27 28

29 30

31 32

33

34 35 36 37 38

/* * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * ** ** Hall_A === > > ACMP0 == > PD7 => pin 19 ** Hall_B === > > ACMP1 == > PC6 => pin 26 ** Hall_C === > > ACMP2 == > PD5 => pin 17 ** ** ** Ph as e_ A === > > H aut = > PS C0 _A (P SC OU T0 0) == > PD0 = > pin 1 ** Bas = > PSC0_B ( PSCOUT01 ) == > PB7 = > pin 32 ** Ph as e_ B === > > H aut = > P SC 1_ A ( PS CO UT 10 ) == > PC0 = > pin 2 ** Bas = > PSC1_B ( PSCOUT11 ) == > PB6 = > pin 31 ** Ph as e_ C === > > H aut = > P SC 2_ A ( PS CO UT 20 ) == > PB0 = > pin 12 ** Bas = > PSC2_B ( PSCOUT21 ) == > PB1 = > pin 13 ** ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * */

39 40 41 42 43 44


45 46 47 48 49

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Macros * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

50 51 52

/ / a c ti v at i o n a nd d e a ct i v at i o n o f p o we r s t ag e t r an s i st o r s : //activation:

67


53 54 55 56 57 58 59 60 61 62 63 64 65

# d ef in e H _ C _O n ( P SO C2 # d ef in e L _ C _O n ( P SO C2 # d ef in e H _ B _O n ( P SO C1 # d ef in e L _ B _O n ( P SO C1 # d ef in e H _ A _O n ( P SO C0 # d ef in e L _ A _O n ( P SO C0 //deactivation: # d e fi n e H _ C_ O ff ( P S OC 2 # d e fi n e L _ C_ O ff ( P S OC 2 # d e fi n e H _ B_ O ff ( P S OC 1 # d e fi n e L _ B_ O ff ( P S OC 1 # d e fi n e H _ A_ O ff ( P S OC 0 # d e fi n e L _ A_ O ff ( P S OC 0

|= |= |= |= |= |=

_ BV ( P OE N2 A ) ) _ BV ( P OE N2 B ) ) _ BV ( P OE N1 A ) ) _ BV ( P OE N1 B ) ) _ BV ( P OE N0 A ) ) _ BV ( P OE N0 B ) )

&= &= &= &= &= &=

~ _ B V ( P O EN 2 A ) ) ~ _ B V ( P O EN 2 B ) ) ~ _ B V ( P O EN 1 A ) ) ~ _ B V ( P O EN 1 B ) ) ~ _ B V ( P O EN 0 A ) ) ~ _ B V ( P O EN 0 B ) )

66 67 68 69 70

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Defi nition of Const ants * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

71 72

/ / _ _ _ _ _ _ __ V a l u es f o r P S C : _ _ _ _ _ _ _ _ _ _ __ _ _

73 74 75 76 77

// # de fi ne v al _d ea d_ ti me _H au t 4 / / # d e f i ne v a l _ d e a d _t i m e _ b a s 4 # define dead_time 8 // 2 50 n s # define period 2048 // W e c ou nt u p t o 2 0 48

78 79

/ / _ _ __ _ __ b u ff e r s i ze s f or U A RT c o m mu n i ca t i on : _ _ _ _ __ _ __ _

80 81 82


83 84 85 86 87

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Decl arat ion of Variables * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

88 89

c ha r d _ c ; // d u ty c y cl e

90 91 92

/ / _ _ _ _ _ _ __ U A R T c o m m u n i c a t i o n : _ _ _ _ _ _ _ __ _ _

93 94 95 96 97




98 99 100 101 102


103 104 105


106 107

108

/ / s ub ro u ti ne t o u pd at e P SC o ut pu t c om pa re r eg is te rs R A a nd R B w it h n ew d ut y c yc le d _c i n l i ne v o i d M A J _ P W M ( c h a r ) ;

68

109

110 111 112 113 114

APPENDIX B. CODES

/ / s u br o u ti n e f or c o m mu t at i o n ( a t c h an g e o f H a ll s e ns o r signals) i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) ; / / s u br o ut i n e t o s t ar t m o to r i n li n e v o id r un ( v o id ) ; / / s u br o ut i n e t o s to p m o to r i n li n e v o id s t op ( v o id ) ;

115 116 117 118

/ / s u b ro u ti n e s f or U A RT t r a ns m i ss i o n v o id p u tc c ( u i nt 8 _t c ) ; v o id U A R T_ p r in t s tr ( c o n st c ha r * s ) ;

119 120 121 122 123 124 125 126 127 128

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Interr upt Service Routines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * / / / I n te r r up t o n A n al o g C o m pa r at o r [ 2 .. 1 ] o u tp u t t o gg l e / / = = h al l s e ns o r h a s d e te c te d s e ct o r c h an g e ISR(ANALOG_COMP_2_vect) { AnaComp_Traitement(); }

129 130 131 132 133


134 135 136 137 138


139 140

/*****************************************************************************/

141 142 143 144 145 146 147 148 149

150 151 152 153 154 155 156 157

/ / I n te r r up t o n r e c ep t io n o f c h ar a ct e r v ia U A RT / / c al l ed w h en b u ff e r I D R 0 i s e m pt y ISR(USART_UDRE_vect) { ui nt 8_ t t mp _t ai l; i f( t x_ he ad = = t x_ ta il ) { U C SR B & = ~ _ B V ( UD R IE ) ; / / d i s a bl e U S A R T _ U D RE _ v e c t interrupt return; } t mp _t ai l = t x_ ta il + 1 ; i f ( t m p_ t ai l > = T X _B U F _S I Z E ) t mp _t ai l = 0 ; t x _t a il = t m p_ t ai l ; U DR = t x _b u f [ t mp _ ta i l ] ; }

158 159 160 161 162 163 164

/*****************************************************************************/ / / " U S AR T0 , R x C o mp l et e " ISR(USART_RX_vect) { c h ar c c ; cc = U DR ;


165 166 167 168

switch(cc) { ca se ’ r’:

169 170 171


172 173

ca se ’ s’:

174 175 176

sto p() ; U A R T _ p r in t s t r ( " \ n S t o p m o t o r " ) ; //putcc(’s’); break;

177 178

c as e ’ 0’ :

179 180 181

M AJ _P WM ( 0) ; U A RT _ p ri n ts t r ( " \ n Du t y c y cl e : 0 ( M I N )" ) ; //putcc(’0’); break;

182 183

c as e ’ 1’ :

184 185 186

M AJ _P WM ( 25 ); U A R T _ p r in t s t r ( " \ n D u t y c y c l e : 2 5 / 2 56 " ) ; //putcc(’1’); break;

187 188

c as e ’ 2’ :

189 190 191


192 193

c as e ’ 3’ :

194 195 196

M AJ _P WM ( 10 0) ; U A R T _ p r in t s t r ( " \ n D u t y c y c l e : 1 0 0 / 2 56 " ) ; //putcc(’3’); break;

197 198

c as e ’ 4’ :

199 200 201


202 203

c as e ’ 5’ :

204

205 206

M AJ _P WM ( 25 5) ; U A R T _ p r in t s t r ( " \ n D u t y c y c l e : 2 5 5 / 2 56 (MAX)"); //putcc(’5’); break;

207 208

ca se ’ +’:

209 210 211 212

M AJ _P WM ( d_c + 1) ; U A R T _ p r in t s t r ( " \ n D u t y c y c l e : " ) ; //putcc(’+’); putcc(d_c); break;

213 214

ca se ’ -’:

215 216 217 218

M AJ _P WM ( d_c - 1) ; U A R T _ p r in t s t r ( " \ n P u i s s a n c e m o t e ur : " ) ; //putcc(’-’); putcc(d_c); break;

219 220

d ef au lt :

sto p() ;

69

70

APPENDIX B. CODES

221

222 223

}

224 225

U A R T _ p r in t s t r ( " \ n M o t o r s t o p pe d : s w i t ch d e fa u lt : " ) ; putcc(cc); break;

}

226 227 228 229 230

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Main Program * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

231 232 233 234 235 236 237 238 239 240

241 242 243

244 245

i n t m a i n ( v oi d ) { init(); / / a c t i v a te g l o b al i n t e r r up t s sei(); / / c h a r g e b o o t s tr a p c i r c ui t H_C_Off; H_B_Off; H_A_Off; P O R T B | = _ B V ( P O R T B1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ; // s et L _C , L_ B , L _A t o 1 f or l oa di ng t he c ap ac it or / / PC TL 0 |= _ BV ( P RU N0 ) ; // s ta rt P SC c o un te r _delay_ms(200); s t o p ( ) ; // s to ps m ot or a nd s et s L _C , L _B a ns L _A Z ER O a nd s t op s P SC c o un t er U A R T _ p r in t s t r ( " \ n B o o t s t r a p i n i t i a l i sa t i o n f i n i s he d . " ) ; D DR E = 0 x FF ;

246

247 248

while(1) {

249

}

250 251

}

252 253 254 255

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / S ubrou tines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

256 257 258 259 260 261 262 263 264 265 266 267 268 269 270


271 272 273 274 275

/ / _ _ _ _ _ _ _ __ I n i t i a li s e U A R T : _ _ _ _ _ _ _ __ _ _ _ / / A c ti v at i o n of U A RT r e c ei v er a n d i nt e rr u pt o n U AR T r e ce i ve / /8 b it , n o p a ri ty , 1 s to p b it , U CP OL = 0 , 3 8 40 0 b a ud s


71

U C SR B |= _B V ( R XC I E ) | _B V ( R XE N ) | _B V ( T XE N ) ; U BR R = 2 5;

276 277 278

/ / _ _ _ _ _ _ _ __ I n i t i a li s e A n a l og C o m p a r at o r s : _ _ _ _ _ _ _ / / a n al o g co m p ar a to r s co n ne c t ed to Ha l l s e ns o rs / / e n ab l e c o mp a r at o r s / / n e ga t iv e i n pu t : " V r ef " / 2 . 13 / / i nt er ru p t o n o ut pu t t o gg le ( a c t iv at ed w he n t he m o t or i s started) A C 2C O N | = _ BV ( A C 2E N ) | _ BV ( A C 2 M1 ) ; A C 1C O N | = _ BV ( A C 1E N ) | _ BV ( A C 1 M1 ) ; A C 0C O N | = _ BV ( A C 0E N ) | _ BV ( A C 0 M1 ) ;

279 280 281 282 283

284 285 286 287

/ / _ _ _ _ _ _ _ __ I n i t i a li s e D i g i ta l I n p ut R e g i s te r : _ _ _ _ _ / / di sa bl e d ig it al i n pu t b uf fe r on a n al og p i ns / / t o r e du c e p o we r c o n su m pt i o n / / c or re s po n di n g pi n r eg is te r w il l a lw ay s r ea d as 0 D I DR 1 | = _ BV ( A C M P0 D ) | _ BV ( A D C 10 D ) ; D I DR 0 | = _ BV ( A D C2 D ) ;

288 289 290 291 292 293 294

/ / _ _ _ _ _ _ _ __ I n i t i a li s e P L L : _ _ _ _ _ _ __ _ _ // F _P LL = 32 M Hz W he n PL LF i s cl ea r / / P L LC S R | = _ BV ( P L LF ) ;

295 296 297 298

/ / _ _ _ _ _ _ _ __ I n i t i a li s e P S C s : _ _ _ _ __ _ / / PS C i np ut c l oc k : PL L = 32 M Hz ( P C LK SE Ln ) ( P LL / 1) / / 2 r am p m od e ( P MO DE n0 = 1) / / P SC o u tp u ts a c ti v e h i gh P CN F2 |= _ BV ( P CL KS EL 2 ) | _B V ( PM OD E2 0 ) | _B V ( PO P2 ) ; / / P OP 2 = 1 - > a ct iv e h ig h P CN F1 |= _ BV ( P CL KS EL 1 ) | _B V ( PM OD E1 0 ) | _B V ( PO P1 ) ; / / P OP 1 = 1 - > a ct iv e h ig h P CN F0 |= _ BV ( P CL KS EL 0 ) | _B V ( PM OD E0 0 ) | _B V ( PO P0 ) ; / / P OP 0 = 1 - > a ct iv e h ig h

299 300 301 302 303

304

305

306

/ / P SC 0 co m pl e t es a cy c le b e fo r e ha lt o p e ra t i on w h en requested / / PS C 1 a nd P S C 2 s ta rt w i th P S C 0 ( s yn c hr o ni z at i on o f a ll 3 P SC s ) P C TL 2 | = _ BV ( P A R UN 2 ) ; P C TL 1 | = _ BV ( P A R UN 1 ) ; P C TL 0 | = _ BV ( P C C YC 0 ) ;

307

308

309 310 311 312 313

/ / s et c om pa re r e gi s te r SB to d ea d ti me / / O CR 2 SB = d e a d_ t im e ; / / O CR 1 SB = d e a d_ t im e ; / / O CR 0 SB = d e a d_ t im e ;

314 315 316 317 318

/ / s et c om pa re r e gi s te r SA to d ea d ti me / / O CR 2 RB = d e a d_ t im e ; / / O CR 1 RB = d e a d_ t im e ; / / O CR 0 RB = d e a d_ t im e ;

319 320 321 322 323 324 325 326 327

/ / up d at e c om p ar e r eg i st e r s ( w i th d ut y cy c le 0) MAJ_PWM(0); }

72

APPENDIX B. CODES

328 329

/*****************************************************************************/

330 331

332 333 334

335 336 337

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " o n ti m e " i n li n e v o id M A J_ P WM ( c h a r o n ti m e ) { / / l o ck o ut p ut c o mp a re r e gi s t er s to w ri t e wi t ho u t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

338 339

340 341 342 343

i f ( o n t i m e = = 0 ) / / o ne r am p t o p er io d , n o s ig na l o n H ig h a nd Lo w { OCR2RA=period; OCR1RA=period; OCR0RA=period;

344 345 346 347

OCR2SA=period; OCR1SA=period; OCR0SA=period;

OCR2RB=0; OCR1RB=0; OCR0RB=0;

OCR2SB=0; OCR1SB=0; OCR0SB=0;

348 349 350 351 352 353 354 355 356

357

d_c=ontime; }

358 359 360

else {

361 362 363 364 365

/ / s et O C R2 S A O C R1 S A O C R0 S A

c om pa re r eg is te r S A t o d ea d t im e = d e ad _ t im e ; = d e ad _ t im e ; = d e ad _ t im e ;

/ / s et O C R2 S B O C R1 S B O C R0 S B

c om pa re r eg is te r S B t o d ea d t im e = d e ad _ t im e ; = d e ad _ t im e ; = d e ad _ t im e ;

/ / s et O C R 2 RA O C R 1 RA O C R 0 RA

co mp ar e r eg is te r R A t o d ea d t im e p lu s d ut y c yc le = d e a d _ t im e + ( 8 * o n t i m e ) ; = d e a d _ t im e + ( 8 * o n t i m e ) ; = d e a d _ t im e + ( 8 * o n t i m e ) ;

/ / s et O C R 2 RB O C R 1 RB O C R 0 RB

c om pa re r eg is te r R B t o p er io d m in us R A = p e ri o d - ( d e a d _ t i me + ( 8 * o n t i m e ) ) ; = p e ri o d - ( d e a d _ t i me + ( 8 * o n t i m e ) ) ; = p e ri o d - ( d e a d _ t i me + ( 8 * o n t i m e ) ) ;

366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382

d_c=ontime;

73


} / / re l ea s e o ut p ut c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

383 384 385 386 387 388

}

389 390

/*****************************************************************************/

391 392

393 394 395 396 397 398 399 400 401

/ / s u b r o ut i ne c a ll e d b y i n te r ru p t o n t o gg l e o f a n al o g comparator / / = = c a ll e d w h e n h a ll s e ns o rs h a ve d e te c te d s e ct o r c h an g e i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) { u n si g ne d c h ar h a ll C BA ; / / lo ck P SC s y nc h ro a n d o u tp u t c on f i gu r a ti o n r e gi s te r s / / t o w r it e wi t ho u t d i st u r bi n g P SC c yc l e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

402


403 404

:

405 406 407 408 409 410 411 412

413 414 415 416 417 418

/ / c o mm u t at e a c co r d in g t o d e te c te d s e ct o r : switch(hallCBA) { / / s te p 1 case 0b00000001: H_C_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_Off; L_B_Off; H_A_On; L_A_On; break;

419 420 421 422 423 424

case 0b00000010:

425

426 427 428 429

/ / s te p 3 H_C_Off; L_C_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; / / c le ar L _C a nd L _B P O R T B | = _ B V ( P O R T B7 ) ; // s et L _A 1 H_B_On; L_B_On; break;

430 431 432 433

case 0b00000011:

434

435 436

/ / s te p 2 H_C_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_On;

74

APPENDIX B. CODES

437 438 439 440

L_B_On; H_A_Off; L_A_Off; break;

441

case 0b00000100:

442 443 444 445

446

447 448 449 450 451

/ / s te p 5 H_B_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _C a nd L _A P O R T B | = _ B V ( P O R T B6 ) ; // s et L _B 1 H_A_Off; L_A_Off; H_C_On; L_C_On; break;

452

case 0b00000101:

453 454 455 456 457 458

459

460 461 462

/ / s te p 6 H_C_Off; L_C_Off; H_B_Off; H_B_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _C a nd L _A P O R T B | = _ B V ( P O R T B6 ) ; // s et L _B 1 H_A_On; L_A_On; break;

463

case 0b00000110:

464 465 466 467 468 469

470

471 472 473

/ / s te p 4 H_B_Off; L_B_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; / / c le ar L _C a nd L _B P O R T B | = _ B V ( P O R T B7 ) ; // s et L _A 1 H_C_On; L_C_On; break;

474

default :

475 476

477

stop () ; U A R T _ p r in t s t r ( " S w i t c h d e f a u lt : H a l l s e n s or o u t p u ts . " ) ; break;

478

}

479 480

/ / re l ea s e PS C s yn c hr o a nd o u tp u t c on f ig u r at i on r e g is t e rs t o u p da t e t h em : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

481

482 483 484 485

}

486 487

/*****************************************************************************/

488 489

/ / s u b r o ut i ne t o s t a r t m o t o r


490 491 492 493 494 495 496 497 498 499 500

75

i n li n e v o id r un ( v o id ) { / / ac t iv a te i n t er r u pt o n an a lo g c o mp a ra t o r ou t pu t t og g le : A C 2C O N | = _ BV ( A C 2I E ) ; A C 1C O N | = _ BV ( A C 1I E ) ; A C 0C O N | = _ BV ( A C 0I E ) ; / / s t ar t P SC c o un t er s : P C TL 0 | = _ BV ( P R UN 0 ) ; / / C o mm u ta t e : AnaComp_Traitement(); }

501 502

/*****************************************************************************/

503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518

519 520 521

/ / s u b r o ut i ne t o s t o p m o t o r i n li n e v o id s t op ( v o id ) { / / de a c ti v at e i n te r ru p t on a na l og c o m pa r a to r o u tp u t to g gl e : A C 2C O N & = ~ _ BV ( A C 2 IE ) ; A C 1C O N & = ~ _ BV ( A C 1 IE ) ; A C 0C O N & = ~ _ BV ( A C 0 IE ) ; / / s wi tc h of f a ll 6 t ra ns i st or s : H_C_Off; L_C_Off; H_B_Off; L_B_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B7 ) ) ; / / s e t L _C , L _B , L _A t o Z ER O / / s t op P SC c o un t er s : P C TL 0 & = ~ _ B V ( PR U N0 ) ; }

522 523

/*****************************************************************************/

524 525 526

v oi d p u tc c ( u i nt 8 _t c ) {

527

u i n t 8 _t t m p _ h ea d ; t mp _h ea d = t x_ he ad + 1 ; i f ( t m p_ h ea d > = T X _ BU F _ SI Z E ) t m p_ h ea d = 0 ;

528 529 530 531 532

i f( t mp _h ea d = = t x_ ta il ) return;

533 534 535

t x_ bu f [ t x_ he ad = t mp _h ea d ] = c ;

536 537

U C SR B | = _ BV ( U D RI E ) ;

538 539

}

540 541 542 543 544 545 546

/*****************************************************************************/ v oi d U A RT _ p ri n ts t r ( c o ns t c ha r * s ) { w h il e ( * s ) { i f ( *s = = ’ \n ’ )

76

APPENDIX B. CODES

547

548

}

549 550

putcc(’\r’); putcc(*s++);

}


B.1.3

1 2 3

77

SR, 2 Ramp Mode, 7.8 kHz


4

//

5 6 7 8

//====>>>> / / f o r A T 90 P WM 3 B

9

/ / m o di f ie d v e rs i on o f 2 _ r a mp _ m od e _ sr //

10 11 12

/ / 2 R am p M od e , w i th S y n ch r o no u s R e c ti f i ca t i on // P WM o n H ’ s, o pp os ed P WM o n L ’ s, 1 o n L ’ s w h en L ow

13 14 15

/ / P W M f r eq u en c y o f 7 .8 k H z * * ** * ** / / H a l l s e n s or s m o de

16 17 18 19 20 21 22 23 24 25 26 27 28

29 30

31 32

33

34 35 36 37 38

/* * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * ** ** Hall_A === > > ACMP0 == > PD7 = > pin 19 ** Hall_B === > > ACMP1 == > PC6 = > pin 26 ** Hall_C === > > ACMP2 == > PD5 = > pin 17 ** ** ** P ha se _A === > > Ha ut = > P SC 0_A (P SC OU T0 0) == > PD0 = > pin 1 ** Bas = > PSC0_B ( PSCOUT01 ) == > PB7 => pin 32 ** P ha se _B === > > Ha ut = > PS C1 _A (P SC OU T1 0) == > PC0 = > pin 2 ** Bas = > PSC1_B ( PSCOUT11 ) == > PB6 => pin 31 ** P ha se _C === > > Ha ut = > PS C2 _A (P SC OU T2 0) == > PB0 = > pin 12 ** Bas = > PSC2_B ( PSCOUT21 ) == > PB1 => pin 13 ** ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * */

39 40 41 42 43 44


45 46 47 48 49

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Macros * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

50 51 52

/ / a c ti v at i on a nd d e a ct i v at i o n o f p o we r s t ag e t r a ns i s to r s : //activation:

78

53 54 55 56 57 58 59 60 61 62 63 64 65

APPENDIX B. CODES

# d ef in e H _C _O n ( P SO C2 # d ef in e L _C _O n ( P SO C2 # d ef in e H _B _O n ( P SO C1 # d ef in e L _B _O n ( P SO C1 # d ef in e H _A _O n ( P SO C0 # d ef in e L _A _O n ( P SO C0 //deactivation: # d e fi n e H _ C_ O ff ( P S OC 2 # d e fi n e L _ C_ O ff ( P S OC 2 # d e fi n e H _ B_ O ff ( P S OC 1 # d e fi n e L _ B_ O ff ( P S OC 1 # d e fi n e H _ A_ O ff ( P S OC 0 # d e fi n e L _ A_ O ff ( P S OC 0

|= |= |= |= |= |=


&= &= &= &= &= &=


66 67 68 69 70


71 72

/ / _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ V a l u e s f o r PSC:_________________________________________

73 74 75 76 77

// # de fi ne v al _d ea d_ ti me _H au t 4 / / # d e f i ne v a l _ d e a d _t i m e _ b a s 4 # define dead_tim e 4 // 2 50 n s * * # define period 2048 / / W e c o un t u p t o 2 04 8 ( 1 2 8. 2 m i cr o s )

78 79

/ / _ _ _ __ _ _ __ _ _ __ _ _ __ _ _ _ b u ff e r s i ze s f or U AR T communication:___________________

80 81 82


83 84 85 86 87


88 89

c h ar d _c ; // d u ty c y cl e

90 91 92

/ / _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ U A R T c o m m u n i ca t i o n : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _

93 94 95 96 97

volat ile volat ile volat ile volat ile


tx_head ; tx_tail ; tx_buf [ T X_BUF _SIZE ]; data [ RX_B UF_SI ZE ];

98 99 100 101 102

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Dec larat ion of function pro totypes * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

103 104 105 106

// initialisation subroutine void init(void);


107

108 109

110 111 112 113 114

79

/ / s ub ro u ti ne t o u pd at e P SC o ut pu t c om pa re r eg is te rs R A a nd R B w it h n ew d ut y c yc le d _c i n l i ne v o i d M A J _ P W M ( c h a r ) ; / / s u br o u ti n e f or c o m mu t at i o n ( a t c h an g e o f H a ll s e ns o r signals) i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) ; / / s u br o ut i ne t o s t ar t m o to r i n li n e v o id r un ( v o id ) ; / / s u br o ut i ne t o s t o p m o to r i n li n e v o id s t op ( v o id ) ;

115 116 117 118

/ / s u b ro u ti n e s f or U A RT t r a ns m is s i on v oi d p u tc c ( u i nt 8 _t c ) ; v oi d U A RT _ p ri n ts t r ( c o ns t c ha r * s ) ;

119 120 121 122 123 124 125 126 127 128

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Interru pt Service Routines * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * / / / I n te r r up t o n A n al o g C o m pa r at o r [ 2 .. 1 ] o u tp u t t o gg l e / / = = h al l s en so r h as d et ec te d s ec to r c ha ng e ISR(ANALOG_COMP_2_vect) { AnaComp_Traitement(); }

129 130 131 132 133


134 135 136 137 138


139 140

/*****************************************************************************/

141 142 143 144 145 146 147 148 149

150 151 152 153 154 155 156 157

/ / I n te r r up t o n r e c ep t io n o f c h ar a ct e r v ia U A RT / / c al l ed w h en b u ff e r I D R 0 i s e m pt y ISR(USART_UDRE_vect) { uint8_t tmp_tail ; i f( t x_ he ad = = t x_ ta il ) { U C SR B & = ~ _ B V ( UD R IE ) ; / / d i s a b le U S A R T _ U DR E _ v e c t interrupt return; } t mp _t ai l = t x_ ta il + 1 ; i f ( t m p_ t ai l > = T X _ BU F _ SI Z E ) t m p_ t ai l = 0 ; t x _t a il = t m p _t a il ; U DR = t x _b u f [ t m p_ t ai l ] ; }

158 159 160 161

/*****************************************************************************/ / / " U S AR T0 , R x C o mp l et e " ISR(USART_RX_vect)

80

162

APPENDIX B. CODES

{ c h ar c c ; cc = U DR ;

163 164 165 166 167 168

switch(cc) { case ’r ’:

169 170 171


172 173

c ase ’ s’:

174 175 176

st op () ; U A R T _ p r in t s t r ( " \ n S t o p m o t or " ) ; //putcc(’s’); break;

177 178

c as e ’ 0’ :

179 180 181

M AJ _P WM ( 0) ; U A R T_ p r in t s tr ( " \ n D ut y c y cl e : 0 ( M I N )" ) ; //putcc(’0’); break;

182 183

c as e ’ 1’ :

184 185 186

M AJ _P WM ( 25 ); U A R T _ p r in t s t r ( " \ n D u t y c y c le : 2 5 / 2 56 " ) ; //putcc(’1’); break;

187 188

c as e ’ 2’ :

189 190 191

M AJ _P WM ( 50 ); U A R T _ p r in t s t r ( " \ n D u t y c y c le : 5 0 / 2 56 " ) ; //putcc(’2’); break;

192 193

c as e ’ 3’ :

194 195 196

M AJ _P WM ( 10 0) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 1 0 0 / 2 56 " ) ; //putcc(’3’); break;

197 198

c as e ’ 4’ :

199 200 201

M AJ _P WM ( 20 0) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 2 0 0 / 2 56 " ) ; //putcc(’4’); break;

202 203

c as e ’ 5’ :

204

205 206

M AJ _P WM ( 25 5) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : 2 5 5 / 2 56 (MAX)"); //putcc(’5’); break;

207 208

c ase ’ +’:

209 210 211 212

M AJ _P WM ( d_c + 1) ; U A R T _ p r in t s t r ( " \ n D u t y c y c le : " ) ; //putcc(’+’); putcc(d_c); break;

213 214

c ase ’ -’:

215 216 217 218



81

219

d ef au lt :

220 221

222 223

}

224 225

sto p() ; U A R T _ p r in t s t r ( " \ n M o t o r s t o p pe d : s w i t ch d e fa u lt : " ) ; putcc(cc); break;

}

226 227 228 229 230

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Main Program * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

231 232 233 234 235 236 237 238 239 240

241 242 243

244 245

i nt m a in ( v o id ) { init(); / / a c t i v a te g l o b al i n t e r r up t s sei(); / / c h a r g e b o o t s tr a p c i r c ui t H_C_Off; H_B_Off; H_A_Off; P O R T B | = _ B V ( P O R T B1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ; // s et L _C , L _B , L _A t o 1 f or l oa di ng t he c a pa ci to r / / PC TL 0 |= _ BV ( P RU N0 ) ; // s ta rt P SC c o un te r _delay_ms(200); s t o p ( ) ; // s to ps m ot or a nd s et s L _C , L _B a ns L _A Z ER O a nd s t op s P SC c o un t er U A R T _ p r in t s t r ( " \ n B o o t s t r a p i n i t i a l i sa t i o n f i n i s he d . " ) ; D DR E = 0 x FF ;

246

247 248

while(1) {

249

}

250 251

}

252 253 254 255

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Su brout ines * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272

/ / I n i t i a l i s a t i on void init(void) { / / I / O d i r ec t io n s / / de fi ne p i ns c o n ne ct ed t o p ow er s t ag e as o u tp ut s //TXD,H_A, D D RD = 0 b 0 0 00 1 0 01 ; //H_B, D D RC = 0 b 0 0 00 0 0 01 ; / / L_ A , L _B , H _C , L _C D D RB = 0 b 1 1 00 0 0 11 ; D DR E = 0 x 00 ; / / d e fi n e s t a nd a rd p o rt o u tp u ts : P OR TE = 0 x 00 ; P O RT D | = 0 x 0 0 ; P O RT C | = 0 x 0 0 ; P O RT B | = 0 x 0 0 ;

82

273

274 275 276 277

APPENDIX B. CODES

/ / _ _ _ _ _ _ _ __ I n i t i a li s e UART:_____________________________________ / / A c ti v at i o n of U A RT r e c ei v er a n d i nt e rr u pt o n U AR T r e ce i ve / /8 b it , n o p a ri ty , 1 s to p b it , U CP OL = 0 , 3 8 40 0 b a ud s U C SR B |= _B V ( R XC I E ) | _B V ( R XE N ) | _B V ( T XE N ) ; U BR R = 2 5;

278 279

280 281 282 283

284 285 286

/ / _ _ _ _ _ _ _ __ I n i t i a li s e A n a l og Comparators:_______________________ / / a n al o g co m p ar a to r s co n n ec t ed to Ha l l s e ns o rs / / e n ab l e c o mp a r at o r s / / n e ga t iv e i n pu t : " V r ef " / 2 . 13 / / i nt er r up t o n o u tp ut t og gl e ( a c ti va te d w h en t h e m ot or i s started) A C 2C O N | = _ BV ( A C 2E N ) | _ BV ( A C 2 M1 ) ; A C 1C O N | = _ BV ( A C 1E N ) | _ BV ( A C 1 M1 ) ; A C 0C O N | = _ BV ( A C 0E N ) | _ BV ( A C 0 M1 ) ;

287 288

289 290 291 292 293

/ / _ _ __ _ __ _ _ I n i ti a li s e D i gi t al I n pu t Register:___________________ / / di s ab l e di g it a l in p ut b u ff e r o n a n al o g pi n s / / t o r e du c e p o we r c o n su m pt i o n / / c or re s po n di n g pi n r eg is te r w il l a lw ay s r ea d as 0 D I DR 1 | = _ BV ( A C M P0 D ) | _ BV ( A D C 10 D ) ; D I DR 0 | = _ BV ( A D C2 D ) ;

294 295

296 297

/ / _ _ _ _ _ _ _ __ I n i t i a li s e PLL:_____________________________________ // F _P LL = 64 M Hz W he n PL LF i s se t ** * P L LC S R | = _ BV ( P L LF ) ;

298 299

300 301 302 303

304

305

/ / _ _ _ _ _ _ _ __ I n i t i a li s e PSCs:_____________________________________ / / PS C i np ut c l oc k : PL L = 64 M Hz ( P C LK SE Ln ) ( P LL / 1) / / 2 r am p m od e ( P MO DE n0 = 1) / / P SC o u tp u ts a c ti v e h ig h P CN F2 |= _ BV ( P CL KS EL 2 ) | _B V ( PM OD E2 0 ) | _B V ( PO P2 ) ; / / P O P2 = 1 - > a ct iv e h ig h P CN F1 |= _ BV ( P CL KS EL 1 ) | _B V ( PM OD E1 0 ) | _B V ( PO P1 ) ; / / P O P1 = 1 - > a ct iv e h ig h P CN F0 |= _ BV ( P CL KS EL 0 ) | _B V ( PM OD E0 0 ) | _B V ( PO P0 ) ; / / P O P0 = 1 - > a ct iv e h ig h

306 307

308

309

310 311 312

/ / PS C 0 c om pl e te s a c yc le b e fo re h a lt o p e ra ti o n w he n requested / / PS C 1 a nd P S C 2 s ta rt w i th P S C 0 ( s yn c hr o ni za t io n o f a ll 3 P SC s ) / / PS C = 16 M Hz ( P SC i n pu t c lo ck d e v id ed b y 4 ( P LL / 4) ) w he n PPREn0=1 P C TL 2 | = _ BV ( P A R UN 2 ) | _ BV ( P P R E2 0 ) ; P C TL 1 | = _ BV ( P A R UN 1 ) | _ BV ( P P R E1 0 ) ; P C TL 0 | = _ BV ( P C C YC 0 ) | _ BV ( P P R E0 0 ) ;

313 314 315 316 317 318

/ / s et c om pa re r e gi st er S B t o d ea d ti me / / O C R2 S B = d e a d_ t im e ; / / O C R1 S B = d e a d_ t im e ; / / O C R0 S B = d e a d_ t im e ;


83

319


320 321 322 323 324


325 326

327 328 329 330

/*****************************************************************************/

331 332

333 334 335

336 337 338

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " o n ti m e " i n li n e v o id M A J_ P WM ( c h a r o n ti m e ) { / / l o ck o u tp u t co m pa r e re g is t e rs t o w r it e w it h ou t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

339 340

341 342 343 344


345 346 347 348




d_c=ontime;

349 350 351 352 353 354 355 356 357 358

}

359 360 361 362 363 364 365 366

else { / / s et O C R2 S A O C R1 S A O C R0 S A

c om pa re r eg is te r S A t o d ea d t im e = d e ad _ ti m e ; = d e ad _ ti m e ; = d e ad _ ti m e ;


c om pa re r eg is te r S B t o d ea d t im e = d e ad _ ti m e ; = d e ad _ ti m e ; = d e ad _ ti m e ;

367 368 369 370 371 372 373

/ / s et co mp ar e r eg is te r R A t o d ea d t im e p lu s d ut y c yc le

84

APPENDIX B. CODES

O C R 2 RA = d e a d _ t im e + ( 8 * o n t i m e ) ; O C R 1 RA = d e a d _ t im e + ( 8 * o n t i m e ) ; O C R 0 RA = d e a d _ t im e + ( 8 * o n t i m e ) ;

374 375 376 377


378 379 380 381


382

383 384 385 386 387 388 389

d_c=ontime; } / / re l ea s e ou t pu t c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

}

390 391

/*****************************************************************************/

392 393

394 395 396 397 398 399 400 401 402

/ / s u br o u ti n e c a ll e d b y i n te r ru p t o n t o gg l e o f a n al o g comparator / / = = c a ll e d w h e n h a ll s e ns o rs h av e d e te c te d s e ct o r c h an g e i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) { u n si g ne d c h ar h a ll C BA ; / / lo c k P SC s y nc h ro a nd o u tp u t c on f i gu r a ti o n r e gi s te r s / / t o w r it e wi t ho u t d i st u r bi n g P SC c yc l e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

403


404 405

:

406 407 408 409 410 411 412 413

414 415 416 417 418 419

/ / c o mm u ta t e a c c or d in g t o d e te c te d s e ct o r : switch(hallCBA) { / / s te p 1 case 0b00000001: H_C_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_Off; L_B_Off; H_A_On; L_A_On; break;

420 421 422 423 424 425

case 0b00000010:

426

427 428

/ / s te p 3 H_C_Off; L_C_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; / / c le ar L _C a nd L _B P O R T B | = _ B V ( P O R T B7 ) ; // s et L _A 1 H_B_On;

85


429 430

L_B_On; break;

431

case 0b00000011:

432 433 434 435

436

437 438 439 440 441

/ / s te p 2 H_C_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_On; L_B_On; H_A_Off; L_A_Off; break;

442

case 0b00000100:

443 444 445 446

447

448 449 450 451 452


453

case 0b00000101:

454 455 456 457 458 459

460

461 462 463


464

case 0b00000110:

465 466 467 468 469 470

471

472 473 474


475

default :

476 477

478 479 480 481

}

stop () ; U A R T _ p r in t s t r ( " S w i t c h d e f a u lt : H a l l s e n s or o u t p ut s . " ) ; break;

86

APPENDIX B. CODES


482

483 484 485 486

}

487 488

/*****************************************************************************/

489 490 491 492 493 494 495 496 497 498 499 500 501

/ / s u b r o ut i ne t o s t a r t m o t o r i n li n e v o i d r un ( v o id ) { / / ac t iv a te i n t er r up t on a n al o g co m p ar a to r o u tp u t to g gl e : A C 2C O N | = _ BV ( A C 2I E ) ; A C 1C O N | = _ BV ( A C 1I E ) ; A C 0C O N | = _ BV ( A C 0I E ) ; / / s t ar t P SC c o un t er s : P C TL 0 | = _ BV ( P R UN 0 ) ; / / C o mm u t at e : AnaComp_Traitement(); }

502 503

/*****************************************************************************/

504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519

520 521 522

/ / s u b r o ut i ne t o s t o p m o to r i n li n e v o id s t op ( v o id ) { / / de a c ti v at e i n te r ru p t on a n al o g c om p a ra t or o u t pu t t og g le : A C 2C O N & = ~ _ BV ( A C 2 IE ) ; A C 1C O N & = ~ _ BV ( A C 1 IE ) ; A C 0C O N & = ~ _ BV ( A C 0 IE ) ; / / s wi tc h o ff al l 6 tr an s is to r s : H_C_Off; L_C_Off; H_B_Off; L_B_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B7 ) ) ; / / s et L _C , L _B , L _A t o Z ER O / / s to p P SC c ou nt er s : P C TL 0 & = ~ _ B V ( PR U N0 ) ; }

523 524

/*****************************************************************************/

525 526 527

v o id p u tc c ( u i nt 8 _t c ) {

528

u i n t 8_ t t m p _ h ea d ; t mp _h ea d = t x_ he ad + 1 ; i f ( t m p_ h ea d > = T X _B U F _S I Z E ) t mp _h ea d = 0 ;

529 530 531 532 533 534 535


536 537



87

538

U C SR B | = _ BV ( U D RI E ) ;

539 540

}

541 542 543 544 545 546 547 548 549 550 551

/*****************************************************************************/ v oi d U A RT _ p ri n ts t r ( c o ns t c ha r * s ) { w h il e ( * s ) { i f ( *s = = ’ \n ’ ) putcc(’\r’); putcc(*s++); } }

88

B.1.4

1 2 3

APPENDIX B. CODES

SR, 2 Ramp Mode, 3.9 k Hz


4

//

5 6 7 8

//====>>>> / / f o r A T 90 P W M3 B

9

/ / m o di f ie d v e rs i on o f 2 _ r a mp _ m od e _ sr //

10 11 12

/ / 2 R a mp M od e , w it h S y n ch r o no u s R e c ti f i ca t i on // P WM o n H ’ s, o pp os ed P WM o n L ’ s, 1 o n L ’ s w h en L ow

13 14 15

/ / P W M f r eq u e nc y o f 3 . 9 k H z * * * * ** * / / H a l l s e n s or s m od e

16 17 18 19 20 21 22 23 24 25 26 27 28

29 30

31 32

33

34 35 36 37 38

/* * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * ** ** Hall_A === > > ACMP0 == > PD7 => pin 19 ** Hall_B === > > ACMP1 == > PC6 => pin 26 ** Hall_C === > > ACMP2 == > PD5 => pin 17 ** ** ** Ph as e_ A === > > H aut = > PS C0 _A (P SC OU T0 0) == > PD0 = > pin 1 ** Bas = > PSC0_B ( PSCOUT01 ) == > PB7 = > pin 32 ** Ph as e_ B === > > H aut = > P SC 1_ A ( PS CO UT 10 ) == > PC0 = > pin 2 ** Bas = > PSC1_B ( PSCOUT11 ) == > PB6 = > pin 31 ** Ph as e_ C === > > H aut = > P SC 2_ A ( PS CO UT 20 ) == > PB0 = > pin 12 ** Bas = > PSC2_B ( PSCOUT21 ) == > PB1 = > pin 13 ** ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * */

39 40 41 42 43 44


45 46 47 48 49

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Macros * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

50 51 52

/ / a c ti v at i o n a nd d e a ct i v at i o n o f p o we r s t ag e t r an s i st o r s : //activation:

89


53 54 55 56 57 58 59 60 61 62 63 64 65

# d ef in e H _ C _O n ( P SO C2 # d ef in e L _ C _O n ( P SO C2 # d ef in e H _ B _O n ( P SO C1 # d ef in e L _ B _O n ( P SO C1 # d ef in e H _ A _O n ( P SO C0 # d ef in e L _ A _O n ( P SO C0 //deactivation: # d e fi n e H _ C_ O ff ( P S OC 2 # d e fi n e L _ C_ O ff ( P S OC 2 # d e fi n e H _ B_ O ff ( P S OC 1 # d e fi n e L _ B_ O ff ( P S OC 1 # d e fi n e H _ A_ O ff ( P S OC 0 # d e fi n e L _ A_ O ff ( P S OC 0

|= |= |= |= |= |=


&= &= &= &= &= &=


66 67 68 69 70


71 72

/ / _ _ __ _ __ _ __ V a lu e s f or P SC : _ _ _ __ _ __

73 74 75 76 77

// # de fi ne v al _d ea d_ ti me _H au t 4 / / # d e f i ne v a l _ d e a d _t i m e _ b a s 4 # define dead_time 2 // 2 50 n s * * # define period 2048 / / W e c ou nt u p t o 2 04 8 ( 25 6. 4 m i cr o s )

78 79

/ / _ _ __ _ __ b u ff e r s i ze s f or U A RT c o m mu n i ca t i on : _ _ _ __ _

80 81 82


83 84 85 86 87


88 89

c ha r d _ c ; // d u ty c y cl e

90 91 92

/ / _ _ _ _ _ _ _ __ U A R T c o m m u n i c a t i o n : _ _ _ _ _ _ _ __ _ _

93 94 95 96 97




98 99 100 101 102


103 104 105


106 107

108

/ / s ub ro u ti ne t o u pd at e P SC o ut pu t c om pa re r eg is te rs R A a nd R B w it h n ew d ut y c yc le d _c i n l i ne v o i d M A J _ P W M ( c h a r ) ;

90

109

110 111 112 113 114

APPENDIX B. CODES

/ / s u br o u ti n e f or c o m mu t at i o n ( a t c h an g e o f H a ll s e ns o r signals) i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) ; / / s u br o ut i n e t o s t ar t m o to r i n li n e v o id r un ( v o id ) ; / / s u br o ut i n e t o s to p m o to r i n li n e v o id s t op ( v o id ) ;

115 116 117 118

/ / s u b ro u ti n e s f or U A RT t r a ns m i ss i o n v o id p u tc c ( u i nt 8 _t c ) ; v o id U A R T_ p r in t s tr ( c o n st c ha r * s ) ;

119 120 121 122 123 124 125 126 127 128

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Interr upt Service Routines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * / / / I n te r r up t o n A n al o g C o m pa r at o r [ 2 .. 1 ] o u tp u t t o gg l e / / = = h al l s e ns o r h a s d e te c te d s e ct o r c h an g e ISR(ANALOG_COMP_2_vect) { AnaComp_Traitement(); }

129 130 131 132 133


134 135 136 137 138


139 140

/*****************************************************************************/

141 142 143 144 145 146 147 148 149

150 151 152 153 154 155 156 157

/ / I n te r r up t o n r e c ep t io n o f c h ar a ct e r v ia U A RT / / c al l ed w h en b u ff e r I D R 0 i s e m pt y ISR(USART_UDRE_vect) { ui nt 8_ t t mp _t ai l; i f( t x_ he ad = = t x_ ta il ) { U C SR B & = ~ _ B V ( UD R IE ) ; / / d i s a bl e U S A R T _ U D RE _ v e c t interrupt return; } t mp _t ai l = t x_ ta il + 1 ; i f ( t m p_ t ai l > = T X _B U F _S I Z E ) t mp _t ai l = 0 ; t x _t a il = t m p_ t ai l ; U DR = t x _b u f [ t mp _ ta i l ] ; }

158 159 160 161 162 163 164

/*****************************************************************************/ / / " U S AR T0 , R x C o mp l et e " ISR(USART_RX_vect) { c h ar c c ; cc = U DR ;


165 166 167 168

switch(cc) { ca se ’ r’:

169 170 171


172 173

ca se ’ s’:

174 175 176

sto p() ; U A R T _ p r in t s t r ( " \ n S t o p m o t o r " ) ; //putcc(’s’); break;

177 178

c as e ’ 0’ :

179 180 181

M AJ _P WM ( 0) ; U A RT _ p ri n ts t r ( " \ n Du t y c y cl e : 0 ( M I N )" ) ; //putcc(’0’); break;

182 183

c as e ’ 1’ :

184 185 186


187 188

c as e ’ 2’ :

189 190 191


192 193

c as e ’ 3’ :

194 195 196


197 198

c as e ’ 4’ :

199 200 201


202 203

c as e ’ 5’ :

204

205 206

M AJ _P WM ( 25 5) ; U A R T _ p r in t s t r ( " \ n D u t y c y c l e : 2 5 5 / 2 56 (MAX)"); //putcc(’5’); break;

207 208

ca se ’ +’:

209 210 211 212

M AJ _P WM ( d_c + 1) ; U A R T _ p r in t s t r ( " \ n D u t y c y c l e : " ) ; //putcc(’+’); putcc(d_c); break;

213 214

ca se ’ -’:

215 216 217 218


219 220

d ef au lt :

sto p() ;

91

92

APPENDIX B. CODES

221

222 223

}

224 225

U A R T _ p r in t s t r ( " \ n M o t o r s t o p pe d : s w i t ch d e fa u lt : " ) ; putcc(cc); break;

}

226 227 228 229 230

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Main Program * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

231 232 233 234 235 236 237 238 239 240

241 242 243

244 245

i n t m a i n ( v oi d ) { init(); / / a c t i v a te g l o b al i n t e r r up t s sei(); / / c h a r g e b o o t s tr a p c i r c ui t H_C_Off; H_B_Off; H_A_Off; P O R T B | = _ B V ( P O R T B1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ; // s et L _C , L_ B , L _A t o 1 f or l oa di ng t he c ap ac it or / / PC TL 0 |= _ BV ( P RU N0 ) ; // s ta rt P SC c o un te r _delay_ms(200); s t o p ( ) ; // s to ps m ot or a nd s et s L _C , L _B a ns L _A Z ER O a nd s t op s P SC c o un t er U A R T _ p r in t s t r ( " \ n B o o t s t r a p i n i t i a l i sa t i o n f i n i s he d . " ) ; D DR E = 0 x FF ;

246

247 248

while(1) {

249

}

250 251

}

252 253 254 255

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / S ubrou tines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

256 257 258 259 260 261 262 263 264 265 266 267 268 269 270


271 272 273 274 275

/ / _ _ _ _ _ _ _ __ I n i t i a li s e U A R T : _ _ _ _ _ _ _ __ _ _ _ / / A c ti v at i o n of U A RT r e c ei v er a n d i nt e rr u pt o n U AR T r e ce i ve / /8 b it , n o p a ri ty , 1 s to p b it , U CP OL = 0 , 3 8 40 0 b a ud s


93

U C SR B |= _B V ( R XC I E ) | _B V ( R XE N ) | _B V ( T XE N ) ; U BR R = 2 5;

276 277 278

/ / _ _ _ _ _ _ _ __ I n i t i a li s e A n a l og C o m p a r at o r s : _ _ _ _ _ _ _ _ _ / / a n al o g co m p ar a to r s co n ne c t ed to Ha l l s e ns o rs / / e n ab l e c o mp a r at o r s / / n e ga t iv e i n pu t : " V r ef " / 2 . 13 / / i nt er ru p t o n o ut pu t t o gg le ( a c t iv at ed w he n t he m o t or i s started) A C 2C O N | = _ BV ( A C 2E N ) | _ BV ( A C 2 M1 ) ; A C 1C O N | = _ BV ( A C 1E N ) | _ BV ( A C 1 M1 ) ; A C 0C O N | = _ BV ( A C 0E N ) | _ BV ( A C 0 M1 ) ;

279 280 281 282 283

284 285 286 287

/ / _ _ _ _ _ _ _ __ I n i t i a li s e D i g i ta l I n p ut R e g i s te r : _ _ _ _ _ _ _ _ / / di sa bl e d ig it al i n pu t b uf fe r on a n al og p i ns / / t o r e du c e p o we r c o n su m pt i o n / / c or re s po n di n g pi n r eg is te r w il l a lw ay s r ea d as 0 D I DR 1 | = _ BV ( A C M P0 D ) | _ BV ( A D C 10 D ) ; D I DR 0 | = _ BV ( A D C2 D ) ;

288 289 290 291 292 293 294

/ / _ _ _ _ _ _ _ __ I n i t i a li s e P L L : _ _ _ _ _ _ __ _ _ // F _P LL = 32 M Hz W he n PL LF i s cl ea r / / P L LC S R | = _ BV ( P L LF ) ;

295 296 297 298

/ / _ _ _ _ _ _ _ __ I n i t i a li s e P S C s : _ _ _ _ _ _ __ _ _ _ / / PS C in pu t cl oc k : PL L = 3 2 MH z ( P C LK SE Ln ) / / 2 r am p m od e ( P MO DE n0 = 1) / / P SC o u tp u ts a c ti v e h i gh P CN F2 |= _ BV ( P CL KS EL 2 ) | _B V ( PM OD E2 0 ) | _B V ( PO P2 ) ; / / P OP 2 = 1 - > a ct iv e h ig h P CN F1 |= _ BV ( P CL KS EL 1 ) | _B V ( PM OD E1 0 ) | _B V ( PO P1 ) ; / / P OP 1 = 1 - > a ct iv e h ig h P CN F0 |= _ BV ( P CL KS EL 0 ) | _B V ( PM OD E0 0 ) | _B V ( PO P0 ) ; / / P OP 0 = 1 - > a ct iv e h ig h

299 300 301 302 303

304

305

306

/ / P SC 0 co m pl e t es a cy c le b e fo r e ha lt o p e ra t i on w h en requested / / PS C 1 a nd P S C 2 s ta rt w i th P S C 0 ( s yn c hr o ni z at i on o f a ll 3 P SC s ) / / PS C = 8 M Hz ( PL L /4 ) w he n PP RE n0 = 1 P C TL 2 | = _ BV ( P A R UN 2 ) | _ BV ( P P R E2 0 ) ; // * P C TL 1 | = _ BV ( P A R UN 1 ) | _ BV ( P P R E1 0 ) ; // * P C TL 0 | = _ BV ( P C C YC 0 ) | _ BV ( P P R E0 0 ) ; // *

307

308

309 310 311 312 313 314

/ / s et c om pa re r e gi s te r SB to d ea d ti me / / O CR 2 SB = d e a d_ t im e ; / / O CR 1 SB = d e a d_ t im e ; / / O CR 0 SB = d e a d_ t im e ;

315 316 317 318 319


320 321 322 323 324 325 326 327


94

APPENDIX B. CODES

328 329 330

/*****************************************************************************/

331 332

333 334 335

336 337 338

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " o n ti m e " i n li n e v o id M A J_ P WM ( c h a r o n ti m e ) { / / l o ck o ut p ut c o mp a re r e gi s t er s to w ri t e wi t ho u t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

339 340

341 342 343 344


345 346 347 348




d_c=ontime;

349 350 351 352 353 354 355 356 357 358

}

359 360 361 362 363 364 365 366

else { / / s et O C R2 S A O C R1 S A O C R0 S A

c om pa re r eg is te r S A t o d ea d t im e = d e ad _ t im e ; = d e ad _ t im e ; = d e ad _ t im e ;


c om pa re r eg is te r S B t o d ea d t im e = d e ad _ t im e ; = d e ad _ t im e ; = d e ad _ t im e ;

/ / s et O C R 2 RA O C R 1 RA O C R 0 RA

co mp ar e r eg is te r R A t o d ea d t im e p lu s d ut y c yc le = d e a d _ t im e + ( 8 * o n t i m e ) ; = d e a d _ t im e + ( 8 * o n t i m e ) ; = d e a d _ t im e + ( 8 * o n t i m e ) ;



367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382

95


383

} / / re l ea s e o ut p ut c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

384 385 386 387 388 389

d_c=ontime;

}

390 391

/*****************************************************************************/

392 393

394 395 396 397 398 399 400 401 402

/ / s u b r o ut i ne c a ll e d b y i n te r ru p t o n t o gg l e o f a n al o g comparator / / = = c a ll e d w h e n h a ll s e ns o rs h a ve d e te c te d s e ct o r c h an g e i n l i ne v o i d A n a C o m p _ T r a i t em e n t ( v o i d ) { u n si g ne d c h ar h a ll C BA ; / / lo ck P SC s y nc h ro a n d o u tp u t c on f i gu r a ti o n r e gi s te r s / / t o w r it e wi t ho u t d i st u r bi n g P SC c yc l e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

403


404 405

:

406 407 408 409 410 411 412 413

414 415 416 417 418 419

/ / c o mm u t at e a c co r d in g t o d e te c te d s e ct o r : switch(hallCBA) { / / s te p 1 case 0b00000001: H_C_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_Off; L_B_Off; H_A_On; L_A_On; break;

420 421 422 423 424 425

case 0b00000010:

426

427 428 429 430

/ / s te p 3 H_C_Off; L_C_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; / / c le ar L _C a nd L _B P O R T B | = _ B V ( P O R T B7 ) ; // s et L _A 1 H_B_On; L_B_On; break;

431 432 433 434 435

436

case 0b00000011:

/ / s te p 2 H_C_Off; L_C_Off; P O R T B & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; / / c le ar L _B a nd L _A P O R T B | = _ B V ( P O R T B1 ) ; // s et L _C 1

96

APPENDIX B. CODES

437 438 439 440 441

H_B_On; L_B_On; H_A_Off; L_A_Off; break;

442

case 0b00000100:

443 444 445 446

447

448 449 450 451 452


453

case 0b00000101:

454 455 456 457 458 459

460

461 462 463


464

case 0b00000110:

465 466 467 468 469 470

471

472 473 474


475

default :

476 477

478

stop () ; U A R T _ p r in t s t r ( " S w i t c h d e f a u lt : H a l l s e n s or o u t p u ts . " ) ; break;

479

}

480 481


482

483 484 485 486

}

487 488 489

/*****************************************************************************/


490 491 492 493 494 495 496 497 498 499 500 501

97

/ / s u b r o ut i ne t o s t a r t m o t o r i n li n e v o id r un ( v o id ) { / / ac t iv a te i n t er r u pt o n an a lo g c o mp a ra t o r ou t pu t t og g le : A C 2C O N | = _ BV ( A C 2I E ) ; A C 1C O N | = _ BV ( A C 1I E ) ; A C 0C O N | = _ BV ( A C 0I E ) ; / / s t ar t P SC c o un t er s : P C TL 0 | = _ BV ( P R UN 0 ) ; / / C o mm u ta t e : AnaComp_Traitement(); }

502 503

/*****************************************************************************/

504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519

520 521 522

/ / s u b r o ut i ne t o s t o p m o t o r i n li n e v o id s t op ( v o id ) { / / de a c ti v at e i n te r ru p t on a na l og c o m pa r a to r o u tp u t to g gl e : A C 2C O N & = ~ _ BV ( A C 2 IE ) ; A C 1C O N & = ~ _ BV ( A C 1 IE ) ; A C 0C O N & = ~ _ BV ( A C 0 IE ) ; / / s wi tc h of f a ll 6 t ra ns i st or s : H_C_Off; L_C_Off; H_B_Off; L_B_Off; H_A_Off; L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B7 ) ) ; / / s e t L _C , L _B , L _A t o Z ER O / / s t op P SC c o un t er s : P C TL 0 & = ~ _ B V ( PR U N0 ) ; }

523 524

/*****************************************************************************/

525 526 527

v oi d p u tc c ( u i nt 8 _t c ) {

528

u i n t 8 _t t m p _ h ea d ; t mp _h ea d = t x_ he ad + 1 ; i f ( t m p_ h ea d > = T X _ BU F _ SI Z E ) t m p_ h ea d = 0 ;

529 530 531 532 533 534

535


536


537 538

U C SR B | = _ BV ( U D RI E ) ;

539 540

}

541 542 543 544 545 546

/*****************************************************************************/ v oi d U A RT _ p ri n ts t r ( c o ns t c ha r * s ) { w h il e ( * s ) {

98

APPENDIX B. CODES

if (* s = = ’ \n ’) putcc(’\r’); putcc(*s++);

547

548

549

}

550 551

}

B.2. SENSORLESS

B.2 B.2.1

1 2 3

99

Sensorless Scheme A, Centre Aligned Mode

/ / A n d r e a K a t h a r i na F U C H S //ENSMP_CAS //10.06.08

4 5

//

6 7 8 9

//====>>>> / / p o u r A T 90 P WM 3 B

10 11 12 13 14 15 16

// // // // // //

m o d i f ie d v e rs i on o f s l _ c am c h a n g e s : s y n c h r o n o u s r e c t i f i c a t i on 1 and 0 o n l ow c e n t er a l ig n ed m o de s ha o o n

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

// // // // // // // // // // // // // //

P L L f r eq u en c y : 6 4 M H z I O C lo ck : 6 4 MH z /4 = 1 6 MH z P S C f re qu en c y = P LL / 4 P WM f re qu en c y o f 3 .9 k Hz c o m mu t at i o n c o un t er 1 : 2 50 k H z ( 4 us ) S t a rt u p : a li gn to s te p 6 , c om mu ta te t o a cc el er at e t o m ot or s pe ed 1 M a ke m e a su r e me n t s o f A DC 6 , 8 ,9 f or Z C d e t ec t io n c h an g e A D C c h an n el i n C o m mu t at e a c c or d in g t o p r es e nt s t ep step 2 and 5: phase 1 floating -> ADC6 MUX3 :0 = 0110 step 1 and 4: phase 2 floating -> ADC8 MUX3 :0 = 1000 step 3 and 6: phase 3 floating -> ADC9 MUX3 :0 = 1001 motor turns in opposite direc tion (6 -5 -4 -3 -2 -1) d i gi t al f i lt e r o n t i m eS i n ce C o mm u t at i o n v a lu e s

32 33 34 35 36 37 38 39

40

41

42 43 44

45

46

/* * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * ** ** Hall_A === >> ACMP0 == > PD7 => pin 19 ** Hall_B === >> ACMP1 == > PC6 => pin 26 ** Hall_C === >> ACMP2 == > PD5 => pin 17 ** ** ** Phase_A === >> Haut = > PSC0_A ( PSCOUT00 ) == > PD0 => pin 1 ** Bas = > PSC0_B ( PSCOUT01 ) == > PB7 => pin 32 ** Phase_B === >> Haut = > PSC1_A ( PSCOUT10 ) == > PC0 => pin 2

100

47

**

48

**

49

**

APPENDIX B. CODES

=> pin 31 Phase_C === >> => pin 12

Bas

= > PSC1_B

( PSCOUT11 )

== > PB6

Haut

= > PSC2_A

( PSCOUT20 )

== > PB0

Bas

= > PSC2_B

( PSCOUT21 )

== > PB1

=> pin 13 ** ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * */

50 51 52 53 54 55 56 57 58 59 60


61 62

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Macros * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

63 64 65 66 67 68 69 70

71 72

73 74

75 76 77

78 79

80 81

/ / a c ti v at i o n a nd d e a ct i v at i o n o f p o we r s t ag e t r an s i st o r s : //activation: # d ef in e H _C _O n ( P SO C2 | = _ BV ( P OE N2 A ) ) // # de fi ne L_ C_ On ( PS OC 2 | = _ BV ( PO EN 2B ) ) # d ef in e H _B _O n ( P SO C1 | = _ BV ( P OE N1 A ) ) // # de fi ne L_ B_ On ( PS OC 1 | = _ BV ( PO EN 1B ) ) # d ef in e H _A _O n ( P SO C0 | = _ BV ( P OE N0 A ) ) // # de fi ne L_ A_ On ( PS OC 0 | = _ BV ( PO EN 0B ) ) //deactivation: # d e fi n e H _ C_ O ff ( P S OC 2 & = ~ _ B V ( P O EN 2 A ) ) / / # de fi ne L _ C_ Of f ( P SO C2 & = ~ _ BV ( P OE N2 B ) ) # d e fi n e H _ B_ O ff ( P S OC 1 & = ~ _ B V ( P O EN 1 A ) ) / / # de fi ne L _ B_ Of f ( P SO C1 & = ~ _ BV ( P OE N1 B ) ) # d e fi n e H _ A_ O ff ( P S OC 0 & = ~ _ B V ( P O EN 0 A ) ) / / # de fi ne L _ A_ Of f ( P SO C0 & = ~ _ BV ( P OE N0 B ) )

82 83 84 85 86


87 88

/ / _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ V a l u e s f o r PSC:_________________________________________

89 90 91 92

# d e fi n e va l _ de a d _t i m e_ H a ut # d ef in e v a l_ d ea d_ t im e_ b as # define pe rio d_OC Rnr B

4 4 2048

93 94

/ / _ _ __ _ __ _ _ _ b u ff e r s i ze s f or U AR T c o m mu n i ca t i on : _ _ _ _ __ _

95 96 97


98 99 100

/ / _ _ _ _ _ _ _ __ _ _ _ _ _ _Z e r o - c r o s s i n g d e t e c t io n : _ _ _ _ _ _ _ _ _ _ _ _ _

101

B.2. SENSORLESS

101

102 103

/ / h o ld - o f f t im e a t t he b eg in ni ng o f e ac h s te p ( ZC d et ec t io n disabled) # d e fi n e h o ld _ of f 1 28 // 2 P WM c yc le s à 2 56 u s =5 12 u s = 1 28 *4 u s = 1 28 c ou nt er s te ps

104 105 106

/ / i n it a l v a lu e f or c o m mu t a ti o n t i me f i lt e r # d e f i ne f i l t e r _ i ni t i a l 8 5 0

107 108 109 110


111 112

c h a r v a r _ O C S A ; // d u ty c y cl e

113 114 115 116 117

/ / t r a ns m i ss i o n f l a g char TX_send=0; / / 1 : d at a a r e i n t he U AR T b uf fe r / / 0 : U AR T b uf fe r i s e m pt y , n ew d at a c an b e s e nt

118 119

/ / _ _ _ _ _ _ _ __ _ U A R T c o m m u n i c a t i on : _ _ _ _ _ _ _ __ _ _ _ _

120 121 122 123 124




125 126 127

/ / _ _ _ _ _ _ __ M e a s u r e me n t o f f l o a t in g p h a se : _ _ _ _ _ _ _ _ _ _ _ _

128 129 130

/ / A DC r ea di ng o f t he f lo at in g p ha se v ol ta ge : v o la t il e u n si g ne d i nt f l o at i n gV o l ta g e AD C = 0 ;

131 132 133

/ / _ _ _ _ _ _ _ __ _ Z e ro - c r o s s i n g d e t e c t i o n : _ _ _ _ _ _ _ _ _ _ _ _

134 135 136

/ / v al ue b ac ke mf i s co mp ar ed t o u n si g ne d i nt Z C T hr e sh o l d = 5 0 0;

V _D C /2 ( V_ DC = 10 23 ) :

137 138 139

/ / p o la r it y o f b a ck e mf ( 0= f a ll in g , 1 = r is i ng ) : v o l a t il e u n s i g ne d c h a r Z C P o l a ri t y = 0 ;

140 141 142

/ / e n ab l es o r d i sa b le s z er o - c r o ss d e te c ti o n v o la t il e u n si g ne d c h ar Z C En a bl e = 0 ;

143 144 145

/ / c o m mu t at i o n c o un t er v a lu e s a t z e ro - c r os s in g : v o la t il e u n si g ne d i nt t i m eS i n ce C o mm ;

146 147 148

/ / f i lt e re d c o m mu t a ti o n c o un t er v a lu e s a t z er o - c r o s si n g : v o la t il e u n si g ne d i nt filteredTimeSinceCommutation=filter_initial;

149 150

/ / _ _ _ _ _ _ __ S e n s o r le s s C o m m u t a ti o n : _ _ _ _ _ _ _ __ _ _ _ _ _

151 152

v o la t il e u n si g ne d c h ar S t ep N u mb e r ;

153 154 155 156

/ / _ _ _ _ _ _ _ _ _ _ __ _ _ _ S t a r tu p : _ _ _ _ _ _ __ _ _ / / a r r a y f or t i me b e tw e en c o m mu t a ti o n s d u ri n g s t ar t up : u n s i g ne d c h a r S t a r t u p D e l a y s [ 8 ] = {2 0 0 , 1 5 0 , 1 0 0 , 8 0 , 7 0 , 6 5 , 6 5 , 6 5 } ;

102

APPENDIX B. CODES

157 158 159 160


161 162

void init(void);

163 164 165

/ / s u b r o ut i ne t o i n i t i al i ze t he A DC void InitADC(void);

166 167 168 169

/ / s u b ro u ti n e s t o i n it i a li z e c o un t er s v o i d I n i t C o u n t er 1 ( v o i d ) ; / / v o i d I n i t C o u nt e r 0 ( v o i d ) ;

170 171 172 173

/ / s u b ro u ti n e s f o r s t ar t up : void Startup(void); v o id S t ar t u pD e l ay ( u n s i gn e d i nt d e la y ) ;

174 175

176 177

178

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s R B w i t h P WM p e ri o d i n l i ne v o i d M A J _ O C R n RB ( v o i d ) ; / / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " v a l_ S A " i n l i ne v o i d M A J _ O C R n SA ( c h a r ) ;

179 180

181

/ / s ub r ou ti ne c al le d b y I S R o n O CR 1B c om pa re m at ch = e nd o f s t ep i n s e ns o r le s s i n l i ne v o i d C o m m u t a t e ( v o id ) ;

182 183

184 185 186

/ / su b ro ut in e t o s ta rt m ot or ( s ta rt up t o m ot or s pe ed 1 a nd s w it c h t o s e ns o rl e s s m od e ) i n li n e v o id r un ( v o id ) ; / / s u br o ut i n e t o s to p m o to r i n li n e v o id s t op ( v o id ) ;

187 188 189

/ / s u br o u ti n e f or U A RT t r a ns m i ss i o n v o id p u tc c ( ui nt 8_ t c ) ;

190 191 192 193 194 195

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Interr upt Service Routines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

196 197 198 199 200 201 202 203 204 205 206 207 208 209 210

/ / I n te r r up t o n r e c ep t io n o f c h ar a ct e r v ia U A RT / / c al l ed w h en b u ff e r I D R 0 i s e m pt y ISR(USART_UDRE_vect) { uint8_t tmp_tail ; i f( t x_ he ad = = t x _ ta il ) { U C SR B & = ~ _ B V ( UD R IE ) ; // d i s a b l e U S A R T _ U D R E_ v e c t i n t e r ru p t TX_send=0; return; } t mp _t ai l = t x_ ta il + 1 ; i f ( t m p _ ta i l > = T X _ B UF _ S IZ E ) t m p_ t ai l = 0 ;

103

B.2. SENSORLESS

211 212 213

t x _t a il = t m p_ t ai l ; U DR = t x _b u f [ t m p_ t ai l ] ; }

214 215 216 217 218 219

ISR(USART_RX_vect) { c h ar c ; c = UDR ;

220 221 222 223

switch(c) { ca se ’ r’:

224

225 226

run () ; / / U A RT _ p ri n t st r ( " \ n Mi s e e n r o ut e d u moteur"); putcc(’r’); break;

227 228

ca se ’ s’:

229 230 231

sto p() ; / / U A R T _ p r i n ts t r ( " \ n A r r e t d u m o t e ur " ) ; putcc(’s’); break;

232 233 234 235

236 237

/ * c as e ’ 0 ’: M A J _O C R nS A ( 0 ) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : 0 (MIN)"); //putcc(’0’); break;*/

238 239 240

c as e ’ 1’ :

241 242 243

M AJ _O CR nS A (3 0) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : 2 5 " ) ; putcc(’1’); break;

244 245 246

c as e ’ 2’ :

247 248 249

M AJ _O CR nS A (3 5) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : 5 0 " ) ; putcc(’2’); break;

250 251 252

c as e ’ 3’ :

253 254 255

M AJ _O CR nS A (4 0) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : 1 0 0 " ) ; putcc(’3’); break;

256 257 258

c as e ’ 4’ :

259 260 261

M AJ _O CR nS A (4 5) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : 2 0 0 " ) ; putcc(’4’); break;

262 263 264 265

c as e ’ 5’ :

M AJ _O CR nS A (5 0) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : 2 5 5 (MAX)");

104

APPENDIX B. CODES

266 267

putcc(’5’); break;

268

/ * c as e ’ + ’: M A J_ O CR n S A ( v ar _ OC S A + 1 ) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : " ) ; //putcc(’+’); putcc(var_OCSA); break;

269 270 271 272 273 274 275

c as e ’ -’:

276 277 278

279 280 281

M AJ _O CR nS A ( va r_ OC SA - 1 ); //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n P u i s s a n c e m o t e ur : " ) ; //putcc(’-’); putcc(var_OCSA); break;*/

282

d efa ul t :

283 284

285 286 287 288

}

289 290

sto p() ; / / U A R T _ p r i n ts t r ( " \ n A r r e t d u m o t e ur : s w i t ch d e fa u lt : " ) ; //putcc(c); putcc(’s’); //putcc(’d’); break;

}

291 292 293

294 295 296 297 298

/*****************************************************************************/ / / I n te r ru p t r o ut i ne o n c o m p le t i on o f A D c o n ve r si o n f o r v o lt a ge measurement ISR(ADC_vect) { / / re a d me a su r ed v o l ta g e an d c op y it t o fl o a ti n g Vo l t ag e A DC : f l o a t i n g V ol t a g e A D C = ( A D CH < < 2 ) ; / / o nl y e i gh t b i t r e so lu ti on , l a st 2 b it s a r e n ot t ak en i n t o a c c o un t

299 300 301 302 303 304

305 306 307 308

309

/ / Z C d e t ec t io n e n ab l ed ? if(ZCEnable==1) { / / Z C de te ct io n is e n ab le d ; ch ec k fo r ZC : i f ( ( ( Z C P o l a r it y = = 0 ) & & ( f l o a t i n g V o l ta g e A D C < = Z C T h r e sh o l d ) ) | | ( ( Z C P o l a r i t y = = 1 ) & & ( f l o a t i n g V o l ta g e A D C > = Z C T h r e s h o l d ) ) ) { / / z er o - c r o ss i ng d e te c te d timeSinceComm=TCNT1; / / r e se t c o m mu t a ti o n c ou n te r , a c co u nt f or d e la y c a us e d b y A D c o n ve r s io n : T CN T1 = 8 ;

310 311 312

313 314

315 316

/ / f i lt e r c o m mu t a ti o n t i me : f i l te r e dT i m eS i n ce C o m mu t a ti o n = ( t i m e Si n c eC o m m + 3 * filteredTimeSinceCommutation)/4; / / s et t im er c om pa re v al ue t o f il te re d t im e : OCR1B=filteredTimeSinceCommutation; / / c le a r t i me r 1 f l ag s : TIFR1=TIFR1;

B.2. SENSORLESS

/ / en ab le I nt e rr up t o n O CR 1B c om pa re m at ch : T I MS K 1 | = _ BV ( O C I E1 B ) ; / / d i sa b le z er o - c r o ss d e te c ti o n : ZCEnable=0;

317 318 319

320

105

}

321

}

322

}

323 324 325 326

/*****************************************************************************/

327 328 329

330 331 332 333 334 335 336 337

/ / I n t e r ru p t r o ut i ne o n T i m e r1 c o mp a re m a tc h A ( O C R1 A ) : / / e na b le z er o - c r o ss d e t ec t io n a f te r h o ld o ff a t b e gi n ni n g o f each step ISR(TIMER1_COMPA_vect) { ZCEnable=1; / / d i sa b le I nt e rr u pt on OC R 1A co m pa r e m a tc h : T I MS K 1 & = ~ _ BV ( O C I E1 A ) ; / / c le a r t i me r 1 f l ag s : TIFR1=TIFR1; }

338 339

/*****************************************************************************/

340 341 342 343 344 345 346 347 348 349

/ / I n t e r ru p t r o ut i ne o n T i m e r1 c o mp a re m a tc h B ( O C R1 B ) : / / E n d o f s te p = C o mm ut a ti on ISR(TIMER1_COMPB_vect) { StepNumbe r --; if(StepNumber==0) { StepNumber=6; }

350 351

Commutate();

/ / r e se t co m m ut a t io n co u nt e r1 an d c o un t er 0 : TCNT1=0;

352 353 354 355 356

357 358 359

/ / c le a r t i me r 1 f l ag s : TIFR1=TIFR1; / / d i sa b le I nt e rr u pt on OC R 1B co m pa r e m a tc h : T I MS K 1 & = ~ _ BV ( O C I E1 B ) ;

360

/ / e na b le ti m er 1 c o mp a re ma t ch A i n te r r up t : T I MS K 1 | = _ BV ( O C I E1 A ) ;

361 362 363 364

}

365 366 367 368

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Main Program * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

369 370 371 372 373

i nt m a in ( v o id ) { init(); InitADC();

106

374 375 376 377

378 379 380 381 382 383 384

385

386 387 388 389

APPENDIX B. CODES

InitCounter1(); sei(); / / a c t i v a t e g l o b al i n t e r r u p t s / / U A R T _ p r i n ts t r ( " \ n H e l l o W o r l d " ) ; / / c h a r g e b o o t s tr a p c i r c ui t H_C_Off; H_B_Off; H_A_Off; //L_C_On; //L_B_On; //L_A_On; P O R T B | = _ B V ( P O R T B1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ; // s et L _C , L_ B , L _A t o 1 f or l oa di ng t he c ap ac it or P C TL 0 | = _ BV ( P R UN 0 ) ; // s t ar t P SC c o un t er _delay_ms(200); stop(); MAJ_OCRnRB(); D DR E = 0 x FF ;

390

391 392

while(1) {

393

}

394 395

}

396 397 398 399

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / S ubrou tines * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

400 401 402 403 404 405 406 407 408 409 410 411 412 413

/ / S s - p r g m d ’ i n i t i a l i s a t io n void init(void) { / / i ni t d i r ec t io n E / S //TXD,H_A, D D RD = 0 b 0 0 00 1 0 01 ; //H_B, D D RC = 0 b 0 0 00 0 0 01 ; / / L_ A , L _B , H _C , L _C D D RB = 0 b 1 1 00 0 0 11 ; D DR E = 0 x 00 ; / / d e fi n e s t an d ar d p o rt o u tp u ts P OR TE = 0 x 00 ; P O RT D | = 0 x 0 0 ; P O RT C | = 0 x 0 0 ; P O RT B | = 0 x 0 0 ;

414

/ / _ _ _ _ _ _ I n i t i a li z e U A R T : _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ / / A c ti v at i o n of U A RT r e c ei v er a n d i nt e rr u pt o n U AR T r e ce i ve / /8 b it , n o p a ri ty , 1 s to p b it , U CP OL = 0 , 3 8 40 0 b a ud s U C SR B |= _B V ( R XC I E ) | _B V ( R XE N ) | _B V ( T XE N ) ; U BR R = 2 5;

415 416 417 418 419 420 421 422

423

424 425

426

/ / D i g i t a l I n p u t R e g i s te r //d´ e s ac ti ve l a l ec tu re d ir ec t s ur l e p or t d e l a v al eu r d es entr´ e e s d ’ A n al o g C o nv e r te r / / p ou r l i re l e u rs v a l e ur s ( i n di re c t , s o r ti e d e s comparateurs), / / r e ga r de r da n s A n al o g C o m pa r at o r St a tu s Re g is t er / / c et t e m ´ e t ho d e ` a D I DR 1 | = _ BV ( A C M P0 D ) | _ BV ( A D C 10 D ) ; l ’ a ir d e f o n ct i on n e r / / c et t e m ´ ethode D I DR 0 | = _ BV ( A D C2 D ) ; a l ’ a ir d e f o n ct i o nn e r `

B.2. SENSORLESS

107

427

/ / _ _ _ _ _ _ _ __ I n i t i a li z e P L L : _ _ _ _ _ _ _ _ __ _ _ _ / / F _P L L = 6 4 M Hz P L LC S R | = _ BV ( P L LF ) ;

428 429 430 431

/ / _ _ _ _ _ _ _ __ I n i t i a li z e P S C s : _ _ _ _ _ _ _ __ _ _ _ / / PS C in pu t c lo ck : ( PL L /4 = 64 M Hz / 4 = 1 6 MH z ) / / c e nt e r - a l i g n e d m o d e / / P SC o ut pu ts ac ti ve l ow P CN F2 |= _ BV ( P CL KS EL 2 ) | _B V ( PM OD E2 1 ) | _B V ( PM OD E2 0 ) | _ B V ( P O P 2 ) ; // P OP 2 = 1 - > a c ti ve h ig h P CN F1 |= _ BV ( P CL KS EL 1 ) | _B V ( PM OD E1 1 ) | _B V ( PM OD E1 0 ) | _ B V ( P O P 1 ) ; // P OP 1 = 1 - > a c ti ve h ig h P CN F0 |= _ BV ( P CL KS EL 0 ) | _B V ( PM OD E0 1 ) | _B V ( PM OD E0 0 ) | _ B V ( P O P 0 ) ; // P OP 0 = 1 - > a c ti ve h ig h

432 433 434 435 436

437

438

439

/ / P SC 0 co m pl e t es a cy c le b e fo r e ha lt o p e ra t i on w h en requested / / PS C 1 a nd P S C 2 s ta rt w i th P S C 0 ( s yn c hr o ni z at i on o f a ll 3 P SC s ) P C TL 2 | = _ BV ( P A R UN 2 ) | _ BV ( P P R E2 0 ) ; P C TL 1 | = _ BV ( P A R UN 1 ) | _ BV ( P P R E1 0 ) ; P C TL 0 | = _ BV ( P C C YC 0 ) | _ BV ( P P R E0 0 ) ;

440

441

442 443 444 445

/ / i n i ti a l is a t io n o f c o mp a re r eg i st e r S B O C R2 S B = p e r io d _ OC R n rB - v a l _d e a d_ t i me _ b as ; O C R1 S B = p e r io d _ OC R n rB - v a l _d e a d_ t i me _ b as ; O C R0 S B = p e r io d _ OC R n rB - v a l _d e a d_ t i me _ b as ;

446 447 448 449 450

/ / in i t ia l i sa t i on o f c o mp a re r e gi s te r RA u se d fo r synchronization / / of A DC w i th m i dd le o f PW M c yc le ( c an no t be 0 ); O CR 2R A = 1 ; O CR 1R A = 1 ; O CR 0R A = 1 ;

451

452 453 454 455 456 457 458 459 460

/ / u pd at e c o mp ar e r e gi st e rs S A ( w it h d ut y c yc le 0 ) a nd R B MAJ_OCRnSA(0); MAJ_OCRnRB(); }

461 462

/*****************************************************************************/

463 464 465 466

467 468 469

470 471 472 473

/ / s u b r o ut i ne t o i n i t i al i ze t he A DC : / * C o nv e rs i o n s y n ch r o ni z e d w it h P S C0 _ AS Y ev e nt P S C0 _ AS Y e v en t : w h en P S C0 r e ac h es O C R0 R A d u ri n g d o w nc o u nt i n g ( O C R0 R A s et t o 1 ) */ void InitADC(void) { / / _ __ _ _ I n i ti a li z e sy n c hr o n iz a t io n s ou r ce f or AD C auto-trigger:_______ / / s en d s ig na l o n m at ch w i th O C R nR A o n do wn - c o u nt in g / * P SO C 2 & = ~ _ BV ( P S Y NC 2 1 ) & ~ _ B V ( P SY N C2 0 ) ; P S OC 1 & = ~ _ B V ( P SY N C1 1 ) & ~ _ BV ( P S Y NC 1 0 ) ; P S OC 0 & = ~ _ B V ( P SY N C0 1 ) & ~ _ BV ( P S Y NC 0 0 ) ; */

474 475 476

/ / _ _ _ _ _ I n i t i a li z e A D C M u l t i p l ex e r R e g i s te r : _ _ _ _ _ _ _ _ _ _

108

477

478

APPENDIX B. CODES

/ / ch o os e e x te r na l r e fe r en c e v ol t ag e ; l ef t a dj u st A DC r e su l t ; s e le c t A DC c h an n el A D MU X | = _ BV ( A D LA R ) | _ BV ( M U X2 ) | _ BV ( M U X1 ) ;

479 480 481

482

/ / _ __ I n i ti a l iz e A DC C o nt r ol a nd S t at u s R eg i st e r A : _ _ __ _ _ / / en a bl e AD C ; a u to t r ig g er m od e , s el e ct f r e qu e nc y prescaler A D CS R A |= _ BV ( A D EN ) | _B V ( A DA T E ) | _ BV ( A D PS 2 ) | _ BV ( A D P S0 ) ; / / 5 00 k Hz @ 1 6 MH z

483 484 485

486

/ / _ __ I n i ti a l iz e A DC C o nt r ol a nd S t at u s R eg i st e r B : _ _ __ _ / / c ho o se h i gh s p ee d m od e ; s el e ct A D C au to t r i gg e r s ou r ce P S C 0 AS Y e v e nt A D CS R B | = _ BV ( A D HS M ) | _ BV ( A D T S3 ) ;

487 488

}

489 490 491 492 493 494 495

496 497

498 499

/*****************************************************************************/ / / s ub r ou ti ne t o i ni t ia li ze t he T im er 1 v o i d I n i t C o u n t er 1 ( v o i d ) { / / T im er / C o un te r1 c l oc k s e le ct = C L KI O / 64 = 2 5 0 kZ @ 1 6 MH z I/O: T C CR 1 B | = _ BV ( C S 11 ) | _ BV ( C S 10 ) ; / / In i t ia l iz e O u tp u t Co m pa r e R eg i st e r 1 A w it h ho ld - o f f time: O C R1 A = h o ld _ of f ; }

500 501 502

/*****************************************************************************/

503 504

505 506 507 508 509 510 511 512 513 514 515 516

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s R B w i t h P WM p e ri o d i n l i ne v o i d M A J _ O C R n RB ( v o i d ) { P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ; O C R2 R B = p e r io d _ OC R n rB ; O C R1 R B = p e r io d _ OC R n rB ; O C R0 R B = p e r io d _ OC R n rB ; P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ; }

517 518 519

520 521 522

523 524 525

/*****************************************************************************/ / / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " v a l_ S A " i n li n e v o id M A J _O C Rn S A ( c ha r v a l_ S A ) { / / l o ck o ut p ut c o mp a re r e gi s t er s to w ri t e wi t ho u t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

B.2. SENSORLESS

109

O C R2 S A = v a l_ S A * 8; O C R1 S A = v a l_ S A * 8; O C R0 S A = v a l_ S A * 8; v a r_ O CS A = v a l_ S A ; / / re l ea s e o ut p ut c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ; }

526 527 528 529 530 531 532 533 534 535 536

/*****************************************************************************/

537 538

539 540 541 542 543 544 545 546

/ / s ub ro u ti ne c al le d b y I S R o n O CR 1B c om pa re m at ch = e nd o f s te p i n s e ns o r le s s / / c h an g es P SC o ut pu t s , Z C p o la r it y a nd A DC c h an n el i n l i ne v o i d C o m m u t a t e ( v o id ) { / / lo ck P SC s y nc h ro a n d o u tp u t c on f i gu r a ti o n r e gi s te r s / / t o w r it e wi t ho u t d i st u r bi n g P SC c yc l e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

547 548 549 550 551 552 553

554 555 556 557 558 559 560 561 562 563

564 565 566 567

568 569 570 571 572 573 574 575 576 577 578 579

//commutate: switch(StepNumber) { / / s te p 1 : case 1: H_C_Off ; P O R TB & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _B a nd L _A P O R TB | = _ B V ( P O R T B 1 ) ; // set L_C 1 H_B_Off; //L_B_Off; H_A_On; //L_A_Off; / / p o la r it y o f b a ck e mf : ZCPolarity=0; / / c ha ng e A DC c ha nn el t o A DC 8 : A D MU X | = _ B V ( MU X 3 ) ; A DM UX & = ~ _ BV ( M UX 2 ) & ~ _ BV ( M UX 1 ) & ~_BV(MUX0); break; / / s te p 2 : case 2: H_C_Off ; P O R TB & = ~ ( _ B V ( P O R TB 6 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _B a nd L _A P O R TB | = _ B V ( P O R T B 1 ) ; // set L_C 1 H_B_On; //L_B_Off; H_A_Off; //L_A_Off; / / p o la r it y o f b a ck e mf : ZCPolarity=1; / / A D C6 : A D MU X | = _ B V ( MU X 2 ) | _ BV ( M U X1 ) ; A D MU X & = ~ _ BV ( M U X3 ) & ~ _ B V ( MU X0 ) ; break; / / s te p 3 :

110

580 581 582 583 584

APPENDIX B. CODES

case 3:

585

586 587 588

589 590 591 592 593 594 595 596 597 598

/ / s te p 4 : case 4:

599

600 601 602

603 604 605

606 607 608 609 610

/ / s te p 5 : case 5:

611

612 613 614

615 616

617 618 619 620 621 622 623 624

/ / s te p 6 : case 6:

625

626 627 628

629 630 631 632

H_C_Off ; //L_C_Off; H_B_On; //L_B_Off; H_A_Off; P O R TB & = ~ ( _ BV ( P O R T B 1 ) | _ B V ( P O R T B 6 ) ) ; // c le ar L _C a nd L _B P O R TB | = _ B V ( P O R T B7 ) ; // s et L _A 1 / / p o la r it y o f b a ck e mf : ZCPolarity=0; / / A D C9 : A D MU X | = _ BV ( M U X3 ) | _ BV ( M U X0 ) ; A D MU X & = ~ _ BV ( M U X2 ) & ~ _ B V ( MU X1 ) ; break; H_C_On ; //L_C_Off; H_B_Off; //L_B_Off; H_A_Off; P O R TB & = ~ ( _ BV ( P O R T B 1 ) | _ B V ( P O R T B 6 ) ) ; // c le ar L _C a nd L _B P O R TB | = _ B V ( P O R T B7 ) ; // s et L _A 1 / / p o la r it y o f b a ck e mf : ZCPolarity=1; / / A D C8 : A D MU X | = _ BV ( M U X3 ) ; A DM UX & = ~ _ BV ( M UX 2 ) & ~ _ BV ( M UX 1 ) & ~_BV(MUX0); break; H_C_On ; //L_C_Off; H_B_Off; P O R TB & = ~ ( _ BV ( P O R T B 1 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _C a nd L _A P O R TB | = _ B V ( P O R T B6 ) ; // s et L _B 1 H_A_Off; //L_A_Off; / / p o la r it y o f b a ck e mf : ZCPolarity=0; / / A D C6 : A D MU X | = _ BV ( M U X2 ) | _ BV ( M U X1 ) ; A D MU X & = ~ _ BV ( M U X3 ) & ~ _ B V ( MU X0 ) ; break; H_C_Off ; //L_C_Off; H_B_Off; P O R TB & = ~ ( _ BV ( P O R T B 1 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _C a nd L _A P O R TB | = _ B V ( P O R T B6 ) ; // s et L _B 1 H_A_On; //L_A_Off; / / p o la r it y o f b a ck e mf : ZCPolarity=1; / / A D C9 : A D MU X | = _ BV ( M U X3 ) | _ BV ( M U X0 ) ;

111

B.2. SENSORLESS

633

634

A D MU X & = ~ _ BV ( M U X2 ) & ~ _ B V ( MU X1 ) ; break;

635

default :

636 637

stop () ; break;

638

} / / re l ea s e PS C s yn c hr o a nd o u tp u t c on f i gu r a ti o n r eg i st e r s t o u p da t e t h em : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

639 640

641 642 643 644

}

645 646 647

/*****************************************************************************/ / / s u b r o ut i ne t o s t a r t m o t o r

648 649 650 651 652 653 654

i n li n e v o id r un ( v o id ) { / / s t ar t P SC c o un t er s : P C TL 0 | = _ BV ( P R UN 0 ) ; Startup(); }

655 656

/*****************************************************************************/

657 658 659 660 661 662 663 664 665 666 667 668

669 670 671

/ / ss pr gm qu i a rr et e l e m ot eu r i n li n e v o id s t op ( v o id ) { / / tu rn o ff a ll u pp er a nd l ow er s w it ch es : H_C_Off; //L_C_Off; H_B_Off; //L_B_Off; H_A_Off; //L_A_Off; P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B7 ) ) ; / / s e t L _C , L _B , L _A t o Z ER O / / s t op P SC c o un t er s P C TL 0 & = ~ _ B V ( PR U N0 ) ; }

672 673

/*****************************************************************************/

674 675 676


c)

677

uint8_t tmp_head ; t mp _h ea d = t x_ he ad + 1 ; i f ( t m p_ h ea d > = T X _ BU F _ SI Z E ) t m p_ h ea d = 0 ;

678 679 680 681 682 683 684


685 686


687 688

U C SR B | = _ BV ( U D RI E ) ;

112

689

APPENDIX B. CODES

}

690 691 692 693 694

695 696 697 698 699 700 701 702 703 704

705 706 707 708 709 710 711 712 713 714 715

716 717 718 719 720 721 722 723 724 725 726 727 728 729 730

/*****************************************************************************/ / / s u br o u ti n e f or s t ar t up // a li gn m ot or to s te p 6 a nd s pe ed r am p up t o s pe ed 1 ( 50 0 trs/min) void Startup(void) { / / s et P WM d ut y c yc le : MAJ_OCRnSA(37); StepNumber=6; / / al ig n ro to r to st ep 6 a nd w ai t 1 s : Commutate(); StartupDelay(10000); StepNumber=5; / / s ki p s e co n d s t ep / / 8 co ns e cu ti v e s te ps i n o pe n l oo p ( no p o si ti on detection): f or ( u n s ig n ed c h ar i = 0 ; i < 8 ; i + + ) { StepNumbe r --; if(StepNumber==0) { StepNumber=6; } Commutate(); StartupDelay(StartupDelays[i]); } / / 5 co ns e cu ti v e s te ps i n o pe n l oo p ( no p o si ti on detection): f or ( u n s ig n ed c h ar i = 0 ; i < 5 ; i + + ) { StepNumbe r --; if(StepNumber==0) { StepNumber=6; } Commutate(); StartupDelay(StartupDelays[7]); } StepNumbe r --; if(StepNumber==0) { StepNumber=6; }

731 732

/ / _ _ _ _ _ _ s w i tc h t o s e n s o r le s s c o m m u t at i o n : _ _ _ _ _ _ _ _

733 734

A D CS R A | = _ BV ( A D IE ) ; // e n a bl e e nd o f A D c o nv e r si o n interrupt

735

736 737

ZCEnable=0;

TCNT1=0; / / r e se t c o m mu t a ti o n t i me r :

T I F R 1 = T I F R 1 ; / / c le a r t i me r 1 f l ag s

738 739 740 741 742

B.2. SENSORLESS

113

T I MS K 1 | = _ BV ( O C I E1 A ) ; / / e n ab l e i n te r r up t o n O C R1 A c o mp a re match

743

744

745 746

Commutate();

}

747 748 749 750 751 752 753 754 755 756 757 758 759 760

/*****************************************************************************/ / / s u br o u ti n e t o g e ne r at e d e la y f or s t ar t up c o mm u t at i o ns : // 4 us ( Ti me r1 ) * 2 5 * ’ de la y ’ = = g en er at ed d el ay in s v oi d S t ar t u pD e l ay ( u n s i gn e d i nt d e la y ) { TIFR1=TIFR1; do { T CN T1 = 0 x ff ff - 2 5; / / W ai t f or t im er t o o ve r fl ow . w hi le ( !( T I FR 1 & ( 1 < < T OV 1 )) ) {

761

} TIFR1=TIFR1; delay --; } w h il e ( d e la y ) ;

762 763 764 765 766

}

114

APPENDIX B. CODES

B.2.2

1 2 3

SR, Centre Aligned Mode

/ / A n d r e a K a t h a r i na F U C H S //ENSMP_CAS //09.06.08

4

/ / t e st e d 1 2 .0 6 .0 8

5 6 7 8 9

//====>>>> / / p o u r A T 90 P WM 3 B

10

/ / w i t h A n dr e a ’ s C A R D ( n o n i n ve r te d d r iv e rs )

11 12

// // // // // //

13 14 15 16 17 18

m o di f ie d v e rs i on o f S e n so r l es s _ 7 o f C a ro l in e c h an g es : s y n ch r o no u s r e c ti f i ca t i on s et d ir ec t l ow s id e 0 or 1 c e n t er a l ig n ed m o de s ha o o n

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

// // // // // // // // // // // // // //

P L L f r eq u e nc y : 6 4 M H z I O C lo ck : 6 4 MH z /4 = 1 6 MH z P S C f re qu e nc y = P LL / 4 P WM f re qu e nc y o f 3 .9 k Hz c o m mu t at i o n c o un t er 1 : 2 50 k H z ( 4 us ) S t a rt u p : a li gn to s te p 6 , c om mu ta te t o a cc el er at e t o m ot or s pe ed 1 M a ke m e a su r e me n t s o f A DC 6 , 8 ,9 f or Z C d e t ec t io n c h an g e A D C c h an n el i n C o m mu t at e a c c or d in g t o p r es e nt s t ep step 2 et 5: phase 1 floating -> ADC6 MUX3 :0 = 0110 step 1 et 4: phase 2 floating -> ADC8 MUX3 :0 = 1000 step 3 et 6: phase 3 floating -> ADC9 MUX3 :0 = 1001 motor turns in opposite dire ction (6 -5 -4 -3 -2 -1) d i gi t al f i lt e r o n t i m eS i n ce C o mm u t at i o n v a lu e s

34 35 36 37 38 39 40 41 42 43 44 45 46

47 48

49 50

51 52

/* * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * ** ** Hall_A === > > ACMP0 == > PD7 => pin 19 ** Hall_B === > > ACMP1 == > PC6 => pin 26 ** Hall_C === > > ACMP2 == > PD5 => pin 17 ** ** ** Ph as e_ A === > > H aut = > PS C0 _A (P SC OU T0 0) == > PD0 = > pin 1 ** Bas = > PSC0_B ( PSCOUT01 ) == > PB7 = > pin 32 ** Ph as e_ B === > > H aut = > P SC 1_ A ( PS CO UT 10 ) == > PC0 = > pin 2 ** Bas = > PSC1_B ( PSCOUT11 ) == > PB6 = > pin 31 ** Ph as e_ C === > > H aut = > P SC 2_ A ( PS CO UT 20 ) == > PB0 = > pin 12 ** Bas = > PSC2_B ( PSCOUT21 ) == > PB1 = > pin 13 **

B.2. SENSORLESS

115

** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * */

53 54 55 56 57 58 59 60 61 62


63 64 65 66 67

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Macros * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

/ / a c ti v at i on a nd d e a ct i v at i o n o f p o we r s t ag e t r a ns i s to r s : //activation: # d ef in e H _ C _O n ( P SO C2 | = _ BV ( P OE N2 A ) ) # d ef in e L _ C _O n ( P SO C2 | = _ BV ( P OE N2 B ) ) # d ef in e H _ B _O n ( P SO C1 | = _ BV ( P OE N1 A ) ) # d ef in e L _ B _O n ( P SO C1 | = _ BV ( P OE N1 B ) ) # d ef in e H _ A _O n ( P SO C0 | = _ BV ( P OE N0 A ) ) # d ef in e L _ A _O n ( P SO C0 | = _ BV ( P OE N0 B ) ) //deactivation: # d e fi n e H _ C_ O ff ( P S OC 2 & = ~ _ B V ( P O EN 2 A ) ) # d e fi n e L _ C_ O ff ( P S OC 2 & = ~ _ B V ( P O EN 2 B ) ) # d e fi n e H _ B_ O ff ( P S OC 1 & = ~ _ B V ( P O EN 1 A ) ) # d e fi n e L _ B_ O ff ( P S OC 1 & = ~ _ B V ( P O EN 1 B ) ) # d e fi n e H _ A_ O ff ( P S OC 0 & = ~ _ B V ( P O EN 0 A ) ) # d e fi n e L _ A_ O ff ( P S OC 0 & = ~ _ B V ( P O EN 0 B ) )

84 85 86 87 88


89 90

/ / _ __ _ __ V a lu e s f or P SC : _ _ _ _ __ _ __ _ _

91 92 93 94 95

// # de fi ne v al _d ea d_ ti me _H au t 4 / / # d e f i ne v a l _ d e a d _t i m e _ b a s 4 #d ef in e v al _d ea d_ ti me 4 # define pe riod _OC RnRB 2048

96 97

/ / _ _ __ _ __ b u ff e r s i ze s f or U A RT c o m mu n i ca t i on : _ _ _ _ __ _ __

98 99 100


101 102

/ / _ _ _ _ _ __ _ Z e ro - c r o s s i n g d e t e c ti o n : _ _ _ _ _ _ _ _ _ _ _

103 104

105 106

/ / h o ld - o f f t im e a t t he b eg in ni ng o f e ac h s te p ( ZC d et ec t io n disabled) # d e fi n e h o ld _ of f 1 28 // 2 P WM c yc le s à 2 56 u s =5 12 u s = 1 28 *4 u s = 1 28 c ou nt er s te ps

107 108 109

/ / i n it a l v a lu e f or c o m mu t a ti o n t i me f i lt e r # d e f i ne f i l t e r _ i ni t i a l 8 5 0

116

APPENDIX B. CODES

110 111 112 113


114 115

c h ar d _c ; // d u ty c y cl e

116 117 118 119 120

/ / t r a ns m i ss i o n f la g char TX_send=0; / / 1 : d at a a re i n t h e U A RT b uf fe r / / 0 : U AR T b uf fe r i s e m pt y , n ew d at a c an b e s e nt

121 122

/ / _ _ _ _ _ _ __ U A R T c o m m u n i c a t i on : _ _ _ _

123 124 125 126 127

volat ile volat ile volat ile volat ile


tx_head ; tx_tail ; tx_buf [ T X_BUF _SIZE ]; data [ RX_B UF_SI ZE ];

128 129 130

/ / _ __ _ __ M e as u r em e n t o f f l oa t in g p h as e : _ _ _ __ _ _ __ _

131 132 133

/ / A DC r ea di ng o f t he f lo at in g p ha se v ol ta ge : v o la t il e u n si g ne d i nt f l o at i n gV o l ta g e AD C = 0 ;

134 135 136

/ / _ _ _ _ _ __ Z e ro - c r o s s i n g d e t e c t i o n : _ _ _ _ _ _ _ _ _ _ _ _

137 138 139

/ / v al ue b a ck em f is c om pa re d to u n si g ne d i nt Z C T hr e sh o l d = 5 0 0;

V _D C /2 ( V_ DC = 10 23 ) :

140 141 142

/ / p o la r it y o f b a ck e mf ( 0= f a ll in g , 1 = r is i ng ) : v o la t il e u n si g ne d c h ar Z C Po l a ri t y = 0;

143 144 145

/ / e n ab l es o r d i sa b le s z er o - c r o ss d e te c ti o n v o la t il e u n si g ne d c h ar Z C En a bl e = 0 ;

146 147 148

/ / c o m mu t at i o n c o un t er v a lu e s a t z er o - c r o s si n g : v o la t il e u n si g ne d i nt t i m eS i n ce C om m ;

149 150 151

/ / f i lt e re d c o m mu t a ti o n c o un t er v a lu e s a t z er o - c r o s si n g : v o la t il e u n si g ne d i nt filteredTimeSinceCommutation=filter_initial;

152 153

/ / _ _ _ _ _ _ _ __ S e n s o r le s s C o m m u t at i o n : _ _ _ _ _ __

154 155

v o la t il e u n si g ne d c h ar S t ep N u mb e r ;

156 157 158 159

/ / _ _ _ _ _ _ __ _ S t a r tu p : _ _ _ _ _ __ / / a r r a y f or t i me b e tw e en c o m mu t a ti o n s d u ri n g s t ar t up : u n s i g ne d c h a r S t a r t u p D e l a y s [ 8 ] ={ 2 0 0 , 1 5 0 , 1 00 , 8 0 , 7 0 , 6 5 , 6 5 , 6 5 } ;

160 161 162 163


164 165 166

void init(void);

B.2. SENSORLESS

167 168

117

/ / s u b r o ut i ne t o i n i t i al i ze t he A DC void InitADC(void);

169 170 171 172

/ / s u b ro u ti n e s t o i n it i a li z e c o un t er s v o i d I n i t C o u n t er 1 ( v o i d ) ; / / v o i d I n i t C o u n t e r0 ( v o i d ) ;

173 174 175 176

/ / s u b ro u ti n e s f o r s t ar t up : void Startup(void); v oi d S t ar t u pD e l ay ( u n s i gn e d i nt d e la y ) ;

177 178

179

/ / s o ub r ou t i ne t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s R B a n d S A w it h n ew d ut y c yc le d _c i n l i ne v o i d M A J _ P W M S R ( c h ar ) ;

180 181

182 183

184

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s R B w i t h P WM p e ri o d //inline void MAJ_OCRnRB(void); / / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " v a l_ S A " //inline void MAJ_OCRnSA(char);

185 186

187

/ / s ub ro u ti ne c al le d b y I S R o n O CR 1B c om pa re m at ch = e nd o f s te p i n s e ns o r le s s i n l i ne v o i d C o m m u t a t e ( v o id ) ;

188 189

190 191 192

/ / su b ro ut in e t o s ta rt m ot or ( s ta rt up t o m ot or s pe ed 1 a nd s w it c h t o s e n so r l es s m o de ) i n li n e v o id r un ( v o id ) ; / / s u br o ut i ne t o s t o p m o to r i n li n e v o id s t op ( v o id ) ;

193 194 195

/ / s u br o u ti n e f or U A RT t r a ns m i ss i o n v o id p u tc c ( ui nt 8_ t c ) ;

196 197 198 199 200 201

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Interru pt Service Routines * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219

/ / I n te r r up t o n r e c ep t io n o f c h ar a ct e r v ia U A RT / / c al l ed w h en b u ff e r I D R 0 i s e m pt y ISR(USART_UDRE_vect) { uint8_t tmp_tail ; i f( t x_ he ad = = t x _ ta il ) { U C SR B & = ~ _ B V ( UD R IE ) ; // d i s a b l e U S A R T _ U D R E_ v e c t i n t e r ru p t TX_send=0; return; } t mp _t ai l = t x_ ta il + 1 ; i f ( t m p _ ta i l > = T X _ B UF _ S IZ E ) t m p_ t ai l = 0 ; t x _t a il = t m p_ t ai l ; U DR = t x _b u f [ t m p_ t ai l ] ; }

118

APPENDIX B. CODES

220 221 222 223 224 225

ISR(USART_RX_vect) { c ha r c ; c = UDR ;

226 227 228 229

switch(c) { case ’r ’:

230 231 232

run () ; / / U A R T _ p r i n ts t r ( " \ n S t a r t m o t or " ) ; putcc(’r’); break;

233 234

c ase ’ s’:

235 236 237

st op () ; / / U A R T _ p r i n ts t r ( " \ n S t o p m o t o r " ) ; putcc(’s’); break;

238 239 240 241 242 243

/ * c as e ’ 0 ’: M A J_ O CR n S A ( 0) ; //MAJ_OCRnRB(); / / U A RT _ p ri n t st r ( " \ n D ut y c y cl e : 0 ( M I N ) ") ; //putcc(’0’); break;*/

244 245 246

c as e ’ 1’ :

247 248 249

M AJ _P WM SR ( 30 ); //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n D u t y c y c l e : 3 0 " ) ; putcc(’1’); break;

250 251 252

c as e ’ 2’ :

253 254 255


256 257 258

c as e ’ 3’ :

259 260 261


262 263 264

c as e ’ 4’ :

265 266 267


268 269 270

c as e ’ 5’ :

271 272 273


274 275 276 277

/ * c as e ’ + ’: M A J_ O CR n S A ( v ar _ OC S A + 1 ) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n D u t y c y c l e : " ) ;

119

B.2. SENSORLESS

278 279 280

//putcc(’+’); putcc(var_OCSA); break;

281

c as e ’ - ’:

282 283 284

285 286 287

M A J_ OC R nS A ( v ar _O CS A - 1 ) ; //MAJ_OCRnRB(); / / U A R T _ p r i n ts t r ( " \ n D u t y c y c le : " ) ; //putcc(’-’); putcc(var_OCSA); break;*/

288

d ef au lt :

289 290

291 292 293 294

}

295 296

sto p() ; / / U A R T _ p r i n ts t r ( " \ n M o t o r s t o p p ed : s w i t ch d e fa u lt : " ) ; //putcc(c); putcc(’s’); //putcc(’d’); break;

}

297 298 299

300 301 302 303 304

/*****************************************************************************/ / / I n te r ru p t r o ut i ne o n c o m p le t i on o f A D c o n ve r si o n f o r v o lt a ge measurement ISR(ADC_vect) { / / re ad m e a su r ed v o l ta g e an d c op y it t o f lo a t in g V ol t a ge A D C : f l o a t i n g V ol t a g e A D C = ( A D CH < < 2 ) ; / / o nl y e i gh t b i t r e so lu ti on , l a st 2 b it s a r e n ot t ak en i n t o a c c o u nt

305 306 307 308 309 310

311 312 313 314

315

/ / Z C d e t ec t io n e n ab l ed ? if(ZCEnable==1) { / / Z C de t ec ti on i s en ab le d ; ch ec k fo r ZC : i f ( ( ( Z C P o l a r it y = = 0 ) & & ( f l o a t i n g V o l ta g e A D C < = Z C T h r e sh o l d ) ) | | ( ( Z C P o l a r i t y = = 1 ) & & ( f l o a t i n g V o l ta g e A D C > = Z C T h r e s h o l d ) ) ) { / / z er o - c r o ss i ng d e te c te d timeSinceComm=TCNT1; / / r e se t c o m mu t a ti o n c ou n te r , a c co u nt f or d e la y c a us e d b y A D c o n ve r si o n : T CN T1 = 8 ;

316

/ / f i lt e r c o m mu t a ti o n t i me : f i l t er e d Ti m e S in c e Co m m u ta t i on = ( t i m e Si n c eC o m m + 3 * filteredTimeSinceCommutation)/4; / / s et t im er c om pa re v al ue t o f il te re d t im e : OCR1B=filteredTimeSinceCommutation; / / c le a r t i me r 1 f l ag s : TIFR1=TIFR1; / / en ab le I nt er r up t o n O CR 1B c om pa re m at ch : T I MS K 1 | = _ BV ( O C I E1 B ) ; / / d i sa b le z er o - c r o ss d e te c ti o n : ZCEnable=0;

317 318

319

320 321

322 323 324 325

326

}

327 328

}

120

APPENDIX B. CODES

}

329 330 331 332

/*****************************************************************************/

333 334 335

336 337 338 339 340 341 342 343

/ / I n te r ru p t r o ut i ne o n T i m e r1 c o mp a re m a tc h A ( O C R1 A ) : / / e na b le z er o - c r o ss d e t ec t io n a f te r h ol d o ff a t b e gi n ni n g o f each step ISR(TIMER1_COMPA_vect) { ZCEnable=1; / / d i sa b le I nt e rr u pt on OC R 1A c om p ar e ma t ch : T I MS K 1 & = ~ _ BV ( O C I E1 A ) ; / / c le a r t i me r 1 f l ag s : TIFR1=TIFR1; }

344 345

/*****************************************************************************/

346 347 348 349 350 351 352 353 354 355

/ / I n te r ru p t r o ut i ne o n T i m e r1 c o mp a re m a tc h B ( O C R1 B ) : / / E n d o f s te p = C o mm ut a ti on ISR(TIMER1_COMPB_vect) { StepNumbe r --; if(StepNumber==0) { StepNumber=6; }

356 357

Commutate();

/ / r e se t co m m ut a t io n co u nt e r1 an d c o un t er 0 : TCNT1=0;

358 359 360 361 362

363 364 365

/ / c le a r t i me r 1 f l ag s : TIFR1=TIFR1; / / d i sa b le I nt e rr u pt on OC R 1B c om p ar e ma t ch : T I MS K 1 & = ~ _ BV ( O C I E1 B ) ;

366

/ / e n ab l e t i me r 1 c o mp a re ma t ch A i n te r r up t : T I MS K 1 | = _ BV ( O C I E1 A ) ;

367 368 369 370

}

371 372 373 374

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * / Main Program * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

375 376 377 378 379 380 381

int {

382 383 384 385

m a i n ( v oi d ) init(); InitADC(); InitCounter1(); sei(); / / a c t i v a t e g l o b al i n t e r r u p t s / / U A R T _ p r i n ts t r ( " \ n H e l l o W o r l d " ) ; / / c h a r g e b o o t s tr a p c i r c ui t H_C_Off; H_B_Off;

B.2. SENSORLESS

386 387

388

389 390 391 392

121

H_A_Off; P O R T B | = _ B V ( P O R T B1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ; // s et L _C , L _B , L _A t o 1 f or l oa di ng t he c a pa ci to r P C TL 0 | = _ BV ( P R UN 0 ) ; // s t ar t P SC c o un t er _delay_ms(200); stop(); //MAJ_OCRnRB(); D DR E = 0 x FF ;

393

394 395

while(1) {

396

}

397 398

}

399 400 401 402

/ * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * / Su brout ines * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * /

403 404 405 406 407 408 409 410 411 412 413 414 415 416 417

//Initialisation void init(void) { / / I / O d i r ec t io n s / / de fi ne p i ns c o n ne ct ed t o p ow er s t ag e as o u tp ut s //TXD,H_A, D D RD = 0 b 0 0 00 1 0 01 ; //H_B, D D RC = 0 b 0 0 00 0 0 01 ; / / L_ A , L _B , H _C , L _C D D RB = 0 b 1 1 00 0 0 11 ; D DR E = 0 x 00 ; / / d ef i ne s t an d ar d p o rt o u tp u ts : P OR TE = 0 x 00 ; P O RT D | = 0 x 0 0 ; P O RT C | = 0 x 0 0 ; P O RT B | = 0 x 0 0 ;

418 419 420 421 422 423

/ / _ _ _ _ _ _ _ __ I n i t i a li z e U A R T : _ _ _ _ _ __ _ / / A c ti v at i o n of U AR T r e ce i ve r a nd i n t er r up t o n UA R T re c ei v e / /8 b it , n o p a ri ty , 1 s t o p bi t , U C PO L = 0 , 3 8 40 0 b a ud s U C SR B |= _B V ( R XC I E ) | _B V ( R XE N ) | _B V ( T XE N ) ; U BR R = 2 5;

424 425 426 427 428 429 430

/ / _ _ _ _ _ I n i t i a li s e D i g i ta l I n p ut R e g i s te r : _ _ _ _ _ _ _ _ / / di sa bl e d ig it al i n pu t b uf fe r on a n al og p i ns / / t o r e du c e p o we r c o n su m pt i o n / / c or re s po n di n g pi n r eg is te r w il l a lw ay s r ea d as 0 D I DR 1 | = _ BV ( A C M P0 D ) | _ BV ( A D C 10 D ) ; D I DR 0 | = _ BV ( A D C2 D ) ;

431 432 433 434

/ / _ _ _ _ _ _ _ __ I n i t i a li z e P L L : _ _ _ _ _ __ _ // F _P LL = 64 M Hz w he n PL LF i s se t to 1 P L LC S R | = _ BV ( P L LF ) ;

435 436 437 438 439 440

/ / _ _ _ _ _ _ _ __ I n i t i a li z e P S C s : _ _ _ _ _ _ __ _ _ / / PS C in pu t c lo ck : ( PL L /4 = 64 M Hz / 4 = 1 6 MH z ) / / c e nt e r - a l i g n e d m o d e / / P SC o u tp u ts a c ti v e h i gh P CN F2 |= _ BV ( P CL KS EL 2 ) | _B V ( PM OD E2 1 ) | _B V ( PM OD E2 0 ) | _ B V ( P O P 2 ) ; // P OP 2 = 1 - > a c ti ve h ig h

122

APPENDIX B. CODES

P CN F1 |= _ BV ( P CL KS EL 1 ) _ B V ( P O P 1 ) ; // P OP 1 = P CN F0 |= _ BV ( P CL KS EL 0 ) _ B V ( P O P 0 ) ; // P OP 0 =

441

442

| 1 | 1

_B V ( PM OD E1 1 ) | _B V ( PM OD E1 0 ) | - > a c ti ve h ig h _B V ( PM OD E0 1 ) | _B V ( PM OD E0 0 ) | - > a c ti ve h ig h

443

/ / PS C 0 c om pl e te s a c yc le b e fo re h a lt o p e ra ti o n w he n requested / / PS C 1 a nd P S C 2 s ta rt w i th P S C 0 ( s yn c hr o ni za t io n o f a ll 3 P SC s ) / / se t P PR En 0 to 1 : PS C in pu t c lo ck d i vi de d by 4 P C TL 2 | = _ BV ( P A R UN 2 ) | _ BV ( P P R E2 0 ) ; P C TL 1 | = _ BV ( P A R UN 1 ) | _ BV ( P P R E1 0 ) ; P C TL 0 | = _ BV ( P C C YC 0 ) | _ BV ( P P R E0 0 ) ;

444

445

446 447 448 449 450

/ / i n i ti a l is a t io n / / O C R2 S B = v a l_ S A / / O C R1 S B = v a l_ S A / / O C R0 S B = v a l_ S A

451 452 453 454

o f c o mp a re r eg i st e r S B + v a l _d e a d_ t i me ; + v a l _d e a d_ t i me ; + v a l _d e a d_ t i me ;

455

/ / i n i ti a l is a t io n of th e co m pa r e re g is t er RB O C R2 R B = p e r io d _ OC R n RB ; O C R1 R B = p e r io d _ OC R n RB ; O C R0 R B = p e r io d _ OC R n RB ;

456 457 458 459 460

/ / in i t ia l i sa t i on o f c o mp a re r e gi s te r RA u se d fo r synchronization // o f A DC i n t he m i dd le o f P WM c y cl e ( ca nn ot b e 0 ); O CR 2R A = 1 ; O CR 1R A = 1 ; O CR 0R A = 1 ;

461

462 463 464 465 466 467 468 469

/ / u pd at e c o mp ar e r e gi st e rs S A ( w it h d ut y c yc le 0 ) a nd R B MAJ_PWMSR(25); }

470 471

/*****************************************************************************/

472 473 474 475

476 477 478

479 480 481 482

/ / s u b r o ut i ne t o i n i t i al i ze t he A DC : / * C o nv e rs i o n s y n ch r o ni z e d w it h P S C0 _ AS Y ev e nt P S C0 _ AS Y e v en t : w h en P S C0 r e ac h es O C R0 R A d u ri n g d o w nc o u nt i n g ( O C R0 R A s et t o 1 ) */ void InitADC(void) { / / _ __ _ I ni t ia l i ze s y nc h r on i z at i o n so u rc e fo r AD C auto-trigger:___ / / s en d s ig na l o n m at ch w i th O C R nR A o n do wn - c o u nt in g / * P SO C 2 & = ~ _ BV ( P S Y NC 2 1 ) & ~ _ B V ( P SY N C2 0 ) ; P S OC 1 & = ~ _ B V ( P SY N C1 1 ) & ~ _ BV ( P S Y NC 1 0 ) ; P S OC 0 & = ~ _ B V ( P SY N C0 1 ) & ~ _ BV ( P S Y NC 0 0 ) ; */

483 484 485 486

487

/ / _ _ __ _ _ I n it i a li z e A DC M ul t i pl e x er R eg i st e r : _ __ _ _ / / ch o os e e x te r na l r e fe r en c e v ol t ag e ; l ef t a dj u st A DC r e su l t ; s e le c t A DC c h an n el A D MU X | = _ BV ( A D LA R ) | _ BV ( M U X2 ) | _ BV ( M U X1 ) ;

488 489

/ / _ _ __ _ __ I n it i a li z e AD C Co n tr o l an d St a tu s R eg i st e r A:______

123

B.2. SENSORLESS

490

491

/ / en a bl e AD C ; a u to t r ig g er m od e , s el e ct f r e qu e nc y prescaler A D CS R A |= _ BV ( A D EN ) | _B V ( A DA T E ) | _ BV ( A D PS 2 ) | _ BV ( A D P S0 ) ; / / 5 00 k Hz @ 1 6 MH z

492 493

494

495

/ / _ _ __ _ __ _ I n it i al i z e A DC C o nt r ol a nd S ta t us R e gi s te r B:_______ / / ch o os e h ig h s pe e d mo d e ; se l ec t A DC a u to t r i gg e r s ou r ce P S C 0 A SY e v e nt A D CS R B | = _ BV ( A D HS M ) | _ BV ( A D T S3 ) ;

496 497

}

498 499 500 501 502 503 504

505 506

507 508

/*****************************************************************************/ / / s ub ro u ti ne t o i ni t ia li ze t he T im er 1 v o i d I n i t C o u n t er 1 ( v o i d ) { / / T im er / C o un te r1 c l oc k s e le ct = C L KI O / 64 = 2 5 0 kZ @ 1 6 MH z I/O: T C CR 1 B | = _ BV ( C S 11 ) | _ BV ( C S 10 ) ; / / In i t ia l iz e O u tp u t Co m pa r e R eg i st e r 1 A w i th h ol d - o f f time: O C R1 A = h o ld _ of f ; }

509 510 511

/*****************************************************************************/

512 513

514 515 516 517 518

/ / s ub ro u ti ne t o u pd at e P SC o ut pu t c om pa re r eg is te rs S A a nd S B w it h d ut y c y cl e " o n t im e " i n li n e v o id M A J_ P WM S R ( c ha r o n ti m e ) { P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

519 520

521 522 523

/ / se t c om pa re r e g is te r S A to d u ty c y cl e f or h i gh s i de signal O C R2 S A = 4 * o n ti m e ; O C R1 S A = 4 * o n ti m e ; O C R0 S A = 4 * o n ti m e ;

524 525

526 527 528

/ / se t c om pa re r e g is te r l ow s i de s i gn a l O C R2 S B = 4 * o n ti m e + O C R1 S B = 4 * o n ti m e + O C R0 S B = 4 * o n ti m e +

S B to d u ty c y cl e p lu s d ea d t im e f or

v a l _d e a d_ t i me ; v a l _d e a d_ t i me ; v a l _d e a d_ t i me ;

529 530 531 532

P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

533 534 535

d _c = o nt im e ; }

536 537

/*****************************************************************************/

124

538

539 540 541

542 543 544 545 546 547 548 549 550 551 552 553 554 555

APPENDIX B. CODES

/ / s u br o u ti n e t o u p da t e P SC o u tp u t c o mp a re r e gi s te r s S A w i t h n ew d u ty c y cl e " v a l_ S A " / * i nl i ne v o id M A J_ O C Rn S A ( c ha r v a l_ S A ) { / / l o ck o ut p ut c o mp a re r e gi s t er s to w ri t e wi t ho u t d i st u r bi n g P SC c y cl e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ; O C R2 S A = v a l_ S A * 8; O C R1 S A = v a l_ S A * 8; O C R0 S A = v a l_ S A * 8; v a r_ O CS A = v a l_ S A ; / / re l ea s e ou t pu t c o mp a re r e g is t er s to u p da t e re g i st e rs : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ; } */ /*****************************************************************************/

556 557

558 559 560 561 562 563 564 565

/ / s ub r ou ti ne c al le d b y I S R o n O CR 1B c om pa re m at ch = e nd o f s t ep i n s e ns o r le s s / / c h an g es P SC o ut pu t s , Z C p o la r it y a nd A DC c h an n el i n l i ne v o i d C o m m u t a t e ( v o id ) { / / lo c k P SC s y nc h ro a nd o u tp u t c on f i gu r a ti o n r e gi s te r s / / t o w r it e wi t ho u t d i st u r bi n g P SC c yc l e : P C NF 2 | = _ BV ( P L O CK 2 ) ; P C NF 1 | = _ BV ( P L O CK 1 ) ; P C NF 0 | = _ BV ( P L O CK 0 ) ;

566 567 568 569 570 571 572 573

574 575 576 577 578

//commutate: switch(StepNumber) { / / s te p 1 : case 1: H_C_Off ; L_C_Off; P O R TB & = ~ ( _ BV ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _B a nd L _A P O R TB | = _ B V ( P O R T B1 ) ; // s et L _C 1 H_B_Off; L_B_Off; H_A_On; L_A_On;

579 580 581

582 583 584

585 586 587 588 589

/ / s te p 2 : case 2:

/ / p o la r it y o f b a ck e mf : ZCPolarity=0; / / c ha ng e A DC c ha nn el t o A DC 8 : A D MU X | = _ BV ( M U X3 ) ; A DM UX & = ~ _ BV ( M UX 2 ) & ~ _ BV ( M UX 1 ) & ~_BV(MUX0); break;

H_C_Off ; L_C_Off; P O R TB & = ~ ( _ BV ( P O R T B 6 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _B a nd L _A

125

B.2. SENSORLESS

590 591 592 593 594

P O R TB | = _ B V ( P O R T B 1 ) ; // set L_C 1 H_B_On; L_B_On; H_A_Off; L_A_Off;

595 596 597

598 599 600 601 602 603 604 605 606

/ / s te p 3 : case 3:

607

608 609 610

/ / p o la r it y o f b a ck e mf : ZCPolarity=1; / / A D C6 : A D MU X | = _ B V ( MU X 2 ) | _ BV ( M U X1 ) ; A D MU X & = ~ _ BV ( M U X3 ) & ~ _ B V ( MU X0 ) ; break;

H_C_Off ; L_C_Off; H_A_Off; L_A_Off; P O R TB & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; // c le ar L _C a nd L _B P O R TB | = _ B V ( P O R T B 7 ) ; // set L_A 1 H_B_On; L_B_On;

611 612 613

614 615 616 617 618 619 620 621 622

/ / s te p 4 : case 4:

623

624 625 626

/ / p o la r it y o f b a ck e mf : ZCPolarity=0; / / A D C9 : A D MU X | = _ B V ( MU X 3 ) | _ BV ( M U X0 ) ; A D MU X & = ~ _ BV ( M U X2 ) & ~ _ B V ( MU X1 ) ; break;

H_B_Off ; L_B_Off; H_A_Off; L_A_Off; P O R TB & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) ) ; // c le ar L _C a nd L _B P O R TB | = _ B V ( P O R T B 7 ) ; // set L_A 1 H_C_On; L_C_On;

627 628 629

630 631 632

633 634 635 636

/ / s te p 5 : case 5:

637

638 639 640 641 642 643

/ / p o la r it y o f b a ck e mf : ZCPolarity=1; / / A D C8 : A D MU X | = _ B V ( MU X 3 ) ; A DM UX & = ~ _ BV ( M UX 2 ) & ~ _ BV ( M UX 1 ) & ~_BV(MUX0); break;

H_B_Off ; L_B_Off; P O R TB & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _C a nd L _A P O R TB | = _ B V ( P O R T B 6 ) ; // set L_B 1 H_A_Off; L_A_Off; H_C_On; L_C_On;

126

APPENDIX B. CODES

644

645 646 647 648

/ / s te p 6 : case 6:

649 650 651 652 653 654 655

656

657 658

/ / p o la r it y o f b a ck e mf : ZCPolarity=0; / / A D C6 : A D MU X | = _ BV ( M U X2 ) | _ BV ( M U X1 ) ; A D MU X & = ~ _ BV ( M U X3 ) & ~ _ B V ( MU X0 ) ; break;

H_C_Off ; L_C_Off; H_B_Off; H_B_Off; P O R TB & = ~ ( _ BV ( P O R T B 1 ) | _ B V ( P O R T B 7 ) ) ; // c le ar L _C a nd L _A P O R TB | = _ B V ( P O R T B6 ) ; // s et L _B 1 H_A_On; L_A_On;

659 660

661 662 663 664

665

/ / p o la r it y o f b a ck e mf : ZCPolarity=1; / / A D C9 : A D MU X | = _ BV ( M U X3 ) | _ BV ( M U X0 ) ; A D MU X & = ~ _ BV ( M U X2 ) & ~ _ B V ( MU X1 ) ; break;

666

default :

667 668

stop () ; break;

669

} / / re l ea s e PS C s yn c hr o a nd o u tp u t c on f ig u r at i on r e g is t e rs t o u p da t e t h em : P C NF 2 & = ~ _ B V ( PL O CK 2 ) ; P C NF 1 & = ~ _ B V ( PL O CK 1 ) ; P C NF 0 & = ~ _ B V ( PL O CK 0 ) ;

670 671

672 673 674 675

}

676 677 678

/*****************************************************************************/ / / s u b r o ut i ne t o s t a r t m o t o r

679 680 681 682 683 684 685

i n li n e v o i d r un ( v o id ) { / / s t ar t P SC c o un t er s : P C TL 0 | = _ BV ( P R UN 0 ) ; Startup(); }

686 687

/*****************************************************************************/

688 689 690 691 692 693 694 695 696 697 698

/ / s u b r o ut i ne t o s t o p m o to r i n li n e v o id s t op ( v o id ) { / / tu rn o ff a ll u pp er a nd l ow er s w it ch es : H_C_Off; L_C_Off; H_B_Off; L_B_Off; H_A_Off; L_A_Off;

127

B.2. SENSORLESS

P O R T B & = ~ ( _ B V ( P O R TB 1 ) | _ B V ( P O R T B 6 ) | _ B V ( P O R T B7 ) ) ; / / s e t L _C , L _B , L _A t o Z ER O / / s t op P SC c o un t er s P C TL 0 & = ~ _ B V ( PR U N0 ) ;

699

700 701 702

}

703 704

/*****************************************************************************/

705 706 707


c)

708

uint8_t tmp_head ; t mp _h ea d = t x_ he ad + 1 ; i f ( t m p_ h ea d > = T X _ BU F _ SI Z E ) t m p_ h ea d = 0 ;

709 710 711 712 713 714

715


716


717 718

U C SR B | = _ BV ( U D RI E ) ;

719 720

}

721 722 723 724 725

726 727 728 729 730 731 732 733 734 735

736 737 738 739 740 741 742 743 744 745 746

747 748 749 750 751 752

/*****************************************************************************/ / / s u br o u ti n e f or s t ar t up // a li gn m ot or to s te p 6 a nd s pe ed r am p up to s pe ed 1 ( 50 0 trs/min) void Startup(void) { / / s et P WM d ut y c yc le : MAJ_PWMSR(37); StepNumber=6; / / al ig n ro to r to st ep 6 a nd w ai t 1 s : Commutate(); StartupDelay(10000); StepNumber=5; / / s k i p s e co n d s t ep / / 8 co ns e cu ti v e s te ps i n o pe n l oo p ( no p o si ti on detection): f or ( u n s ig n ed c h ar i = 0 ; i < 8 ; i + + ) { StepNumbe r --; if(StepNumber==0) { StepNumber=6; } Commutate(); StartupDelay(StartupDelays[i]); } / / 5 co ns e cu ti v e s te ps i n o pe n l oo p ( no p o si ti on detection): f or ( u n s ig n ed c h ar i = 0 ; i < 5 ; i + + ) { StepNumbe r --; if(StepNumber==0) { StepNumber=6;

128

APPENDIX B. CODES

753

754 755 756 757

758 759 760 761

} Commutate(); StartupDelay(StartupDelays[7]);

} StepNumbe r --; if(StepNumber==0) { StepNumber=6; }

762 763

/ / _ _ _ _ _ s w i tc h t o s e n s o r le s s c o m m u t a ti o n : _ _ _ _ _ _ _ _

764 765

A D CS R A | = _ BV ( A D IE ) ; // e n a bl e e nd o f A D c o nv e r si o n interrupt

766

767 768

ZCEnable=0;

TCNT1=0; / / r e se t c o m mu t a ti o n t i me r :

T I F R 1 = T I F R 1 ; / / c le a r t i me r 1 f l ag s

769 770 771 772 773

T I MS K 1 | = _ BV ( O C I E1 A ) ; / / e na b le i n te r r up t o n O C R1 A c o mp a re match

774

775

776 777

Commutate();

}

778 779 780 781 782 783 784 785 786 787 788 789 790 791

/*****************************************************************************/ / / s u br o u ti n e t o g e ne r at e d e la y f or s t ar t up c o m mu t a ti o n s : // 4 us ( Ti me r1 ) * 2 5 * ’ de la y ’ = = g en er at ed d el ay in s v o id S t ar t u pD e l ay ( u n s i gn e d i nt d e la y ) { TIFR1=TIFR1; do { T CN T1 = 0 x ff ff - 2 5; / / W ai t f or t im er t o o ve rf lo w . w hi le ( !( T I FR 1 & ( 1 < < T OV 1 )) ) {

792

} TIFR1=TIFR1; delay --; } w h il e ( d e la y ) ;

793 794 795 796 797

}

Appendix C

AVR Butterfly To practice programming microcontrollers, the book ”C Programming for Microcontrollers” of Joe Pardue, published in 2005, and the AVR Butterfly kit of ATMEL are used. In this chapter, the benefits and the disadvantages of this training program are briefly discussed.

C.1

C Programming for Microcontrollers

The book is easy to read and explains the complex matter clearly. It begins with bit shifting and setting and builds up until PWM. All programs are written for the ATMEL AVR Butterfly and can be tested with it. Unfortunately, the explanations are only available for an old version of WINAVR and AVRStudio. Some basic blinking programs can be simulated in the simulator AVRStudio, which is really practical. To run the programs in the simulator, no extra time is necessary and the effects of the programming can be well visualised. The simulation can only be used for simple commands, like blinking lights and connections between different PORTs.

C.2

AVR Butterfly kit

The AVR Butterfly is a low priced demonstration board for the ATMega169V AVRController of Atmel. In addition to the microcontroller, the Butterfly kit consists of a display, a joystick, a thermo-sensor and three different interfaces. With the RS-232, the Butterfly should be easily and quickly programmed. Unfortunately, this in system programming (ISP) did not work as expected. The butterfly could only be programmed with the aid of the STK500. The expected application was unsuccessful.

C.3

Personal Recommendation for Learning to Program Microcontrollers

For learning to program microcontrollers, the book is very helpful and highly recommended. The simulator of the AVRStudio is helpful to get an idea of the effects of a simple C-program. Regrettably, the AVR Butterfly kit is not so easy to use. It would be better to program directly.

129

130

APPENDIX C. AVR BUTTERFLY

Bibliography [1]

¨ ntje Caroline Claasen: Control Go

of Permanent Magnet Brushless Mo-

tors . Diploma Thesis, 2008. [2] ATMEL: AT90PWM2, Datasheet, 2008.

AT90PWM3,

AT90PWM2B,

AT90PWM3B .

[3] Dal Y. Ohm and Richard J. Oleksuk: Influence of PWM Schemes and Commutation Methods for DC and Brushless Motors and Drives . P.E. Technology, 2002. [4] Ward Browm: AN857: Brushless DC Motor Control Made Easy . Microchip Technology Inc, 2002. [5] Padmaraja Yedamale: AN885: Brushless DC (BLDC) Motor Fundamentals . Microchip Technology Inc, 2002. [6] ATMEL: AVR444: Sensorless control of 3-phase brushless DC motors . Application Note, 2005. [7] ATMEL: AVR493: Sensorless Commutation of Brushless DC Motor (BLDC) using AT90PWM3 and ATAVRMC100 . Application Note, 2006. [8] The MathWorks: Permanent Magnet Synchronous Machine . SimPowerSystems Modelling Block, 2006. [9] Jianwen Shao: Direct Back EMF Detection Method for Sensorless Brushless DC(BLDC) Motor Drives . Master’s thesis, Virginia Polytechnic Institute and the State University, 2003.

131

bafuchsan

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