Digital Design
Preface To IIIv!alllily. Alii.". Eric. Kelsi, alld Mom: IlIId ' 0 ' hose ellgill eers II'ho applv ,hel l' sk ills 10 bll ild 'hillgs ,hll' illlp''O I'e 'h e 1111111011 colldll lOlI .
\ P A;\ D EXECLTI\ 'l:, PUBLISHER
BRL'CE SPATL.
\SSOC IATE PLBLI SHER ~E;\, IOR ,.\ CQ ISITIO:--: S EDITOR ..\ \10 PRODL'CT MANAGER PROJ ECT EDITOR
DAN SAYR E Ct\TII ERINE FI ELDS SHULTZ GI.J\ DYS SOTO
SE;\' IOR FDITOR IA L ASS ISTANT ,\ IEDI\ EDITOR SENI OR PRODllCTION ED ITOR 1\I ARKETI:"\G l\ 1,\,'\AG ER COVER JLLL'STR ATIO~
STEVEN CHASEY V,\ LERI E A V,\RGAS PHYLLI S CERY5 ~ lI C II ..\ EL JU NG
DANA KEL LOGG
COVER DES IGj\ER
~ I A D ELY N
PRODc cn ON SE RV ICES
INGRAO ASSOC IAT ES
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TO STUDENTS ABOUT TO STUDY DIGITAL DESIGN Dig ilal ci rc u.its . ~hich form th e basis of general-purpose computers as well as peciaJ purpose devl~es h.k~ cell phones or video game consoles. are dramatically changing the worl d . S lUdymg d igItal design not only gives you the confidence Ihal comes" ith fundame ntall y unders tand ing how d igital circ uits work. but also introduce!' you 10 an e:tcitiof! a nd usefu l possible career direction. This statement appl ies regardless of "-hether )ou'; maj or is Electrica l Engineering. Computer Enginee ring. or even Computer Science (in fac!. the need for digita l designers with strong computer science skills continues to increase). J hope you find (hi subjeci to be as ime restin e:. excitin2. and useful as J do. Throughout lhi s book. J have tried not only to in~uce con~ep{S in the rna I inruilive and easy to learn manner. but I have al 0 tried (Q sho\\ ho" those concepb can be a ppli ed to real-world systems. such as pacemakers. ul trasound machine . pnmers. automobil es. and cell phones. Young and capable engineering ludems (including computer science students ) Some limes lea\ their major. clai ming the) " 'ant a job that is more: "peopl e oriented." Ye t we need those people-oriented rudenlS more than e\cr. 35 engineering j obs are increas ingly people-oriented. in scveraJ wa) s. First. engineers ~uaJI~ wo rk in ,ighTly-imegraled groups involving numerous other engineers (rather than "silting a lo ne in front of a compu le r all day" as many studen ts belic\'e). econd. engineers often wo rk direCily lI'ilh CUSTomers ( uch as busine people. doctors. la\\ ) ers. go\ cmment officials. etc.). a nd mu st therefore be able 10 connect with those non-engineer ClJ.)(Qmero. Th ird . a nd in my opinion mosl importantly. ellgineers build 'lrings tlral dramatically impo('l people's /in's. teedcd are engineers \\ ho combine the.ir e nthlbiasm. C'T'eati\i £) . a nd innm'alion wi th Iheir olid engineering skills to con ehe and buiJd ne" product., thai il11prme people's quality o f life.
I have included " Designer Profiles" at the e nd of most chaplen.. The de"lgnef't.. \\ hose experi ence le \els \ 'M) from j ust a ~ ear to . e\ eral dec:lde .. , and \\ho. l.'"Omparu mnge fm m 5111alli0 huge . , hare \\ ith ~ ou their e\perience~. in .. ighb. and ad\ Il.':e. h'IU \\i ll notice hO\\ co mmon I) the) disc uss the people aspects of wetr Job~. You m3~ 3ho notice thei r cOIhu li; ias m a nd p:bs iQn for their job .
TO INSTRUCTORS OF DIGITAL DESIGN TIlis book. brea k!o from the 19 (hJ19 Os. digiml d(!, ign \It:" empha:.llm~ 'Iu-hmlted dc\ igll, lI1 :--tc3d cmph 3!
iii
Preface
Preface
to a beller app rec iati on of modem computers 3nd other digi tal devices. but n more 3CCUr~HC unders tandin g of careers involving digi t31desig n. Such an accurate und crst:'lIlding is cri ti cal to atlr3C( co mputing majors 10 C3rcers involvi ng some 3mOUJl( of digital design. and to cre~lI e 3 ci.ldre of engineers wi th the comfort in both ··softw3re" and " h3rdware" nccessary in mode m embedded comput ing system design. The dis tinguishing of basic desig n fro m optimiznrion should not be interpreted as avo iding a bOllom-up 3pproac h or glossing over import,lIlt steps - th e book takes a concrcte bOllom-up 3pproac h, starting from transistors. and building incrementall y up through gates. flip -fl ops. registers. controllers. datapath components. etc. Rather, the disting uis hing enables th e stu de nt to initiall y develop a solid understanding of basic design. before considerin g the morc advan ced topic of optimizati on, akin to how a phys ics book introd uces Newton's Ja ws of Illotion initiall y ass uming fri cti onless surfaces and no wind rcsislJ.nce. Furthermore. optimi zation IOday invo lves more than j ust size minimi zati on. ins tead requiring a broader understanding of tradeoffs among size, perform ance. and power. and eve n of tradeoffs among custom digi tal ci rcuits and microprocessor soft ware. Aga in , coverage is kept conc rete and appropriate to an int rod uctory digital desig n course. Nevertheless. the book distinguishes basic design from optimiza tion in a way that cleanly provides an ins tructor max imum Hexibility to introduce optimi za ti on at the tim es and to the ex tent desi red by th e instructor. In pani cular. the optimiza ti on chapter's subsections (Chapter 6) eac h correspond directly to one earlier chapter. such that Secti on 6.2 can direct ly follow Cha pte r 2. Secti on 6.3 can fo llow Chapter 3. 6.4 can follow 4. and 6.5 can follow 5. Several additional features of the boo k include:
HDL cOl'erage flexibility. The book's organization cleanly allows instructors to cove r HDLs (hardware descri ption languages) intennixed with the introduction of desig n concepts. to cove r HDLs later. or 10 not cover HDLs at all. The HDL chapter's subsecti ons (Chapter 9) each correspond to an earlier chapter. sucb that Sec tion 9.2 can directly fo llow Chapter 2. 9.3 can follow 3. 9.4 can follow J , and 9.5 can follow 5. Funhennore. rather than the book choosing jUst one of the popular languages - VHD L. Veri log. and the relatively new SystemC - the book provides equ al coverage of all three of those HDLs. And we use our extensive ex perience in synthesis with commercial tools to create HDL descnptions well -s uited for synthesis. in addi ti on to being suitable for imulation. Accompanying HDL-introdlictiOIl books. InstruclOrs wishing to co\er HDLs to an
eve n greater extent can utili ze one of our HDL-introduclion books specifically designed to accompany this tex tbook. wriuen by the same author as this textbook. Our HDL-introducrion books follow the same chapter tructure as. and use examples from. this tex tbook. eliminating the common situation of students struggling to correlate their distinct. and sometimes contradicting. HDL book ilIld digital desig n book subjects. Our HD L-intmduction books discuss language. simulanon. and testing concepts in more depth. providing numerous HDL e."tamples. and are al 0 designed to be usable by themselves for HDL learrung or ,..,fereoc<:. The books emphasize use of the language for real design. clearl) distio_uishing HDL use for symhesis fro m HDL use for testing. and include e."tlensive examples and fi gures throughout to ill ustrate conceplS. Our HDL-introductioD ~ come "",ith complete Powe rPoi nt slides th at use graphic and animations lO sene as an ea:Syto- use tutori al on the HDL.
Extensil'e lise of applied examples alldfigures. Afte r desc ribing a new conce pt and providing basic examples. Ihe book provides exampl es th at ap pl y the co nce pt 10 appl icati ons recog ni zab le to a student. like a seal belt unfas tened warnin g sys tcm. a computerized checke rboard ga me. a color printer, or a di gital video camera. Furulermore. the end of mOst chapters include a product profi le. intend ed to give students an eve n broader view of the applicability of the concepts. and to introduce clever appl icati on-speci fi c conce pts the students may find ve ry interestinglike the idea of beamfoml ing in an ultrasound machine or of fi ltering in a cellular phone. The book exte nsive ly uses fig ures 10 illustrate conce pts. contai nin g over 600 figures.
Allthor-created graphical animated Pou'uPo;nt slides. A rich set of Po,,-erPoint
lides are available to in tructors. The slides were reated by the textbook' author. res ulting in consiste ncy of perspective and emphasis be(\\, een the tides and this book. The slides are designed to be a truly effective teaching tool for the instructor. Most slides are graphics based (avoiding sLides con isting of j\bl bulleted lists of tex.t). The lides make e:<. t en ~ i\'e us of animation \\ here appropmue to gradually uO\'eil concept or build-up circuits. ~et e\en nnimated sli~ can b! printout out and undersuxxi. 1early e\er) figure. oncepL and e"tampie from tlt.b book i included io the set of almo t 500 lides. from \\ hich instructors choose.
=
Learn ing through discovery. The boo k emphasizes understanding the need fo r
new concepLS. which not onl y helps stude nts learn and remembe r the concept~. but develops reaso ning skills that can apply the concepts to other do mains. For example. rat her than just defi ning a carry- lookahead adder, the book shows intuitive bu t inefficient approac hes to buil ding a fas ter adder. even tua ll y solving the inefficienc ies and leading to ("discovering") the carry-lookahead des ign. Introduction to FPGAs. The book incl udes a full y boltom-up int rod uction to FPGAs. show ing stude nts co ncretely how a ci rcuit ca n be co nvcrtcd into :1 bitstream Ihat prog rams th e indi vidual lookup tables. switch I11 tl tri cc!!. and olher pro~ grammab le co mponents in an FPGA. This co ncrete int rod ucti on cli mi nntcS the mystery of th e increasingly-common FPGA devices.
Complete solmiOlls mallilal. Instru tors rna) obtain
3 complete - luuons m3DuJl (about 200 pages) containing !!olutions to c\ ef) end-of-chapter execci..-..e In thho book. The manual e.\tensively utilizes figures to illu. tr..ne .;:oluoo05.
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PLUS ·
11r,1,,'PLU lIebsi". Dicit.1 Design;' supported b) \\'jle)PLL' - 3 po\\ rful nnd 'highly intcgrnted sulte of t a;hing and learning re,oun.-es dosign
nal 3.: h II ~Iud '1doo . . olutions of selt"Cted e\ample.... anim:nion, f pen1l1ent 1,.'\m(,."C'pt. (b..."'llh ~ b) Prole>""r Ed DD
Preface
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Preface
and aut hor-created an im:ttt.::d Po\\crPoint >;. pili:' cour~c an d homcwork managemcnt lOob. in one ~al:.y-to- li se wcb:, itc. To learn how to aCCC:":" thcsc fC~lIu re~. go 10 the Book Co mpa ni on Site at \\ w\\.w iley.comlcollcgelvahid. or w \ \ \\.dd\ ahid.com.
HOW TO USE THI S BOOK Thi... book \\a~ tlcsigned to allow nc\ ibil ity to choose among the most C0 l111110n appro:lt·hc:. to ma terial covc ragl!. We desc ribc :.cvcra l ilp proachcs below.
1Oe;
Completely traditional approach
RTl· focused appro a ch A n RTL-focu:-cd approach wo uld :.irnpl y covc r the fir!)t 6 chapters in ord er:
I. Introduction (C hapte r
controllers) before combinational components (e.g .• adders. comparators. etc.,. Such reordering may lead into RTL des ign more natu rall y than a tmditional approach. foll""lI1. instead an a~pr~ac h of increas ing abstraction rather than the traditional approach that arat es co mbmatlonal and sequentiaJ de ign. HD Ls can aga in be introduced at the end. left for another cou rse, or integrated after eac h chapter. This approach could aJw be used as an intermediary lep when migrating from a fu lly-trad itional approach to an RTL approac h. Migraling might involve gradually postponing the Chapter 6 sectjon~ - for example. covering Chapters 2 and 3. and then Sections 6.2 and 6.3. before mo,in. on to ~~~ -
I)
2. Co mbina tional logic de"-ign (Chaptl:f 2) J. Scquenti al logic design (C hapter 3) ..,t COlllbinmional and ~eqllc nti ;l l com ponent design (Chapter-t ) 5. RTL dc~ i gn (Chapter 5) 6. Optimizations and Tradeoffs (Chapter 6). to the extent desi red 7. Phyo;;ic;\I implcmcnl:ltion (C hapter 7) and/or Processor design (Chapter 8). to the c'Xlcnt des ired. We thin!'" thi ... io;; a great way to order the 1l1~lIcri'll. re:-.ulting in stud ents doi ng in teres ting RTL dc:..ign:- in abollt 7 \\ech. HDL" cnn be int roduced at the cnd if tim e pe rm its. or left fo r a !-Iccond course on digital desig n (as donc at UC R). or covcred immcdi ate ly a rter cach ch"ptcr - ,,11 threc app roac he~ appea r to be quil c C0 111111 0 n . Tra dition a l approach with some reordering
Thi", book can be readily u~ed in a trad itional approach that int roduces optim izatio n along \~ ith ba~ic dcsign. wit h a slight diffcrcnce from thc traditio nal approach bcing th e wapping of cove rage of combinat ion'll component.:. and sequent ial logic. a~ follo\V~: I . Introduction (Chaptcr 1) 2. Co mbinational logic dC!o.ign (C hapter 2) fo llo\\cd by combi nati onal logic opti m i~ n ll ion (Sec tion 6.2) 3. Scquential logic des ign (C hapter 3) fo llowed by ...cqucnti al Im! ic optimizati on (Section 6.3) -t o Combinati onal and sequcntial componc nt de\ign (C haptcr 4) fo llowed by componellt tradcoffs (Section 6.4) 5. RTL dc ... ign (Chapter 5) to the ex ten t dc, ired. followed by RTL opti1l1 i / ~ll ion/ tradeoff, (Swion 6.5) 6. Phyo.,ical i~l1plcmcn t::nion (Chapter 7) and/or Proccv.• or dc,ig n (C hnptcr 8). to the extcnt d e~ lrcd.
Till ... i".. :I ve ry rcao.,onabh.: and ef~·ec.t iv~ approach. completing all d i ~cus,ion or Oll l.! tu pie (c.~ .. I-SM dL''''lgn ~I'''. \\c ll :to., Optl l11 l1~lI l~lI1) he fore mov ing on to the nl.!x t topic. The n:nrtienng lrom .1 tr:ldlliona l ,Ipproach Introduce", h~h l c ,cqucnli al dC'Ign (FS M' tlild
Th is book could also be used in a com pletely traditional approach. '" follo\\ : I. Introd uction (Chapter I) 2. Combina ti onal logic design (Chapter 2) follo\\ed by combtnational logic opumi· zation (Section 6.2) 3. Co mbi national component design (Section 4.1. 4.3. 4.4. 4.5. 4.7. 4 .. 4.91 fol· lowed by co mbin ati onal component uadeoffs (Section 6A - Adders 4. Seq uential logic des ign (Chapter 3) followed b) sequential logic opumizanon (Section 6.3) 5. Sequential component design (Chapter 4. ecuons 4.2. 4.6. 4.101 follo\\OO b~ sequential co mponent tradeoffs (Section 6A - ~ l ultiplie~) 6. RTL design (Chapter 5) to the extent desired. follo\\OO b~ RTL opumizationl tradeolTs (Sectio n 6.5) 7. Ph ysical implementation (Chapter 7) andlor Proce",or design (Chapter l. to the ex tent desired.
This is thc mos t widespread approac h durin g. the past (\\ 0 decnde~. \\ ith the addition of RTL towards the end. Al though the emphasized distinction be{\\ een combmationJ.l and scquentia l design may no longer be rele\'ant in the era of RTL de... ign ~\\here both type:... of design are imemli xed). some people belic\-e that such distinction make~ for ~ C3.... ier learnin g path. which may be true. HOLs an be in luded at the end. left for a tller C\."')lII"'e. or integmted throughout.
ACKNOWLEDGEMENTS Man) people and organization~ contributed to thb ediuon I.)f the tx,,-"'l.. tafT memben. at Joh n \\'ile\ and Son ... Pubh ... he", hJ\e e\len"'l\el~ ",upP'-"'noo ~ book's de\'elopment. includi-ng Cutherine hultZ, GlJd~ ... l.)tO, Dana J....l!lk;g. and Kelly B ylc. Bill Zobrist ,upported m) e3J'lier ··Emb«lded ~ ,tern o,,'tgn- N . motivated me to \\ rite the pre~ent btlOk. Jnu pro\ IUNI g~.lt JJ\ II.: ~ thl\.\Ughl'lllt develop ment. R):111 ~ l :U1nion contributed man) lIem~. II1dUJ,lOg the Jrrcnu11.: • nwt".~I'\\U'" I: xamplc"- and C\C'rcl~e:.. ~e\ eml :.ub ... t: 'lion.... the ':I.)mrl<.'le !.'\ClX'l,e ,,,-)Iuth.)n ... manual. fnct.chcc!...tn\!, e\ ten'l\e proo(re~tdtng. IJ\:'mend\.,u ... J.."t'I .•lnl.:· Junn£. P(\"duclI(ln. help \\ Ith th;' ,lid6. plent) llf I...ka., dunnt! ..IN.'u''1 ...''n' .•\OJ l11u,,--h m\m!
viii
Preface Ro man Lyscc ky deve loped numerouS exampl es and exe rcises. contri buted most of the conte nt of the HDL chapler. and co-authored our accompanyin g HDL-introduction books. Roman and Susan Lysecky providcd muc h proo freading assistance. Numerous reviewe rs provided outstanding feedbac k on various vers ion s o f the book. Spec ial thanks go to earl y adopters, such as Niki l Out!, Shannon Tauro. J. Dav id Gillanders, Shcldon Tan. Trav is Doo m. Roman Lysecky, a nd others. who prov ided excelle nt feedba ck from them se lves and from their students. Th e importance of th e support provided to my resea rch and lcachin g caree r by the Natio n'll Science Fou ndation cannot be overstated. Additional suppo rt from th e Se mi condu ctor Researc h Corporation ca tal yzed industry co llaboratio ns lhat in tum inOuenced mallY of th e perspectives in thi s boo k.
ABOUT THE COVER The cove r's image of shrinking squares graphically depicts the amaz ing rcal-life pheno men a of di gital ci rcuits ('computer chips' ) shrinking in size by one half roughl y every 18 mont hs. for several decades now. a phenomena ofte n referred to as Moore's Law. Such shrinki ng has enab led in credibly powerfu l computing circuits to fit in tiny devices. like modem ce ll phones, medical devices, and portable video games. See pages 34 and 35 for a disc uss ion of Moore's Law.
ABOUT THE AUTHOR Frank Vahid is a Professor of Computer Science & Engineering at the Uni versity o f Ca lifornia. Ri vers ide. He holds Electrical Engin eering and Compu ter Science degrees: has worked/consu lted for Hewlett Packard. AMCC. NEe. Motorola. and medica l equipm ent makers: holds 3 U.S. patents: has received several teaching awards; hclped se tup UCR's Computer En gineering program; has a uthored two prcvious textbooks: and has published ove r 120 papers on digital desig n to pics (automation. architeclu re, and low- power).
Reviewers and Evaluators Rehab Abdel-Kader Otmane Ail Moha med Hussa in AI -Asaad Rocio Alba-Aores Basse m A lhalabi Zekeriya Ali yaz iciog lu Visha l Anand Bevan Baas Noni Bohonak Don Bouldin David Bourner Elah eh Bozorgzadeh Frank Cand oc ia Ralph Carestia Rajan M . Chandra Ghulam Chaudhry Michael Chelian Ru sse ll Clark James Conrad Kevan Croteau Sa njoy Das Ja mes Davis Edward Doering Travis Doom Jim Duckworth Nikil Dutt De nni s Fairclough Paul D. Franzo n Subra Ganesan Zane Gastineau J. Dav id Gill a nder, C lay Gl oste r Ardian Grcca Eric Ha nse n Bruce A. Harvey John P. Hayes Mi chae l Helm William HolT Erh-We n Hu Baback ILadi
Georgia Southern University Concordia University University of California. Davis University of Mjnnesota. Duluth Florida Atlantic Un iversity Cal iforn ia Pol ytechnic State UniversIty. Pomona SUNY Brockpon University of California. Davis Uni versity of South Carolina. Lancaster University of Tennessee University of Maryland Baltimore Coun!) Uni versity of California. m i ne R orida International University Oregon Institute of Technology California Polytechnic State Universi!). Pomona University of Mis ouri. Kansas Cit~ Californi a State University. Long Bea h Saginaw Val ley State Univcrsit} University of Nonh Carolina. Charlotte Francis Mari on University Kansas Slare Unh'ersity Uni versi ty of South Carolina Rose-Hu lman Institute of Technolog) \Vrighl Slate Uni \ crsiry \Vorcester Pol) technic institute University of California. Iryine Utah Valle) late College 'orth Carolina uue Unher;il'\ Oakland Uni, ersit) . Harding ni,ersi!) Arkansas tate Unherslt) Howard nh ersil) Georgia S uthem l'nhersit) Dartmouth College FAM U·FSll College of Englne-ering Uni\·e~it) of ~1 ichigan
Texas Tech
Unt\t:'~lt~
C lorad chool of Mine. \ i1liam Ptllcf'lon Unt\en.lt) of l\'e\\ Jef't:~
UNY 'e\\ P:tlu
Reviewers and Eva luators
viii
Jerf J 3ck~OIl An ura J ay a ~ ulllan;} Bruce Johnson Ri chard J o hn ~ toll RJji v Kapadia Bahadir Knruv Robe rt Klenke Clint Koh l Ht:rrnann Kromphol z Timoth y KUI7;Wt:g JUl1lokc L ~l d eji - Osi3s
Jeffrey Lillie
ABOI
David Livingston Hong Man Gihan M ilndour Di ana M :lrculesc tl Miguel [l,llarin M Ll ryHIll M ouss avi
Olb
ABO
Na~raoui
P;:1Irici~1 Nava John Nestor Roge lio Pal oll1cra Ji.IIllC:-. Peckal \Vitale! Pedrycz Andrew Pcrry Denis Popel Tariq Qilyyum Gang Qu M ih:lclu RLldu Suresh Rai William Rcid Mu!.okc Scndnu ln SCOlt Smith
Gary Spivey Lnrry St ephens Jamc!. Stine Philip Swain Shannon T
University or Alabama Colorado State Uni versity Universit y or Nevada, Reno Lawrencc Technologic
Springfield College Bakcr University Cali romia Polytec hnic State Universit y. Pomona University of Maryland Rosc-Hulman Insti tute or Tcc hnology Louisiana Statc UniverSity. Bnt on Rouge Clemson Uni versity Temple Univcrsity Boise Statc University Gcorge Fox University Univcrsity or South Carolina Ill inois InstitUic or Technology Purduc University University or California. Irvinc Gonzaga Universi ty
Oregon Institute of Techn logy Univcrsity or Kansi:\'\ Wright State Ullivcr~ ity Ncw York In,titutc of Tcchnology Roc;hcM:r Institut e of Technology
Califom" Sto te Univcr\ it y. Lo ng Be.lch San Jaoqui n Delt a oll ege
Contents Preface iii
3.3 3A 3.5
Finite-State Machines (FSMs) and Controllers I II Controller Design 120 More on Flip-Flops and Controllm
3.6
Sequential Logic Oplimizations and Tradeoff~
Content s xi
CHAPTER 1 1
Introduction 1. 1 1.2 1.3
1.4 1.5
Digital Sys tems in the World Around Us Th e World or Digital Systems 4 Implemcnting Di gital Systems: Programming Microprocessors versus Designing Digital Circuits 17 About thi s Boo k 23 Exercises 24
(See Section 6.3) 3.7
Sequenlial Logic Descrip[ion using Hardware Description Language..,
(Sec Section 9.3) 137 3.8 Product Profile-Pacemaker 3.9 Chapter Summilr) 1~0 3.10 Exercises I ~O
137
CHAPTER 4
CHAPTER 2 Combinational Logic Design
Datapath Co mponents
30
~. I
2. 1 Introduc ti on 30 2.2 Switches 30 2.3 Th e CMOS Transistor 35
4.2
4.3
2.5
Boolean Logic Gates-Building Bl ocks ror Di gilill Circuits 38 Boolean A lgebra 47
2.6 2.7
Representation s of Boolean Fun ctions 55 Combination:.11 Logic Design Proce s 67
2.4
130
137
2.8 More Gates 73 2.9 Decoders :.1nd Mu xc 77 2. I 0 Add itioll:.11 Considerations 83 2. 11 Combi nmional Logic Optilll iz:.1t ions and Tradeoffs (See Secli on 6.1) 86 2. 12 Combinational Logic Descripti on using Hardware Description L:lI1guagt!s (Sec Section 9.2) 86 2. 13 Chapter Summary 86 2. 14 Exerc ises 87 CHAPTER 3 Seque ntial Logic Design- Controlle rs 3. 1
Introd ucti on
95
3.2
Storing One Bit- Flip.Flop,
96
95
4.4 ~. -
~ .6
150
Introduction 150 Registers 151 Adders 165 Shifters 173 Comparators 177 COunters 18\
4.7 ~lultiplier-ArrJ) t)le 189 4.8 Subtracto.." 190 -t9 Arilhm~tic-Logic L'nib-ALL".., 101 -I-. I 0 R ~2i~ tcr Fil('~ 2O..J 4.11 Da~apath Component Tradeoff, ( co eeuon 6.41 109 . t I ~ D~1I3p:lt.h Component De,C'ription u.qng
Hardware [Xscnption l:mguagc!" eClllln 9A) 109 _16
( ('c
4.13 Chapter Summar) -1-.14 E\r:
"b~!'>
11
CHAPTER 5 Register-Transfer level (RTl) DeSign 1_S 5.1 Introdu("lton .!!.S .5 ..! RTL IX'lell \ l
xii
Contents
vi ii 5.5 Behavioral-Level Design: C to Gates (Oplional) 254 5.6 Memory Components 258 5.7 Queues (FIFOs) 27 1 5.8 Hierarchy-A Key Design Concept 275 5.9 RTL Design Optimiza ti ons and TradeofTs (See Section 6.5) 278 5.10 RTL Design using Hard ware Dcscriplion Languages (Sec Section 9.5) 279 5. 11 Produci Profi le: Cell Phone 279 5. 12 Chaptcr Summary 285 5. 13 Exercises 285
AS
AE
CHAPTER 6 Optimizalions and Tradeoffs 294 6.1 Imroduct ion 294 6.2 Combinational Logic Optimizalions and Trodeoffs 296 6.3 Scquelllial Logic Optimizalions and Tradeoffs 317 6A Dalnpalh Componelll Tradeoffs 333 6.5 RTL Design Optimizations and Tradeoffs 345 6.6 More on Oplimizations and Tradeoffs 354 6.7 Product Profile: Digital Video Playerl Recorder 36 1 6.8 Chapler Summary 370 6.9 Exercises 370 CHAPTER 7 Physical Implementation 379 7. 1 In lroduClion 379 7.2 ManufaclU rcd IC Technologies 379 7.3 Programmable IC Technology-FPGA 388 7.4 Other Technologies 40 1 7.5 IC Technology Comparisons 409 7.6 Prod uel Profile: Giani Video Display 412 7.7 Chapler Summary 416 7.8 Exercises 4 17 CHAPTER 8 Programmable Processors 421 8.1 In!roduclion 42 1 8.2 Basic Architecture 422 8.3 A Three- Instruction Programmable Proce!)sor 428
8A
A Six- Instruction Programmable Processor 434 Example Assembly and Machine Progrnms 438 8.6 Funher Extensions 10 the Programmable Processor 439 8.7 Chapler Summary 44 1 8.8 Exercises 442 8.5
CHAPTER 9 Hardware Description Languages 445 9.1 Introduction 445 9.2 Combinational Logic Description Using Hardware Description Languages 447 9.3 Sequential Logic Description Using Hardware Description Languages 459 9.4 Dmapmh Companelll Deseriplion Usi ng Hardware Description Languages 467 9.5 RTL Design Using Hardware Description Languages 475 9.6 Chapler Summary 492 9.7 Exercises 492
1 Introduction 1.1 DIGITAL SYSTEMS IN THE WORLD AROUND US Meet Arianna. Arianna is a five-year-old girl who lives in CaJjfomia. She's a cheerful. outgoing kid who loves to read, play soccer. dance. and lell jokes thai she makes up be""lf.
APPENDIX A Boolean Algebras 496 A. I BOOlean Algebra 496 A.2 SWilching Algebra 497 A.3 Impanam Theorems in Boolean Algebra 498 AA Olher Examples of Boolean Algebras 504 A.5 Funher Readings 504 APPENDIX B Additiona l Topics in Binary Number Systems B.I Inlroduclion 505 B.2 Real umber Represcnlation 505 B.3 Fixed Poilll Arilhmelic 508 8.4 Floming Poim Represelll," ion 509 B.5 Exercises 514
505
APPENDIX C Extended RTL Design Example 515 C.I Inlroduclion 515 C.2 DeSigning Ihe Soda Di 'pen,cr Con !roller 516 C.3 Undemanding Ihe Behavior of Ihe . odn Dispcn;cr COlllrOlicr nnd Dn",,,nlh 5 19 Index 526
One day. Ananna's family was driving home from n soccer game. She was in the middle of excitedly talking about the game when suddenly the van in which she was riding was clipped b~ 3 car thai had crossed O\'er to the wrong side of the higb", a~ . Although lhe aceidenl wasn·, panicularly bad. the impa I caused a loose item from the rear of the van 10 project forward inside Lhe: van. slriking Ananna in the back of the head. he "cnt unconsciou . Annnna wns rushed to a hospital. Doctors immediatel) noticed that tk!r b~athmg wns vcry weak-a common situ:llion after a se\ ere blo" to the head-.. o ~~ put her onto n ventilator. which is Amedical dl!vice lh::u ~bL' with breathing. he;' hJd ... ~t3Jnro brain tmumA dunng the blow (0 the hend. nnd she rel1lain~ unco~(:i~ for ~ \ern1 weeks. All her vi tal signs were !)t3ble, ex ept ,he ("onllnued to re-qulre breaming a.. . . . I.. Innce fro m the ventilmor. Patients in such tl Idtu3tion some tames 1'l'\."'O\er. .:md 'nnl
I Introduction
viii
1.1 Digital Systems in the World Around Us Thanks to the advenl of modern port able venti lators, Arianna's parents were gi ven the opti on of taking her home while they hoped for her recovery, an option they chose. In addition to the remote monitoring of vi tal signs and the daily at-home visits by a nurse and respiratory therapist. Arianna was surrou nded by her parents, brother, sister. cousins. other family, and frie nds. For the majority of the day. someone was hold ing her hand , singing to her,
Portable ventilators help not only trauma victims. but even more commonly help patientS with debi litating diseases, like multiple sclerosis. to gain mObility. Such people can today move about in a wheelchair, and hence do things like attend school. visi l museum . and take part in a family picnic. experiencing a far better quality of life than was feasible JUSt a decade ago when those people would have been confined to a bed connected to a large. heavy, expensive ventilator. For example. the young gi rl pictured on the left will li kely require a ventilator for the rest of her life-but he will be able to Phoro courtesy of PlllmOI1l'li('~ move about in her wheelchair quite freely. rather than being mostl y confined to her home. The LTV 1000 ventilator described above was conceived and de igned by a mall group of people. pictured on the lefL who sought to build a ponable and reliable ventilator in order to help people like Arianna and thousands of others like her (as well as to make ome good money doing o!). Those designers probably started off like you. reading textPholO cOllrles), oj PIIIII/Ollel;c,,' books and taking courses on digital de ign. programming. electronics. and/or other subjectS. The ventilalor is just one of literally thol/sands of use ful device that have Come about and continue to be created thanks to the era of digital circuits. If you top and think about how many dev ices in the 1V0rid around you rely on or are made po sible becau e of digital cirCuits, you may be quite surpri sed. A few such devices include:
whispering in her ear. and encourag ing her LO recover. Her
sister slept nearby, Some studies show th at such hu man interaction can indeed increase the chances of recovery. And recover she did. One day, several months later, with Arianna's mom sitting at her side, Arianna opened her eyes, Later that day. she was transported back to the hospital. After some time. she was weaned from the ventilator. Then, after a lengthy time of recovery and rehabilitation. Arianna finall y went home. Today, six-yearold Arianna shows few signs of the accident that nearly took her life. What does th is story have to do with digi tal design? Arianna's recovery was aided by a portable ventilator device, which in turn is possible thanks to di gital circuits. Over the past three decades, the amoun t of digital circu itry that can be stored on a single computer chip has increased dramatically_by nearly 100.000 times . bel ieve it or not. Thus. ventilators, along with almost everything else that runs on electrici ty, can take advantage of incredibly powerful and fast yet inexpensive digital circuits. The ventilator in Arianna's case was the Pulmonetics LTV 1000 ventilator. Whereas a ventil ator of the early 19905 might have been the size of a large copy machine and cost perhaps $100,000. the LTV 1000 is not much biooer or hea' h 00 I'ler t an this textbook and costs on ly a few thousand dOllars~small enough, and inexpensive enough, to be c,arned In med ical rescue helicopters and ambulances for life-saving Situat ions, and even to be sent home with a patient. The digital circuits in side conti nua lly mon itor the pat ient 's breathing, and provide just the right amount of air preSSure and volume to Ihe palient. Evel), breath thai the deVice deli vers requ ires 1II;/I;OIlS of compulations for proper delivery, computat ions carri ed ou t by the digital CirCUitS inside.
AI
A
g
Portable velllilator
3
Antilock brakes. ai rbags. aUlofocus cameras. automatic teller rn3 hines. aircraft conrroUers and navigators, camcorders. CilSh regi ster. ce ll phones. computer net\\orks. credit card readers, cruise controllers. dcfibrillmors. digital cameras. DVD players. electri card reader'S. electron ic games. electronic pianos. fax machine!), fingerprint identjfiers. hearing aids. home
securi ty systems. modems. pacemakers. pagers. personal compute". personal digita1 assislants. photocopiers, port able music players. robotic aml . I.,canner-, lele\"ision~. IDc!nn Stat
cOlllrolicrs. TV se t-top boxes. ventilators. vid\!o game consoles-the a ile il/dicalor oj Ihe ra fe I"ar lIe\\' ;III'(:' m;OIl .\' are
deve/oped is Ih e
number of 11(:,11' ptllelltS gran/ct/-
170.000 per yellr i" the U.S. (llolle!
Ii.:,(
goe\ on.
Those devices were created by tens of thousands of designers. including omputer sc ientists. computer engineers. electrical engineers. mechanical engineers. and others. working together wi th scienti sts. doctors. busine s people. teachers. etc. One thing that seems clear is thai new devices wil l continue to be inyented for the foreenelit. Future designers. li ke YOllrselr perhaps. \\ ill h Ip dl'tennine th;}t.
4
1.2 The World of Digital Systems
1 Introduction
1.2 THE WORLD OF DIGITAL SYSTEMS Digital versus Analog
.
. h one of a finite sel of possIble values, A digilal signal is a signal Ihal al any lime can ave log signal can have one of an . ' I [n contraSI , an alia continuouS sional. A signal I.S · I k an d I S a so ' nown as a discrete Si g na. . . . d ' Iso known as a 0 mfil1lle number of possIbl e values, an IS a . I I every inslant of time. An . . I h a unIque va ue a JUSI some physIcal phenomena 11al as ts'lde because phys ical tem. . h temperature ou " . everyday exam ple of an analog sIgnal IS t e b 92 356666 degrees An ture may e · .. . . perature is a continuous value-the lempera ft· you hold up because the . . humber 0 lIlgers , eve ryday examp le of a di gital sIgnal IS l e n fi '1 set of values [n fac t the . 7 8 9 or IO--a 111 e ., va lue must be en her 0, I, 2. 3, 4, 5, 6. , , ' . . (d"1 s) 111eaning finoer .. " .. . d f "dl on" Igl U , 0 . lerm dlgnal comes from Ihe Lalln wor or 0 . I those th'lt can have one of dOoital siona s are ( In compuling syslems, Ihe mOSI common 10 0 d 1 or 0) . Such a two-valued . I'k ff (often represenle as on Iy two possIble values. I'e on or 0 . d' '1 I slem is a system that takes . . k b' resenlauon. A Igl a sy representauon IS ' nown as a lIIary rep .. .. . nnection of digital com.. . .. I A dlgllal clfclIIl IS a co dlgnal mputs and generates dlgna out pUIS. . b k the term dioital wi ll refer 00 ponenlS Ihat logelher comprise a digilal system. [n thIS text 1 k' own as a binary digit or A' I binary slona IS n , , . . . 10 systems wnh bmary-valued sIgnals. slllg e 0 I ular in the mid-1900s bil fo r short (binary digit). Digi lal electrolllcs became extreme YbPOPI med 011 or off usin o . ' switch thaI can e uh 0 after the . mve. nllon of the transIstor, an eIectnc . . f rther in the next c apler. another electric signal. We' ll descnbe IranslSlors u .
A geneml-pllrpose compllfer
Embedded systems
Digital circuits are the basis for computers d . b bl . . ICIrCUI ' 'Is 'n The most well -k nown use of dlgna I the world aroun us IS pro a yI'kto build the microprocessors that serve as the brain of general-purpose computers, I e h t you mi ooht have at. home. Generalthe personal computer or laptop computer ta purpose computers are also used as servers, \vhich operate behllld . the . scenes to implement banking, airline reservation, web search, payroll , and SImilar such systems. General-purpose computers take digital input data, such as lellers and numbers received from files or keyboards, and output new dIgItal data, such as n~w lellers and numbers stored in files or di splayed on a monitor. Lear,~ lI1 g about dlglt~~ design is therefore useful in understanding how computers work u.nder the hood, and hence has been required leaming for most computing and ele~t nca lengineenng majors for decades. Based on material in upcoming chapters, we II deSIgn a SImple com puter in Chapter 8. Digital circuits are the basis for much more " Increasingly, di gital circuits are being used for much more than Implem: ntmg general-purpose computers. More and more new applicallonsconve.rt analog SIgnals to digital ones, and run tho e digital signal s through customIzed dlgllal CirCU Its, .to achieve numerous benefits. Such applications include cell phones, automobIle engine controllers, TV set-lop boxes, music instruments, digital cameras and camcorders, video game consoles, and so on. Digital circuits found inside applications other than general-purpose computers are often called embcllded sysl ems, because those digital systems are embedded inside another electronic device.
o ~
5
The world is mostly analog, and therefore many applications were previously implemented with analog circuits. But many implementalions have changed or are changing over to digital implementations. To understand why, we might first notice Lhat although the world is Sound waves •_____ ..::::L ________ . most ly analog, humans often obtain advantages when converting move the analog signals 10 digital signals before "processing" that infonnation. For example. a car horn is actually an analog signal-the volume cao take on infinite possible va lues, and the volume varies over time due to variations in the battery sLrength, temperature, etc. But. we i + j the magnet. humans neglect those variati ons, and we "digitize" the sound we hear , , into one of two values: the car hom is "off." or the car hom is "on" (gel out of Ihe way!). Converting analog phenomena to digital. for use with digital cirwhich creates CUi IS, can also yield many advantages. Let's illustrate this point by current in the nearby wi re considering one example, audio recording, in some detail. Audio is clearly an analog signal. with infinite possible frequencie and volumes. Consider recording an audio signal. li ke music, through a microphone. 0 that the music can laLer be played over speakers in an electronic stereo y tem. One type of microphone. a dynamic microphone, works based on a principle of electromagnetism-moving a magnet near a wire causes changing current (and hence voltage) in a nearby wire. The more the magnet moves. the higher the VOltage on the wire. So a microphone has a small membrane attached to a magnel near a wire-when sound hits the membrane, the magnet moves. causing current in the wire. Likewise. a peaker works on the same principle i; reverse--a changing current in a wire wi ll cause a nearby magnet to move, which if allached to a membrane wi ll create sound . (If you get a chance. open up an old speaker- you'lI find a strong magnet inside.) If the microphone is allached directly to the speaker (through ao amplifier that strengthens the microphone' output current), then no digitization is required. But what if we want to save the sound on ome sort of media, so \\e cao record a song now and play the song back later? We can record sound using analog methods or digital methods. but di gital methods have many advantages. One advantage of digital methods is lack of deterioration in qualiry over time, When I was grow ing up, the audio casselle tape, an analog method. was the mo t common method for recording song. Audio tape contain huge numbers of magnetic particles that can be moved to particular orientations using a magnet and that hold that orientation even after the magnet is removed. Thus, using magnetism, we could hange the tape' surface. ome pans up. ome higher. some down. etc. This is similar to how you can -pike your hair, some up, some sideways. some down. using hair ge\. The po ible orientations of the tape's particles. and your hair, are infinite, so the tape is definitely anal g. To record onlO a tape, we pas the tape under a "head" that generates a magnetic field based on the electric current over the wire coming from a microphone. The tape' panicle "ould thus be • the t:lpe moved to particular orientations. To playa recorded song back. \\c \\ uld under the head again, but this time the head operate in reverse, genernting current Q\ r a wire based on the changing magnetic fie ld of the tape. and that current then gets amplified and sent to the speakers.
:I '+
: '
I IU 6.'d i::i~hb:::~s
t ===_
l ___ ~!:~ ~~~_~~_'!--. .:-="=:
,
6
1.2 The World of Digital Systems
I Introduction analog signal on,wire
, ,, ,, ,
", ___ digitized signal ,,--- 000 11 01011 111101101 000
analog signal reproduced from
read from tape. CD. etc.
000 1101011111 101 101 000
,digi~ize~ signal
,, "" ,
wi re
: :
"
Ii : If "
0/
I
,
,
1 :
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I
,
,
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:
\ :.
t.tOO : 01 :10 : 10 : 11 : 11 : 11 :01 , 10 , 10 ,00 , time
speaker
. d' . I . al (top). and vice versa (bollom). Notice Figure 1.1 Converti ng an analog Signal 10 a Igna sign some quality loss in the reproduced signal.
is that the orientations of the panicles on the tape's ~ . . . A pro blem W .ith aud'10 tape surface change over time- just like a spiked hatrdo In the morning eventually flatten s o~t throughout the day. Thus, audio tape quality deteriorates over time. Such detenoratlOn IS a problem with many analog systems. . .. . Di gitizing the audio can reduce such deterioration. Digiti zed audIO :"orks as shown in Figure 1. 1. The fig ure shows an analog signal on a wire dunng a period of ttme. We sample that sional at panicular time intervals, shown by the dashed hnes. Assummg the analog signal ~an range from 0 Volts to 3 Volts, and that we plan to store each sample usin o two bits. then we must ro und each sample to the nearest Volt (0, 1, 2, or 3), shown as p~ints in the figure . We can SlOre 0 Volts as the two bits 00, I Volt as the two bits 01 , 2 Volts as the two bits 10, and 3 Volts as the two bits 11. Thus, we wou ld conven the shown analog signal into the fo llowing digital signal : 00011010111111 0 11 0 1 000. To record thi s di gital signal, we just need to store Os and Is on the recording media. We could use regu lar audio tape, using a short beep to represent a 1 and no beep to represent a 0, for example. While the audio signal on the tape wi ll deteriorate over time, we can still certai nly tell the difference between a beep and no beep, just like we can tell the difference between a car hom bei ng on or off. A sligllll y quieter beep is still a beep. You 've likely heard digi ti zed data commu nicated using a manner simi lar to such beeps when you've picked up a phone being used by a computer modem or a fax machine. Even betler than audio tape, we can record the digital signal using a media spec ifically designed 10 store Os and Is. For example, the surface of a D (compact di sk) can be configured to ei ther refl ect a laser beam to a sensor strongly or weak.ly,
7
Ihu s sloring Is ~nd Os eas il y. Likewise. compUler hard disks in compuler use magnetic panicle onematl on 10 Slore Os and Is, making such disks si mil ar 10 audio tape. but enabling fas ler access to random pans of the disk since the head can move sideways across the top of the spinning disk. To play bac k this digitized audi o signal, we can simpl y conven the digital value of eac h sampling peri od to an ana log signal, as shown at the bOllom of Figure 1. 1. Notice Ihal Ihe reproduced signal is not an exact repli ca of the ori gi nal analog signal. However. the faster we ample Ihe analog signa l and the more bits we use for each sample. the closer Ihe reproduced analog signal derived from the digil ized signal will be to Ihe origina l analog signal- a! so me poinl , humans can' l not ice Ihe difference between a pure audio signal and one thm has been digitized and then convened back to analog. Another advan lage of digitized audio is compres ion. Suppose Ihat we'lI be lOring each sample with ten bits, in stead of IWO bits like above, 10 achieve much beller quality due 10 less rounding. But thal 's a lot more bils for the same audi o-the signal in Figure 1. 1 has eleven amp les, and a[ len bils per sample. that yields one hundred ten bits 10 store the audio. If we sampl e hundreds or Ihousands of time a second. we end up with huge numbers of bil s. Suppose, though, that a panicular audio recording has many samples th at have Ihe value 0000000000 and Ihe value 111111111l. We could compress the digital file by using the following trick: if the firsl bit of a ample i O. the nex l bit being 0 means the sample is actually supposed 10 be expanded 10 0000000000: the nex t bi t being I means the sample i 111111111l. So 00 i shonhand for 0000000000. and 01 is shonhand fo r 1111111111. If the first bil of a sa mple is l. then the next len bits represent the actuaJ sample . So the digitized signal "0000000000 0000000000 0000001111 1111111111 " would be compre cd to "00 00 10000001111 01." The receiver. which must know the com pres ion scheme, wou ld decompress that signal into the original digitized signal. There are many other tricks that can be used 10 compress digitized audio. Perhaps the mo tly widely known audio compression scheme is known as MP3. which is popular for com pres ing digitized songs. A typical song mighl requ ire many lens of megabyle uncompre ed. bUI compressed usually only req uires about 3 or 4 megabyte . An audio CD can lore aboul 20 songs uncompressed. but aboul 200 ongs com pres cd. Thanks 10 compre ion (combined wilh higher-capacily disks), loday ' ponable music players can tore thousands of songs-a capability undreamt of by mo I people in Ihe 1990 . Di giti zed audio is widely used not only in mu ic recording, but also in voi e communicali ons. For example. digilal ce llul ar telephones digitize your voice and then compres the digilal signal before transmilling Ihe ignal. enabling far more cell phones to operate in a panicul ar region than possible using analog cell phones. Satellites DVD Video players recorders Portable Cell phones music players Cameras 1995
1997
1999
2001
2003
2005
MusJCal instruments
TVs 2007
Figure 1.2 More and more analog produ ts are bt.-coming primarily digit!!.!.
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•
1.2 The Wo rld of Digital Systems
8
Introductio n
9
Digital Encodings and Binary Numbers
manner sl11111ar 10 that descnbed for aud.o. Pi ctures and video can be dlgll ized In a , h ghl y-co mpressed dl glla l fo rm . and pictures In I Dl glla l Cdmems. for example, slOre d sks In compressed form too dlgllal Video recorders SlOre Video onlO tapes or I few of the hundreds of new a nd d Video arc Just a . Dlg lli zed audiO, pictures. an of ana 100 phenome na As shown 111 zalion '" d Illl ure ,'ppl ,callo ns th at bene fi t from dl",lI '" lar products prev IO usly base o n d de numerouS popu ' ani 10 dlgllal technology Ponable muSiC Figure I 2. over the past eca. to CDs In the midd le 1990s, a nd "n 310g technology. ha ve conve rted pnm, Y I d from cassette tapes I \I phones used analog comm UOlcapl,.ye rs. for exampl e. SWIIC1e lecent ly to MP3s and other dlgll al form ats Ear y ce mdar In Idea to that shown 111 1990 d tal commulllcallon , S. tl o n. but In the late s Igl , I 2000s, analog VHS v.deo players gave way Figu re 1. 1. beca me do minant In the ear y b t dl ollize v.deo be fo re stonng the 'd corders have egun 0 '" to d lg llal DVD players. VI eo re d fi l ntlfely and In stead slOre photos m e . ha ve eliminate vlcleo o nto tape. wh. Ie cameras Iy d. gllal-based wllh e lectrontC 1 t l1cnts are Increasmg . uSin g dlglla l cards Muslca inS rU I ' rit and electnc gUllars w llh d .g .tal prodrums and keyboa rds IIlc reasIng III popula Y'. . Y 10 di oital TV. Hundreds of . . I A aloo TV IS also giVing wa '" cess lIlg appea nng recent y. n '" . . I' st decades such as cloc ks a nd other dev ices have conve rted from analog 10 d.glta InhPa ometers (' which now wo rk in t human temperature term watches, ho usehold th ermosta s, ) gine controllers oasoline the car ra ther than under the tongue or other places car en . e
The previous section showed an example o f a di gital system, which involved digitizing an aud io signa l into bits, which we could the n process using a digital circuit to achieve several bene fits. Those bits el/coded the data of interest. Encodi ng data into bits is a central tas k in di g ita l systems. Some of the data we want to proces may already be in di gita l fo rm, whi le other data may be in ana log form (e,g. aud io, video. temperature) and th us req uire convers ion to dig ital data first , as illustrated at the top of Figure 1.3. A di gital syste m takes di gi tal data as input, and produces di g ita l data as output. E ncoding a na log phenomena An y ana log phe no mena ca n be digitized, and hence cou ntle s a pplications have evolved and contin ue to evolve that digiti ze ana log phenomena. Automobiles digitize informatio n about the e ng ine te mperature, car speed. fue l leve l. e tc., 0 that an on-chip compute r ca n moni to r and contro l the vehicle. The ventilator we introduced earlier digiti zes the measure o f the air fl ow into the patient, so that a compute r can make calcu lations on how muc h addition a l Row to provide. And so on. Digitizing analog pheno mena req ui res;
t
pumps. hea rin g aids. and so on.
. d bein o introduced in di gital form from the o. .' . .d oes have been di gital sillce thelf IIlceplion . . ve ry start. For example. VI eo ",am .' 1 d Os. Computations uSlllg Di giti zat ion requ ires that we encode tillngs Into sl an d Os We introduce these di gi tal circuits require that we represent numbers usmg s an . aspects of digital circuits now.
Many devices were never analog. IOstea
Figure 1.3 A typical di gital system.
Sell and his assistant Watson disagreed on
operates using the electromagnetic principle described earlier-your speech creates sound waves that move a
how
membrane. wh ich moves a magnet, which creates
current on a nearby wire. Run that wire to somewhere far away. put :l magnet connec ted 10 a membrane near that wire. and the membrane will move, producing sound
waves tha. sound like you talking. Much of .he telephone system today di gitizes the audio '0 improve quality and quantity of audio transmissions over long distances. A
couple of illleresting facts about the .elephone; Believe it or no•. Western Union actuall y tumed dow n Sell's initial proposal to develop the telephone. perhaps .hinking that the then-popular telegraph was all people needed.
to answer the
phone; Watson wanted "Hello:' which won. but Sell wanted "Hoy hoy" instead, (Fans of the TV show "The Simpsons" may have noticed lhat Homer's boss, Mr. Sums, answers the phone with a "hoy hoy." )
o0
1 0 000 1
"' t's 33 degrees" All early-slyle ,elepltolle.
(Source of some of the above materia l: www.pbs.org. trunscript of '1'he Telephone").
An alia log-la-digital call verIer that convens the electrical ignal into binary e ncodi ngs. The converter must sample (measure) the e lectrical signal at a panicular rate and conve n each sample to some value of bits. Such a converter was featured in Figure 1.1, and hown as the A2D compo nent in Figure 1.3. Likewise. a digilal-Io-allalog COli verier (s hown as D2A in Figure \.3) convens bits back 10 an e lec trical s ignal , a nd an achlOlor convens mat electrical signal back to physica l phenomena. Sensors and actuators together represent type of devices known as Irallsdllcers--devices that convert one form of e nergy to anomer. In many examples th roug hout this book, we will utili ze idealized sensors mat themselves directly output di g itized data. For example. we might utilize a temperature sen or that reads me present tempe rature and sets its 8-bit output to an encoding mat represents the te mperature as a binary numbe r (see next sections for binary number encoding ).
.. THE TELEPHONE. The telephone. pmented by Alexander Graham Sell in the late 1800s (though invented by Antonio Meucci).
A sel/sor that mea ures the analog physical phe nomena and converts me measured va lue to an ana log e lectrical signa l. One example is the microphone (which measures sound ) in Fi gure 1. 1. Other common examples include video capture devices (whi ch measure li ght), thermo meters (which measures temperature). and speedo me te r (whic h measure peed).
E ncoding digita l phenomena Other phenomena a re inhere ntl y di g ital. Such phenomena can only as ume one value from a finite set of values. So me d ig ita l phenomena can a ume only one of two pos ible value. and mus can be straigh tforward ly e ncoded as a sing le bit. For example. the following types of sensors may output an e lectri cal signal that a umes one of twO valu : Motion sensor; o utputs a positive voltage (say volts when no mot ion is sensed.
+.' )
when motion is en
. 0
10
1 Introduction
1.2 The World of Digital Systems
when li oht is sensed, 0 V when dark. ' . d 0 V when Light sensor: outputs a pOSlllve volta " C " .. I ge when the button IS presse . Button (sensor): outputs a posllive vo ta nOl pressed . r's output to a bit. with 1 representi ng We can straight forwardly encode each senso I tl oughout thi s book we will the pos iti ve voltage and 0 representing 0 V. In examp es . lr I ' .. . . . I t t the encoded b11 va ue. utili ze Idea lized sensors that dIrect y OUpu 'bl I s For example a keypad , e several POSSI e va ue . Other digital phenomena can assum ' bl k A desioner mi oht create a ' oreen.' and. ac. " 001;" blue might d blu ~." may have four bUllons. co lored re. h the value circuit such that when red is pressed. a three-bll output as d the output mioht be 000. output 010 . green 011. and black 100 . If no bunon IS presse , " "
a
a
t
a
.
0
na IS the Enollsh alphabet. Each FIgure I 4 Illustrates such a keypad An even more general di gItal phenome " keyboard " fi t set of characters so typtng on a f ' th d tal data to bIts by charactcr comes rom a nt e I data We can convert e Igl results tn dlgl ta I. not ana og, . I odll1 o of Engltsh assl o nll1g a bl l encodtng to each character A popu ar e~c d" d Code for cha;;'cters IS known as ASCII (standtng for Amencan tan ar F des each character tnto seven blls. or 'A" "1000001" and Inlormalton Interchange). wIllCh enco CII d fo r Ihe uppercase lener IS , example. Ihe AS enco IIIg . , , , 00001 " d 'b' IS "1100010." for 'B' IS "1000010 " A lowercase a IS 11 , an 1000010 Th ' h e "ABBA" would be encoded as "1000001 us. I e nam d ' II 26 I tters (upper 10000101000001 " ASCII defi nes 7-blt enco tngs .or a . e . I sy mb0Is 0 tllrouoh and lowercase), Ihe numenca '" 9 punctuatIon " . marks, ande even a number of encod ings fo r nonprinlable "control operaltons. There ar 128 encodings 10lal in ASC Il . A subset of ASCli encodll1gs .IS shown .in Figure 1.5. Another encoding, Unicode, is increasi ng tn popul anty due to Its support of international languages. Unicode uses 16 bils per character, II1s tead of jusl the 7 bils used in ASC II , and represenls characters from a dIversity of languages in the world .
Figure 1.4 Keypad encodings.
Symbol
Encoding
R
1010010 1010011 1010100 1001 100 1001110 1000101 0110000 0101110 0001001
S T N
E 0
Symbol
Encoding
1110010 1110011 1110100 1101100 1101110 1100101 0111 001 0100001 0100000
Figure 1.5 Sample ASCn encodings. Encoding numbers . . Perhaps the most important use of digital circuits is to perform arithmetIC computallOns. In fact , a key dri ver of earl y digital com puter design was the arithmetic computations of ballistic trajectories in World War L1 . To perform arithmetic computat ions, we need a way to represent numbers using binary digi ts-we need binary numbers.
~
WHY BASE TEN?
Humans have len fingers. so they chose a numbering system where cHeh digi t can represent len poss ible
values. There's nOlhing magical aboul base ten. If humans had nine fingers, we'd probably usc a base nine numbering sys tem. It !Urns Out thut base twelve was used somewhat in the past 100, because by using our lhumb. we can easily point 10 twe lve different
spots on the remaining four fingers on that Ihumbs's
523
Figure 1.6 Base len number system.
The Wt,b s('(lf'C:h engin e Google's Illlm e cOllieS from ,IIe lI'om "googol"
f ollowed by JCKJ :.elves,
-(J }
aplJllrelllJy
imply ing the ellg ille ellll search
a/% j '-,l/o rl1lal;oll.
o Figure 1.7 Base Iwo number system.
I sail' the/ollowillg 011
II
a T-shirt, ami
Jound il rather
filllllY:
"TIlere nrc I0 types or people in the world: those who get binnry. and
those who don't."
hand-the four tops of those fingers. the four middJe pans of Ihose fingers , and the four bottoms of those fingers. Thm 's likely why the number twelve is common in human counting today. Uke the use of the term "dozen," and lhe lwelve hours of a clock. (Source: " Idem. and Information: ' Arno Pen'lias. W.W. Nonon and Compa ny).
To under tand binary numbers, we might firsl ensure Illat we understand decimal numbers. Decima l numbers use a base len numbering syste m. The basic definition of base len is a numbering syslem where the rightmost digit represent the number of ones ( LO~ we have. the nexi digit represents the number of groups of tens (10 1) we have. the next digit represents the number or groups of len tens ( 102) we have. and so on, as illu trated in Figure 1.6. So the digi ls "523" in ba e 10 represent 5* 102 + 2*10 1 + 3*100. Because humans have ten fin ger. they developed and used a ba e ten numbering system . They came up with symbols to represent quan litie ranging from no fingers (0) to all the fin gers but one (9)-lhese are called "ones" rather than "fingers" though. because we aren' t always counting fin gers. To represem a larger quantily than nine one , humans introduced another digil to represent the number of groups of all the fingers. called "ten." NOle thai we don't need a unique symbol for the quantity ten itself. ince that quantity can be represented as one group of ten and no ones. To represent more than nine tens. humans introduced yet another digit, 10 represent the number of groups of len tens. which are called "hundreds." To represent ten hu ndreds, they introduced another digit. called "thousands. " English (as spoken in America) doesn't have a name for a group representing ten thousands. nOr for the group representing ten ten thousand . which is referred to as hundred thousands. The next group is called millions, and further group that are mu ltipl es of one thousand have names too (billions. trillions, quadrillions. etc.). Now that we better understand base ten numbers. we can introduce base two numbers. know n as bi/lary /lllll/b ers . Since digital circuits work with values that are either "on" or "off," such circu its need only two symbols. rather than ten ymbols. Let tho e two symbols be 0 and I. I f we need to represent a quantity more than I. we'll use another digil, whi ch wi ll represent the number of groups of 21 which we'll call two. So "10" in base two represenlS I IWO and 0 ones. Be careful nOI to call "10" ten-in tead. you might say "one-two." If we need a bigger quantity. we'll use another digil. which "ill represent the number of groups of 2 2 , which we'll call four. The weights of each digit in base two are shown in Fi gure 1.7. For example. the number 101 in base IWO equal 1*2 2 + 0*2 1 + 1*_0. or 5. in base ten. In other words. 10 1 can be poken as "one-four zero-two one-one." I t people comfortable with binary might instead ju t say "one zero one." To be "ety lear, you might say "one zero one, base two:' But you should definitely /lOT say "one-hundred ne, base two." 101 is one-hundred one in base ten. but Ihe leftmost 1 does not repre,.;em nehundred in base IWO.
12
1 Introduction
1.2 The World of Digital Systems Knowing powers of two
~ COUNTING "CORRECTL Y" IN BASE TEN. The fJe l Lhill there are name~ for ~omc of the groups in base ten. but 110( o lhcn" prevents many people from
g3i ning an intuitive underslunding of base ten. Further liddi ng to the co nfusion arc the abbreviated names for
gr ups of lens-the numbers 10. 20. 30..... 90 should be ca ll ed One len. two ten. three len..... ninc ten . but instead use abbreviated nam es: one tc n as just "ten:' Iwo tell as " twe nt y:' three len us " thirt y," " .. and nine len as ·'ninety." YOLI can sec how "n inety" is a
I think makes more sense). Thus. the num ber 523
~~:~
Id be spoken as "fi ve- hundred two-ten lhree" rnt~er "five-hundred twenty- three:' I believe Lhat kids
have a harder time learni ng math because ofin thea
confusing number naming-for example. carry g one from the ones column to the tcns"column make~ more sense if the ones column adds ( 0 o n~ ten seven rather than to "seventcen"-the resul ~ obvl ~ u s l y. adds
!-honcning of "nine ten:' Funhcnnore. short names arc also used for the numbers between 10 an d 20. II o;hould be "o ne len o ne: ' but is instead "cleven," wh ile
one 10 Ihe tens column. Learning btnary tS slightly harder for some studenls due 10 a lack of a solid understanding of base 10. caused largely by the naming confusion. Perhaps. when a store clerk tells
19 should be " one ten nine" but is instead "nineleen," Tab le 1.1 indictll es how 10 count "correclly" in b3se ten
you "that will be ninety-nine cents." y~u can co~ecl him by saying "you mean ~ine: ten nme ~ent s . Lf
(where I boldly define "correcll y" us counling the way
enough of us do Ihis. perhaps 11 wtll calch on.
TABLE 1.1 oto 9
,
helps in learning binary:
Counting "correctlv .. in base ten. A s usu:.ll: "zero;' ··one." "two;' etc.
10 10 99
".:" "one 10. 11. 12. , .. 19: "one tcn," "one ten onc... ..one len I wo, .. ten nine" 'ne" 20. 2 1. 22 .. ... 29: "two ten:' "two ten one," "two len two, ... two len nl 30. 40 . ... 90: "three len," "four ten," ... "nine len"
100 10 900
As usual: "one hundred." "two hundred," ... "nine hundred." Even bener wou ld be 10 replace the \ ord "hundred" by "len to the power of 2."
1000 and up
As usual. Even bener: replace "thousand" by "ten 10 Ihe power of 3". "len thousand" by "len to the power of 4:' e IC.• eliminati ng all the names.
as "one zero one in base two equals five in ba e ten."
16
8
2
Figure 1.8 Basc two
num ber
"'y~ l e l11 .
EXAMPLE 1.1
256 512 1024 2048 ...
EXAMPLE 1.2
When converting from binary to decimal , people often fi nd it useful to be comfortable knowing the powers of two. since each Success ive place to the left in a binary number is two times the previous pl ace. In binary. the firs!. righlmost place is 1. the second place is 2, then 4, then 8. 16. 32. 64. 128, 256. 512. 1024. 2048. and 0 on. You might top at this poinl to practice counting up by powers of Iwo: 1,2.4.8. 16.32,64. 128, 256. 512. 1024. 2048, etc .. a rew times. Now. when you see the number 10000 Ill. YOll might move along the number from righ t to lefl and count up by powers of two for each bit to delermine Ihe weight of the leftm ost bit: 1.2,4.8. 16.32.64. 128. The nexl highest 1 ha a weight of (counting up again) 1,2. 4; add ing 4 to 128 gives 132. The next I has a weighl of 2; addi ng Lhat to 132 gives 134. The rightmost 1 has a we ight of I; adding Ihat to 134 gives 135. Thus. 10000 III eq ual 135 in base ten. Counting in binary Count ing from 0 10 7 in binary looks as follows: 000. 001. 010. 011 , 100. 101. 110. III. An interesting fact abo ut binary numbers-you can quickly determi ne whether a binary num ber is odd j ust by checking if the rightmost digit has a I. If the righLmost digil is a O. Lhe number mllst be even, since the number is the sum of even number . Converting between decimal and binary numbers using the subtraction method As we saw earli er, converting a bin ary number to decimal is easy-we j u t add the we ights of eac h dig it having a 1. Converting a decimal number to binary take slightly more effort . One mel hod for converting a decimal number to a binary number that is easy for humans to carry o ut by hand, which we' ll call the sllb/ractioll m e/hod. i hown in Table 1.2. The met.hod starts wiLh a binary number thal is all Os. TABLE 1.2 Subtraction method for converting a decimal number to a binary number. Slep Descripti on
When we are writ ing numbers of different bases and the base of the number is not obv ious. we indicate the base with a subscript, as follows: 101 2 = 5 10 , We mt ght say thiS
o
lJ128
2 4 8 16 32 64
13
,
Note that since bi nary isn' t as popular as decimal. people haven I created short names for its groups of 21. 22, and so on. like they have for groups in base ten (hundreds, Lhousands. millions, etc.). Instead . people just use the equivalent base len name for the group--a sou rce of some confusion to people just learning binary. Nevertheless, tt may sLil1 be eas ier to think of each group in base two uSlllg base 10 names, rather than increasing powers of two, as show n in Fig ure 1.8. Binary to decimal Convertlhe following binary numbers to deci mal numbers: 1. 11 O. 10000. 10000 Ill. and 001 10. 0 12 is jusl 1*2 . or I/ o. . . 110, is 1*2 2 + 1' 2 + 0*20. or 6 10, We mighl lhink of Ihis using the group wetghls shown In Figure 1.8: 1' 4 + 1*2 + 0*1. or 6. 10000, is 1' 16 + 0*8 + 0' 4 + 0' 2 + 0' 1. or 1610, looooi 1h is 1' 128 + 1' 4 + 1*2 + 1' 1 = 135 10, Not ice Ihis lil11e Ihat we didn ' l bother to write O~I th e groups with a 0 bit. 001 102 is Ihe sal11e as 11 02 above - the leading O's don'l change Ihe value.
0. PUllin PUI a 1 in the highesl binary place who e weigh I is less than or equal 10 the c:;;" highest place dec imal number. Updale N Updale the decimal number by Subtntcling the highesl binary place's \\ eight from 0. decimal the decimal number. The new decimal number is lhe remaining quanti£)' to be c:;; " number converted 10 binary. If Ihe updaled deci mal number is nOI zero. return 10 step I.
For example. we can convert the decimal number 12 as shown in Figure 1.9.
1. Put 1 in highest place Try place 16. too big (16)12) Next place. 8. is highest (8<12) 2. Update decimal number Decimal not zero. return to Step 1 1. Put 1 highest place Next place. 4. is highest (4=4) 2. Update decimal number Decimal number is zero. done.
Decimal Binary 12 )( 1 0 0 0
168421
(current value
is 8)
-8 4
1
-4 -0-
1 0
0
168421
(cumm' value IS 12)
Figure 1.9 Converting Ihe decimal number 12 10 binary usi ng the ubtntclIon "lethO
14
Int rodu ction 1.2 The World of Digha l Systems W
e cu n c heck Our wo rk by co nven in " 1100 back to eC 'Il n ,al'. 1*8+ 1*4 +0*2 +0*2. = 12. A s a no th e r example. Figure 1. 10 illustrates the subtrac ti o n method fo r convert 109 t~e d ec ima l number 23 to bin ary. We can chec k our wo rk by co nvertlll g the lesu lt, 101 1 ,
15
d
~ 1. Put 1 in highest place Place 32 too big, but 16 works. 2. Update decimal number Decimal not zero, return to Step 1
1. Pu t 1 in highest place Next place is 8 . too big (8)7) 4 works (4<7) 2. Update deci mal number
23
~ 10
0 00
168421
-16
2. Divide quotient by 2
(current value
is 16)
1 0
0
168421
(current value is 20)
1 0
1. Put 1 in highest place
Decimal nol zero , return to Step 1
Decimal number is zero, done
1 1
0
168421
-2
1
3. Divide quotient by 2 Insert remainder Into the binary number Continue since quot ient (1) is greater than 0
213
4. Divide quotient by 2
2V1 -0 l'
-2
l'
o
Insert remainder into the binary number Quotient Is 0, done
(current value is 22)
Figure 1.11 Converti ng th e decimal num ber 12
10
0
0
21 (current value: 0)
1 0 4 2
0 1
(current value: 4)
1 0
0
8421 (current value: 12)
binary using the divide-by-2 method.
1
EXAMPLE 1.4
1. Put 1 in highest place
Nexl place is 1, works (1=1) 2. Updale decimal number
o
-4
-3-
Decimal number not zero, return to Step 1
Next place is 2. wo rks (2<3) 2. Updale decimal number
2.[6 -6
Insert remainder into the binary number
Continue since quotient (3) is greater than 0
- 7 1 0
~+'J
1. Divide deci mal number by 2 Inse~ rem~inder into the binary number Conllnue since quotient (6) is greater than 0
back to d ecimal: 1* 16+0*8+ 1*4+ 1*2 + 1* 1 =23.
1
0
1
1
168421
-I
(current value
i523)
Convert th e followi ng numbers to bi nary using the div ide-by -2 method: 8. 14.99.
o
Figure 1.10 Conve ni ng the decimal number 23
to
To convert 8 to binary, we start by di vidi ng 8 by 2: 812=4, remainder O. Then we divide the quoti ent , 4, by 2: 412=2. remainder O. Then we divide 2 by 2: 212=1 . remainder O. Finally. we divide I by 2: 1/2=0. remainder I. We stop di vidi ng because the quotient is now O. Combining all the remainders. least sig nifican t.digi t. fi rst, yields the binary number 1000. We can check this answer by mullip lYlllg eac h binary dig it by liS weight and adding the terms: 1*23 + 0*22 + 0'2 + 0'20 = 8. ' To conven 14 tn binary, we follow a similar process: 1412=7. remainder 0.712=3. remainder I. 3/2= I, remainder I. 112=0, remainder I. Combining the rem ainders gi ves us the binary number 1110. Checki ng the answer verifies that 1110 is correct: 1' 23 + 1*22 + 1'2' + 0' 20 = 8 + 4 + 2 + 0 = 1.1. To conven 99 to binary. the process is the arne but natumll y takes more step: 9912=49 remainder I. 49/2=24, remainder I. 24/2= 12, remai nder O. 1212=6. remainder O. 612=3 , remainder O. 312= I. remai nd er I. 112=0. remai nde r I. Combining th e remainders tnge ther gives us the binary number I 1000 1I. We know from Example 1.3 th at this i the correct answer.
binary using the sublIacti on method.
EXAMPLE 1.3 Decimal to binary Convert th e fo llowing deci mal numbers to binary using the subtrac ti on me thod : 8, 14, 99. To convert 8 to binary. we start by putting a I in Ihe 8's place, yieldin g 1000. Since 8-8=0, we are done-the answer is 1000. To co nve rt 14 to bi nary, we stan by pUiting a I in the 8's place (16 is too much). yielding 1000. 14 -8 =6. sn we PU I a I in th e 4' place. yielding 11 00.6 - 4 = 2, so we put a I in th e 2's place, yieldi ng I I 10. 2 - 2 = 0, so we are done-the answer is 111 0. We can quick ly chec k our work by conve rtin g back 10 decima l: 8 + 4 + 2 = 14. To convert 99 to bi nary, we stan by pu tting a I in the 64 's place (the nex t hi gher place, 128. is too bi g-noti ce that being able to count by powers of two is handy in this problem), yielding 1000000.99-64 is 35, so we PU I a I in the 32's place, yieldi ng 1100000.35-32 is 3. so we put a I in the 2's place. yieldi ng 11 000 10.3 -2 is I. so we put a I in the I 's place, yielding th e fina l answer of I 1000 I I. We can chec k our work by conven.ing back to dec ima l: 64 + 32 + 2 + I = 99. Convertin g betwee n decimal and binary numbers using the divide-by-2 method An a lte rn ative approach for co nverting a decimal number to binary, perh aps less intuitive th a n the s ubtrac ti o n method but easier to automate using a comp ute r p rogram , invo lves re pea ted ly dividing th e decimal number by 2-we' ll call this the divide-by-2 m ethod. The rem a inder at each s te p (ei ther 0 o r I) beco mes a bit in the binary numbe r, s tarting from the leas t s ig nifi cant (ri g htmost) digit. For exa mple, th e process of convertin g the dec imal number 12 to binary us ing th e d ivide-by-2 method is show n in Fi g ure 1. 11.
Decimal to binary using the divide-by-2 method
Con ve rting fr om any base to any other base using the di vide-by-n method We have bee n di v iding by 2 in o rder to conven to base 2, but we can u e the arne basi meth od to conve rt a base 10 number to a number of any base. To conven a number from base 10 to base 11. we s impl y repeatedly divide the number by /I and add the remainder to the new base /I number, sta n ing from the lea t s ignifican t digit.
EXAMPLE 1.5
Decimal to arbitrary bases us ing the divide-by-n method Conven the num ber 3439 to base 10 and to base 7. We kn ow the num ber 3439 is 3439 in base 10. but let's use the divide-by", (where n i- 10l meth od to illustrate that the method works fo r any base. We tart by di\;ding 3439 b) 10: 3439/ 10=343, remainder 9. We th en divide the quotient by 10: 343110=34. remainder 3. We do the same with the new quoti ent: 34/3=3. remai nder 4. Finally, we divide 3 by 10: 3/10=0. remainder . Combining the remainders. least signifi ant digit firs t. gives us the base 10 number 3439.
16
1.3 Implementing Digital Systems: Programming Microprocessors versus Designing Digital Circuits
IntrOdu ction . " 1 excepl we now divide by 7. We begin by our calculations we get: 49 117==70, < < , dividing 3439 by 7: 3439n=-191. rematn er -' . 3 In=o remainder I. Thus. 3439 in base remai nder I. 70n= 10. remainder O. Ion = I, remalOder . I ' sull' I*r' + 3*73 + 0*72 + 1*71 To conven 3439 to base 7. the approac h IS Simi ~r. .' . d ? Continuing
7 is 130 12. Checking the answer ve ri fies Ihat we have the corree re + 2*70 = 240 1 + 1029 + 7 + 2 = 3439.
.
d from one base to another by first convening Generall y, a number can be convene n number to the desired base using the that number to ba e ten. then convenm£ the base te clivide-bY-/l method. Hexadecimal and octal numbers. . . . b known as " exadecl/lwl /ltlmbers or Just "ex, are 164 163 162 161 160 Base SIxteen num ers. b . d' 't is also 0 ular in digital design. mainly because one. ase sIxteen Igl. A F . PI P r r base twO di oits making hexadeCImal numbers a Illce eq ulva ent to 'ou " ' . I fi d" t t t . for binary numbers. In base SIxteen , t le rst Igl0 shonhan d represent.llon fif nes-the sixteen sy mbols commonl y used are , 10001010 1111 represents up 10 teen 0 _ . binary I. 2..... 9. A, B. C. D. E, F (so A=ten, B=eleven, C=twelve, D-thlneen, hex binary hex ---+-_.:...E=fourteen and F=fifteen). The next digll represents, the number of 0 0000 8 1000 group of 1'6 1 Ihe next di gil the number of groups of 16-, ebc., as shown 0001 9 1001 . F' I 12 S SAF equals S*162 + 10*16 1 + 15* 16, or 2223 10 , 0010 A 1010 111 Igure . . a 16 d~ d" . b t a 1011 Since one digit in base 16 represents 16 values, an our Iglts III ase w 0011 8 4 0100 1100 represents 16 values, each digit in base 16 represents fo ur dIgIts III base C 5 0101 0 1101 two, as show n at the bOllom of Figure 1.1 2. Thus, to convert SAF I6 to 6 0110 E 1110 binary. we convert 816 10 10002, AI 6 to 10102, and FI6 to 111 .12' resulllllg 7 0111 F 11 11 in 8AF I6 = 1000 101 0 1111 2, You can see why hexadeclll1al IS a popular Figure 1.12 Base sixleen number system. shonhand for binary: SAF is a lot easIer on the eye than 100010101111. To convert a binary number to hexadecimal , we Just substItute every fou r bits with the corresponding hexadecimal digit. Thus, to convert 10 II 0 II 0 12 to hex, we group the bi ts into oroups of four staning from the right, yielding I 0 II 0 110 I. We then replace each group" of four bits with a single hex digit. 110 I is D, 0 II 0 IS 6, and I IS I, resulting in the hex number 16D 16. 8
,
A
F
EXAMPLE 1.6 Hexadec imal to/from binary Conven the following hexadecimal numbers 10 binary: FF. 1011 , AOooo. You may find il useful to refer 10 Figure 1.12 10 expand each hexadecimal digillo four bils. FFI 6 is 1111 (forthe left F) and 1111 (for the righl F), or 11111111 2, 10 1116 is 000 1. 0000. 000 1. 000 I. or 000 1000000010001 2, Don'l be confused by lhe facI that 1011 didn'l have any symbols bUI I and 0 (which makes Ihe number look like a bll1ary number). We said il was base 16, so it was. If we said il was base 10. then 1011 would equal one Ihousand and eleven. AOOOO l6 is 1010, 0000,0000, 0000.0000. or 1 0 I OOOOOOOOOOOOOOO~ . Convert the following binary numbers 10 hexadecimal: 0010. 0111111 0, 1111 00. 00102 is 2 16, o I I I I I 102 is 0 I I I and I I 10. meaning 7 and E, or 7E 16. 1111 00, is II and 1100. which is 00 11 and 1100, meaning 3 and C. or 3C 16. NOlice that we start-grouping bits into groups of fou r from Ihe righl. nOI tlte left.
17
. The subtraction or di vide-by- 16 method can al 0 be used to conven decimal to hexadecul1al, however, convening directly from decimal to hexadecimal can be a bit unwieldy for humans SUlce we are not used to working with powers of sixteen. Instead. it is often qUIcker to conven from dec imal to binary u ing the ubtraction or divide-by-2 method and then conventng from btnary to hexadecim al by grou ping set of 4 bi ts.
EXAMPLE 1.7 Decimal to hexadecimal COIll'en 29 base 10 10 base 16. To perform thi s conversion, we can firs t convcn 29 to bi nary and lhen conven the binary result to hexadecimal .
Convening 29 to binary i straighlforward usi ng Ihe divide-by-2 method: 29/2= 14. remainder I. 14/2=7 . remai nder O. 712=3. remainder I. 312= 1, remainder I. 112=0. remainder I. Thus. 29 is 111 01 in base 2. Convert ing 111 012 10 hexadecimal can be done by grouping selS of four bilS. so 11101, is I, and 1101 2. meaning 116 and D16, or ID I6. Of course. we can use Ihe divide-by-16 method 10 conven directly from decimal 10 bexadecimal. Slarti ng wi lh 29. we di vide by 16: 29116=1 , remainder 13 (DI6). 11 16=0. remainder I.
Combi ning the remainders togelher gives us I D 16 - Though lhis particular conversion was simple. convening larger numbers directly from decimal to hexadecimal can be lime-<:on uming. and lhe two-step convers ion may be preferable.
Base eight numbers. known as oClallllllllbers, are sometimes used as a binary honhand too. since one base eight digit equal s three binary digits. 503 8 equals 5*82 + O*SI +3 *So 323 10, We ca n convert 503 8 directly to binary imply by expanding each digit Into three bits, resulting in 503 8 = 101 0000 II , or 1010000 I !,. Likewise. we can conven binary 10 octal by grouping the binary number into groups o(three bits starring from the right, and then replacing e.ch group with the corresponding octal digit. Thus. 1011101 2 yields I 011 101 , or 135 8, Appendix A di scu ses number represemations further.
=
1.3 IMPLEMENTING DIGITAL SYSTEMS: PROGRAMMING MICROPROCESSORS VERSUS DESIGNING DIGITAL CIRCUITS Designers can implement a digital system for an application using one of tWO common digital system implementation methods-programming a microprocessor or creating a custom digital circuit (known as digi tal design) . As a concrete example, consider a simple application that !Urn on a lamp whenever there is moti on in a dark roo m. Assume a motion detector has an output wire alled a that outputs a 1 bit when motion is detected , and a 0 bit otherwise. Assume a light sensor bas an output wire b that outputs a 1 bit when light i sensed. and a 0 bit othen\ise. And a sume a wire F turns on the lamp when F is 1, and rum off the lamp when O. dra\\ing of the system is shown in Figure 1. 13(a). The design problem i to detennine what goes in the block named Dm'Clor. The Detector block takes wires a and b as inputs. and generates a \'lliue on F. -uch that the light turns on when motion is detected when dark. The Detector :lpplicati n is readil) implemented a a digital system. as the application ' inpull and utpUtf obviousl) are
18
Introduction
1,3 Implementing Digital Systems: Programming Micro processors vers us DeSigning Digital Circuits
. "
' . h A desioner can implement the Detector (li gna !. haVing only two pOSS Ible values eac. 3(b"')) 'no 'J custom di oital cirCUIt block by programming a microprocessor (FIgure I, I or USI ", ' '" (Figure 1.13(c)).
~II
Detector
Digital System
>~
Detecto r
a
Detector
Micro-
----~
(b)
(c)
(b) implementation
Software on Microprocessors: The Digital Workhorse
Desioners that need to work with digital phenomena often buy an off-the-shelf microprocess;r and write software fo r that microprocessor, rather than design a custom dtgttal circui t. Microprocessors are really the "workhorse" of digital systems, handltng most dig it al process ing lasks.
is (l programmllble
proct'ssor implemellted 011 (J sillsle compllter chip-rile "micro"
PO
;;: P1 o· P2
i3 P3 i3
'0
Q
P4 P5 P6 P7
(b )
(a)
Figure 1.14 Basic microproce sor's in put and output pins.
J US! meallS sl1Ial/
here. The
microproce.uor lerm became
popular il/ Ihe 19805 whell
processors shrank
dOlvlIfrom mulliple cflips to
jusl OIlC. Th e first single-chip microprocessor was the Imel 4004 chip ill 1971.
a and ! b ,
F
Figure 1,13 MOlion-in-lhe-dark-deleclor syslem: (a) sySlem block di agram, using a microprocesso r. (c) implementation using a custom digit al c irc uI t.
"~
Ivhile (1) { PO ~ 10 && ! 11 : 1/ F
PO
~ -- - -- --- ---
A "processor" processes. or tralls/orms, dow. A "m icroprocessor"
shown in Figure LI S. The des igner connects the a wire to the microprocessor input pin 10, the b W, re to Input pin 11 , and output pin PO to the F wire, The designer could then speCIfy the II1structions for the microprocessor by wri ting the fo llowing C code: void rnain() {
(a)
10 11 12 13 14 15 t6 t7
19
A microprocessor is a programmable digital device that executes a user-specified sequence of instructions, known as a prog ram or as software, Some of those instructions read the microprocessor's inputs, others write to the microprocessor's outputs, and other instructions perfo rm computati ons on the input data, Let's assume we have a bas ic microprocessor wi th eight input pins named 10, 11, ..., !7, and eight output pins named PO, PI, .. ., P7. as shown in Figure 1.l4(a), A photograph of a real microprocessor package with such pi ns is show n in Figure L 14(b) (the ninth pin on thi s side is for power, on the other side for ground). A microprocessor-based solution to Ihe motion-in -the-dark detector application is ill ustrated in Figure 1.1 3(b), and a photograph of an actual physical implementation
C is one of several popular lanmotion sensor guages for describing the desired F instructions to execute on the microproce sor. The above C code works as fo llows. The mi croprocessor. after lamp being powered lip and reset, executes the instructions within rna in's cllrl y brackets ( ). The fi rst instruction is "wh i 1e (1) " which simply means to repeat the insrructions in the while's curly brackets forever. Inside the while's curly brackets is only one instruction "PO = 10 && ! 11," Figure 1,15 Physical motion-in-the-dark which assigns the microprocessor's detector implementation using a microprocessor. output pin PO with a 1 if the input pin lO is 1 alld (written as &&) the input pin I 1 is not 1 (meani ng 11 is 0). Thus, the output pin PO, which tums a O --~ the lamp on or off, forever gets 1 assigned the appropriate value based b on the input pin values, which come 0-------' fro m the motion and light sensors. 1 F Fi gure 1. 16 show an example O--~ of signals a, b, and F over time, I I I I 6:00 7:057:06 9:00 9:01 time with time proceeding to the right. As tim e proceeds, each signal Figure 1.16 Timing diagram of motion-in-the-
•
I
20
1.3 Implementing Digital Syste
Introduction wi th lime proceeding
Ihe riohl. and Ihe va lues or digital signals show n by high or ·IS known as a IWll . .llg <> d ' (a and' b) 10 bef Iow I' Ines. lagram . We draw Ihe inpul lines . whalever va lues we walll . bU I Ihen the oUlpul line (F) musl desc ribe Ihe behavIOr 0 Ihe digilal sys lem . EXAMPLE 1.8
10
Outdoor motion notifier lIsing a microprocessor LeI's use th e basic microprocessor of Figure 1.1 4 to implement a 10
PO 11 P1 ~ 12 n P2
13 14
buzzer
sy~ l cm thai sounds a bu zzer when moti on is detec ted at any of Lhree mOlion sensors outside a house. We connect the motion sensors ~o
microprocessor inpul pins 10. 11. and 12. and conneCI OUlpUI pill PO 10 a buzzer (Figure 1.17). (We assume Ihe mOli on sensors and
.g P3 g P4
buzzers have appropri ate elcclro nic interface to th e micro processor pins.) We can then wri lc the foll owing C program :
'"
15 ~ P5 Q 16
P6
17
void main()
P7
( ~Ihile
molion sensor
PO
(1) =
10
(
II
II
II
IlIlel named 'heir t!VO/l,illg 1980S/
12:
90s desktop processors using /llimbers: 80286, 80386. 80486. As pes bc(:ame popular. Intel switched 10 c(lu:hier ,wmes: the 80586 lVas called 0 PemiuIII
Figure 1.17 Motion sensors connected to
mi cro processor.
The progrnm executes the statement inside the while loop repeated ly, That Sla tcmcnt will set
PO 10 I if lO is I sels PO 10 O. EXAMPLE 1.9
01'
(wrillen as
II
in Ihe C language) I I is I or 12 is 1. olherwise Ihe slalemenl
Counting the number of active motion sensors
("pellfa" mealls
5),JollolI'ed by the
In this example. wc'lI usc the basic microprocessor of Figure I 14 to implement a sim ple di gital system th at outputs in binary the number of Illation sensors that presently detect motion , We' ll assume two motion sensors, meaning we'll need to ou tput a two-bit binary number, whi ch can represent the possible counlS 0 (00). I (0 I). and 2 (10). We' ll connecl Ihe mOlion sensors to microprocessor
Pentium Pro. Ihe Penlium II, alld
others, £1'e"llIall)~ the "ames tiomill(IIeti over the nllmbers,
inpul pins 10 and I I and OUlpullhe bi nary number onto outpul pi ns PI and PO. We can Ihen wrile the follOwing C progrzHll:
void main()
.p '. ms. rogrammlllg Microprocessors versus DeSigning Digital Circuits
Designers like 10 use microproce _ sors In their digi tal systems because microprocessors are readily avai lable, Inexpensive. easy 10 program. and ea y to reprogram. II may surpri se you 10 learn Ihat you ca n buy cenai n microprocessor chips for under $ 1. Such microprocessors are found in places lIke lelephone answering machines. mi crowave ovens. cars, IOYs. certain medical devices, and even in shoes with blinking lighl s. Examp les include Ihe 805 1 (ori ginally designed by Inlel). the 68 HC II (made by Motorola). and Ihe PIC (made by Mi croChip). Other microprocessors may cos I lens of do l-
21
(a)
(b)
Figure 1.18 Microproeessorchip packages: (a) PIC and 805 1 microprocessors. costing aboUI S I each. (b) a Pen tiu m proces or with pan of ilS package cover removed. showing the si licon chip inside,
lars: found in pl aces like cell phones, ponable digital assistams. office automation equlpmenl, and med ica l equipmenl. Such processors include the ARM (made by the ARM corporal Ion), Ihe MIPS (made by the MIPS corporation). and others. Other microprocessors, like Ihe well -known Pentium processors from Intel. may cost several hundred dollars and may be found in desklop computers. Some microprocessors may cost s~veral thousa nd dollars and are fou nd in a main frame compuler running perhaps an alrlme reservallon system. There are literal ly hundreds, possibly even thousands, of differem microprocessor Iypes avai lable, di ffe ring in performance. cost. power. and olher melrics. And many of Ihe small low-power processors cost under $1. Some readers of Ihi book may be fami li ar with software programming. others may no\. Knowledge of programmi ng is not essemial 10 learning Ihe material in this book. We wi ll on occasion compare custom digilal circuits with their corre ponding software implememali ons-the ullim ale conclusions of Ihose comparisons can be understood withoul knowledge of programming it elf.
Digital Design- When Microprocessors Aren't Good Enoug h
(
while (J) if ( ! 10 && ! I I) ( P1 = 0; PO = 0 : II output 00 . meaning zero
With microprocessors readi ly avai lable, why would anyone ever need to design new digital circuits, olher Ihan those relatively rew people de igning microprocessors themselve ? The reason is that sofI ware nlnning on a microproce sor often isn 'l good enough for a particular applicalion. In many cases. software may be too slow. Microproce sors only execUle one instruclion (or aI most a rew instructions) at a time. But a custom digital circuit can execute dozens, or hundreds. or even thousands of compUlations in parallel. Many applicalions, like picture or video compression. fingerprim recognition. voice command detection. or graphics display. require huge numbers of computation to be done in a hon period of time in order to be praclical-afler all , who wants a voice-controlled phone thaI requires minutes 10 decode your voice command. or a digilal camera that require 1- minutes t take each picture? In other ca e , microprocessors are too big. or nsume mu h power. or would be too costly, making ustom digital cireuils preferable.
else if( ( 10 && ! ] 1 ) II ( !] O && ] 1 ) ) ( PI = 0 ; PO = 1 : II output 01. meaning one else if (]O && ]ll ( P1 = 1 : PO = 0 : 1/ output 10 . meaning two
n
22
1 Introduction
1.4 About this Book
For the mOlion-in-the-dark-detector application. an ahernati ve to the I.llicroprocesso rbased dc.!\ign lISC!) a custom digital circui t inside the. De~ec1O" ~I ock. A c~~cll.1I IS an lIl~erc~n·t· r I . W Sl desion ·lcII'CUllthat.loreach dlffelent combInauon ne~ 1011 0 C eClnc components. C I11U e' lIch circuit is shown in Fi ure or Input, a and b. gcnerate, the proper val ue on F. One S .g ' 1 1 d 'b I ts ' I n Lilat circuit later. But you've now ' V I . 13( C.) \' C c~cn c Ile componen . , . seen one SImple example of designing a digita l circuit to solve a design problem. The mIcroprocessor also has a circuit inside. but becallse that ci rcuit is designed to execute programs rather Lhan Just cietect 1110tion at ni ght. the microprocessor's ci rcuitml1Y conwin about ten thousa nd components. compared to j ust two components in Ollr custom digital Cl rClI lt. Thus" our custom di gi tal circuit may bl! smaller. cheaper. fas ter. and consume less power than an llTIplemental ion on a microproccs~or.
. ..
.
Many applica ti on use bot h microprocessors and custom dI gItal deS Igns w attam a ~ys t cm th aL ~Ichil!vc~ j u!'.t the right balance of performance. cost, power, Size, deS ign time,
flexibil ity. etc.
EXAMPLE 1.10
DeCIding among a microprocessor and custom digital circuit \VC I11U"" dc~ign a digita l ~y~ t cll1lo conlrol a figiller jet's aircra ft wing. In order to properl y control the aircrafl. the diuital ,ystCIll must execute. 100 li mes per second . .a computation lask th at adjust the wing'S pos it io; ba~\.!d on the aircraft'lj prescnI and desired speeds. pi tch. yaw, and other night fac tors. SllPPO~C we e~til11atc thai software on n microprocessor would req uire 50 ms (milliseconds) for each execlition of the computa ti on uhk. whereas a custom digital circuit would requ ire 5 ms per execution. Execliting the computation task 100 times on the microprocessor wou ld req uire 100 * 50 ms = 5000 ill S. or 5 ... econcis. But we require those 100 executions to be done in I second. so th e microprocc~sor i:.. not fast enough. ExecUl ing the task 100 times with the custom digi tal circuit would
require 100 • 5 111'
= 500 111,. or 0.5 seconds. As 0.5 seconds is less than
I second. the custom
digi tal circuit can !'tali:..!'y the system's performance constraint. We thus choose to implemen t the digita l sys tcm as J c u~tom digital circuit.
EXAMPLE 1.11
Partition ing tasks in a digital camera A digita l Cilmera cap turcs pictures digi tally usi ng several steps. \Vhen the shuller button is pressed, a grid of a few million light-sensitive electron ic clements capture th e image. each elemenL storing a binary number (perhaps 16 bit~) representing the intensity of light hilling the element. The camera Ihen performs several tasks: the cnmera reads th e bits of each of these clements. compresses the tens of millions orbits into perhaps il few mill ion bits. andslOl-es lhe compre ssed bilSas a file in the camcrn's nash memory. among other ta sks. Table 1.3 provides sample task exec ution tim es on an inexpcnsive low-power microprocessor versus a custom digital circui!.
TABLE 1.3 Sample digital camera task execution times lin seconds) on a microprocessor versus a digital circuit, Task
Microprocessor
Read
5
0. 1
Compress
8
0.5
Store
Custom digital circuit
0.8
. We need '0 decide which tasks to Irn~l emcnt on the microprocessor and which to ~mpl e mcnl as a CUstom digital ci rcuit. s U~Jecl to the constraint Ihal we shou ld strive 10 minimize the amount of Custom digital circuitry in order 10 reduce chi C.OSl~. Such decisions are known as parll.. t tO lllIIg. Three panitioning opt ions are hown in Figu re 1.19. I f we implement all three tasks On th e microprocessor th e camera wi ll require 5 + 8 + I = 14 se~ol1d s to take a picture-too much lime for the camera 10 be popular wilh consumers. \Ve cou ld implemelll all the tasks as Custom
digi.al ci rcuits. resulting in 0. 1 + 0.5 + O. = 1.4 seconds. We could ins.ead implement lhe read and compress tasks wilh CUStom digital ci rcuit s. while leaving the store uisk to th e microprocessor, resulting in 0. 1 + 0.5
+ I. or 1.6 seconds. We might decide on this lasl implementation Option. to save COS t without much noti ceable time overhead.
23
Microprocessor (a)
(Read. Compress. andSlore)
(b)
(c )
Figure 1.19 Digi tal camera implemenred with: (aJ a microprocessor. (b) CUStom ci rcuits. and (c) il combination of Custom circuits and a microproces or.
1.4 ABOUT THIS BOOK Section 1.1 di scussed how digital systems now appear everywhere arou nd us and iooificant ly il~pact the way we li ve. Section 1.2 highlighted how learning digital d~ign accompli shes two goals: showing us how microprocessors work "under the hood." and enabling us to implement ystems usi ng custom digi tal circuit rather than or alon2 ide microprocessors to achieve beller implementati ons. This latter goal i becomin2 inc~as ingly significant since so many analog phenomena. like music and video. are becomin2 digital. That section also introduced a key method of digitizi ng analog igoal. namely binary numbers. and described how to convert among decimal and binary numbers. Section 1.3 described how designers tend to prefer to implement digital ystcms by writing software th at executes on a microprocessor. yet designers often use u tom digital circuits to meet an applicati on's performance req uirements or other requirement . [n the remainder of this book you will learn about the exciting and challenging field of digi tal design. wherein we convert desired system funcLionality into a custom digital circuit. Chapter 2 will introduce the most basic foml of digital circuit. combinational circu its. whose ou tputs are simply a functi on of the present values on the circuit"s inputs. That chapter will show how to u e a foml of math ca lled Boolean algebra to de - ribe our desired circuit functionality. and will provide clear sleps for conve-rting Boolean equations to circui ts. Chapter 3 will introduce a more advanced type of ircuit. equential circuits, whose outputs are a function not only of the present input value. but aI 0 of previou input val ues-i n other words. sequential circuits have memory. uch circuits are commonly referred to as controllers. ThaL chapter will show us how t u' another
26
1.5 Ex ercises
Introduction . ' . . etll od: 1. 12 Convert lhe foll owing decimal IHllllbcr::. to binary Ilumbers uSing the dl vlde-by-2 nl
(") 9
J.2J Convert the following hexadecimal numbers to binary: (a) BOC4
(b) I EF03 (e) F002 (d) BEEF
(b) 15 (e) 32 (d) 140 1. 1J C{lIlvcrt thl! foll owing dec imal numbers 10 binary numbers
. u Sing
Ihe cli vide-by-2 1l1
e
lhOd:
1.22 Convcn Ihe following hex adeci mal num bers 10 decimal: (a) FF
(") 19
(b) FOA2
(b) 30 (c) 64
(e) OFIOO (d) 100
(d) 128 . ' . . e l h Od : 1. 1-' Convert the fo llowing deci mal numbers to binary numbers lI smg the c11 vlde-by-2 111
(") 3 (b) 65 (e) 90
(d) 100 . ' . . ? m e l ]1od: 1.15 COllvert th e following decimal numbers 10 blllary numbers usmg the dlv ldc-by--
,
(") 23 (Il) 87 (e) 123 (d ) 101
l.16 Conve rt the followi ng binary numbers to hexadecimal: (") 11110000 (b) 111 11111 (e) 010110 10
(d) 1001101 101101
1.17 COnVl:ft th e foll owing bi nary numbers 10 hexadecimal:
(d) 1101101111100
1.18 COllvert the f
1.26 Delenni ne the decimal num ber ra nges thal can be represented in bina,). octal. decimal. and number range 0 Ihrough 3 in binary (00 through II ). 0 through 63 in octal (00 through 77), 0 Ihroug h 99 in decimal (00 th rough 99), and 0 through 255 in he,xadecimal (00 through FF). (a) I
(b) 11 00 1000 (C) 10100 100
11'11
1.19 Convert the following hexadecimal numbers to binary: (a) FF
(b) FOA2 (c) OF IOO (d) 100
1.20 Convert the following hexadecirnallllllllber!> to binary:
(d) DEED
(e) 999,999 hexadecimal using the following numbers of digits. For example. 2 digits can represent decimal
(a) 111 00 111
(b) 3FAD
1.25 Compare the number of digits necessary 10 represent the followi ng decimaJ numbers in bioary. octal, decil11111. and hex adecimal representauons. You need nOI determine the actual representations-j ust the number of required dig it s. For example , representing the decimal number 12 requires four di gits in binary ( 1100 is th e aClUal representalion), two digital in oct:JJ ( 14) . twO digils in decimal ( 12). and o ne d igi l in hexadeci mal (C). (a) 8
(d) 1000
(c) 11 110001
(e) 3E2 A
1.201 Conve rt (h e dec imal number 128 to the foll owing number sys tems: (a) binary (b) hex adeci mal (c) base Ihrce (d) base fi ve (c) base fineen
(c) 300
(Il) 10100101
(a) 4F5E
1.23 Convert the rollowing hexadecima l numbers to decimal : (a) 10 (b) 4E3 (c) FFO (d) 200
(b) 60
(a) 11001101
(d) (JIll
].7
(b) 3
(e) 6 (d) 8
SECTI ON 1.3: IMPLEMENTING DIG ITAL SYSTEMS: PROGRAi\(,\IlNG M IC RO PROCESSORS VE RSUS DES IGNING DIG ITAL C IRCUITS 1.27 Use a microprocessor like thai in Figure 1.14 to implement a system that sounds :In aJ3.lTll whenever there is motion detec ted al the same lime in three different roon ~. Each n.'){)m~s mot ion sensor output comes to us on tl wire as a bit 1 meaning motion. 0 meaning no mou(\o. \Ve sound the alann by selling an Output wire "alann" to 1. hm\ the l'Onnt."Ctions tl'l..Uld tn.")nl the microprocessor. and the C code to execute on the micropf"()C"e ·or.
28
Introduction 1.5 Exerc ises . I ent a system th at counts the number of . I hat III . FI gure I, 14 10 nnp em 1.28 Use a mi croprocessor like has a senso r th at o ut put s a 1 .I f a car is cars in a parking 101 wit h seven spaces. Each space h Id be written in binary over three . e The output 5 all prC~l: nl . and thaI outputs a O Qt herWls . d the C code. Hint : use a loop an d an wires. Show the connecti ons with the microprocessor an a 1 if-else state ment or a switch b f cars present. then usc < I i nteger va riable to caunl the nutll er 0
fO nate 3-bit output.
state ment to convert the integer 10 the app P . thn! displays the number . ... I 1410 Implemenl a syslem . d 1.29 Use a microprocessor Itke thai In Figure . . II LEOs 'Irranged III a rowan display There are elg 1 , 1 th LED of people in a wai ting roo m o nlO an • ' . . th at wi ll output a when e I . ped with a sensor < • eight chairs in the wa iting room, eac 1 equip d I number of sealS being occupied, · LED 1"1 viII corres pon 10 11e fi I SCa l is in lise. The number 0 S I \ f l ' h two seats those are), th e r5t two . h · d (regardless 0 1I' 1iC " ed the first three LEDs in th e row will hg t up. For insHlllcc. if two se:lts are OCC Up lC LEDs will lig ht l~ P: if lh~ee seats are OCCUpl i~d the lights will light up incrementall y. Show Regard less of whic h particular seals arc occup c ~ ro ri ate C code. th e connec ti ons with the microprocessor and th l PP P . d I ' d c pIing I orts encrypted Video. an t lal e ry 1.]0 Suppose a pan icul ar TV SCI-lOp box al a hole supp C Th ec uli on limes of each lask on each video frame consists of three sub· tasks A . B. and . e ex I 1S ~o r A 10 I11 S versus 2 . I ' . are 100 ms ve rsus n • a microprocessor versus a custom dl·glla CirCUl i th e microprocessor and f C Panilion Ihe tasks among ms fo r B, and 15 ms ve rsus I ms or . . f Stom di gital circuitry, while custom d igital circ uit ry, sllch that you minimize the amount 0 cu meetin o the constra int of decrypting at least 30 fram es per seco nd. e .. a er tic kets for oaining entrance to base1.31 The owner of a ba ebnll stadium wan Is to ei1mll1a~e p p w tho~e auending the game to ba ll na mes. She would like 10 sell lickels eleclrollicall y and allo . . II . Ihe fin gerprinl e . . TI has two opllons for Instu II1g enter by sc~u1lling theIr finge rpnnt. le owner . h fi erprint recoonition .. yst"m thm Implements L e 1I1g 0 T fi recog nition system, ~e rst opt~on IS a s t: The'second option is a custom di gital circuit using soft ware exec uting on a m,lcroproces.s?r, Th ftware system req uires 5.5 seconds to d' . I ' '1 desig ned specificall y for fi ngerpnm recognition. e so · and costs 550 pe. r unit . whereas th e Iglta ClrCUI recoe· nize an indiv idual'S finge rprmt ' th I requie res 1.3 seconds for recognition and costs S I00 pe' r Ull!'t. The owner wants to ensure d Ih as u . be able 10 enter thestad·IU111 befo re Ihe ga me' starts, Can everyone attend ing the game will needs 10 be ab le 10 suppon 100,000 people enlerin g Ihe sladium wilhin 15 mmules. ompare the two altern ati ve systems in terms of how many people per minute each sys Le~l1 can s~ppon, how ma ny un its of each system would be neede d to support 100000 ' . people 111 15 mmules, and what Ihe overall cost of installation would be for the two competing systems. 1.32 How ma ny possible partiti onings are there 0 f a set 0f lasks where each (ask can be implemen ted on il microprocessor or ilS a custom di gi tal circuit? 1.33 *Wrilc a program th at automati call y partitions a set of 10 tasks among 0 l"e a pnrlllioning approach Ihal makes Some ed ucmed gues,"s. Your program lif..c ly won." I. "': able 10 g uaran lee lhal il find, Ihe "':Sl panilioni ng, bUI il , houl d (I I le"'1 li nd a good parlillorlillg.
29
~ DESIGNER PROFILE
---.:::;:;;:::;::;::::"!!
Kelly firsl became interested in engineering while allending a lalk about engineering at a career rair in hi gh chool. " I was dazzled by Ihe interestin g ideas and the cool graphs." While in college. Ihough. she learned Ihat "Ihere was much more to engineering - ......._ .........__
Ihan ideas and graphs. Engineers apply Iheir ideas and ski lls 10 build Ihings lhat reall y make a difference in people 's li ves, for generat ions to comc." In her first few years as an enginee r. Kell y has worked on a varicty of project "(hat may help numerous individuals," One project was a ventilator system li ke the one mentioned earlier in this chapter. "We designed a new conlrol system that may enable people on ve ntilators to breathe with mOre comfort while still getting the proper amount of oxygen," In addition, she examined alternative implementations of Ihat control system. incl Uding on a microprocessor, as a Custom di gital circuit, and as a combination of Ihe Iwo. 'Today"s lechnologies. like FPGAs, provide so many differenl oplions. We examined several options to see what the tradco ffs were among Ihem. Underslanding the Iradeoffs among Ihe oplions is quite important if we wanl to build the best system possible:' She also worked on a projecl Ihal developed ·'small self-explanalory eleclronic blocks Ihal people could connect together to build useful electron ic systems
involving almoSI any kind of sen or. like motion or lighl sensors. Those blocks could "': used by Jcids 10 learn basic concepls of logic and compUlers, concepts which are quite important 10 leam these days. Our hope is that these blocks will "': used as leaching lools in schools. The blocks can also "': used 10 help adu lts sel up useful systems in their homes, perhap to mOrU lOr an aging parenl, or a child al home sick. The polential for these blocks is greal-il will "': interesting 10 see whal impacl Ihey have:· "My favorite thing about engineering i the variety of skills and creativily invo lved. We are faced with problems Ihat need 10 "': solved. and we solve them by applying known techn iq ues in crealive ways. Engineers must continually learn new [echnologies. hear new ideas. and lrac k current prod ucls, in order 10 be good designers. It's all very exciting and challenging. Each day a( work is diffe rent. Each day is exciting and is a learning ex penence. '·Studying 10"': an engineer can "': a great deal of work bUI it"s wonh il. The key is 10 lay focused, 10 keep your mind open. and to make good use of available resources. Staying focused means to keep your priorities in orderfor exa mple. as a Student. studying Come firsL recreation second. Keeping you r mi nd open mean [0 alway be willing [0 listen to different ideas and [Q learn about ne\llo' technologies. Maki ng good use of resources means to ao g:ressively seek informatio n. from the lnterneL from from books. and 0 on. You ne\ er knO\\ where you ~ goi ng 10 get )our ne'U importrult bi, of info rmation. and you \\ On'l get that infonnarioo un} you seek il:·
c~iieagues.
2.2 Switches
31
Electronics 101
2
You '. re probably fam iliar with the idea of e lectrons, or let's just say charged panicles. fl ow ll1g through wires and causing lights to illu minate or stereos to blast mu ic. An anaJogous situation is Wate r flowin g through pipes and causing sprinklers 10 pop up Or turbi nes to turn . We now describe th ree bas ic e lectrical terms: Although
Combinational Logic Design 2.1 INTRODUCTION of the A dio ita l c ircuit. whose out puts d epend sole ly on the present . .combinatioll .. b circlIit . b t . ". I 's called a combillatiollal circllit. Combll1ali onal CirCUIts are a aS lc u II/PillS va lies / , b . ponantly . I . f di oital c irc uits ab le to imple ment some syste ms. ut more 1m Important c ass 0 ,," f' . T I 's chapter introduce the scrvin o as the basis for more complex classes 0 ClrCLlIlS. 11 . ( des ion"of bas ic combinational c ircuits. Late r chapters will deal with mo re ad ~anced combi na7ion'1 1 c ircu its and with sequent ial circu its. whose outputs depend on t e seqhuedn?re " . UIt. ,s.Inpu ts .Fio (hi story) of va lues . that have appea red at t he CirC " ure 2 . I Illustrates te l -
Voltage is the difference in e lectri c potential between two points. Voltage is measured in volts (V). Conventi on says that the emh. or ground. is 0 V. [nformally, voltage tells us how "eager" the charged panicles on one side of a wire are to get to grou nd (or a ny lower voltage) on the wire's other side. Voltage is analogous to rhe press ure of wa ter trying to flow th rough a pipe-water under higher pressure is more eager to fl ow. even if the wa ter can't actually flow perhap becau e of a closed faucet.
wu/erstalldillg 'he electronics underlyil/g tligiftll
logic gtlles is Optiollal,II/("' )I peoplejilld II basic IIlu/ersflIlldillg satisjies IIIlIch clIriOSilY alld al,..o helps ill I/Iulersullldil/g SOllie of the 1/01/· ideal digital gate behavior later 01/.
Current is a measure of the fl ow of the charged panicles. Informally, current teli us the rate that panicles are ac tua ll y flowing. Currem i analogou to water flowing th ro ugh a p ipe. Cu rrent is measured in amperes (A). or amps for hon. Resistance is the tendency of a wire (o r anything. really) to re i t the flow of curre nt. Res istance is a nalogous to a pipe's diameter-a narrO\ pipe re isIS water fl ow. while a wide pipe lets wate r flow more freely. Electrical resistance i measured in o hms (Q ).
Ference between combinati ona l and seque ntIal Clrcu tts. f"
a b
'"l>
If we know the present input bi t values, then we can determine the output value. If ab=OO. then F is a
tl ab=O l , then F is 0 If ab= l 0, then F is 1 If ab=ll, then F is 0
F
F
We cannot determine the output value
just lrom tooking at the present input values. We must atso know the history 01 input va tues. e.g., il ab was 00 and then 10, F is 0 but il ab was 11 and then 10. F IS 1
Figure 2.1 Combinati onal versus sequential digital circui ts.
The chapter will introduce the basic bu ilding blocks o f combinati o na l c irc uits, know n as logic gates. and will also introd uce a form of ma thema tiCs, known as Boolean a lgeb ra, that is usefu l for designing com binationa l c ircuits.
2.2 SWITCHES Electronic sw itc hes form the basis of all di gital c ircuits, so they make a good sta ning point for the disc ussion of di gi ta l circuits. You usc a type o f switch, a li ght ,witch, whel.lever you turn li ghts on or ofr. To understand a switch, it help, to understand some ba IC e lec tron ics.
30
2 ohms 9V
Cons ider a battery. The panicles at the positive terminal Want to flo" to the negat ive te rmina l. How "eager" are they to flow ? That depends on the \oltage diffe rence be tween the terminals-a 9 V battery'S panicles are more eager to flow than a 1.5 V battery's panicles. because the 9 V battery'S panicles ba\e more potential energy. Now suppose yo u connect the positive tenninai through a light bul b back to the negati ve terminal as shown in Figure 2.~ . The 9 \ ' batteI) will result in more current fl owing. and thus a brighter lit light. than the 1.- V baneI). Prec isely how muc h current will flow is detemlined using the equation:
V = IR (k nown a Ohm's Law) 4.5A
Figure 2.2 9V battery connected to light bulb.
where V is voltage, I is current. a nd R is resistance (in this case. of the light bulb). So if the res istance were 2 ohms. a 9 V battery would re ult in ~.) A lsint'e 9 = 1*2) of c urrent. while a I.) V battery would re ult in 0.75 A. Rewriting the equation as I = VIR might make more inruitive ense--the higher the voltage. the more current: the higher the resistance_ the k -- current. Ohm's Law is perhap the most fundamental equation in electroni s.
The Amazing Shrinking Switch Now back to swi tc hes. Figure 2.3(b) show_ that a s"'it h has three pans-let's call them the source input. the o utput , a nd the ontrol input. The source input has hlgher \OIt3~ than the ou tput. so c un'ent wanlS to flo\\ from the source input through the ,,,it -h It> the OUlpUt. The who le )JlIIlJose of a switch is to block t1U1 current" h 'n th' 'onrrol '{~ th switc h "ofr." and to allow that cmrent to Ilo\\ \\ hen control, 'ts th <\\I(.:h "(,n." F...'r exa mple. when yo u flip a light switch up to tum th' ,,, it-'h on. the ," Itch 'au ,~, t
32
Combinational Logic Design 2.2 Switches
wire so curren t flows. When you flip the Source input wi re to physically touch the output . ' II ates the source input from . . If h 'tch physlca y separ switch down to turn the SWItch a . t e SWI . I'k r cet valve that determi nes the o utput. In our wa te r analogy. the control input IS I 'e a au , whether water fl ows through a pipe. conlrol input
•
source
I \
input
discrete transistor
quarter
(a)
(to see the relative size)
output
con trol input
Ie
vacuum tube
relay
/
"off"
~ MDfBUGGING" In 1945, a moth got stuck in one of the relays of the Mark 11 computer at Harvard. To get the compu ter working properl y again. technicians found and removed the bug. Though the tern, "bug" had been used for decades before by engineers to indicmc a defect in mechanical Or electrical eq uipment. the removal of that moth in 1945 is considered to be the origin of the term "debugging" in computer programming. Technl~.ans taped that moth to their written log (shown in the picture to the s.de), and that moth is now on display at the National Museum of American History in Washington , D.C.
"on"
The machine said to be the world 's first general.purpose computer. the ENIAC (Elec~ trOI1J~ Nu mencal Integrator And Computer), was completed in the U.S. in 1946. ENIAOO
output
contatned about 18.000 vac uu m tubes and 1500 relays. weighed over 30 ton . was I fee l long and 8 feet high (so it would likely not fit in any room of your house. unles you have a n absurdly big house). and consumed 174,000 wans of power. Imagine the heat generated by a room full of 1740 IOO·wan light bulbs. That' hot. For all thaI. E'llAC could compute aboul 5000 operations per second-compare that to the billions of operations per second of today's personal computers, and even the tens of millions of computations per second by a handheld cell phone.
I source
33
input (b)
Figure 2.3 (a) The evolution of switches: relays (1930s), vac uum tubes ( I940s). discre.te transistors ( 1950s). and integrated ci rcuits (Ies) contain ing transistors ( 1960s-present). lC's on gmally held about len lransislors: now they can hold more than a billion. (b) Simple view of n SW Jlch.
Although vacuu m tu bes were faster than relays. they consumed a lot of power. geoerated a lot of heat, and failed frequeJ1lly.
Switc hes are what cause digital ci rcuits to uti lize binary numbers made from ~its the on or off nature of a switch corresponds to the Is and Os in binary. We now dtscuss the evolution of swi tches over the 1900s, leading up to the CMOS tran sistor switches commonly used today in digital circuits.
Vacuum tubes were commonplace in many electronic appliances in the 19605 and 1970s. I remember taking trips to the store with my dad in the early 19705 to buy replacement tubes for our television set. Vacuum rubes sti ll live today in a few electronic de\;c<7' One place you might still find tubes is in electric guitar amplifiers. where the rube unique-sounding a udio amplification is still demanded by rock guitar enthusiasts who want their version of classic rock songs to ound just like the originals.
1930s -Relays Enaineers in the 1930s tried to devise ways 10 compute using electronically controlled sw~ches-s\Vitches whose control input was another voltage. One such swi tch , an electro· magnetic relay like tha t in Figure 2.3(a), was already being used by telephone industry for switching telephone calls. A relay has a control input that is a type of magnet, whtch becomes magnetized when the control has a positive voltage. In o ne type of relay, that magnet pulls a piece of metal down, resulting in a connection from the sou rce input to the output-akin to pulling down a drawbridge to connect one road to another. When the control input re turn to 0 V, the piece of metal returns up again (perhap pushed by a small spring), disconnecting the source input fro m the output. In telephone systems, relays enabled calls to be routed from one phone to another, without the need for those nice human operators that previously would manually connect one phone's line to another.
Jo ck Kilby 01
1940s-Vacuum Thbes
Texas IlIsfmmellls mill Roben No}'ce
Relays relied on metal pans moving up and down, and thus were rather slow. In the 1940s and I 950s. vacuum tubes, shown in Figure 2.3(a) and ori ginally used to amplify weak e lec tri c signals like those in a telegraph , began to replace relay. in computers. Vacu um tubes had no moving pans, so the tubes were much faster than relays .
1950s-Discrete Transistors T he invention of the transistor in 1947. credited to William Shockley. John Bardeen. and Walte r Brattain of Bell Laboratories (the research am, of AT&n. resulted io mailer and lower-power computers . A solid·state (discrete) transistor. hown in Figure 1.:(a). uses a small piece of silicon. "doped" with some extra materials. to create a wit h. inee these switches used "solid" materials rather than a vacuum or even moving pans io a rein}. the} were common ly referred to as solid·state transistors. Solid· tate transi tors were maller. c heaper. fas ter. and more reliable than rubes. and became the dominant mputer swit h in the 1950s and I 960s.
01 Fojr"hild
.
SemicOIu/lictors
lire often credited
1I';,h ellch/IO"'·lIg illriept'lIdt'lIIly im't'lIled rhe I e.
1960s-lntegrated Circuits The invention of the illtegrated circuit (IC) in 195 reall) Ie\ luti nized computing. An Ie. n.k .a. a chip. packs numerou tiny tran$i'tor.; on a fingernail·sized pi f :ili o. So instead of 10 transistors requiring 10 discrete ele troni mponc.>nt> n} our lx>ani. 10 transistor.; can be implemented on one component. the ·hip. Figure _.:\3) .. \\ . a picture of an IC thut ha$ a few million transistors. Though earl} I ,fe3tured < nl_ t us f
I
34
Combinational Logic Design
2.3 The CMOS Transistor
lransistors. improvemen ls in IC technology have resulied in nearly ONE BfLLlON tran· sistors on a chip loday. IC lechnology has shrunk transislors down 10 a tota lly dIfferent scale. A vacu um lUbe (aboul 100 mm long) is 10 a modem IC transislor (aboul 100 nm) as a skysc raper (aboul 0.5 km) is 10 Ihe Ihickness of a credi l card (aboul 0.5 mm). I've been worki ng in Ihis field for IWO decades. and Ihe amounl of transIstors on a chip slill amazes me. The num ber I bill ion is bigger than mosl of us have an intuilive feel for. Th ink of pen nies, and consider Ihe volume Ihal I billion pennies would occupy. Would Ihey fil in your bedroom? The answer is probably no (unless you have a really huge bedroom), since a Iypica l bedroom is aboul 40 cubic meiers, while I billion pennies wou ld occupy aboul 400 cubic melers. So you would need aboul 10 bedrooms, roughly Ihe size of an el1lire house, packed from wall to wall , floor 10 ce iling, wi th pennies, 10 slore all Ihal money. And if we Slacked the pennies, Ihey would reach nearly 1000 miles imo Ihe sky-for comparison. a jel fli es at an allilude of about 5 mi les. That 's a lot of pen ni es. BUI we manage to fi l I billion lransislors onto si licon chips of jusl a few square cemimelers. Truly amazing. The wi res thai connecl all those transistors on a chip, if straightened into one straight
~
35
HOW 00 THEY MAKE TRANSISTORS SO SMALL? USING PHOTOGRAPHIC METHODS
If you look a pencil and made Ihe smallest dOl Ihat you could on a sheel of paper. Ihat dOl'S area would hold many thousands of transi stors on a modem sil icon chip.
How can chip makers create such liny transistors? The
key lies in photographic mel hods. Chip makers lay a special chemical OnlO the chip, special because Ihe chemical changes When exposed 10 light. Chip makers Ihen shine Iighl through a lens Ihal focuses the lighl down to ex tremely small regions on the chi p-si milar to how a microscope' lens ICls us Sec li ny things by focusing light. but in reverse. The chemical in Ihe small illu mi nated region changes. and lhen a solvent washes away th e chemical-but some regions stay because of
the lighl that changed thaI region. Those remaining
regions form pans of transislors. Repeating this proces over and over again. with different chemicals at different steps, results not only in transistors. but also wires connecting [he transistors. and insuJators preventing crossing wires from touching.
Photograph of a Pentium processor's silicon chip haviflg millions of lraflsislors. Acltlal si:e is about I em each side.
wire. wou ld be several miles long.
IC Iransistors are much smaller, more reliable, fasler. and less power-hungry than discrele lransislors. Thus, IC lransistors are now by far the mo t com monly used switch in computing.
ICs of the early 1960s could hold tens of transistors, and are known today as small. scale il1legrati on (SS/). As transistor sizes shrank. in the late I960s and early I970s, ICs cou ld hold hundreds of transistors, known as medi um-scale integration (MS/). The 1970s saw the developmem of large-scale integration (LS/) ICs with thousands of transistOrl;, while very- large scale integrat ion (VLS/) chips evolved in the I980s. Since then, ICs have cominued to increase in their capacity, to around I billion transistors. To calibrate your underst:lI1ding of thi s number. consider thai the first Pentium microprocessor of the early 1990s required only aboul 3 million transistors, and some popular but relatively small microprocessors require only about 100,000 transistors. Many of today' high-end chips Iherefore comai n dozens of microprocessors, and can conce ivably comain hundreds of the relatively small microprocessors (or just one or two big microprocessor ). IC density has been doubling roughly every 18 months since the I960s. The doubling of IC densi ty every 18 months is widely known as Moore's Law, named after Gordon Moore, a co-fo under of [ntel Corporat ion, who made predict ions back in 1965 that the num,ber of componenls per IC would double every year or so. At some point, chip makcrl; won t be able 10 hnnk transIstors any fun her. After all . the transistor has to at least be
~ A SIGNIFICANT INVENTION We now know lhal lhe inven tion of the transistor was the sian of the amazing computation and communication
revolutions thaI occurred in the laller half of Ihe 20th century. enabl ing us 10 loday do Ihings like see the world On TV. surf Ihe web. and lalk on cell phones. Bul Ihe Implications of the transistor were not known by mOSI
people at Ihe time of its invenlion. Newspapers did nOl headline the news. and mosl stories Ihat did appear predlcled "mply Ihal transislOrs would improve things like rad,os and heari ng aids. One may wonder whal recently invented bUI unnoti cd lechnology mighl SIgnificantly Change Ihc world once again.
D
wide enough to lei electrons pass through. People have been predicting the end of Moore's Law for over a decade now. but transistors keep shrinking. Not only do smaller transistors and wire provide for more functionality in a Chip. but they also provide for Faster circuits. in pan because electrons need not travel as far to get from one transistor to the next. This increased speed is the main reason why personal computer clock speeds have impro ed so drastically over the past few decade. from kilohem frequencies in the 1970 to gigahenz freq uencies in the early 2000 .
2.3 THE CMOS TRANSISTOR The most popu lar type of IC transistor is the CMOS transi tor. Although a detailed e.~pla nation of how a CMOS tran istor works is beyond the cope of this book. nevertheless. I've found that a simplified explanation seems to satisfy much curiosity. A chip is made primarily from the element silicon. A hip. also known as an integrated circuit, or IC, is typically about the size of a fingernail. Even if you open up a computer or ot her chip-based device. you would not actually see the ilicon chip, inee chips are actually inside a larger. usual ly black. protccti"e package. But )OU ""'nainl) should be able to see those black package. mounted on a printed ireuit board_ in ide a variety of household electronic devices. Figure 2.4 illustrates a cross section of a tiny pan of silicon hip. howing the ' ide view of one type of CMOS transistor-an nMOS trnnsistor. The trnnsistor has the thre..> parts of a switch: ( I) the SOl/ree input: (2) the output. which is ailed the drain. I suppobecau e electric panicles flow to the drain like water Hows to 3 drain: and (3) the :onO'OI input. which is ca lled the gate. I suppose because the gate blocks the current Ho\\ like a gate bl ocks a dog from e caping the ba kyard . A hip maker o-eates the soun-e and drain by injecting cenai n elements into the -iii on. Figul'e _..! al'o 'ho\\ _ the el 'O'Onic s)mool of an nMO transistor. Suppose the drain was onne 'ted to a slllall po -ithe ,oltagc (Illodem t 'ho'iogi: use about I or 2 ) knO\\~l as the "power suppl):' and the source \\:l> X'nn ·ted thn.'\U.gh
36
2 Combinational Logic Design A positive
... aHracts electrons here, turning the channel between Source and drain into a conductor.
vol tage here ..
2.3 The CMOS Transistor
nMOS~ gate--jl
~
{
conducts
37
~
~l
does not conduct
(bJ
(aJ
PMOS~
,"'-4,
Figure 2.4 CMOS transistors: (aJ transistor on silicon. (b) nM OS tran sistor symbol with indicati on of conductin g when
~
'4
l
does not conduct (c)
'-4\J conducts
gate; I. (c) pMOS transistor symbol condu cts when gate; O. a resistor to grou nd. Current would thus want to Row from drain to source, and on to gro und . (Note: unfortunatel y, conve ntion is that current How is de fined using positive cha rge, even tho ugh ac tuall y negati vely charged electrons are fl ow ing-so you may notice that we say current fl ows from drain to source, even though e lecLrons flow from source to drain .) However, the silicon channel between source and drain is not normally a cond uctor, or in other words, the channel is normall y an in sula tor. We can think of an insul ator as a n extremel y large resistance. Since I ; VfR, then I will essentiall y be O. The sw itc h is off. The really inte resting thing about silicon is that we can c hange the chan nel from a n ins ul ato r to a conductor just by applying a sma ll positive voltage to the ga te. Th at ga te voltage doesn' t result in cu rrent fl ow from the ga te to c hannel , beca use o f the s ma ll insulator (ox ide) between the ga te a nd the c hannel. But, that gate vo ltage does create a posi ti ve electric fie ld that a ttrac ts e lec trons, whi c h have a negat ive c harge, fro m the larger silicon region into the channe l regio n-a kin to how yo u can mo ve paper clips on a tab letop by mov ing a magne t under the tab le. When e nough e lectrons gather into the chan nel, the cha nne l all of a sudde n becomes a co nd uctor. A co nd uctor has ex treme ly low resistance, so c urren t flow s a lmost free ly betwee n drain and source. The sw itch is now on. As yo u can see, s ili co n is not quite a conduc tor but no t quite a n in sulator ei ther, mlhe r re presenting something in betwee n- he nce the te rm semicOllducl or. An a na logy to the cu rrent trying to cross the channe l is a pe rson try in g to cross a ri ve r. No rma ll y, the ri ver mi ght not have e nough stepping sto nes for the pe rson to be ab le to wa lk across. But if we could altract stones from othe r pa rt o f Ihe river into one pathway (the c hannel), the pe rson could eas il y wa lk ((cross the river (Figure 2.5).
Figure 2.5 CMOS transistor operation analogy-A person may not be able to cross a river until JUSt enough stepping stones are attracted into one pathway. Likewise, electrons can 't cross the channel between Source and drain until just enough electrons are attracted into the channel.
We mentioned that nMOS was one type of CMOS transistor. The other type is pMOS . A pMOS is similar except that the channel has the opposite functionality-the chan nel is a conductor norma ll y, and then doesll'r conduct when the gate has a positive voltage. Figure 2.4 shows the e lectronic sy mbol for a pMOS transistors. The use of these two "complementary" types of transistors is where the C comes from in CMOS. The MOS stands for Metal Oxide Semiconductor, but the reasons for that name go beyond the scope of thi s discussion .
~ SILICON VALLEY, ANO THE SHAPE OF SILICON Silicon Valley is not a city, but refers to an area in Northern Califomia. about an hour south of San Francisco, that includes several cities like San Jose, Mountain View. Sunnyvale, Milpitas, Palo Alto. and others. The area is heavily populated by computer and other high-technology companies, and to a large extent is the result of Stanford University's (located in Palo Alto) effons to attract and create such companies. What shape is silicon? Once. as my plane arri ved in Silicon Valley, the person next to me (who happened to be a college senior studyi ng Computer Science) asked "What shape is a silicon anyways?" I eventually rea li zed he thought silicon was a type of polygon. like a pentagon or an octagon. Well . the words do sound similar. Silicon is not a shape. but an element. like carbon or aluminum or sil ver. Silicon has un atomic number of 14, has a chemical symbol of"Si:' and i the second most abundan t element (next to oxygen) in the earth's crust, found in items like sand and clay. Silicon is lIsed to make mirrors and glass. in nddition to chips.
In fact. to the naked eye. a silicon chip actw!lJy looks like a small mirror.
A d rip packagt w;lh its chip coveT ~mQ\-nJ-."ou see rhl! mirror-like SiliCOII chip ill lite ctnur.
C'lUt
38
2 Combinational Log ic Design
2.4 Boolean Logic Gates- Building Blocks for Dighal Circuits
2.4 BOOLEAN LOGIC GATES- BUILDING BLOCKS FOR DIGITAL CIRC UITS You'vc seen that CMOS transistors can be used to implement switches on an incredibly tiny scale. However. trying to usc switches as Our building blocks to bui ld complex digital ctrcults is aki n to urying to use small rocks to build a bridge. as illustrated in Figure 2.6. Sure, you could probably bui ld someth ing from rudimentary building blocks, bu t the building process would be a real pain . Switches (and small rocks) are just too low-level as buildi ng blocks.
Transistors are
00);)00 These blocks ...
hard to work with ...are hard to work with.
------ ---- ----- - - - - - - - - -- - - ---- -- --- - ----. ---- - . ---- -.
---- - - --- - ----- -- ------- -
The logic gates that we'll soon introduce enable
greater designs ... enable greater designs.
Figure 2.6 Hav ing Ihe ri ght build ing blocks can make all the difference when building thi ngs.
Boolean Algebra and Its Relation to Digital Circuits Fonunately. Boolean logic gates help us in the design task by representing digital circuit bu ilding blocks that are much easier to work with than switches . Boolean logic was developed in the mid- 1800s by the mathematician George Boole. not to bui ld dig ital circuits (which weren' t even a glim mer in anyone's eye back then), but rather as a scheme for u ing algebraic methods to formali ze human logic and thought. An algebra is a branch of mathematics that uses letters or sy mbols to represent numbers or values, where those letters/symbols can be combined according to a set of known rules . Booleall algebra uses variables whose val ues can on ly be 1 or 0 (representing true or false, respectively) and whose operators, li ke AND, OR , and NOT, operate on such variables and return 1 Or O. So we might declare variables x, y . and z, and then say th at Z = x OR y , meaning z is 1 only if at least one of x or y is 1. Likewi se. we might say z = x. AND NOT(y). meaning z is 1 only if x is 1 ;lI1d y is O. Contrast Boolea n algebra with Ille regular algebra you 're familiar wi th from perhaps high school, in which variabl e va lues could be integers (for example), and operators cou ld be addition, subtracti on, and multipli cation. The basic Boolean operators are AND, OR. and NOT: A D return. 1 if both its operands are 1. So the result of a A D b is 1 if both a ~ 1 and b= 1, otherwise the result is O.
OR returns 1 if either or both of its operands are 1. So the result of a OR b is 1 the following cases: ab=OI , ab= 10, ab= 11. Thus, the only time a OR b IS 0 IS when a b-O O.
111 any.or
NOT returns 1 if its operand is O. So NOT(a) return 1 if a is O. and returns 0 if a IS 1. We use Boolean logic operators all the time in everyday thought such as in the statement "I'll go to lunch if Mary goes OR John goes, AND Sally does ~ot go." To represent thIS uSll1g Boolean concepts, let F represent my ooing to lunch (F-l means I'll go to lunch , F=O means I won ' t go). Let Boolean variables m, j, and 5 represent Mary, John. and Sally each going to lunch. Then we can translate the above English sentence into the Boolean equation:
F - (m OR j) AND NOT (s)
One thing we can do is determine the value of F for different values of m. j . and 5: • m=I , j=O, 5-1 ~ F = (l OR 0) AND NOT(l) • m=I , j=I , s=O ~ F = (lOR 1) AND NOT(O)
- -.._
--
= 1 AND 0 = 0 = 1 AND 1 = 1
In the first case, I don 't go to lunch; in the second, I do. A second thing we could do is apply some algebraic rules (which we'll discuss later) to modify the original eq uation to the equ ivalent equati on:
F - (m and NDT(s») OR
(j
and NOT(s»)
In other words, I'll go to lunch if Mary goes AND Sall y doe not go. OR if John goes AND Sally does not go. That statement, as different as it may look from the earlier ooe. is eq uivalent to the earlier one. A third th ing we could do is formally prove propertie about the equation. For example, we could prove that if Sally goes to lunch (5=1). then I don't go to lun b (F=O) no matter who else goes, using the equation:
F - (m OR j) AND ND T(I) - (m OR j) AND 0
0
No matter what the values of m and j . F will equal O. Noting all the mathematical activities we can do using Boolean equati ns. you can stan to see what Boole was trying to accomplish in formalizing human reasoning.
EXAMPLE 2.1 Converting a problem statement to a Boolean equation Convert Ihe following problem st3lemenlS 10 Boolean equation. u ing 10rs. F shou ld equal I only if: I. a is I and b is 1. A llslI'er: F = a A D b
2. ci lher of a or b is 1. AllslI'er: F = a OR b
~.
39
So F wi ll eq ual 1 if either m or j is 1. and s is O. ow that we've translated the English sentence into a Boolean equation. we can perform several mathematical activities with that eq uation.
DOD The right building blocks ...
"ob==O J" ij' s/rorrlullld fo r "0= 0. b=I."
roo
R. and :O\OT
('3-
40
Combinational Logic Design
2.4 Boolean Logic Gates- Building Blocks for Digital Circuits
J. both a and b are not O. AIl.\,wer:
(a l Oplion I: F; NOT(a) AND NOT(b) tbl Oplion 2: F ; a OR b 4. a is 1 and b is O. AII.m·er. F ; a AND NOT(b) .
atemcnts
J
Convert the followin g English prob em 51
"
. (0
Boolean equati ons:
d h
.
r ifhiah heat
IS
sensed an
ys tcm is set to enabled.
I CS
"
d F rep _
I A fire sprinkler system should spray wale . o . d " e represent "enabled, an . Answer: LeI Boolean variable h represent "'ugh heat IS sense .
.
,. TI
resent "sprayln g wate r.
quation is' F; hAND e.
len all e .
.
haken or the door is
.
bl d and eilher Ihe car IS s
, A ca r alarm shou ld sound if the alann I S e lla e . I "car 'IS shaken " d represent ., . bled" S rcprcsen , opened. AIIslI'er: Lei a re present alarm IS ena" ' i n is' F = a AND (s OR d). .. . ' ~d " and F represent "alarm sounds. Then an equat 0 .
_..
door ISopcne . ' . or d ro resenlS "door is closed" inslead of open (al Alternali vely. assunllng Ihal our door sens p blain the following equation : F; ( mc~ning d=l when the door is closed, 0 when open), we 0 a AND (s OR NOT(d)).
EXAMPLE 2.2 Evaluatin g Boolea n eq uations
f . bles a b Evaluale Ihe Boolean equalion F ; (a AND b) 0 R (c AND d) for Ihe given values 0 vana " C. and d: a=I, b=I , c-1. d- O. AIISII'er. F = (1 AND 1) OR (1 AND 0) a=O . b=1. c=O, d=I. AIISII'er. F a-I. b- 1. C= l.d =l. AIISh'er. F
(0 AND 1) OR (0 AND 1) ( 1 AND 1) OR (1 AND 1)
1 OR 0
1.
o OR
0
O.
1 OR 1
1.
One might now be wondering what
SIUlIIlIOfl,
by,he
1\'0)', ;.roI50
co".ridered the fa/hero! illfimllorioll theory dill' /0 "if later l1'ork 0 11 diXllal commlmic(J/WII .
Boolean algebra has to do with bui lding circu its using switches. In 1938, an MIT orad uate student named Claude Shannon ~vrote a paper (based on hi s Masters thesis) describin o how Boolean algebra could be applied t~ swi tch-based circuits, by showing that "on" switches could be treated as a I (or true). and "ofr ' switches as a 0 (or fal se), by connecting Ihose switches in a certain way (Fi oure 2.7). His thesis is widely considered as ~he seed that developed into modem dioital design. Since Boolean algebra comes w~h a rich set of ax ioms, theorems, postulates, and rules, we can use all those things to manipul ate digital circu its USing algcbra. In other wo rds:
Boolean algebra (mid-1800s)
Switches (1930s)
j !
Shannon (1938)
~
oro
gate
10
refer
"'ogic gOle."
/0
a
Let's first implement Boolean logic gates using CMOS transistors. and then later we' ll show you how Boolean algebra helps bui ld better circuits. You really don ' t hove to understand the underlyi ng transistor implementations of logic gates to learn the digital design methods in the rest of this book, and in fact many textbooks omit the tranSistor discussion entirely. But an understanding of the underl ying transistor implementation can be quite satisfyi ng to a student, leaving no "mysteries." Such an understanding can also help in understanding the nonideal behavior of logic gates that one may later have to learn to deal with in digital design. We ' ll start by using "I " to represent the power suppl y's voltage level, which today is usually arou nd I to 2 V for CMOS technology (e.g., 0.7 V, or 1.3 V). Let"s use "0" to represe nt ground. Note that we could have chosen any two symbols or words. rather than "I -and "0," to represent power and ground voltage levels. For example, we could bave used " t rue" and " f a 15 e," or " H" and "L." Remember that the "1 '- does nO! nece sarily correspond to I V, and the "0" does not neceSSari ly correspond to 0 V. In fact each usually represents a voltage range, like "1" representing any VOltage between 1.2 V to 1.4 V_
Symbol
For telephone switching and other
electronic uses Showed application of Boolean algebra to design of switchbased circuits
Truth table
NOT
OR
~
y 0 0 0 0 1 0
Figure 2.7 Shan non applied Boolean .. algebra 10 swilch-based circuils. p~vld ll1g a form al basis 10 digital circuil deSign.
1
1 0
Figure 2.8 Basic logic gales symbols, trulh lables, and transislor circuits: (a) NOT (i nverter) gate. (b) 2-i npul OR gate, (c) 2-input AND gate. Warning: rea l AND and OR g",es arell " aClually buill this way, but ra th er in n more complex manner-sec Section 2.8.
AND
xV- F ;D-F ;D-F xF xF o
Digital design
We ca n build circuits by doing math.
-... - -
Earlier we said a "gate" was the .flilitch c:ofllrol iI/put of a CMOS tralls is to r, but fl OW we're tlllkiflg about "logic: gates." III all ulI/orluI/ate Iwming similarity, the sallie \.... (gate) refers to two different things. D Oli '/ worry /h ollgh; (I/ter Ihe "ext sec/io l/, we '/I jus t be /I sing the wo rd
To bui ld digital circuits that can be manipulated using Boolean algebra, we tirst implement the Boolean operators AND, OR, and NOT using small circuits of switches, and we call those circuits Boolean logic gates. Then, we fo rger obour swirches_ and instead use Boolean logic gates as Our building blocks. Suddenly, we have the power of Boolean algebra at Our fingertips when deSigning more complex circuits! This is akin to first asse mbling rocks into three shapes of bricks, and then building structures like a bridge from those bricks, as illustrated in Figure 2.6. Trying to build a bridge from small rocks is much harder than bUilding a bridge from the three basic brick shapes. Likewise, trying to build a moti on-in-the-dark circui t (or any digital circuit) from switches is harder than building a circuit from Boolean logic gates.
Boole's intent: formalize human thought
That 's an ex tremely powerful concept. We' ll be building circuits by doing math throughout this chaptcr.
..
41
AND, OR, & NOT Gates
Transistor circuit
F
(a)
(b)
y
~
0
1
0
0
0
42
2 Combinational Logic Design 2.4 Boolean Logic Gates- Building Blocks for Digital Circuits
NOT Gate I s be the oppos ite, or inverse, A NOT gale has an input X and an output F. F should n way We can bu ild a NOT C • • I ' called an /IIver a f X-lor thI s reason. a NOT gate IS common) . F' ler . ? 8(a) The tri anole at . s shown In IOllfC _ . ,. co gate using one pMOS and one nMOS transIstOr, a of' l ower supply which .. e voll '.0. aoe a lIe p ents ground , which the top of Ihe transistor circuit represents the POSII1V we represent as 1. The seri es of lines at the battorn of Ihe ClfCUlt" repres11 onduct ,but the , we represe11l as O. When Ihe .1I1put x .IS 0, Ihe pMOS transIstorh'WkI cf the circuit as a . not. as shown .111 F,gure . ?_. 9( a) . In Ih a t case nM OS will , we can t In. a1 the nMOS will . fl'O m 1 to F, so when x =0, F =1. 0 n tIIe a ther hand when X IS , e can think of " wife 29(b) . . In that. case, F' w 28 called a conduCI, bu t Ihe pMOS wil. l not, as shown .In FIgure " the ClfCUlt as . a Wife from 0 10 F, so when X= 1, F-- O. The table 111 ' Iguret .t ,for every Irlllll lab le, summarizes the NOT gate's behavior by listing the gate s au pu poss ible input.
o~
F
Figure 2.11 OR gate conduclion paths when: (a) one inpul is l. and (b) bOlh inputs are O.
time
Figure 2.12 OR gate liming diagram.
Figure 2.9 In ve rt er conducti on paths when:
D-
(a) the input is O. and (b) the input is 1.
F1 ~ o - - - - -...
time
Figure 2.10 Inverter liming diagram.
Figure 2. 10 shows a liming diagram for an inverter-when the input is 0, the output is 1; when the input is 1, the output is O. Electrically, combining pMOS and nMOS in this way has the benefit of low-power. otice in Fi gure 2.8(a) th at fo r any value of x, either the pMOS or nM OS tranststor wi ll be nonco nducting. Thus (conceptually), current can never now fl'Om the power source to ground- thi s feature will also be true fo r the AND and OR gates we' ll define next. Thi s feature makes CMOS circuits consume far less power than other transistor techn ologies, and part ly exp lains why CMOS is the most popular logic gate tranststor technology today. OR Gate A basic OR gale has two inputs x and y and an OUIPUI F. F should be 1 only if at least one of X or y is l. We can bui ld an OR gate using two pMOS transistors and two nMOS trans istors, as shown in Figure 2.8(b) (although we will see in Section 2.8 th at OR gates are actually built in a more complex manner). If al least one of X or y is 1. then we get a connecti on from 1 to F, but no connection from 0 to F, so F is 1, as shown in Figure 2.II(a). If both X and y are 0, then we get a connection from 0 10 F, but no connection from 1 to F, so F is 0, as shown in Figure 2.11 (b). The truth table for the OR gate appears in Figure 2.8(b).
43
. Figure 2.1 2shows a timing diagram for an OR gate. (See Section 1.3 for an introductIon to lIm1l1g diagrams.) We set inputs x and y to each possible combination of values. and show that F wlil be 1 if ei ther Or both inputs is a 1. Larger OR gates, having more than two inputs, are also pos ible. If at least one of the OR gate 's inputs are 1, the output is l. For a three-input OR gate. the tran iSlOr clrcuit Figure 2.8(b) would have three pMOS transistors on top and three nMOS transi [Ors on the bottom, instead of two transistors of each kind .
AND Gate A basic AND gale has Iwo inputs x and y and an outpul F. F should be 1 only if both x and y are l. We can build an AN D gate usi ng two pMOS transi stors and two nMOS transistors, as shown in Figure 2.8(c) (again, we will see in Section 2.8 that AND gates are actually built in a more complex manner). If both x and y are 1. then we get a connection from power to F, but no connection from ground to F, so F is l. as hown in Figure 2. 13(a). If at least one of x or y is 0, then we get a connection from ground [0 F. but no connection from power to F, so F is 0, as shown in Figure 2.13(b). The truth table for the AND gate appears in Figure 2.8(c).
x~JLJ
~~
F
0----1'
Figure 2.13 AND gate conduction paths when: (a) all inpuls are l. and (b) and input is O.
time
figure 2.14 AND gate timing di:'lgram.
Figure 2. 14 shows a tim ing diagram for an AND gate. We set input$ \ and) to a h possible combination of va lucs. and show that F \\'ill be 1 onl) if both inputs :II\' a .
- - - - - -- - -- - ._-44
,-
, 1 onl y if 'ble The output IS aroer AND oates, having more than twO inPhu ts, are P sO t ~~lcir~uit Figure 2. 8(b) wo uld L • " " . . ut AND oate. t e transl . tead of '111 the inputs are 1. For a three-tnp d h " nMOS transistors on the bOllom , tnS ;,ave three pMOS transistors on top an tree twO transistors of each ktnd.
2.4 Boolean Logic Gates-Building Blocks for
Combinational Logic Design
Building Simple Circuits Using Gates Detector
a -,.- - --1
EXAMPLE 2.5
how how to build
:%, ;0-, (3)
examp les.
Convert the following equation to a circuit:
F :
a AND NOT( b OR NOHe)
We start by drawing F on the ri ghi, and then worki ng backwards toward ',he inputs. (We ~ould instead start by drawing the Inputs on (h.c left and work ing toward the output.) The equation for F
ANDs IWO ilems: a. and the OUtpUI ~f a NOT. We thus begi n by draw ing the CIrCUit of Figure 2.. 15(a). The NOT's inpul comes from an OR of Iwa Items: b. and NOT(C). We th us complete the drawtng tn Figure 2. 15(b) by includi ng an OR gate and NOT
(b)
Figure 2.17 Using multiple-input AND gates: (a) using 2-input AND gates. (b) using a 3-input AND gate.
-i>D-F (3)
,~' Figure 2.t5 Building the circuit for F: (a) partial, (b) complete.
The same approach applies to OR gates. For example. F = a OR b OR e "auld typically be implemented using a single three-input OR gate. We now provide examples tarring from Eng lish problem de criptions. which we convert to Boolean equations, and then fi nally implement as a ci rcuit.
EXAMPLE 2.6 Seatbelt warning light Suppose you
Want
to design a system for an au tomobile Lhal
illuminates a warning light whenever the driver's seatbelt is not fastened and the key is in the ignition. Ass ume the followiog sensors: a sensor with output S indicates whether the driver's belt is fastened (5 = 1 means the belt is fastened ). and
gate as shown .
EXAMPLE 2.4 M e examples converting Boolean equations to gates
. or . . s to circui ts bUilt from Fioure 2. 16 provides IwO more examples of convertmg Boolean equ~ lI on e fi ure shows the lo:ic gates. We agai n start fro m the output and wo rk backwards to th~ tnputs. ~~e I~ced each gate " a ndenee between equa ti on operators and gates. and the order In which p corresp in the circui t. F = (a AND NOT(b)) OR (b AN D NOTlc)) 2 1 3
F
a sensor with output k indicates whether the key is in
the igni tion (k =1 means the key is in).
Assume the warni ng light has a single input wthaI i1luminales the light when w is I. So the inputs to our digital system are 5
and k, and the Outpul is w. wshou ld equal 1 when both of the fOllowi ng occur: 5 is 0 and k is I. Let's first write a simple C program executing on a microproce sor to solve thi s design problem. If we connect S
to 10, k to n, and I. to PO, then Our C code inside the C program's main () function would be: wh i 1 e (1) I PD - ! 10 && I I :
(3)
(b)
Figure 2.16 Examples of conve ning Boolean equations to circuits.
45
Figure 2. 17(a) shows an implementalion of the equation F = a AND bAND c. using two-input AND gates. However. deSigners would typically instead implement such an equation using a single threetnput AND.gate, shown in Figure 2. 17(b). The function is Ihe same. but the three-input AND g3le uses fewer tran IStOrs, 6 rather than 4 + 4 =8 (as well as having Ie s delay-more on delay later). Likewise, F = a AND b AND c AND d would typically be implemented u ing a four-input AND gate.
.. bl k f om transistors, we now s F' Having bu il t logic gate butldtng ~Ic ~ r Recall the digi tal system example of Igure use ful circ ui ts from those bUlld tng oc s. t'on and b=O meant dark, so we . d ark de tector. a= l meant 010 Ih , . erter to get NOT ( b ) , and I 13 the mo ti on-tn-the. . d F - a AN D NOT(b). We can connect b throug an tnv . F The resulting circuit wante . AND oate whose output IS . '" . We now provide more ect the result along with a tnto an conn I 13(c) to the left for conve ntence. appears .111 F'19ure . , shown again ....
EXAMPLE 2.3 Convertin g a Boolean equation to a circ uit with logic gates
Dig~a l Circuits
Using AND and OR gates with more than two inputs
The code repeatedly checks the sen ors and updates the warning lighl. Now leI's write a Boolean equlllion describing a ircui[ implementing the design: w - NOT( 5) AND
46
2 Combinational Logic Design
.
lete the
.
ccd earlier. we can eas il y cam p Usi no the AND and NOT logic gales that w~l1ltrod~ ld connect ing the resultin g NOT(s) and ' n ' f ~ur first system. by con necting s to a N? ~3te, [
~e~~o:~~ inputs of a 2-input AND gate,. as shO\~n l~h:'~~r~Cu~: I ~~ a timing diagralll, we can set :~~ Figu re 2. 19 provides n IImmg dwgram or
draw the ou tput line to match the Clfeu
whatever values we want. but theOn \V~,;~U~~ then 10. then 11. The onl y time that the . I h figure we set 5 and k to . t , function. n t c . ' . 0 d k ' 1 as shown in the fi gure. output \'1 wi ll be 1 IS when S IS an IS . inputs
a
to
Inpuls
kl~
BeltWarn
o
5 1
0
_ _ __
J
OulpUIS
wl~ o ..
warni ng cireui !.
fu~her
L.et·s
ex.tend th e previous example. Automo_
biles tYPically IIghl up all their warning lights when you first lurn the key. so yo u can check that all the
BeltWam
wa~,"g IJ g,hts are working, Assume that Our sys tem
receives an Input t that is 1 for th e first 5 seconds after a key is inserted into th e ignition, and 0 afterward (don't worry aboui who Or whal sets t in thai way). So we wan! '1=1 when p=l and s =D and k=l , OR when t =1. NOle that When t =l . we illuminale the light, regardless of the values of p, s, and k. The new circuil equation is:
w
=
(p AND NOT (s)
AND k) DR t
Figure 2.22 Extended seat belt warning ci rcuit.
The circuit is shown in Figure 2.22.
Some circuit drawing rules and conventions There are some rules and conventions thaI designers commonly fOllow When drawing circuits of logic gates: Logic gates have one or more inputs and one outpul, bUI we typically don ' l label each gate's inpUlS or output. Remember that the order of the inputs inlo a gate doesn'l impact the logical behavior of the gale.
We stated earli er that logic gates are more approp riate than transistors as building blocks for desionin o digital Clrcutts. Note, however, that the 100 i; oates are ultimately implemented " as shown I.n . F'Igure .-:??O For using trans"istors, ' _
w
C programmers, an analogy IS Ihal w rltmg soft-
ware in C is easier than wri ting 10 assembly. even though the C ultimalely gets implemenled using asse mbly. Notice how much less mlUltlve and less descripti ve is Ihe tran s l slor-bas~d circuit in Figure 2.20 than the equi valent logiC gate-based circuil in Figure 2.18. Figure 2.20 Seat belt warning
EXAMPLE 2.7 Seat belt wa rn ing light with driver sensor
Seat belt warning light with initial illumination
ti me
Figure 2.19 Timing diagram for seatbell warning circuit.
Seatbelt
Figure 2.18 Seat belt
2.5 Boolean Algebra
EXAMPLE 2.8
circuit usin g transisto rs,
Each wire has an implicit direction. going from one gate's Outpul to another gate's inpuI, but we typiCally don' l draw arrows showing each direction.
no
yes
=D- D-
A single wire can be branched OUI inlo two (or more) wires going 10 multiple gate inputs-the branches have Ihe same value as the si ngle wire. But two wires can NOT be merged into one wire-whal wo uld be the value of that one wire if the incomi ng IWO wire had different values?
Let 's extend the previous example by adding a sensor. wi th ou tput p. that detects whether a
perso~ IS
aClUally sitting in the dri ver's seat, and by
ehang~ng
the system 's behavior
LO
BellWarn
on ly illuminate the warning
when a person is detected in the seat (p=l) . So the new ci rcuit equation is:
w-
P AND NDT(s ) AND k
In this case, we need a 3-input AND gate. The cireuil is shown in Figure 2.2 1. Be aware thaI the order of the AN D gale's inputs does not matter,
Figure 2.21 Seal be ll warning circuit with person senso r,
2.5 BOOLEAN ALGEBRA Logic gales are lIseful for implementing circuits. bUI equations are bener for manipulating circui ts. The algebraic tools of Boolean algebm enable us to manipulate Boolean equations so we can do th ings li ke simplify the equations. check if two equati as are equivalent, find the inverse of an equation . prove properties about the equati n . et '. Since a Boolean equation consisting of AND. OR. and 'OT opemti n an be straightforwardly transformed into a circuil of AND. OR. and 'OT gate' . manipulating Boolean eq uations can be con idered as manipulating digital circuils. Well informally introduce some of the most u 'eful algebraic I' f Bool an a lgebra . API endi x A provides a fOrlnal definition of B lean algebr.l.
47
48
2.5 Boolean Algebra
2 Combinational Logic Design
TABLE 2.1 Symbol
Notation and Terminology d 'b' n o Boolean equati ons. We' ll . d linolooy fo r escn I " I" book We now define some notation an tem use these definitions extensively throughout t 1e .
(J
Name Parentheses NOT
Operators tors in equatio ns is cumbersome. Thus, Boolean Writing out the AN D, O R and NOT opera . . f those operators. _, I 'whic h o ne peaks of as algebra uses si mpler notauon or . .. ' or a. We I use a , "NOT (a)" is typIca ll y wn tten as a I t of a or the illl'erse o f a . . k 1 as the comp emell . "a prime." a ' IS a lso ' noWI ' fi ' 11y 'Intended to look similar to . "a + b " spec l C,I f "a OR b" is typica ll y wntten as :, b'" ve n referred to as the slim 0 . I loebra. a + IS e II b" lhe addition operator III regu ar a 0 " b" is usually spoken of as a or . . a and b. a + . . "* b" or "a. b." specifically Intended to look "a AN D b" is typ Icall y wntten as a. I Ige bra and even re fe rred to as . I' . operator \0 regu ar a J ..." ~ h sim ilar to the multlp Icatlon . I b a we can even wnte a b ,or t e t as In regular a ge r , . I d b are separate va riabl es IS c ear. the product of a and b. Jus f and b as lon o as the fact that a an ". prod uct 0 a . Of" d b" or even just as . a b. "a *b" is usually spoken 0 as a an . . h otations for Boolean operators, but the above nota. s like ly due to the Intenuonal MathematiCIans often use ot er n tions seem to be the most popular among englnee;o;' b simil ari ty of those operators wi th regul~r algea:~~;:xaampie of: Usi ng the simpler notallon, our ear ler se
w = (p AND NOT(s) AND k) OR t could be rewritten more conci sely as:
w = ps ' k
+ t
which wo uld be spoken of as "w equals p s prime k, or I." EXAMPLE 2.9
Speaking Boolean equations Speak the fo llowi ng equations: I. F = a' b'
2. F :::
a +
+ e. Allswer: "F equals a prime b prime or c." b
*
c ' . Answer: "F equals a or band c prime:'
Convert the fo llowing spoken eq uations into wti ucn equations: I. "F equals a b prime c prime." Answer: F = a b ' e' .
2. "F equals abc or d e prime." Answer: F = a be + de'. Th rul:
les o f Boolean algebra require that we evaluate expressions using Ihe precedence
~at * has precedence over +, that complementing a v:triablc has precedence over *
d that we of course compute what's in parentheses first. We can make the earlter d+ an • an .. . , r II " w _ (p * (5') * equation'S order of evaluation explICIt uSlOg parentheses as 0 OWS. k) + t. Table 2. 1 summarizes Boolean algebra precedence rule, .
49
Boolean algebra precedence, highest precedence first
AND
+
OR
Desc ription Evalullle expressions nested in parentheses fi rst
Evaluate from left to righl Evaluate from left to right Evaluate from lefl to right
Conventions Although we borrowed the multiplication and add ition operations from regular aJoebra and even use the terms sum and produ ct, we dOli '! say "times" for AND or "plus" fo~ OR. Dtgl ta l. deSIgn tex tbooks typicall y name each variable u ing a single character. bec~use uSlOg a slOgle charac ter makes for concise equations like the equations above. We II be WfltlO g many equations, so conci eness wi ll aid understanding by preventing equations that ~rap across multiple lines or pages. Thus. we'l l usuall y follow the conventIOn of uS lOg slOg Ie charac ters. However, when you de cribe digital systems using a hardware description language or a programming language like C. you hould probably use much more deSCriptive names so that your code is readable. So in tead of u ing " s " to represeot the o utput of a seat-belt-fastened ensor, you might instead use " SeatBel tFastened." EXAMPLE 2.10
Evaluating Boolean equations using precedence rules Evaluale the following Boolean equations. ass uming a=l, b=l. e - D, d=l. J. F = a * b + C. Answer: * has precedence over +. 1 ) + 0 = (1) + 0 = 1 + 0 = 1.
0
we evaluate the equation as F ::: (1 '"
2. F = a b + e . Allswer: the problem is identical to the previous problem. using the hortband notation for *. a b ' . Answer: we first evaluate b' because OT has precedence O\'er AND. resulting in F = 1 * (1 ' ) = 1 * (0) = 1 * 0 = D.
3. F
4. F = (ae) ' . Allswer: we first evaluate what is inside the parentheses. then \\e :"OT the result. yielding (l *0) ' = (0)' = 0' = 1. 5. F = (a + b ' ) * c + d ' . Alls,,·.r: The parentheses h"e highest preceden e. Inside the parentheses. NOT has highest precedence. So we evaluate the parentheses pan !IS ( 1 l ' 1 (] + (0» = (] + 0) = 1. ext. * has precedence O\er +, yielding (] ~ 0 - l ' ( 0) + 1 ' . The NOT has preceden e over the OR. gi"ing (0) + ( I' ) = ( 0) _ = 0 + 0 - O. Variables, Literals, Terms, and Sum of Products Le t's define a few more concepts, u ing the e 'ample equation: F ( a . b. e)
abc' + ab + c.
a' c
Variable : A variable represen ts a quantil) (0 or D. The abo\e equJtit>n h ,three variables: a . b. and c . We typically USe \:uiables in Boolean <'quation, to repn'sent the inputs of our system ometimes \\e e'\plicitl) li,t" fun,'u n', \arlabl , as above ("F (a. b. c) = ..... ). Other times we omit th e'Pli~it Ii,t (" F _ ..... \.
50
2 Comb inational Logic Design
2.5 Boolean Algebra
. ble in either true or complemented Literal: A literal is the appearance of a v~n ab ' a b c ' a, b, and e . form. The above eq uati on has 9 literals: a .' e, T'h ' b 'equat ion has four . a product of hterals. e a ove Prodllctterm : A product term IS . f d t terms is known as terms: a' be, a be ' , a b, and e. . . as an OR1I1" 0 pro uc SlI m-oJ-Prodll cts: An eq ual10n wntten quation for F is in sum-of. f d f n The above examp e e , bei ng 111 sum-o -pro ucts . on . . II in sum-of-products form: producls form. The follow1l1g equations are a
i
a + a' = 1 a * a' = 0 This also makes intuitive sense. Regardless of the value of a, a' is the opposite. so yo u get a 0 and a 1, or you get a 1 and a O. One of (a, a ') will always be a 1. so ORlllg them (a+a ' ) must yield a l. Likewise, one of (a, a ' ) will always be a 0, so AND1I1g them (a*a') must yield a O.
abc + abc ' a b + a ' e + a be h ve ' ust one literal). a + b ' + a e (note Ihat a prod uct term can a J . ' SUIn -of-products form: The fo llowing equal10ns are alI NOT 111
+ b)e (a b + be) (b + c)
Let's now apply these basic properties to some digital desi!m examples to see how these 0 , propertjes can help us.
(a
(a') ' + b a(b + e(d + e)) (ab + be) '
Some Properties of Boolean Algebra I bra. Assume a, b, and e are Boolean We now li st some of the key ru les of Boolean age variables, which each hold either the value of 0 or 1.
Basic Properties The followin g properties, known as postu lates, are assumed to be true:
51
Makes intuit ive sense right? OR ' . 0 . . 1I1g a with (a+o) Just means that the result will b h .. , . e*w atever a IS. After all , 1+0 is 1, while 0+0 is O. Likewise, ANDing a with 1 (a 1) results 111 a. 1 *1 is 1, while 0*1 is O. • Complement
EXAMPLE 2.11
Applying the basic properties of Boolea n algeb ra Use Ihe properties of Boolean algebra for Ihe foll owing problems: Show Ihal abc ' is equ ivalenllO c ' ba . The commutative property allows us 10 swap the operands bein. ANDed, so a*b*c' a*e ' *b = c ' *a*b = c ' *b*a = c ' ba . Show thai abc + abc ' = ab . The firsl di slributive property allows us 10 factor out the a b tenn: abc + abc' a b (e+c ' l. Then, the compie men I property allow us to replace the c+c' by 1: a b (c+c ' ) = a b ( 1 ). Finally. the identity property allows us to remove the 1 from the AND lerm:ab(1) = ab*1 = abo Show that Lhe equati on X + x ' Z is equivalent to X + z.
• COlllmutative
a + b a * b
=
b + a
=
b * a
This property should be obvious. Just try it for different values of a and b. • Distriblltive
a * (b + c) = a * b + a * c a + (b * c) = (a + b) * (a + c) (litis aile is Irick)'!) Careful , the second one may not be obvious. It 's different than .regular algebra. But yo u can verify that both of the distributive properti es hold Imply by evaluating both sides for all possible values of a, b, and e. • Associative (a + b) + c = a + (b + c) (a * b) * c = a * (b * c) Again, try it for different values of a and b 10 see Ihat this holds. • Identity o + a = a + 0 - a
1
* a
~
a * 1 - a
The second distributive property (the tricky one) allows us to replace x+x' Z by (x+x' )*(x+zl. The complement property allows us to replace (x+x' ) by 1. and the identity property allows us to replace 1*( x+z) by X+Z.
EXAMPLE 2.12 Simplification of an automatic sliding door system Suppose you wi sh to des ign a system to conlTOl an
aUlomatic sliding door. like one ~l at might be found at a grocery slore's entrance. An input p lO ou r system
indicates whether a sensor detects a person in front of the door (p= I means a person is detected). An input h indicates whether the door should be manually held open (h =1) regardless or whelher a person is detected. An inpul C indicate whether the door should be rorced to stay closed (like when the store is closed for business)-c = 1 means the door shou ld SlOy closed. The latter two wou ld nomlally be set by a manager with the Figure 2.23 Initial door opener ircui!. proper keys. An OUlput f opens the door when f is l. We want to open the door if the door is set to be manunlly held open. OR ir the door is nOi set to manually held open but a person is detected. However. in either ase, we nl~ open the door if the door is not set lO stay closed. \Ve can tmnslate these requirements into 3 Boolean equurion as: f - he ' + h' pc '
52
Combinational Logic Design
he ' + h'pe' e ' h + e 'h'p e ' (h + h ' p) e ' ( ( h+h ' ) * (h+p) ) e ' ((l)*(h + p» e ' (h+p)
(by the commutative property) (by the first distribu ti ve property) . I (by the 2nd distributive property-tncky one ,) (by the complement propert y) (by the identi ty property)
Note that th e simpler equation still makes intuitive sense-we open the door only if the door is not set to stay
DoorOpener
• Idempotent Law a + a a * a -
• Involution Law (a ' ) ' - a Again, fairly obvi@s, If a is 1, the first negation gives 0, while the second gives 1 aga in . Ltkewlse, If a tS O. the first negation gives I, while the second gives 0 agai n.
• DeMorgall 's Law (a + b) ' - a'b ' (ab) ' = a'
menting thi s equation is shown in Figure 2.24. Thu s. by
Simplification of logic circuits will be the focus of Section 2. I I .
figure 2.24 Simplified door opener circuit.
Equ ivalence of two automatic s li di ng door systems Suppose yo u found a reall y chea p device for automatic sliding door systems. The device had inputs e . h. and p and output f , as in Examp le 2. 12, but the device's documen tati on satd that. f
=
e ' hp + e ' hp' + e ' h ' p
Does that device do the same as that in Example 2. J 2? One way to check is = =
e 'hp + e ' hp' + e ' h'p e ' h(p + p') + C'h'p e ' h(l) + e ' h ' p e 'h + e ' h'p he' + h'pe '
(by (by (by (by
~Ions intUIti vely here, Consider ( a + b)' = a' b ' . The left side will only be 1 tf (a + b) evaluates to 0, which only occurs When both a AND b are 0 meanina a ' b' - the right side, Likewise, consider ( a b)' - a' + b'. The left ide only be 1 if (a b) evaluates to 0 , meaning at least one of a OR b muSt be O. meaning a' + b ' - the right s ide. DeMorgan 's Law can be stated in Englisb as follows: The complement of a sum equals the product of the complements: the complement of a product eq ua ls the sum of the complements. DeMorgan's Law i WIdely used, so take the ttme now to understand it and to remember it.
will
Let's apply some of these additional properties in more example.
EXAMPLE 2,14 Applying the additional properties (0
see if we can manipu-
late the above equation into the equation in Example 2.12:
f f
+ b'
Thes~ are. not as obvious. Their proofs are in Appendix A. Let's consider both equa-
appl yi ng the algebraic properties. we obtained a simpler ci rcuit. In other words, we used math to simplify the circuit.
a a
Again, this should be fairly obvious. If a is 1 1+1-1 d 1*1-1 hil'f a' 0 O+O ~ O and 0*0-0. ,an , weI IS.
closed (e ' ), AND either the door is set to be manua ll y held open (h) OR a person is de tected (p). A circuit imple·
EXAMPLE 2.13
53
2.5 Boolean Algebra
.' h'· "" ( on as in Figure 2.23. \Ve could bui ld a ci rcuit to lI11plemcnt ( IS cqua.l .' . d 'b'd earl 'ler Looki ng al the equa. . the properties escn l: ~ . . . 'ow let's manipulate the cquttllon lISlI1g . h b"" ble to simplify th e rema lnmg tion we believe we call factor Oul the c ' . We might 1 el~ ca e " "h+'h ' p" part toO. Let's try some transformations. fi rst factonng out
the distributive propert y) the complement property) the identity property) the commutat ive property)
That's the same as th e origi nal equation of Example 2. 12. so the device should work for us. Additional Pro perti es Let 's consider some add itional propenies. whic h happen to be known as theorems becau e they can be proven using the above postu lales:
• N ull elements
a + I - 1 a * 0 - 0 These sho uld be fairly obvious. I OR anything i, going to be anything is going to be 0,
1. while 0 AND
Convert the equation F = a b (e +d ) into sum·oF-products fonn. The distributive property allows us to "multiply out" the equation to F = a be Convert th e equation F
=
a bd.
wx (x ' y + zy ' + xy) into sum-of.productS form. and make
any obvious simplifications.
The distributive property allows us to "multiply out" the equation: wx (x ' y+zy' T y) = wxx ' y + wxzy ' + wxxy. That equation is in sum-of·products form. The complemen! property allows us to replace wxx ' y by w*O*y. and the null element property means thO! w*O*y = 0, The idempotent property al lows us to replace wx xy by wxy (because xx = Xl. The res ultin g equation is 0 + wxzy' + wxy - wxzy' + w y. Prove tha t x ( x ' + y ( X ' +y . ) ) can never evaluate to I. Repeated application of the first di tributive property yields: xx' +xy ( '+y') - x • + xy x ' + xy y , . The complement property tells us that X ' -0 and yy '-0. ~;elding + O*y + x*O. The null element property leads to 0 + 0 + O. \\hich equals O. Thus. the equation always evaluates to O. regardless of the a tunl \'a1ues of x and y. Determine the opposite function of F = ( a b' + e l. The desired fun ction is G = F' = (ab' +e ) ' . DeMortlan's Ul\\ ,i elds G a ' , * e', Applying DeMorgan's Law again to the firs t term-) ields G ~ ( a'·.-( b' 1 ' e ' . The involution property yields (a' + b ) ~ c ' . Finall). the dlstributh. prope~ yie lds G - a' c ' + be ',
54
2 Combinational Logic Design
2.6 Representations of Boolean Functions
~ YOUR PROBLEM IS MY PROBLEM
. raft lavatory sign EXAMPLE 2.15 Applying DeMorgan ,s Law .In an alrc .
~s
. 'Iled sioo indlcatCommercial ai rcraft Iypica ll y have ,an 'II I ~ J1lm. .:= se an airin£! whether a lavatory (bathroom)
IS
available. Suppo t
c~ft has three lavalorics. Each lav:llory has a sensor ~u ~u 1 if the lavalory door is locked. 0 otherwise. OUf circuli .
(linD
'0
WI
from those sensors. as
0
have three inputs. a. b. and c. camino . 'cd (whether shown in Fiourc 2.25. If (lilY lav:llory door IS un lock. .
55
Figure 2.25 Aircraft lavatory sign block.
The use of Boolean algebra for digital design is an example of ~l e powerful general concept of mapping one problem to another. By mapping a new problem (digital desig n) to an old problem (logic representation). the SOlutions (Boolean algebra) to the old problem can
"shou ld I1lul11lnate one. two. oreall three doors ~lre un lk oc ed) , \\1,; 1
be applied to the new problem. Immediately. the new problem can benefit from perhaps decades of work of solving the old problem. Mapping one problem to another is extremely common in engineering. especialJy in computing. Afler all, why reinvent the wheel?
the "Available" si!!.Jl by setting the ci rcuit's output S to .
\\l~th' th is understanding.
we recogni ze that the OR fu nc-
tion suits the problem. as OR ou tpu tS 1 if any of ,its i n~~ts are
" 1 We beglll 1. regardless 01. how many II1P.UtS ~re. '. ~ an 0 equation fo r S. 5 should be 1 If a IS 0 OR b IS 0 OR c . wnun o
Saying a is 0 is the same as sayi ng a
I.
Circuit
Su ppose your autommic door Contro l has an input with the opposite polarity as what we expect: 0 means open th e door, while 1 means close. \Ve can compUle the function 9 lhat opens the door. and simplify tha t func ti on, as fo llows:
a
Thus. the equatIOn for
9 9 9 9 9
5 is: S-a '+ b ' +c ' \Ve tran slate Ihe equation to Ihe ci rcuit in Figure 2.26. \Ve can apply DeMorgan's Law (in reverse) 10 the equation by noting th ai (a be) a +b +c so we can I
I
I
I
I
Figure 2.26 Aircraft lavatory sign circu it.
f' (c ' ( h+p » ' (c ' ) ' + (h+p) ' C + ( h+ p) ' + h'p'
(by sub tituting the equation for f) (by DeMorgan's Law) (by the Involution Law) (by DeMorgan 's Law)
replace the equation by:
= (abc) ' The circuit for that equation appears in Figure 2.27.
:$5Cf
2.6 REPRESENTATIONS OF BOOLEAN FUNCTIONS A Booleall jUllctioll is a mapping of each possible combination of values for the function's variables (t he inputs) to either a 0 or 1 (the output). An example of a Boolean funcrion described in regu lar English is a function F of variables a and b. such that the fun ction out pu ts I when a is 0 and b is 0, or when a is 0 and b is 1. There are e\'eraJ bener representati ons than Engli sh for de cribing a Boolean function. including equati ons, circu its, and truth tables, as shown in Figure 2.28. Each repre emarion has its own advantages and di sadvantages, and each is useful at different times during design . Yet all the representations, as different as they look from one another. represent the very arne funct ion. It 's like how there are different ways to represent a particular recipe for chocolate chip cookies: wri tten words, pictures, or even a video. But no matter how the recipe is represented, it 's the same recipe.
Figure 2.27 Circuit after applying DeMorgan's Law.
EXAMPLE 2.16
Proving a property of the automatic sliding door system Your boss wants you 10 prOl'e lhal the automati c sliding door circuit of Example 2. 12 ensures th:t the
door will stay closed when the door is supposed to be forced to stay closed. namely,when c- 1. [f the function f = c ' (h+p) describes the sliding door, you can prove the door wil l stay closed (f=O) using propenies of Boolean algebra: f = C ' (h+p) Let C = 1 (door forced closed) f 1'(h+p) f O(h+p) f Oh + Op (by the distributive prope rty) f 0 + 0 (by the nu ll elements propenyl f = 0
Therefore, no matter what the va lues of hand p, if c= 1, f wi ll eq ual O-thc door will stay closed.
EXAMPLE 2.17 Automatic sltding door with opposite polarity In Example 2. 12, we computed the function to open an automatic sliding door as: f-c'(h+p)
English 1: "F outputs 1 when a is 0 and b is 0, or when a is 0 and b IS 1:' English 2: " F outputs t when a is O. regardless of b's value."
(a)
o
I
Figure 2.28 Seven
1
I 0
representations of th e very
Truth table
F (b)
same function F(a.b): (a) nvo English descriptions, (b) two eq uations, (c) two circuils, (d) a truth table.
a~F~
/~
~~ ~ 1 1 0
I 0
(d)
56
2 Combinational Logic Design
2.6 Representations of Boolea n Functions
Equations One way to represent a Boolean function is by using an equation. An eqllatioll is a Il) . ' 'b' all) ematical statement equatll1g one ex pressIon with another. F ( a , b) = a + a ' b .' an example of an eq uation. The right-hand side of the equation is often referred to as IS expressioll . wh ich evaluates to either 0 or l. at) We've seen Il,at differe11l equations can represent the same function. The eqUa . F(a . b) = a ' b' + a ' b represents the same function as does the equation F ( a , b )tll)ll. a ' . BOlh equations pcrfonn exactly the same mapping of the input values to output values '" pick any input va lues (e.g .. a=O and b=O). and both equations map those II1put values tl) ------same output value (e.g .. a =0 and b=O would be mapped to F= 1 by either equation). One advantage of an equation as a Boolean functi on representation compared other representations is that we can easil y manipulate an equation using propertie tl) Boolean algebra, enabling us to simplify an equation. prove that twO equation s repre:eI)f the same func!lon. prove propertIes about a function, and more. I)t
th~
Circuits A second way to represent a Boolean function is using a ci rcuit of logic gates. A c;r is an interconnection of components. Because each logic gate component has a Cll;, . f ' I .' Pre defi ned mappmg a Input . va ues to output values, and because wIres Just tran smit tl)e'va lues unchanged. a cIrcuIt descnbes a function. ItWe've seen that differe11l circu its can represent the same function . The two circu its' Figure 2.28 both represent the same function F. The bOllom circuit uses fewer gates b II) the function is exactl y the same as the top circuil. ' Ut One advantage of a circuit as a Boolean function repre entation compared to Otl)er representa!lons IS that a CIrcuit may represent an actual physical implementation I)f Boolean function. and ultimatel y our goal is to implement digital circuits physical! a Another advantage IS that a CIrcuit drawn graphically can enable quick and easy corn y. hension of a function by humans. pre_
Truth Table A th ird way to represent a Boolean function is usin o a trllth table. A truth table's left side lists the input variabl es, and shows all possible valli e cOlllbillatiolls oj th ose illPlIts, with
Inputs a b
o o
Output F
0
one row per combination, as shown in Figure 2.29. A truth 1 o table's ri ght side wou ld then li st the function 's output va lue (l or 0) for the row's particul ar co mbination of input values, as was shown in Figure 2.28(d). Any function of two variabl es figure 2.29 Trulh lable wi ll have those fou r input combinati ons on the left side. Mfucture for a twoPeople usuall y list the inpu t combinations in order of input funclion Fen.b), increasing binary val ue (00=0,01= 1,10=2,11 =3), as we've done above, though strictl y speaking. we could list the combi nations in any order as long as we li sted all possible combi nations. For any comb ination of input va l ue~ (e.g., a-O, b-O). we merely need to look at Ihe corre, ponding vaJue in
_
the oUlput column (i n the case of a=O b= :>7 determ1l1e the function 's output. , 0 , the OUtPUt shown in Figure 2.28(d) is 1 ) to FIgure 2.30 shows the truth tabl fu nc t'lon , and a four-input function e structure s ~or a tWO-input functi on a th . . ' ree-IOpUt a b 0
o o
1
o (aJ
F
a b c 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 (b)
Figure . 2.30 Trut h table structure for: (a) • two-Input functIOn F(. ,b). (b) • th ree-input rullCbtlon F(. ' b.c).' an d (c. ) four-input function F( . a·l,c,d)· Defining. specific function would In.vo ve fi lIing in the rightmost column for F wuh • 0 or a I for each row.
F
a b c d 0 0 0 0 0 0 0 0
F
0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1
1
1
0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1
(e)
. . Truth tables are not only found in d~gllal deSIgn. If you've studied basic
Gene
pair
Outcome
M o bIOlogy, you've likely seen a type of truth F blue blue blue table describing the Outcome of various blue brown brown gene pairs. For example, the table on the brown blue brown fight shows outcomes for different eye brown brown brown color genes. Each person has two genes for eye color, one (labeled M) from the mom , one (labeled 0) from the dad. Assumin o ani . bl ue and bro wn the table lists all ·bl" .y two poSSIble values for each "ene POSSI e combmati f " ' , person may have. For each combinau' th b . ons a eye color gene pairs that a 0 an. e ta Ie h ts the t as two blue eye genes will they h bl au come. . nly when a person h . ave ue eyes' hav' 0 results In brown eyes (due to th b . . m" one or two brown eye 2cn . e rown eye gene bemo d . - Unhke eq uations and circuits a Boolea "ommant over the blue eye gene.) representation . , n functIOn has ani 0111' truth table
One advantage of a truth table as a Boolean funetio . other representations is the fact that a f unctIon . h representauon compared to as only onen truth bl ' we can conven any other Boolean f ' . ta e representanon. so .,.. uncnon representatIOn t th bl ' a tru ta e to determine if d.Illerent . representations represent th e same f un lion-if th tlon. theIr truth tables will be identical T th bl C) rep,re :nt the same fun.:readers, as a truth table clearly h tho ru ta e are also quite mtuiti\'e to human ow e output for el'e 'bl ' that we 1I ed truth tab les in Figure 8 t d ' be . . f) .p."' I e mpul. Thu '. n'ti, basic logic gates. - . a esen 111 an IIltulme manner the beha\ior l f
58
Combinational Logic Design
2.6 Representations of Boolean Functions
ber of inpuls the number of truth A drawback of Irul h tables is Ihal fo r a Iarge num ' h b f input tabl e rows can be ex trem e))1 laroe. Given a function with It inputs, t e n~11l ~r 0 " . Id h 2 10 - 1024 pOSSIble IIlpUI comcombinations is 2". A funcl ion wilh 10 mputs wou ave -. f . . . I ble havlllg 1024 rows A unction binali ons-you can' l easily sec much of anythmg m a a . with 16 inpuls would have 65 .536 rowS in ils trulh lable.
EXAMPLE 2.18
Captu ring a function as a truth ta ble TABLE 2.2
Create a truth tab le describing a funct ion th at detects wh~ther a three-bit input 'S' v
Truth table for
5-or-greater fun ction.
a 0 a a a 1 1 1 1
b 0 a 1 1 a 0 1 1
C
a 1 a 1 a 1 a 1
F a a a 0 a 1 1 1
greater. Table 2.2 shows a trulh table for the funclion. We first list all possible combinations of Ihe three Inpul bitS, whIch III
all
remaining rows.
Given Ihe above representat ions, we can view combina~1, tional logic design as defining Ihe appropriate Boolean Equa1ions ' - - 2 / ~IS funcli on 10 solve a parlicu lar problem, and then creaLing a ci rcui l representalion of Ihal function. Defining the appropriale Boolean funClion requires nOl only thaI we Ihink aboul what Lhal function should be, bUI also ' - Trulh lables -"" Ih at we capl ure Ihal function in some form-Iypically eithe r as an equal ion or a trulh table. Then , we musl Figure 2.31 Possible conversions conven Ihe caplured funclion representation inlo a cir- from one Boolean fu nction cuit. Thus, combinalional logic design requires Ihal we represen tation to another. know how 10 conven from one Boolean funclion represemation 10 another. For Ihe three representations we have di scussed so far (equalions, circuils, and truth lables), there are six possible conversion from one represenlation 10 another, which we now describe (Figure 2.3 I).
( ----4
3)
6)
(
5
I. Equations to circuits Co nverting an equation 10 a circ uil can be done slraighlforwardl y by using an AND gale for every A D operator. an OR gale for every OR operalor, and a NOT gale for every NOT operalOr. We already gave several examples of such conversion. in Secti on 2.4.
2. C ircuits to eq uations Conven ing a circuil inlo an equation can be done by slaning from Ihe circuils inpuls. and then wriling the OUIPUI of each gate as an expression invol ving Ihe gale's inpuls, The ex pres ion of Ihe lasl gale before the OUlpUt represents the expression for Ihe circuil's
.
Figure 2.32 Converting a circuit 1O
an equation.
Q
we' ve labeled a. b. and C. We then enter a 1 in the outpu~ row
if the inputs represent 5. 6. or 7 in binary. We enter as
Converting among Boolean Function Representations
..
funcli on Fo h . ' . r exa mple, suppose we are given [ e CIfCUIl In Figure 2.32. To convert to an equall on,. we Slart wilh Ihe inverter, whose OUIPUI wI ll represen l C ' . We continue wilh Ihe OR gale-nOle Ihat we can'l delermine Ihe OUIPUI for Ihe AND gale yel umil we creale expr,essions for all Ihat gale's inpulS. The OR gale s OUIPUI represents h+p . Finally. we wrile Ihe ompul of Ihe AND as C ' ( h+p) . Thus, Ihe equallon F ( C . h , p) C' ( h+p ) repre ents Ihe same funclion a Ihe circuit.
-_. _---
3. Equations to truth lables o Convertin . " an equat'ton 10 a Iruth lable can be done by fi rsl creallng a Irulh lable struclure appropriale for the number of . bl . funcll on InpUI . vana es. and then evaluallng the riahl-hand SIde of Ihe equali on for each combination of inpul values. For example, 10 conven Ihe eq uation F ( a , b) = a' b' + a ' b 10 a truth lable, we would firsl creale Ihe truth lable structure for a IWO-InPUI funclion , as shown in Figure 2.30(a). We would then eva luate the righI-hand side of the equation for each row's comblnallOn of inpul va lues, as follows:
.
a=O and b=O, F
0' *0 ' + 0' *0 0 ' *1 ' + 0 ' *1 1' *0 ' + 1 ' *0 1 ' * 1 ' + 1 ' *1
a= O and b=1, F a =1 and b=O , F a =1 and b=1. F
1*1 + 1*0 1*0 + 1*1 0*1 + 0* 0 0~1
0*0 +
Inputs
Output F
o a
0 1
1
o
0
o Figure 2.33 Truth table for F(a.b)=a'b'+ab. + 0 0 + 1
1
0
0
0
0 + 0
0
We would Ihere fore fi ll in Ihe lable' righl column as shown in Figure 2.33. NOle thaI we applied propenies of Boolean algebra (mostly the identity pro~ny and null elemems propenYl 10 evaluale Ihe equations. Notice Ihal convening the equation F ( a . b ) =a ' 10 a truth lable re ults in exa t1v the same truth lable as shown in Figure 2.33, [n particular. evaluating the right-hand ide of the equatIOn for each row 's combinalion of inpul values yields: a =O and b=O, F a=O and b=1. F
0' :
0'
1
a= 1 and b=O. F = 1 ' 0 a = 1 and b= 1. F 1' = 0
Inputs a b 0 0
Output F
a' b'
a' b
0
1
0
1
1
0 0 0
1
1
1 0 0 0 1 1 Some people find il use ful 10 creale inter0 0 mediate columns in the lruth lable 10 compule Ihe eq uat ion's inlermediate value. Ihus filling Figure 2.34 Truth ubi. for Fla.b)=ab - , ~ with intemledinte lumn ~ eac h column of Ihe lable from lefl 10 righl. moving 10 the neXI column only after filling all ro\\S of the ' umm lliumn. An e:l.:lmpl for Ihe equallon F ( a . b ) - a' b' + a ' b is h \\ n in Figure ~ .3 ~ .
I
59
60
Combinational Logic Design
4. T ruth tables to equations To conve rt a truth table to nil equation. we cre:.l (C a product lenn for cach 1 in the outpu t column. a nd we Ihe n OR a ll the product terms. For the table on the ri ght (Figure 2.35). we get the terrns shown in Ihe ri glllll10st column of lhat tab le. ORing those terms yields F = a ' b ' + a ' b.
5. C ircuits to truth tables
2.6 Aepresentations of Boolean Functions Inputs b
0 0
Outputs
Term
F
F - s um of a' b' a' b
0 1
1
0
0 0
P • a 'b' c + a ' be ' + ab ' e ' + abe We could Ihen d ' h - . cSlgn 1 C Circuit using four A 0 gales and an
OR gate.
Note that even p ' d . h amy OC5n t Illean for Sure that {he data is correct ( note 1 at we were c'lref J I . was "assumed" (0 b . <, U 0 say earlier that the transmission two errOrs OCc e c?rrecI If I~C parity was correct), In particular. if For e . I ur On dlffere nl blls. Ihen Lhe parity will sLill be even . . xamp e, the sender may se d Oli 0 1111 1111 . ' . n . but Ihe receIve r may receive · . has even pari ty and thus looks correct. More powerful error detecl lon meth ods 'bl nrc POSSI c to detect multiple errors like this b . one, ut al the price of add ing ex tra bi ts.
Figure 2.35 Converting a truth table to 3n equatio n.
W e can convert a combi nnLional circuit to a truth
,
tabl e by firsl conve rtin g Ihe c ircu it to an eq uation (described earlier). a nd Lhe n converttng the equation 10 a lruth tab le (descri bed earl ier).
Parity generator circuit design sta rting from a truth table Nothing is perfect, and digital ci rcuits are no exception. Some ti mes a bit on a wire c ha"g~s when it's not supposed to. So a 1 becomes a O. or a 0 becomes a 1. For example. a 0 may be travehng along a wire. when suddenly some electrical noise comes out of nowhere and chang.es the
For
tllIJ
exllmple,
Harling/rom a
wble IS II more natural IfUl/J
{'/J oice t/Jall (III t!qUUfIfHl,
a 10 n. 1. While we
can redu ce the like lihood of such crrors. perhaps by usi ng we ll -insulated wires. we can"t completely preven t such errors. nor ca n we de lec t nod correc t all of th em- but we can de lcct some of them. Designers typicall y look for situat ions where errors are likely to occur, such as data being Lransmitted between two chips over long wires-like from u compu ter over a printer cable to a printer, or from a computer over a telephone line to anoLher computer. For those silUJ tions. designers add circuits that at least tfY to detect that an error has occurred. in which case the recei vi ng circuit can ask the sending circui t to resend the data. One common method of detec tin g an error is called parity. Say we ha ve 7 data bi ts to transmit. We add an extra bit. ca lled Ihe parity bi!. to make 8 bits tala I. TIle sender sets the parity bit to a 1 if Lhat wo uld make Ihe lotal number of 1s even-thai's called evell parity. For example. if the 7 data bils we re 0000001. then the parity bil would be 1. making the 10 101 number of Is eq ual to 2 (an even number). The complete 8 bi ls wou ld be 00000011. If Ihe 7 data bits were 1011111, then the parity bit would be O. making Lhe total number of Is eq ual 10 6 (a n even num ber). The complete 8 bi lS would be 10111110. The receive r now can detec t if a bit has changed du ring transmission by checki ng lhat there's an even number of 1s in the 8 bits received. If even, the transmission is assumed correct. If not even, an error occurred durin g tra nsmission. For example. if the rece iver receives 0000 0011. the trans mission is assu med 10 be correct, and the parity bit can be di scarded. leavi ng 000 0001. Suppose instead Ihat an error occurred and the receiver receives 10000011. Seei ng the odd num ber of 1 s, the receiver knows th at an error occurred- note that the receiver docs tlot know which bil i, erroneous. Likewise, 000000 I 0 would represenl an error 100. NO lice in this case that the error occurred in the parity bit. but the receive r doesn' t know where the error occurred. Let's describe a fun ction Ihat ge nemles an even paril y bit P for 3 dal" bit> a, b. and e . Staning from an equation is hard-what's the equation? For Ihis example. sian ing with a truLh lable is the natural choice. a, , hown in Table 2.3. For cach configuration of dOIa bil' (i.e .. for each row in the Lruth lable). we 'et the parily bilto make Ihe lOla I num ber of 1, eVCl1. From Ihe (ruth tub lc. we then obtain the followi ng equati n for the pari ly bi!:
TABLE 2.3 Even parity for 3-bit data.
o o o o
b
e
p
o o
o
o
o o
o
o o
o o o
Odd parity is also a common ki nd of parily-the parity bit value rna kes the lotal numb I' 1 od b . er a s d. There's no quality difference etween even parrly and odd parity- the key is simply Lhat the sender and receiver must both lise lhe same kind of parity. even or odd. A popular rcpresenlalion of lellers and num bers is known as ASCII which encodes each character Into 7 blls. ASCII adds 1 bi t for parity. for a tOlal of 8 bils pcr ch~cter.
6. Truth tables to circuits . We can convert a truth tab le 10 a c ircuit by first convertin g Ihe trut h tab le to an equatton (desc ribed earli er). and then convening the equation 10 a circ uit (described earlier).
EXAMPLE 2.19
61
EXAMPLE 2.20
Converting a combinational circuit to a tru th table Conven the circuil depicted in Figure 2.36(a) inlo a truth table. .
We beglll by convenin g the circ ui t 10 an equation. Starting from the gales closest (0 the AND gale and the invener in thi case-we labe l each aate's output as an express Ion of Ihe gate's inputs. We label Ihe leflmost AND gate' outpu t. for ex:mple. as a b. likeWIse,. we label .the leftmost inve ner's Output as C •. Continu ing through the circuit's oates. we label the nghlmosl Inverter' ( b) ' _ . e ( ) s OUlput as a . Frnally. we label the nghtmo t D .ate's OUtpUl as a b ' c ' . which corresponds 10 the Boolean equation for F. The full y labeled ci';;uit is hown in FIgu re 2.36(b).
IOPuts~the leftmost
.
From the Boolean equation. we can now construct the truth table for the combinational circWL
~lIlce our circuit has three in pu ts-a, b. and C-there are 23 = possible combinations of inputs (I.e. abe~OOO. 001. 010. 011. 100. 101. 110. 111). so our truth table has the ei.ht rows ~hown in Figure 2.37. For each input. we compute the value of F and fill in the correspondim! com
i
the lruth lab le. For example. when a ~O . b~O. and e=O. F is (00) • ~O' - (0)' ~ 1 : I ~ 1~ We con~pute the circuit's output for the remaining combinations of input using a truth table with IIllcrmedmlc values. shown in Figure 2.37. In
=,
F
F
Figure 2.36 (a) Combinalional ireu il. and (b) cireuit
\I
it h gates' output c' prc:"on, lJt-ckd.
62
2 Combinational Logic De Sign
2.6 Representations of Boolean Functions Outputs
Inputs
a
b 0 0
e 0
1 1
0
1 1
0 0
0
1
1
0
1
1
1
0 0 0 0
1 1
1
(ab)'
1
F 1
0
0
c'
ab 0 0 0 0 0 0
1 1 1 1 1 1
1
1
0
1 1
0 0
0
0 0 0
1
1
0
0
1
Figu re 2 37 TrUlh table ror the circu it 's equation
Standard Representation and Canonical Form Truth tables as a Boolean function standard representation We stated ea rli er that . although there are many possible equation representations and circu it represem3tions of the same Boolean function. there is only one pos ible truth table representation of a Boolean function . Truth tables therefore represent a standard representation of a function-for any func tion, there may be many poss ible equations, and many possible circuits, but there is only one truth table. The truth tabl e representation is unique. One use of a standard representation of a Boolean fu nction is for comparing two function s to see if they are equivalent. Suppose you wanted to check if two Boolean equation s were eq ui va lent. One way wou ld be to try to manipulate one equati on to be the same as th e ot her equation. like we did in our automatic sliding door example in Example 2. 13. But suppose we were not successful in gelling them to be the sa me- is that because they really arc not the same, or because we just didn't manipul ate the equation enough? How do we really know the two equations are not the same? A conclusive way to check if two fu nctions are the same is to create a truth F = a'b'+ F=ab+a ' table for each. and then check whether the a' b + ab truth tables are identical. So to determine a b F b F whether F = a b + a ' is eq uivalent to F 1 o o 1 o o = a ' b ' + a ' b + a b. we could geno 1 1 1 erate truth tables for each, using the o o o method described earlier of evaluating the function for eac h output row, as shown to the right. We see that the two functi ons are indeed equivalent, because the outputs are F = (a+b) , identical for each input combinati on. Now let's check if F = ab + a ' is equi valent b b F F a to F = (a+b) ' by comparing truth tables. o o o o As seen to the right, those two func1 o 1 1 o o o tions are clearly not equ ivalent. Comparing o o truth tables leaves no doubt.
63
While compari ng truth tables works fine when a function has only? inputs wh t 'f 10 32? , a J a functton has 5 ' . tnputs, or . ,or . . Creating truth tables becomes increasingly cumber;?'~' and tn many cases Just pl atn unrealistic, since a truth table' number of rows equals , here n tS the number of tnpulS. 2" grows very quickly. 232 is approximately 4 billion for example. We can't reali stically expect to compare 2 tables of 4 billion rows each. . However, 111 many cases, the number of output Is in a truth table may be very small cOmpared to the number of output Os. For example. consider a function G of 5 variables a b, c, d, and e : G = a bcd + a ' bc de. A truth table forth is fu nction would have 32 rows' but .only three Is in the output column-one 1 from a ' bcde, and two 1 from abed (which covers rows corresponding to a bcd e and a bcde '). This lead to the question : Is there a more compact but still standard representation of a Boolean function ?
Canonical Form-Sum-of-Minterms Equation The answer to the above. question is "yes". The key is to create a tandard representation that only deSCribes the situations where the function outputs 1. with the other situations assumed to output O.A n equation, s uch as G = abcd + a ' bcde. is indeed a repre entatIOn that only deSCribes the Slluatl ons where G is 1, but that representation is not unique. that IS, the representation is not tandard . We therefore want to define a standard form of a Boolean equation, known a a cal/ol/ical Jorm . You've seen canonical forms in regular algebra. For example, the canonical form of a 2 polynomlal ofdegree twoi s:a x 2 + bx + c. Tocheck if the equation 9x 2 + 3x + 1 is equivalent to the equation 3 * (3x 2 + 1 + x), we conven each to canonic,a1 form , resulting in 9x 2 + 3x + 3 for both equation. One canonical form for a Boolean function i known as a um-of-minterrns. A mil/term of a function is a product term whose literals include every variable of the funclion eraclly ollce. in either true or complemented form. The function F (a . b . e l = a' bc + abc ' + ab + c has four terms. The firs t two terms, a' be and abc ' . are minterrns. The third term, a b. is not a minterm since c does not appear. Likewise. the fourth term. C. is not a min term, since neither a nor b appears in that term. An equation i in sum-oJ-minterms Jorm if the equation is in sum-of-product form. and every product term i a mimerm. Convening any equ ation to sum-of-minterms canonical form can be done follo\\i n!! just a few steps: T
l. First, we manipulate the eq uation until il i
III um-of-product form . uppo ewe are given the equation F( a . b . e) =( a+b)(a '+ aclb. We manipulate it as follows:
F = (a +b )( a '+a c) b
F = ( a+b )(a 'b+ac b l F = a ( a ' b+a c b ) + b( a' b+acb) F = aa ' b + aa cb + ba' b + ba cb
F = O*b + a c b + a ' b + acb F = acb + a'b + acb F = a c b + a' b
(b. the di triburiYe propenYl (distributive property) (distributi"e propel'!) ) (complement. commUl3ti\e. idempotent) (null elements) (idempotent)
64
Combinational Logic Design 2.6 Representations of Boolean Functions 2. Second, we expand each tenn until every term is a minterm:
F F F
aeb + a'b aeb + a ' b* l aeb + a'b* (e+e ' ) a e b + a ' be + a 'b e '
(identity)
H - a ' bede + abede ' + abede
(complement) (d istributive)
is the sum of the minterms 15,30, and 31 , which can be com pactly written as:
H
3. (Optional step) For neatness, we can arrange the literals within each te~m to a con-
sistent order (say alphabetical), and we can also arrange the terms they would appear in a truth table:
F
~
In
the order
a ' be ' + a ' be + abc
The equation is now in sum-of-minterms form . The equation is in sum-of-products form, and every product term includes every variable exactly once. An alternati ve canonical form is known as product-of-maxterms. A max/erm is a sum term in which every variable appears exactly once in either true or complemented form. such as (a + b + e ') for a function of three variables a, b, and e. An equation is in produc/-of-maxterms form if the equation is the product of sum terms, and every sum term is a maxteml. An example of a function (different from that above) in productof-maxterms form i J ( a . b, c) ~ (a + b + e') ( a ' + b ' + e ' ). To avoid confusing the reader. we will not discuss the product-of-maxterms form further here, as sum-of-minterms form is more common in practice, and suffi cient for our purposes.
~
Multip le-Output Combinational Circuits Many combinationa l circuits not only invol ve more than one input. but also involve more than one output. The simplest approach to handling a multiple-output circuit is to treat each output separately. leading to a separate circuit for each output. Actually, the circuits need not be completely separate-they could share common gates. We'lI show how to handle multiple-output circuits through examples.
EXAMPLE 2.22 Two-output combinational circ uit Design a circuit to implerncnllhe rollowing two equations of three inputs a. b. and c:
Comparing two functions using canonical form
G
Suppose we wanllo delenmine whelher Ihe fun ctions G( a , b, e , d . e) ~ abed + a' bede and H(a,b.e . d . e) = abede + abede' + a ' bede + a ' bede(a ' + e) are eq uivalent. We
=
ab + e ' ab + be
We can design the circuit by simply creating Iwo separate circ ui ts. as in Figure 2.38(a).
first com'cn G to sum-of-minterms form :
G G G G-
1:m(l5 , 30 , 31)
The summation symbol means the sum , and then the numbers insi de the parentheses represent the minterms being summed on the right side of the equation.
F EXAMPLE 2.21
65
corresponds to 1111 0, or 30; and a be d e corresponds to lIllI, or 3 I. Thu . we can say that the function H represented by the equation:
a
abed + a ' bede abed( e+e') + a ' bede abede + abede ' + a ' bede a ' bede + abede ' + abede
b
F
F
We then conven H to sum-of-m imerms form:
H H H H H
abede + abede ' + a'bede + a'bede (a ' + e) abede + abede ' + a ' bede + a'bedea ' + a 'b edee abede + abede ' + a 'b ede + a ' bede + a ' bede abede + abede ' + a' bede a ' bede + abe de ' + abede
G
(b) (a)
Clearly, Gand Hare equivalent.
Figure 2.38 Multiple-output circuit: (a) trealed as two separale circuits. :lIld (b) \\ ith gale sharing.
NOle thai checking Ihe equivalence using truth tables would have resulted in 2 rather large tru lh lables having 32 rows each . Using sum of mintenms was probably more appropriale here.
We can instead notice thai the lenn a b is common to both equations. ThUs. the
£\\ 0
circuits an
share Ihe gate thai compules a b. as shown in Figure _.3S(b). Compact sum-of-minterms representation A more compac~ represent~tion of sum-of-minterms form involves listing each minterrn as a number, ~Ilh each mtnterm 's number determined from the binary representation of Its vanables values. For example, a' bede corresponds to 01111. or 15 ; abede '
EXAMPLE 2.23
Binary number to seven-segment display converter 1nny electronic appliances display
3
number for us
10
read. E.ample applian< - indud: a d
mi~ro\Vave oven. and a telephone answering ma hine. A \ cry ~pul~ and simple dC\I:-e tor dl~r tJ.~. ing a single digit number is a se"en-segment display. illustraled III FIgure 2.39.
66
.-, , ,", ,,: '..'
Combinational Logic Desig n a f -----, b 9 e -----, e - - - -_ d ------,
abedefg =
1111110
(0)
2.7 Combinationa l Logic Design Proc ess
We can create a Custo m logic ci rcuit to implement th e converter. Note that the above table is in
the fonn of a truth table hav ing multiple outpu ts (a th rough g). We can treat each output separatel y. so ~e deSign a circuit for a . then for b, elc. Looking al the Is in the a column. we obtain the fol -
lOWing equation for a:
a - w' x ' Y' Z' + w' x ' yz ' + w' x ' yz + w' xy ' z + w' xyz ' w' xyz + wx ' y ' z ' + wx ' y ' z
1101101
0110000
The displ ay consists of seven light seg ments. each of which can be illu minated independently of the others. We can display the desired di git by sell ing the signals a , b . c , d . e: f , and 9 appropriately. So to display the di git 8, we set all seven signals to 1. To display the di git 1, we set b and C 10 1. A useful combi national circu it is one thai converts a binary number to the seven-segment display signal s a- g thm display the number as a deci mal digil. We need fo ur bi ~s . say w, x, y, ~d z. to represent the binary values of the ten possible di gits 0 to 9. Table 2.4 deSCri bes the conversion of cach binary nu mbe r to the seven-segment display's signals. We decided to ac tivate no segments for the nu mbers 10 through 15. Fo r rhis t·xwnple. starting f rom a table is a mo re natural choice {han all eqllarion.
TABLE 2-4
4-bit biDary number to seven-segment dis pl av truth table
w
x
y
z
a
b
c
d
e
f
9
a a a a a a a a
a
a
1
1
1
1
1
1
0
a a
1
0
1
1
0
a
a
a a
0
1
0
1
1
a
1
1
0
1
0
1
1
1
1
1
1
0
a
1
1
a a
0
a
1
1
a
1
1
1
1
1
a
1
1
1
1
1
I
1
1
I
a a
0
1
1
I
1
1
1
I
a
0
0
0
0
1
1
1
0
1
1
1
1
I
I
1
0
a a
0
1
1
1
1
I
1
0
1
1
1
0
1
0
0
1
0
1
1
1
I
a
a a a a a a
a a a a
a a a
0
0
0
a
a a a a a a
a a a a a a
a a a a a a
1
1
a a
1
1
1
a
1
1
1
1
1
0 0
a a 0
0
+
Looking at the 1s in the b column, we obtain the following eq uation for b:
(c)
(b)
b - w' x ' y ' z ' + w' x ' y ' z + w' x ' yz ' + w' x ' yz + W' xy ' z ' + w' xyz + wX ' y ' z ' + wx ' y ' z
Figure 2.39 Seven-segment display: (3) connections of inpu ts 10 segments. (b) input values for numbers O. I. ::md 2. ~nd (c) a pni r of real seven-segment display components.
Inlll!
67
.-.'-'
We could then proceed to create equ ations for lhe remaining outputs C through g. Finally. we would create a circuit for a hav ing 8 4-inpul AN D ga tes and an 8-input OR gale, another circuit for b hav ing 8 4-input AND gates and an 8-i nput OR ga te. and so on for C throu gh g. We coulci of Co urse, have minimi zed the logic for each equ::uion before cremi ng each of the circuits. You may notice th at the equat ions for a and b have several terms in common. For exam ple. the term w' x ' y ' Z ' appears in both eq uations. So it would make sense fo r both outpu ts to share one AND gate ge nerating th at term . Looking al the trul h table. we see that the tenn w' X ' Y , z ' is in fact needed for outp uts a, b, C, e, f, and g, and thus the one AND gate generating thaI te rm cou ld be shared by all six of th o e outputs. Likewise. each of the olher requ ired tenTIS is shared by several outputs. meaning each gate ge nerating each term could be shared among severa l outpu ts,
2.7 COMBINATIONAL LOGI C DESIGN PROCESS
• a:-. :.-.•
.'-1- .-
.:..-. :J. .:.. :.
-. -.
Based on the prev ious sections, we can define a traighrforward method for designing combi national log ic, sum mari zed in Table 2.5 TABLE 2.5
Combinational logic design process.
Step Capture the ~ f unclion 0.
N
fr
COllvert (0
equm iol/s
c;:j
Description
Create a truth table or equations. whichever is most natural for the gin~n problem. to describe the desired behavior of the combinational logic. This step is onl y necessary if you captured the function using 3 truth rable instead of equations. Create an equation for each output by ORing all the mintenns for lhat output. Simpl ify the equations if desired.
~ Implem efll as a
J5
For each out put. crente a circuit corresponding ro the outpu( equation. gate-based cireuit (Sharin g gales among multiple Outputs is OK optionally.)
Gate-based circuits designed such thaI Ihe inpul reed into a column of , that feeds into a single OR gale are known as two-iel'eilog;c impiemenlariollS.
glHl!S
EXAMPLE 2.24 Three 1s pattern detector We want 10 implemelll a circuit th at cnn detec t whether :1 pattern of at least thret' adJ3~nt h IJxur anywhere in an 8-bit input. and that outputs a 1 illthut case. The inputs are a . b. c . d. e. f. g. JnJ ".
68
Combinational Logic Design
2.7 Combinational Logic DeSign Process
_ 000 III aI y should be !. si nce there are three and the output is y. So for an input of a bc de f~th;; 10 I aI aII: the output should be a,. since th~re Is 111 a row (on IIl puts d. e . and f J. For an IIlp III I 0000 should res ult in y = !. Slllce havlllg are not three Is in a row anywhere. An Input of h . uil is an ex treme ly simple example of I '11 tput a I Sue a wc Id h •. p . de tectors arc widely used, for exarnp e, more than three I s in a row S Oll 511 Oll . . k lIem delcclOrs altern d a general class of CirCUits ' nown as pOl . k ' a digi ti zed video image. or to elect in image processing to detect things. like humans or tan ' 5, In specific spoke n words in a digitized audio stream. . . For this example. stoning f rom an
Step I:
eqllMiml is a lIIo re
naruml choice fholl a lrutf, toble.
Step I:
Capture the funclion. Capturing the function for this example is most naturally aChieved usi ng a truth table. We list al l the possible input combinations, and the desired output nu mber, as in Table 2.6. TABLE 2.6 Truth table for number-of-ls counter. Inputs
re the functi on as a rathe r large truth table, listing . Capillre Ihe JII"cllO". We could captu . 1 'or y in eac h row where at least .. f . ts and entenng a ., , out all 256 combmnllons 0 I,"PU . od for ea turing this particu lar function is to th ree I s occur. However. a slmple~ melh currence:of three Is in a row. One possibility create an equation th at lists thepoSSlble oc =111 Likewise, if cde =11!. def=lll, is that of a bc= 11 J. Anot her IS that of bcd I h possibi lity the values of the , fd e f g= 1J1 orfgh=1 11 we should output a . or eac . ' , . S 'f a bc= III we output a I. regardless of the values 0 , other In puts don I mailer. 0 1 .. ' .' . e . f, g, and h. Thus. an equ ati on desc nbmg y IS simply.
F
y
=
Convert to equations. We can skip this step since we already have an equation.
Step 3:
. . No simp . I'fi Implem ellt as a gate-based CIrcUli. I ea t"Jon of the equation is possible. The
(# of l s)
Outputs
b
c
0
0
0
( 0)
0
0
( I)
0
0
(])
0
0 0
a bc + bc d + cde + def + efg + fgh
Step 2:
69
1
1
( 2)
0
0
(I )
y
z
0
0
0 0
0
1
(2)
0
1
0
(2)
0
(3 )
1
resulting circ uit is shown in Figure 2.40.
Step 2:
Convert to equations. We create eq uations for each
OUrpUI
as follows:
y - a'bc + ab'c + abc ' + abc l - a'b ' c + a'bc ' + ab'c' + ab c We can simpli fy the first eq uation algebraically: y
Step 3:
g--_1-1
Figure 2.4ll Three Is pattern detector.
=
a'bc + ab ' c + ab (c ' + c) = a'b c + ab' c + ab
Implement as a gate-based circuit. We then create the final circuits for the two outputs. as shown in Figure 2.41.
a b
a b c
g c
EXAMPLE 2.25 Fo r fh is e;wmple.
starring fro m a I fll l h wb/t! is a more natural cho ice Ihon an
equation.
Num be ~o~l s coun~r
a
b
We want to design a circuit that counts the number of Is present on 3 inputs a. b. c. and outputs that number in bi nary using 2 outpu ts, y and l. An input of 110 has two I s. so our circu it should output 10. The number of I s on 3 inpu ts can range from ato 3. so a 2-bit output is suffi cient. since 2 bit can represent 0 to 3. A nu mber-of- Is COunter circuit is useful in a varie ty of situations. such as detecting the density of electronic particles hitting a collection of sensors by countin g how many sensors are ac tivated. As another example, there are airpon parking lots th at have sensors above each parking spot, coupled with signs that inform drivers of the number of avai lab le parking spots on a panicular level of a multilevel parking Structure (by cou nting the number of zeros, but th ut's the same as counting the num ber of ls with all inputs first complemented).
c Figure 2.41 Number-of-ls counter gate-based circuit.
Simplifying circuit nolations
.
We u ed a couple of new simpli fying nOlations in our circuits in ~e pre.n u~ ex~ple. One simplifying nOla lion is to lisl the inputs multiple times. to a,·o.d hanog ltn~S tn OUT drawi ng crossing one anolher-an inpul lisled multiple times is - umed to ha,e been branched from the same input.
70
Combinationa l Logic Design
2.7 Combi national Logic Design Process Another s implify ing nolttli on is Ihe use o f a n inversio n bubble at th e inpul o f a g al e. ra th er th a n the use of a NOT ga te. An tnpUI th:ll is inverted in to many gates is ass umed 10 feed throu gh a s ing le inve n er th at is then
~ SLOW DOWN! THE QWERTY KEYBOARD
branched ; ut to those gates. An alternative simplifi ca ti o n is to simpl y .include co mp lem e tHed va ria bles. like b ' . as tnputs. EXAMPLE 2.26
12-button keypad to 4-bit code co nve rte r Yo u've pro bably seen 12-bullon keypads in many
Fo r t"is example. starling Jrom equatio ns is a mOre natural c" oice I" {UI a Irwh table. although lI 'e used all inJo rmol table (1101 a lruth table) 10 help LIS dete nnille the equations.
TABLE 2.7
diffe rent places. like on n telephone or at an ATM mnchi nc as shown in Figu re 2.42. The first row has _r1 bUllons I. 2. and 3. th e second row has 4. 5. and 6. Ihe third row has 7. 8. and 9. 3nd th e las l row has *, O. and #. The ou tputs of such a keypad consist of _r2 seven signals-one fo r ench of the fo ur rows (r 1. r 2 . r 3 . and r 4). and one fo r eac h of the three col_<3 um ns (c l. c2, and c3). Pushing a part icul ar button causes exactly two outpu ts 10 become 1. correspond ing to the row and co lumn of Ihal button. So pushing butto n ''1'' causes r I : I and C I: I. while pushin g bUllan " #" ca uses r4 :: 1 and c3=1. \Ve c1 c2 c3 wa nt to design a circuil th nt co nve rts the seven signa ls frolll (he keyp.:ld illla a 4-bit binary number Figure 2.42 12- bullon keypad. 'v-I XY Z indi cat ing whic h bU lton is pressed. We wa nl buttons "0" to "9" to be coded as 0000 th rough 100 I (0 th rough 9 in binary), res pectively. Let's encode butt on " . .. as 1010. # as lOll. and let's let III I mea n that no button is pressed. Let's ass ume for now lhat only "one" bu tton can ever be pressed at a given time. \Ve could capture the functi ons forw, X. y, and Z using a truth lab Ie. with the seven inputs on the left side of the tab le. and the fou r outputs on the ri ght side. but that table would have 2' = 128 rows, and most of Lhose rows wou ld correspond merely to multi ple bunons bei ng pressed. Le t's try instead to capture the functio ns using eq uat ions. The infonn al Table 2.7 mi ght he lp us ge t tarted.
Inside a standard computer keyboard is a small microprocessor and a ROM . The microprocessor delec ts which key is being pressed. looks up th e 8-bit code for that key (muc h like the 12-button keypad in Exa mpl e 2.26) fro m th e ROM . an d send s th at code to the computer. There's an intercstin g story behind the way th e keys are arranged in a standard PC keyboard , whi ch is known as a QWERTY key board beca use th ose are th e keys that beg in th e top left row o f lette rs. The QWERTY arrangement was made in th e era of typewriters (s hown in the picture below), whi ch, in case yo u have n' t seen one, had each key conn ected to an arm th ai woul d swi ng up and press in k ribbo n an agai nSI paper.
Keys cOllnected to arms
Signals
w
I
rl
cl
0
2
rl
c2
3
rl
c3
0 0
4
r2
cl
0
Bullon
y
0
0
r3
c2
0
0
0
0
9
r3
c3
0
0
I
r4
cl
0
0
r4
c2
0 0
I
0
0
a
r4
c3
5
r2
c2
0
I
II
6
r2
c3
0
0
( no ne )
7
r3
cl
0
' '--'---
0
r 2c l + r 2c2 + r2 c3 + r3cl + rl ' r2 ' r3 ' r4 ' cl ' c2 ' c3 ' rlc2 + r l c3 + r 2c3 + r 3cl + r 4cl + r 4 c3 + rl'r 2 'r 3 ' r4 ' c l' c2 ' c3 ' : r lc l + rl c3 + r2c2 + r3cl + r3c3 + r4c3 rl' r2 'r 3 ' r4' c l' c2 ' c3 '
Y
8
0
r 3c2 + r3c 3 + r4 c l + r4 c3 + rl ' r2 ' r3 ' r4 ' cl ' c2 ' c3 '
X
y
4-bit code outputs
w
>,
We could then creale a circuit ror each OUlpUt. Obviously. the h SI teml of each equation L'OUld be shared by a ll fo ur out puts. Likewise. other tenns could be shared too (like r2c31. No te that th is ci rcuit wou ld not work well if multiple bUllons can be pre~ "00 ~i muJtaneousl~ . Our circuit will outp ut ei ther a valid or inval id code in that situation. depending on \\hich bunoos we re pressed. A prererable circuit would trem multiple buttons being pres!'cd as no button being pressed, \Ve leave the desig n of that circui t as an exercise.
I
0
..
Signa ls
An annoying problem with rype:writers was that arms would often get jammed side-byside up near the paper if you typed too fastlike too many people getting jammed sideby-side while Irying 10 Arms stuck! simultaneou Iy walk through a doorway. So typewrite r keys were arranged in the QWERTY arrangeme nt 10 slow down typing by separaring common lellers. since slower typing reduced me occurre nces of jammed keys. \Vhen Pes were invented. the QWE RTY arrangement was the natural choice for PC keyboards. as people were accuslomed to that arrangeme nt. Some say the differently-arranged D\orak keyboard enables faster r) ping. but that type of keyboard isn' t very common. as people are JUSt too accustomed to the QWERTY keyboard.
Us ing this fab le. wc call derive equ rni ons for each of the fo ur OUlpUlS, as follows:
Informal table for the 12-bunon keypad to 4-bit code converter. 4-bit code outpu ts
Bulton
71
Circuit s sim ilar 10 what we des igned above exis t in computer ke~ board..!., e',,"eptlhat lh~re are a lot more rows and colu mns, EXAMPLE 2.27
Sprinkler valve co ntroller
Automatic law n sprinkler systems use a digital y ~ tem to control th~ opc:nmg. and d o'-mg of w:uc-r va lves. A sprinllcr system u~lIull) !':upports se\ernl ditTcrent zonc~, ~UCh;b the;" bal' ~.ln.i. kft 'Ide ya rd. rig ht si Ie yard. fro ll! yard, elc. Onl~ on~ zone 's \'!the can ~ o~~t."'d 3t.1 tlTlk~ In \.wdt"r tQ m~ tain enough water prcs~ure in the !t:ns e:lch \'ahc ani) nt sJ:k~\.'itic tim!?!' of the d!t~ ~Uld fo r 'J.lt.."Cltk Jut'"J two, :urp...r
72
Comb inational Logic Design
2.8 More Gates 4
( I pi ns avaihble to control the va lves. not 8 outputs as req uired all pu th Illic
th e microprocessor onl y. has ~ h 8 les We C'1O Instead program or I e
ZOI.
<
.
e . b' Th we the 3 other ins to output th e active zone (0. I, ... , 7) In mary. us,
should be opened. and u,eiollal circuit ~avi llg 4 inputs. e (the enabler) and a. b. c (Lhe bi nary value need to deSign . combln.L . 8 d7 . d6 . ...• dO (Lhe val ve controls). as shown In Figure . ) and haVing outputs 1 of th e nC ll ve zone . (.
2.43. When e: 1. the clrCUiL. shauId decode the 3-bit binary input by setting exacLl y one ou tput to .
Step I:
Capture t he fune ron I . Valve 0 should be ac ti ve when abc:OOO and Lion for dO is: dO : a ' b ' c ' e
e~l.
So Lhe equa-
d I : a ' b ' ce
dOf-- - - - - - -r'I dlf----------~
Micro-
d31-- - - - - - - " d41-- - - - - - - . . . d51-- - - - - . ,
decoder d6f-- - - - --., d7f------." Figure 2.43 Sprinkler valve controller block diagram. For this example, stoning from equations is a
The eq uati ons ror the remaining outpu ts can be
determ ined similarl y:
lable.
NAND
A NAND gale (short for "not AND") has the opposite output as an AND gate, OUtputting a
o when all inputs are 1, and outputting a 1 if any input is a O. A NAND gate has the same behavior as an AND gate followed by a NOT gate. Figure 2.45(a) illustrates a AND gate. A NOR gate (short for " nol OR") has the opposite output as an OR gaLe, OUtputting a 0 if at least one input is a 1, and outputting I if all inputs are O. A NOR gate has the same behavior as an OR gate followed by a NOT gate. Figure 2.45(b) illustrates a OR gate. We earlier warned you in Section 2.4 Lhat our CMOS transistor implementations of AND and OR gates were not realistic. Here's Why. It turns out that pMOS transistors don'l actually conduct Os very we U, but they conduct I s just fine. Likewise. nMOS transistors don ' t conduct Is well , but they conduct Os just fine. The reasons for these asy mmetries are beyond this book's scope. But the implications are that the AND and OR gates we built earlier (see Figure 2.8) are not feasi ble, since they rely on pMOS transistors to conduct Os (but pMOS conducts Os poorly) and nMOS rransistors to conduct Is (but nMOS conduc ts 1s poorly). On the other hand, if we swap power and ground in the AND and OR circuits of Fig ure 2.8, we obtai n the gates shown in Figure 2.45 (a) and (b)Those gates have the behavior of NAND and NOR gates, which makes sense since output I s become replaced by Os, and Os by 1s.
dO d2 d3 d4 d5 d6 d7
more nQlltral c hoice {han a IrIIlh
NAND & NOR
NOR
d2f-------~--_,
processor
We earlier introduced three basic logic gates: AND, OR, and NOT. Designers commonly use several other lypes of gates too: NAND, NOR, XOR, and XNOR.
G =I>-
. .sc. vaJ ve I SIlOUIdbeacLive when abc:OOl and e:l,so LheequaLionfor dl iS: LlkevJl
a ' bc'e a ' bce ab ' c ' e ab ' ce abc ' e abce
NAND
dl d2
Convert to equations. No conversion is needed since we already have equ ati ons.
Step 3:
Implement as a gate-based circuit. The circui t implementing the equations is shown in Figure 2.44. The ci rcuit we've
y 0 0 0 1 0
y 0 0 0 0
1
0
XOR
XNOR
D D-
1
0 0 0
xy 0 0 0 1 0
F
0
1 1
xy 0 0 0 1 0
0
d4
dS
designed is aCLually a commonly used component known as a decoder lVilll
ellable. We'll introduce decoders as a building block in an upcoming section.
NOR
;GF;D-F x F x F
d3
Step 2:
d6
x-cj
F
F
x---1 d7
Figure 2_44 Sprinkler valve conLrolier Circuit (actually n 3x8 decoder wi th enahle).
73
2.8 MORE GATES
(e)
Figure 2.45 Additional gates: (a) NA D. (b)
OR. (c) XOR. Cd) XNOR.
(d)
F
0 0
74
Combinational Logic Design 2.8 More Gates
We can sli ll implemenl an AND gale in CMOS. bIll we would do so by appending a NOT gale aI Ihe OlliPUI of a NAND gale (NAND fo llowed by NOT gives us AND). as shown in Figure 2. ~ 6. Likewise. we would implemen l an- OR gale by appending a NO: gale at Ihe OUIPUI of a NOR gale. BUI Ihal s ~bviouSl y slower Ihan a circuil direclly implemenled as NA ND and NOR . FOriunalely. we
F
can apply straightforward meth ods to convert any AN D/ORINOT cireuil 10 a NA D-only
Airc raft lavatory sign using a NAND gate
Figure 2.46 AND gate in CMOS .
Example 2. 15 cre~Hed a 1 i1\,~lI ory available sign using
the followi ng eq uatio n:
s•
Circuit ( a be)
,
a-<-+--; b -<~--(
Notici ng that the lenn on the ri ght side corres ponds
XNOR gates can be used to compare two data ilems for equalily. ince a 2-input )(}\:OR oUlputs a 1 only when Ihe inpu ts are bOlh a Or are both 1. For example. suppose a byte II1pUI A (a7a6a 5... aO) to your system i counting down from 99. and you want 10 sound an alarm when A has Ihe sa me va lue as a econd byte inpul B (b7b6b5 ... bO). You can detect such equality u ing eight 2-input XNOR gate . by connecting a7 and b7 to the firsl XNOR gale, a6 and b6 to Ihe second )(j OR gale. elc. Each X OR gate leUs us whether the bits in Ihal panicular pos iti on are equal. By ANDing all the XNOR OUlpUlS. we can te ll whether every pos iti on is equ al. Generating and detecting parity using XOR
circuit. or 10 a OR -only circuit. We 'll desc ribe Ihose melhods in Seclion 7.2. EXAMPLE 2.28
c -<~--(
P-- - t - S
to a NAND. we can implement the circuit using a single NAND gale. as show n in Fig ure 2.47.
Figure 2.47 Circ uit usi ng NA ND.
An XOR gate can be used to generate a parily bit for a set of dala bilS (see Example 2. 19). XORing Ihe dala bits result in a 1 if there's an odd number of 15 in the data. so XOR computes the correCI parity bit for even parity. ince Ihe XOR's output 1 would make the tOlal number of 1s even. Notice that Ihe truth table we created for generating an even parity bil in Table 2.3 does in fact represe nt a 3-bi t XOR. Likewise, an XNOR gate can be used 10 generale an odd parit) bit. XOR can also be used to detect proper pari ly. XORing the incoming data bilS along with the incoming parity bit wi ll yield 1 if the number of I s is odd. Thu . for even parity. XOR ca n be used to indicate that an error ha occurred. since the number of I s i upposed 10 be even. XNOR ca n be used to delect an error when odd parity is used.
XOR & XNOR Completeness of AND/OR/NOT, AND/NOT, OR/NOT, NAND, NOR A 2- inpul XOR gale. shorl for "exclu sive or" and pronounced as "ex or:' ou lPUIS a 1 if exact/" one of Ihe Iwo inpu ls is a 1. So if such a gale has inpuls a and b, then the output' F is 1 if a· l and b·O, or if b'l and a·O. Figure 2.45(c) illustrates an XO R gate (for si mpli city. we omit the transistor-leve l im plement at ion of an XOR gate). For XOR ga tes with 3 or more inputs, the output is 1 onl y if the num ber of input Is is odd. A 2- input XOR ga te is equ ivalenl to the fun cti o n F ab ' + a ' b.
An XNOR gale. shari fo r "exc lusive nor" and pronounced "ex nor," i simply the opposite of XOR. A 2- input X OR is equi va lent 10 F - a' b ' + abo Figure 2.45(d) illu strales an XNOR ga le. omitting the transistor-level impl ementation for imp lic ity.
Interesting Uses of These Additional Gates Detecting all as using NOR
o o o
7S
Detecting equality using XNO R
A NOR ga le can detect the situation of a data ilem eq ual 10 O. ; ince NOR outputs a 1 only when all inputs are O. For example. suppose a byte (S-b il ) inpu t to your system i counting down from 99 10 0, and when the by Ie reache O. you wi~h to ound an alarm. You can delect Ihe byte being equal to 0 by si mply connecting the 8 bit.'> of Ihe byte into an 8-input NOR gale.
It should be fairly obviou that if you have AND gate. OR gate. and NOT gates. you can implement any Boolean functi on. Th is is because a Boolean function can be represented as a sum of product . which consists only of Al D. OR. and NOT operations. What might be slightly les obviou is that if you had onl) ro and ;\OT gat"". you could still implement any Boolean fu nction. Why' Here ' a simple explanatioll--lO obtain an OR. si mpl y put NOT gates at the input and ourputs of an .~'\'O. TJtis \\Qrks because F ~ ( a ' b' ) ' ~ a" + b" (by DeMo'llan' Law) ~ a - b. Likewise. if you had on ly OR and NOT gates. you could implement any Boolean functi on. To obtain an AN D. you could si mply invert the inpuls and ourpUts of an OR. sinceF ~ ( a ' +b ' ) ' ~ a"*b " ~ a bo It follows thai if you ollh' had NAN D gates a,ailable to you. you uJd still implement any Boolean fun cti on. Why? Because we can think of a NOT gate - a I-input NA ND gate. and we an imp lement an D gate using n 1'1 , D gate follo\\ed by a 1_ input NA D gate. Since we can implemem any Boolean fun tion l"ing ;\OT and :\_'\'0. we can therefore impl emen l any Boolean fun lion u>ing just :\'A~D . :\ X ;\D gate" thus known as a 1I11i1'er sa/ gme. Li kewi e. if )OU had ~lly I OR gate. you ould implement any Bool an fun,ti,n. because we an implement a NOT gUlf a! a I-inpul NOR gate. and an R gat llio~ng l NOR fo llowing by a I-input 'OR. inc" NOT and OR C~lIl lI11plement Jny B, ,I an tun ,li on. so can OR. OR gate is thus abo I.m",n 3< a uni,e _,t/ gat
76
2 Combinational Log ic Desig n
2.9 Decoders and Muxes
Number of Possible logic Gates Having seen several diffcrent types of basic 2-input logic gales (A I D, OR , lAND, NOR, XOR. XNOR). one might wonder how many poss ible 2- inputlogic gales ex ist. That quest ion is the same as as king how many Boolean functions ex ist for two variables. To answer the
b 0 1 0
0 0
question. we firs t note th ai a two-vari-
2 choices 2 choices 2 choices 2 choices
~
'"
'"
'"
Figure 2.48 Cou nting the number of possible Boolean functions of two variJ bJ es.
0 0
0
11 0 0
12 0 0 1 0
13 0 0
14 0
1 0
15 0 1 0
0
D
'"
0
z
D
16 0
f7
D
a:
x
18
0 0 0 0
1 0
0
..:
D
a:
0
D
a:
0
z
'" '" '"
'"
Decoders A decoder is a higher-level building block commonly used in digital circuits. A decoder decodes an inputl/-bi t binary number by selling exactly one of the decoder's 2" OUtputs to 1. For example, a 2-inpu t decoder, illustrated in Figure 2.50, would have 22=4 outputs. d3. d2. d 1, dO. If the two inputs iIi 0 are 00 , dO would be 1 and the remaining outputs would be O. If iIi 0=01 , dl would be 1. If iIi 0=10, d 2 would be l.lf i 1 iO=ll, d3 would be 1. The internal design of a decoder i straightforward. Consider a 2x4 decoder. Eacb output dO, dl, d2 , and d3 is a distinct fun ction. dO should be 1 only wben i 1=0 and iO=O , so dO il'iO '. Likewise, dl=il ' iO, d 2=iliO ' , and d3 =iliO. Thus. we build the decoder with one AND gate for each OutpUl. connecting the true or complemented values of i 1 and iO ta each gate, as shown in Figure 2.50.
=
Figure 2.49 lists all 16 of those functio ns. We indicate the 6 familiar func tions in the figure. Some of the mher function s are 0, a, b, a', b', and 1. The remaini~g functions are not necessaril y common functions, but each could be usefu l for some panlcular apphcati on. Thus, we don't necessarily need to build logic gates to represent those fu nctions, but we instead wou ld build those fu nctions as a circuit of the basic logic gates. 10 0 0 0 0
Two additional components, a decoder and a multiplexer. are also commonly used as digital circuit building blocks, though they themselves can be buill from logic gates.
F
Oar 1 Oor 1 Oorl Oar I
possible functions
able functi on's truth table will have 22=4 rows. For each row. the funct ion could output one of two poss ible values (0 or 1). Thus. as illustrated in Figure 2.48. there are 2 * 2 * 2 * 2 = 2' = 16 possible functions.
b 0 1 0
dO
dO 0 iO dl 0 0 il d2 0 0 d3 0
19 110 111 112 f13 f14 f15 1 1 0 0 0 1 0 t 0 0 1 0 0 0 D
a:
~
io
'"
'"
A more general question of interest is how many Boolean fun cti ons exist for a Boolean function of N variables. We can detemline this number by first noting that an
N- vari able fun ction will have 2N rows in its truth tabl e. Then, we note lhat each row can outputNone of two possible va lues. Thus. Ihe number of possible fun ctions will be 2 • 2 • 2 *_2 times. Therefore, the total number of func tion~ is: 22N
2 '
So 16 there arc:
= 2 = 65,536
8
2 ' = 2 = 256 possible Boolean possible functions of 4 variablc~.
dO 0 iO dl 0 il d2 0 d3
function~
of 3 vuriablc." and
dl d2 d3
D
z ..: z
z x
il
iO
(b)
Figure 2.50 2x4 decoder: (a) outputs for possible input combinations. (b) internal design .
etc.
2
dO 0 dO 0 iO dl I 0 iO dl 0 il d2 0 1 il d2 d3 0 d3 0 (a)
0
0
Figure 2.49 The 16 possibfe BOOlean func tions of two variables.
2
77
2.9 DECODERS AND MUXES
The internal design of a 3x8 decoder is similar: dO =i 2 ' iI ' i 0 '. d -i 2" A decoder often co Illes with an extra inpm called el/ab/e. When enable is 1. the decoder acts normally. But when enable is O. the decoder outputs all Os-no output is a 1. The enable is useful when sometime you don't want to activate any of the outputs. Without an enable, one output of the decoder mllSf be a 1. because the decoder has an output for every possible value of lhe decoders II-bit input. We rented and used a decoder with enable in Figure ~A-I. A block diagram of a decoder with enable appears in Figure _.51.
•i ,
dO
0
iO
dl
0
10) : '
il
d2
0
11
e d3
~O
1
0
(a)
(b)
Figure 2.51 Dec."Od
outrut- O.
0
d2 - 0
78
Combinational Logic De sign . . h'ck if part (or all ) of the ,ystcm's functionWhen designing :1 partIcular system. we C c . d cod'r red uces the amount of . -. d oder USIng a e " . '11 sec in Example 2.30. ah ty could be calTled oul by a ec combinat ional logic design thaI we need to perfonll. as YOLI EXAMPLE 2.29
Basic questIons about decoders I. \Vll a! would be
AIIJWel.
2. \Vhat wou ld be a 2x~ decoder's output va lues when the inputs arc II'!
AIlSII'er:
d2-0 . d3-0.
-.
I'
dO-O. dl-0.
ne of Ihe decoder's OUlpul; 10 be 1 al Ihe f d d ' Ulputs can be 1 at a
same time ? AflSI,'er: No such input vn llles exisl. Onl y onc 0 a ceo er S 0
given lillle.
'.,
.,
·t \Vh m wo uld the input va lues of a decoder be If the output \allles.lre dO Answer. The in put vi:llues Illllst be ; 1=0. i 0= l. This question i ~
.
.
'f I.he outpuI \'alues arc dO- 1 " d 1 - 1 d2:0. d3-0? . not valid. A decoder only has Olle ou tput equ:1lto 1 at any time.
5. \Vha! wo uld the inpu t val ues of a decoder be<> AIlS11'e r;
:0 dl= l d2-0. d3-0?
I
6. How Illany outputs would:1 5-input decoder have'? Answer: 25. or 32.
EXAMPLE 2.30
New Year's Eve countdown display A New Year's Eve counldown display could make use of a decoder. The di>play may have 60 lighl
Notice that we implemented this system without having to design any gate-level combinatiOnal logic-we merely used a decoder and connected it to the appropriate inputs and outputs.
•
d2-0. d3-1. J. \Vhm in put va lues of a 2x4 decoder cause more t lan 0
Multiplexer (Mux) A multiplexer ("mu x" for short) is another higher-level building block in digital circuits. An Mx I multiplexer has M data inputs and I output, and allows only one input to pass th rough to that output. A set of additional inputs. known as select inputs, determines which input to pass thro ugh. Multiplexers are sometimes called selectors because they select one input to pass through to the ourput. A mux is like a rai lyard swi tch that connects multiple input tracks to a single outpur track, as shown in Figure 2.53 . The swi tch ·s control lever causes the connection of Lbe appropriate inpu t track 10 the output track. Whether a train appear al the output depends on whether a train exists on the presently selected input track. For a mUll. the switch 's control is not a lever, but rather select inputs, which represent the desired connection in binary. Rather than a train appearing or nOI appearing at the ourpul a mUll outpu ts a 1 or a 0 depending On whether the connected input ha a 1 or a O.
bulbs goi ng up a tali pole. We want one light per second to turn on (with the prevIous one turning
off). slanin-g from bu lb 59 al the bollOIll oflhe pole. and ending wilh bulb 0 al the lOp. We could use a microprocessor [0 cou nl down from 59 to 0, butlhe microprocessor probably d ocsn ~t hflve 60 OU I put pin s that we cou ld use to control each light. Our microprocessor progr~m cou ld Instead output
the num bers 59. 58 ..... 2. I. 0 in binary on a 6·bit OUIPUI pan (Ihus oUlpuIIlllg 1110 11. ~ 11010• .... 000010 . 000001. 000000). We could conneCI Ihose six bits 10 a 6-lIlput. 64 (2 )-OUlpUI decoder. wilh decoder OUlput d59 lighling bulb 59. d58 lighling bulb 58. elc. . We'd probably want an enable on our decoder in Ihis example. since we'd wa nt all Ihe IIghlS off until we started the COuntdown. The microprocessor would initially sct enable to 0 so that no li.hlS would be illuminated. When Ihe 60 second countdown begin,. Ihe microprocessor would sel e;able to 1. and Ihen Outpul 59. Ihen 58 (I second laler). Ihen 57. "IC. The final system would look like that in Figure 2.52.
Figure 2.52 Using a 6x64 decoder 10 interface a microprocessor and a column
of ligh" for a New Year', Eve di ' play. The microprocec,,')or sets e - 1 when the la.." minute countdown begin..,. and th en counte., down from 59 100 in binary on
Ihe pill' i 5 .. i O.
ole Ihal Ihe
microprocessor ... hould never output 6(),
61.62. or63 on i 5 .. i O. and Ihu, Iho," OUlPU" of Ihe decoder go unu,cd
iO (; - - il ill i2 i3 ~ a. i4 e i5 u
.,
~
Happy New Yearl
dO dl d2 d3
...
6x64 d62 dcd d63
Figure 2.53 A multiplexer is like a rn ilyard swilch. detennining \\ hich inpul track conn IS to !be single outpul track. according 10 Ihe SWilCh's contrOl lever. A 2- inpul mUltiplexer, known as a 2x I multiplexer. has two dala inputs i 1 and i~ . one elect input 5 O. and o ne dnta output d. a- shown in Figure 2 .~. If 50-0. . . \llIue passes th rough . If 50=1. i l's value pa' ses th roug h.
d58 d59 d60 d61 )59
79
Whenever you have outputs such that ex actly one of those outpu ts should be set 10 1 based on the value of inputs representing a binary number. think about u ing a decoder.
_ dO-l d 1-0
2x.-l decoder's output values when the inputs nre DO?
:J
2.9 Decoders and Muxes
The intern al design of a 2x I multiplexer is hown in Figure 2 . ~ . When 50- i1. the top A D gate OU lputs 1* i 0- i O. and the bOIlOIll AND gate outputs ~. 1- . Tb ' . th OR gate output iO+O - iO. a iO pa es th rough u, desired. U ke" i-. \\hen S -:. the bOIlOIll gate passe i 1 while the t p gate outputs O. re.ulling in the R pass ing i 1.
80
2 Combinational l ogic Design
2x1 iO i1
2.9 Decoders and Mu.es
88 iO
I. S IsO -.0 1. A llswer : Because sls0-01 passes inpul i Ilhrough value of 1 1, whIch presently is 1.
i1
2. S 1 sO ~ I!. AlISlVer : Thai config uralion of seleci line inpul values passes i 3 through. so d wo uld have Ihe value of 1 3, which presently is O.
i1
sa
sa 1
sa
0
w
3.
~ ~ ~ Fig ure 2.542 x I multiplexer: (a) block symbol, (b) conneclions for sO-O , and sO-l, and (c)
4.
internal design.
A 4-i nput muiliplexer. known as a 4xl multiplexer, has four data inputs.i 3, i 2, i 1, and i O. two seleci inpulS S 1 and sO, and one dala outpul d (a mu x a/ways has Just one data Outpul , no matler how many inpulS). A 4x I mux block diagram IS shown III Figure 2.55.
4x1 iO i1 d i2 i3 51 sO
i1
~any inpu ts arc there on a multiplexer hav ing fi ve select inpUlS? Answer: Five select inputs
can unIquely identify one of 2'=32 inputs 10 pass through
10
the OUlpUt.
Mayor's vote display using a multiplexer Mayor's switches
Cates his vote on Ihe proposal (approve or de ny). Very consislently. righl after Ihe mayor indicales his
i2
vote, the town's citizens boo and shout profanities at the mayor-no matter wh ich way he Vo tes. Having
i3
had enough of Ihis abuse, Ihe mayor selS up a simple digital system (Ihe mayor happens 10 have laken a
sa (b)
Figu re 2.55 4 x I muhiplexer: (a) block symbol and (b) internal design. The internal design of a 4x I multiplexer is shown in Figure 2.55 . When S 1 sO-DO, the to p AN D gale out puts i 0*1 * 1= i O. the next AND gate outputs i 1 *0* 1-0. the next gate o ut pu ts i 2*1 *O~O, and the bOllom gate outpu ts i 3*0*0=0. The OR gale outpulS i O+O+O+O~ i O. Thus, i 0 passes through, as des ired. Li kewise, when s 1 sO-O l. the second AN D gate passes i l. while the remaining AN D gates all o utput O. When 5150=10, the third AND gate passes i 2, and the other AND gates output O. When s 1 5 0= 11, the bOllom AND gate passes i 3, and the other AN D gates OUtput O. For any value on s 1 sO, onl y I AN D gate will have two 1s for its select inputs and will thus pas its data input ; the other AND gates wi ll have at least one 0 for its select inputs and will thus ou tpu t O. An 8x I multiplexer would have 8 data inputs i 7... i 0,3 selec t inputs 52 . s l and sO, and one data outpu t. More generally, an Mx I multiplexer has M data inputs, log2(M) select inputs, and one data outpu t. Remember. a mult iplexer always has just one output.
EXAMPLE 2.31
d, then d would have the
~ow many s~lecl lines arc there on a 4x2 multiplexer? Answer: This question is not valid--there IS no such thIng as a 4x2 multi plexer. A multiplexer has exac ily one ompul.
S. How
EXAMPLE 2.32
10
~ow many select inp~ls mus., be ,present on a J 6x I mulLiplexer? Ansu:er: Four select inputs ould be needed 10 ulllquely Ide ntI fy which of Ihe 16 inputs 10 pass through 10 the OUlpUt since log,( 16)=4.
Con.sider a srn alJ IOwn with a very unpopular mayor. Dunng every town mee ting, th e ci ty manager presents four proposals to the mayor. who then indi -
iO
sl (a)
81
iO
Basic questions about multiplexers
AS5u.me a 4x I muhipJexer's four input.; presently have the followlllg valuc" i 0-1. iI - I. i 2-0, and 13-0. Whal wou ld be Ihe value on muhiplexcr', OUIPUI d for Ihe folio" illS ,ciCCI inpul volu ?
course in digital design), shown in Figure 2.56. He provides himself with four switches that can be positioned up or down, outpUlling 1 or O. respecti vely. Wh en the time comes during th e mee ting for
him 10 VOle on the fi rst proposal. he places the firs l swilch either in the up (accept) or down (deny) position-bUI nobody else can see the position of the switch. When th e lime comes to Vote on the second
Figure 2.56 Mayor's \Ole displa~ ~S[em implemented using a 4x I mu.<.
proposal. he VOles on the second proposal by placing the second swilch up or do"n. And 00_ When he has fini shed casting all his VOles. he leaves Ihe meetine and he~ds OUI for off"". \\ith the mayor gone, the city manager power up a large green/red light. \\'hen the input to the lighl is ,
the lighl Iighls up red. When the inpul is 1. the lighllighlS up green. The cil} manager controls!VoO switches th at can route any of the mayor's switch outputs to the light. and so the manager sreps
through each configuralion of Ihe swilches. slarring with configuration 00 (and alling OUI "n,., mayor's VOle on Ihis proposal is ..... ). then 01. the n 10, and finally 11. causing the lighl lolighl either green or red for each configuratio n depending on the IX> itions of the 013)Or'£ S\\;tcbes. The sys tem can easily be implemented lIsi ng a 4x I mu ltiplexer. as shown in Figure 1.56,
N-bit Mxl multiplexer Muxes are oft en used to sele ' rively po s through n t ju tingle bilS. but 'v-bit data item..<. For example, one set of inputs A may onsist of four bits a3, aZ. d 1, a .:md anocMr: ( of inputs B may a lso consist of four bi ts b3 . b2. b1. bOo \\' \\:int t mullipl \ th< inputs to a four-bit output C. consi ti ng of c3. c2, cL eO. Figure 2.5 (al >hO\\S h,)\\ to accomplish ' uch mult iplexing using ~ ur _\ I lllU \ CS .
82
2 Combinational Logic Design 2.10 Additional Considera tions Simplifying notation:
4 A-.'-IO 4
4
4·bit 2xt D
....... C
rs
C
short for:
8-.'-11
sa sa
-
c3
-
c2
-
cl
-
sO (b)
(a)
B
=:....___ A
E iii 0'=
u:
~_T_..,..--, 10 '"'-_~Il
B·bit 4 Xl
8
D
?-12
~
l
"
j..,\
M 8 - -.....-..1 3
~~ --------
~~~-~
cO
rep rese nt .... sin gle wires.
Because mux ing data is so common. another common building bloc k is lhat of an N-bit- w ide Mx I mul7iplexer. So in our example. we wo uld use a 4 ·bil 2x I mu x. Don't get confused. lho ug h- an N-bil Mx I muhiplexe r is reall y just the same as N separa le Mx I multi plexers. with a lilhose muxes sharing the same select inpuls. Fi gure 2. 57(b) provIdes the sy mbo l fo r a 4- bi l 2x I mu x.
Multiplexed automobile above ·mirror display
Some cars come with a displ ay abovc the rcarview mirror, ::I S shown in Figure 2.58. Th e car's driver can press a button named mode to select among di5.playing the outside tcmperatu re, th e average miles-per-gallon of lhe car, lhe instantaneous miles-per-gallon, and th e approx imate mi les remaining until the C:1r ru ns out of gasoline. Assume the car's cenlral compUier sends
Figure 2.59 Above-mirror display using an 8-bil 4x I mux. Notice how many wires must be run from the car's central computer. which may be under the hood , to the above-mirror display-B * 4 = 32 wires. That's a lot of wires. We'll see in a later chapter how to reduce the number of wires.
. Notice in the previous example how simple a design can be when we can utilize hIgher-level building blocks. If we had to use regular 4x I mu xes. we would have 8 of them, and lots of wires drawn . If we had to use 2ates. we would have -lO of them. Of course, underlying Our simple design in Fig ure 2~59 are in fac I eight 4x I muxes. and underlyi ng those are 40 gates. And unde rl ying those gates are lOIS more rransislOrs. We see that the higher- level building blocks make our design task much more managable.
2.10 ADDITIONAL CONSIDERATIO NS Schematic Capture and Simulation
Ihe dala 10 the di splay as four 8·bil binary num. bers. T (the temperature). A (average mpg). I (inslanlaneo us mpg). and M (miles rema ini ng). T consists of 8 bils: t7. t6. t5. t4 . t3. t2. tL to. Likewise for A. l. and M. Assume Ihe display sys tem has two add itional inputs X and y. which always change accord ing (0 the fol-
;:;~ 8g-
0
(e)
Figure 2.57 -J -bit 2x I 11l1lX: (a) intern ;}1design using four 2x I nlu xes for selec ti ng al11.ong 4-bi l data items A or B. and (b) block diagr:lJl1 of iI -I.-bit 2x I mu x component: (e) The block diagram uses a C01111110n simpli fying notation. using one thick wire with a slanted line and the number 4 to
EXAMPLE 2.33
~~
83
Figure 2.58 Above· mirror di'play.
lowing seq uence-OO. 0 I. 10. ll-whenever the mode bU llon i, prc"cd (\I c'lI ,cc in [I lata chapler how 10 creale such a ,equence). When xy-OO. we wanl lo di'play T. When xy - O1. we wa nt to di'play A. When xy - l O. we wa nl lo di' play I. and when xy- I I. we wnnl to di'p lny M. A
When we design a circuil , how do we know that we designed the circuit correctly" Perhaps we created the truth tab le wrong, puning a 0 in an outpul column where we houId have PUI a 1. Or perhaps we wrote down lhe wrong mintenn . writing y z when we should bave wrole xy Z '. For exa mple, consider the num ber-of-one's counter in Example 2.25. We c reated a tru th table, then equations. and fin all y a circu it. Is the circuit correcl? One method of checking our wo rk is to re verse engineer the function from the c ircuit-staning with the c irc uit. we could conve n lhe circuil to equations. and then the equatio ns to a trulh table. If we gel the same ori ginal tru th table. then the circuil 5h uld be correct. Howeve r, sometimes we stan with an equalion ralher lhan a truth l:tble. 3S in Example 2.24 . We can reverse eng ineer lhe circuit to an equati n. but that equation ma~ be different than o ur ori g ina l equation. espe ia lly if we algebmicaIl) manipu!JI~ the original equalion when des igning the c ircuit. A nd checking that two equati ns are equi\'a le nt may requ ire convening to canonical rOm! (su m-of-minten11S1. \\hich may result in huge equalions if our functi o n has a large numbe r f inputs. In fact . e ve n if we didn ' t make nny mistakes in nvening ur mental undersr.mding of the desired func lion into a lruth lable or eq uatio n. ho\\ d \\ e \"no\\ that our mental
under tanding was correct ?
84
Combinalional Logic Design 2.10 Additional Considerations
.' Ih'lI (I circuil works (IS we expect is called A commonl y used method for checkmg ' f 'd' g omple in l)U IS 10 the circuit . . . . . ' . h process 0 provl In u sl mul allon. SlIlIlIlatlOlI of a CirCUli IS I e . ' 1' OUIPUI for the given inputs. th I compules Ihe Circul s and running a compu ler program a I The compUler program that We can then check Ihal the OUIPUI malches whal we expec . performs simulalion is called a s;mllialor. To use simulalion 10 check a circuit, we mUSI describe the circuit using a method that enables compuler programs 10 read the. Cl rcui!. One melhod of descri bing a cIrCUlI IS to draw the circuil using a schematic capture 1001. A schemat;c caplllre 1001 allows a user 10 place logic gates on a com pUler screen and 10 draw wires con necting those gates. The 1001 allows users to save their ci rcuit drawinos as compuler files. All the circuit dr~wings in this chapter have represented examples of schematics-for example, the circui l drawing in Figure 2.50(b), repreFigure 2.60 Display snapshot of a commercial schematic senting a 2x4 decoder. was an example ofa capture tool. schematic. Figure 2.60 shows a schematic for Ihe same des ign. drawn usi ng a popular Inpuls commercial schemalic capture tool. Schematic capture is used nOI onl y to capture circuils for simul ator lools, but also for tools that map our circuits to physical implementai1 Outputs Outputs nd3 d3~Ltions, which wi ll be di scu ed in Chapler 7. Once we've created a circuit u ing sched2 d2-.rmatic capture, we must provide the simulator d1 d1JL with a sel of inputs for which we want to check for proper output. One way of prodO dO~ viding the inputs is by drawing waveforms (a) (b) for the circuit 's input ' . An input's waveform Figure 2.61 Simulation: (a) begins wilh us defining Ihe inputs is a line thaI goe from left to right , represignal over time. (b) automatically generales the oUlput senting the va lue of the input as time waveforms when we ask the simu lato r to sim ulate the circui t. proceeds 10 the right. AI different times, we draw the line as high 10 represent 1, and low to represenl 0, as shown in Figure 2.6 1(a). After we are sat isfied wi th our input waveforms, we instruct the si mulator 10 simulale our ci rcu it for the given inpu ts waveforms . The simulator determines what the circuit outputs wou ld be for each unique combination of inputs, and generates waveforms for the outpUts. as illustraled in Figure 2.6 1(b). We can then check that the output waveforms malches the outpul val ues Ihat we wou ld expect for each input. Such checki ng can be done visuaJly. or by providing certain checking statements (often called assertions) to the simulalor. Simulation still does not guarantee thaI our circuil is correct. but rather increa es our cOllfidence that our circuit is correct.
iO---.-fL
I'.M+
i1~mulat~
~ .
.-- - -
85
Nonideal Gate Behavior-Delay Ideally, logic gale oUlputs would change Immediately in response to changes in the gate's inputs. The liming diagrams earlier in this chapter all ass umed such x ideal zero-delay gates, as shown again in o ! Figure 2.62(a) for an OR gale. Unfortunalely, real gate oUlputs don' l change 1 immedialely, but ralher after some short lime delay. After all , even the fastesl F 1 au tomobi les can't go from 0 10 60 milesF per-hour in 0 seconds. The delay in gates o , O ! .. is due in part 10 Ihe fac t that transistors time time don't switch from nonconducting to con(a) (b) ducting (or vice versa) immedi ately-it Figure 2.62 OR gale timing diagram: (a) withoul takes some time for electron to accumugale delay. (b) with gale delay. late in Ihe channel of an nMOS
1Ju- 1Ju-
:lr ~Jt-i___..
! ro-f-l
JJ
transistor, for example. Furthermore, electric current travels at the speed of light. which, whi le extremely fast. is slill nOI infinitely fast. Additionally, wires aren'l perfect and can slow down electric current because of "parasitic" characteristics like capacitance and inductance. The timing diagram in Figure 2.62(b) illustrales how a real gate' output changes slightly after change in the inpulS. Gales delays for modem CMOS gates may take less than I nanosecond to respond 10 changes--extremely fast. but still not zero.
Demultiplexers and Encoders Two additional components, demultiplexers and encoders. can also be con idered as combinational build ing blocks. However, those component" are far les commonly used than their counterparts of multiplexers and decoders. everlheless. for completeness. we' ll briefiy introduce Ihose addi lional components here. You may notice throughout thi s book thaI demultiplexers and encoders don't appear in many examples. if in any examples at all . Demultiplexer A demultiplexer has roughly the opposite functionality of a mulriple_
86
Combinational Logic Design
2.14 Exercises 87 and NOT gates, enabling . us to build d . ex tremely powerful conee t S ' ~n manipulate circuits by using mathB I p . ecnon 2 6 Introduced I ' an 00 ean function s namely equation '.. severa dIfferent representatiOIl5 of straightforward th;ee-step process fO~' d~;~ UItS, and truth tables. Section 2.7 described a exa mples of bui lding real circuits usin th g~ng combinatIOnal CIrcuits. and gave several NA ND and NOR gates are actuall get ree-step process. Section 2.8 described why CMOS technology, and showed y mare commonly used than AND and OR eates in could be built with NAND gates ~~~ea:~ ~~~It built from AND. OR. and NoT gates two other commonly used gates XOR d gates alone. That seCllon also introduced commonly used combinational bUildin an XNOR. Section 2.9 introduced two additional bl Introduced schematic capture tools ;. hoCI~s. decoders and mUltiplexers. Section 2.10 puter programs can re'ld thos . ,w IC a . ow us to draw our circuits uch that comd d' . , e CirCUitS and als ' the output waveforms for user-pro 'd d' . a Intra uce SImulation. which generates ' . . VI e Input waveforms t hi a CirCUIt correctly. That section also discu a e p us venfy that we created between the time that I'n t h ssed how real gates actually have a small delay pu s canoe and the t' b h ' secti on also introduced sam I '" Ime t at t e gate s output changes_ The . e ess common ly used c b' . aI . . tlplexers and encoders. am illatIOn building blocks. demul-
OU lpUt is 00 . 0010 yields 01, 0100 yields 10 . and 1000 yields 11. In other words, d O~ 1 resul ts in an OUl pUt of 0 in binary, d 1 ~ 1 results in an output of 1 '~ blllary, d 2- 1 results in an output of 2 in binary. and d3~ 1 results in an omput of 3 ttl btnary. A priority e/l eoder has si mil ar behavior, but handles situations where more than one input is 1 at the same ti me. A priority encoder gives pri ori ty to the hIghest Input that IS a 1. and outputs the binary value of that input. For example. if a 4x2. pri ority encoder has inputs d3 and dl both equal LD 1 (so the inputs are 1010). the pnonty encoder gIves pnority to d3 , and hence outputs 11.
2.11 COMBINATIONAL LOGIC OPTIMIZATIONS AND TRAOEOFFS (SEE SECTION 6.2) The earlier secti ons in this chapter described how to create basic combinational circuits. This section. Secti on 2. 11 , physically appears in this book as Secrion 6.2, and describes how to make those circuits better (smaller, fas ter, etc.)-namely, how to make optimizations and tradeoffs. One use of this book covers combinational logic optimi zations and tradeoffs immed iately after introducing basic combi national logic design, meaning covering that section now (as Section 2. 11 ). An alternative use of the book covers that section later (as Section 6.2) , after al so introducing basic sequential design, datapath components. and register-transfer level design- namely, after Chapters 3, 4, and 5.
2.14 EXERCISES Any problem noted with an asterisk (*) represent an especially challenging problem. SECTION 2.2: SWITCHES
2.12 COMBINATIONAL LO GIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAG ES (SEE SECTION 9.2) Hardware description languages (HDLs) allow designers to describe their circuits using a textual language rather than as circuit drawi ngs. Thi s section. Secti on 2. 12, introduces the use of HDLs to describe combinati onal log ic. The section physically appears in the book as Section 9.2. One use of mi s book introduces HDLs now (a~ Section 2. 12), immediately after introducing basic combinational logic. An alternative use of the book introduces HDLs later (as Section 9.2), after mastery of basic combinational, eq uenti al, and regIster-transfer level design.
2.13 CHAPTER SUMMARY Section 2. 1 introduced the idea of u. ing a custom digi tal circu it to implement a system's desired fu nctionality and defi ned combinational logic as a digi tal circuit whose outputs are a function of the circuit's present inputs. Section 2.2 provided a brief history of digital switches, starting from relays in the 19305 to today's CMOS transi. tors, wi th the main trend being the amazing pace at which switch size and delay have continued to shrink for the past several decades, lead ing to ICs capable of containing a billion transistors or mar:. Sect ion 2.3 described the basic behavior of a CMOS tr. nsiMor. j ust enough informatIOn to remove the mystery of how trans i s to r~ work . ecti on 2.4 introduced three fundamenta l bui lding blocks fo r bui lding di gital ci rc uit ~-A D gates. OR gates. and NOT ga te~ (i nverters), which arc far c.1sier to work with thun tranSiMor~ . Section 2.S showed how Boolean algebra could be u,cd to rcprc,ent circuit; built from D, OR,
2.1 A microprocessor in 1980 used aboul 10.000 transislors How . would fil In a modern chip having J billion transistors? . mallY of those mtcroprocessors
2.2 The fi rsl Pentium microprocessor had about 3 processors would fi l in a
'1"
.
od . . m~ I~on lr.lnSISIOrs. HO\\ many of those microm em chip havmg I billion transistors?
2.3 Define Moore'S Law.
~ PLUS
2.4 Assume for a pan icular year that a panicular ' h' . cOOlain I billion t ' . sIze C lp uSing tate-of-Lhe-an technolo!!)
ranSlSlOrs. ASSUll11112 Moore's Law h Id
same size chip be able 10 contai n in Ie; years ?
2.5 Assume a cell phone co the phone used vacu um I cubic inch?
.
50
0
s.
h
0\\
man)
-
:lD
rran~islors will the
"
:~~~Sinst~:~I~~~r::::~t~rs.
How. big would such 3 cell pb oe be If ' assumIng :1 \ 1} uum rube has a \olume of
2.6 bi A modem desktop proces. sor, suc h as [he Pentium -f, has about 300 million tr.Utsistors.. H
V3~UUI11 [U~ ~~~::~la~:k~~PI ~::re ~I:C~? if we used vacuum rube
of the I
~ . -suoun~
a
SECTION 2.3: THE CMOS TRANSISTOR 2.7 Describe the behavior of Ihe CMOS lransislor circuit
shown .in Figure 2.63. Slstor ClrCUiI conducts.
clearly indicati ng when the tr:Jn-
2.8 If we apply a voltage 10 the gate of a CMO lransbtor, \~hy ?ocsn', the CUITCnt fl ow from the gale 10 lht: tr..tnSistor S source or drain?
Figure 2-63 Ctrcuit, Nlt lrung t\\ O
~t
tr.ll~L"h.."'f'.
88
Combina tional Logic Desig n 2.14 Exercises
SEC TION 1.4: 800LEAN LOGIC GA TES-8 UILDING 8LOCKS FOR DIGITAL C IRCUITS . . OT . appropriatc for cach of Ihe fo li ow lOg. 2.9 \Vhich Boolean opcralion. AN D. OR. or . IS d' 'I house (c~lch motion sensor outputs 1 when Illolion is detected). ",' ssed simultaneous ly (eac h bUBo n ou tputs I when (b) Detectin g that th ree bu ttons arc bt: lOg pre
a
bu lt~1I
is being pressed)"
r oll! sensor (the ligh t sensor out puts 1 when light is 10
sensed).
.
Boolca." equ ations:
2. J 0 COllvcn the rollowing English probl em sl.lI~mel ' d "d ' d th e system is set 10 enabled. n h Id a pump If water IS CICCI!.; an (a) A ood deleclor S ou lum on , . ; 11 if il is nig hl and lig hl i delecled inside a (b) A house energy monitor should sound an a an .
.,.
lIS 10
room bu t 1110 [ion is n OI de tected. . . . wate r valve if the sys te m is enabled and (c) A n irriga ti on sys tem should open the spnnkl er s neither rai n nor freezing tempelJ.tures are de tec ted. . 1.11 Eva luale Ihe Boo lean equali on F = (a AND b) OR c OR d fo r Ih e g ive n va lues o f vanables a . b. c. and d: (a) a-I. b=1. c=1. d=O (b) a=O. b=1. c=1. d=O (c) a=1. b=1. c=O . d=O (d) a-I. b-O . c= l. d-l
e.
o
PLUS 2.20 A DJ ("·disc joc key." meaning someo ne who plays the mus ic al a party) would like a system to aUlo malically conlrol a strobe li ghl and disco ball in a dance hall depending on whether music is play in g and anyone is dancin g. Assume we have a sound sensor with output S mat indicates whelh er mu sic is pl ay ing (5= 1 means music is p laying) and a motion sensor M that indicates whether peopl e are dancing (11- 1 means people are danc ing). The strobe light bas an input L Ihal lums Ihe lig hl on when L is 1. and the di sco ball has an inpul B thai turns the ball on when B is 1. The DJ wants Ihe di sco ball 10 tu m o n on ly when music i playiDg and nobody is dan ci ng. and Ih e DJ wan Is the strobe li ghl lo lum o n o nly when music is playing and people are danCing. Using A D. OR. and NOT gales. creale a si mple digilal circuil to activate: (a) the di sco ba ll. and (b) Ih e stro be li ght.
2.21 We wanl to concise ly descri be the fa llowing si ruation usi ng a Boolean equation. \Ve Wanl to fire a foolball coach (by setting F -1) if he is mean (represented by M= 1). If he is nor mean. but has a losing season (represented by the Boolean variable L- 1). we wanl 10 fire him anyway. Write an equ ation thai translales the siluation directly 10 a 8 00lean equation for F. "ithout any simplificmi on.
2. 12 Eva lu ale Ihe Boo lean eq uali on F = a AN D (b OR c ) AN D d fo r Ihe g ive n va lues o f variables a . b. c. and d: (a) a=l. b-1. c=O. d-l (b) a=O. b=O. c=O, d-l (c) a-I. b-O. c=O , d=O (d) a-I. b=O. c=1. d=1 2.13 Eval uale the 8 00 lean eq uation F ab ies a . b. c . an d d: (a) a-I, b-1. c-O. d-l (b) a-D. b-O. c-O . d-l (c) a-l. b-O. c=O. d - O (d) a-l. b-O. c-1. d - l
=a A
a + bcd'
2. 19 We Want to design a system that sounds a buzzer inside Our home whenever motion outside is detec led al ni ght. Ass um ing we have a mo ti on se nsor wi th o utput M thal indicates whether mol ion is delec led (M-l means motion delecled) and a lighl sensOr wilh Outpul L that indica les if li ghl is delecled (L = 1 means li ghl is delecled). The buzzer inside the home has a sing le inpul B Ihat when 1 crea les a loud warn ing sound. Usi ng AND. OR. and NOT gates. creale a s imple dig ital circuit 10 impl ement the mo ti on detec tor at night system.
(a) Detecti ng mOl ion in any Illolion se nsor surrOUIl 109 •
(e) Delccllng (he :1 bscncc of light from a
SECT/ON 2.5: 800LEAN ALGE8RA 2.22 Fo rthe funclion F = a + a' b + acd + c': (a) Lis l all Ih e vari ables. (b) Lisl all Ihe li lerals. (c) Lis l all Ihe prod uci lerms.
D (b OR (C AND d) ) fo r Ihe g iven va lu es of vari·
2.23 Fo r Ihe fun cli o n F - a ' d' + a ' c + b' cd' (a) Lisl all the varia bles. (b) Lisl all the lilerals. (c) Lisl a ll Ihe prod uci lerms.
2. 1 ~ Show the conduc li on paths an d OUIPUI va lue of the OR gale transi lor c irc uil in Figure 2.11
+ cd:
2.24 Lei varia bl es T represent being tall. H bei ng heavy. and F being fast. Let" consider an)ooe who is nOI lall as short . not heavy as li gh l. and not fast as slow. Write a Boolean equation to represe nl Ihe fo llowing:
when: (a) x = 1 and y = O. (b) x - I and y = I. 2.15 Show the conduc lion paths and OUIPUI va lue o f Ihe AN D ga le lrans i'lo r circ uil in Fig ure 2.1 3 when: (a) x = 1 and y - O. (b) x = 1 and y - 1.
(a) Yo u moy ride a panicu lar amu semen l park ride only if you are either tall !Uld ligb~ or s hort and heavy.
2. 16 Conven eac h of Ih e fo ll Ow ing equali ons directly 10 gate-level circlIi l-" (a) F a b ' + bc + c ' (b) F - ab + b ' c 'd'
(b) YOll may NOT ri de an amuse ment park ride if you are either tnll !Uld lighl. or -bon !Uld heavy. Use a lge bru 10 si mp lify the eq uatio n 10 sum-of-produ IS. (c) Yo u are e li g ibl e 10 play o n a panicul", baskelball leam if you are tall !Uld fast. or tall :tnd s low. Sim plify Ihi s equ alio n.
(e)
F
E
« a + b' )
*
(c ' + d»
+
(c + d
+
e' )
(d) Yo u are OT e lig ible 10 play on " particular foolball 1
2.17 Conven each of Ihe following equali ons direclly 10 gate-leve l circ uits:
+ b' c
(a) F -
a ' b'
(~ F (c) F -
ab + b c + cd + de (( a b) ' + (c» + (d + e f) ,
2. IS Conven each of Ihe fOllowing equation; direell y 10 gale- leve l C"ClliL'. (a) F - abc + a' bc
89
+ a e + f' (c) F = (a + b) + (c ' * (d + e + f9» (b) F -
fu-s
2.25 Le i variab les 5 represenl n pockagc being -mall. H being he3\). and £ being <\pensl\e. Let", co ns ider a package th aI b not small as big. nO( heJ.\') ~ light. and not c:\pensl\~" \ nsi"c. \ rile n 8 00lean equmion I represent Ihe fOllowing:
90
~
Combinat ional Log ic Design
2.14 Exercises
inexpen sive.
.
(b) You can NOT deli ve r a package Ihal IS
r
15
b
led above. Use nlgebru to simplify th e eq ua tion .
10 sum -of-products . k I 'f Ihe pockoges "rc small and lighl, small (c) You can load the pac bges into you r truc on ~ I . S' rfy Ihe equallon . and heavy. or big and light. IInp I "b d ' bove Simplify to sum -of-products. OT I d h packaoes descn ea . (d) You can N oa l e , . o I ' equarion (0 sum-of-products form: 2.26 Use algebraic manipu lation to convert the fol OWing (b - c)(d ' ) + ac ' ( b + d ) F a aloebrnic + h followin 2.27 Use manipu lation to conve rt te d )'o equation to sum-of-products ronn: a ' b( ; + d ' ) +a ( b ' + c) +a ( b+ c.. +a 'b
.
f the following equatio n: F
;;;:
abe
c
F
a o a
a
0
0
a o o o a
T}BlE 2.10
~·S
a
G
b
c
F
a
1
c>
a
c:- - - f igure 2.65 Combinalional circuil C.
2.35 Fill in Tab le 2.S's columns for Ihe equalion: F- ab + b ' . TABLE 2.8 Truth table,
a a
d
a
o o a a a
1
a
2.34 Convert each of lhe foll owing Boolean equalions 10 a !ruth table: (a) F ( a , b . c) = a' + bc ' (b) F( a , b , c) = ( ab ) ' + a c ' + bc ab + a c + a b ' c ' + c ' (c) F( a , b , c ) (d) F ( a , b , c , d ) = a ' bc + d '
Truth table.
0
2.3 1 Creme a Boolean equation representalion of the dig ital circuit in Figure 2.64.
10
an equalion. Don'I minimize
2043 Creale a lrulh table for Ihe circuil of Figure 2.65.
--.a
c'
2.33 Convert each of Ihe Boolean equalions in Exercise 2.30 lrulh table.
10
2.41 Use algebraic man ipulat ion to minimize rile equation obtained in Exercise 2AO, 2.42 Creale a lrulh table for Ihe circuil of Figure 2.64.
2.4~
(J
2.32 Create a Boolean eq uat ion repre entation for the dig ital circuit in Figure 2.65.
b -----r~
2.37 Use algebraic manipulafion to minimize the equation obtained in Exercise 2.36.
Convert Ihe funclion F shown in Ihe lrulh lable in Table 2.9
10
a digital circui t.
2.45 Convert Ihe funclion F shown in Ihe lrulh lable in Table 2. 10 10 a digital circuit.
SECTION 2.6: REPRESENTATIO S OF BOOLEAN
(d) F ( a . b , c )
an equation. Don't minimize
2.39 Use algebraic manipulation to minimize the equaLion obtained in Exercise 2.38.
'
Figure 2.64 Combinalional circuit F.
10
2.40 Convert the function F shown in the truth table in Table 2. I I to an equation. Don't minimize the equat ion.
.
FU CTIONS . 2.30 Convert Ihe following Boolean equalions 10 a digi lal circ u,,: (a) F (a , b , c ) a ' bc + a b (b) F ( a , b , c ) a' b (c ) F( a , b , c ) abc + ab + a + b + c
2.36 Convert the functi on F shown in the truth table in Table 2.9 [he equation.
2.38 Convert Ihe funclion F shown in Ihe lrulh lable in Table 2. 10 the equation.
1
a a
2,28 Usc DeMoroan's Law 10 find Ihe IIl verse 0 . F ' = ( a bc + a ' b) , e r Hint' Stan wllh Redu ce 10 sum· of-products ,om1. . . ' .F _ ' + a bd' + ac ' 9 Use DeMorg an's Law to find the .In verse 0 f the follo\\llOoe equation . PLU·S _.- acd . Reduce 10 sum-of-produc ls fom1 .
o
91
TABLE 2.9 Truth table.
k "'S are either small and c,'
o Truth table.
TABtE 2.11
b
c
F
o a
a
o
1
1
a o o
a a a
a
o
a
o o a a
a
2.46 Convert the function F shown in the truth table in Table 2, 1J to a digital circuit. 2.47 Convert th e following Boolean equa tions to canonical sum-of-m imenns fonn: (a) F ( a , b , c ) a ' bc + a b (b) F (a , b , c) a'b (c) F(a , b, c) a bc + ab + a + b + c (d) F (a , b , c) c' 2.48 Delenn ine whelher Ihe Boolean funclions F ( a + b ) ' *a and G equivalen!. using: (a) algebraic manipulation. and (b) !ruth lables.
a
T
b' are
2.49 Detennine whelhcflhe Boolea n funclion s F = a b ' and G = ( a ' + a b) ' are eq ui\'alenl using: (a) algebraic manipulalion. and (b) lrulh lables.
2.50 Delennine whelher Ihe Boolean funclion G _ a 'b'c + ab' c + a bc ' + abc isequivalent to the function represented by the circuit in Figure 2.66.
b H
2.51 Determ ine whether the two circuits in Figure 2.67 are eq ui va lent circuits using: (3) algebraic manipulalion. and (b) lrulh lables.
Figure 2.66 Combinational irruil H.
G
Figure 2.67 Combinntional circuils F and C. . 2.52 · Figure 2.68 shows two circuit~ in \\ hich Ihe- inputs of the cirt'uil'\ Jre un~;)tx-Ied_ (a) Dctenninc whether the 1\\ 0 circu jt~ arc cquh-ak nl. Hint : Tr) ;1JI ~l\.)'~I t'tle IJ~hng' ,)t lM inpulS fi r both circuit:"
92
Combinational log ic Design
2.14 Exercises
' . ,'II au need 10 perform to dc temli nc if IWO circuits with (b) How many circ uli compansolls ,\ I Y 10 unlabeled inputs arc C(lui va lenl ? ..
D
Dr>-F
2.60
Sh~w the conduction pmhs and ou tput va lue of the NAND gale transistor circuil in Figure 2.4) when: (a) X = 1 and y = O. (b) x = 1 and y z 1.
2.61 Show Ihe eonduelion parhs and OUlpUI valu'e of Ihe NOR gale lransislor eireuil in Figure 2"+5 when: (a) X = I and y - O. (b) x - a and y = O. 2.62 Show the conducti on paths and output va lu e of the AN D gale lransislOr circuit in Figure 2.46 when: (a) X = 1 and y - 1. (b) X = a and y _ 1. 2.63 Two people, denoted using variables A and B, wanl (Q ride with you on your mOlorcycle. Write <'1 Boolean cquUlion that indicates thaI exac lly one of the Iwo peopl e can come (A=l means A can cOllle, A=O means A can ', come). Then use X OR 10 si mpli fy your equation. 2.64 Simplify Ihe fo llowing equarion by using XOR wherever possible: F = a ' b + ab' ~ cd ' + c ' d + ae.
G
Figure 2.68 Combinalional eireuils F and G. SECTION 2.7: CO/l'IBI NA TIONAL LOGIC DESIGN PROCESS 1.53 A mu seum has three rooms. each with a IllOlion sensor (m O. ~1. and m2) ,thai outputs 1 when moti on is detected. At nigh!. the only person in the museum IS one s~c unly guard who wal~ from room to room Create a circuit thai sounds an alaml (by CUing an output A to l ~ Ir nlOl ion is ever dClcc;ed in more than one room at a lime (i .e~ . in two or three rooms). meanmg there must be an imruder or inlnJders in the museum. Start with a truth table.
2.54 Creale a cireuil for the musem of Exercise 2.53 thaI delccls whelher the guard is properly patrolling the museum. detected by exactly one mOlion sensor being 1. (If no mOlion sensor is 1. Ihe guard musl be sining or sleeping.) 2.55 Consider the museum security aJarrn function of Exerci se 2.53. but, for
sages musl be rese n!. Using the eombinarional design process of Table 2.5. creale a collision detec tion circuit for a router that connects 4 computers. The circuit has 4 inputs labeled MO th rough M3 th aI are I when Ihe corresponding compuler is
2.57 Using Ihe eombinalional design process of Table 2.5. creale a 4· bil prime number deleclOl. The eireuil has four inpu ts. N3. N2. NI. and NO Ihar corre'pond 10 " 4-bil number (N3 is the most ~ i gni ficam bit) and one output named P Ihal outpUl!oo a 1 when th e input is a prime number or 0 otherwise.
2.65 Use XOR odd.
10
creale " cireuil thaI OUIPUIS a 1 when the num ber of Is on inputs a. b. c. d i
2.66 Use XOR or.XNOR
[Q
creme a eireuil Ihal deleclS if al l inputs a. b. c. d are as.
2.67 Use XOR or XNOR are Is.
10
creme a eircuil Ihal de leels if an even nu mber of rhe inputs a. b. c. d
2.6S Show Ihal a 4-bi l XOR gale is an odd funelion (meaning Ihe OUIPUI is 1 only if rhe number of inpUI Is is odd). SECTION 2.9: DECODERS AND MUXES 2.69 Design a 3x8 decoder using AND. OR. and NOT gates.
2.70 Design a 4" 16 decoder using AND. OR. and NOT gales. 2.71 Design a 3x8 decoder with enable using AND. OR. and NOT gares. 2.72 Design an 8x I mu hi plexer using AND. OR . and NOT gales. 2.73 Design a 16xl muhiplexer using AND. OR , and
OT gales.
2.74 Design a 4-bit 4x I rnull iplexer using 4x I multiplexers. 2.75 Create a circuit th at rings a bell whenever motion is dClccrcd from one oflwo motion .sensors. A switch 5 determines which sensor to pay allention to: 5=0 means ring the bell when there's moti on at motion sensor 1. 5=1 means motion sensor 2.
2.76 A home enlenainmenr cenler has four differenr audio ourees thar can be pla)ed over rhe same sel of speakers. Each aud io Source. named A. B. C. and D. is eonnccled using " ires on "hieb the digitized audio signal is tmnsmiued. The user seleclS wttich audio Duree i.:,
=
SECTION 2.10: ADDITIONAL CONSIDERA TIONS 2.78 Design a Ix 8 de muhiplexer using AN D. OR. and NOT gale . 2.79 Design a 4x2 encoder using A D. OR. and NOT gales.
5-bil binal) number. Create a circuit that iliumlllarcs a "low tire prc.."'''iurc'' inthc;.lIor fift ht (by setting an YOIl
mighl find
II
""'Ier 10 ereale l
ci rCUli that detccl,lhe invcl'M! ru nction. You can lhcnjU"i1append an IIlvencr 10 'he outpul circuit
ort~
be pla)ed
output the user's selec ted audio source.
2.-9 A car has a low- ti re-pre\'~u re ~ nsor Ihat outputs the current lire prc ...... ure as
3
10
using a rolary swilch wilh four OUlpUIS. 5 O. 51. 52. 53 . of which e.• a tI) one wil1 be . . al any give n lime. If 5 a = ' I ' . Ihe audio souree A shoul d be pla)ed. if 5 I = 'I '. rhe audio B should be played. and so on. Creare a digilal cireuil \Virh a single -bit ourpur a thaI "ill
2.58 A car has a fuel-level deleclor th aI OUlpu ts Ihe currenl fuel-level ", a 3-bil binary number. wirh 000 mea ning emply and III meaning full. Create" cireuil Ihal ilium in:!le, a " low fuel" indio calOr lighl (by , cuing an OUlpO! l 10 1) when Ihe fucl level droJl~ below level 3.
OUIPUI T 10 I) when the lire pre"ure drops below 16. Il in!:
93
SECTION 2.8: MORE GATES
2.77 Design a 1..4 demulriplexer using A D. OR. and NOT gores.
2.110 Design an 8x3 encoder using AND. OR. and
OT gale . . , ume rhal onl)
Oil<'
inpul will be
I ;.11 any given time. 2.8 1 Design 3 -'-':2 priori t)' encoder usi ng
a is encoded as 00.
D. OR. nnd NOT gales. ""urne th;u e\
9-1
2 Combinational Logic Design ~
DESIGNER PROFILE
experience. "For the sma ller team projc~l . each pe~on had more responsibility. and overull effiCiency was high. focu sed his advanced For the lame team project. each per!;on worked on a i<.lUdics on integrated spec ific pa'; of the project-the chip lVas div ided into circuit (Ie) design. clu sters. each clu ster into units. and each unit had a be lieving the industry to leader, We relied heavi ly on design nows and ha ve a great future. methodologies." Years laler now. he Sam son has seen th e industry's peaks and valleys reali zes he was right: during th e past IwO decades: "Li ke any industry. the Ie "Looking brick 20 years job market has ils ups and downs." He believes the in high tcc h. we have industry survives the low !>oims in large pan due to experienced four major "innov3lion:' "Brand name sell products. but without revo lutions: the PC innovation , markets go elsewhere, So we have to be very rc\ OiUlion. digital rC\Olulion. cOlll l1luni ca ti on revolution. innovati ve, crea ting new products so lhal we are always Jnd Internet rc\oJution-all four enabled by the Ie ahead in the e:lobal competition," indul.,ll') . The impacl of these revolutions 10 ollr daily life But. "inno~alion doesn't grow on trees ," Samson points is profound:' out. "There are two kinds of innovations. The first is He has found his job to be "vcry challenging. invention. which requires a good unders tanding of the interestin!! . and exciting. I cO lllinually learn new skills to physics behind technology. For example. to make an keep up. ; nd to do m~ job more efficicm ly:' analog TV into a digi tal TV, we must know how human One of SJmson's key design projects was for digital eyes perceive video images, whi ch parts can be digitized, television. namely. high-definition TV (HDTV). involving how digital images can be produced on a silicon chip. elc. companies like Zenith, Philips, and Intel. In particular, he The second kind of innovmion reuses existing technology led the 12-person design teal11 that built Inters first Liquid for a new application. For example, we can reuse Crystal on Silicon (LCoS) chip for rear-projection HDTY. ad vanced space technologies in a new non-space product "Traditional LCoS ch ips are analog. They apply different serving a bigger market. c·8ay is ano ther example-it analOR voltage.. on each pixel of the display chip so it can reused Internet technology for on-line auctions. produ~e an image. But analog LeoS is very sensitive to Innovations lead 10 new products, and thus new jobs for noise and temperature variation. We used digital signals to many years, do pube width modulation on each pixel." Samson is
quite proud of his team', accompli,hments: "Our HDTV picture quality was much bener." Sam son also \\-orked on the 200-mcmber design team for Inlers Pentium II processor. Thai was a very differen!
Thus. Samson point out that ''The industry is counting
on new engineer from college to be innovative. so they
can continue to drivc the high tech industry forward. When you graduate from college. it'~ up to ),011 to make things beuer."
~3
Sequential logic Des ignCo ntro" e rs 3.1/NTRODUCT/ON The output of a comb ina tion a l circu it is a function o nl y of the circuit's present inputs. A combina tion a l c irc uit has no me mo ry-we cannot to re bits into a combinational ci rc uit a nd later read the bits o ut th at we saved. Combinational circuits by them eh' are rather limited in the ir usefulness. Desig ners ins tead typicall y use combinational circ uits as part of larger c irc uits called sequ entia l ci rc uits--circuits that do have memon . A sequel/tial circllit is a circuit w hose o utputs depend not only on the circuit's prese~t inputs, but also o n th e c irc uit 's present state, which is all the bits stored in the circuit. The circuit 's s ta te in turn depends on the past sequel/ce of value that ha\'e appeared at the c irc uit 's inputs. An everyday example of a combinational circuit i a doorbell-push the button (the input) now. and the bell (the o utput) rin gs. Push the butt on again. and the bell rings again. Pus h the button tomorrow. o r next week. and the bell ring the arne en h time. A doorbell has no state, no memory-its o utput value (whether the bell ring or not ) depends solely on its present input value (whether the button i pressed or not ). In ontnst. an example of a sequentia l circuit is an automa ti c garage door sy tem-pu h the button (the input) now. and the door opens. Push the button again. and this time the door loses. Pu b the button tom orro w. a nd the door opens again. The system' output (\\ hether the door opens or closes) depends o n the s ta te of the system (whether the door is pre. entl~ open or closed). which in [urn depe nds on the sequ ence of pasl input value in e we turned on the ystem . Most di gita l sys tem with which you are familiar in\'oh e sequential cin:-uits that store bits. A handheld ca lculator mus t contain a sequential cin:-uit. because [he ,'a/culator mus t store the numbers you en te r. in order to operate on tho ' e nWllbe~. A digital amen s tores pictures. A traffic lig ht controller store. infonnmion indicaring \\ hi h light i. prese ntly g reen. A c ircuit t.h at counts d wn from 59 to 0 Stores the present 'l'unt \ alu', to kn ow what the nex t val ue should be. In th is c hap ter. we describe ba~ic sequential ireuit building bl 'I..s. Jnd th- d "tgn 01 a cennin c1a~~ of sequential circui ts kno\\ n as c ntrollers .
.
---~
. --
-
96
3 Sequential Logic Design-Contro llers 3.2 Storing One Bh-Flip-Aops
3.2 STORING ONE BIT-FliP- FLOPS To build a sequential circui!. we need a Call ~_r---, Blue light building block that enables us to store a buHon ~ bi!. By store a bi!. we mean that we can save a bit in the block (say a 1) and latcr Cancel~ ~ bunon come back 10 see what we saved. As an example. suppose we want to bui ld the fli ght attendant call-button system in Figure 3.1 Flight attendant ca ll-button Figure 3.1 . An airline passenger can push system. Pressing Call turns on the light, the Call bunon to tum on a small blue which stays on afl er Ca ll is released. Pressing Cancel turns otT the light. light above the passenger's sea!. indicati ng 10 a fli ght attendant that the passenger . needs service. The light stays on even after the call button is released. The hght can be turned off by pressing the Callcel button. Since the light has to stay on even after the call button is released. we need a way to " remember" that the call button wa pressed. We can remember by u ing a bit storage block. and storing a 1 in the block when the call button is pressed. and storing a 0 when the cancel button is pressed. We connect the output of this bit storage block to the blue ligh!. The light illuminates when the block's output is 1. To introduce the internal design of such a bit storage block, we' ll introduce several increasi ngly complex circuits able to store a bit-a bas ic SR latch. a level-sensitive SR latch. a level-sensitive 0 latch, and an edge-triggered 0 flip-flop . The 0 flip-flop will then be used 10 create a block capable of storing multiple bits, known as a register, which will serve as our primary bit storage block in the rest of the book. Each success ive circuit elimi. nates some problem of the previous one, leading to the robust 0 Rip-flop and then register. Be aware that designers rarely use bit storage blocks other than 0 flip-nops. We introduce the other blocks primarily to provide the reader with the underlying intuition of the 0 flip-flop 's design.
Feedback-The Basic Storage Method The basic method used to store a bit in a digital circuit isfeedback . You've surcly experienced feedback in the form of audio feedback, when omeone talking into a microphone stood in front of the speaker. causing a loud continuous humming ound to come out of the speake~ (in tum causing everyone to cover their ears and snicker). The talkcr gcnerated a sound that was picked up by the microphone, came out the peakers (ampli fied), was picked up again by the microphone, came out the speakers again (amplified even more), etc. That' feedback. Feedback in audio systems is annoying, but in digital sy terns is ex tremely useful. Intuitively. we know that we need to somehow feed the output of a logic gate back into the gate itself, so that the stored bit ends up looping arou nd and around, like a dog chasing its own tail. We might try the circuit in Figurc 3.2. Suppose initially 0 is 0 and 5 is O. At some poi nt. uppose we set 5 to 1. That ca uses 0 to become 1. and that 1 feeds back into the OR gate, causing 0 to be 1. ctc. So even when S rctums Ftgure 3.2 FiNt (failed) attempt at u\lng fecdbxk to O. 0 stays 1. Unfonunmely, 0 St;ty~ 1 from then on. and we
Srf2j-
to '-lore a bi!.
have no way of reselling 0 to O. But hopefully you understand the basic idea of feedback now-we did successfully store a 1 using feedback. . We draw in Figure 3.3 the timing diagram for our attempted feedback circuit from Ftgure 3.2. NOIe that we assume the OR gate has a small input to output delay, as was discussed in Section 2. 10. Initially, we assume both OR gate inputs are 0 (Figure 3.3(a)). Then we set S to 1 (Figure 3.3(b», which causes 0 to become 1 slighlly later (Figure 3.3(c» , which in tum ca uses t to become 1 lightly later (Figure 3.3(d». Finally. When we change S back to 0 (Figure 3.3(e». 0 will stay 1 because t is I. The firsl curved line with an arrow indicates that the event of 5 changing from 0 to 1 cau es the eVent of 0 changing from 0 to 1. The second curved line with an arrow indicates that the eVent of 0 changing from 0 to 1 in turn causes Ihe eVent of t changing from 0 10 I. And that 1 then Continues to loop around, forever, with no way of 5 resetting 0 to O.
S~ t
f
Q0
~l2J-~l~~ ! (a) :
;
~L
\
\
~C},:
(b)
'
' ----fei) -'
(e)
/-;f'/
(
~)f-;£":;'~/__/_/_---__________ 0 stays 1 forever
\,
Figure 3.3 Tracing the behavior of our first attempt at bit storage.
SR Latch Basic SR Lalch It turns out that the simple circuit in Figure 3.4. called a basic SR latch . implements the bil slOrage building block we desire. The circuit consists of just a pair of cross-coupled NOR gates. Making the cireui!"s S input equal to 1 causes Q to become 1. while making R equal to 1 causes Q 10 become O. Making both 5 and R equal to 0 causes whatever value 0 i. 10 keep loopi ng around. In other words, S "sets" the latch to 1. and R "resets" the latch to O-hence the lellers 5 (for set) and R (for reset). Let's ee why the basic SR lalch works as it does. Recall that a OR gate outputs 1 when all the gate 's input ' equal 0; if at least one input equals 1. the NOR g1tle outputs O.
s
o Figure 15
R latch \\ hen
0-----
o
=0 and R =I.
98
3 Sequential Logic Design- Conlrollers
3.2 Storing One Bit- Flip-Rops S k 5 0 d R-l as in Ihe SR Imch ci rcuil or Figure 3.5. and that . e bOllom 'ate or Ihe cireuit has at uppose. lhm we ma 'c = an - . • we don'l 11lIllally know the va illes or 0 and t. SlI1ce Ih . . g. . 1 . becoming equal 10 1 (R). the gale oulPUIS 0- in Ihe IImlll "O dlagrmn. R. . leasl one IIlpUI callScs 0 10 become O. In the circuil. O's 0 reeds back 10 Ihe lap OR ga te. wh Ich WIU have . OUIPUI equaI Ia 1. In the limin "o dIagram. 0 becoming 0 bOlh li. S .IIlPUIS equal 10 0 and liS . callses t 10 become 1. In Ihe cirell il. thai 1 reeds back 10 Ihe bOllom OR gale. whIch has al leasl one inpul eqllal 10 1 (nclUnlly. bOlh inpuls equal 1). and so Ihe botiom gate will contin lle 10 Oll lplll O. Thlls the OUlp11l 0 equals O. and all values are slable. Now suppose we make 5=0 and S 1 R=O . as in Figllre 3.6. The bOllom gme 0---- slill has aI leasl one inpu l equal 10 1 (Ihe input coming rrom the top gale). so the
botiol11 gale cOlliinues 10 OIl IPUI O. The lOp gale cOlllin lles 10 have bOlh inpu ls equal 10 0 and cOlllinlles 10 OUlpu l 1. The OUlpUi 0 willihus slill eq ual O. Thus Ihe earli er R= 1 srored a 0 inlo Ihe SR lalch. also known as resellillg Ihe Ialch . and Ihal 0 remains slOred even when we Figure 3.6 5R laleh relUm R 10 O. when 5=0 and R= O. Now lei's make 5= 1 and R=O . as in afler R equaled I. Figure 3.7. The lap gale in the circuil now has one inplII cqual 10 1. so Ihe lap gate ou tputs a O- the liming diagram shows Ihe change or 5 rrom 0 10 1 causing t 10 change from 1 10 O. The lOp ga le'. 0 OUIPUI reeds back 10 Ihe ,_ - 1 _----- 0 botiom gale. which now has both inpUis \. . . :><.: ,. ,. ", equa l 10 0 and OUIPUIS l - Ihe limi ng \~Q di agram shows Ihe change or t rrom 1 10 0 causing 0 10 change rrom 0 10 1. R=O The botiom gale's (0) 1 OUiPUI reeds Figure 3.7 5R Inlch back 10 Ihe lap gale. which has al leasl when S= I and R=O. one inpu l equal 10 1 (ac lUally. bOlh inputs equa l 1 now). a Ihe lap gale conlinues 10 OUIPU I O. The OUIPUI 0 Iherefore equa ls 1. and all va lues are slable. _---- 0 I ow lei's make 5- 0 and R=O aga in , ,_ - t , a, in Figure 3.8. The top gale slill has aI leasl one inpu l eq ual to 1 (the inpul Q comi ng from the botiom gale). so the lOp gale cOnlin ue, 10 output O. The botiom R=O ga le cOnli nuc, 10 have bolh inputs equa l Figure 3.8 SR laleh 10 a and eOnlinue, to oU lpul I. The when 5=() and R =0. ou ipul 0 " 51ill eq ual to I. Thu" Ihe aflcr 5 equaled I.
o
Level-Sensitive SR Latch A problem wilh Ihe bas ic SR Ialch is 5 and R both equaling 1 al Ihe same time causes
Q
0
S
~
0
R 0
- ---------1
~ --
earlier 5= 1 stored a 1 into the SR latCh, also known as sellillg Ihe lalch, and thai 1 remains slored bunon even when we relU rn S 10 O. The basic SR Ialch can be used 10 implemenl the flighl allendant cal/-bullon syslem (Figure 3.9). We conneCI the ca ll bUllon 10 5, Ihe Cancel cancel button 10 R. and Ihe lighl 10 bunon O. Pressing Ihe call bUllon sels 0 10 I, Ihus lurning on Ihe lighl. 0 stays I even when the call button is Figure 3.9 Flight auendant caIJ-bulton system using a basic SR laleh. released. Pressing Ihe cancel bUllOn reselS 0 10 0, Ihus turn ing orf the lighl. 0 Slays a even when Ihe cancel bUllon is released.
unden ned behavior-we mighl have stored a I, we mighl have slored a 0, or we might even cause Ihe latch ourp Ui 10 oseillale from 1 10 0 10 1 10 O. and so on. Lei's ee wby. If 5 = 1 and R= I, both gales have at leasI one inpul equal 10 1. and thu both gate OUlput 0, as shown in Fig ure 3. 1O(a). A problem occurs when we rerum 5 and R 10 O. Suppose 5 and R rerum to 0 al exaclly the same time. Then both gates will have all 0 ar Iheir inpulS, so Iheir ourp uls wi ll change from Os to Is. as shown in Figure 3.1 0(b). Those Is feed back 10 the gate inpuls, causing Ihe gates 10 OUIPUI as. as hown in Figure 3. IO(c). Those as feed back 10 the gale inputs again. causing the gates to OUtpUI Is. And 0 on. Going from I 10 a 10 1 10 0 and so on is cal/ed oscillation . Oscillation is not a de irable fealure of a bil slorage block.
0
Q
0
~~
S
R
\~::: :~------- 1
0
Figure 3.1 0 The silUation or S = I and R = I causes problems-Q as il/Oies \\ hen R re!Urn 0
Q
0
to
00.
In a real circuil . the delays or Ihe upper and lower gales and wires lI ould b.! ,tightl~ different fro m one anot her. a after a lime of os illation. one of the gale. ma~ gel ahead of the olher (Ou lpu ll ing a 1 before Ihe other d . then a 0 b.!fore the other on de -, cle.). II ntil it gets rar enough lI hend to cause the cirt'uil I enler a ~Iable siluati n of ither OaO or 0= I-which case will happen. li e don'l knOll . u 'h a ~irualion. in IIh,,-h th· tinal
99
100
Sequential Logic Design-Controllers 3.2 Storing One Bit-Flip-Flops
value of a memory circuit depe nds on the delays of gates and wires, is known as a race condition . Figure 3. 11 shows a race condit ion involving oscillation but end ing with a stable situation of 0: I. But we did n' t know wh ich value 0 wou ld eventually sellie into (it could have settled into 0:0), so Figure 3.11 Q eventually seliles to the fact that 0: I is not useful to us in our use of ei ther 0 or I. due to race condition. the bit storage block. In our fl ighl attendant call -bullon system, if the passenger pushes both buttons at the same lime. the result could be thallhe blue light slarts osc ill ating. and then Ihe lighl either ends up on or off. 5 and R should In summary. Sand R should never both equal 1 in an SR lalch. flt'I'U bOlh equal In practice. we would never aClually conneci buttons directl y to an SR latch's inputs I in all SR lotch (we did Ihal just for the purpose of an intuiti ve example). So we can safely ass ume the S and R inpuls come from a digi tal circuit. Thus. we can desig n that digi lal circuit such thai 5 and R should never both equal 1. BUI even if we Iry 10 design Ihal circuit such thai S and R sho uld never both be 1. we could still fi nd that S and R inadvertentl y bOlh become I at the same time. For example. cons ider the simple circui l in Figu re 3. 12. In Iheory, S and R can' l both be I -if X:l. then 5: ] bUI R:O . If X:O. R may equal 1 bUI 5:0. So S and R can' l both be I -in Iheory. In rea lilY, both 5 and R could both be ] for a short lime in Ihis circuit. because of the delay of real gales. as introduced in Figure 2.62. Suppose X has been and Y has been ] for a long time, so 5:0 and R: l. Then suppose we change X 10 1. 5 wi ll change 10 I almost immediately. but R will stay] for a short while as the new value of Xpro!>, agates Ihrough the inverter and Ihe AND gate, after which R changes to O. If each componenl has a delay of I ns (nanosecond). then 5 and R wou ld aClu ally both be I for 2 ns (Figure 3. 13). Temporary values on ignals ca used by ga te delays are referred 10 as glitches.
a
' . --1J," .'
' ,!.'::-'' "--------
1
Figure 3.12 Conceptually. Sand R can' t both be I in thi' sample circuit. But in reality. they can. due to the delay of the invene r and AND gate.
A
I
~
:
: SA = 11
1~ ' /! :\
o
A
Figure 3.14 Level-sensitive SR latcban SR latch with enable input C.
The introduction of the enable input leads 10 the idea of setting the enable to I only when we are sure that Sand R have stable val ues. Figure 3.15 shows the inverter/AND circuit from Figure 3.1 2, this time using an SR latch with an enable inpu t. If we change X, we should wait for at least 2 ns before setling the enable input C to 1 in order to ensu;:' that the SR inputs to the latch are stable and are not equal to II . Level·sensitive SA latch
S~~ 1
R 0
: '.. _
'
il'--+-----
c~ 1 ; i r IL S1~
:
>2ns Figure 3.15 Level-sensitive SR latch-an SR latch with enable input C.
! ;
o
o
c
: !'
o~
y
S
Level'sensitive SA latch
~'-----------
1
I
I
figure 3 13 Grllc delny' Con cau,c SR = II.
101
S
l---f-, : .L...;;_ _ _ __ Rl 0
, X
A partial solution to this problem is to add an enable input C to the SR latch. as shown in Figure 3.1 4. When C:l, the S and R signal s propagate th rough Ihe two AND gates to the S I and Rl inpu ts of the basic SR latch circuit , because S*I:S and R*I=R. However, when C:O, the two AND gates cause S I and Rl to be O. regardless of the values of S and R. Thus, when C:O, the basic latch 's value cannot change. (You might note that a difference in the lOp and bottom AND gate delays could result in S I and RI both being I for a very short time equal to that difference, but that time is too short to cause a problem.)
An SR latch with an enable is lenown as a level-sensitil'e SR latch . beeau e the lat h is only sensilive to its S and R inpu ts when the level of the enable input is 1. uch a Iat b is also called a transparent latch, beca use setting the enable input 10 1 makes the internal SR latch transparent 10 the 5 and R inpulS. You may have noticed tllal the lOp NOR gate of an SR lalch outputs the opposite val ue as the bottom gale, which i connecled 10 the oUlput O. Thus, we can include an o utput 0' on an SR lalch almost for free , j ust b connecting the top gate to Ihat out put. Mosl latche ' do in faci come with bOlh 0 and 0 ' outpul . The symbol for a Figure 3.16 ymbol for level-sensirive SR IMCh wilh such dual outputs is hown dual-{lU(put 10\ ek nsnh in Fig ure 3. 16. R lalch.
102
3 Sequential Logic Design- Controllers 3.2 Storing One Bn-Flip-Flops
Clocks and Synchronous Circu its ble si nal C that we must sct to 1 a rter we are The level-sensitive SR latch uses an ena gd h to set the enable C to I? Most bi B t how do we decI e w en 5 d R sure an are sta e. U '0 al that ulses at a constan t rate. For example, sequentia l circuits simply use an enableslon, I0 ~s then low for IOns, then high for we could make the enable SIgnal go hIgh for ' 10 ns, then low for 10 ns. etc .. as in Figure 3. 17. Freq.
X. Y safe 10 change must not change X, y
100 GHz 10 GHz 1 GHz 100 MHz 10MHz
/~,
t
elk
o
o
Figure 3.17 An example of a clock signal named elk. Circuil inputs should only change while z 0, such that lalch inputs will be stable when e lk - I .
elk
The time high and time low need not be the same-for example, we cou ld create a . . signal that is low for 10 ns, high for I ns, low for 10 ns. hIgh for I ns. etc . Such a pulsing enable signal is called a clock signal. because the Ignal licks (hIgh, low, high. low) like a clock. A circuit whose storage elements (Ill thIS case. latc.hes) can only change when a clock signal is ac tive is known as a sync hronous sequenttal CirCU li, or j ust synchronous circllit (the sequential aspect is implied-there's no such thlllg as a synchronous combinational circuit). A sequent ial circuit that does not use a clock is caHed an asynchronous circllit. We leave the important but cha llengi ng topic of asynchronous circui t design for a more advanced di gital design textbook . The majori ty of seq ue ntial circ uits designed and used today are synchronous. Designers typicall y use an a ci llato r to generate a clock ignal. An oscillator is a circuit that outpu ts a signal that aitemates between I and 0 at a constant freq uency, like that in Figure 3. 17. An osci llator component typica ll y has no inputs (o ther than power), and has an output representing the clock signal. ~
HOW ODES IT WORK?-OUARTZ OSCILLATORS,
Concept u al l y, a n oscillator can be thought of as an inverter feeding back to itself, as shown on the left. If C is initially 1, the value will feed back through the inverter and so C will become 0, which feeds back through the inver1er causing C to become 1 again, and so on. The oscillation frequency would depend on the delay of the inverter. Real oscillators mu t regulale the oscillation frequency more precisely. A common type of oscillator uses qULJrlZ, a mineral consisting of silicon dioxide in crystal (arm. Quartz happens to be such that it vibrates i( we apply an electric current, and thaI vibration i, at
a precise frequency determined by the quartz size and shape. Furthermore, when quartz vibrates, it generates a voltage. So, by making quanL a specific ,ize and shape and then Oscillator Ie applying a current, we ge t a preci,e electronic o,cillator. We attach the o«illator 10 an IC', clock slg"al input, a' shown above. Some IC, come with a built-Ill osci liator,
Period 0.01 ns 0.1 ns
1 ns 10 ns 100 ns
103
. A c lock signa l's period is the time after which the signal repealS ilSelf-or mare SImply, the tllne between successive Is. The signal in Figure 3.17 has a period of20 ns. A clock cycle refers to one such segment of time. meaning o ne segment where the clock IS 1. and then O. Fig ure 3. I 7 shows th ree and a half clock cycle. A clock signa)'s frequ ellcy IS the number of cycles per second, and is compu ted as I/(the clock period). The slgn~1 III F,g ure 3. I 7 has a frequency of 1/20 ns = 50 M Hz. The units of frequency are Hert z, or Hz, whe re I Hz = I cycle per second. MHz is short for Megahertz_ meaning one mdl'on Hz. . A convenient way to menta lly convert common computer clock periods to frequenc Ies. a nd VIce ve rsa, IS to remember that a I ns period equals a I GHz (Gigahertz, meanll1g I bIllI on Hz) frequency. Then , if One is slower (or faster) by a factor of 10. the other is slower (or fas ter) by a fac tor of 10 a lso-so a 10 ns period equals 100 MHz. whde a O. I ns period equals 10 GHz.
D Flip-Flop While the SR la tch is useful for introd ucing the notion of storing a bit in a digital circuiL most c irc uits actua ll y use slightly more advanced devices. namely. D latches and D llipnaps, to store bi ts. Level-Sensitive 0 Latch-A Basic Bit S tore
Olaleh
The SR latch has the an noying problem of entering all unde fined tate if the 5 and R inputs are both I when the clock is high. Ensuring that we desig n c ircuits that don 't set 5 a nd R to both 1 imposes a burden on the deSigner. One way to relieve designers o f this burden is to instead u e a new type of latc h. called a D latch . shown in Figure 3.1 8. A D latch sto res whatever value is present at the la tch's D input when C= 1. a nd holds that val ue when C = O. Internally. the latch's D input connects to 5 d irectly. a nd to R through an inverte r. Fig ure 3. I 9 provides a timing diagram of the D latch for sample input values on D and C. When D is I a nd C is 1. the latc h is et to 1. because 5 is I and R is O. When D is 0 and C is 1. the la tch is reset to O. because R is 1 a nd 5 is O. By making R the opposite of S. we are ass ured that 5 and R won 't both be I at the sa me time. as long as we ani c hange 5 and R when C is O.
Figure 3.18 D latch internals.
R
o
0--+---,
o
Figure 319 D Iat
104
3 Sequenlial Logic Desig n- Controllers 3.2 Sloring One Bit- Flip-Flops
The symbol fo r " 0 lalch wilh dual-oUlpU IS (0 and 0 ') is shown in Figure 3.20. Figure 3.20 D larch symbol.
--fo+
o lalch
~
Edge-Triggered 0 Flip-Flop-A Robust Bit Store The 0 latch slill has a pOlentially nasly problem Ihat can Ca use unprediclable circuil behavior- namely_ signals can propagale from a lalch OUlpul 10 an olher lalch's inpul while the clock signal is 1. For example, consider Ihe circui l in Figure 3.2 1. When e lk = I. Ihe va lue on Y wi ll be loaded inlO Ihe firsl lalch and appear al thaI latch's output. If ( 1 k slill equals I. Ihen Ihat value will also gel loaded into Ihe second latch . The value wi ll keep propagating Ihrough the latches umi l (1 k returns 10 O. Thro ugh how many la tches will the value propagale? It 's hard 10 say-we would have 10 know the precise tim ing delay information of each lalch.
Clkt==================--.J '---'--'---(a)
Clk~
01
0 2 02
03
03
04
_ _-..J
r , Too short-ol
01
0 1102
--.l '
01 /02 _ _ _ _ _ __
S2_______
S2===:t,)SR= 11
R2 _____________
02~dlalChsel 01
-
Clk ~e
01
R2
y
o latch
(b)
04
0 2 _ _ _ _ _ __ (e)
Figure 3.22 A problem wilh level-sensitive lalches: (a) while C~ 1. 01 's new value may propagale 10 D2. (b) such propagation can cause S2 and R2 10 both be 1 for a shan time while the latch 's enable is 1 (bul SR ~ 11 is never supposed 10 occu r). or can cause an unknown number of latches along a chain 10 gel updaled, (c) Irying 10 shonen Ihe clock's high lime 10 avoid propagalion 10 the neXl lalch, bUI long enough 10 allow a lalch 10 reach a slable feedback silualion. is hard. because making the c1ock's high lime 100 short prevents proper loading of the latch.
=-.....=_--l
Clk .....----+-__
Figure 3.21 A problem wilh lalches-through how many Ialches will Y propagale for each pulse of Clk_A ? For Clk_B?
Figure 3.22 ill uslrates Ihis propagat ion problem in more delail. Suppose 01 is inilially 0 for a long lime, changes 10 1 long enough 10 be stable. and Ihen C1 k becomes I. 0 1 wi ll th us change fro m D 10 I after aboul Ihree gate delays, and Ihus 02 will also change from 0 10 1. as hown in Ihe left timing diagram. If C1 k is slill 1. then thaI new va lue for 02 wi ll propagale through Ihe AND gales of Ihe second latch. causing S2 10 change from 0 10 1 and R2 from 1 10 D. Ihus changing 02 fro m 10 I, as shown in the left IlmlOg diagram. Also nOle in the left liming diagram that changing 02 whi le C2-1 causes S2 and R2 10 both equal 1 for a short lime, due 10 Ihe extra delay on the palh 10 R2 cau ed by Ihe Inverter. Ihough Ihe lime thaI bOlh are I is probably 100 short 10 cause a prob lem.
a
You mighl suggesl maki ng the clock signal such thaI the clock is I onl y for a shan amount of tl,,;e .. so there's nOI enough li me fo r Ihe new OUIPUI of a lalch 10 propagate 10 Ihe nexl lalch s mpulS. BU I how short is shan enough? 50 ns? IOns? Ins? 0. 1 ns? And if we ~ake Ihe clock's time m I 100 short, Ihat li me may nOI be long enough for the bit al a lalch s 0 mpullo Sl~btl l z~ m Ihe lalch's feedback circuil . and we mighl Iherefore nOI successfully Slore Ihe bll , as tl luslraled in Figure 3.22 (c).
A good solution is 10 des ign a more robuSI block fo r storing a bil- a block that stores Ihe bil al Ihe 0 inpul at Ihe illslalll lhal the clock rises from 0 10 1. Note thaI we didn 't say thaI the block Slores the bil inslantly. Rather, the bit thaI wilJ eventually get slOred into the block is Ihe bil Ihat was slable at 0 al Ihe inslal1l Ihal Ihe clock rise from to 1. Such a block is ca lled an edge-Iriggered D flip-flop . The word "edge" refers 10 the vertical pan of Ihe line representing the clock signal, when the signal !Tansirions from 10 1. Figure 3.23 shows three cycles of a clock signal. and indicales the Ihree ri sing Figure 3.23 Risi ng clock edges. clock edges of those cycles.
a
a
Edge-Triggered D Flip-Flop Usillg a Masler-Serllalll Desigll. One \\'a 10 design an edge-triggered D flip-flop is to use 111'0 D latches. as shown in Figure 3.24. The first 0 lalch. known as the mOSIer. is enabled (can slore new val ue on Om) \I hen C1 k is (due 10 the inverter). while the second D latch. known as the sen ·OIll. is enabled when C1 k is 1. Thus, while C1 k is O. Ihe bil on 0 is slOred into the masler lal h. and hence Om and Os are updaled- bul the servant latch doe nOI lore this new bil beenu Ihe serva nl latch is nOI enabled ince C1 k is nol 1. When C1 becomes 1. the mn ter
a
105
106
3 Sequential logic DeSign- Controllers
,
o flip·flop o lalch
o
Om
Om
o lalch Os
Os'
0'
Os 0 servant
,
Clk - - r - - - L ~O/Om
..'--,
i
Cm Om/Os
Cs
Os _ _ ---,c-'
Figure 3.24 A D fli p- flop implemenling an edge-lriggered bil slomge bolOCk. in l e r~a:I Ycut~ng ~w~ latches in a master-servan t arrangement. The master D i3lch slores 1,IS m Input W I e : : : : , UI lhe new va lue appearing al Om and hence al Os does 1101gel slored mlo the servant latch. because the servanl lalch is disabled when elk = O. When elk becomes 1. Ihe servanl D lalch becomes enabled and Ihus gelS loaded wilh whalever value was in Ihe mas'er lalch JUSI before elk changed from 0 10 1. latch becomes disabled (relai ns ils stored value), thus hold ing whalever bit was at the 0 input j usl before the clock changed from 0 to 1. Also, when elk is 1: the servant lalch becomes enabled. thus storing the bil that the master IS stonng. wh ,ch 's the bll thaI was al the D inpu l jusl before elk changed from 0 to I-hence implementing an edge-triggered storage block. The edge-triggered y 01 01 02 02 block using two inlernal 03 03 latches thus prevents the stored bi t from propagating thro ugh more Ihan one elk ....-===::.....~==::.....~ lalch when Ihe clock is 1. Consider the chai n of flip Aops in Figure 3.25. which is simil ar to the chain in Figure 3.25 Using D Rip-flops. we now know through how Figure 3.2 1 bUI with 0 Rip- many Rip-Rops Ywill propagale for C1 k_A and for C1 k_Bfl ops in place of 0 lalches. one Rip-Rop exaclly per pulse. for either clock signal. We know that Y will propagate Ihrough exactly one Rip-flop on each clock cycle. The drawback of a maSler-servanl approach is that we now need two 0 lalches 10 store one bit. So Figure 3. 25 shows four Rip-Aops, but Ihere are IWO latches inside each Aip-flop, for a tOlal of eight lalches.
__----'
The common
name ;s actually "master-slave... Some clroou insll!ad to use the term "servant "
due 10 some people finding lire
term "slave " offenSive. Others use the turns "primary.ucondary. "
There are many ahemati ve methods other Ihan the maSler-servant method for designing an edge-triggered Aip-Aop. In fac t, Ihere are hundreds of different designs for latches and Aip-flops beyond the designs we showed above, with those designs differing in lenns of their size, speed. power, etc. When we use an edge-triggered Aip-nop, we usually don'l worry aboul whether the flip-flop achieves edge-triggering using Ihe masterservant melhod or using some olher method. We need only know that the f1ip-Rop is edgetriggered, meaning the data value present when the clock edge is rising is the value thai gets loaded into Ihe flip-Aop, and that appears atlhe flip-fl op's outpul some time later.
-
-_._---
3.2 Sloring One Bit- Flip-Flops
107
We'~e aClually been describing whal's known a.• positive Or risillg edge-triggered flipAops. wh,ch are Inggered by Ihe clock signal going from 0 10 I. There are also Aip-Aops known as lIegati,'e or Jallillg edge-lriggered fl ip-ft0l s. which are triggered by Ihe Signal gOll1g from 1 10 O. We can build a negalive edge-triggered 0 flip-llop usi ng a maSler-servalll deSIgn where Ihe second fl ip-fl op 's clock inpul is invened. rather than the fi rst fli p- Aop 's. Posi tive edge-Iriggered fli p- fl ops are drawn using a small triang le al Ihe clock inpul. and negative edge-Iriggered fli p-flops are drawn USing a small Iriangle along wilh an in version bubble. as shown in Figure 3.26. Bear in mind thar all hough Our maSler-scrva l1l design doesn'l change Ihe output unlil Ihe railing Figure 3.26 Posili ve (shown on lhe clock edge. Ihe fl ip-fl op i slill po ilive edgeleft) and negalive (righl) edgeIriggered. because Ihe fl ip-flop Slores Ihe value Ihal Iriggered D fl ip. flops. The sideways was al Ihe 0 inpul al Ihe in' Wnl thm Ihe clock edge
In ill
j
riSing.
rriungle input rcprescnls an edge-
Iriggered clock inpul.
Latches ,'ersus Flip-Flops: Various lex lbooks defi ne the temls latch and fli p-nop differently. We'lI use what seems to be the mOSI common convention among des igners. namely:
A latch is level-sensilive. and • A jlip-jlop is edge-Iriggered.
So saying "edge-Iriggered flip-Rop" is redundanl , since flip-fl ops are by defin ilion edge-triggered. Li kew ise. saying "Ievel-sensilive latch" is redundant. since latches are by defi nili on level-sen ili ve. Figure 3.27 uses an example liming ,, diagram 10 illuslrale the di fference belween , level-sensili ve and edge-Iriggered bil IOrage blocks. The fig ure provides an example of a clock signal and a value On a signal D. The nex t signal trace is for Ihe 0 OUIPUI of a 0 larch, which as we know is level-sensili ve. The lalch ignores Ihe firs l pulse on D(labeled Q (0 latch) a 3 in the fi gure) because elk is low. However, when elk becomes high (I), the latch 0 (0 flip.flop) f oUIPUI follows the D inpul , so when 0 :9 10:fr--changes from 0 10 1 (4), so does the latch OUlpul (7). The latch ignores Ihe nexl changes on 0 when elk is low (5). but then Figure 3.21 Lalch versus flip-Rop liming. follows D again when elk is high (6, 8). Compare this wilh the nex l signal trace. howing the behavior of a rising-edge-triggered 0 Aip-fl op. The Aip-fl op amples D at the fi r t ri ing clock edge (I). fi nding 0 to be O. The flip-flop thus slores and oUlpul a 0 (9). The Rip-fl op amples 0 al the next rising clock edge (2). finding D 10 be 1, and thus stores and outputs a 1 (10). Olice that the Ripfl op ignores all changes 10 0 Ihat occur belween Ihe ri ing clock edges (3. -1. 5. 6)-even ignoring changes On 0 when Ihe clock is high (4. 6).
Clk~
O~
,
i
108
3 Sequenti al Logic Design- Controllers
EXAMPLE 3.1 Flight attendant call-button uSing a D fl ip-flop Lei· ... dc\i gll ollr ni el ill ,lItcm.lant cu ll -bullon system lIsing a D
3.2 Storing One Bit- Flip-Flops
TABLE 3.1 0 truth table for call-button system.
flip-nop. If Ca 11 e i~ prcs:-.cd. we wanl 10 store a 1. If Cance 1 i ~ prc',cd. \\ C \\Iu nl !oo lo re n O. If neither is pressed, we W;J1l1 to siore whatever i, prcscnll y Siored. meaning O. \Vc Ihu, I1c~d ;1 , imp/c l'olnbin:.Hiollal circuit in fron t of the 0
inpul. dc,cribe
Level-sensitive 5R lalch
Ca ncel
0
0
o latch
0
0
0
0
Om Om
0
0
)
)
lowing eq ual io n for 0:
D B Cancel ' 0 + Call
0
)
0
0
)
)
0
)
0
0
)
Problem:
1
0
1
)
5R=11 yield undefined O.
)
1
0
1
1
1
)
)
o flip-flop Olalch Os Os, O' Cs Os 0
0
B
Aner ~OIl1 C algebraic liimplific:l.lion. we obtain (he fol-
o lalch
5
Ca II
Fealure: 5 =1 Fealure: 5 and R only sels 0 101 , R=I have eHecl when C=I. resels 0 10 O. We can design oUlside
circuil so SA:: 11 never
happens when C=I . Problem: avoiding 5R=11 can be a burden.
Fealure: 5R can'l be 1/ if 0 is slable before and while C= I , and will be II for only a brief glilch even if 0 changes while C=l . Problem: C=I 100 long
Fealure: Only loads 0 value presenl al rising clock edge, so values can'l propagate 10 olher flip-flops during same clock cycle. Tradeotf. uses more gales inlernally Ihan 0
propagates new values
lalch. and requires more
Ihrough 100 many lalches; exlernal gales than 5R- but too Short may nOI enable gate count is less of an issue
The final !
a slore.
loday.
Figure 3.29 Increasingly better bit storage blocks. leadi ng to the 0 flip-llop. The D flip-fl op-based design uses more gates tha n Ihe SR lalch-based in Fig ure 3.9 (w hich could have just as eas il y used an SR fl ip-flop) . One reason ror the exira gate!' is Ihal a D flip- fl op always slores ils D inpul on every c lock cycle, so we muSI explicil ly feed 0 back inl o D 10 mainta in the same va lue. In contrast. we could just SCI S=R~O 10 mainlain Ihe same va lue wilh an SR flip-fl op. Furthermore. we must convert Ihe bU lion presses 10 the appropriate D inpul value, requiring ext ra logic. rather than just cuing ei ther 5 or R 10 1. In Ihe late 1970s and
earl y I 980s. Ihose ex tra gates were a big deal. beca use ICs came with just a
Call ,--, burton Cancel button
_-'
Flight altendant call-button system (a)
Call button Cancel button
Basic Register-Storing Multiple Bits A reg ist er is a sequcn lia l componen l thai can store multiple bits. We ca n bui ld a basic reg isler simply by us ing multi ple fli p-flops, as shown in Figure 3.30. That reg ister can hold 4 bi ts. When the clock rises, all 4 fli p-fl ops get loaded wi lh inpu ts 10, 11. 12, and 13 si multaneously. 13
12
f1
(b)
Figure 3.28 Flight attenda nt call -button system: (a) block diagram. and (b) implemented using a o fli p-flop.
few gales on Ihem , so extra gales often meant extra ICs, meaning ex tra size, cost, power, etc. But today, in Ihe era of mill ion-gate ICs, the savings of an SR flip-fl op are trivial. In modern des ign. nearl y all designs u e D flip-fl ops, not SR flip-fl ops. As a poin l of informal ion, deSigners commonly refer to fl ip-fl ops simply as flops . We wenl Ihrough several inlermediale designs before arri ving at our robust D flipfl op design for Our desired bil storage block. Figure 3.29 summ arizes those designs, including Iheir features and their problems, leading to the robust edge-triggered D flip-flop . In look ing Over the summary, notice that the D flip-fl op reli es on an internal SR lalch to mai nt ain a stored bil be/ ween clock cycles, and re lies on the designer to introdu ce feed back outs ide Ihe D fl ip- fl op to mai ntain a stored bit fro rn aCIVss clock cycles.
109
01
00
Figure 3.30 A basic 4-bit register internal design (left) and block symbol (right). This register, made simply from multi ple fli p- fl ops. is the mo t basic fornl of a register-so basic that some companies refer 10 s uch a register simply as a "4-bit D fl ipfl op." We' ll describe more advanced regislers, namely, registers with more feat ures and operations, in Chapter 4.
EXAMPLE 3.2 Temperature history display using registers We Want to design a system that records the outside temperature every hour and displays the last three recorded rcmperalUrcs. so thai an observer can see the lcmpermure trend. An architecture of
the system is shown in Figure 3.3 J. A timer generales a pulse on signal C every hou r. A tel11pera!u~ cnsor outputs the prese~I
lemperature as a 5-bit binary number ranging from 0 to 31 . cOlTespo~dtng to those temperatures Celsius. Three display COIll'e l1 Iheir 5-bit binary inputs into a numencal dtsplay.
tn
110
3 Sequential logic Design- Controllers 3.3 Finite-State MaChines (FSMsl and Controllers
111
This example dcmollSlrnres one of Ihe grea t things lIbOU I synchronous circuits built from edgetriggered nip-nops-many Ihings happen at once. yel we need nOI be concemed aboul signals propagating
))) Figure 3.31 Temperatu re hislory display syslem.
[00
fast through
II
register to nnOlher register. The rcason we need nOI be concerned is
because registers ollly gel loaded 011 lhe rising clock edge. which effectively is an infinitely small period of lime. so by fhe lime signli is propagate through a register to a second regislcr. it's too laIc-that second register is no longer paying attention to its data inputs.
TemperalureHistoryStorage
timer
C
We should mention that , in practice. designers typically try to avoid connecting any signal other than an oscillator ou tpul to the clock input of a Rip-flop or register. So in practice. we might Iry to avoid connecti ng the signal C to the registers' clock inputs, since C comes rrom a timer output, not an osci llator. We' ll show in Chapter 4, Example 4.3, how to des ig n a s imi lar ys tem using an osci llator ror the clock.
avoid connecting the timer output
(In practice. we would actually ( 9 an oscillator output to a clock input.)
C to a clock input, instead only connec In
. S" componen t usin o three 5-bil registers, a ·1/ Ill > prese~t teml>era ture on inputs .. 31 E I I' signal C loads a WI 1 " shown In Figure ~. _. ~c 1. pll se 0.11 . R . I the 5 input bits). At the same time that register x4 . . xO (by load lllg the) flip-naps IIlslde a W.1t 1 Rb octs loaded with the value th at was in Ra. Ra 2CIS loaded wi th that present tempera ture. reglstc~ d Ol · ';]1 the sam e time namely on the \'Ve can implemen t the Temperal/lreHlsfOl)' IOIfI!fR'
Lik;wisc. Rc gels loaded wilh Rb's value. Alllhree
Oil s lappen In Ra and Rb
rising edge of C. The errect is [hat th e v:ilucs that wcre shifted illlO Rb and Re. respec ti ve ly.
---------
04 03 02 01 00
a4 a3 a2 al a0 r - 14 04 13 03 12 02 It 01 10 00
r~
r~
,----
f-:-1 4
~13 ~12 ~It
Figure 3.32 lnlemal design of (h e TemperalllreHiSlory Storage com ponent.
~IO xO
c
.
re Ih; clock
Just befo
b4 b3 b2 bl bO , - - - 14 13 12 tl 10
cd e
et
g g
c4
c3 c2 cl cO
04J03 I - 02 ~ 01 00
I~ TemperatureHistoryStorage
Fieure 3.33 shows sample values in Ihe regislers for several clock cycles, assuming all ihe reg-
isters i~itially held Os. and assuming that as tim e proceeds the inputs x4 .. xO have the values shown al th e (OP of rhe timing diagram .
3.3 FINITE-STATE MACHINES (FSMS) AND CONTROLLERS Registers store bits in a dig ital circuit. Stored bits means the circui t has memory, also known as slale. resulting in what are known as sequential circuits. While a register storing bits happens to result in a circuit with state. we can ac tually use state to design circuits that have a . pecifi c behavior over time. For example, we can specifically design a circuit that o utputs a 1 for exactly three cycles whenever a button is pressed. Or we cou ld design a circuit that blinks lights in a specific pattern . Or we could design a circuit that detects ir three buttons get pushed in a particular sequence and that then unlocks a door. In all the e cases. we wo uld be making use of sta te to create specific time-ordered behavior for Our circ uit. A sequential circuit that controls Boolean Ou tpulS based On Boolean inputs and a specific time-ordered behavior is often referred to as a cOlllroller.
EXAMPLE 3.3 Three-cycles-high laser timer-a poorly done first design Consider the design of a pan of a laser surgery syslem. such as a syslem for scar removal or correc tive vision. Such systems work by turning On a laser for a precise amounl of time (see "How doe it work ?laser surgery" on page I 12). A general archilec ture of such a system is hown in
Figure 3.34. A surgeon activates the laser by
Figure 3.33 Example of va lues in the
Temperolure Hislory Storage registers. One
panicuJar daw item ) J 8, is shown moving through Ihe regiSlers on each clock cycle.
Ra Rb Rc
clk patient
Figure 3.34 Laser timer system. pressing the bUllon. Assume Ihe la er . . should Ihen Slay on for exaclly 30 ns. Assuming our clock 's period is 10 ns. 30 ns means 3 clock cycles. (Assume thai b IS synchroruzed with the clock and Slays high for onl y I clock cycle.) We need 10 design a controller component Ihal. once delecting Ihal b ~ I. holds X high for exactly 3 clock cycles. thus luming on the laser for exaclly 30 ns. . . This is one example for which a software solution may nol work. USlllg JUSI regular programming statements reading inpul pons and wriling OUtpUI pons, we may nOI have a way 10 hold an OUlput pan high for exaclly 30 ns-for example. when Ihe microprocessor clock frequency IS not fasl enough. or when each slalemenl takes 2 cycles 10 execule.
112
Sequential log ic Design-Conlrollers
J.J Finite-Slate Machines IFSMs) and Controllers
Let's try to crea te a sequential circuit implementation for the system. After th inking about the problem for a while. we miglll come up with the (nol so good) implementation in Figure 3.35. Knowing we need 10 hold the output high for three clock cycles, we used three flip-flops. with the idea bein!! that we'll shift a I throu gh those three flipflops. taking three clock cycles for the bit (0 move
lhrough all lhree flip-naps. We ORed the nip-nap outputs 10 generate signal x, so Ihal if any flip-flop comains a 1. the laser will be on. \Ve made b the
In the previous chapler, you. saw Ihal we cou ld design a combinational circuit by first descnbmg the deSired CirCUli behaVIOr using a malhematical formalism known as a Boolean eq uation , and then converting the equation 10 a circuit. For a sequential circuit. a Boolean equatIOn alone is not sufficient 10 describe behavior-we need a mOre powerful malhematlcal formali sm Ihal incorporales lime.
clk
Figure 3.35 Firsl (bad) allempl 10
Finite-slale machines (FSMs) are jusl s uch a method. The name is a bil but Ihe concepl is straighlforward . An FSM consists of severa l Ihings, the mOS I Imponanl of wh ich IS a sel of states representing every possible stale, Or mode, of a system.
awkw~rd ,
implement Ihe laser surgery syslem.
inpu l lO the firsl flip-flop. so when b= 1, the firsl nip-Hop Slores a 1 on Ihe nex i clock cycle. One (0 0, Ihe firsl flip-flop will gel loaded with O. One clock cycle Imer. Ihe third flip-fl op wi ll gel loaded wi!h 1. and Ihe second flip-flop wilh O. One clock cycle Ialer, Ihe Ihird nip-flop wi ll gel loaded wi!h O. Thus. the circuit held the aUipul X at 1 for three clock cycles after the bulton was pressed. clock cycle Imer. the second flip-fl op will get loaded with 1, and assuming b has now returned
~
~··:'-d . ·~I .1 "
_
. "
".
The prel'iolls example illllsrra,ed rhe need for a way of describing 'he desired behol'ior of a sequential cirr;ui,.
~
We did nOI do a very good job implementing this syslem. First of all, what happens if the surgeon presses the button a second time before the three cycles are completed? Such a situation could cause the laser 10 Slay on 100 long. Is Ihere a simple way to fix our circuit to accounl for that behavior? Second, we didn'l use any orderly method for designing the circuil-we came up with the ~Ring of nip-flop OUlputs, bUI how did we come up wilb that? Will thai merhod work for all lime-ordered behavior that we mighl wan l 10 design? We need IWO Ihings 10 do a bener job al designing circuilS having time-ordered behavior. Firsl, we need a way 10 explicitly represenlthe desired time-ordered behaviorwe' ll introduce the finite -slale machine represenlation for thi s purpose. Second, we need an orderl y method for implemenling such behavior as a sequenlial circ uit-we' ll introduce such a standard method.
.
-
-
.
.
1
'. i
'
1.like 10 u~e my daughler's hamsler as an intuitive example. After baving a hamster as a family pel, I ve learned Ihal hamsters basically have four stales: Sleeping, Eating, Run IIlIIg 011 The Wheel, and Try illgToEscape. They spend mOSI of their day leeping (being nocturnal), a bit of tllne ealing or running On the wheel, and the rest of their time desperalely Irylng 10 escape from Ihei r cage.
As a more electronics-oriemed example, lei 's design a system thai repealedly sets an OUlpul X 10 0 for one clock cycle and 10 1 for one clock cycle. The syslem clearly has on ly two states, which we' ll ca ll Off and Oil. In slate Of(, X = 0; in stale 011_ x = 1. We can show Ihose slales, and the transilions between them , usi ng the state diagram in Figure 3.36.
~~~~ Outputs: x
clk cycle
Outputs:
~
I I
I I
I
t
I I
i
i
!
i
hcycle 2 hcycle 3 hcycle 4 i
1
slate~
HOW DOES IT WORK?-LASER SURGERY.
Laser surgery has become very popular in the pasl decade, and has been enabled due 10 digilal syslems. Lasers. invented in Ihe early I960s, generale an intense narrow beam of coherenl light with pholOns having a single wavelength and being in phase (like being in rhythm) wilh one another. [n contraS!, a regular light's pholons fly OUI in all directions. with a diversily of wavelengths. Think of a laser as a plaloon of soldiers marching in synch, while a regular lighl is more like kids running oul of school althe end-of-theday belL A laser's lighl can be so inlense as 10 even CUI steel. The ability of a digilal circuilto carefully control the location, intensilY. and duralion of the laser is whal makes lasers so useful for surgery. One popular use of laser for surgery is for Scar removal. The laser is focused on the damaged cells sljghlly below the surface, causing Ihose cells 10 be
vaporized. The laser can also be used 10 vaporize skin ceUs !hat fonn bumps on Ihe skin. due 10 scars or moles. Similarly. lasers can reduce wrinkles by smoothing ille skin around the wrinkle to make the crevices more gradual and hence less obvious, or by stimulating lissue under Ihe skin 10 slimulale new collagen growth. Another popular use of lasers for surgery is for cOlTecling vision. [n one popular laser eye surgery method, the surgeon CUIS open a fl ap on the surface of Ihe comea_ and Ihe la er Ihen reshapes the cornea by thlOnlOg Ihe cornea in a panicular pallem, with such IhlOmng accomplished Ihrough vaporizing cells. A digilal syslem conlrols the laser's localion, energy, and dural ion, based on programmed informalion of the d~Slred procedure. The availabilily of lasers, combined wuh low-coSi high-speed digilal circui ts. makes such precise and useful surgery now possible.
---- - -
113
Finite-State Machines (FSMs)
X
I
I
,
I
--r--1---J!
Figure 3.36 A simple slale diagram (len) and Ihe timing diagram de cribing the state diagram's behavior (ri ght). Above the timing diagram. we see the FSM going from one
Sl'ate 10
the other in
each clock cycle. "e 1 k A" represenls Ihe rising edge of the clock signal. Assume we Slarl in Slale Off. The diagram shows thai x is set 10 0 while the y lem is in Slale Off. The diagram also shows thai on Ihe neXI rising edge of the clock signal . C/kA, the syslem Iransilions 10 Slale 011, and the diagram shows thul i el 10 I in Ibal Slale. On the next rising edge of the clock, [he diagram shows lhal the y "lem tran ilions 10 slale Off again . A l.iming diagram showing the sy lem' beha,~or i hown in Figure 3.36. Recall in Example 3.3 thai we wan led a syslem Ihal held ils OUrpUI high for three cycles. Toward that end. lel's extend the simple Sime diagram of Figure 3.36 I ha\e on off Siale and three on slales, as shown in Figure 3.37. The OUIPUI will be 0 for one C) -Ie.' and Ihen 1 for Ihree cycles. as shown in the liming diagmm of the figure.
Sequential Logic Design- Controllers
Outputs: x
=o
3.3 Finite-State Machines (FSMs) and Controllers IkA
1
~ elkA x=1 Onl
Off
~
elkA~ ~~3 ~
~
elk
JUULJLILJLJLJl-
EXAMPLE 3.4
We can create an FSM to describe Ihe earlier introduced laser timer system. The system might have four states: Off, all / , 0112. and On3. In the Off state, the laser should be off (x -D). The anI state wo uld be the first clock cycle the laser is On (x - 1), On2 the second cycle, and On] the third cycle. The state dIagram of Ihe FSM is in fact identical to that shown in Figure 3.38. . Here's how Ihe FSM shou ld be interpreted. We start in our initial state Off. We stay in state Off until One of Us two outgoing transitions has a true conditi on. One of those transitions has the condition of b' AND rising clock (b ' *c1 kA)-in Ihal case, we transition right back to state Off. The other of Ihose transilions has Ihe condi tion of a b AND a rising clock (b*c 1 k A)-in that case, we transitIOn to Siale 0111. We Slay in Slale a,,} until its one outgoing transition 's condition. a rising clOCk. becomes true-in which case we transition to stale On2. Likewise, we stay in On2 until the ~ex( riSing clock. Iransilioning to 0113. We Slay in 0,,3 until the next rising clock. causing a transitIon back 10 slate Off. In stale Off. we have associaled the action of setling x-O, while in states anI, 0112, and On3, we have associated the action of selling X= 1.
State@ff lonl ;on2pn310ff lonlpn2 iO n310ff l
~
Outputs:
-.J
U
L
x
. 'He diaornn1 (left). timing diagr:111l (ri ght ). Fi ure 3.37 Three-cycles-hi gh system. st. 0 . g 'ti ons 10 funh e r ex tend the behaV ior. . ditions on the LranSI .. . '. 38 b hanoin o the condillOn on the tra nSition We can introduce Input con . 11 in F, oure 3 Y c ~" . " I k d' We ex tend the stat e wgn.lI e Ih~ new cond ition require s not Just a n S I ~l? CDC, fro m state Off to stale ani. such that.. f OljJback to Off. wi th the condlLlon ofa dd a tranSillon rom ' d . . the fi oure shows the state an outpUt but also that b= 1. VIIe a Iso a . ' " . . . d b=O The liming diagram Ill . rlSlIlg clock an . '. values on b. behav ior for the given IIlput
elk Inputs: b
Thus. we have precisely described the desired time-ordered behavior of the laser timer system
using an FSM.
JLJLJLJllJuLl ,,
rn
/t 's inleresting to examine the behavior of this FSM if the button is pressed a second time
,,
while the laser is on. No[ice thm the lransilions among the On sta tes are independent of the value of
b. So this system will always lurn Ihe laser on for exactly three cycles and then return to the Slale 10 awail another press of the bUllon.
1
'
i
I
L
I I I I jonl:on210n~ Off I
Srate !Off Off Off Off Off Outputs:
-------------"
. h system.. state diaorom (left), liming diagram (right). Figure 3.38 Three·cycles·hlg e
A set of states. Aur ex a mple had four states: {Onl. On2, 01/3,. Offl· . A set of IIlputs, and a set 0 f outputs. Our example had one IIlpllt: {b }, and one output: {x }. -' al tate, name Iy, a s tate to stan in . when we power An .Illili d ' up dthe d ystem. . h An . ' al tate can be .In d I'cated graphically by a ;lIlgle ItCCle e ... ge, Wit FSM 's .IIllli , I no . ' '(al source state , Ihat pOint to t he 1111 I . tate . An FSM can only have one IIltlia state. Our example's initial stale was Off. . ' on 0 f Ihe nex t sa t te to go 10 based on the cu rre nt sta .le and thedva.l A deSCripti ' . ues of lhe inputs. ur exam p Ie u.sed directed edges. .with a,wciated "Input carr. IflOns to tell us Ihe nex t state. Those edges wilh condil lon arc known ,l~ trlll/Slfrorrs. _
.
a
'
. . of what OUlput values 10 generate in each Mate. Our exa mple a signs A d eSCrlplion . M ' .. Ii a value to X in every slate. Assigning an outpU I In an FS "nown as an ac on.
.1\
VII sed a graphical represenlation of an F M. kn own a slale diagram , to ho" e ufo r our exa mp Ie. We co u ld have repre5ented the FSM " the F M lex luall y lIl'tead. but stale diagram~ arc very popular for visualiting an FSM , hchavlOr.
Off
Simplifying FSM Notation: Making the Rising Clock Implicit
,
macilirr e, or FSM, is a mathFrom the above examples. we can see that . ajirrile-slate . emalical fomlalism consisLing of several things.
115
FSM for the three-cycles-high laser timer
a"clkA
(J+D a'
C:r-D
Thus far, we have included the rising clock edge (c 1 k A) as pan of the condition of every FSM transi tion. We included that edge because we are onl y considering the design of sequential circuits that are synchronous and that use rising edgetriggered Rip-Rops to store bits. Synchronous sequential c irc uits with edge-triggered Rip-Rops make up the Vast majority of sequential circuits in modem design practice. As such, most textbooks and designers, to make their state diagrams more Figure 3.39 readable, follow the convention lhat every transiassuming every tmn irion is ANDed tion in an FSM is implicirly ANDed with a rising with a rising clock . c lock edge. For example, a transition labeled "a '" ac tua ll y means "a' *c1 kA." Hencefonh. we will not include the rising clock edge when drawing FSM transitions, and we will follow the convention that every transition is
~ "STATE" I UNDERSTAND, BUT WHY THE TERMS uFlNITEu AND "MACHINE? . FinilC-Slate machines, or FSMs. have a mther "machine" is used in irs mar.hematical or computer awkward name th m sometimes causes confusion. The science sense, being a concepTUal object that can term "finite" is there 10 contrast FSMs with a similar execute an abSlr3et language--specificaJl . that sense representation used in mathematics Ih31 can have i.U1 of machine is not hardware. Finite- tnte m3ClliMs are infinite number of stliles; Ihal represenlmion is nOI also known :IS jinile-S14U aUlolfllJllJ. FSMs ~ used very useful in digilal design. F Ms, in contmst. have for many things other than just digilllJ design. n limiled, or finite, number of SIUI.S. n,e lem,
116
Sequential Logic Design-Controllers
3.3 Finite·State Machines (FSMs) and Controllers
• ' do Fioure 3.39 illustrates the laser timer state implicitly ANDed wiLh a nSlllg clock c ~e. . " ,. . lock d sino an Imp Jell C . diagram fro m Figure 3..l0. re rawn u ~.. . ply tra nsi tions o n the next clock cycle, A transition-with no assoc iated condlllon slIn . ' .
0----0
because of the impl ici t rising clock edge. . ho v 10 describe lime-ordered behavior Let's consider a rew more examples shOWing \ using FSMs.
EXAMPLE 3.5
Secure car key
. . ew aUlOmobiles have ::J thicker plastic h ea~ t~ a~ III the H<1 ve you nOllced... that Ihe keys for J~lan). 11 believe it or 11 0 1, there is a computer chi p IIlslde the past (see Figure .lAO)? Th~ reason IS th~I., In n basic version of suc h a secure car key, when (which is under the hood and commuhead of th e key, implemcntll1g a secure car ke~, the driver tums the key in the ignition, the car s com puler . 'onal aski ng the car key 's chip to h b {'OI) sends out a ra d 10 510 .. nicates using what's ca~led t, e a~esta ' ~ '0 The chi in Ihe key then responds by sending respond by sendin g an Identifier via a rad iO sIena!. P s onder ;'transmits" in "response" the identifier (ID) usin o what's known as a transponder (a tJan P , h fD d'f ' e . es ponse or the key s response as an 1to a request), If the bases!ation d~es not rece,l\'e a r h com uter shuts down and the car ferent than the lD program med 1111 0 the car s computer. ( e p won't start. •
. "
•
I
Figure 3.40 Why are the he3ds of keys gelling thicker? Note th31 .the key on the ri ght is .thicker than the key on the left. The key on the right has a computer chip inSIde that sends an Iden lJ fier to the car's compu ter, thus helping to reduce car thefts. Let's design the controller for such a key having an ID of 10 11 (re31lDs are typically 32 bits long or more. not just 4 biLS). Assume the controller has an input a that is 1 when the car's computer requests the key's ID. Thus the controller initially waiLS for the input a to become I. The key should then send its ID (lOll) serially, staning with the right· most bit, on an output r: the key send 1 on the first clock cycle. I on the second cycle. 0 on the third cycle, and finall y 1 on the fourth cycle. The FSM for the controller is shown in Figure 3.4 1. Note that the FSM sends the bits 'lUning from the bit on the right. which is known as the leart significant bit (LSB). Figure 3.42 provides a timing diagram for the FSM for a particular Silu. ation. When we set a - 1, the FSM ente" ,tate K J and output.> r - 1. The FSM
\
Inputs: a; Oulputs: r
---- .
Inputs
Timing di agrams represe nt a particular situation defi ned by how we sel
the inputs. What wou ld have happe ned if we had held a = I for many more clock cycles? The timing di ag ram in Figure 3.43 illustrates that situalion. Notice how the FSM, after retu rning to stare Wait. proceeds to Slate K I again on the nex t cycle.
Figure 3.41 Secure car key FSM.
clk~ Inputs~
a State
I iNail Flail I K t I K2 I K3 1 K4 IWait!W8iti
lJ7
Clk~
even thoug h we returned inpUi a to O.
a _ _ _--'
State
IIWait IWail I Kl I K2 I K3 I K4
Wait Kj
Outputs
r~ Figure 3.43 Sec ure car key timing diagram for a different sequence of values on input 3.
The computer chip in the car key has circuiLry that converts radi o signals 10
bi ts and vice versa,
"So my car key may someday need its batteries replaced?" you might ask. Actually, no-those chips in keys draw their power as we ll as their clock from the magnetic componem of the radiofrequency field genermed from the computer baseslaLion. The extremely low power requiremem makes Custom digi tal circuitry, ramer th an software on a microprocessor, the preferred implementation method. Computer chi p keys make stea ling cars a lot harder-no more "ha l- wiring" 10 stan a car, since the car's compuler won' t work unless it also receives the correct idemifier, And the method above is acrually an overly simplistic method-many cars have more sophisticated commun ication berween the computer and the key, in volvi ng several communi cmions in both directions, even using encrypted communicmion- maki ng fooling the car's compUler even harder. A drawback of secure car keys is that you can't just run down to the local hardware Store and copy those keys for S5 any longer-eopying keys requi res special tools th at today can run $50-$ I 00. A common problem while computer chip keys were becoming popular was that low-cost locksmiths didn't realize the keys had chips in them. so copies we re made and the car owners went home and later couldn't figure ou{ why their car wouldn 't start. even th ough the key fi t in the igni tion slot and turned.
EXAMPLE 3.6 Code detector
Figure 3.42 Secure car key tllTlIng diagram.
....
Ihen proceeds Ihrough K2. KJ, and K4, OutpUlling r: 1, 0, and 1, respect ively.
You 've probably seen doors in airpons or hospitals th at require a person to press a panicular sequence of bUllons (i.e .. a code) to unlock the door. For example, there migh t be th ree bUllons, colored red, green, and blue. and 3 fourth bUllon for starting the code. Pressing the stan bUllon. then the fo llowing bUllon sequence-red. blue, green, red- unlocks the door. wh ile any other sequence does not un lock the door. Such a system may have the ge nernl architecture shown in Figure 3.44. An extra output from the bUllons component, a, is 1 whenever a ll)' button is pressed.
Start Red
Green Blue
Code detec10r
Door lock
Figure 3.44 Code detector W"Chitocture.
We can de cribe the behavior of the CodeDetector block using an FSM ""cured as the SOte diagra m shown in Figure 3.45. . For simplicity, ass ume th at the bUllons each h3ve a pecial ireuit that S) n h~nlZes the butt n with the clock ignal. nnd cre'lles a pulse exn tly one clock yele " ide for e3<,h unique press of the
118
Sequential logic Design-Controllers bUllon . This is necessary
to
3.3 Finite-State Machines (FSMs) and Controllers Inputs: s.r.g,b,a; Outputs: u
en!'urc
Lhal the CUlTcm SIZlIe does n '( inadvcncnr ly change 10 another Slate if a
button press i:.Isls longer thall a single clock cycle. (\Vc'lI design such a synchronization circu it in Example
3.9.) The behavior of Ihe FSM is a~
fo llows:
Sia le . As long as the slart bU IIon is nOl pressed (5 ' ), the
FS M
Figure 3.45 Code deleclOr -
Standard Controller Architecture for Implementing an FSM as a Sequential Circuit
.
the Sian Slale.
d bl FSM is now ready (0 delcct the sequence re . ue, green, . S I If a bUlIan is pressed AN D that bUI. d ( ') he FSM stays ," tar. red. If no bUllon IS presse a . I R /I If a bUllon is pressed A D Ihal bUllon . db (a r) the FSM noes 10 slale et . ' . Ion IS the re ullon. e h Wa i t stalc-nole Ihal when III Ihe Wall . b ( r ' ) the FSM retums 10 I e . IS nOI Ihe red ullon a . Id be i.nored. unlil the SIan bUllon IS pressed stare. further presses of the colored butlons wo u ~ FSM oaes •
10
0,
Being
In
buttons simultaneously, fo ur time in a row? Well , the way we defined the FSM. the door wo uld unlock! A solution to this undes ired ituation is to mOdify the conditions on the arcs that go back to the Wail state. Rather than the condition a r ' , we could use the condition a (r '+b+g). Thus, when the FSM expects the red bUllon, then not pressing the red button. Or pressing the blue or green bUllon , causes a transit ion back to the Wail stateand so does not unlock the door. Likewise when we are ex pecting other specific buttons. An improved FSM is shown in Fig ure 3.46. Fixing the FSM was easy: trYing to fix a circui t deri ved from the FSM wo uld have been much harder. It turns Out that the FSM in Figure 3.46 still has a problem-a fairly seriou one. We' ll describe that problem in Exampl e 3. 13.
The FSM begins in the Wait
FSM slays in m,il: when Ihe sIan bUllon is pressed ( S). Ihe
J 19
the 5wrr stal e means the
agai n. b lion is pre sed (a'). If a bullon is pressed and The FSM stays in Slate Redl as long as no U 81 "f Ihal bUllon is nOI blue (ab ' ) Ihe thaI bU llon is blue (ab). the FSM goes 10 Slale lie. I , FSM relUrns to state 1'0i1. , . state B1/Ie as Iong as Likewise. the FSM stays 10 .. no bUllon , is pressed (a ). and goes 10 Slale Green on con ditio n a g. and state Wair on cond ition a 9 . .. Finally. Ihe FSM slays .III Creen 'f I no bIn ur a is pres ed. and goes 10 Slale Red2 on condItIon a r. and to state \~0il on condition a r R d2 h eans that Ihe user pressed Ihe bUllons III the correel If Ihe FSM makes il 10 slale e . I al m kin Ihe door. Ole thaI all olher Slates sell/=O. sequence-Ihus, Red2 sets 1/= I. thus unloc g I
The FSM then relums to slate Wail.
•
Recall tha l every transi tion' condi ti on is implicitly A
Checking FSM Behavior Correctl y defi ning the behavior of a system is hard. The earlier we fi nd problems, the easier they are to fix. So after we create the FSM , we migh t take time to as k que tions abou t how the ystem behave under cenain input si tuations and then verify that the FSM responds as we expect. Consider the code detector FSM in Figure 3.45. What happens if the user presses the stan button and then presses all three colored
•
Ded with a rising clock edge.
Inputs: s,r,g,b,a; Outputs: u
~
Now that we 've seen how to desc ri be seq uential behavior using an FSM. we need a Structured method to conven the FSM to a sequential circuit. The method is actually very straightforward when we use a standard implementation archi tecture for the circuit. consisting of a state register and combinational logic_ LOgether known as a conlroUer. There are many other ways to implement an FSM, but stiCking to the tandard architecture results in a straig htforward design method. The standard architecture may not yield the minimum nu mber of transistors, but as we've mentioned many times. that's not a drawback these days. A standard cont roller architecture for an FSM consists of a state register and combinational logic. The standard architecture for the laser timer FSM of Figure 3.39 is sho wn in Fig ure 3.47. The architecture consists of a state reg i ter and combinati onal logic. The state register is a 2-bi t regis ter that holds a binary num ber representi ng the present state (i n thi s case, the reg ister is 2 bits wide to represent each of the 4 possible states). Figure 3.47 Standard conlroller The combinational logic's inputs are the architecture for the laser timer. input of the FSM (in this case, b), as well as the state register's ou tputs (s 1 and sO). The combinational logic 's outputs are the outputs of the FSM ( x ), as well as the nex t tate bi ts to be loaded into the state register (n 1 and nO). The details of the com binational logic detemline Ule behavior of the circuit. The prace s for creati ng those detai l wi ll be covered in the next secti on. A more general view of the tandard controller architecture appears in Figure 3.-18. Th31 fig ure ass umes a state register that is 11/ bits Figure 3.48 tandanl ,,,,"troller wide. aJ"('hireC'ture--genl"ml \ i '\\.
120
3 Sequential Logic Design-Controllers
3.4 Controller Design
3.4 CONTROLLER DESIGN
us to easily sec which rows correspond to whi ch Slates. We fi ll all combinati
~~ the left, as usual for a truth table. For each row, we look at the state dia~ i ;,puts
0Cb:
I' five step process summari zed in Table 3.2. We'll illus. , We can deSign a control er uSing a tra te thi s process with some examples.
Likewise, for the two rows slarting with
Descri ption
5 150 = a 1 (state 0111). x should be 1 and the nex t state should be 0112 (regardless of the value of b), so nInO should be 10. We
Create an FSM th at describes the desired beha vior of the controller,
complete the lasl four rows similarly.
TABLE 3.2 Controller design process. Step
fr
Be careful [Q nOle the difference between the FSM inputs and outputs of Figure 3.49. and the combinational logic Inputs and outputs of Figure 3.5O--the latter
ii;
Creale the N
arc/ZirecllIre
a.
"
ii;
Encode (h e slates
r.
fr
ii;
"'fr"
Create the standard architecture by using a stale reg ister of appropriate width. and combinati onal logic With.inputs being the state regiSler bits and the FSM inpuls and ou tpul S bemg the next state bits
and the FSM outputs.
Creme the stale table
Assign a unique binary number 10 each s t~le . Each bin~ number represen ting a state is kn own as an ellcodlllg. Ally encodlJ1g will do as long as each stale has a unique encoding.
Create a truth table for the combinational logic such that the logic the inputs with state bits fi rst makes this truth table describe the state behavior. so the table is a state lab Ie,
.,.,
Implement the combinational logic using any method .
c.
"
ii;
Imp/emelll the combil1alioll{l//ogic
EXAMPLE 3.7 Three -cycles-h igh laser timer controller Icontinued) We can implement th e laser limer (see Example 3.4) as a sequential circuit using the fi ve·step process.
Step I:
Capture the FSM. The FSM was created earlier (see Figure 3.39).
Step 2:
Create the architecture. The standard contrOller architecture for the laser timer FSM was shown in Figure 3.47. The Slate regi ster has two bilS to represent each of the four states. The combinational logic has external input b and inputs 51 and sO coming from the state register, and has external output x and outputs nl and nO going to the state register.
Step 3:
mcludes the bits from and
Step 5:
Encode the states, We can encode the states as follows-Off 00. 0,,/ : aI, 0,,2 : la , a,,]: 11. Remember.
the stale register.
outputs:
On3
0,,1
sO
nl
nO
a a a a a a o a a a a o a a a
o o a a
o o
o
a
x = 51 + sO (note fromthetabIe that x=I if S1=lorsO=I ) n1 n1
51 ' sOb ' + 51 ' sOb + s1s0'b' + sIsO'b 51 ' 50 + 5150 '
nO
SI ' 50 ' b + sIsO ' b ' + S150 ' b 51 ' sO ' b + 5150 '
nO
We th en obtain lhe sequential circuit in Figure 3.50. implementing the FSM .
Many textbooks will organize the state table in different ways than that in Table 3.3. However, we intentionally organize the table so that it serves both as a state table and a truth table that can be used to design the combinational logic of the controller.
The state diagram with encoded states is shown in Figure 3.49. Create the state table. Given the implementation architecture and the
binary encod ing of each state, we can create the state table for the combinational logic, as shown in Table 3.3. Listing the inputs from the state register first in the input columns allows
51 Off
0112
any nonred undant encoding is fine.
Step 4:
[0
TABLE 3.3 State table for lasertimer controller. - - - - - - - - ,_ _ _ _ __ Inputs Outputs
Implement the combinational logic. We ~an fi nish the design by using the combinational logic design process from Chapter 2. From the truth table, we obtain the following equa!lOns for the three combinational logic
wi ll generate the correc t FSM outputs and nex t state signals. Ordering
ii;
O
. 9 to determine the appropriate outpu ts. For the two rows starting with SI~O Ig~~ ~:ta~~ should be O. If b - 0, the controller should stay in state Off, so nInO Sh:uld '" . I, the controller should go to state anI. so nInO should be 01.
Five-Step Controller Design Process
CapillI" Ihe FSM
121 f'
Figure 3.49 Laser timer state diagra m with encoded ~tate s. Figure 3.50 Final implementation of the threc·cyc les-high Inser tim er controller,
Combinational logic o c: -5 c:
0;
122
3 Sequential Logic Design- Controllers
3.4 Controller Design
EXAMPLE 3.8 Understanding the laser timer controller's behavior ,
EXAMPLE 3.9
.
FSM leI's trace through the behav ior of the
. "~ II in state 00 (5 I 50-0 0). b is 0, and lhree-cycl~s- hl gh laser (liner controller. A~sume \~e are m~~l. yba sed 0 11 the combinational logic, X the clock IS currentl y low. As shown in Figure 3.) 1 (left ~ I de). . a ' h I 00
To betler understand how" controller implements ,In
. wtll be
a (the desired output in state 00). nI
'II b 0 'lI1d nO will be . mc.lnlng t e va ue
e .' d 00 wi ll be waiti ng
b( ><.=.1 _
x= 1
-<$))b'
x=1
~~110n3
b( ~ __
x=1
e oa e
In
0
~ __ x=1 x=1 s-'~110n3
0&
e
We want to build :l circuit that synchroni zes a bUlion press to a clock signal. such Lhat when a user presses the bUllon. the result is a signal thm is high
elk
:
:
---r-1----
Capture Ihe FSM. Figure 3,53(a) shows an FSM describing the circuit' behavior. The FSM waJt~ In slate A, outputting bo""O . until bi is 1. Th e FSM then transitions to stale B, OUlptlt,llng bo:; I. Th e FSM will then tran sition to either sla te A or C. which both set bo=O again, so that bo was 1 for just one cycle, as desired. The FSM 0DCS from B toA if b 1 returned to O. If b i is still 1. the FSM goes to Slate C. where the °FSM wailS for b i fa return D. causing a trans ition back to Slale A. FSM inputs:
bi; FSM outputs: bo
~ i'
o !lL----~s=lal~e=~OO~---t
hcycle2 ncycle3 ncycle4
~e~entmg the but ton b,eing pressed, we want to se t bo to 1 for exactly one cycle. We [hen wait for 1 t~ return to a agalll , alld then wa ir for bi to become 1 again. which would represent the next pre ssmg of th e button ,
elk r'-"*O-F'-,
o
cycle 1
bi -..J ' for exactly one clock cycle. Such a synchronized , L Outputs: J : Signal IS ~se rul (0 prevcm a single bulton press th at I~s ls mu ltI ple cycles from being interpreted as mU/ bo (I?'e blltto~ presses. Figure 3.52 uses a liming diagram to Illustrate the desired circuit behavior. The ci rcuit's input wi ll be a signal bi and Figure 3.52 DeSired lIming diagram oflhe the output a sjonal bo Wh bl' bcco mes. I' rep- bu([on press synchromzer , 0 < , en
Step 1:
slale=OO
clk Inputs:
4
b(
x=1
s-'S-<11
WI
-~ -b-'----""
x=o _ - - - - _
- <$:»b'
' 11 b i d d ' t th
WI
\.
bi
b"
bi
A
slale=01
r
bi
B
C
b"
bo=O
bo= 1
FSM inputs:
bi; FSM outputs: bo
r
bo=O
(a) Inputs:
b - - - - - -____~ Outputs:
" '___________ ,
--------------------------~ Figure 3.51 Traci ng the behavior of the three-cycles-high laser timer controller. Now suppose b become I. As shown in Figure 3.51 (middle). x will still be O. as desired. n I will be O. but nO wi ll be I. meaning the value 01 will be waiting at the stale regisler's inputs. Thus, on the lIex( clock edge. aI will be loaded inlo the state register, as desired. As shown in Figure 3.5 1 (right side). soon after 01 is loaded into the state registe r, X will become I (after the register i loaded, theres a slight delay as the new values fo r 5 I and sO propagate through the combinational logic gates). That output is correct-we should output X= 1 when in state 01. Also. n1 wi ll become 1 and nO will equal 0, meaning the value 10 will be waiting at the state register inputs. Thus. on the next clock edge. 10 will be loaded into the state register. as desired. After lO is loaded into the state regiSle r, x will Slay I , and n I nO will become II. When another clock edge comes. 11 will be loaded into the register. x will SlaY I. and nl nO wi ll become 00. When anOlher clock edge comes. 00 will be loaded into the register. Soon aftcr. x wi ll become O. and if b is O. nInO wi ll stay 00 : if b is I. nInO will become 01. No tice we're bnck where we started. Understanding how a State register and combinational logic implement a state machine can take a wh ile, ince in a particular state (indicated by the value presentl y in the state regisler). we generate the eX lemal output for that state. and we generate the signal, for Ihe lI ext state-bul w. don't lran ;i tion to that next state (i.e .. we don't load the
123
Button press synchronizer
(b)
bo=1
n1 = s1 'sObi + s1s0'bi nO = s1 'sO'bi bo = s1 'sObi' + s1 'sObi = 51 '50
bo=O
(c ) Combinational logic
Inpuls s1 sO bi 0 0 0 0 0 1
Oulpuls n1 nO bo 0 0 0 0 1 0
0 --cn--o- Tb-T-' o CD --1-'0-0-6-'0--0--' 1 1
Figure 3.53: Bulton press synchroni zer design steps:
(0
unused
;:.J!l
bi
ff! .~
1 0 1
1 o 1 1 o 0 --1--'--0- -6-'0--0--' 1 1 1
0 0 0 (d)
clk (e)
--~----
124
Sequential Lo gic Oe sig n~Con trolie rs Step 2: Step 3: Step ~:
S lep 5:
EXAMPLE 3.10
3.4 Controller Design
. • FSM has three sta tes. the arc hitec ture has a two-bit Cre~lte th e arc hit ect ure. Smce the st~lIe regi ster. as shown in Figure 3.53(b). . I ~ vard ly encode the th rce , tates as 00. 01. and E ncode Ihe s la tes. We can str:lJg 11 Of' 10. as shown in Figure 3.53(c). " T." cOllvert the FSM wi th encoded states to a state table as Creale Ihe s lale lab le. '" I t bo 0 d unused Slate 11. we have C lOsen to o utpu = an show n in Figure 3.53(d). For the ret urn 10 sl ~lIe 00. . . . .' " We derive the equ
Sequence generator
Inpuls: none; Outputs: w. x. y,
\Ve want to design a circuit wi th fo ur ou tputs: w. x,, y .
z
to genera te the next pattern o nly on a ri sing cI ~k edge. Sequence generators arc co mmon in a w l~e ra nge of systems. For exampl e. we might want [0 blink a ~el
wxyz=OOll
to
attrac t the magnetized motor
10
Step 2:
Step 3:
S tep 4 :
~ o
r ----+- y -gc z
in
sI
X
sIsO '
y
5 I • sO
z
51 •
nI
51
nO
sO '
nl
xor
sO
Figure 3.56 Sequence generator con trol ler archileclurc.
Secure car key controller (continued) Let"s complete the desig n fo r the sec ure car key controiler from Examp le 3.5. We already carried oUl the Ca pture Ihe FSM s tep o f the fi ve-s tep process. wi th the FSM shown in Figure 3.41. The remaining steps arc as foll ows.
Wo
the
x C "TI y~~
z
S tep 2:
in
S lep 3:
Capt ure Ihe FSM. We capture the sys tem 's be havior as the FSM shown in Figure 3.54. The FSM has four states. which weve labeled A. 8. C. and D (though any other four un ique names would do j ust fine). Creale Ihe a rchit ecture. The standard controller arc hitecture for the sequence generator wi ll have a 2- bit state reg i ter to represen t the fou r poss ible states. no inputs 10 the logic. and o utputs w. x. y. z from the logi c. alo ng wi th outpu ts n I and nO. as s hown in Figure 3.55.
"TI
X
3.56.
EXAMPLE 3.11 Figure 3.54 Seq uence ge nerator FSM.
next position in the rotati on-such a motor is kn own as a stepper motor. si nce th e molor rOiates in steps. We can design the sequence ge nerator controller us ing our five-s tep process. Step I :
W
wxyz= ltOO
of four lights in a particular paltcrn . such 35 in a festi ve ligh ts disp lay. We might instead want to rolate an electric motor a fixed number of degrees o n each cl oc k cycle by powering magnets arou nd the motor in a spe-
=
125
The fina l circuit is shown in Fig ure
cb--cb
seq uen ce. slarting m 0001 again. We wanl the circuit
Impl ement Ih e combin a liona l logic. We derive th e eq uati ons for each o utput of the co mbinationa l logic from the ta ble. Afler so me algebra ic s implification. the eq uatio ns arc as fOll ows:
w
-qs~oo
and Z The circui t should oenerate the followlIlg sequen~e of ou tput pallems: 000 I. 00 II. 11 00. and 1000. After 1000. the circuit should repea t the
cific sequence
Slep 5:
C reale Ih e a rchileclure. Since the FSM has five statcs. wc' lI need a 3-bit state regiSler. A 3·bi t stat e regis ter can reprcsent eighl slates. so three Slates will be unu ed. The input to Ihe logic is sign al a. while the OutpulS are sig nal r and next SlalC oUlpurs n2. n 1. and nO. The architcclure is shown in Figure 3.57. E ncod e Ihe s lates.
Let"s encode the states using a straig htforward binary encoding of
000 through 100. The FSM with state encodings is shown in Figure 3.58.
clk
r Figure 3.55 Seque nce generalor con tro ller architect ure .
Combinalional n2 logic
o
C"TI
Inputs: a ; Outputs: r
-g~ in
TABLE 3.4 State lable for s equence generator controiler. Ou tputs
Inpu ts
Encode Ihe s tates. We can encode Ihe s tates as foil ows~A: 00. 8: 01. C: 10. D: II. Any other encoding with a un iq ue code for eac h state would also do fine.
A
0
a
0 0 0 I
8
0
I
0 0
I
I
Create Ihe stale tabl e. The Slale lable for Ihe FSM with encoded states is shown in Table 3.4.
C
I
0
1
I
0
0
D
I
1
I
0
0 0
sI sO
w
X
y
z
nl nO
0 I I
a
I
I
a a
Figure 3.57 Sec ure car key contro ll er archil cc lu rc.
Slep 4:
Figu re 3.58 ecure car k<~ F M encoded Sl3le___ .
\I
ith
Creale th e Slule lab le. The FSM convened 10 a sto te table is ,ho.I n in TJ~le Ih e unu sed :\ttH cs. we h:wc ch sen to SCI r - 311d the nc\! 'tale 10 000.
a
3.: . For
126
3.4 Controlle r Design
Sequential Logi c Desig n- Controllers Slep 5:
Impl emen t th e comb in 'l.ti o l~a l logic. We ca ll desig n four Cl fCU ltS. one fo r c;lch output. 10 implement II~e combin ational logic. We Icave thi S step as an exercise for th e reader.
EXAMPLE 3.12
OUIPUIS
InpulS 52 51 sO a Wait
. seq uenlial funclio n . . We have been conve rllng an FSM 10 a c ircuit using a fi ve-step process. We can also convert a circuit to an FSM by applying Ihe five-slep process of Table 3.2 in rever~e. In general. convertin g a c irCUit to an equation or FSM is known a,s re,_'erse ellgilleerillg Ihe behav ior o f Ihe CirCUIt.
ra ll y, the Sl ates have already been encoded. bU I we ca n still name eac h Slate. We arbi trarily choose Ihe labcls A. B. C, and D. secn in Table 3.6.
controller.
More on Controller Design Converting a circuit to a n FSM . . We showed in Section 2.6 Ihal a clrc ulL Iruth table. and equat ion were al l ways 0 1 representing the same combinationa l fu nction. Similarly. a circui t. state lable. and FSM are all ways o f represe nling Ihe same
111 step 3, we mu st encode the ~Iale~. Natu-
TABLE 3.5 State tab le for secure car key
KI
K2
K3 K'/
Unused
r
n2 nl nO
Slep 2 calls for Ihe crealion of Ihe slandard c~nl roll e r arc hitec ture. Th is step req uires no work Since the controller architec ture was already defined.
o o 0 00000 0 o 0 I 0 00 1 00 0 o o 0 o 1 0 0 1 0 1 1 o o 1 0 1 1 0 o o 0 0 0 o 0
1
o o o o I 1 1 I
0 0
o
I I 0 0 1 1
o
0
I I
o 1 o 1
0 0 0 0 0 0
0
0
0 0
0 0
0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
Converting a sequential circuit to an FSM Give n the seq uential circuit in Figure 3.59. fi nd III :; an equivalent FSM. .~ x oc We Slart from slep 5 of Ihe 5-Slep process :2 Z -ij described in Table 3.2. The combinalional f2 c ;;; circuit has already been implemented. and we can proceed to step 4. where we create a stale lable. The combinational logic in the controller architecture has 3 inputs: 2 inputs. 50 and s1. repreo;;;ent the conlents or the Slate register. and I input, x, is an eXlema.1 input. Thus ~ur slate table wi ll have 8 rows Ince there arc 2 ::; 8 pas· sible combinat ions or inputs. A ncr we set up the state table and cn u· meratc al l pas ible combinations or inpu ts (e.g.. s l sOx~O~O ..... slsOx=ll l). lI'e use Ihe lechniques described in Secllon 2.6 10 Figure 3.59 A
Finall y, in Slep I. we caplure Ihe FSM. Initiall y. we can set lip an FSM di agra m with th e rOllr slates we 've labeled in step 3, shown in Figure 3.60(a). Nex l, we lisl Ihe va lues of Ihe FSM outpu ts y and Z next to each state. For example. in Siale A (51 sO = 00). Ihe OUlputs y and z are 1 and O. respectivel y. so we list "y l = 10" wilh Siale A in Ihe FSM .
Outpuls: y, Z
0)
0
0
0 (a)
127
TABLE 3.6 State table for sequential circuit In puts 5I
sO
A
0 0
0 0
B
0 0
C D
0 0
OUlputs nl
nO
y
0 I
0 0
0 1
0 I
0 0
0 I
0 I
0 0
0 0
0 I
0 0
0 0
0 0
0 0 0 0
0 0
Inputs: x: Outputs: y, z
0
0
YZ: 10
0
0
yz:01
yz:10
yz: 10
yz:oo
YZ:0 1
(b )
(c)
Figure 3.60 Conve rting a Slale lable 10 an FSM diagram: (a) inilial FSM. (b) FS~I with OUlputs specified. and (c) FS M wi lh OUIPUIS and transilions specified. Arter listing the outputs for Slares B. C. and D. shown in Figure 3.6O(b). \\C tum 10 the ,late tmnsil ions specified in the s late table by 111 and nO. Consider th e first row oflhe sttlte table. \\hich says Ihal nlnO-OO when s1s0x=000. In olher words. when in laleA (s1s0=00). the nnl Siale is Siale II (nlnO = 00) if X is O. We can represe nl Ihis in the FSM diagram b) dr.l\\ing an arrow rro m slate A back to stale A and labclin2. the new trnnsition " X ' ," No\\ consider the . nd row o f the stale table. which indicates th at fron~ Sl3lC A. we tr.msition to state B \\hen \ =- 1. \\'c add a transition arrow from Slale A 10 B and label it "x." Arter labeling all the tr.lnsitions. \\ e are left wilh Ihe FSM in Figure 3.60(c). You mny nOlice thut sl
Gi ven any synchronous circ uit co n ~ i s t ing of logic gales and flip-flops. \\e ':m al\\a~< redraw the ci rc uit as con ~ i sting of a state register and logi -{)ur st:mdard l'('ntroll r arc hiteclUre-just by grouping all Ihe Oip-O ps logelher. Thus. the appfO.Ich dc>cnbnl above works for any synchro nous circuit. not j ust a circuit alr'ead~ dra\\ n in the fonn ,I' o ur siandard controlle r arc hiteclure.
128
Sequential Logic Design- Controliers
~ ab=llnext state?
... o:::X0 a'b
~ whati'
ab=OO? a'b'
...
~
3.4 Controlier Design
Com mon Pitfa lls Mistakes are commonl y made when capturing an FSM , relating to prop~rties regarding the transitions leaving a state. In short, one and ollly one tra nsitIOn condt tlOn should ever evaluate to true du ring any rising clock edge. The propert ies are:
:~Ib~
I. Only one condilioll sholiid be Irlle-For a given s13te, for any rising clock edge,
no more than one transition condit ion should be trUe. For example, consider an FSM with inputs a and b, and a state SWle I with tWO outgoing tra nsitions, one labeled "a ", and the other labeled "b." What happens when a = 1 and b ~ 1which transition should the FSM take? The FSM designer must ensure that the conditions are exclusive-only one could possibly ever be true at one ti me. In the example, the designer might label the transitions "a" and "a ' b" to solve the problem. Actually, a particular type of FSM , known as a nondetermillistic FSM, does allow more than one condi tion to be true and chooses among them in some arbitrary way-but when designi ng circuits, we usually want detenninistic behavior, so we don ' t consider no nde tenninist ic FSMs further.
+ a'b + a'b' • a + a' ( b+b . ) a a + a ' *l • a + a'
- 1 . Analyzing Ihe equalions Illad f .. ellher 1 or is a 101 of work. TIl e ~om c~nd l l lons of every stale and proving they equal two slIuations and inform the d ,ere ore ,. ,I good FSM capture 1001 wi ll delecl the above e Igner 0 t Ihe SIl U3110n.
a
EXAMPLE 3.13 . Verifying transiti on properties . for the code detector FSM FIgure 3.46. shows an FSM ~Or a code detector ( ,property for the transilions leavi ng '1:
truc"
2. Olle cOlldilioll sholiid be Irlle-For a given state, for any rising clock edge, aile of the transitions fro m that state must be take n. In other words, every input combination should be accounted for in every state. Designers sometimes forget to ensure th is. For example, consider an FSM with inputs a and b, and a state Slalel with two outgoing tran sitions, one labeled "a", and the other labeled "a ' b." What happens if the FSM is in Slate l . and a = 0 and b ~ O? Neither of the two transitions from Stale l has a true condition. The FSM is not full y specified-we need to add a third transition, indicating what state to go to if a ' b' is true. With that th ird condi tion, we have covered all possible values of a and b. A commonly forgotten transition is a transition pointing from a state back to itself.
rollows:
(a*a ' )*b 0 * b
o
For th: second situation of one condi tion being true, we can check that the OR of all Ihe condlllOlIS all l/'QnS/llOllS of a stale always re~II/IS in 1 . Conside ring the same example ofa state that has two tranSitIOnS, one with condItion a and the other with condition a ' b uSlOg transfonnations of Boolean algebra we obtain : '
c
+ a'b a * (1 +b ) + a' b + ab + a ' b a + (a +a' ) b a + b
'
a r * a' m( a*a')r - O*r D
algebra we obtain:
=
We \V'mtIO ,' f
h '
ven y I e 'only one condilion should be
S'
a r +b+g). We Ihus have three pairs of S '"~• . llIrl. There are Ihree condilions: a r, a'. and
We can verify the above two propertie using Boolean algebra. For the first property of only one condition bei ng trUe, we can check that the AND of evelY pair of cOlldilions all Irans iliolls of a stale always reslIlls ill O. For example, if a state has two transitions, one WIth condi tion a and the other with condition a ' b, using transfonnations of Boolean
* a'b
129
Clearly. Ihe OR of Ihose Iw .. . were bolh 0, neither condilion "~~~ndlllons '~ nOl l. bUI rather a+b . Thus. if a and b specIfied 10 the FSM . Abov d be .Irue, ,lIld Iherefore the neXI Slate wou ld Checking yields: e, we fixed Ih,s prob lem by addi ng another transi ti on,
As evidence 'hat lilis "pitfa" " is ifldeed common,
we ad",il ,har 'he mLfloke we made
in Figure 3.46wos ge1ll1;1I£. and lIof just made fo r
educatiollal purposes. A reviewer of Ihe book caugh, il. We left the mistake ill alld added this '
example. to stress 'he pOitllllzat the misrake is
commo",
0
con( II IOns. which we AND and prove each equal 0 as
a ' * a ( r ' +b+g) - (a'*a)*(r ' +b+g) O* ( r'+b+g)
ar * a ( r ' +b+g) - (a*a)*r*(r ' +b+g) - a*r*(r'+b+g) - arr ' +arb+arg - 0 + arb+arg arb + arg - ar(b+g)
• 0
It appears our FSM is not fu ll s cifi d result in 0, which in IUm means bOI~ cpe d' e , as Ihe AND of Ihe third pair of conditions does nOt delerministic FSM (if bOlh d" on 1I10ns could be true at Ihe same time-resulti ng in a non con Illons arc fmc Wh ' l ' . h deleCtor problem descripll'on tllat ' . a IS t e nexl stale?). Recall from the code a bUllon is pressed (a - I) and Ih twe b wan(. to trans'It"Ion f rom the Slarr slale 10 Ihe Red l Slate when . a ullon IS Ihe red bUllon . ,and no Other colored bUllon is pressed. Th e FSM III Figure 3.46 has the con d" shou ld instead be arb' g' . h Ilion a r. Our mIstake was underspecifying Ihis condilion' 'It - Ill ot er words a b tt h be . (r) and Ihe blue bUllon has nOI been p (b '~ on as en pressed (a) and il is the red button The transilion from Starr I back to Iher~~s~ and Ihe gree n bUllon has not been pressed (g '). the same as in Figure 3 46 aft I ' all stale could then be wrillen as a (rb ' g' ) , (which is verify the "only one CO~di tio:~:~~::.ngr DeMorgan 's Law). After this change, we can agai n try 10 and a (rb ' 9 , ) ': p operty for all paIrs of the three conditions arb' g'. a' .
d
arb'g' * a' aa '*rb'g ' O*rb'g'
D
a ' *a(rb ' g ' )' O*(rb 'g' )' ~
0
o
arb ' g' * a (rb ' g ' ) ' a*a*(rb ' g')*(rb'g')' write rb ' g ' a Y for clarily.. . D a*a*Y*Y' = a*a*O =
c
0
We wou ld need 10 change Ihe [ 'f d' . Ihe pairs of condilions for those slalreaS~sl' Ion con It Ions of the olher slates similarly, and then check ran sltlons too.
130
3.5 More on Flip-Flops and Controllers
Sequential Logic Design- Controllers
, SltIrr we OR the three conditio ns and
To verify the "one condition is mlc" property fo r stale prove they
cqu~1I
more functionality than D flip-flops . to reduce the logic gates required ou t ide of the flipflops, and hence to reduce the number of ICs neces ary to implement a circuit. Those flipflop types Included SR. JK. and T flip-flops .
'
I:
arb ' g ' a' + a' + a' +
+ a ' + a ( r b ' g', ) ', ) ' (write rb' g' as Y for clarity) arb ' g ' + a(r b 9 aY + aY ' a (Y +Y' ) = a ' + a(l )
SR Flip-Flop The SR flip-nap is similar to the SR latch descri bed earlier. with additional logic to make the CorCUlt triggered by the edge of a clock. rather than just the level of the clock. JK Flip-Flop
- a' + a 1
The JK flip-fl op is similar to an SR flip-fl op. wi th J corresponding to S, and with K corresponding to R (I remember this by thinking of " K" standing fo r "Klear" or clear). The JK flIp-fl ap's behavior differ from the SR flip-flop when both inputs are I . Recall that an SR flip-flop 's behavior is undefined when both inputs are I. A JK flip-flop. in contrast. togg le when both inputs are set to I (at the next clock edge. of course). To toggle means to change to the opposi te state, meaning if the present stored bit is I. the next stored bit wo uld be O. Likewise, if the present stored bit is O. the next stored bil would be I.
We wou ld need to chec k the property for all other states toO,
a---o ... a---o a=O b=' c=0
b='
a=O b=O c='
c='
. I'f' FSM Notations ' Unassigned Outputs .. b ' . I" .. ' . ' FSM otation of every translu on eong Imp .cnly SImp I yong . I We already introduced the slmphfYlng h n commonl y used simplificatio n involves . . . lock edoe Anot er <> • l'stin the assionment of every output in ANDed wIth a riSIn g c . . If FSM has many outpu ts, I <>O " asslgno ng outpu ts. an I d ke the relevant behavior of the FSM hard to every state can become cumbersome, an ma as follows-if an output is not explicitly discern. A COllllllo n simpll fy mg notati on IS .
0
T Flip-Flop
ass i~ned in a state. the output is implicitly assIgned a .
A T fli p- fl op acts like a JK flip-flop wi th the JK inputs tied together to form the T input. In other words, whenever T is 0, the flip-flop maintains its current state. but whenever T is I, the flip-flop toggles (think of "T" for ·'Toggle").
- . . . , '. I licit Clock Connections Simphfyong C,rc u, t Drawongs. m~ v a sinoIe clock signal connected to all seque ntial Many if not most sequential CorCUlts a. e <>. I because of the small triangle input \~ k ' a component IS sequenua k b I Many circui t drawings therefore use a simplifi. components. e no\\. drawn on the component S bloc. sym o. 'be connected to all sequential components, . cat ion wherein the clock sIgnal IS ass umed to • simp lificatIOn . leads to Iess c luttere d wiring in the draWIn g. This
. .' I d Sequentia l Circ uit Design Ma thematica l Formalisms on Combmatoona .an B i n functions and FSMs for We have described two mathematical formahsms, 00 ea . ' . . o combon .atlona . I and sequelltial circuits, respect ively. Note that web dId 'Id' not halle th to deslgllln "CorC · UI ts. Recall that our first use thosee formah. sms to d eSlgn . attempt at UI 109 a . ree· toge ther on Lile . laser ti. cycles-hl2h mer'on F·Igure 335 . J'ust had us connecti . ng components ' . . a correctIy workin "o circuit However, provIdes hopes of creating .. . . usong those formahsms . . for a structured and sound method of designong corcuns. Those fonnaiosms also proVIde Lile basis for powerfu l automated tools to assist us with design, s uch as a tool that would auto. II y c hec k' lor C the common pitfalls described matlca . earioer . ' on thIS secllon ,' tools Lilat. . II y conven Boolean equations or FSMs onto corcun , tools that venfy that tM aulomallca circu its are equivalent, tools that simulate our systems, etc . And, we have s~arcely touched on all the benefits of those mathematical formalisms relating to automatong the vanous aspects of designing circuits. and verifying the circui ts behave properly. The Importanceo[ using sound mathematical formalisms to gUIde deSIgn cannot be overstated.
Nonideal Flip-Flop Behavior Generally, when we first learn about di gital design. we assu me ideal behavior for logic gates and flip-flops, JUSt like when we first learn physics of motion. we as ume there's 00 friction or wind resistance. There is. however. a non ideal behavior of flip-ftops-metastabiJity-that is such a common problem in real digital design practice, we feel obliged to discuss the issue briefly here. Digital deSigners in practice should study metastability and possible SOlutions quite thoroughly before doing serious designs . Metastability comes from failing to meet fl ip-flop setup or hold times, which we now introduce. Setup Times and Hold Times
Clk---IL-
o-riL:
:
:----:
setup time
3.5 MORE ON FLIP-FLOPS AND CONTROLLERS Other Flip-Flop Tvpes Today, designer generally use registers to implement their bit storage needs, and LilOSl regi ters typically are built from D flip-flops . However, in the past, tran Istors were m~cb more scarce than today. Thus, designer often utilized other types of flIp-flops, haVll\!
131
Clk~ I
C)~ , , ,, ,,
t--')
hold time
Flip-flops are built from wires and log ic gates, and wire and logic gates have delays. Thus, a real flip -flop imposes ome restrictions on when the flip-fl op's inputs can change relative to the clock edge. in order to ensure correct operation de pite those delays. Two important restriction are:
• Setllp time: The inputs of a flip-flop (e.g" the D input) must be stable for a minimum amount of time, known a the setup time. before a clock edge arrives. This intuitively makes sense-the input values mu t have time to propagate thro ugh any internal logic and be waiting at the internal gate ' inputs before the clock pu l e arri ves.
• Hold time: The inputs of a flip-flop must remain stable for a minimum amount f time, known as the hold time, after a clock edge arrives. Thi at 0 makes intuitive sense-the clock signal mUSt have time to propagate through the internal gate- to create a stable feedback state.
132
Sequential Logic Design-Controllers
3.5 More on Flip·Flops and Controllers
. . I k pul se width- the pulse must be wide A related restrict ion is on the mlnllnum C oc . II ' d , tl ough the tnterna oglc an create a enough to ensure that the correc t values propdgate lr stable feedback state. , ' . . II y comes W'th describi ng setup li mes, hold limes, and A flip-flop typlca I ,a datasheet , minimum clock pulse widths. . . I" D han cd 10 0 too close g Figure 3.61 ill ustrates an example of a setup lime Via allan. c the risino clock. The res ul t is that R was not 1 long enough 10 create a stable feedback " . Q betng ' 0. Inslead in Ihe cross-coupled NOR gates With . , Q glitches . . to 0 bn .efl y. That glitch feeds back 10 the lOp NOR gale, causing Q' to gillch to 1 bn~ny. Thai giltch feeds back 10 the bOllom NOR gate, and so on. The oscillalion would ilkely conttnue until a race condition caused the circuillo senle inlo a stable si luation of Q~ 0 or Q ~ l~r, the circuil could enter a melastable state, which we now descri be. 10
D lalch
C D
S
R Q' Q
Figure 3,61 Setup lime violation: Dchanged 10 a (I) 100 close 10 the rising clock, u changed 10 1 after the invener delay (2), and then R changed 10 I afler Ihe AND gale delay (3), BUI then the clock pulse was over, causing Rto change back 10 a (4 ) before a stable feedback situalion with 0-0 occurred in the cross-coupled NOR gales. R's change 10 I did cause 0 10 change 10 0 after the NOR gate delay (5), bUI R's change back 10 a caused 0 10 change righl back 10 1 (6). The glitch of a 0 on Q fed back inlo the lOp NOR gate, causing 0' 10 glitch 10 1 (7). That glitch of a 1 fed back 10 Ihe bottom OR gale, causing anolher glilch of a aon 0, That glilch runs around Ihe cross-coupled OR gale circuil (oscilialion}-a race condilion wou ld eventually cause Q 10 ettle 10 1 or 0, or possibly enter a metaslable stale (10 be discussed),
dk-----FL
o--t--©L 1
,
H
setup ~me violation
o~ metastable state
Metastabili ty If a designer fails to ensure that a circuit obeys the setup and hold times of a Rip- fl op. the result could be that the flip-flop enter a metastable state. A Rip-fl op in a m etastable stall is in a state other than a stable 0 or a stab le 1. Metastable in ge neral mean s that a system is on ly marginally stable-the system has other states that are far marc table, A fli p-Hop in a metastable state may have an output with a va lue thllt is not a Q or a L instead outputting a voltage somewhere between that of a 0 and that of ai , That voltage may nl 0 o<;cillate somewhat. That's a problem. Since a flip-flop' output i< connected to other components like logic gates and other flip-nap" that wangc volLOge va lue may cause other components to output strange value" and soon the V(Iluc, throughout our entire circuit can be in bad ~ hape ,
133
Why would we ever violate setup and hold times? After all, within a circuit we design we can measure the longest possible path from any Rip-Rap output to any flip-Rap input ~ long as we make the clock period sufficie ntly longer than that longest path, we can ensure Our CirCUli obeys setup li mes. Li kewise, we can ensure that hold times are satisfied too The pro blem is that our circuit li kely has to interface to external inputs, and we ~an't control when those inputs change, mean ing those inputs may violate setup and hold times When connected to Rip-fl op inputs, For example, an input may be connected from a button bell1g pressed by a user- the user can ' t be told to press the bunon so many nanoseconds before a clock edge and to be sure to hold the button so many nanoseconds after the cl~ck edge so that setup and hold ti mes are satisfied. So metastability is a problem pnman ly when a Rip-fl op has inputs that are not synchronized with the circuit's c1ocksuch II1pUts are said to be asy nchronous. Designers usually try to synchronize a circuit 's asynchronous input to the circ uit's clock aj ----0>--"':,.----1 before propagating that input to components in the circuit. A common way to synchro ni ze an asynchronous input is to fi rst feed the asynchro" nOlls iI/pur imo a single D flip-flop, and then use the output of that Rip-Rap wherever the input is needed, as shown for the asynchro nous input a i in Figure 3.62. Using a si ngle Ri p- Rap as shown aj also eliminates a second problem of different values of the same signal appearing at the various internal Rip-Raps at a clock edge, due to different path delays. synchronizer "Hold on now! " you might say. Doesn' t that synchroni zing Rip-Rap experience the setup and hold time problem, and hence the same metastaFigure 3,62 Feeding asynchro~ous bility issue? Yes, that's true. But at least the external inputs into a single flip-Bop asynchronous input directly affects only one Ripcan reduce melllSlJlbilit) problems. fl op, rather than perhaps several or dozens of Ripfl ops and other components. And that synchronizer Ri p-Rap is pecifica lly in troduced for synchronization purpo es and has no other p~ whereas other Rip-Raps are bei ng used to store bits for other PllIpDSCS- We can !herefore choose a fli p-flop for the synchronizer that minimizes the metasrnbilit) prohlem-we can choose an extremely fast Rip-flop, andlor one with I'el)' small setup and hold times. and/or one wi th special circ uitry to minimize metastability_ That Rip-Rop may be bigger than nonnal or can ume more power than nonnaL but there's only oe su h Hip-Hop per -ynchronou input. so those issues aren't a problem. Bear in mind that 0 matter what we 00_ though, the synchronizer flip-Rap could still become mc:tasrnble. but 3t Ie -t we can nunimize the odds of a meta 'table state happening byeh -iog a good Hip-Hop, Another thi ng to cons ider i that a Rip-flop will typicnll not '(3) metast:lbl for I~ I ng, Eventually, the flip-flop will "t pple" mer to amble 0 or a tahle _ It e how 3 oi n tos cd onto the ground nm spin for a \ hi Ie (a mctustubl state) but will elentuall~ topple over to :1 stable head or tail. Whm many designcn; th refore do IS IIltrodu:e til )/' 1110rc flip-flops in series for s nchronitation purposes, as ShOll'11 in Figure 3 63, '0 I n If
134
Sequentia l Logic Design-Controllers the first flip- fl op becomes metastable. that fl ip-fl op will likely reach a stable state before the next clock cycle. and thus the second flip-fl op is even less likely to go metastable. Thus the odds of a metastable signal actually making it to our circuit"s normal flip-flops are very low. This approach has the obvious drawback of delaying changes on the input signal by severa l cycles-in Figure 3.63. the rest of the circ uit won't see a change
3.5 More on Flip-Flops and Controllers
Probability of flip·llop being metastable is:
very very low
Incredibly low
al
synchronizers
Figure 3.63 Synchronizer flip-fl ops reduce pro bability of melaslabilllYin our regular flip-flop .
. ... on the input a i fo r three cycles. As clock periods become shaner and shaner. the odds of the firs t flip-flop s t~bllizmg before the next clock cycle decreases. so metastability i becomIng a more challengIng Issue as clock periods shrink. Many advanced methods have been proposed to deal with the. iss~e . Nevenheless no malter how hard we try. metastability wlil alway be a posslblilly, meaning our cir;uit lIIay fa il. We can minimize the likelihood of fail ure, but we c.an't completely eliminate failures due to metastability. De igner often rate their deSigns using a measure called mean time between failures . or MTBF. DeSigner typically 31m for MTBFs of many years. Many students find this concept-that we can't design failproof circuits-somewhat disconcening. Yet . that concept i the real situation in design. Designers of serious high-speed digital ci rcu its should tudy the problem of metastability, and modem soluti ons to the problem. thoroughly.
Flip-Flop Reset and Set Inputs Some D flip-flops (as well as other flipflop Iypes) come with extra inputs that can force the flip-flop to 0 or 1, independently of the D input. One uch input is a clear, or reset, input, which forces the flip-flop to O. Another such input is a set input, which forces the (a) (e) (b) flip-flop 10 1. Reset and set inputs are Figure 3.64 0 nip-flop, with : (n) 'ynehronous very useful for initializing flip-flop to resel R. (h) a ynehronou rc et AR. and (e) an inilial value (e.g., initializing all flip- asynchronou; rescl and ... 1. flops to Os) when powering up or resetting a system . These reset and set inputs hould not be confused with the Rand S inputs of an RS latch or flip-Hap-the reset and set inputs are ~ pecial control inpu t ~ to any type of flip-flop (D. RS . T. JK ) that take priority over the nomlal data input ~ of 0 nip-flop. The resel and 5et inpull of a flip-flop may be either synchronol!\ or 0'> nchronou . A synchronous reset input force the flip-flop to 0, regardlc \\ of the ,·aluc on the D inpuL during a rising clock edge. For the flip-flop In Figure I.M (a). ctllng R to 1 ~ rces the
-r:r0~ yyr-y
135
~ip-flOP to 0 on the nex t clock edge. Li kewise, a synchronous set inpul forces the flip. op to 1 On a rising clock edge. The reset and set inputs Ihus have priority over the 0 Input. If a flip-flop has both a synchronous reset and a synchronous set input. the flip-flop datasheet must Inform the flip-fl op user which has priority if both inputs are sellO 1. An asynchronous reset forces the flip-fl op to 0 independently of the clock signalthe clock does not need to be rising, or even be 1. for the asynchronous reset 10 OCcurhence the term "asynchronous." Likewise, an asynchronous set. also known as preset. can be u ed to asynchronously force the flip-flop to 1. We omit discussion of how synchronous/asynchronous reset/set inputs would be internally designed in a flip-flop. cycle 1 cycle 2 cycle 3 Sample behavior of a flip-fl op's Clk -----!l--_~ L---4L---_ asynchronous reset input is shown in Figure 3.65. We assume Ihe fl ip-fl op D initially stores 1. Selting AR to 1 , forces the flip-fl op to O. independent AR ' of any clock edge. When the nex t clock edge appears, AR is still 1. so Q : : ; the flip-fl op stays 0 even though the input 0 is 1. When AR returns to O. the flip-fl op foll ows the 0 inpul on Figure 3.65 Asynchronou reset forces !be flip-Hop successive clock edges, as shown. to O. independent of c 1 or D.
--LLr----L
Initial State of a Controller Particularly observanl readers may have come up with a question when we implemented FSM as controller in thi section-what happened to the indication of the initial tale of an FSM when we designed the controller implementing the F M' The initial -mle of an FSM i the state that the FSM starts in when the FSM is first a ti\1lted-or in ntroUer temlS. when the controller i firsl powered on. For example. the laser timer ntroller FS 1 in Figure 3.39 has an initial state of Off. When we omened our graphi-al FS~ls to state table in this section. we ignored the initial tale infonnation. Thus. all of our ntroller circuits stan in some random stale based on whate,,:r \'alues happen 10 appear m lhe state register when we power up the circuit. , ot kno\\;n" the initial -tale of J -ircuil could pose a problem-for example. we don't want ur laser timer ntroller I ;!:lrt in state lhat immediately turns on the laser. One olu ti on i to add an additional input. r eset. to e",,) L'OnlI'Olier. tting "ese: to 1 should cau e a load of the initial state into the stnlC regber. Thi inioal 51 Ie ' W be forced into the tate register. The re ' et and set inputs of a flip-Hop ( OJ 10 \ ') b;md~ in thi situalion. We enn imply onnect the controller' - rese input I the ('e. l;md input of the tate register" Hip-ft ps in a \\ ay that sets the Iltp-Il< s 10 the imtiJI 5t I when rese i 1. For c~antple. if the initial state of n ~-bil sw regi, r . h,'Illd lhen we could nneet the ontrollcr's re.cI inrut 10 re,et .ll1d set tnpU flop . . as .ho\\ n in Figure 3.M .
136 3 SeqUential L .
ogle DeSign- Controllers
.
3.8 Product PrOfile-Pacemaker
Or cou"e . for thi; reset fun c-
-
tIonality to wor~ as desi red. the deSigner must
lhal the conlroll er ', reset input is I when the
sYStem is fir>! powered up. Ensuring lhe reset input is I duri ng power up an be hnndlcd using an appropriate e lec lronic circui t connected to the On/off Sw itch. the description of \Vh,ch is beyond Our scope. ate that. if the synchronous re ' et Or se t inputs of a flip- na p are Used . then the earlier-discus ed etup and ho ld times. and assoc i. ated metastab il ity issues. apply 10 tho e reset and sct inpu ts.
Nonideal Cont
II B ' . ro er ehavlOr: Output Glitches
~
b
cn~lIrc
Combinational logiC st
elk
State register
t> ....
Of-
~
f;;o-
tsO
,---
t> ~p-
resel
~
O' p..
D
t>
0 f.-
S--
Figure 3.66 Three·cycle ·high laser timer con~lIer with a reset input th at loads the stale register with the initial "Iatc 0 1.
G litching is the presence of temporary values on a wi re. typica ll y caused by differe~t delays of different log ic paths leading 10 thm wi re. We saw an example of gluchll1g m Figure 3. 13. G litchino wi ll also often occur when a controllcr changes states, due to dlffe rem path lenOlhs fr~m each of lhe controller's state reg i ter flip- fl op to the controller's OUlpUI~. Consider lhe Ihrec·cycJes-hioh laser timer design in Figure 3.50. The laser shou ld be off (output x =O) in Slat: 5150=00 and on (x - I) in . tates 5150- 01. sIs 0 = 1 O. and 5 I 50= II. However. the delay from 5 I 10 x's OR gatc 111 thc fig ure could be lo nger lhan the delay from 50 to that OR gate. The resu lt could be lhat when the state regi ster changes Slate from 5150 =01 to 5150-10. the OR gate ' input cou ld momentaril y ee a 00. The OR gate wou ld thu output 0 momentarily (a glitch). In the laser timer example. that glitch could momentarily shut off the lascr-an undeS Ired ituation. Even "'or~e would be glitche that momentarily tum all a la;cr. . Real deSigner must detenninc whether such glitching would really pose a proble~ 111 lheir pani ular ~y tem. and if so. those designer\ should take action to avoid s~ch gluchll1g. One solution in the laser timer example might be to insen a 0 nip-fl p after x s OR gate 10 Figure 3.50. Thi ~ would shift the x output later by I clock cycle (\till resulting 111 three cycles high. however). bu t shou ld eliminate glitche\ see n at the x output. as only the table value appearing at the output would be loaded into the fl ip-flop on a ri~ing clock edge.
Active-Low Inputs (Negative Logic) D
mil now, we ha ve a \umcd acti ve·high input' on flIp-flop, and other componelll'. An actil'e-iligil input h a comrol Input who\c a"ociated operatIon I< aCll~:llcd hy ,cll ll1g the '"put to I For examplc, If an Input ca n rc'ct a fl,p-Oop. we '" umed that '"flut rc'ct ",hen thc Input \ value Wi" I Hnv.c'er, a
-..,
.
__----...
o figura J 67
f)
Olr-O
lp Wllh
In\\- )n hrnnuwlo rr'Cl IOp"l
3.6 SEQUENTIAL LOGIC OPTI MIZATI ONS AND 'TRADEOFFS (SEE SECTION 6.3) The earlier secti ons described how to design basic sequential logic. Thi section. "hicb phys icall y appears in this book a Section 6.3. describes how to create bmer sequential logic (smaller. fas ter, etc.) using optimization and tradeoffs. One use of !hi boo ' describes sequenti al log ic design optimization and tradeoffs immedialel~ after inrroducing basic sequential logic design. meaning now. An altemati\'e use describes seq uenti al logic design optimizalions and tradeoff later. after completing the introduc. lion of basic datapath components and RTL de ign (Chapters -4 and -).
3.7 SEQUENTIAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES (SEE SECTION 9.3) This section. which phy icalJy appears in thi book as Se ti n 9.3, lI1trodu . the_ use oi HDLs for describing equenlial logic. One use of this book imrodu uch use ot H~Ls immed iately after introducing basi equential logi design. meaning nO\\ . An altemat]\e use introduces such HDL use later.
3.8 PRODUCT PROFILE-PACEMAKER
O' ~
A pn emaker is nn electronic devi e that pnl\ ides electrical stimulati n t .~ hem to help regulate 3 hean ' beating. .. teau ing 3 heart \\ hose bod)'~ natural "lOtnn~I" r, ~ not worki nc properh . perhaps due to di.ease. ImplantJble pa III 'e '_ \\hl~h ,~,_ . '''' •' h0 \\ n III . F''ll"ni. _'~' ally placed, under .the '~1Il ' . . an' \\ l'rn b\. el\ r I :: mill" mcricUlt'. The) nrc pl.l\\en:d b) J bJllcl) thm t,st tcn ~ af' r nh:n!. Pa.: nl _ illlpnl\cd the qt;n lit) (1f hfe II.' \\ ell ,h l'llgth ned the li\c', f mJn\ nil II I,,", .'1
=
ad;'e
137
component can instead have an active- low input. An active-low input (also known as a /l egative logic input) is a control input whose operalion is aClivated by seuing the input to O. Figure 3.67 depicts a 0 Rip-Rap with an acti ve-low synchronous reset input-the circle at the R input indicates that the R input is aClive-low. Thus. LO reset the flip-flop LO O. we would set R to 0, whereas for nonnal 0 Rip-flop operalion, we would set R LO 1. Active-low inpulS can OCcur on any component with a control input. not just on flipfl ops. For example, the enable control input on a decoder could be active-Iow-seuing that enable to 0 (meaning the decoder is enabled) would cause nonnal decoder operation, while selli ng the input to I (meaning the decoder is disabled) would resu lt in all OUtpUls being O. When discussing the behavior of a component. designers wiIJ often use the Lenn assert to mean setting a control input to the val ue that activates the associated operation. Thus, we might say that one must "assen " the R inpul of the 0 flip-flop in Figure 3.6 in order to reset the Rip-fl op to O. Using the tenn assen avoids pos ible contu ion mal could occur when some control inputs are active-high and others are acti\·e-Io". Active-low inputs typicall y exist when the internal design of the component requires fewer gates when implemented with an active- low input than with an active-high input
138
3 Sequential Logic Design-Controllers
. . I (left and right) . The ve nlrtcles . I ) 'md I WO venlrl C cs . . ,' , the blood fr0111 the vein. A very A heart has two atria (left and ng 11 , . "I he utna rece"e , . I contraction in the heart s rt ght venush the blood out to the artenes. whl e t p . ' Ie I'f th e simple pacemaker has one sensor 10 detect a" nalll I t'ra 1111ulation to thm nght ve Olnc '' period- tYPIC" . II YJU ' t un der one " to deI'IVer electnca" s wire d ' . I d one output tnc e, an . h" pec lfie li me " nalUral contraction doesn't occur WIt In , s ct',on nO! only in the nght ventncle, . causes a contra . second. Such electrical Sll.mu lallon but also the left ventricle.
3.8 Product Profile-Pacemaker
139
The ri ght side of the fig ure shows the controller's behavior as an FSM. Initially. the COOlroller reset the timer in state ReselTimer by setting t = 1. ormally. the controller wa its in state Wail , and stays in that state as long as a contraction is nO! detected (5 ') and the timer does not reach 0 ( z '). If the controller detects a natural contraction ( 5), then the controller again resets the timer and returns to waiting again. On the other hand. if the cOOlroller sees that the timer has reached 0 (z = I), then the controller goes to stale Pace. which paces the heart by setting p= 1, after which the controller returns to waiting again. Thus, a long as the heart Contracts naturally. the pacemaker applies 00 stimulation to the hean . But if the heart doesn't contract naturall y within 0.8 econds of the last contraction (natural or paced), the pacemaker forces a contraction. The atri a receive blood from the veins. and contract to push the blood iDlO the "eotric1es. The atri al COOlractions OCcur jusl before the ventricular contractions. Therefore. many pacemakers. known as "atrioventricul ar" pacemakers. sense and pace nO! just the ventricular contractions, but also the alrial contractions. Such pacemakers thus bave two sensors, and two output wires for electri cal stim ulation. and may provide bener cardiac output, with the des irable re ult being higher blood pressure (Figure 3.70). Inputs: sa, za, SV, zv Outputs: pa, la. pv. tv la=1
Figure 3.68 Pacemaker with leads (Ieil). and pacemaker . localion under the skin (right). Counesy of Medtronie. Inc. . . fa sim Ie pacemaker's control ler usi ng the FSM in We can descn be the behaVIOr 0 h P h pac ' maker con i ting of a controller and 'de of the figu re sows t e e . 69 Th I ft Figure 3. . e e Sl . h the timer when t - 1. pon being reset. the . Th " h n input t wh,c resets . a umer. e umer as a . 8 d If the timer cou nts down to O. the lImer timer begins counting down from °id ~con ;befOre rcaching O. in which case the timer sets its output z to 1. Th~ II mer COhU . re t:rt counting down from 0.8 seconds again. d t z to 1 and Instead t e lImer . . . h ocs not se . h' h ' 1 when a contraction i~ sen~ed In the ng t ven. The controller has an input s. w IC IS h' h the controller sets to 1 when the controller tricle. The cOOlroller has an output p. w IC wants to cause a paced contraction.
psI
t. o F,gure 3 69 A ba'lt pacemaker", ."nlloller
~SM
Figure 3.70 An atriovenlrieular pacemaker'S contrOller FSM (using the comenoon thaI FS)\ OUIPUIS nOI explici lly sel in a Slale arc implieili, sel 10 0). The pacemaker has two ti mers. one for the right atrium (TimerA) and ne for th... right ventricle (TilllerV). The comroller initiall) resets TimerA in tate Re etTunuA. and then wailS for a nat ura l atria l contra tion. or for the timer 10 reach O. If the xmuoller detects a natu ral at ri al contraction (sa). then the ontroller skips pacing of the ~trium. On the other hand. if Tilll erA rea he 0 first. Ihen th ... :omroller gO for nat ural entricular con traction. or for the timer to ~Jch O. If a n"rural , ... ntnculJ.r u'fltr.lCtion occurs. the contmllcr skips plICing of the \enmde. n the other hand. If n a\ reaches 0 first. then the controlla gO
d
I~O
Sequential Logic Design-Controllers
3.1 0 Exercises
Th is example demonstrates Iho use fulness or FSMs in desc ribing a com rOller's behavior. Real pace makers have controllers wilh lens or even hundreds or SlaleS 10 deal wilh ""ri ous details lhal we left Oul of Ihe example ror simpli cilY· With Ihe adve nl of vcry low-power microprocessors . a trend in pacemaker design is lhm or implemenling Ihe FSM on a mi roprocessor ralher than wllh a custom scquenllal ci rcui!. Microprocessor impiel11clllalion yields Ihe advanwge or easy reprog ramming or lhe FSM . expanding the range of treatmenls Ihat a doclor can ex peflmenl wllh.
141
(d) 10 GHz (PCs of Ihe early 2000s)
(e) I THz ( I lerahcnz) 3.2 Compule Ihc clock . r' (a) 32.768 kHz pe ,od for the following clock frequencies. (b) 100 MHz (c) 1.5 GHz (d) 2.4 GHz
Compute Ihe clock frequency for the following clock periods. 3.3 (a) I s (b) (c) (d) (e)
3.9 CHAPTER SUMMARY Seclion 3. 1 introduced Ihe concepl or sequenlia l circuilS. namely circuils thai slore bits, meaning the circuils have memory. known as 5(3IC. Section 3.2 developed a series of increasingly robusl bil storage bl ocks. includ ing Ihe SR lalch. D lalch. D nip-nap. and fina ll y a register. which can store muliiple bils. The seclion al a introduced the concept of a clock. whic h synchronizes Ihe loads or registers. Sec lion 3.3 introduced fin ite-state machines (FSMs) for capluring the desired behavior of a equenlial circuit. and a slandard archileclure able 10 implemenl FSM s. Wilh an FSM implemenled using the archi lecture known as a controller. Seclion 3.4 then descri bed a fi ve- tep process for con"en ing an FSM 10 a controller implementati on. Seclion 3.5 highlighled some types of flip- fl ops Olher lhan Ihe D flip-fl op. Ihose olher Iypes being popul ar in the past. Thai seclion also desc ribed several liming issues related 10 Ihe use or flip-fl op . including setup lime. hold lime. and metastabililY. The seclion introduced asynchro nous clear and sel inpu ts to nip-flops. and described their usc for inili alizing an F M to il initial tate. Secl ion 3.8 high li ghled a card iac pacemaker and illu trated the u e of an FSM 10 describe lhe pacemaker's behavior. Designi ng a combinational circ uil begi ns by capluring Ihe desi red circuit behavior using either an eq ualion or a lrulh table. and lhen following a everal slep process 10 convert Ihe behavior 10 a combi nalional ci rcui!. Designing a eq uenlial ci rcuil begins by caplUring the des ired circuil behavior as an FSM . and then following a cveral step process to convert the behavior lO a circuil consi ling or a register and a combi nalional circui!. known as a con troller. ConceplUall y. then. with the knowledge in Chapler 2 and 3. we can build any digital circui!. However. many digita l ci rcuil dea l wilh inpul data many bits wide. ; uch as five 32-bit inpu l5. Imagine how complex ur equal ion . lruth tables. or FSM s would be if they involved 5"32 160 inpul'. Fortu nalely. components have been developed specifically 10 deal with data inpuls and Ihus ~impl ify the de ign process--components Ihal will be described in lhe ne~1 chapler.
=
I ms 20 ns I ns 1.5 ps
3 .~ Compule Ihe clock r (a) 500 ms requency "or the following clock periods. (b) 400 ns (c) 4
ns
(d) 20 ps
3.5 *Assume scienlists have developed a t hO h lance, meaning signals w'lh ' h' . Ip 3vmg perfect transi tors and "ires 'With no resissecond. Assuming th I k
OUf
I In t IS chip can tra\'e l at lh peed f . '" digital circu't h 'dth e5 0 hghl. or 3xlv- meters! ' as a w, oP - mm and a h'!!h f -
e c oc . period and clock frequenc
a single cl ock period is:
'h
y. \\ ere
th
-
e,_ t 0 ~ mm. compute
.
e longest dl lance an) signal must £r3\"cl durim~:
(a) one-eighlh of the wid,h of the circ uil
-
(b) one-half the heigh, of the circuit
(c) lhe widlh of Ihe circuit (d) diagonally across the circuit (e) Ihe perime,er of lhe circuit 3.6 Trace Ihe behavior of an 5R latch for lhe fo llowino· . . for a long time. then 5 chanaes 10 I and ~ Slluaoon. Q. . and Rare 0 and
Qs
3.7 Repeal 3.6. but aSS ume thai S "'as hanged .' rop Exercise h to I just long enough for P
ag.atc l rough one logic gate. after \\ hich
nOI sallsf), Ihe hold ,ime of the lalch.
logic g3lcs have a tiny bu t nonzero
deI3~ .
'"pllt
.
'
mplete the nmmg
c (0)
S~~~~__~_______
reprc,enL' an e pecl3l1) chnilenglllg problem.
A ____~!l~
SEc.-no ' 3.2: STORI NG ONE BIT- FUr', f'LOl'S
SI
3. 1 Compule Ihe clocl period for Ihe folil)wlIlg cJocllrequcnClc, (J) ')0 lHI (Cilfly compule"l (hi lfJO MHI (Son} Pld)'IJ"'1Il 2 pre""'''''1 Ie) 1 ~ Glil ({nlel Pcnllum 4 prll"t Or)
Al Q
Figure 3.71
~
" 1!OJJ _
\\as changed back to O--in other \\ords.
Gs 3.8 ;f"JCC the behavior of a level-sensili'e 5R la'ch (see Figure , I~l ~ th . "gure 3.7 1. Assume 5 1. RI. and Q are inilialh 0 Co . ' . or e
3.10 EXERCISES Any problem nOled wilh an a\icri,k
!la,,,
be
____~r_l
'-----
10
did
p"ttem m
dJ~~ J..~""Ummg
142
. I L 'c Desig n- Controll ers Sequentl. ogl
. . 3 I~ ) fo r the input pattern 111 .. SR I teh (~c;t! Figure. . .' . . T ,. h behavior of a level-scnslt l\'C ... a 0 COI npktc the timing diag ram . ass ummg .\.9 ract: I e R i d Q arc 1Il 1 1l ~l ll y . Fiourc 3.1'1. A~S 1l11le S I. . an I lo~iC gates have a tiny but nonzero de la).
3.10 Exercises 3.1 3
----,
Trace the behavior of an edge- tri ggered D Ri p-Rop using a master-servant design (see Figure 3.24) for the inp ut pattern in Figure 3.76. Ass ume each internal latch initially stores a O. Complete the timing di agram, ass uming logic gates have a ti ny but nonzero delay.
n
n
R
L-J
C~
C
S
143
>
D/Dm
n
~r--JI~._ _ _ _ _ _ _ _ _ _~
I~_____ ~_ _ _ _ _ _ _
Cm
Sl
Orn/Ds
R1
Cs Q
. .
d'
om!1l 13,::='
as
fo r Exercise 3.9
Fi ure 3.72 SR latc h input pattern tIIll1llg • • g ] for the. "'put pattern . 111 . '. SR latch (sce F'Igure.. C Ictc the ti min " dIag ram. ass uming T h behavior of ;1 levcl-sensIU\ C 51 RI and Q are ini tiall y O. OI1lP c ,\.10 race t e ,
I ~)
Figure 3.76 Edge- triggered D Rip-Rap inp ut pattern timing illagram for Exercise 3. 13
Figu re 3.73. Assume . ' de la ' logic gates have :l liny but nOlllcro ).
3. 14 Trace th e behavior of an edge-triggered D Rip-Rap using the master-servant design (see Figure 3.24) for the inpu t pattern in Fig ure 3.77. Assume each internal latch irtitially stores a O. Complete the liming diag ram. assumin g logic ga tes have a tiny but nonzero delay.
~--,
n n
C S
n
R
C D/Dm
Sl
Cm
R1
Orn/Ds
a
Cs
as
. . di agrn m for Exe ise 3. 10 Figure 3.73 5R lalc h in put pattern II mlllg
Figure 3.77 Edge- triggered D Hip- Hop inpul patte rn tim ing diagram for Exercise 3.1 4
ure 3 I ) for the inpu t pattern in Figure 3.74. Assume Q .1.11 Trace the beha"ior of a D latch (see F ig . . I gic g.te haH'" ti n), bu t nonze ro delay. is inilially O. Complete the liming diagram. assu ming 0
I
I L--J
~-- I
C
~
3.1 5 Compare the behavior of D lalc h an d D Rip-Rop devices by completing the timing illagram in Figure 3.78. Ass ume each device initiall y stores a O. Provide a brief explanatioo of the be havior o f each device.
'-----
D~L_ _ _ _~rlL----
C--.J
Figure 3.74 D latch input pattern timing diagram for E
Figure 3.78 D I31Ch and D flip-Rap input pattern ti ming illagram for E.lereise 3. 1
Fi J 18) (or the IIlPUI p.llern III Ftgure J .75. ume Q C' .1.12 Trace the behavior of a D latch (\ee Igure : logIC gate, h",c ,I tin) bu t nonlero del.). P L U'S " initiall) O. Complete Ihe IImlllg dtagrnm. as\um"'g
D
L
a (D latch) a (D flip-flop)
R
a
C
L-1
D~~_ _~
S
3. I 6 Compare the behavior of D latch and D Hi p-Rap de' ice by completing the timing di8gram in Fig ure 3.79. Assume each device initiall) stores a O. Provide a brief explanation of the bdla,"1OI" of each de ice.
- . f I L -____~
C D _ _ __
S R
a (D flip·llop)
o Figure 3 75 0 lilkh ",put pJttern IlIning diagram f.. r
---'
a (D la tCh) Figure 3.79 D latl'll und D tli p-Ih,p '"I ut p,mern ttnllng dl'l!)rnm f..... E.«n:" _1, I
r:"",'C 1 12
t
s
I~
3 Sequentia l Logic Design- Controlle rs
3.10 Exercises
. ..
niches connected in ~c ri c:, ( the o utput o f o ne IS can·
vC how D I. 3 cl 'oc k Wi.l h a long hi gh-li me can cause the value . , ', of three Icvcl-senslll a Cl feUI h . I k d 10 the input of the nexth). ow h orc th 'tn one Intch dUring the same c oc 'cklc throug III • at the input of the fi rst D late 10 Ln
3. t7 C r ealc
neet e
cycle . . fl . ' lid , how how the input of the first D . cdgc- t n·." ." . how long the CIOC k signa ' I 'IS h'Ig. h 3 18 Repeal Exercist: 17 uSlIlg ~el,;' red D . flif1 P' op, 0 maller . latch does nol tri ckle through to the nex t fllp- op n 3. 19
sin2 D fl ip-flops. creatc tI circuit wi th ~an input X and an output Y. such that Y always equals X ddayed by twO clock cycles.
.'.20 Us ing fou r registers. des ign a circ ui~ lhal stores the previous four v~ l u ~:-;
a3 a2 a 1 aO
c
- t>
12
II
10
reg(4)
03 0201 00
see n at an 8-bil inpu t D. The circ uit
should have a single S·bit output that ca n be configured usin g IWO in pu tS 5 I
and sO to output anyone of l~e fou r
reg isters. (Hin t: use an 8-bu ..h: 1
b3 b2 b1 13
12 11 reg (4)
mux .)
3.21 Consider three ~-bi l registers connee ted togethe r as shown in ~igure 3.80. Assume the initial values In the registers are unknown . Trace the behavior of the reg isters by completi ng the Liming diagram of Figure
I I I1
bO 10
3.23 Draw a state diagram for an FSM thai has an input X and an OUlput Y. Wheneve r X changes from 0 to I , Y should become I for two clock cycles and then return to O-even if X is sti ll I. (Assume for this problem and all other FSM problems th at an implicit ri sing clock is ANDed with every FSM transition condiLion.)
a3 a2 a1 aO
c
3.24 Draw a state di agram for an FSM with no inpu ts and three outputs, x, y. and z. xyz should always follow th e following sequence: 000. 00 1, 0 10. 100. repeal. The outp ut shoul d change onl y on a rising clock edge. Make 000 the initial Sla te .
"I Ti l 13
145
SECTION 3.3: FINITE-STA TE MACHINES (FSM) A D CO NTROLLERS
13 ~
12
11
10
reg(4)
ao
030201 00
03 02 01
I I I I. c3 c2 cl cO
d3 d2 dl dO
J J J1
Figu re 3.8lI Register confi guraLion.
3.81.
3.25 Do Exercise 24, but add an inpu t I tha t can stop the sequence when sel to O. When input I returns to I . th e sequence res um es from where it left off. 3.26 Do Exercise 25, exce pt the equence starts from 000 whenever I returns 10 I. 3.27 A wriSlwatc h display can show one of four items: the
d3 d2 dl dO time, the alann. th e stopwatch. or the date. controlled by two signals s I and sO (00 displays the Lime. 0 I the figure 3.83 Regi ter configurntioo. alarm. 10 the stopwatch, and II th e date-assume s I sO co ntrol an -bit-wide mu x that passes through the appropriate regi ter). Pressing a button B (which sets B = I ) sequ ences the display to th e next item (if the presentl) displayed item is the date. th e ne xt item is the current time). Create a state dia!!J'llID for an FS~l descri bing this seq uencing behavior. ha ving an input bit B. and 1"0 oUlp;t bilS 1 and sO. Be sure ( 0 only sequence forward by one item each Lime the bUllon is pressed regardl
of
how long the bUllon i pressed-in other words. be sure 10 wait for the bunoo to be relea..'>ed afrer seque ncing forward one item. Use shan but descriplh-e names for each ute. :\.faki! C b3 .. bO
c3 .. cO d3 .. dO
Fig ure 3.81 4-bit reg"ter inpu t pattern timing diagram for Exe rci,e 3.21 . d ether a< ,ho" n In Figure 3.83. Ass ume the initial 3.22 ConSider three 4-bit registers ck'onnecteTr~~~ the behaVIOr of the reg"te" by ompleting the vaJues in the regl.sler) arc un nOwn. liming diagram of Figure 3.82.
di splaying th e time be the initia l stale. 3.2S Extend the state diag ram you created in Exercise _7 by adding an input R. R= I ~ FSM to return to the state Lhat displays the Lime.
3.29 Draw a slate diagmlll for an FSM with an input 'em and three outputs. ..t'• •~ and :. The t:' .. outputs genera te a sequence called a Gray code in \\ hi b exactly one of the three oulpUlS changes from 0 to I or from I to O. The Gray code sequence that the FSM should ""tpUt is 000. 0 IO. 0 II. 00 1. 10 1. I II , 11 0. 100. repeal. The output should bange 001) on 3 rb'J11g clock edge when the input gem = I. Make the initial tate 000. 3.30 Trace th ro ugh the excc ution of the FSM ),ou created in E,
genl C b3 bO
c s
c3 .. cO d3 .dO
Figu r.3.82 4-DIl reg"tcr Input pallern IImln8 ding".", rnr F\c""" \ 22
Figure 3.84 F M input pattem tinlln!! di~ram fN
\ <1\'1
.. .\0
c
1~6
Sequential log ic Desig n- Controllers ",
3.10 Exercises "
FSM in Fi ,ure 3.85. >ueh that the FSM ;tart; in state Wail. ~ b I bch'lVior of the circu li III English. Dt:scn c I le •
, H Dr.1\\ a t!ll1m£, di ag ram lor tht: I ~ .. reacht!~ S13h: EN, and return s to \\'ail.
Inputs: s,r Oulpuls: a.en
147
3.39 Using the five-step processor for designi ng a con-
troller. can veil Ihe FSM of Figure 3.87 to a co~trolJ er. implementing the controller using a stale regISter and logic gates. 3.40 Using the five-slep process for designing a con-
troller. canveil the FSM you created for Exercise 24 to a con~ro lle r. implementing (he controller using a stale register and logic gates.
y=l
3.41 Using the five-slep process for deSigning a cona;1
troller. convert the FSM you created for Exercise 27 to a controller. implementing the controller using a Siale register and log ic gales.
en;O
a;O en;O
en= 1
Figure 3.85 FSM for Exercise 3.31 . . be- f tates indicate the srn allest possible number of bilS "\ l' For FSi\I s with the follOWing num rs 0 5 . . .. - for:l st.:lIe reg ister representing those stJtes:
Figure 3.87 FSM for Exercise 339
3.42 Using Ihe five-step process for designing a controller. canvell the FSM you created for Exer-
CIS~ 29
to a COntroller, implementing [he controller using a stale register and logic gates.
3.43 Usmg the five-Slep process for designing a controller. convell the FSM in Figure 3.88 to a ~ontroller.. Slopping once you have created the state table. Note: your state table will be quite arge. havmg 32 rows-you might therefore want to use a computer tool. like a word pr0ceSSOr Or spreads heel. to draw !he table.
(a) 4
lnputs:g.r
(hI 8 9 (d) 23 (e) 900 3._'3 How many possible states can be represenled by a 16-bi t register? .. . 3 ,~ If an FSM has N tates. what is the maximum number of poss~ble tranSlllons thai co~ld ext~t .. in th e FSM (assuming there are a large number of inpuls. meaning the number of lranSlllOns IS
Outputs: x.y.z
(c)
nol limited by the number of inputS)? 3.35 .Assuming one inpul and one output. how many po sible four-statc FSM exist? 3.36 . Suppose you are given twO FSMs that execule co n~urrentl y.. De'~ ribc an approach for merging those two FSM into a ingle FSM with identical funclionalllY as the two epara" FSM . and provide an example. If the fir.it FSM has , Iates and the sccond has M states. how many tate will the merged FSM have? 3.37 · Sometimes dividing a large FSM into t,,·o , mailer FSMs res ul tS in simpler circuitry. Divide the F M shown in Figure 3.88 into two FSMs. one contaming GO-G3. the other containing G4-G7. You may add
xyz=OlO
xyz=Oll
X}'Z=111
Figure 3.88 FSM for Exercises 3.37 and 3,43. 3.~~ Create an FSM Ihat has an inpul X and an output Y. Whenever X changes from 0 to I. r should become I for five clock cycles and then relurn to O--even if X is
slill I. Using the five-step process for designing a controller. convell the FSM to a controller. stopping
addilional Mates, transitions, and inputs or outputs
between the two FSMs. as required. Hint: you will need to mtraduce signal; between the FSM, for one FSM to tell the other FSM to go to some state.
once you have crcnred the Siale table.
3.45 The FSM in Figure 3.89 has two problems: one state hn two lr.lnsitions whose condition ('Quid simulta~ neausly c\'nlu3Ie 10 lllIc. and another states has
SECTION 3.4: CONTROLLER OESIG N UX U"ng the fi,e-step processor for de"gl1lng 2 controller. con, ell the FSM of Figur. 3.86 10 a controller. Implemenlmg the controller u
xyz=110
lransistions that aren't gunrnnleed
Figure 386 F
(0
hu\'c at leas( one
of Ihe tmnsition conditions true. By ORing and ANDing Ihe conditions for each stnte's tr.lnsitions. prove that these problems exist. Then. fix these problems by refining the F M. taking your best gue. < .s (0 whnl \\o.~ the F ~I creator's imcllt.
xyz=101
xyz=001
148
Sequential Logic Design-Controllers
3.10 Exercises . I circuil shown in Figure 3.90.
3..16 Reverse engineer the behavior of the sequcnlla
Combinational logic
o
COl
\.-----r~fj Ul
~~
51
sO
Figure 3.90 A seq uen(al I circuit 10 be reverse engineered.
SECTION 3.5: MORE ON FLIP· FLOPS AND CONTROLLERS ' . . d shown in Figure 3.92. Trace lhe behav Ior of the flIp3.47 Conside r lhree T fllp-flopsconn ecl.e e as in Fi eure 3.9 1. Ass ume a ll the flip-flops initially flops by compleLing the umJng dlCloram 0 contain 0·5, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ __ _ __ T
C 01
02 03 Figure 3.91 T flip-fl op input panem timing di agram for Exercise 3.47 3.48 Show how to con neCl fo ur T fl ip-fl ops 001 T T together to create a circuit that counl~ fro~ T o to 15 in binary and back to 0 agaJO- JO other words, that counLS 0000. 000 I, 00 I0, .... 11 11 , and back 10 0000 agai n. Hint: consider usi ng the Q OUlput of a flip-flop as the C _~_ _ _--_ _ _....J clock inpu t of another flip-fl op. Assume all lhe flip-flops in itially co ntain O·s.
Figure 3.92 Three T flip-fl ops.
3.49 Define metastabi lity. · a cantro II er wll' h a 4- b'I t sta te register th at gets synchronou sly initialized to state 1010 3.5 O DeSign when an input resel is SCI to 1. 3.5 1 ' Design a D nip-fl op with asy nchronous reset, AR. and a,y nchronous set, AS, inputs using basic logic gates.
~
149
DESIGNER PROFILE Brian got hi s baChelors deg ree in Electri cal
Engineerin g and then worked for severa l years. Realizing the future demand for digi tal design targeting an increasingly popular type of digi ta l chip known as FPGAs (see Chapter 7), he returned to school to obtain a masters degree in Elec trical Engineering with a thesis topic targe ting dig ital design for FPGAs. He has bee n employed at two different companies, and is now working as an independen t digital design consultant. He has worked on a number of projects. including a system that prevents house fires by tripping a circui t breaker when current running in the circuit indica tes arcing is occurring, a microprocessor architeclUre for speeding up the processing of di giti zed video, and a mammography machine for precise location detection of tum ors in humans.
One of th e proj ects he has found most interesti ng was a baggage scanner for detectin g explosives. " In th at system. there is a lot of data being acqui red as well as motors running, x-rays being beamed, and other things happening. all at the same time. To be successful. you have to pay anent ion to detai l, and yo u have to communicate wi th the other design teams so every one is on the sa me page." He fou nd th at proj ec t particularl y interestin g because "1 was working on a small part of a very large. co mplex machine. We had to stay focu sed on our part of the design, while at Lhe same time being mindfu l of how all the parts were going to fit toge ther in
th e end." Thus, bei ng able to work alone as weil as in large groups was imponant. requiring good communicati on and team skills. And being able to understand not onl y a part of lhe system, bUl also important aspects of the oth er parts was also important.. requiring knowledge of diverse topics. Brian is now an independent digital design consultan~ something that many electrical engineers, computer engineers. and compu ter scientists choose to do after ge tting experience in lheir field. " I like the flexibility that bei ng a co nsultant offers. On the plus side. I get to work on a wi de variety of projecLS. The drawback is that sometimes I onl y ge t to work on a small part of a projec~ rather than see ing a product through from stan to finish. And of course being an independent consultant means there's less stability than a regular positio n at a company, but I don ' t mind that " Brian has taken advantage of lhe flexibi lity provided by consulting by taking a part-time job leaching an undergraduate digital design course and an embedded systems course at a university. " I really enjoy leaching and I have learned a 10l through teaching. And I enjoy introd ucing students to the field of embedded systems." Asked what he likes most aboul the field of digital design, he says. " I like building prodUCLS that make people's lives easier, or safer, or more fun. That's sa tisfying." Asked to give advice to studen ts. he says that ODe imponant lhing is "to ask questions. Don'l be afraid of looki ng dumb when you ask questions .t a new job. People don't expect you to know everything, bUl they do expect you to ask questions when you are unsure. Besides. askin g questions is an importanl part of learning."
4.2 Registers
as register-transfer level (R TL ) components, also known as datapath components. and a Circu it composed of such componenls is known as a datapalh . Datapalhs can become quile complex, and Iherefore il is crucial to build datapaths :rom. a SCI of dalapalh componenls Ihal each encapsulale an approprialely high level of uncllOnallly. For example, if you were asked whal components make up an aUlomobile. you wou ld probably lisl components like an engine, tires, a chassis. a body, and so on. Each of Ihose componems encapsulares a high-level function of the automobile. You thought of a tire, nOi of Ihe rubber, slee! wires, valve stem, valve, sidewalls, and oiller parts thai make up the lire. Those delai led pans make up Ihe design of a lire. nOI an aUIOmobi le . A tire is an appropriately high level of componem when thinking of a car; a valve stem IS nol. Likewise, When we design dalaparhs, we mUSI have a set of dalapath companems aI Ihe appropriately hi gh level- logic gales are 100 low-level. This chapler defines such a sel of datapalh componenlS. and also inLroduces simple dalapal hs. In Chapler 5, we' ll see how 10 create more advanced darapalhs. and how 10 combine datapat hs and Controllers 10 bu ild an even higher-level componem known as a processor.
4 Datapath Components 4.1 INTRODUCTION . . increasinoly complex building blocks Ihat can be used to Chaplers 2 and 3 II1lroduced . 0 d diaDic o'lles mul!iplexors, decoders, basic build digilal circui ls. Those blocks IO C1u e ° °d fa; implementing systems having lLroliers Controllers are goo . d fi II reglSlers, an na y cal. .' 1 d eneralin o some number of control output sigf antral Inpul Slona S an g o . some num ber a c o . I . I become 1 (correspond 109 perhaps see a part icul ar conlro II1pU Ie. 'f nals. For examp I. .wed) Ihen we may want 10 gener,ate ,a 1 on a control output (corre. b to a bUllon ell1g ples s e , . I ' 'h ler we inslead focus on creating . I liohl !lIrnln 0 on) In I liS C ap , spondll1g penaps 10 a 0 d ~ ° I ~s havi no dara inputs and outputs. In general, bui ldin g blocks Ihat are goo or sys el . ' 0 II )' digita l ;ystems have IWO Iypes of inpuls (and oUlpU IS as we .
4.2 REGISTERS An N-bit register is a sequemial componem ab le 10 store N bils. Typical regi ter width (the number of bit N) are 8, 16, and 32 bits, though any wid th is possible. The bilS in a register often represenl data, such as 8 bils represeming a lemperature as a binary number. The common name used for storing data imo a register is loading, although tbe words writing and storing are also used. The opposile aClion of loading a regi ler is known as reading a register's coments. Reading consisls merely of connecting to the regi ler's outputs-note thai reading therefore i not synchron ized with Ihe clock. and funherrnore. nOle Ihal reading does nOi remove the bils from the regi ter or change them in any way. Regislers come in a variely of slyles. We'll introduce some of the mOSI common slyles in thi s seclion. Registers are perhaps the most fundamemal dalapath campanelli. a we will provide numerous examples of their design and their use.
one bil, representing a part"icu Control' A con tra I .InpUI .IS Iypically ' . lar event .
occurri~o OUlside Ihe system. li ke a bUllon being pressed,.or representing a panicor a car bemg " . ular stateo of sameth'mg OU tSI'de the system, like a door being closed at an intersection. Control inputs could sometimes be grouped 11110 mullJple bus. 4. . wh'ICh a f 16 bUllon is pressed, or 2 bits representing each ilke bits represenllng of 4 possi ble states of a door (closed. open 113rd, open 2/3rd,. or fu lly open), . II y used directly to influence a controller s present state. Control .II1pUtS are typlca
Parallel load Register
Data: A data input is typically multiple bi ts, collect ively repr~senting a single a temperature In binary, A' . 7-bu . For examp Ie. a 32-b'lt input may represent entlly. . . 00 ft .Input may represen tthe present floor location of an.elevator . In a I "- oar bUlldmg, · Input 111 that we A dala Input may be a s·In gle bit I differin 0o from a slOgle-bll control , don' t directly rely on that bit's value to influence the controller s present state.
Not all input can be strictly classifi ed as ei lher comrol or dala-th e~e are some inputs thai fall somewhere on the border in belween the IWO Iypes. BUI most Inputs can be classified as one or the other. (A nd. of course, a digi tal ystem also has power Inputs, ground inputs, and clock inpuls too, in addition to conlrol and data inputs.) .. . Coni rollers are a good building block for buildi ng systems cons lstll1g mall1ly or comrol inpu ts and cOlllrol OUlputS. But we also need building block. for systems con· si . ting of data inpuls and OUlpUIS. In particular, we need registers 10 hold the data, and functional unilS to operale on (e.g. add or divide) Ihe daw. Such component are known 150
151
The mas I basic type of regi ster, shown in Figure 3.30 in Chapter 3. cons iSIs ll1erel~ of a set of flip-flops that gel loaded on every clock cycle. Thai ba ic regi ler is useful as the stale regi ter in a coni roller, since the state register is loaded on every clock cycle. Ho\\ever, for most other uses of registers, we walll ome way 10 control whether or nOI a regisler gets loaded on a particular clock cycle--{)n some cy les we wanl 10 load. whereas on other cycles we j usl wanl 10 keep Ihe previous value. ~
WHY THE NAME "REGISTER"?
Hislorically, the term "regisler" referred 10 a sign or chalkboard 01110 which people could lemporarily wrile OUI cash lransactions. and later perfonn bookkeeping using those tran sactions. The tenn generally refers to n
device for sloring dntn. In Ihis contex!. -inee
3
collection of Hip-flops stores data. the n3.m~ register
seems quile nppropri3le.
152
Oatapath Components
4.2 Reg isters
153
~iagram
in Figure 4.3(a). We can Ihen delermine the values in regislers RO. RI. and R2. as shown in -'gurc 4.3(b). Before the fi rst clock edge. we do not know the values in the registers, so we show the registers ' contents as "????" The Contents are actuaJ ly some combination of four 0 and 1 vaJues but we don't know what those particular values are.
•
a
Before the fi rs l clock edge, we are give n that a 3 .. a become 11 11. Thus. on the first clock edge, RO will be loaded with III I . AI the same momenl, RI and R2 wi ll be loaded with the value in RO, whi ch is " ???? ," so R I and R2 will still have con tents of" ? ?? ? ."
(a) ~
o
Clk_~n11
.& a3 .. aO
11
--l-l-l-l--i.I-X
n n n
~
:2
0001
i
X ! 1010
------------------i---------- --~ ----'-------------
'0
'"
n
:3~---~i 4L---.....,15~---~
-_-_-_~-t,-_-__-_-_-__-_-___ ..,.~_-__-_-_-__-_-_-__-_-_
.t, _-__ _- __ - __ -
!2
.
( ).
Figu re 4.1 4· bil parallel load reg ister: a mtern
al desian (b) palhs when 1oad=O and 10ad =l , 0
Ihe data inputs whe n loa d is 1. " . A reoister w ith a load line that co ntrols whether the register IS loaded With ex t~rnal mputs, . aII t°h ose .Inputs b' Wllh elflg I0 aded in parallel . is know n as a parallel load reglSler. Figure . . . - - - - -- - - - --
Rl
????
R2
????
1010 1010 0101
-
-
--,
: 1010
(b)
i ,~ 0101 :1101011 0101 1 c.;,:""" "'R O,2"-'-'! Rl R2
Figure 4.3 Basic regis ter example: (a) timing diagram. and (b) the contents of each register.
Before clock edge 2. we are give n th at a3 .. aO change to 00 01. Thus, on the second clock edge. RO will be loaded wi th 0001. Simult aneously, RI wil l be loaded with the value of RD. which was 1111, and R2 will be loaded with the value of RO inverted, meaning 0000. Before the third clock edge, we are gi ven that a3.. aO change to 1010. On the third clock edge, RO wi ll be loaded with 1010, while simultaneously RI gets 000 1. and R2 gets Ilia. We are given Ihat a3 .. aO stay at 1010 before the fourth clock edge. On the fourth edge. RO again will be loaded with 1010. while simultaneously RI gets 1010 and R2 gets a 10 I. As a 3 .. a a stay at 1010 before the fifth clock edge. then on the fourth edge. RO again will be loaded with 1010, while R I again gets 1010 and R2 agai n gets a 10 I. The important fea ture 10 notice in this example is that the RO. RI . and R2 registers all ger loaded siml/lralleol/sly. Thus, even though RO gets loaded with a new value on a clock edge. RI and R2 gel the previous value. not the new value. on that same clock edge.
EXAMPLE 4.2 W eight sa mpler
EXAMPLE 4.1 BaSIC example uSing registers Figu re 4.2 show, a simple conneclion of Ihree regislers RO. R I. and R2. Suppose we are laid Ihal Ihe inpul values on a3.. aO have Ihe va lues show n in Ihe liming
????
•
and (e) regi ster bloc k symbol. . ' . . I I d ' g of a reoister by add ing a 2x I rnuluplexor In front .0 . 1 d' . We can ac hieve con tra ove r oa In c h 4 b't reoister In F,oure 4.I(a). Whe n the oa sIgnal IS 0 of each flip-flop as shown ,or t e - I 0 " 0 I h . F' 0els loaded with its own va ue. as sown m Igure .' . I fl' fl ., d and the clock signa l rISes, eac l iP- op" . h fl ' fl . rese nt contents. the register S conte nts a not change . . . h fl ' fl 4 I (b) Because 0 IS t e IP- op s P . '1 d ' 0 Wh en the lo ad sional is I and tile clock s ignal nses, eac [P- op gets when oa IS. 0 . I d d . loaded with one of Ihe data inputs 10. I I , 12, o r I 3- thus, th e regIs ter gets oa e With
4. 1(c) provides a block symbol for a 4bil parallel load register. A block symbol o f a component shows a component's inputs and outputs. wi th out showing the component 's internal details. Because register are suc h a fundamental component in datapaths, we prese nt a number o f examples invo lving reg isters. to ensure the reader gai ns suffi c ient comfo rt with registers.
RO
Figure 4.2 Bn,ic regisler ex ample.
Consider a scale at a grocery store used to weigh fruit. The scale may have a display that shows the presen t weight. We want 10 add a second display. and a bunon that the user an press to remem ber th e present weight (sometimes called "sampli ng"). so that when the fruit is remo,'ed. the remembered we ight continues to be displayed on the second display. A diagmm of the system is sbown in Figure 4.4.
154
4.2 Reg isters
Oatapath Components
We must ensure that when th e timer ge nerates its hourl y pulse on C, the pulse is 1 fo r onl y one clock cyc le. Otherw ise, th e registers would gel loaded marc than once during a single pulse (beca use du ring that pu lse. multipl e rising clock edges wo uld occur. and regi sters get loaded on each rising clock edge). and so the presen t temperature would get loaded into two or even aU three registers. We Can accomp lis h a sin gle-cyc le hi gh outpu t by usin g the Same clock as input to the timer, and then deS ig ning the timer's internal state machine to only sel C"'l for o ne slate-similar 10 how we set an output to 1 For exac tl y three stales in Example 3.7 in Chapter 3.
Assume the sca le outpul ~ th e
prese nt weigh t as n -I.-bit b~llar~ !lumber. and the "Present we ight Jnd "Saved weight" di spl nys ~u(O matically conve rt their inpu~ blllary numbe r to the proper displayed v;J lue. We cu n design th e Weight· Sampfa block using a -lobi! parallel
Weight Sampler
EXAMPLE 4.4
load rce islcr. \Ve co nnect the bu tton signal to the load inplll of the reg-
b
is~er. The OUlplil connects to the "Saved weight"' display. Whenever b is L the weig ht va lue gelS loaded into the register. and thus appears on the second display. When b retunlS to O. the register kee.ps its value. so the second display conti nues 10 show the same weight. eve n if other items
Figure 4.4 Weight sampler imp leme nt ed us ing a 4-bit
are pJaced on the scule and the first
parallel load reg ister.
disp lay cha nges.
EXAMPLE 4.3
T m erature history display using registers (again) . e p . a pulse on an Input C every hour. We 3 . whi.ch a Ilrner gel,eraled ,
• t s and those regis ters we re connected such Recall Example 3.2 of Chapter . 111 I k ' UIS of three reg is er . co nnected that input C to the c oc II1p 'perature the second register would get the . I d d / th the prese nt ten Id the te mperature before that one, o n the rising that the first registe r woul d be oa e ".1 . d h thi rd reo lSler wou ge t d connec t any input o ther than a clock signal previous temperature. an t e o . . . e typIca ll y a not edge of C. However. In pracllce. w . W therefore redes ig n the system LO use a clock . . clock IIlput e can (from an osc illator) 10 a reg ister S . . II 11 ad reoister. We co uld then con nect th e input C signa l as the regi ster clock inpul. by uSlllg a'par~ e a 0 ... . show n III Floure 4.5. 0 I er hour In fact due to the nature of how to the load inputs o f the reg isters. as . f . n be fas ter Ih an I pu se p . , The osc li lator requency ca ? Q rr Osc ill ators· o n page 102 in Chapter 3), osc illators are made (see "How Does It Work . - ua z . oscillalOr frequencies are usua lly at leas t in the k.ilohertz range .
------.....
,----
r.;;.. 14
~
04 03
14 13
12 Rb02 11 01 10 00
clkl~
r~
~13 ~12
~1 1
~IO to
osc~
a4 a3 a2 a1 ao _ _
04 03 02 Ra 01 00
C
~
1
newline
Automobile above-mirror display using parallel-load registers In Chap ter 2, we described an exa mpl e of a sys tem above a rearview mirror that could di play one of fo ur 8- bit in puts, T. A. I, and M. In that example, we ass umed the car's central compu ter was connected 10 the above-mirror sys tem usi ng 32 lines (4*8). Thirty-two wires is a lot of wires to have 10 connect from the computer to above the rearv iew mirro r_ In stead, assume that the computer connects to the above- mirror sys lem usi ng 8 data lin es (C), 2 contro l lines a 1 aD that specify whic h data item prese ntl y appears on C (be ing T when alaO-OO. A when alaO-Ol. J when alaO-lO. and M when a 1 a 0-11), and a load control line load, For a total of II line . ratherthan 32 lines. The Computer can se nd the data items in any orde r. at any lime. The above-mirror system should s impl y SlOre dal a items in Ihe appropri ale regis ler (accord in g to a laO) when the data items anive. and thus lhe sys lem needs four para ll el-load reg isters in whic h to store each data item. The control lines a 1 a 0 wi ll therefore serve as th e "address" thai tell s us which regis ter 10 load. As in the earlier example. inputs xy determine whi ch va lu e to pass thro ugh to the 8-bit d isplay OutpU t 0 (wi th xy sequenced by th e user pressing the mode button). We can des ign the sys tem as show n in Fig ure 4.6. The fi g ure uses a popular "shonhand" notation th at replaces a grou p of wires by a si ng le thicker wire having a s lanted line and number indi ca ting the number of wires in the gro up .
~====n:-l iO
~~rli1
8-bit 4x1
o
c4 c3 c2 c1 cO
b4 b3 b2 b1 b 0 r 14 13
155
04 I03
12 Rc 02 11 01 00 10
r---
-
IT Temperature History Slo,age
Figure 4.5 Internal de,ign of the TempemlllreNislorySlorag" co mpo nen i. using parallel load reg lslers.
Figure 4.6 Above-mirror dis pl ay design. a I a O. set by the car's central computer. delennines whi ch register to load Wilh C. whil e 1 oad-l enables such loading. y . which are !Odependent of a 1 a 0 and are sel by the user pressing the mode button. dctennine \\ hkh register to output to the di splay D. Th e decoder decodes a 1 a 0 to enable exactly one of the four regbten;. The load line en3bl<$ the decoder- if 1 oa d is O. 110 decoder OUlput is I and so no register get. loaded. The multIpk\ 'r pUrl of the sys tem is the sa me as in th e earlic.!f example.
156
Datapath Components Let's
!
4.2 Registers how thi s system work s far a sample sequence of inputs. Suppose init il.l ll y that all reg-
. . , 0 and xy=OO . Thu s. the di splay wi ll show O. Ir the user presses the mode button fo.ur ,Sters store s ' . h I 0 I 1 0 II and back to 00. ror each press still dlS-
times the inputs
xy
wlil seq uence t roug 1
•
•
•
•
la , i~(l 0 (..::ince all registe rs are Os). Now suppose that during some clock cycl e. th~ car s computer po) e ' 1 d-l d C=000010 1 0. Then register 1 wi ll be loaded wnh 0000 1010. sets a 1aO=01. oa - . an . . . Since xy=OO . the di splay will still show the contents or regISter O. and thus th e dISp lay wil l show O. Now. ir thc user presses the mode button. xy wi ll become OL and the dis play 11' 111 show the decimal value of ree.i ster I 's 0000 1 010 value. which IS len III deCima l., Pr~sslOg mod e ~gal~ WI)) clWI1e.c xy to 10. s~ the display will show the co nt en ts of register whIch I ~ O. At any tlme ,ln the fUlUr;. the car's compu ter can load the other reg isters. or reload regl s ~er I . with new val,ues. In any order. Note th at the i03ding of the reg isters is independent from the display of those reglsters.
2:
EXAMPLE 4.5
Computerized checkerboard Checkers (known in some countries as "draughts") is ont! of the world's most popular board gam~. A checkerboard consists of 64 squares. formed from 8 colum ns and 8 rows. Each player starts ~Ith 12 chec kers (pieces) on the board. A co mputerized checke rboard may replace the checkers by uSing an LED ( liglll~el1l illing diode) in each square. An on LED represent ~ a checker 111 a square;.an o~ LED represen ts no checker. For simplicity of the example. ignore the Issue of each player havmg hIS
observer would probably see all th e LEDs change at the same time. not noti cing that some LEDs are changIng rm croseconds earlier th an others. Let 's use one register per column. meaning we' lI need eight 8~bil registers tOla!. as shown below the checkerboard in Figure 4.7(a), with those registers named R7 th rough RO. Each register'S 8 bits of ~ata corres~ollds to a particular row in the register's column. ind icating whether (he respecti ve LED IS.on or off , as shown in Figure 4.7(b). The eight regi sters are connected to the microprocessor. The mi croprocessor uses eight pins (D) for data, three pins (i 2, i 1. i 0) for addre sing the appropriate register (whi ch is decoded into a load line fo r each of the 8 regi sters). and one pin (e) for the register load line (linplemented using th e decoder's enable), ror a total or 12 pins-a num ber much more feasible than 64 pins. To config ure the checkerboard ror the begin ning of a game. the mi croprocessor would crea te the following sequence of register wri tes shown in Figure 4.8.
own color of checkers. An example board is shown in Figure 4.7(a).
clk O LEO
e
lit LEO Figure 4.8 Timing diagram indicating an input sequence that can be used to initia1ize.
~ HOW DOES IT WORK? COMPUTERIZED BOARD GAMES,
Figure 4.7 An electronic checkerboard: (a) e ight 8· bit regi !>lers (R7 through RO) can be used to dri ve [he 64 LEDs. using one reg j ~ ter per column. and (b) detail or how one regi ster connects to a column', LEDs and how the va lue 10100010 stored in that register would li gh t th ree LEDs.
from
from
microprocessor decoder (b)
(a)
A computerized chcckerboard typically has a mi croprocessor that keep' trac k or where each pi ece is located. moves pieces according 10 user cOlTImnnds or accordin g to a checker-playing program (whcn playing against the computer), keeps score, etc.
157
Notice that the microprocessor must set va lues for 64 bits one bit for each square However th~. inexpensive type of microprocessor used in such a device p~obably does not have ~ pins. Th~ IllICroprocessor needs ex ternal registers to store th ose bits that drive the LEDs. and will write to those registers One at a time. The microprocessor writes to the registers so fast.. though. that an
Many of you have played a computeri zed board game, like checkers, backgammon, or chess. either using boards with small di splays to rep resent pieces, or perhaps usi ng a graphics program on a personal computer or website. The main method the computer uses fo r choosing among possible nex t moves is called lookahead. For the cu rrent configuratio n of pieces on the board, the computer considers all possible single moves that it might make. For each such move. it might also consider all possible single moves by the opponen t. For each new confi gurati on res ulting fro m possible moves, the computer evaluates the configuration's goodness, or quality, and picks a move that may lead to the best configuration. Each move that the computer looks ahead (one computer move. onc opponent move, another computer move, another opponent move) is called the lookallead amount. Good programs might lookahead three, four, five moves, or more. Looking ahead is costly in terms of compu te time and memory-ir each player has 10 possible moves per tum. then looking ahead two moves results in 10' 10 = 100 config urations to evaluate: three moves in 10' 10' 10= 1000 configurations. fo ur moves in 10,000 confi gurations, and so on. Good game-
playing programs will "prune"' configurations that appear to be very bad and thus unlikely to be chosen by an opponent, just as humans do. [a reduce the configurati ons to be considered. Compute~ can examine millions of configurations. whereas humans can onJy mentally examine perhaps a few dozen. Chess. being perhaps the most complex or popular board games, has attracted ex tensive attention since the early days of computing. Alan Turing. considered one of the fathers of Computer Science, wrote much abou t using computers for chess. and is credited as having written the first compu ter chess program in 1950. Howe\'er. humans proved better than compu ter chess programs until 1997. when IBM's Deep Blue computer defeated the reigning world champion in a classic chess match. Deep Blue had 30 lllM RS-6000 SP processors connected to -I Ospecial purpose chess chips. and could evaluate 200 million moves per second, and hence many billi ns of m \'eS in [) few minutes. Today. chess toumamenlS nOt only mat h humans against compu ter prognun~. but also progT':l.l1lS against programs, many hosted b. the lnrern:ltionaJ Computer Games Association. (SoufC'e: Ct)mpllt~r Chess Hislf'I)', b~ 8 dt WaH),
158
Datapath Components
4.2 Registers
On (he first rising clock edge. RO .g~ls loade~
O lED
.
with 1010001 D. On the second nSJllg clock cdoc. R I gets loaded with 01000101. And so
159
Rotate Register
litlED
A rotate register is a Slight vari ation of a shift register in which the ou tgoing bit gelS shi fted back in as the incoming bit. So on a right rotate, the rightmost bit gets shifted into the leftmost bit, as seen in Figure 4. 12.
on- Arter eight cloc k cycles. the reg isters would the desired values. and the board's LEDs would be lit. as shown in Figure 4.9.
co~tain
1
~
Shift Register One thing we might want to do wi th a register is shift the register's con ten ts to the left or to the right. Sh ifting to tile right means to move each stored bit one nip-nap to the right. If a 4-bit register originally stores 11 01. shifting right wou ld resu lt 1tl 0110, as shown in Fi gure 4. 10(a). We dropped the rightmost bit (in this case a 1), and we shifted a 0 into the left most bit. To bui ld a
0 1
Register contents before shih right
1 1 1 0
Register contents after shift right (a)
(b)
Figure 4.12 Right rotate example: (a) register contents before and after the rotate. and (b) bit-by-bit view of the ro tate opcral ion.
Implementing a rotate register is achieved by modifying the design of Figure 4.11. feeding the rightmost nip-nop output , rather than the 5 h r _ i n input. into the leftmost mux's i 1 input. A rotate register needs Some way to get va lues into the register--either via a shift, or via parallel load.
regi ster capable of shi ftin g to the rig~l . \~e
conceptually need to connect the regtster s Aip-Aops in the manner similar to that shown in Figure 4. 10(b).
~
o Figure 4.10 Right shift example: (a) sa mpl e
c onteOlS
before and
after a nght shift and (b) btl-by-btl view of the shi ft.
1 1 0 1
Reglslercontents before shllt nght
o1
Register contents after shift fight
1 0
EXAMPLE 4.6 Figure 4.9 Checkerboard after load ing registers for init ial checker positions.
shr_~ (b)
Above-mirror display using shift registers In Example 4.4. we redesigned the connec ti on between a
This bundle
car's centra l computer and an above-mirror display system to reduce th e num ber of wires fro m 32 down lO 8+2+ 1= II .
should be
However. even II wi res is a JOI of wi res to have to run fro m the comput er to above the mirror. Let 's reduce the wires even further by using shi ft regis ters in [he abovemirror system. The in puts to the above- mirror system from the car's com puter wi ll be one data bit C. two address lines
f eU' wires. lIot ele\lefl
wires.
a 1 a D. and a shift line S h i ft. for a total of only 4 wires.
(a)
When the computer wants
W o' t able to shi ft to the right as shown in Figure 4. 11. The register . h ~1 s a ri ght shift on a rising e can create a re"ts cr includes two control mputs, S h rand 5 h r _ , n. 5 r cause . . clock cdoe whi le s hr~O causes the register to maintain its present value. 5 h r _, n tS the bit that :e'want to shift into the leftmost register bit during a shift operation.
[0
wri te
to Oll e
of th e abovc-Illjrror system's regis ters. the computer will
set a 1 a 0 appropriately and will then set 5 h i f
t to 1 for exactly eight clock cycles.
For cHe h of th ose eight clock cycles. (he computer wi ll se t c to one bit of the -bit dara to be loaded. starti ng wi th the least-signifi-
cant bit on the firs t clock cycle. and
Note: this tine is 1 bit, rather than 8 bits like before
ending w ith the Illost-significant bit on th e eighth cloc k cycle. We can thus design the above-mirror sys tem as shown in Figure 4.13.
x 51
2x4
iO 8
4",
dl aO -... iO
Figure 4.13 Above-mirror display design using shift
Figure 4.11 Shirt regi' ter: (a) implementation. (b) path' when Sh r~ 1. and (e) block symbol.
I>
03 I
02
01 I (c )
00 I
reg ister being londed with th e sent 8-bit value.
il 8
al -... il
d
d2
regi sters to reduce the number of li nes coming from the
car's computer. The compu ter sets a 1 a 0 to the desired register to load. and then holds S h i ft ~ 1 for eight clock cycles, with C equaling the register conten ts bitby-bi t, one bit per clock cycle. resu lting in the desired
y
t sOt
i2 8 shi~
e d3 •
i3 8
8
D
160
4 Datapath Components
4.2 Registers
~ HOW DOES IT WORK? COMPUTER COMMUNICATIONS IN AN
~ HOW DOES IT WORK? WIRELESS AND USB COMMUNICATION BETWEEN DIGITAL DEVICES.
AUTOMOBILE USING SERIAL DATA TRANSFER. Modem automobiles contai n dozens of computers distributed throughout the car-some under the hood, some in the dash, some above the mirror. some In .the door. some in the trunk. etc. Running wires thro ughout the car 50 those computers c~ n communicate is a challenge. Thus. most aUlOma,blle comp uters communicate seriall y. meaning one bit at
a time , like the co mmu ~ i cali o n in ~x ampl e 4.6, to reduce the number of wires. A ~artl c ularl y ~opul~r seria l communication scheme I n automobil es IS
Serial communi cation between di gital device. such as between personal computers. laplops. printers. cameras, elc., is ubiquitous. The popular US B in terface is a seria l communication scheme (USB is short for U"i.'ersal Serial Bus) lIsed to connect personal computer and other devices together by wire. Furthermore. nearl y all wireless cOlllmunication schemes, such as WiFi and 8 1ucTaolh. use serial
known as the "CAN bus." short for Controller Area Network. which is now 3n mte~nalion a l standard defi ned by ISO (International Standards Organization) standa rd number I 1898.
. ria te reo ister gels a new value shifted in durin g the next eig~1 When Shl ft-l. the approp 0 arallelload from eight separate inputs. but uti'
lizes fewe r wi res. This example
~
de~onstrate~ a .0
Multifunction Registers
.
~
communical ion. sending one bit 31 a lime over a radio frequency. While data communication between devices may be serial. compulations inside devices are typically done in parallel. Thus. shift registers are commonly used inside circuils ( 0 convert internal parallel dal a into seri al data to be senl 10 another device, Jnd to receive seria l data and convert that data into parallel da ta for inlcrn al device use.
Let 's exa mine the mux and flip-fl op of the rightmost bi t. When 5 I s0:00 . the mux passes the present fl ip-flop value back to the flip-fl op, causing the flip-fl op to get reloaded with its present value on the next rising clock, thus mai ntaining the present value. When 51 S 0:0 I , the mux passes the ex ternal 10 input to the flip-fl op, causing the flip-flop to get loaded. When 51 S 0: 10, the mux passes the present value of the flip-fl op output from the left, Q I, thus causing a right shift. s i s 0: 11 is not a legal input to the register and thus sho uld never occur; the mux passes Os in this case.
clock cycles. This method achieves the sa me as a p
communication. in wh ich the
161
nn of comm unication between di gital circuits known as serial . ale data by se nding the data o ne bit at a lime.
Circ Ui ts comm unl C
. ' " nn a variety of operations (also call edjimcll olls), li ke load, shtft ngh~
Many registers can pe 0 ft Th egister user selects the presentl y demed operatIon . . . h 'f I ft t t rioht rotate Ie etc. e r J t e . ro a e o , _ .' , now introduce some multifu nctI on regIsters. by setting the register's control mputs. We II
Register with Parallel Load, Shift Left, and Shift Right
S
Adding a shift left operati on to the above 4-bit register is straig htforward. and is hown in Figure 4. 16. Instead of connecting Os to the 13 in put of each 4x I mux. we instead connect the output from the flip- fl op to the right. The ri ghtmost mux's 13 input wou ld be connected to an addi ti onal input 5 h 1_ in.
Re 'ster with Parallel Load and Shift Right . gJ .' . is that of both parallel load and shIft. We can A popular combmauon of operatIOns on a reoister 0 " . . design a 4-bll. regIster capable 0 f para II. e I load and shift right, the. details of whIc h are shown 10 Figure 4.14(a). Figure 4.14(b) shows a block symbol of the regIster.
13
t2
t1
to
flTrr-nTrt--~*~~-d~Lls~hun
to
shUn shr_in 51 sO
(b) (a) (a)
Figure 4.14 4-bil register with parallel load and shift right operations: (a) internal design. and (b) block symbol. Notice that we used a 4x I mux, rather than a 2x I mux , in front of each flip-fl op, because each flip-fl op can now receive its next bit from one of three locations (the fourth mux input is unu ed). The register has two control inputs, with the control behavior shown in Figure 4. 15.
.1 0 0
.0 0
t 0
Operation Maintain present value Parallel load Shi~ right (unused - let's load Os)
Figur. 4.15 Operation lable of a 4-bil register wi lh parallel load and shift right operalion\.
(b)
Figure 4.16 4-bi l regisler wilh parallel load. shift lefl. and shin righl operations: (a) internal design. (b) block symbol. ~
UNUSED INPUTS,
The example in Figure 4. 14 included 3 mux wi th 4 inputs of which we onl y used 3 inpuis. Notice that we aClually sel the unused input to a particular value. rather th an simply leaving the input unconneclcd. Remem ber that the input is controlling lransistors inside the component- if we don't <.15sign n value to the inpul. will
the internal [fUn istors conduc t or nOI conduct? \Vc:: don't rea lly know. and so \\ e C' uld get undesired beh:l\ iar from the mIL'. Leaving inputs unconnected should not be done. On Ihe other hand. lea\'ing outputs unconnected is no problem-an unconnccted output ma~ ha\ e a 1 or n thai simply doesn't control anything clse.
162
4 Datapath Components
4.2 Registers
The register has the operat ions shown in Figure 4. 17.
sl
sO
Operation
0
0
Maintain present value
1 0 1
0 Parallel load Load/Shirt Register with Separate Control 1 Shift right Inputs for Each Opera tion 1 Shift left Reg isters Iypica ll y don' l come wilh conlrol inpulS Ihal encode Ihe operation inlO the Figure 4.17 Operation table of a 4-bit minimum number of bils li ke the conlrol register with para llel load. shirt left, and shin ri ght o penllions. inpulS on Ihe regislers we designed above. Inslead. each operalion usually has ils own cOlll rol inpul. So a registe r wilh Ihe operati ons of load, shi fl lefl. shr shl Operation and shift righl. mighl have Ihe Id inpulS and operation lable o o o Maintain present value shown in Figure 4. 18. The Shift left o o fo ur poss ible operations o Shift right o Shift right - shr has priority Over shl 1 (mainlain , shilt left, shifl right o 1 o o Parallel load and load) really onl y req uire Parallel load - Id has priority o 1 two control inputs, but the o Parallel load - Id has priority fig ure shows that the register Parallel load - Id has priority has three control inputs-l d, shr, and shl. Figure 4.18 Operat ion table or
t>
I
describing ope rat ions of a
along wit h the ma ppi ng of the register control inputs to th e inlcmal 4x I mu x
select lines: (a) complete operat ion ta ble defi ning the mapping or 1d, s hr . and shl to sl and sO.
L combinational circuit
shein
j-- sl
r - sO
t>
13 12 11
Note Operation
Maintain value
Shift left Shift right Shift right Parallel load Parallel load Parallel load Parallel load
--
~
f1
Id
shr shl
Operation
0 0 0 1
0 0 1
Maintain vaJue
X
0 1
Shift left Shift right Parallel load
X X (b)
We can design that combinational circuit starti no from a simple truth table shown in Fig ure 4.20(a). 0 We th us obtain the fOll Owing eq uations for the regi ster's combinational circuit: sl = ld'*shr ' *shl + ld ' *shr*shl ' + ld'*shr*shl sO = ld'*shr'*shl + ld Replacing the combinati onal circuit box in Figu re 4. 19 by the gates described by the above equati ons would complete the register's design. . Register dalas heets typica lly show the register operation table in a compact form. takll1g advantage of the priorilies among Ihe control inputs. as shown in Figure 4.20(b). A sll1gle X 111 a row means that row is actually two rows in the complete table. with one row hav ll1g 0 111 Ihe position of the X, the other row having I. Two Xs in a row means that row IS actually four rows in the complete table. one row havi ng 00 in the positions of those Xs, anot her row having 01. anO,ther 10. and another 11. And so on for three Xs. representll1g 8 rows. Note lhat pUlling hi gher priority contro l inputs to the left in the table keeps the table' opera lions nicely organi zed.
Register Design Process Table 4. 1 describes a general process for designing a register with any number of functions. TABLE 4.1 Four·step process for designing a multifunction register.
Step Determine
Descri ption Count the number of operations (don't forget the maintain present vaJue
operation!) and add in rront of each flip-Rop a mux "ith at least that number of in puts.
2. shl in
030201 00
I I I I Figure 4.19 A small combi national circui t maps the control inputs 1 d. shr. and shl to the mux ,elect inputs S1 and sO.
Create mllx operaTion fable
3.
03 /0 2 /01 /00 /
163
(a)
mllX size
10
shUn
Outputs s hl s l sO 0 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1
and (b) a co mpact ve rsion of th e opcn:llion tab Je.
I.
I
Inputs Id shr 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
register with lert/right shirt and parallel load
'3 / '2 / '1 /10 /
shr in
-~ -~ - ~
I
Figure 4.20 Truth tables
4.
COl/fleet mll.X
Crc:uc an operation tab le defi ning the desired ope ralion for each possible va lue of the 1ll1lX selec t lines.
For each operation. connect the corresponding
I1lUX
data. input to Lhe
inplllS
appropriate external input or flip-fl op OUlput (possibl~ pa..-.sing through some logic) to achicve the desired operat ion.
Map cOllfrol lili es
Create a lnllh table that Illaps ex ternal control lines to the internal mu, select lines. with appropriate priori Lies. and then design the logi to ach ieve lhnl mapping
We' ll illustrate the regi ster design process \ it h ano ther example.
164
4 Datapath Components
EXAMPLE 4.7
4.3 Adders
Register with load, shift. and synchronous clear and set . . . . following operations: load. shift lelt. synchronous clear, and We want 10 design a register with the r h on<>ration (1d. 5 h 1. c 1 r. set). The s)'l/chro-
Loo ki ng at each output in Figure 4.23. we deri ve the cqu3Iions desc rib ing the circuit that maps the external comrol in puts to the 1l11IX select li nes as follows: ~ c1r ' *set 51 c1r " set ' *ld "'sh1 + c1r sO ~ c1r ' *set ' *ld + c1r
52
.h . co ntrollOpUIS lor enc .. synchronous SCI. wit uniq ue . I d all Os into the register on the nex t rising clock nOlls clear opermion on :1 reglSle~ means to °1~ a~ nil 15 in to th e register on the nex t rising clock Th I s set opernuon means to edge. e S) 'IIC tTOIl Oll .' cd because some registers co me wilh asy" chronous clear or edge. The lerm synchronous IS Includ h 'gister design method of Table 4. 1. we perform the folasynchronous set operations. FollowIOg I e rc
We could then cre3(e a cOlllbin:ll iona l circuit implementi ng th ose equations, to map the ex ternal register control inpu ts to the mux selec t li nes. and hence. complcling thc register's design.
lowing sleps:
. . , . . There arc 5 operati ons- load, shift ,left : synchronous clear. sy~chroStcll l. Determlilc mux Size D ',rorget the mmntaIn present va lue operat ion as Ilaus se t, and ma intain preselll I'a/ll e. on , th at opcnl1ion is implicit.
Step 2: Create mux operation table. We' ll use the fi rst 5 inputs of an 8x I mux for the
s2
desired 5 operations. For the re m ~m l~g 3 mux in puts. wc' lI choose to mmnlam
o
o o
Ihe present value. though those mux in puts should never be utili zed. The
,able is shown in Figure 4.21.
s1
sO
Maintain present value
o
Parallel load Shih leh Synchronous clear Synchronous set
1
o 1
1
o
Maintain present value Maintain present value Maintain present value
o
Figure 4.21 Operation lable for a register wit h load, shift, and sync hro nous clear and set.
In
Step 3: Connect mux inputs" We connect Ihe
.......Hrl~0f--~~;===;~Irom On-l
mu x in puts as shown in Fi gure 4.22.
which for simplicily shows onl y the Illh nip-nop and mux of the register.
D
Figure 4.22 Nth bit-slice of a register with the following operations: maintain present value. parallel load. shirt lefl. synchronous clear. and synchronous sel.
o
the register contro l inputs would be mapped to the 8x J mu x select hnes as shown
In
Figure 4. 23.
elr Figure 4.23 Truth table fo r the control lines of a register with the Nth bit-slice shown in Figure 4.22.
0 0 0 0
0 0 0 X
0 0 X X
shl 0
1 X X X
4.3 ADDERS Adding two bi nary numbers is perhaps the most co mmon operation perfonned on da ta in a dig ital system. An N-hil adder is a d:ltapa th co mpo nent Ihat adds two N-bi t binary num bers A and B, and generates an N-bit sum S and a I-bit carry C. For instance, a 4-bit adde r adds two 4-bilnu mbers. like DIll and 0001 , result ing in a 4-bit sum . li ke 1000 . with a carry of O. 1111 + 0001 wo uld resull in a carry of I and a sum of 0000 (or 10000 if yo u treat the carry bil and sum bits as o ne 5-bit result). N is often referred to as the \Vidlil of the adder. Designing fasl ye t size-effi cient adders is a subject that has received considera ble attent ion for many decades. Altho ugh it ap pears that we could des ign an N-bil adde r by fo ll ow ing the com bi nati o nal logic des ig n process of Table 2.5 , it IUrn s o ut th ai buildin g an N-bit adder fo ll owing that process is not very pracli ca l when N is much large r than 4. A 4- bit adder has IWO 4-b it input s. meaning eighl inputs to tal, and has fo ur sum outputs and a carry oUlpUt. So we could des ig n the adde r using Ihe standard com binalional logic des ig n process of Table 2.5. For exampl e, a 2-bit adde r, which adds two 2-bit nu mbers, could be desig ned by starting with the truth table de picted in Figure 4.24. We could then impl ement Ihe logic using a two-leve l logic gale based implementation for each o utput.
On
Step ~ : Map control lines. We' ll give c 1 r highest priority, followed by set' .l d. and Sh 1, ~o
Inputs set Id
Some reg isters co me with asynchronous clear and/o r asynchronous set control inputs. Those inpulS could be implemented by connecting them to asynchronous clear or asy nchronous set inputs thm ex ist on the ni p-nops themselves.
Operation
o o
o o
Output. s2 .1 sO 0 0 0 1
0
0 1
0 0
0 0 1
0
165
Operation Maintain present value Shih leh Parallel load Set to all i S Clear 10 all Os
.1 0 0 0 0 0 0 0 0
Inputs aO b1 0 0 0 0
0 0
bO
e
0
0 0 0 0 0 0 0
1
0 1
1
0 0
0 1
0
Outputs s1 sO 0 0
0 1
0 1
0
1 0
1
1
0
0
Figure 4.24 Trulh table for a 2-bil adder.
.1 1
Inputs aO b1 0 0 0 0
bO
e
0 0
0
0 0
1
0
1
1
1
0 0
0 1
0
0
Outputs s1 sO 1
0
1
1
0 0
0
1
1
0 0
0
0
----------------------------~~~~
166
Datapath Components
4.3 Adders
. hat for wider adders. the approac h res ul ts in The problem with such an approach" t , 6 b' . dd >r has 16 + 16 = 32 inputs ' bl ' d too m~ln y gate,. A I - II a c , I I' h too "rge 0 Iru t t,1 e' ,In .// . 's A two- level logic gate based . , bl ' Id h'IVe over jOllr bl rO/l IVII . mealllng the trulh t.l e wou , . "II ' of oates To ill ustrate this . I> > , " I' h' ' bl> would likely req UIre ml Ion 0 . IInp ement,lIl on a t ,II ta e. . . 'h we used Ihe standard combinational logic tn whlc . ' h I b' dd 'u Point ' we performed an expcnm~nl .. .' width stantng Wit - II a ers on up. ",e de'ign proce" 10 create adder> 01 Increasing i n 'tool avai lable. and asked the tool to used the most advanced commercial logiC des g r d" OR . . ( I ve l of AND gates lee tng tnlO an gatt create a design u. ing two leve ls of logiC one e II ') . . for each out pu t) and using the minimum num ber of gates (actua y. trans istors .
+ 0
Figur. 426 Adding
The plot in Figure 4.25 summari ze:,
OUf
results. Not ice how
*
Adder-Carry-Ripple Style An alternative approach to the standard combinational logic design process for adding two binary numbers i to instead create a circuit that mim ics how we add binary numbers by hand. which is one column at a time. Consider the addition of a binary num ber A-IlIl ( 15 in base 10) and 8-0110 (6 in base 10), colu mn by column, shown in Fi gure 4.26.
o
+ 0
bln"ry numbe"
o
t
t
o
0 1
I 0
I
For each column, we odd Ihree bit, togelher, "lid we ge nerate II SlIllI bit ror the pre~ent column and a carry bi t fnr the ne" co lllllln. The firs l COIUIlIII is all exception in that we onl y ad I two bi t, t ge lher, hUI ,till gc ncr:tt ~ a MIIIl IIlId tt cu rry bit. The carry or the last column become, the lifth bit or the ' lim. The MIIIl i, 101 0 I (2 I in base 10). We can create a c mhinat ional compollenl to perrOrlll the requ ired add ilion 1'01' a sing le column . The input' and ou tpuh of ' "ch colllpOllent s arc , ltow il in Figure 4.27. Thus, all we need to do i, de, ign tho,c cOlllpOllentS tha i perrorm Ihe addi lion in each co lumn. and connect them together u, shown ill Figure 4.27 to create" 4- bi l adder. Bear in mind, though. that this llIethod or creating lin adder ;' illtended to enuble eflicient design of wider adder,. like those with 8 hil ' and above. We arc ill uslruting Ihe metllOd u. ing on ly n 4-bi t adder becm,," that ,ile adder keeps our figures sma ll and readable, but if al l we rca lly needed wa' a 4-bi l adder, Ihe , tandurd combinaliollal log ic design process for two-Icvel log ic wou ld probably work jUM line.
1 ~-----------------------'
fast the nu mber of transi. tors 8000~------------------~~ grows as the adder width i, 1? increased. Th is fast growth is an 6000 'in effect of exponential growth- for c 4000~----------------~~~ ,::'" an adder wi dth of N. the number of 2000~--------------~~" truth table rows i, proportiona l 10 2N (more preci,ely, 10 2"'·,v). 5 3 2 7 Clearly, Ihi s exponential growth N prohibits uS from w,ing the stanFigure 4.25 Why large adders aren't built using dard design proces, for adders !"wndard two-level combinati ona l logic-nOlice the wider than perhaps 8 to 10 bits. We exponential grow th. How many transistors would a could nOI complete our experi32-bil adder require? ments for adders larger than 8 bi ts-the 1001 simply could nOI . . complete the design in a reasonab le amount of ti me. The too l needed 3 seconds 10 build the 6-bll adder,40. sewnds to bUIld the 7-bi t adder, and 30 minu tes for the S-bit adder. The 9-bl t adder dldn t fi nt sh after one full day. Looking at this data. can you predict the number of transistors requlfed b~ a 16bi t adder or a 32-bi t adder u ing two-levels of gates? From the fig ure, II looks hke the nu mbe r of transistors is doubling for each increase in N, with about 1000 transistors for N=5 . 2000 t.ransistors fo r N=6. 4000 transistorS for N=7. and 8000 transistors for N=8. Assuming that trend continues for larger adders, then a 16-bit adder would have S more do ublings beyond the S-bi t adder. meaning multiplying the Size of the S-bll adder by 28=256. So a 16-bit adder would require 8000 • 256 = about two mi liton transistors. A 32-bit adder wou ld require an additi onal 2 16=64K doublings, meaning 2 mi ll ion • 64K = over 100 bi/lio/l transistors. That's an outrageous number of transistors. We clearly need another approach for designing larger adders.
1\' 0
by column .
b) h;md. colum n
167
0 -------, A:
+ Figure 4.27
B:
o
0
sing
combinat ional components
to add Iwo binary numbers
colu mn by colum n.
SUM
We' ll now design the components in each column of Figure 4.27. Half-Adder A half-adder is a combinalional component that adds two bits (a and b), and generales a sum (5) and carry out (c o) bit. ( ote that we did flot ay that a half-adder adds /lVO 2-bit /Ill/fi bers-a half-adde r merely adds tlVO bits.) The componenl on the ri ght in Figure 4.27 that adds the rightmo t column 's two bits (a and b) and generates the sum (5) and carry-out (CO) bit is a half adder. We can design a haJJ-adder using the straightforward combinational logic design process from Chapter 2, as fo llows:
Inputs b
Outputs
co
0
0
0
0
1
0 0
0
0 1
0
Figure 4.28 Truth table for a half-adder.
168
Dalapalh ComponenlS
4 J Addors
'tep I: CoptU" /" ~ Juncllon. We ' ll use a nppropnnle lrul h lable" hO" n In Figure 4.2
lrulh table 10 caplure lhe funclion. '!be
and rhal
Slep 2: Convert 10 ~q/lations. We can clearly see lhal db' Ole Ihallhe equullon S - d' b + ab' i lhe arne as Slep J: Creole I" ~ circuil. The cIrcUli for ,I half-adder, Implemenl'"g Ihe above equulloo;. I' ,h()wn III Figure 4 29(a), Fi gure
a
S
-
a' b •
Half·adder (HA)
co
Full-Adder
5
Jull-adder " " cmnb,",lIona l compoco (I ) nenl Ih"1 Jdd' Ihree hll\ (d, b, and cO (b) and ge nerale, J 'um (s ) ,,"d a carry-oul figure 4211 Half-adder' (.) cireuil. and (co ) bll. ( ole Ihar we did flol ~uy Ihal a (b) block symbol. full -adder add, 111'0 J-bll fI"mben- 1I llIerely .,dd, bllf. ) The three component in Figure 4.27 thaI add the Iwo bilS of a column (a and b) along Wllh Ihe carry from Ihe column on the righl (ci) and generates the SUIll (s ) and carry oul (co ) bll_ are full -adders, We can de ign a full-adder usi ng !be ' 1r:lI ghlforw" ru comblllallonal logIC de,ign proccs . as follows :
,"r",
Step I: Capillre t"e Jl/llction. We'll usc a ItUth lable 10 caplure Ihe fun cllon, , hown In Figure 4.30,
co - a 'b c + ab'c + abc' + abc co - a ' bc + abc + ab'c + abc + abc' + abc co - (a'+a)bc + (b ' +b)ac + (c '+c)ab - a'b ' c + a ' bc ' + ab ' c' + abc - a'(b'c + bc ' ) + a(b ' c ' + bc ) - a ' (b xor c) ' + alb xo r c) , t
thr drt'u;t. The CIrcUlI f{lr ~ lull',ld
a a
\ddrr
L"lOg Ihrec lull'Jd(k" ,Uld one halt -add r, "e an dC'I~n a 4-bll carT)-npple adder, "h,ch add, I"" -I bll numbe" ,lOd gener.He, " J bll urn. ,ho"n 111 h j!urc .j L The 4-hll CdrT) npple Jdder ,10,0 generale' J l'drT) oul bll aJb3
co
b
112b2
co
(I )
Figure 4 31 I uti Jddrr (,lllIreu'l. II"d (b) hlock 'YlIlh,,1.
., bl
J
03020 100
4·bll ddor
Outpula
b 0
01
co
I
a
a
a
1
a a a
0
a
url') -Rippl
a
co
Inpula
0 1
1
a a
a 1
a
1
169
r~OJ
J:
-I- Oil
b
tep Z: Co m'.rl/o equations. We oblain the followi ng equali on, for co and S, For ; impli ilY, ler's wri le Ci as c, We'lI u,c algebmic method, 10 implify rhe equations,
t~p
co
53
. 1
s3s2s 150
- II
aO
(a)
(b)
fIgure 4 J2 4·bll adder, ( ) arry "pplc ImplCIllCnlnllOn Wllh 3 fuli -adde" und I 111M-udder, und (bl blocl tmbol
0
a
1
0 0
Figure 430 Trurh lable for a full-.dder,
We can Include a carry-In hll WIth Ihe 4-blt lIdder, which cnllble; u ~ to connCCl 4-bil adder\ logether 10 build larger adde". We Include the cllrry-in bil by replacing Ihe halfadder (whIch WOL\ In Ihe rightm \1 bil po\lllonj by a fu ll-adder. a ~ , hown in Figure 4,33, a3b3
a2b2
81 bl
• ,
During algebmic simplification. for co, we nOled Ihat each of rhe first three terms could be combi ned wilh Ihe In I term abc. as each of the first three lerms differed from rhe last lem1 in jusl one lileral. We thus re3led three instances of rhe last' term a bc (which doesn 't change the funclion ) and combined rhem with each of rhe first three lerms. DoO'I worry if you aren'l able 10 come up wirh thaI simplification on your own righl nowSeclion 6,2 introduces merhocls to make such simpli fication more straightforward. If you have read rhn! seclion , you mighl try usi ng a K-map (introduced in that secLion) to simplify the equalions,
co
53
s2
51 (a)
sO (b)
figure 4.33 4-bi l adder: fa) carry-ripple implemenlalion with 4 full-addc". wilh a carry-in inpul, and (bj block symbol.
170
Datapath Compone nts
Keep wa iting. After a third full-adder delay. the new va lue of co2 wi ll have propagated through the nex t full -adder, resultin g in 52 becomi ng 1+0+1 - 0. with c o2 becoming 1. So a fter three fu ll-adder de lays, the output will be 00000. as hown in Figure 4.34(c). Just a htl le more patience. After a founh full-adder delay. co2 has had time to propagate th rough the last full-adder. resulting in 53 becoming 0+0+1-1, wi th c03 staying O. Thus, after four full-adder del ays. the o utput w ill be 01000. as hown in Figure 4 .34(d), and 01000 is the correct re ult. To recap. until the carry bits have had time to rippl e thro ug h a ll the adders. from ri g ht to left. the ou tput was not COrrect. The intermedi ate o utput va lues are known as spurious values . The delay o f the 4-bit adder, meanin g the time we must wait until the Output IS the stab le correc t va lue, is equal to tile delay o f fou r full-adder. or 8 ns in thi s case. wh ich is the time fo r the can'y bits to ripple throu g h a ll the adders-hence, the term
0111+0001
c030
Output after 2 ns (1 FA delay)
Os3
The Ie I'm "ripple< carry" adder is
carry-ripple adder.
(IClltol/Ylllore COII/IIIOIl. I prefer Ille term "corn-
Students often inti all y confuse full-adders and N-bi t adders. A full-adder ad ds 3 bilS. In contras t. a 3 -bit adder adds two 3-bit numbers. A full -adder produces o ne sum bit and one carry bit. In contrast, a 3-bit adder produces three sum bilS and o ne carry bit. A fulJ adde r is usually used to add o nl y olle colf/1I111 of two binary numbers. wherea an N- bit adder is used to add two N-bit numbers.
ripple" for
.
cOllsistent I/alll illg
lIIith OIlier adder
o
17 J
4.3 Adders
. .' r Su ose that all inpu ts have been Os for a long Let's ana lyze the behavIOr 01 thi s adde. POP d ' II c i va lues of the full adders will '11 b 0000 co wtl l be . an d S time. meaning that WI e . 11 d 8 becomes 000] at the sa me time (whose also be O. oW suppose that A becomes 0] an f A and 8 will propaoate throuoh the Th ,ew values a , " " sum we know sho ul d be ] 000) . ose I . ? S So 2 ns after A and 8 change, the sum full-adde rs. Suppose the de lay of a full -adder IS - n .. F' re 4 34('1) So 53 will become '11 h 0 as shown In Ig u . ,. outputs o f the full-adders WI c. an"e. +0+0= ] (with c02=0), 5] will become 0+0+0=0 (with c 03=0). 52 w tll become ]1 ]-0 ( 'th coO=] ) But 1111 + OllO . 1-0) d sO will beco me + WI ., 1+0+0=] (with co - . an 01000 What we nt wrong ?> sho uld not be DOll O-inste:ld. the sum should be .
Output after 4 ns (2 FA delays)
0
types. like carrysdeCi (lIId carrylookailea{/, which we describe in Chaprer 6.
An N-bit adder often comes wi th a carry-in bit. so that the adder can be cascaded w ith other N-bit adders to form larger adders. Figure 4.35(a) haws an 8-bit adder built from two 4-bit adders. We would set tWe carry-in bit (ci) o n lhe ri ght to 0 when adding two 8-bit numbers. Figure 4.35(b) shows a block ymbo l of that 8-bi t adder. a7a6a5a4
b7b6b5b4
a3a2al aO
b3b2bl bO
ci
a·bit adder
CI
Output after 6 ns (3 FA delays) co (a)
(b)
Figure 4.35 8-bit adder: (a) carry-rippl e implementati on built from two 4-bit carry-ripple adders. and (b) block symbol.
o
o
(d )
o
Output after a ns (4 FA delays)
Figure 4.34 Exa mple of adding 0111 +0001 using a 4-bil carry-rippl e adder. The output wi ll ex hibit temporaril y incorrect (spu ri ous) results until the carry bit from th e fi ght most btl has had a chance to propagate (ri pple) all the way through to the leftmost bit. OI hin g went wrong-the carry- ripple adder simply is n' t done yet a fter ju t 2 ns. After 2 ns, co O changed fro m 0 to 1. Now, we must all ow time fo r that lIew va lue of coO to proceed through the nex t fu ll -adder. Thus, afte r another 2 ns, 51 wi ll eq ual 1 +0+ 1=0, and co 2 wi ll become 1. So after 4 ns (two full -adder delays). the o utput will be 00 100, as s how n in Figure 4.34(b).
EXAMPLE 4.8
DIP-switch -based adding calc ul ator
Let 's design a very simple calculillor that can add two 8-bit binary numbers and produce an 8-bil result. The input binary numbers wi ll come frol11lwO 8-swilch DIP switches. and the ourput \, i11 be displayed usi ng 8 LEDs. as illustrated in Figure 4.36. An 8-bit DIP (Dualllllille Package) ,witch is a simple digital component havi ng switches th at a user cnn by h:md mo\'e up or dO\\ n. \\ ilh up outputting a ] on th e corresponding pin. and down outputt ing a O. An LED (Iight-emitling diode) is jU'1 a smalllighl Ihm illumi nates when the LED 's input i~ 1. and is dark when the input i~ O. We con implement this calculator by ut ilizing an 8-bit c:llT) -ripple adder for the CALC block. as shown in Figure 4.36. \Vhcn n lIs~ r moves the switches on 3 DIP s \\ itch. the ne\\ bm3~ \-alu~$ propaga te through the carry~ ripplc adder's gates. generating intcnnittent outputs and henC'<' C3lb1ng
172
4 Datapath Components
4.4 Shifters
173
Delay and Size of an 8-Bit Carry-Ripple Adder Assuming full-adders are implemented usi ng two levels of gates (ANDs followed by an OR), and that every gate has a delay of I ns, let 's compute the total delay of a 32-bit carry-ripple adder. Let 's also compute the size of such an adder.
B.bit carry-ripple adder
ci
To determine the delay, note first that the carry must ripple from the first full-adder to the 32nd full-adder. The delay of the first full-adder is 2 gates * I nslgate = 2 ns. The new carry must now ripple through the second fu ll-adder, resulting in another 2 ns. And so on. Thus, the total delay of the 32-bi t carry-ripple adder is 2 nstfu ll -adder * 32 full -adders = 64 ns. To determine the size, note that a full-adder requires approximately fi ve gates (we say approximately because the 3-input OR gate in a full-adder requires more transistors than each 2-input AND gates, and the 3-input XOR gate requires even more transistors). Since the 32-bit adder has 32 full-adders , the total size of the 32-bit carry-ripple adder is 5 gates/full-adder * 32 full-adders = 160 gates. The 32-bit carry-ripple adder has a long delay, but a reasonable number of gates. In Section 6.4, we' ll see how to build faster adders, at the expense of using more gates, but still using a reasonable number of gates.
0
CALC Figure 4.36 8-bit DIP-switchbased addi ng calculator. The addition 2+3=5 is shown.
LEOs
. .' 0 until the values have finally propagated through the entire cirrapid blinking of some of the LE s'. d th LEOs display the correct new sum. CUil, al which point the outpu t stabliJZes an LEeD 1' '1-. 'I.e intenniuent values. we can introduce a • ,L bl" ki g of the s w "' "' If we want to aVOId ",e In n . h ' d' t ' s when the new value should be displayed. We .. ] ..) t the system whlc to lea e button e (for equa s . a fi ured 'both DIP switches to represent the new inputs to be summed. press e only after haVing can g . . F re 4 37 We connect the e input to the 1oa d We can utilize the e input with a register, as JO Iguwl'tc'he~ on the DW switches, new intennittent d . When a user moves 5 input of a parallel loa regISter. bl k d at the register's inputs, as the register holds its values appear at the adder outputs, but are'L OC e 'ous value When the e button is pressed, then on th LED d' splay ",at previ . previous value and hence e s J ded d the LEOs will then display the new value. the next clock edge the register will be.IIOabe '~ct only if the sum is 255 or less. We could connect Notice that the displayed value WI I carr co to a ninth LED to display sums between 256 and 51 1.
1
O'~~FFFFF-~FFFFFF~
B-bit adder
Figure 4.37 8-bit DIP switchbased adding calculator, using a register to block spurious LED outputs. The LEOs onl y get updated after the button is pressed, which loads the output register.
ci
0
CALC LEOs
EXAMPLE 4.9
Compensating weight scale using an adder A scale, such as a bathroom scale. uses a sensor to determine the weight of an
object (e.g .. a person) on the scale. The sensor's readings for the same object may change over lime, due to wear and tear on the sensing system (such as a spring losing elasticity), resulting perhaps in reponing a weight that is a few pounds too low. Thus, the scale may have a knob that the user can tum to compensate for the low reponed weight. The knob indicates the amount to add to a given weight before displaying the weight. Suppose that a knob can be set to change an input compensation amou nt by a value of 0, I, 2, 7, as shown in Figure 4.38. We can implement the system using an 8-bit carry-ripple adder, as shown in the figure. On every rising clock edge, the display register will be loaded with the sum of the currently sensed weight plus the compensation amount.
B-bit adder
ci ~ O
Weight clk t==~::;::::j:::::j:::::j:::::j:::::j:=J:=J:~_.!.A~d~jU~s~te:rJ to display Figure 4.38 Compensating scale: the dial outputs a number from 0 to 7 (000 to Ill), which gets added to the sensed weight and then displayed.
4.4 SHIFTERS Shifting is a common operation applied to data. Shifting can be u ed to manipulate b!ts, li ke when we want to reverse the bits of a number. Shi fti ng is useful for communi aung data serially, as was done in Example 4.6.
174
Datapath Components 4.4 Shifters .. d' 'd' " by a factor of 2. In base I 0, you are Shift ing is also useful for multlpl ymg or IVI In" d b s· Ilply appendin a 0 to a o . I . I ' b 10 can be one y II 0 fami li ar wit h the Idea that mu li p yJJ1g Y . O· I '111e as shiftin o left one -' O· -0 ApP ' ndJJ1 o a IS tIe s, I 0 num ber. For exa mple. ) times I IS). " 0 d b pend in o a 0 meaning by 0' .. . . . b ? I ' I . 1" by ? can be one y ap pOSI tiOn. LIkeWIse. In ase -. mu tip yll " h . base 10 multiplying .. 01 . . ?' . 1010 Furt ermore, 111 . times - IS . . . I f ' So '11 base 2 multiplying Shiftin g left one pOSlll on. So 01 O ' 11Iftlno e t tWIce. I , , . O f I . . base 2 1's 1.I·ke multiby 100 can be done by ap pcndJJ1g two s. 01 S . Ie ft tWIce. . SI11' f(II10 Ie t t"ee lII11es In . I, ' by 4 can be do ne by shI. ftIng " b ? h' f( Plyino by 8. And so on. And since shifting left is the same as multl p yJJ1g y _, S I 109 o ... Od" ddb ? ls 0101. ri ght is the same as dl vld JJ1g by 2. So 101 IVI e . y . fi nd the need to . can be done uSIng . a Sh·ft I reo" lster' so metimes .. d Iwe h'ft b d'f Althou" h slll. ftlng " combinati . .onal component that ~e r fa. n11S the ShIft , an t lat can S l Y 1use a separale fere nt nu mbers of positi ons and in di fferent directions.
EXAMPLE 4.10 Approximate Celsius to Fahrenheit convener using a shifter We arc given a digital thermometer that digiti zes a tempermure in
Celsius inlO on 8-bit binary num ber C. So 30 degrees Celsius would be digilized as 0001111 D. We wan! to Conve n Ihal lem perat ure '0 Fahrenheit . aga in using 8 bits. The equmion for converting is:
F = C*9/5 + 32 Let's assume that we are nOI concerned abou t accuracy. so we' ll replace th e equation by a simpler oll e;
F = C*2 + 32 We can design the converter stra ightforwardl y using a left shifter (wilh a shin in value of 0) 10 compule C*2. and Ihen an adder to add 32 (00 100000). as in Figure 4.40.
Figure 4.40 Celsius to Fahrenheit conve ner.
Simple Shifters An N-bit shifter is a combinat ional component that can shift an N- bit input by some amount to generate an N- bit output. ... .. 5 we wa nt a s hifter that The simplest shi fter shi fts one pOSItIOn 111 one directIon. .ay . . 0 • shi fts left by I positi on. That simpl e shifter's deSIgn IS strai ghtforward , COnSIStln o of Just wires as show n fo r the 4-bit left shifter Figure 4.39(a) . Note that the shIfter has an addItional' input thaLis the va lue La shifLinto the ri ghLmost bit. i3
i2
i1
iO
W q3 q2 q1
qO
$-
~in
i3
i2
i1
iO inl
q2
q1 (b)
qO
whereas most of the world uses the metri c system's
Celsius. Presidents and other U.S. leaders have desired lO switch to the melfic system for almost as long as the U.S. has existed, and several aC lS have been passed over
the centuries, the mosL recem being the Melric Conversion Act of 1975 (amended several limes since). The ACLdesignates the metric sysLem as the preferred system of weights and meas ures for U.S. Irade and ' commerce. Yet switChing (0 metric has been slow. and
~~ q3
.. FAHRENHEIT VERSUS CELSIUS_ The U.S. represents temperature using Fahrenheit.
few Americans Loday are comfonable with metric. The problem with such a slow transirion was poignantly demonstraLed in 1999 when Ihe Mars ClimaLe Orbiter. q3
q2
q1
costing seveml hundred million dollars. was destroyed when enteri ng the Mars atmosphere too quickly_ The reason: "a
navigati on error resu hed
spacecraft commands being
from some
ent in English units
instead of being converted to metric units." (Source: www.nasll.gov). Perhaps if all readers of this book in the
U.S. use Celsius when they talk. we' ll help speed up the transition? So instead of saying ·~It 's a warm ninety
degrees outside today," say "II 's a warm thirty-two degrees outside today." Actually. we mjghl say '11's a wann three ten and two degrees outside today"
(remember correct counting in Chapler I?).
qO
(e)
(a)
EXAMPLE 4.11
Temperature averager Recall Example 4.3 , in which registers
were used to save a hislOl)' of tempera-
Figure 4.39 Combi national shifLers: (a) len shifter wiLh block symbol shown at bOLlom, (b) len shin or pass component. (c) left/rig ht shi ft or pass component. A more advanced shi fte r can eiLher shifL one pos iLi on when an addiLio nal inpuL sh is 1, or can pass the inpuLS Lhro ugh La the OULpULS unshi fLed when s h is O. We can deSign LhaLshifLer USi ng 2x I muxes, shown in Figure 4.39(b). . . An even mo re advanced shifLer can shift left or righL o ne pos iL ion, shown JJ1 FIgure 4. 39(c). When bOLh shi ft control inpuLs are 0, the inpuLs pa s th ro ug h unchanged. When s hl=l , the shi fLer shifLS left , and when sh R=l, the shifLer shi fLS ri ght. When bOLh Lhose control inpuLS are I, the shi fLer could be des igned La OULput Os by connecL ing Os La the 13 inpuLS of the muxe (noL shown). Funher eX Lensions of the simpl e shIfter ~re pOSSIble: such as all owing shi fts of one po iLi on or two posiLi ons. Such mulu funcLl on shlfLers inLernal designs require larger muxes, and mapping of the control Ignals to the mu~ select lines, jusLas was necessary in designing multifuncti on reg i Lers.
ture values over the last three clock peri ods. We wa nt to extend thi s system 10 save th e last four values instead of three. We also want the sys tem to compute the average of the las t four values and ou tput
thai average on an output Tavg. The average of four va lues Ra, Rb. Re, and Rd is (Ra+Rb+Re+Rd) 14 . NOie thaI dividing by 4 is the same as shining right by two. Thus. we can design the sys tem using a right shifter Ihat shifts by two pl aces (wiLh a shift in value of 0). as shown in Figure 4.4 1. Figure 4.41 Temper:Jlure a\'erager using a right10 divide b) 4.
shifl-by-~
175
b
176
4 Datapath Components
Barrel Shifter An N.bil barrel shifler is a general purpose N·bit shifter that can shift or rotate any number of posi tions. For sim plicity. le!"s consider only left shIfts for the moment. An .. bit barrel shifter can shift left by I position. 2 positIons. 3 poslllons. 4 posllJOns, 5 poSI· tions. 6 position,. or 7 positions (and of cour eO positions. meaning no shift is done). An 8.bi t barrel shifter therefore requires 3 control inputs . say x. y, and Z, to speCIfy the dts· tance of the shift. xy z- OOO may mean no shift. xy z~OO I shift by I pos ition, xy z~OIO shifL by 2 positions. etc. We cou ld design such a barrel shifter by placing an 8x I mux in front of each of the 8 shifter outpu ts. connecti ng xyz to each of the eig ht mu x's select input. and then con· necLing the mux inputs wi th the appropriate shifter inputs for each configuraLion of x, Y, and z. So 10 (corresponding to xy z- OOO. meaning no shi ft) of each mu x would just get the present bit's sh ifter in put. II (corresponding to xyz~OOI. meaning left shift by one position) would get the shifter input one posi tion to the right. 12 (xy z=O I 0, meaning left shift by two positions) would get the shifter input two positions to the right. And so on. Such a design. while conceptually straightforward. has too many wi res being routed about. And the design does not scale well to larger bit· widths. such as a 32·bit barrel sh ifter-a 32x I multiplexor cannot be built with two levels of gates (AND/OR), because gates with 32 inputs are too big to be implemented efficiently. and must instead be imple· mented using multiple levels of smaller gates. A more elegum de,ign for an S·bi t barrel shifter consists of 3 cascaded simple shifters. as shown in Figure 4.42. The firs t simple shifter can shift left four positi ons (or none). the second c
4.5 Comparators
177
45 COMPARATORS We often Want to compare t b' than the other F wo tnru: numbers to see if Ihey are equa l, or if one is greater suring huma~ ~ ex~mple. we 111Ight want to sound an 819rnl if a thermometer meaFahrenheit (394 d Y emperature reports a temperature greater than 103 degrees binary number~. egrees Celsius). Comparator components perf0n11 such comparison of
Equality (Identity) Comparator An N·bil eqllalily COm I ( . para or sometImes called an idel/lily comparalor) is a datnpath cfomLhponent .that compare two N· bi t input A and B. setting an output control signal to 1 I e two tnputs are equal 1\yo N b' . B-b3b2blbO . . • It mputs, say two 4· bit inputs A- a3a2a l aO and a3-b3 2 b2' arc equal If each of theIr corresponding bit pairs are equal. So A-B if .a - ,al-bl. andaO -bO. turinFOllowing the combinational logic design process of Table 2.5, we can start by capg the functi on of a 4· bit equali ty comparator as an equation: eq - la3 b3+a3 'b 3 ' 1 laObO+aO 'bO' 1
* la2b2+a2 'b 2 ') * lalbl+al'bJ'1 *
b th ~Ch term detects if the corresponding bits are equal, namely, if both bits are 1 Or o liS are O. The expressions inside each of the parentheses represent the behavior of ?n XNOR gate (recall from Chapter 2 Lhat an XNOR gate outputs J if the gate's two tnput bIts are equal), so we can replace the above eq uation by the equivalent equation: eq - (a3 xno r b31 xnor bO)
* (a2 xnor b2) * lal xno r bl) * laO
We convert the equation to the circui t in Figure 4.43. a3 b3
a2 b2
4·blt equality comparator eq Ib)
Figure 4.43 Equality comparalor: la) inlemal design, and (bl block symbol. Of course, we could have built the comparator starting with a truLh Lable, but that would be cumbersome for a large comparator, with too many rows in the truth table to easily work with by hand. A truth Lable approach enumerates all the possible situation for which all the bits are equal, si nce only those situations would have a I in the column for the output eq. For two 4-bit numbers, one such situation will be 0000 -0 000.
J
178
Datapa th Componen ts 4.5 Comparators
Anot her wi ll be 000[=0001.
learly, there wi ll be as many situ at ions as there are 4-bit
binary n ll ll1bcr~-lllca n ing there wi ll be 2J = 16 ~ itu a l.i ons where both n~lll be rs are equaJ.
F r two 8-bi t numbers, there wi ll be 256 equal ilU allons. For two 32-b lt numbers, there will be four bi ll ion equal ,i tuat ions. A comparator built wilh such an approach wi ll be large if we do n' t min imile Ihe equation, and Ihat minimi zali on will be hard with such large nu mbe" of terms. Our XNOR-based des ign looks 10 be much simpler and scales to wide inp uts wonderfu ll y- widening Ihe in puts by one more bil invo lves merely adding One morc XNO J~ gil le.
ou t_9 i 11_9 + (i 11 €q A a ' b ' ) ou _It - in. It + (i n_€q * a ' , b) out_€q - in €q * (a XNOR b)
Magnitude Comparator- Carry-Ripple Style
cGJ)
An N-bitmagl/itll de comparator i, a dalapalh componenl Ihal compares two N-bit binary num bers A and B. and indicmes whel her A>B . A=B , or A A=a3aZalaO-10 11. B=b3bZb lb O= 100 1. We stan by looking al the high-orde r bi IS of A and B, namely. a3 and b3 . Since Ihey a.re equal (bot h are 1). we look at Ihe nc.XI pair of bits. a Z and bZ . Again . since Ihey are equal (both are 0), we look at the neX I pair of bi". al and b1. ince aJ>bl (l>O ), we conclude th ai A>B . Thu" comparing IwO bi nary num bers takes place by comparing from the high bitpairs dow n 10 Ihe low bil -pairs. A; long as bi l-pairs arc equal. we need to compare the neXI lower bil -pa ir. As soon as a bil-pa ir is different. we conc lude that A>B if a i =1 and b i =0 , or Ihal A
b3 b
tgl __ in_gl leq ..... in_ eq
lIt __ in_1I
a2
~
al
b2
~
~
bl
~
~
(a)
Stage 1
o
1
bl
bO
AglB AeqB AIIB Stage2
Slage l
(0 ) 1
a3
b3
~Q) a2
StageO
o
b2
1
aO
bO
AglB AeqB AIIB (b)
AglB AeqB AtlB SIage2
o
b3
~
oul_gl oul_eq OUUI
Stage3
a3
aO bO a
1
0
b3
a2
Slagel
StageO
cG]) al
bl
SlageO
AgtB AeqB AIIB StageO
4·bil magnilude comparalor
o
1 (b)
Figure 4.44 4-bil magnil ude comparalor: (a) internal design usi ng iden lical components in each slage. and (b) block symbol. Each stage works as follows . If i n_9t=1 (meaning a higher stage determined A>B), th is stage need nOl compare bits, and just sets ou t_9 t = 1. Likewi se, if i n_lt =I (meaning a hi gher stage determined A
179
if acl and b-O , sellinc Ollt I - [ ' f' ~ I a-O and b- 1. " nd setl ing ou t €q-l if a and b bOlh equa l I or bOlh equal O. . , ' We could C'lplu re II r Ie unCllon 01 a siage', block u~ in g a Irulh lab Ie wilh 5 ;'lP1115 For . h ' brevlly l a ugh " II ' I . . 'f ~ , \\e " mp y U"" Ihe fo llow ing equal ions deri ved from the earlier exph nati on 0 how c!ach Si a k I ' . ' . " ge wor s: I Ie CirCUli for each stage wo uld follow di reclly from tIlese eq uall on>:
a3
~
b3
t
a2
b2
al
~
~
~ aO bO ~
glB eqB ItB Stagel (d)
Figure 4.45 The "rippl ing" wilhin a magnitude comparalor.
Stag eO
180
4.6 Counters
. f A~ 1011 and 8~1001. . arator works for an IOpUt a . Figure 4.45 shows how thIS camp sisting of four stages . We can view the comparator's behavIOr as can by sellin o the external input I eq~ I, 5() ve star! 0 . -1 d In Stage3 shown in Figure 4.4 a, \ the comparison. Stage3 has 1 n_ eq- ,an to force the comparator to actually do '11 become I , while o ut _g t and out_I t since a 3 ~1 and b 3~l, then ouLeq WI
Data path Components
wi ll become O. that since out_eq of Stage3 connects we see .'11 be 1 Since a2~0 and b2~O, then In Stage2 shown in Figure 4.45(b). 2' in eq WI '. to in eq of Stage2, then Srage s -t d ou t 1 t will be O. h'l out 9 an . out eq will become I , w J e that since Stage2' s out _e q IS con4.45(c), we see ' 1 1 be 1 Since a1 ~ 1 and b1=O, In S-tage I shown in Fioure 0 J's i 0 eq WI . nected to Stagers i o_e q, Sla;~t eq ~d out_l t will be O. out gt will become 1, whIle that the outputs of Slagel cause . 445(d) we see In StageO shown in FIgure . . h'directly causes StageO's out_g t to become StageO's i o_g t to become I, whlc b a Notice that the values of a a and bO l and causes out_eq and o ut_l t to e . t to the comparator's external out, . 0' outputs connec are irrelevant. SIOce Slage s 8 d A1t8 will be O. 8 ' 11 b 1 whIle Aeq an puts, Agt WI e , h he staoes in a manner similar to a I . les throug t " . Because of the way the resu t npp '1 h' way is often referred to as havIOg a . d para tor bUl t t thou h whatIS's rippling is not rea IIy a " carry .. b'II. carry-ri pple adder, a magOltu e com ca rry-ripple style implementallon, even g t d straiohtforwardly WIth another 4-bll . an be connec e o . . . The 4-bit magOltude comparator c. . d comparator and likeWIse to bUIld any tu 'Id 8-btl maglll e , ( magnitude comparator to bUl an. o . on outputs of one comparator Ag tB , . I b size comparator, sImp y y connectln . 0 theofcompans the next comparator (I 9 t, I eq, I It) . Aeq8, A1t8) wi th the comparIson IOpUtS of looic, and a gate has a I ns delay, then each If each stage is built from two levels f " -ripple style 4-bit magnitude comparstaOe wi ll have a 2 ns delay. So the delay 0. a Carryarator built with thi s style wi ll have a ato~ is 4 stages • 2 ns!stage = 8 ns. A 32-blt comp delay of 32 stages * 2 ns!stage = 64 ns. EXAMPLE 4.12
. . . f 0 numbers using a comparator Computing the mll11mUm 0 tw ak I va 8-bil inputs A and 8, and OUlputs an t es \ magnitude comparator and an 8.bu 2xl f A dB Wecanusea 8-btt OUlpUI C thaI IS the min Imum 0 an shown In FIgure 4.46 I mponent that We want to deSign a combmauona co
multiplexor to Implement thiS componen t, as MIN
A1-__~Bl;::::::::::::::::lh~~8 8 8
A
B
8-bit magnitude comparator
8-bit
2x1 mux
8 C
(b)
. .mUm 0 f Iwo numbers:
181
If A
4.6 COUNTERS An N-bit COUllIer is an extended N-bi t register component thaI can increment or decrement its own va lue on each clock cycle, when a count enable control input is I. Illcrement means to add I. while decr emellt means to subtract I. A counter that can increment is known as an liP-COli liter , a counter that can decrement is known as a downCOli Iller , and a counter that can increment and decrement is known as an IIp/doWIICOlllller. A 4-bi t Up-counter would thus count the fo llowi ng sequence: 0000 , 0001. 0010 , 0011 . 0100, 0101. 0110, 0111. 1000. 1001, 101 0, 1011, 1100, 11 0 1. 1110, 1111. 0000 , 0001,etc. Notice that a counter wraps aroulld (also known as rollillg over) from the highest value (1111) to O. Likewise, a downcounter would wrap around from 0 to the highest value. A control output on the counter, often called termillal COU llt, or tc , becomes 1 during the clock cycle that the counter has reached its last (terminal) count value, aft er which the counter wi ll roll over. Figure 4.47 shows the block symbol of a 4-bi t up-counter. When co t=I , the counter increments its own value on every clock cycle. When cot~O. the counter maintains its present va lue. On the cycle that the counter rolls over from 1111 10 0000, the counter sets tc=l for that cycle, returning tc to a on Figure 4.47 4-biI up-counter block symbol. the next cycle.
Up-Counter We can design an N-bit up-counter using the register design process described in Table 4. I- the incremented value of the register would be fed into a mux input, and the counter's control lines would be mapped to the mux select lines. A simpler view of an upcounter design is shown in Figure 4.48, assuming an incrementer component exists to add 1 to the present value. When c nt=O . the register should maintain its present val ue. When c n t = I, the register should be loaded wi th ils present va lue plus 1. Note that the 4input AND gate causes temlinal count t c to become 1 when the counter reaches 1111. Figure 4.48 4-bil up-counter imernal design.
182
4.6 Counters
Datapath Components Incrementer
.'
We could usc the sa me combi nat ional log ic des ign process to build larger incrementers. Reca ll that we said in Section 4.3 th at building adders USing the combinational
'rcuit for the incre-
We need to des ion a CO lllbJl1Htl Onal CI
.
0
th e
0 11 00 1 1
carries:
. menter. We could" sImply use .an N-bit adder. by. setlln" a an N-bit d I · ·n to But usm" 8 input to 0001 an tIe CaJrY- I . e loo ic involved in adder is overki ll-we do n t need all th t '0001 Instead. an N-bi t adder, because 8 is always JUs . .' mber dd ' 1 to 3 bma1 )' nu observe in Figure 4.49 that a mg ' three bits per invo lves only two bns per column . not b rs col umn like when add .mg twO gener,31 bmary num S ( eon.4 3) Recall that a half-adder adds two bits (see ec I 1." lf: Thus. a simp le .mcrementel. caul d be budt usmg 1,1 adders, as shown in Figu re 4.50.
a
logic design process was not very practi ca l. Yet here we built an incremenler using the
combi national logic des ign process. A key difference to note is that a 4-bit adder has 8 inputs, whereas a 4-bit incrementcr has only 4 inputs. Thus. we can build wider incrementers as two- level logic imp lementat ions usi ng the combinat ional log ic design process. Of course, at some point. even the number of inputs for an incrementer gets too large, in whi ch case we might chain smaller incrementers toget her to make a wider incrementer.
unu sed ~ 1
00100
Figure 4.49 Adding I to a binary number requi res onl y 2 bits per co lumn.
EXAMPLE 4.13
Up-counter used in the above-mirror display In Example 4.4 and Exa mple 4.6. we assumed
pressing a mode button would cause input." xy to
sequence from 00. 01. 10. 11. and back to 00 again. A simple design to ach ieve such sequencing. assuming the mode input is 1 for exac tly one clock
x y
cycle per bUllon press (sec Example 3.9), "tilizes an
:!.
up-counter. as shown in Figure 4.52.
$c
"E~
EXAMPLE 4.14
u
Figure 4.52 Sequencer for xy inputs of
1 Hz pulse generator using a 256 Hz oscillator
above-mirror display.
Suppose we have a 256 Hz oSci llntor. but we wa nt a
S
(b)
I Hz pulse signal. We can cOllven the 256 Hz signal
to a I Hz signal P lIsing an 8-bi t Counter. The 8-bit COUlHer wraps around every 256 cycles. so we can si mply connect the osci llator signal to the counter's clock input, se t the counter's load input to 1. and th en use the cou nter's tc output as the pulse signal.
Figure 4.50 4·bit incremenrer: (a) internal design. and (b) block symbol.
as showll in Figure 4.53. A I Hz signal may be
We could instead design an incremen ter
using th e combin a·
tiona I logic design process fro m Chapter 2. We wou ld start with a truth table, shown in Figure 4.5 1. We obtain each output row simply by adding 1 to the corresponding input row binary number. We would then deri ve an equation for each output. For example, we can easily see that the equation for cO is eO=a3aZa1aO . We can also easily see that sO=aO · . We would derive eq uations for the remaining outputs, and then implement the circuit for each output. The resu lting incrementer would have a total delay of on ly two gate levels, which is less delay than the incrementer in Figure 4.50 built from half-adders.
32
31
0
0 0 0 0
0 0
0 0 0
1 0 0
00 0 1 0 1 0 1 0
0 0 0
0 0 1 1 0 0
usefu l for driving a clock or a wmch, for example. since I Hz means I pul se per second.
Outputs
Inputs 33
0 1 0 1 0 0
183
cO
s3
s2
sl
sO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o o o
0
0
1
0 0
o o o o
1
1
o o
0 1
o 1
1
1
o
o
0
o o
o
o
1
o 1
1
o
0
o
1
o 1
1
1
1
o
0
o
0
Figure 4.51 Truth table for four-b it incrementer.
Figure 4.53 Clock divider.
Down-Counter A down-coumer can be designed simil arly to an up-counter, repl acing the incrementer by a decrememer, as shown for tile 4-bit downcounter in Figure 4.54. A decrementer could be designed in a similar manner as an incrementer, staning from a tnlth table like that in Figure 4.5 1. Note that the term inal count te becomes 1 when the down-coumer reaches 0000 , implemented using a NOR galerecall Ihat NOR oUlputs 1 when all its inputs are O. The reason the down-counter detects 0000 for te, rather than 1111 like the upcou nler. is because a down-counter wraps around after 0000. as in the fo llowi ng coum sequence: 0100, 0011, 0010, 0001. 0000.
1111, 1110. .
Figure 4.54 4~bit down~counter dl!sign.
184
4 Datapath Components
4.6 Counters
An
up/down-coullter
can
COLIIlI
e ither up or down. It requ ires an input signa l d i r to indi cate the cou nt d irecti on, in audition to the count e nab le signal cn t. We' lI let d i r=O mean to count up anu d i r= I mean to cou nt down. Figure 4.55 shows the design of such a .J-b it up/dow n-counte r with synchro nous clear. A 2x I mu x passes e ithe r the decremented or incremented
va lue.
with
dir
elr ent
di r
selectin Q among the two-d i r=O (co unt ~p) pass~s the incremented va lue and d i r = I (co unt down) Figure 4.55 4-bi t up/down-cou nter design. passes the decremented value. The passed va lue gets loaded into the 4-bit register if cnt=1. di r a lso se lects w~,eth e r to pass the NO R or AND output to the termina l count tc ex te rna l output-d 1 r-O (count up) se lects the AND. while d i r= I (count dow n) se lects the NOR. . . Alternati vely. we could design an up/down-counter using the regtster destgn process of Section 4.2. by directly connecting the incrementer and decreme nter outputs to mu xes In front of each flip-flop. and mapping the c 1 r. cn t. and d i r control stgnals to the mux select llIles. No tice that we a lso added a control input c 1 r. whic h we could have added to the ~p counter and down-cou nter too. Ihat when 1 SYllchrollol/sly clears the regt ster, mealllng reselling the reg ister to a li Os on a risi ng clock edge. We used a 4-b it register wi th clear to support the c lear operati on.
EXAMPLE 4.15
light sequencer We want to design a sLrip of 8 light bulbs. such thaL the bu lbs illuminate one :1t a lime. ri ght to left , and then repeal illuminating in Lh aL sequence. The sequence
clk (1 Hz)
should proceed at the rate of one bulb per second. Such a lighting displ ay might be attracti ve outside a restaurant or movie the.ner. for example. For simplicity. assume we have an oscillaror that
generate a I Hz clock signal (meaning one rising clock edge per second). We ll connecl Ihis clock to a 3bi L up-counter. and connect the counter' s three outputs 10
I8S
Counter with Parallel Load
Up/Down-Counter
lights O O O O O O O O Figure 4.56 Light sequencer.
a 3x8 decoder. as shown in Figure 4.56. When the power is on, the system counlS up (we don't kn ow what th e initial value of the counter
wa,. but it doesn't really matter). wrapping around from 111 10 000. We don' t need the tc output in this example. Notice that we used a 3-bil COlllller will! (I decoder, and 1101 all 8- bil COlllller , even though there were 8 OUlpUtS. An 8-bit counter would generate the sequence 00000000 . 0000000 1. 00000010 ....• 11111110. 11111111. That sequence is 1101 the desi red sequence.
Cou nters often come wi th the abi lily to initiali ze the count va lue, achieved by load ing the counter's registe r wi th parallel da ta. Figure 4.57 shows the design o f a 4-bit upcounter with para llel load . When control input 1d is 1. the 2x I mu x passes load data input L to the register; when 1d is O. the mu x passes the incremenled value. Furthemlore. we OR the counter's 1d and cnt s igna ls to generate the load signa l for the registe r. Whe n c n t is 1. the incremented value wi ll be loaded. Whe n 1d is 1. the parallel load da ta wi ll be loaded. Even if c nt is 0, 1d = 1 causes the register to be loaded. A dow n-counter or up/ down-counter could similarly be exte nded to ha ve a para llel load. Para llel load is useful when we wan t to generate a pu lse signal that is not directl y obtainable from lelting a counter wrap around and pulse its t c output natura lly. An N-bit counter narurally wraps around every 2N cycles. What if we wan t a pulse e very X cycles, where X is not a
Figure 4.57 Inlemal design of a 4-bit up-counter with load.
4-bit down-counter
Figure 4.58 A counter selup thaI pulses t C every 9 cycles.
power of2? For example. say we have a 4-bit down-counter. which nonnally pul es the tc OUlput and wrap aro und every 16 cycles. and suppose we want to pulse every 9 cycles. We can ach ieve Ii pu lse every 9 cycles by selling the load data input L to 9-1. or 8 (1000). and by connecting the tc outpu t to the load con trol input 1d. as shown in Figure 4.58. When the counte r reaches its lowest value (0000). tc wi ll become 1. cau ing the 1d inpul to become 1. Thus. on the next clock cycle, the counter will load 1000. rathe r than wrapping around to 1111. (Note: the load occurs on the lI exl cycle. not the present cycle. because t c changes to I after the rising clock edge. so the new value for 1 d doe n' t gel seen until the next clock edge.) The counter would thus count in the sequence 8. 7. 6. 5. 4. 3. 2. I. O. pulsing tc and the n re tu rn ing 10 8. The reason we load 9-1 . rather than 9. even though we wan t a pul e every 9 cycles. is because we must remember that 0 is included in the count sequence-just as Ihe count from 15 down to 0 takes 16 cycles. We could instead u e an up-counter for the same purpose. but we must make the load value eq ua l to the tota l cycles minus the desired cycles. So for the above example. we wou ld use a load va lue of 16 - 9 = 7 (0111). The counter would count the sequen e 7. 8. 9. 10. I I. 12. 13, 14. 15. pulsing tc and then retuming to 7.
186
4 Oata path Components
EXAMPLE 4.16
4.6 Counte rs
New Year's Eve countdown display
d
d ad
I ul the numbers 59 down to O. an a ec
gale output set the COunter clear inpu t to I . We assume the counter's clear input clr lakes precedence o:er th e Counter's coun t input ('nt. Since th e AND gme'~ output wi ll pulse every 60 cycles and the Input clock freq uency is 60 Hz. th is circuit convcns a 60 Hz input clock into a J Hz output clock. A circliit thm convcns an input clock into a new clock wi th a lower frequency is known as a
er
h' . 1ple we' ll repl ace the micropro" " b d h' l output In t IS cX3 n . (0 Il lumlllate one 01 60 IIght~
187
clock diJll·der.
I d 59 'nlO the coumer and then the ' 11 d reset 10 oa . I . down. Assume the u~er can press a bUllon ca e . . (d' nl) 10 the 1 position (coun t) to . d f Ih" pOSI tion on user can move n switch count own rOI11 L: • FI cou. 459 down-coumer ava il ab le. whi ch ca n CO ll nt rom -
a
beg in the countdown. The system im plcmcn13lion is shown III
Igure .
Timer
.
A common use of a counte r is as the centra l compone nt wilhin anolher device called a li mer. A limer is a special type o f counter that mea ures time. Measuring time is a very common tas k in a dig ital syste m.
Happy
a
cO c1 c2 c3 c4 c5 c6 c7
iO i1 i2 i3 i4 i5
New
dO
Yea r!
d1
d2 o---.,........... d3 1---........-r'\
bC('(lIIse we mus,
•••
remember ,"m 0 ;s parr o/the
d5a d59
CO/U/I. Tr\' cOlmlillg from 9 D. raising
dOll'll fO
d60
(I finger ('(lch lime )'011 say a I lIImbe r. No/ice {"m H'hell roll remc/t D. fell fingers are lip.
d61
a·bit
c~~~~~r Ie
fireworks
d62
~~~4
One type of timer is based on " down -counte r. We sto re a value into the counler. and wa il for the terminal count (0) to be reached. If we know the counter's oscillator frequency. the n we can load " value corresponding to a des ired time interval. For example. SUppose we Want 10 know when one second has passed. usi ng a counter havi ng a clock freque ncy o f I kH z. We would thu load 999 (in binary. meaning 1111100 Ill) into the counte r and enable count ing. Aft er I second, the counter wo uld reach 0 and assen its terminal count outpu!. notifying us that I second has passed. A timer may repeat this process a utomatically, using the term inal count to auto mat icall y reload the de ired time va lue (999 in our example) into the counter. Such a timer might be used in any type of watc h or clock. Our earlier three-cycles-hi gh lase r time r (from chapter 3) could have been bui lt using a timer component. especially if in tead o f wa nting the lase r high for three cycles, we wa nted the laser hi gh for a pe riod of time like 1.5 seconds. Another type of timer is based on lin up-counte r. We reset that counte r to O. and then e na ble counting whe n some e ve nt occurs that we wa nt to time. When the event e nds. we di sable the counter, aft er which the Counter contains the nu mber of cycles that occurred during the event. Knowing the time of one clock cycle. we mUltiply the number of cycles by the time of one clock cycle to obtain the total time for the event. For example. if we time an event as las ting 500 cl oc k cyc les. and the timer's osc ill ator freq ue ncy i I kHz . the n the time for the event was 500 cycles * 0.00 1 slcycle = 0.5 s. We ill ustrate this type of timer using all example.
We load 999. rather ,hall 1000.
d63
Figure 4.59 Happy New Year counldown system using a down-counler. Notice thaI the tc signol is our "Happy New Year" indicotion. We'veconnecled that signal to an outpul called fi reworks. which we' ll assume aClivates a deVIce Ihat Ignlles fireworks. Happy New Year!
EXAMPLE 4.17
1 Hz pulse generator using a 60 Hz oscillator In the U.S .. electric ilY 10 Ihe home operates as an alternating current with a frequency of 60 Hz. Many appliances convert Ihis signal to a 60 Hz digital signal. and then convert the 60 Hz dlgll,1 signal to a I Hz signal. 10 drive a clock or olher device needing to keep track of lime at Ihe granu· lari ty of seconds. Unli ke Example 4.2. we can 't simpl y use a cou nter of a parti cular bilwid th. since no basic up-counter wraps around after 60 cycles-a 5-
bit counter wra ps around every 32 cycles, whil e a 6· bit counter wraps every 64 cycl es. Let's start with a
EXAMPLE 4.18
Hig hway s pee d meas uring system Many highways and freeways have ys tems that measure the speed of car at various parts of the highway and upload Ihal speed information to a cenl ral compu ter. Such inforn1a tiol1 is used by law cnrorcemcnr, traffi c planners. and rad io nnd Internet traffic rcpons.
6-bit up-counter
One technique ror measuring the speed of a car use two sensors embedded under the road. 3S ilJ ustraied in Figure 4.6 1. \Vhen a car is over a sensor, the sensor ourputs n 1: otherwise. the sensor outputs a O. A sensor's output travels on underground wires to a speed-measuring computer box. some
csc
6-bit counter, which coun ts fro m 0 to 63 and then (60 Hz) wraps around to O. We' II add some some extra logic, as shown in Figure 4.60. The extra logic should detect when Ihe counter has counted up 10 59, and should clear the counter back to 0 on the neXl rising clock edge ra lher Ihan lelting the counter continue counting to 60 and beyond . Fi fty- nine as a 6-bit binary number is 111 11. Thus the AND gale in Figure 4.60 detec ts 111 11. in which case the AND Figure 4.60 Clock divider.
of wh ich are above Ihe ground and others of which are underground. The speed measurer delermines speed by di viding Ihe distance betwcen the sensors (which is fixed and known) by the time required for :l vehiclc to Lra vel frollllhe first sensor to the second sensor. If the distance between the ~ensors is 0.01 miles, and a ve hicle takes 0.5 seconds to tr3vel from the first 10 the second sensor. then the ,elucle's . peed is 0.0 1 miles I (0.5 seconds • ( I hOllr 13600 seconds)) = 72 mile per hour. To measure the lime between the sensors. we can con truct a imple FS~ l lhat controls:1 16-bu
a a
timer. as shown in Figure 4.61. State SO clears the timer to O. The FS~I transition, 10 ' tate J \\ hen a car passes over the first sensor. 51 starts Ihe timer counting up. The F M stays in J until the 3r
e
188
4 Datapath Components
4.7 Multiplier-Array Style
189
4.7 MULTIPLIER-ARRAY STYLE An NxN lIIulliplier is. a d'II ' li.es two N-blt. inpul binary , ,'IP'a tl1 component Ihat mul tip Illl.mbers A (Ihe multiplkand) nnd B (Ihe multi plier). and OUIPUIS an (N+N)-bi t result. For example, an 8x8 muili plier multiplies 11'0 8- bil bi nnry numbers and OUIPUIS a 16-bil resu lt. Deslgnlllg an NxN multiplier in 11'0 levels of log ic using the siandard combinati ona l deSign process wi ll result in 100 complex of a design. as we've al ready seen for prev Ious operati ons like add ition and compari son. For multipliers wilh N grealer than 4 or so, we need a more effi cienl melhod .
,, !..-----------a (a)
b'
. We can creale a reasonably sized multiplier by mimick ing how we perl'onn multiplicall a n by hand. ConSider multiplying 111'0 4-bil binary numbers 0110 and 0011 by hand:
Figure 4.61 Measuring veh icle speeds in a highw<.Jy speed measuring system .
OllO
(b)
'lSSCS over the o;::ccond 'ensor. causing a transi ti on 10 swtc 52.52 SlOpS Ih~ counti ng .'lIld computes ~~~ ',i;11C lIsino II~e limcr"'s outpu t C. Assuming a I kHz clock input to the tim er. mean.lI1~ each cycle is 0.00 1 s~co~ds. theillhe tim e would be C * 0.001 s. :hal re s~Jl I wou l ~ th~~l be Il1UltlP~l~d by 3600 to obl~lin the speed. We omit the impiemen talion detail s of th t; speed computatIOn, which
D.?"
wou ld Illost likely be implcmented as so ft warc 011 a microprocessor.
• HOW DOES IT WORK? CAR SENSORS IN ROADS.
a2 b2
al b1
aO bO
bOa3 bOa2 bOal bOaO bla3 bla2 bl al bl aO 0 b2a3 b2a2 b2al b2aO 0 0 + b3a3 b3a2 b3al b3aO 0 0 0 - - - - --- - ------ -- --- - ------- - - - - - - - -p7 p6 p5 p4 p3 p2 pI pO
Many people lhink Ihal Ihe loops seen in Ihe pavemenl are scales the loops trying 10 gel a lighl 10 change. ThaI does n'l work, bUI II sure is entenain ing to watch.
tum green
a3 b3
- - - - - - - - - - - - - -- - ---------------- ----
that measure weight-I've seen bicyclists jumping up and down o.n
10
(Ihe product is Ihe sum of all Ihe panial producls: 18. which is 6*3)
X
change the current and seeing how much the current reaJly changes In a certain time period). and if inductance is more than nonnal, the circuit aSSumes a car is above the loop of wire.
for the emergency vehicle (e.g .. 3M's "Oplicom" syslem). Such systems are anolher example of digilal syslems, reducing the lime needed by emergency vehicles 10 reach the scene of an emergency as well as reducing accidents involving the emergency vehicle ilself proceeding Ihrough a traffic light, thus often saving lives.
(Ihe lap number is ca lled the lIIultiplicalld) (Ihe bOllom number is ca lled Ihe IIIl1ltiplier) (each row below is called a partial product) (because Ihe righlmoSI bil of Ihe multipli er is 1. and 0110*1 =0110) (because Ihe second bil of Ihe multiplier is 1, and 0110*1 =0110) (beca use Ihe Ihird bil of Ihe multipli er is O. and 0110*0=0000) (because Ihe leflmOSI bil of Ihe mullipli er is O. and 011 0*0=0000)
Each panial prodUCI is easi ly oblained by ANDing Ihe presenl multip lier bit wilh lhe multipl ica nd. Thus. multiplication of IWO 4-b il numbers A (a3a2alaO) and B (b 3b2 blbO) can be represenled as fo ll ows:
ci rcuil keep checking Ihe wire's induclance (perhaps by Irylng 10
signal from emergency vehicles, causing the traffic light
0110 0110 0000 +0000 00010010
How does a highway speed sensor or a traffic light car sensor know mat a car is present in a parti cu lar lane? The main method t.oday uses what's called an inductive loop. A loop of wire is placed Just under the pavement-you can usually see the cu ts, as in Figure 4.62(a). T~at loop of wire has a particular "inductance," which is an electrol1lcS tenn describing the wire's opposition to a change in eleclIic current-:higher inductance means the wire has higher opposition to changes 10 current. It turns out that placing a big hunk of metal (like a car) near the loop of wire changes the wire's inductance. (Why? Becau ~e the metal disrupts the magnetic field created by a changing current In the wire-bul that's getljng beyond our scope.) The traffic light c,antral
Many others believe Ihal small cylinders a((ached 10 a Lraffic lighl 's suppon anns, like Ihal in Figure 4.62(b), delecl vehicles. Those inslead are Iypically devices illal delecl a special encoded radio or infrared-lighl
001l
(b)
Figure 4.62 (a) Inductive loop for delecling a vehicle on a road, (b) emergency vehicle signal sensor for changing an intersecti on's traffic
lighl 10 green for Ihe approaching emergency veh icle.
(ppl) (pp2) (pp3) (pp4)
Afler generaling Ihe partial produclS (pp l. pp2. pp3. and pp4) by ANDing the preselll mu lli plier bil wilh each mullipl icand bit. wc me re ly need 10 sum those partial products together. We can use Ih ree adders of varying widths for compuling Ihat sum. The resulting design is shown in Figure 4.63. Th is design has a reasonable size. abo ut Ihree times bigger than a carry-ripple adder. The design has reasonable speed. The delay consists of I gate-delay for generating the partial producls. plus Ihe delay of Ihe adders. If each adder is a carry-ripple adder. then the 5-bil adder delay wi ll be 5*2 = 10 gate-delays, Ihe 6-bi l adder delay will be 6*2 = 12 gale-delays, and Ihe 7-bil adder delay will be 7*2 = 14 gate-delays. If we a sume lhat lhe 10la l delay of Ihe adders is simply Ihe sum of lhe adder delays. Ihen the lotal delay would Ihus be I + 10+ 12 + 14 = 37 gale-delays. However. Ihe 100ai delay of carr -ripple adders when chained logelher is aClually less Ihan Iheir sum-see Exercise 4. 15.
190
Datapath Compone nts
4.8 Subtractors a3
a1
a2
191
itself borrow from the fa n l I . u 1 co umn . The result of the second column is then 10 _ I _ 1. The third column bec f h b '. , ause a I e a rrow generated by Ihe second colu mn. has an a of 1, whIch IS nOi less than b I If ' . . . so 11e resu l athe Ihlrd co lumn IS I-I ~O. The founh col umn has a=O due 10 Ihe bo f h . . 0-0=0. rrow rom I e Ihlrd colu mn. and smce b is also 0, the resull is
aO
l si column
o - 0
o
% 10
2nd column 10
o l{) 1
..y
..y
41h column
3rd column
o
0
..y
- 0
~O
1
0
-0
o
..y
0
0
- 0
o
1
0
(a)
~ A B ;
p7 .. pO
Block symbol
Figure 4.63 Inlerna l design of a 4-bil by 4-bil array-SlY Ie ll1ullipl ier. Delays for larger multipliers. which lVili have an even longer chain of adders, lVi li be even slolVer. Faster mU liplier des igns are possible. al Ihe expense of more gates.
(b)
(e)
Figure 4.64 Design of a 4-bil sublraClor: (a) subtraclion "by hand". (b) borrow-ripple Implementation with four full -subtraclors \vi th a borrow-in input wi. and (c) block symbol.
4.8 SUBTRACTORS An N-bit slIblracl or is a datapath component that takes two N-bit binary inputs A and B. and outputs an N-bit resull 5 equaling A- B.
Subtractor for Positive Numbers Only Subtracti on gets slightly more complex when we consider negati ve res ults, like 5 - 7 = -2, because thus fa r we haven't discussed representation of nega ti ve numbers. For now, let's assume we are on ly dealing with positive numbers. so the subtractor's inputs are positive, and the result is always positi ve. This cou ld be the case, for ex ample, when we are designing a system that only subtracts smaller numbers from larger nu mbers. such as when compensating a sampled temperature that wi ll always be greater than 80 using a small compensation value that will always be less than 10. Designing an N-bit subtractor using the standard combinati onal logic design process suffers from the same ex ponenti al size growth problem as an N-bit adder. (See Section 4.3.) Instead. we can aga in try to mimi c subtraction by hand in hardware. Figure 4.64 shows subtraction of 4-bit binary num bers "by hand." Starting wi th the nrst column , we see that a is less than b (0 < 1). necess itating a borrow from the previous column . The nrst column result is then 10 - 1 - 1 (in base ten, two minus one equals one). The second column has a for a because of the borrow by the nrst column, mak ing a < b (0 < 1), generating a borrow from the third column- which must
a
Based on the above-described behav ior. we could create the internal design of 3 fullsubtractor combinat iona l component to implement the behavior of each col;mn. with a full- subtractor having an input wi representing a borrow by the previous colum n. and an output wo representing a borrow from the next column. in addition to the inputs a and b and the output s. (We use w's for the borrows rather than b's becau e b is already used for the input : the IV comes from the end of the word borrow.) We leave the design of a fu ll -subtractor as an exercise for the reader.
EXAMPLE 4.1 9 DIP-switch-based adding/subtracting calculator In Example 4.8. we designed a simple ca/culalor Ihal could add IWO 8-bil bi nary numbers and produce an 8-bil resuli. using DIP switches for inpuls. and a regisler plus LEDs for outpUI. LeI' extend thai calculator to tlllow the user
(0
choose
311lo ng
addi tion and subtraction operations. \Vc'l!
introduce a singlc·swilch DIP switch that CIS a signal f (for "function") as another sy When f =0. Ihe calculator should add: when f ~ l. Ihe calcutator shoutd subtr:lcl. One illlplemcnlntion of thi s calculator would use an adder. a subtractor. and
3
(em
input.
multiplexor. as
in Figure 4.65. The f inpul chooses which component. the adder or sublraclor. 10 pass through the I11U X to (he register inputs. \Vhen the user presses e. ei ther the addition or subtrnclion result gets
loaded inlo Ihe regisler and displayed al Ihe LEDs. This example assumes the result of a subtraction is always It also assumes thm the result is always between 0 and 255.
:l
positive number. ne\"l~:r negathe.
192
4 Datap ath Compone nts
4.8 Subtractors
1
o
C M Y
CALC Figure 4.65 8- bil DlP-swi lchbased adding/subtrac tin g c"lcul mo r. Inpul f sc lecls between addition and subtraction.
EXAMPLE 4.20
I
193
Notice ~h at a color printer may have three color 10k cartri dges, one cyan. one magenla. and one yellow. Figure 4.66 shows th~ ink cartridges for a particular color pnnter. Some printers have a single cart ride:c for ~o l or i ~l s lcad of three. wi th Ihal single cartndge lIltemally contai ning separated nuid compartments for the three colors. A printer must convert a received RC B inKlge into CMY. Let's design a fas t circuit to perform th ut conversion. Given three 8-bit value s fa: R. C, and B for a part icular pixel. the equati ons for C. M. and Yare simpl y:
DIP switches
OOOOO.O'/ LEDS
Color space converter- RGB to CMYK
Computer moni tors. di gital cam era s. scanners, primers, and other electro ni c dev ices deal with color images. Th ose devices Lreal an image as millions of tiny pixels (short for "pi ctu re elemems"). wh ich are indi visible dots representing a tiny part of the image. Each pi xel has a color, so an image is j ust a collecti on of colored pixels. A good computer monitor may support over 10 milli on uni que colors fo r each pixel. How does a monitor create each unique color for a pixel? In a common meth od used in what are known as RGB monitors. the moni tor has three light sources inside-red, green, and blue. Any color of li ghl can be crealed by adding spec ific inlensities of each of th e three colors. Thus. for each pixel. the monitor shines a spec ific intensity of red. of green, and of blue at th at pi xel's locati on on th e monitor's screen. so th ai th e three colors add IOgelher 10 creale Ih e des ired pi xel color. Eac h subeolor (red, gree n, or blue) is Iypica ll y represented as an 8- bit binary number (thus each ranging from 0 to 255), meaning a co lor is represented by 8+8+8=24 bils. An (R. G, B) value of (a, 0, 0) represe ms bl ac k. ( la, 10. 10) re presenl s a very dark gray, while (2 00, 200, 200) represenls a li ght gray. (255, 0, 0) re prcse nlS red, whi le ( 100. 0, 0) represe nts a darker (noninl ense) red. (255, 255, 255) represenls while. ( 109, 35. 201 ) rcpresellis some mixture of the three base colors. Representing color lIsing intensity valu es for red. green. and blue is kn own as an RGB color space. ROB color space is great for compuler monitors and cert ain other devices, but not the besl for some other devices, like pri nters. Mixing red, green. and blue ink on paper will not result in white, bu t rather in black. Why? Because ink is not li ghl; ralhcr, ink re ReCis li gh!. So red ink refleClS red lighl, absorbing gree n and blue li gh!. Likewise, gree n in k absorbs red and blue li gh!. Blue ink absorbs red and green li gh!. Mi x all Ihree inks logelher on paper, and the mi xlUre absorbs olf lighl, re Recti ng none, Ihu s yielding blac k. Printers Ih ererore use a differenl color space based on th e compleme ntary colors or red/gree nlblue, name ly, cyan/magent a/ye llow, know n as a eMY color space. Cyan ink absorbs red, re Rectin g gree n and blue (Ihe mix ture o f whi ch is cya n). Mage nta ink absorbs green Ii ghl , re Reclin g red and blue (whi ch is mage ma). Ye llow in k absorbs blue, rcRecling red and gree n (w hich is yellow).
255 255 255
R G 8
(255 is the max imu m value of an 8-bi t number). A circui t to perform such conversion can be built using subtractors. as shown in Figure 4.67. Ac tua lly. Ihe conversion needs 10 be slighll y more co mplex. In k isn'l pcrrcci. meani ng that mixing cyan, magenta, and
Figure 4.66 A color pri nter mixes cyan. magenta. and yellow inks 10 create any color. The picture shows inside a color printer having those three colors ca n ridges on Ihe righ l. labe led C. M. and Y. Such pri mers may usc black ink direc ll y (Ihe big cnnridgc on the left). ru ther Ihan mi xing the three colors . to make gr:.Jys and blacks, in order to creale a better-looking black and to conserve the more e,xpcnsive color inks.
ye llowyields a black Ihal docs n' l look as black as you mighl cxpeCi. Funhennore. colored ink.s are expenSive c?l11.pared 10 black ink. Therefore. color printers use black ink whenever possible. One way 10 maX imize usc of black ink is to fac tor out Ihe black from the C. M. and Y values. In other words, a (C, M. Y) value or (250. 200. 200) can be Iho ughl of as (200. 200. 200) plus (50. O. 0).
>:2 u £2
"a: Figure 4.67 RGB
10
CMY converter.
Figure 4.68 RG B 10 CMYK convener.
1 9~
Datapath Components
4.8 Subtracters
The (200. 200, 100). which is i.I light gray. call be generated using black ink. Th e remaining (50, O. 0) can be ge nera ted lIsing a small amoun t of cyan. and u s ill~ no mage ~ll iJ or yellow ink at all , thus
savi ne. prec ious color ink . A CMY color :-.pace c.xtcnd ed with black IS knowll as a CA1 YK color spnce- (th e "K" comes from the last Jetlcr in the word "black'" " K " is used instead of " 8" 10 avoid confusion with the " B" frol11 " blu e"), An RGB to CMYK conver1er can thus be desc ribed ;1S:
K ~ Min imu m (C . M. Y) C2 C K M2 ~ M - K Y2
~
Y - K
where C. M. ;lnd Y are defi ned as ear lier. \Ve thus create the circuit in Figure 4 .68 for convening an 10 a CMYK color space. We've used the RGBloCMY component from Figure 4 .67. \,Vc've also used two in ~tance s of th e MIN component lhat we created in Example 4.12 to compute th e minimum of two !lumbers: using twO such components computes th e minimum of th ree numbers. Finally. we use three more subtractors to remove th e K va lue from the C. M, and Y va lues. In a rcal primer. th e imperfections of ink and paper requi re even more acijllsllneills. A more rea li sti c color space conve ner mult iplies the R. G. and B va lues by a se ri es of constants, whic h can be described using matrices:
RGB color space
I CI
I mOO mO 1 m02 I
I MI ~ Im l 0 mll m12
IYI
1*
Im20 m2 1 m22 I
I RI I GI I BI
We (/re illiroducillg l ell's
complell/em
jll SI
/or illllliliol/
purposes- we '1/ (lclltally be usillg 11\'0 's complemelll,
familia ri ze yourself with the concept. but bear in mind that the mtenll on IS to use complements in base two. nOt base ten. Consider subtraction invol ving two single-d igit base ten numbers, say 7 - 4. The result should be 3. Let' defin e the complem ellt of a single-digit base ten number A as Ih e m lm ber Ihal ,vhell added 10 A res,,/Is ill a S"III of lell. So the complement of I is 9, of 2 is 8, and so on. Figure 4.69 prov ide the complemen ts for the numbers I th rough 9. The wonderful thing about a compl emen t is that you can use It to p~rform subtraction uSing addition. by repl acing the number bemg subtracted with its complement. then by adding , and then by fin ally throwing away tJ,e carry. For example:
7 - 4 - ) 7 + 6 ~ 13 - ) t 3 ~ 3
195
1-9 2-8 3-7
4-6 5-5 6-4 7-3
8-2 9-1
Figure 4.69 Complements in bnse ten.
We replaced 4 by its compl emen t. 6, and then added 6 to 7 to obtain 13. Finally. we then threw away the carry. leav ing 3. wh ich is the correct re ult. Thus, we perforllled sub. lr(lCl fOli u Sin g
oddi/ioll.
complements
Further discussion of such a ma tri x- based converter is beyond th e scope of this exa mple.
Representing Negative Numbers: Two's Complement The subtractor design in the prev ious section ass umed we onl y dea lt with positi ve input numbers and positi ve results. But in many systems, we may obtain results that are nega· ti ve. and in fact. our input values may even be negati ve numbers. We thus need a way to represent negali ve numbers using bilS. One obvious but not very effecti ve representati on is know n as signed-magnitude. In thi s representation. the highest-order bi t is used only to represen t the number's sign, with o meaning positi ve and 1 mean ing negative. The remain ing low-order bits represent the magnitude of the number. In thi s representation. and using 4-bi t numbers, 0111 would represent +7. wh il e 1111 would represent -7. Thus, fo ur bits cou ld represent -7 to 7. (Notice. by the way. that both 0000 and 1000 would represent 0, the former representing O. the laller -0 .) Signed- magnitude is easy for humans to understand , but doesn 't lend itself easily to the design of simpl e arit hmetic components li ke adders and subtractors. For ex ample. if an adder's inpu ts use signed-magnitude represent ation, the adder would have to look at the highc t-order bit. and then internall y perform either an add ition or a subtraction , using different circuits for each. Instead . the most common method of representing negati ve numbers and performing subtraction in a digital system actually uses a tri ck th at allows u to lise (III adder 10 p elfo rm subtractiOIl . Using an adder to perform subtract ion would enab le us to keep our simple adder. and to u e the same component for both additi on and subtract ion. The kcy to performing subt racti on using addit ion li cs in what are known as comple· mellts. We' ll first inlroduce complements in the base ten numbcr system just so you can
7-4~3
Adding the complement results in an answer exactly 10 too much - dropping Ihe lens column gives the right answer.
Figure 4.70 SUbtracting by adding- subtracting a number (4) is the same as adding the number" complement (6) and then droppi ng the carry. since by definition of the complemenl. lhe result will be exactly 10 too much. Arter all . that's how the complement was defined- the number plus its complement equals 10. A number line helps us visualize why complement work. as shown in Figure -1.70. Complements work for any nu mber of digits. Say we want to perfonn ubtraction using two two-digit base ten numbers. perhaps 55 - 30. The complement of 30 would be the number that when added to 30 results in 100. so the complement of 30 i 70. - - + 70 is 125. Throwing away the carry yields 25. which is the correct result for 5: - 30. So using compl ements achieves subtraction using addition. "Not so fast! " you might say. In or ler to determine the complement. don't w{, have to perform subtraction? We know that 6 is the complement of 4 by computing 10 - ~ = 6. We know that 70 is the complement of 30 by computing 100 - 30 = 70. 0 haven't \\ e just moved the subtracti on to another step-the step of computing the complement'?
196
4 Datapath Components
Two'scomplemellr call he compllled s imply by ifli'erti"8 the bits and adding JIh llS al'o iding the
needior slIbrracrion Il'hen computing a complement.
Yes. Except. it lUms out that ill base two, we call compute rite complemel1{ ill a milch simpler way-jllsl by inverling all Ih e bils alld addillg J. For example, cons ider computi ng the comple ment of the 3-bit base- two number 00 1. The complement would be the number that when added to 001 yields 1000-you can probab ly see that the complement should be 111. Using the same method for compu ting the comple ment as we did in base ten , we compute the two's comple ment of 001 as: 1000 - 001 = Ill-so III is the complement of 00 1. However, it just so happe ns that if we inve rt all the bits of 00 1 and add 1, we get the same result! Inverting the bits of 00 1 y ields 110 : adding 1 yields 110 + 1 = I l l -the correct complement. Thus, to perform a subt raction, say all - 00 1, we wo uld perform the following : a ll - 001 - ) all + (( 001 ) ' +1 ) all + ( 110+1) =011+11 1 = 1010 (th rowaway the carry) - ) 010
The highest-order bit in two 's
complemem aClS
as a si8" bit: 0 means pOJilive, I mean.' negative.
That's the correct answer, and didn 't involve any subtractions-onl y an invert and addi ti ons. We o mi t di scussion as to why one can compute the compl ement in base two by inverting the bits and adding I -for our purposes, we just need to know that that trick works for binary numbers. There are ac tuall y two ty pes of complements of a binary number. The type we've been using above is known as the two 's complement, obtained by in verting all the bits of the bin ary number and adding 1. Another type is known as the olle's complemellt, which is obtained simply by inve rting all the bits, without adding a 1. The two 's complement is muc h more commonly used in digital circuits and results in simpler logic. Two's complement leads to a simple way to represent negati ve numbers. Say we have fo ur bits to represent numbers, and we want to represent both positive a nd negative numbers. We can choose to represent positive numbers as 0000 to a 111 (0 to 7). Negative numbers wou ld be obtained by taking the two 's complement of the positive numbers, because a - b is the same as a + (-b)' So - I wo uld be represented by taking the two's complement of 000 1, or( 000 1 ) '+ 1 = 1110+ 1 = 1111. Likewise, -2 would be (00 10) ' +1 = 1101+1 = 1110.-3 wou ld be (0011 ) ' +1 = 1100+ 1 = 1101. And so on. -7 would be (all]) '+1 = 1000+1 = 1001. Notice that the two's complement of 0000 is 1111 + 1 = 0000. Two's complement representation has on ly one representation of 0, namely, 0000 (unlike signed-magnitude representatio n, which had two re presentatio ns of 0). Also notice that we can represent - 8 a 1 000 . So two 's complement is Sligh tly asy mmetric, representing one more negative number than positive nu mbers. A 4-bit two's-complement number can represent a ny numbe r from -8 to +7. Say you have 4- bit numbers and you wan t to store-5 . - 5 wo uld be (0 101) '+1 1010+1 = 1011. Now yo u want to add -5 to 4 (or 0100). So we s imply add : 1011 + a 1 a a = 1111, which is -I-the correct answer. Note that negati ve numbers all have a 1 in the highest-order bit; thu . the highestorder bit in two's complement is often referred 10 as the sign bit, a indicating a positive number, 1 a negative number.
4.8 Subtractors
197
If yo u Want to know the n . d f' . . . I ag nuu e a a two s complement negatIve number, you Can obtall1 the mag Dl tude by ta ki ng the two's complement again. So to determine what number 1111 represents, we can take the two's complement of 1111 : (1 111 ) ' + 1 = 0000+1 .= 000 1. We put a negative sign in front to yield -0001, or-I. . A qUI ck way fo r humans to mentally figu re out the magnitude of a negative number ln 4-bn two's comple me nt (having a 1 in the high order bit) is to subtract the magnitude of the three lowe r bits from 8. So for 1111 , the low three bits are 111 or 7, so the ma o nnude IS 8 - 7 = I, which in -tu m means that 1111 represents _ I. For an 8-bit two':s comple ment number, we wou ld subtract the magnitude of the lower 7 bits from 128. So 10000111 would be-(128-7) = - 12 1. . To sum,,:,ari ze, we can represent negati ve num bers using two's compleme nt representall on. AddulOn of two's complement numbers proceeds unmodified-we j ust add the num bers. Even if one or both numbers are negati ve, we simply add the numbers. We perform subtractIon of A - 8 by taking the two 's complement of 8 and then adding that two's complement to A, res ulting in A + (- 8) . We compute the two's complement of 8 by simply inverting the bits of 8 and then adding 1.
Building a Subtractor Using an Adder and Two's Complement With knowledge of the two's compleme nt representation, we can now see how to subtract using an adder. To compute A - 8, we compute A + (-8) , which is the same as A + 8 ' + 1 because - 8 can be computed as 8 ' + 1 in two's complement. Thus, to perform subtraction, we inve rt 8, and input a 1 to the carry- in of an adde r, as shown in Figure 4.7 1. Figure 4.71 Two's complement subtrac tor buill with an adde r.
Adder/Subtractor We can straightforwardl y design an adder/s ubtractor component, havi ng an input sub , such that when s u b= 1 . the compone nt subtracts, but when sub=O, the component adds, as shown in Figure 4.72(a). The N-bit 2x I multipl exor passes 8 when sub=O. and passes 8 ' when sub=l. sub is connec ted to C in also, so that c i n is 1 when subtrac ting. Actually, XORs can be used instead of the inverters and mux , as hown in Figure 4.72(b). When sub=O, the output of XOR equals the other input 's value. Whe n sub=]' the o utput of the XOR i Ihe inverse of the other input's value.
b7
sub
b6
.:t E:ft\SUb , ..
IvY' \~ ... _----- ..,,/ adder's B inputs (b)
Figure 4.72 (a) 1\1'0'5 complement adderl ubtrn tor using a I11UX. and (b) allemative circuit for Busing XOR gate.
198
4 Datapath Components
EXAMPLE 4.21
4.8 Subtractors
DIP-swltch-based adding/subtracting calculator (continued) Let's revisi t our DIP-switch-based 3dding/subtfaC ling calculator of Example 4. 19. Ob ervc Lhat at any ojvcn lime th e OlilpUI displays the results of either the adder or subtraclOr. ,but ,never both
Simultnncou~ly. · Thus. we rca ll y don', need both an adder and a. sublraclOf ~peratmg
In parallel; instend. we can lise a single adde rlsubtraClOr component. ASS UI1lI~lg DIP swltc.hes have been set, setting f ""0 (add) verMIS f 3 1 (subtract) should result in th e followlIlg computations:
00001111 + 00000001 ( f~O ) 00010000 00001111 - 00000001 ( f~l) ~ 00001111 + 11111110 + 1 00001110 \Ve achieve thi s simply by co nnecting f 10 (he 5 u b input o f th e ~ldderls ubtraclor. as shown in
Figure
~ . 73 .
DIP switches ~------~~
~~~------
Figure 4.73 S-bil DIPswilch-based adding! subLracting calcula tor. using
an adder/s ublractor and
two 's complement number representation. Le('s consider signed numbers using (Wo's complement. If the user is unaware tha t two's com. plement represcntation is bei ng used and the user will only be inputting positi ve numbers using the
DIP witches. Ihen Ihe user should only use Ihe low-order 7 swi lches of the 8-switch DIP inputs, leav ing the eighth switch in the 0 position. meaning the user can only input numbers ranging from
0 (00000000) to 127 (0111 I Ill). The reason the user can'l usc the eighth bit is that in two's
199
binary. We can eas ily detect overfl ow when adding two binary number simply by 100kll1g m the carry-out bit of the adder- if the carry-out bi t is 1. overflow has occurred. So a 4-bl t adder adding IIII + 0001 would output 1 + 0000. where the 1 is the carry out-i ndicming overflow. When using two's com plement numbers, detecting overflow is sign bits somewhat more complicated. 1 1 1 1 1 0 0 0 Suppose again we have 4-bi t ~o 0 A:Jooo ~111 numbers but now those numbers are in two's complement form . Con(j)ooo @11 1 (j) 1 1 1 sider the additi on of two posi ti ve overflow overflow no overflow (a) (b ) (c) numbers, such as 0111 and 000 I If the numbers' sign bits have the same value. which in Figure 4.74(a). A 4-bi t adder differs from the resuWs sign bit, overflow has occuned. wou ld ou tput 1000, but that is incorrect-the result of 7 + I should Figure 4.74 Two's complemem o'erflow be 8, but 1000 represents -8 in detection comparing sign bits: (3) when adding two po itive numbers. (b) when adding {Wo two's complement. The problem is negative num bers. (c) no overflow. that the largest positive number we can represent in 4-bittwo's complement form is 7. Thus, when adding two positive num bers. we can detect O\'erflow by checking whether the most significant bit is a 1 in the result. Likewise, consider the add it ion of two ne£ati ve numbers. such as 1111 and 1000 in Figure 4.74(b). An adder would output a sun~ of 0111 (and a caIT) out of 1). 0111 i incorrect: - I + -8 should be -9. but 0111 is +7. The problem is that the mo t negative number we can represent with 4-bit two' complement i -8. Thus. when adding two negative numbers. we can detect overflow by checking whether the mo t ignificant bit is a a in the result .
(0\
r;\
rl
Notice thaI adding a po itive with a negative. or a negative with a positive. can never result in overflow. The result wi ll always be less negati"e than the moot negati\e number. or less positive than the most positive number. For example. the extreme i the addition of -8 + 7. which is - I. Increasing -8 or decreasing 7 in that addition still re ults in a number between -8 and 7.
Detecting Overflow
So detecting overflow in two's complement iovo" es detecting that both input numbers were positi ve but yielded a negative result. or that both input numbers were negative but yielded a positive result. Restated. detecting overflow in 1\\0' complement involves detecting that the sig n bit ' of bOlh inputs are the same as one another but differ from the result 's sign bit. If we call the sign bit of one input a and the . ign bit of the other input b. and the sign bit of the result r . then the following equllti n outputs I \\ heo there is overflow:
When we perform ari thmetic using binary num bers of a nxed bit width . sometimes the result i, wider than the fixed bitwidth, a si tuation known as overflow. For example, can. ider adding two 4-bit binary numbers (just regular bi nary numbers for now, not two's complement numbe,,) and storing the result as another 4-bit number. Adding 1111 + 0001 yields a re_ult of I OOOO-a 5-bit number. which i, bigger thnn the 4 bi lS we have to store the re, ult. In ot her words. 15 + I = 16, and 16 require 5 bi" to repre em in
Although the cireuit implementing the above o\t'fflO\\ del'ction equation is quit simpl e Hnd illluiti vc. we cun cre:tte an e\en simpler circuit if our adlkr gen r:uc!\ 3 1Oa~· ou t. The simpler method merel) ompare ' the can, into the 'Ign 1>11 alumn \\ ith the arry out of the sign bit column-if the calT) in allll ';In, (lut dlll>r. \)\emo\\ h < occurred.
complement representation. making the highest-order bit a 1 causes the num ber to represe nt a negative number. If the uScr iii aware of two's complement, then the user could use the DIP switches to represent
negative number too. from - I (1111111) down 10 - 128 (10000000). Of course. the user will need to check Ihe lefimoSI LED 10 delerminc whclher Ihe ou tpul represent. " posilivc number or a negali ve number in two's complement form .
-----_.._---
ove rflow - abr ' + a'b'r
200
Datapath Components Figurc
4.9 Arithmetic-Logic Units-ALUs 4.75
illustra tes
this
0 0 0
1 0
method for several cases. In Figure
4.75(a). the carry into the sign bi t is l. whereas the carry out is O. Because the carry in and carry Oll t difTer. overflow has occurred . A circuit detecti ng
+ 1 0 0 0
+0
ot
10
0 1 no overflow (e)
0 0 0 overflow
overflow (b)
4.9 ARITHMETIC-LO GIC UNITS-ALUS
0 0
+0 0 0
(a)
whe ther two bits dirfer is j ust an XO R gatc. which is slightly simpler than the ci rcuit or the previous mcthod. We om it discussion as 10 why thi s Illctilod
0 0 0
1
An N-bit adthmetic-Iogic ullit (A LU) is a datapath component able to perfonn a variety of anthmellc and log ic Operations on two N-bit wide data inputs, generating an N-bit data o utput Example arithmetic operations incl ude addi ti on and ubtraction. Example logic operallons .'"clude AND, OR , XOR. etc. Control inputs to the ALU indicate which panicular operatIon to perfonn . To unde rstand the need ror an ALU component, consider Example 4.22.
" the carry into the sign bit column diffe rs from the carry out of that column. overflow has occurred.
Figure 4.75 1\\lo's complement overflow detec ti on comparing carry into and out of the sign bi t column: (a) when adding two positive nu mbers. (b) when adding two negative numbers. (c) no overfl ow.
works. but laoki ne: at the cases in
Figure 4.75 should help prov ide the intuiti on.
EXAMPLE 4.22
Multi-function calculator without using an ALU LeI's extend our earlier DIP-switch-based calculator to sUPPOI1 eight operations. determined by a three-switch DIP switch that provides three inputs x. y. and z to our system. as shown in Figure 4.76. For each combi nation of the three switches. we want to perform Lhe operations shown in Table
4.2, on the S-bit data inputs Aand B. generating the S-bit output on S. TABLE 4.2
~ WHY SUCH CHEAP CALCULATORS?
then you need to add $1.000,000 to the se lling price or thai chip if you wanl to break even (meaning to recove r your design and setup COSlS) when you sell the away for free by many companies selling something chip. Ir you plan to produce and sell 10 such chips, else. But a calculator internally contains a chip then you need to add S 1.000.00011 0 = $ 100.000 to the implementi ng a digital cireu i!. and chips nomlally selling price of each chip. Ir you plan to produce and arcn '{ cheap_ Why are some cnlcu l:uors such a sell 1.000.000 such chips, then you need to add only bargain? S1.000.00011.000.000 = $ 1 to the selling price or each The reason is known as economy of scale. which chi p. And if you plan to produce and sell 10.000.000, means that products are often cheaper when produced you need to add a mere $1.000.00011 0.000,000 = in large vol umes. Why? Because the design and setup 50. 10 = 10 cenlS to the selling price or each chip. Ir costs can be amonized over larger numbers. Suppose it the actual raw materials only co t 20 cenlS per chip, cOSIS S 1.000.000 to design a CUSlom calculator chip and you add another 10 cents per chip for profit. then I and to setup the chip's manuracturing (not so can buy the chip from you ror a mere 40 cents. And [ unreasonable a number}----design and setup costs are often caJJed nonrecurring engineering. or NRE. coSIS. If you plan to produce and sell one such ch ip.
can Lhen give away such a calculator for free, as many
companies do. as an incentive ror people to buy somethi ng else.
/
Display
--_
... _-_.
Desired calculator operations
Inpu ts
Se\'eral earl ier examples dealt with designing simple ca1culators. Cheap caJcularors. costing less than a dollar. are easy (Q find . Calculators are even given
Chip (covered)
Battery
201
X
Y
Z
0
0
0
0
0
0
0
0 0
0
0
0
Operation
Sample output ir A=0000 Illl, B-OOOOO 10 I
S-A+B
5=00010100
5=A-B
S=OOOOIOIO
S=A+ I
5=00010000
S=A
5=000011 II
S = A AND B (bitwise A D)
S=OOOOO 10 I
5 = A OR B (bitwise OR)
5=00001111
S = A XOR B (bitwise XOR)
S=OOOOIOIO
S= OT A (bitwise complement)
S=I II 10000
The table includes several bitwise operations (AND. OR. XOR. :Illd complement). A biI>. Furthermore. every operation is computed all th~ nme. \\hh..~h \\asfes power. hmlgi nc instead that \\c were dealing nOt with -bit numbel'$. but in~tead \\ ith 3~-blt numbers. and we wanted to suppan not just operations but 3_ opernuons. Then \H~ \\ould hJ.\ C!\ n morc wires (32*32 = 1024 \drc~ at th~ I1lU\ inputs). and e\en more po\\cr n!>umpu\'In. Funhermore. a 3:!x I lIlU~ \\ ill rcquir'l:' sc\cral I~, els of I!ntes. be,,~a use du ~ to pr.t ~t1 .... al ~~ "'ns. d 3~-inpu( logic gate (insid~ the IllU\) \\ill li"-cl) n':c.!d to'" be implemented U~lOg ,~'~rn.1 I~\ -I, ('If ... mall r logic £u t c~.
202
4 Datapath Components
4.9 Arithmetic-Logic Units-ALUs DIP swilches
,..---=-=-=-=-=-="
1
o
I.-- - - - -yo
203
control inpul.~ x. y. and z. such that the desired arithmetic or logic result appears at the adder s output. The AL-extellder actu ally consists of eight identical components labeled abext. one for each pair of bits a i and b i . as shown in Figure 4.77(b). It al so has a Component cillext to compute the c i n bit.
OODDDOOB 8
Thus. we need to design the abext and cillex t components to complete the ALU design. Con ider the fi rst four calculator operations from Table -1.2. wh ich are all arithmetic operations: Wasted power
When xyz=OOO . S=A+B. So in that case. we want IA=A. 1B=8. and ci n=O. When xyz=OO l, S=A - B. So we Want 1A=A . 18=B ' . and ci n= 1. When xyz =O1O. S=A+ 1. So we want 1A=A. 1B=O. and c i n=1. When xy z =O ll, S=A. So we want I A=A. IB =O. and cin=O .. Olice that A will pass through the adder. because A+O+O =A. The last four ALU operations are all logica l operations. We can compute the desired operation in the abext component. and input the result to 1A. We then set 1B to 0 and cin to O. so lhat the va lue on 1A passes th rou2h the adder unchan2ed. One possible design of abext pl aces ; n 8x I mux in front ~f each output of the abexr and cillext components. wilh x. y. and z as the select inputs. in which case we would set each mux data input as described above. A more efficient and faster de ign would reate a custom circuit for each component output. We leave the completi on of the internal design of the abe rt and cillext components as an exerci e for the reader. Examp le 4.23 redesigns the multifunction calcul ator of Example -I.n . this time utilizing an ALU.
CALC
Fig ure 4.76 -bit DIP-switch.based multifunction calculator. using
separ.lIe components for each function.
We saw in the above example that using sepamte components for each operalion is not effi cient. To solve the problem. we observe lhat the calculator can only be configured to do One operation at a time. so there is no need to compute all the operallons III parallel as was do ne in the example. Instead. we can create a slllgle component (an ALU) that can compute any of the eight operati on . Such a component would be more area and power efficie nt. and would have less delay because a large mux woul d nO! be needed. Let's stan wi th an adder a our ba e internal AL design. To avo id confusion. we'll call the inputs to the internal adder 1A and 1B. shon for " internal A" and "interna l B.': to di ~ti ngui s h lhose inputs from the ex ternal ALU inputs A and B. We stan \YlIh the deSign shown in Figure 4.77(a). The ALU consists of an adde r. and ~o l11 e logiC III fro nt of the adders inputs. We' lI ca ll lhat log ic an arithmeticfl og ic extender. or IIL-extellder. The purpose of the AL-extellder is to et the adder inpu ts based on the values of the ALU's a7 b7
a6 b6
la7 ib7
la6 1b6
Figure 4 77 Arnhmetlc- Ioglc unll' de\lgn ba",d on a \I ngle
adder with an anthmcllc/Joglc
Multi-function calcu lator uSing an ALU Example 4.22 bui ll an eighl· funclion calculmor \\ ithoUl an AL . The result \\ as W:bled area and power. complex wiring. and long deja) . sing the abo\ c-designed ALL', the akulJ.mr could in lOtcad be built :IS shm\ 11 in Figure 4.78. I otice the simple and efficient de~ig n.
aD bO
la) AL
extender. dnd IOJ drnhmClltlloglc «Icnder detail
EXAMPLE 4.23
Flgur. 4.78 S-hlt DIP(b)
, \\ ih:h-hn, cd mull! calcuhuor. nn ALU
flllll' llOn
U'll1g
4 Datapath Components
4.10 Register Files
410 REGISTER FILES An MxN register file is a datapalh memory component that prov ides effic ient access to a
collec ti on of AI registers. where each register IS N blls Wide. To .understa nd the need for a regis te r file component in building good datapaths. rather than JlIst uSll1g M separate regist~rs. consider Exa mple -1.24 .
EXAMPLE 424
-+
Above·mlrror display system uSing 16 32·bit registers Recall the above-mirror display syslem rrom Example 4.4. Four 8-bit r~g i st e~ were m~lIiplexed to all S-bil OUlpUt. Suppose imacad that the sys tem required sixteen 32-blt registers: to display more va lues. c3ch of more precis ion. We wou ld therefore need a 32-~ it -\~ id~ 16:< I mulllP.lexor, ~ shown in Fif!ure . t 79. From 3 purely digital log ic perspective. Ihe deSign ISJust fin.e. BUI In pra~ lIce, that mu ltiplexor i~ \'cry incfli cicnl. COllnt the number of wires that would . be fcd Into that multlplexor16:<12 = 511 wi res. That's n 101 of wires to Iry 10 route from the rcguers to the I1lUX~s-lry plugoin!! 5 11 wires into the back of one stereo system for a hands-on demonstration. HaVing too many i;;;~ in a small area is known as cOllgestioll .
:
~iO " E
., 0
~~ ~
u..ec Q)
"
4x 16
4 13'10
o
e load
co~ponent having a si ngle N-bit wide data inpul. and a si ng le N-bit wide data outpuL The wlfmg mSlde the component is done carefully to handle fanout and congestion. Figure 4.80 shows a block symbo l of a 16x32 register file ( 16 registers. each 32-bits wide). . Consider writing a value to a register in a reg32 32 Ister fi le. We would place the data to be written on the input W_ data. We then need a way to indicate A_data """':'which register we actually Want to write. Since A_addr there are 16 registers, we need four bits to speci fY a panicu lar register. Those four bits are called the A_en _ registe r's address. We wo uld thus write the desired regi ter's address on the input W_ add r . For example, if we wanted to write to register 7. we wo uld set W_addr~Oll1. To indicate that we actually Want to write on a panicular clock cycle (we won' t want to wri te on every cycle). we would set the input W_en to 1. The coUection of inputs W_ da tao W_add r. and W_en i known as a register file' wrile port. Reading is similar. We would pecify the register to read on input R_addr. and set R_en~ 1. Those valJes would cau e the register file to output the addressed regi ter contents Onto outpu t R_data. R data,R addr.and R en are known as a re.n terfile' read port. The read pon and writ; pon are i ndependent ;;f one another. Thus. during the same clock cycle, we can write to one register. and read from another (or the same) register. Let 's consider how to internally design a register file. For simplicity. con ider a 4 x 3_ register file. rather than the 16 x 32 register file described above. One internal design of a 4x32 register fi le is shown in Figure 4.81. Let's consider the circuitry for writing to this register file, found in the left half of the figure . If W_en~O. the reg; tcr file \\ on't write fO any register, because the write decoders outputs will be aliOs. If W_en~ I. then the write decoder decodes ~Ca dd r and sets to 1 the load input of exactly one regi ter. lllat register will be written on the next clock cycle with the value on W_data.
32
W_data
32 + - -...,...'-___ .....___--,
d
figure 4 79 Above·mi rror display design. ass uming sixt ee n J2. bit registers. The mux has too many input wires . re~ulli ng in conge~lio n . Also. the data lines C arc fanned out to too many regj~ters. re~u ltin g in weak current. Likcwi\e. consider routi ng the dala inpUlto all c;; ixtccn rcgi~tc~. &Ich data input wire is being branched inlo ,ix tccn ~u bw irc,. Imagine electric current being Iikc a ri ver of waler- branching a main river inlo ~ i x tccn smaller rjver~ will yield much le~, waler now in each c;maller river than in the main river. Likcwj~e. branChing a wire. known a}. jallolli . can only be done so many times before lhe branched wires' current~ arc 100 \ mall to ~ umcicnt l y conlrol l r.lO ~i,tors . Furthennore. low-c urrent wire, may be very 'low altOio. '0 fa noul can crea te long delayc; over wires too.
The fanout and congestion proble ms illustnllcd in the prev i u< e nmple nn be solved by ob,ervi ng that we never need to load more Ihan one regi~ter (It a lime. and lhal we never need 10 read more than one re!p~ter al a lime ei lhe r. An M N rcgmcr foIe
2x4
iO it d wnle decoder d
e
4x32 register "ie
206
Datapath Components 4.10 Register Files Notice the circled I ri~ n g ul a r one-input one-output
d
compone nt placed on Ihe ICda ta line (there would a ILIally be 32 such components since ICda ta is 32 blls Wide).
q=d
That component i ~ "'-flown as a drirer. so mc l~me~ ca lled a
(a)
bllffer. illU'1r3!ed in Figure 4.82(3). A dnver S OUIPUI equals it, input. but the OU IPUI is a stronger (higher current) ,i~ nal. Remember the fa nout problem we desc nbed III E;amplc -l.2-l? A drive r reduces Ihe fanout prob lem . In Fi2ure -l .8 1. the IC da ta lines only fan out to twO registers before Ihey go Ihro ugh the driver. The driver's OUlput then fan~ ou l to on ly IWO morc registers. Thu s. inslcn d of a
e= l : q=d d - q e=O: q='Z' d- ; - q like no conn~ction (b)
Such componem s ore more commnnl\' J..nOh ll 0\ . tn-sla te
dnn:rs rtflher
than' three-stote."
But "tri-state" a registered trademark of If
VOl/ollal
SemlC:ondu({or
Corp .. fO rother than pUllln ~ the requITed (rademarJ.. Hmbol
aJlu t"\ er;. ~se of lhe lerm UaU.
"frI-
man,\
documenH 11ft' the term rh"l'-\lClle
ranout of four, Ihe H_da ta lines have a ranout of only two (actually three if you count the driver itself). The inserti on Figure 4.82 (a) driver, (b) of drivers is beyond the scope or Ihis book. and is inslead a Ihree-Slale driver. subjeci ror a VLS I design book or an advanced digital . . desi2n book. But secinc at least one exam ple of the usc of a dnve r hoperull y gives you an idea-or one reason wh; a register file is a userul component-the component hides the complexity or ranou l rrom a designer. . To under;tand Ihe read circuiuy. you must fi rst understand Ihe behaVior or another new componelll thai we've illlroduced-the triangular component having two inputs and one output. That component is known as a three-Slate driver or three-state bllffer, Illustrated in Figure -l.82(b). When the control inpul C is 1. th e component acts like a regular driver-the componen t's out put equals its input. However, when the control inpu t c is 0, the driver's OUIPUI is neither D or 1. but instead what is known as hi gh-impedance, written as 'Z'. High-impedance can be thought or as no connection at all between the driver's inpul and output. '"Three-stale" means the driver has three po, ib le ou tput tates-D, 1, and Z. Let's now consider the circuitry ror reading rrom the register file. round in the right hall' or Figure 4.81. II' R_en=D . the regisler fi le won 't read rrom any register, since the read decoder's ou tputs will be all Ds, meaning all the three- ~ tate drivers wi ll output Z's, and thus the Outpul R_da ta wi ll be high-impedance. II' R_en-1. then the read decoder decodes R_addr and scts to 1 the control input or exactly one three-Mate driver. which will pa s ilS register val ue through to the R_da ta output. Be awarc that each shown th ree-state drive r actually repre,en ts a set or 32 three,tate driver>. one ror each or the 32 wires coming rrom the 32-bit rcgi~ters and going 10 the 32-bit R_da ta OU lput. All 32 drivers in a ,el arc controlled by Ihe same contro l input. The wi res red by the various three-Mate driver', arc known a, a bllS, as indicated in Figure 4. 8 1. A bus is a popu lar alternative to a multiplexor when each mux dala input i~ many bllS wide and/or when there are many mux dma inputs. becau e a bus result; in les, congestion. Notice that Ihe regi ster file design ,cales well to larger numbe" or registen. The write data 11I1e, can be driven by more drivel'\ If nece "ary. The read data line arc red rrom three-state drivers and thu, there " no congc'l1on at a single multiplexor. The reader may wi sh to compare the rcg"ter file de Ign In Figure 4. I with the de\lgn In hgure 4.6. which was c"cntially a poor dcslgn or" regi\tcr file .
- - ---_.-
. Figure 4:83 provides example timing diagrams describing wriling and reading or a regIster fi le. Dunng cycleJ, we do not know the contents of the register file. so the register file's contents are shown as "?" DUring cycle J, we set W_d ata =9 (in binary. or course). H_addr=3, and W_e n=l. Those values cause a write of9 to regisler file location 3 00 the first clock edge. Notice that we had set R_en=D. so the regi ter file outputs nothing ('T). and the value we put On R_addr does not matter (the value is a "don't care", written as "X"). elk
2
3
~
W_dataX
Gtx
X
w_addrX::=:::t ;
W_en}
: 1
-:
i
;:::..
R_data >
Z
R_addr(
X
i
X
i'
Z
'
I
i
,
5
i~ X; ~~::3±==
I
:
~
I
:
I.
,
Z~
!X21X I
4
X
! \~
\3
~ I
I
i
i k'
L'
,
I
3
i
.1
I'
I
! I
I
~:~? I~:~? i~:.:~ i~:;? i~:;? i~:I? i ~!!~
2: ? 3: ?
! 3:
:I 2: ? 9
i 3:
:I 2: ? 9
I 3:
I
,
,
t 2:
,
? 9
:I 2:
i 3: •
? 9
:I 2: 177 2. 177 : 3: 9 11 3.j 555 •
Figure 4.83 Writing and reading a regisle, fi le. Duri ng cycle2, we setICdat a=22. W addr=1. and W en= . These values ause a wri te or 22 to register file location I on c1~k edge _. During cycle3. we et W_en=D. so then it-doe n't marter to wbat valu \\e set W_data and W_addr. We also set R_addr=3 and R_en= 1. Those "alues use the reg_ ister file to read out the contents or register file location 3 0010 R_da a. ausing ~_ a:c to output 9. Notice that the reading i not yn hronized to cI k ed~e changes soon after R_en becomes I. Examinin2 the desi2n or Fi2ure -l. I hould make clear why reading i not synchronous- etting R_en t; 1 simpl~ enabl the output decoder to turn on one set or the three-state buffers. During cycle-l. we return R_en to D. Note that this cause me ", 3gtllD. During cycle5. we Want to simultaneously" rite and read the regi ter iile. We read locati on I (which causes JLda a to be ome ~_) while simultanrou -l~ writing 1 ati 02 with the value 177. Finally. during cy le6. we want to simultan usl~ read and 'Hite the : me register fi le location. We set R_addr=3 and R_en-l. causing I ation 3'< contenl'> fQ to appear n R_da a sh rtll' after setting those '-:llues. We also set W.3 .Q3t3 =...:S. llld W_ en-1. On clock edge 6. 5:5 thu. gets ,tored into localion.1. :\ou clock edge. R. da a abo changes to :55. TIle ability t simultnneou\l~ read and " nte locations cf J regl,ter til. , n the • ution. i ' a "idel) u,ed feature of regbter fiie>. The ne\ t e\ .ullple m e, \I> l fth.it fe lUI\".
208
4 Datapath Components
EXAMPLE 4.25
4.13 Product Profile: An Ultrasound Machine
E)..;}mple 4.4 used four S-bil registers for an above-mi rror display SYMC I~l . Example 4.24 extended the system to use sixteen 32-bi t regi sters. resulting in ranOl~t and c onges~loll problems. \Ve can redo that ~x ample using a reg ister fi le. The design is shown in Flgu~e 4.84 . 5 11lcc ~he system a"~~ys OUtputs one of the register va lues to the display. we ti ed the R_ en Input to I . Not ice that the wn ung and reading of panicular regi sters are independent of one another.
figur.4.84 Above·mirror display design. using a register file.
16x32
':": ~'I
register lite
-
1
RA
A register fi le having one read pon and one write pon is sometimes referred to as a dual-ported regisrer file. To make clear that the twO pons consist of one read pon and one write pon. such a register fil e may be referred to as follows: dllal·porred (I read, I write) register file. A register file may actuall y have just one pon, which would be used for both reading and writing. Such a register file has only one set of data lines that can serve as inputs or outputs. one set of address inpu ts. an enable input, and one more input indicating whether we wish to wri te or read the register file. Such a register file is known as a sillgle-ported register file . Multiported (2 Read, 1 Write) Register File. Many regi ster fi les have three pons: one write port , and two read ports. Thus. in the same clock cycle. two registers can be read simultaneously. and another register written . Such a regi ster file is especially use ful in a microprocessor. since a typ ical microprocessor in. truction ope rates on two reg ister and stores the resu lt in a third register. like in the instruction "RO
Th~ I ',,~
mml ",) rt f rnm on 0
r~~lffn fil~ In
pmdulf
Mat'
(I
fO
r"ul ptJ rt f and 5 lot
rift' {J'J r lf
Ul9
4.11 DATA PATH COMPONENTTRADEOFFS (SEE SECTION 6.4)
Above· mirror dis pl ay system using a 16x32 register fil e
Other Register File Varia/iOtls. Register files come in all sons of configurations. Typi cal numbers of registers in a regiMer fi le range from 4 to 1024. and typical register widths range from 8 bi ts to 64 bits per register. but ~ i/e, may vary beyond those mnges. Regi ters fil es may have one pon . two pons. three pons . or evcn more. but increasing to many more than three pons can slow down the rcgbtcr filc'~ perf0n110nCC ~lDd incrca c its ~ i l.e signifi cantly. due to the difficulty of routing olllhose wires around in,ide the regi ter file. Nevenheless, you' lI occasionally run aero" rcg i'lcr liIe, with perhops J wri te ports and 3 rcad pons, when concurrent access IS cflti co l.
For each datapath component that we introduced in previous sections. we created the most basIc and easy-to-understand implementation. In thi ection. which physically appears in the book as SectIon 6.4, we describe alternative implementations of several datapath components. Each alternative trades off one design criteria for another-most of those alternatIves trade off larger size in exchange for less delay. One use of this book covers those alternatI ve Implementations immediately after introducing the basic implementations (mean ing now). Another use of the book covers those alternative implementations later. after shOWing how to use datapath components during register-transfer level design.
4.12 DATAPATH COMPONENT DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES (SEE SECTION 9.4) Thi s secti on, which physically appears in the book as Section 9.4. shows how to use HDLs to describe several datapath components. One use of the book describes such HDL use now, wh ile another use describes such HDL use later.
4.13 PRODUCT PROFILE: AN ULTRASOUND MACHINE If you or someone you know has ever had a baby, then you may have seen ultrasound images of that baby before he/she was born. like the images of a fetu . head in Figure 4. -(a).
figure 4.85 (a) Uhrasound image of a fetus. created using an ullrnsound devi e lhat is simply placed on the mom's abdomen (b) and lhm fonns the image b~ gc ncrn ting sound waves and listening to the t.~hoes.
Pholos coune y of Philips ~l edica1 )Slems. That image wasn't taken by a camem omt'how in. ned into th uteru" Nt r:uh r ~ an ultrasou nd machine pressed against the mom 's skin :md pointed to\\ ,mI th f tlL.<' Ullrasound imaging is now common prJctice in ob ·terri · - Illainl) helping d.: ·tl . t" truck the fetus' progres, and om t potential probl ms earl). Nt aI . ... );1\ 11\£ nl:- a huge thrill when the get their tirst glimpse of their bab) 's h' ud. h:md..... :md lint f 't'
1 10
4
Datapath Components
4.13 Product Profile: An Ultrasound Machine
Functi onal Overvie w
Real designers mllsl often lean!
This section brieny describes the key func tional idea, of how ullra ound imagi.ng work . Digital de,igners don't typica lly work in a vacuum-in>tead. they a l~pl y their skills to par· ' ~'Ind thus designers typically learn the . -I ar ..lpp I~" lieu I(;~l t'Oll I S. _ . .key functIOnal Ideas underlY . . lllg tho,e application,. We therefore inlroduce you to lh ~ basIc Ideas of ult rasound appitcatlons. Itra,ound imaging works by sending sou nd waves IIlto the body and itstelllng to the echoes that return . Obj~ct; like bones yield difTerent echoes than objects like ski n or nU ld , so an ullrasound machine processes the different echoes to generate Images li ke th ~se III FIgure -I.85(a)-strong echoes might be displ ayed as white. weak ones as black. Today . ultrasound machines re ly heavi ly
0/1
rast
d i gi t~1I
circuits to generate the sounds waves, li sten
10
the
echoe,. and process the echo data to generate good quality images in real lime.
Figure 4.86 Ba.:;ic components of an Ullr'JSound machine.
Figure -1 .86 illustrates the bas ic pan of an ultrasound mac hine. Let's discuss each pan individuall y. Transducer A lrallsdu cer convens energy from one form to another. You're cena inl y fa mi liar with one type of tran sducer. a te reo speaker, wh ich convens electrical energy into sound by changi ng the current in a wire. which causes a nearby magnet to move back and fonh, which pushes the air and hence creates sound. Another familiar tra nsducer is a dynamic microphone. which convertS sound into eleclrica l energy by letting sound waves move a magnet. which induces current changes in a nearby wire. In an ult rasound machine, the lransducer conven> eleclrica l pulses into sound pu lses. and sound pu lses (lhe echoe ) into electrica l pul ses. but the lranducer u!.es piezoe leclric cry.. tab inMead of magnets. Applying electric current to such a crystal cause .. the cry'tal to change ,hape rn pidly, or vibra te. thus generating sound waves-typically in the I to 30 Mcg"hert l frequency range. Human.. can't hea r much above 30 ki lohenl- thc term " ultrasound" re fers to the fact that the frequency is beyond human hearing. Inver,ely. ,ound wave, (echoes) hitting the crystal create electric current. An ultrasound machine', tr:l n,duccr component may contain hundred .. of , uch crYMal,. which we ca n thin~ of ;" hundred, of t",n;ducer.;. Each ,"eh tran,ducer i.. con.. idered to form a challl/ci. Bea mfo rmer A heamform er elel/rfill/ClIIII' "focu,c," and "qeer," the 'OIlI1d beam of:1I1 amy of lllln . duce" to or from panicul,,; foca l poinL'. without ac tually mO\lIIg.ln hardware like 3 d"h to obtall1 \lIch focu .. lI1g and .. teen ng.
abolll ,he doma;"
for which 'he)' will deSign, Mall)' designers cOllsider such
leam ing about domains. like II ltrasoul/d, as olle
of 'he !ascillmillg fea tures of Ihe job.
211
To understand the idea of beamforming. we mUSl first under Land the idea of additive sound . Consider two loud fi reworks exploding al the same lime. one I mile away from you, and the olher 2 miles away. You' ll hear the clo er firework after about 5 secondsassum ing sound travels 0.2 miles/second (or I mile every 5 seconds)--a reasonable approximation. You'll hear the fanher fi rework after about 10 second . So you'lI hear "boom ... (five seconds pass) ". boom." However, suppose instead that the closer firework ex ploded 5 seconds later than the fanher one. Then you'lI hear both at the ame timeone big "BOOM!" That's because the two sounds add logether. ow suppose there are 100 fireworks spread throughout a city, and you want all the sound from tho e fireworks to reach one panicular house (perhaps somebody you don't like very much) at the same time. You can do this by ex plod ing the closer fi reworks laler than the farther fireworks. If you time everylh ing just right, that panicular house will hear a tremendou Iy loud ingle " BOOOOOM! !!!." probably rattling the house's wal ls pretty good. as if one huge fire. work had exploded. Olher houses lhroughout the city will instead hear a serie of quieter booms. since the liming of the explo ions don 't result in all the sounds adding at th.ose olher hou es. Now you understand a basic principle of beamforrning : If you have multiple sound source (fi reworks in our example, lransducers in an ultrasound machine) in different locations. you can cause the sound to add together at any desired point in pace. by care. fu lly riming the generation of sound from each source uch that all the ouod wa\'es arrive at the desired point at the ame lime. In other words. you can electronically focus and steer the sound beam by introducing appropriale delays. Focusing and teering the sound to a panicular point is useful because lhen Ihal poilll will prodllce a much louder echo ,ltan all ollter POiIllS, so we can easily hear the echo from lhat point o\'er all the echoes from other points. Figure 4.87 illustrate the concept of electronic focusing and teering. using two sound ources to foc us and steer a beam to a desired point X. Bo/h waves reach the focal
point ~~ the same ome focal
focaf
polnt
,>- ... ,
I
' .....'
wave
(a)
(b)
(e)
(d l
Figure 4.87 Focu>ing .ound at 3 p3nic'ul3r point using be3mfonning (al Ii t nme
~'lQI~ ~
boll 111 tran du cr g~ncrntc~ ~ound. (b) ~c.'·{lnd lime :-tt'p--the lOp [r:lnMlu r 00\\ ge:oer.u _ ~ ~ too. (e) third time ~tcP-thl' 1\\ 0 '\ound \\ ~l\e~ ~IlJd Jllhe f "at POlOt (d) an II1\bD'3o m, l.I\g thul the top tmnsduccr j., (\\ 0 lime 'Icp~ II\\ J~ from the focal p0lOt. \\ hlle the )[tl'l11 tr'3.ru three time tel' 3\\,1). mcun1l1g the lOp trnn,du,'er ,hould gent:r.ut." ... ~nJ \'Oe un\( p t r the bollOIl1 lrnll,dul'cr.
Datapath Components
4.13 Product Profile: An Ultrasound Machine
te) (Fioure .j.87(a)), the bottom source has begun lra n s m i !lir~g its At the fi, ' e (F' ur' .j 87(b», the top source has begun lransmllllng , r. t lime S.I !)ound wave. Arter two lime steps Ig C • h its sound wave. After tllece time steps (Figure 4.87(c»: the waves frol11 both se n~ors reac . . I TI , II continue adding as long a the waves fro m both . . t he focal POlllt addll10 t02et ler. Ie) . ' e. th ' r We can si mplify the draWing by shOWing only the sources are 111 phase wnh one. ana ~ .' wn in Fi 2ure .j.87(d). lilles from the sources to the focal POII1!. as sho -.. . An ultrasound machine uses this ability to electrolllcally focus and steer sound,. In in fron t of the LIansducers. The machine . ' I entire reoion ord er to scan, POIIl! by pa in!. tIe e .. does such scanning perhaps tens or hundreds of limes per second. . . I he m3chine needs to It sten to . the .echo lhat. comes bac k from FOr eac I1 fDCa1 P01l1t. . . . whatever object is located at the focal point , to determine If that object IS bone, skin, blood. etc., utilizing the fact that each such object generates a differe nt echo. Remember, the echo from the focal point wi ll be louder than echoes from ~lher POlillS, because lhe sound adds at lhat pain!. We can use beamfomling to also focus ilI on a pan lcular pOint 111 space that we want to lislell to. In the same way lhat we generated sound pulses wl lh par, ticular delays to focus the sound a ll a panicular pain !. likewise, to "listen" to the sounds from a panicular point, we also want to introduce delays to the Ignals received by the transducers. That's because the sounds will arrive at the closer lransducers sooner lhan at the fanher lIansducers, so by using appropriate delays. we can '.'Iine up" the signals fro~ each LIansducer so Ihat the sou nds coming from the focal pOint all add together. ThiS concepi is shown in Figure 4.88.
foca l POInI
x"-J \
Q)Q) •
(a)
(b)
'
Signal P rocessor, Sca n Converter, a nd Monitor The signal processo r analyzes the echo data of every point in the scanned region. by filtering out noise (see Seclion 5.11 for a discussion on filLering), interpolating between pOInts. asslgnlllg a level of gray to each poim depending on the echoes heard (echoes corresponding to bones might be shaded as while, liquid as black, and skin as gray. for example), and olher tasks. The resulL is a gray,scale image of the region. The scan convener steps lhrough this image to generate the necessary signals for a black-and-while monitor, and the monitor displays the image.
Digital Circuits in an Ultrasound Machine's Beamformer Much of the conLIol and signal processing lasks in an ullIasound machine are carried OUi using software running on one or more microprocessors, typically special microprocessors specifical ly designed for digital signal processing, known as digital signal processors, or DSP . But cenain tasks are much more amenable to custom digital ci rcuilIy. such as those in the beamfomner. Sound Generation and Echo Delay Circuits
I
--'
(e)
213
8 eamforming is lremendously common in a wide variety of sonar applications, such as observtnga fetu s, observing a human hean, searching for oil underground, monitoring the .surro undlllgs of a submarine, spying, etc. 8eamfomning is used in some hearing aids havlllg mu lupl.e microphones, lO focus in on the source of detected speech-in that case, lhe beamfomnlllg must be adaplive. 8eamforrning can be used i.n multimierophone ceU phon es to focus III ,on the user's voice. and can even be used in cellular telephone base stallons (uslllg radiO signals lhough , not sound waves) lO focus a signal going lO or commg from a cell phone.
(d)
resull wilhoUi Ihedelay
Figure 4.88 Li lening 10 ound from a particular poinl u. ing beamfomling: (a) firsl lime Slep. second lime slep-lhe lOp transducer has heard the sound 1i,,1. (c) Ihird lime slep-lhc bouom Iran,ducer hears the sound al Ihis lime, (d) delaying Ihe lOp lra n,ducer by one lime slep results in the waves from the focal poinl adding, amplifyi ng the sound. (b)
NOle that lhere wi ll cenninly be echoes from olher poinL' in Ihe region, but those coming from the foca l poilll will be much slronger- hence, the weaker echoes can be fil· lered OU!. NOIice lhal beamforming can be u' cd to listen to a panicu lar po int even if the ounds com ing from lhat poim are not echoe' coming bac ~ from o ur 0\\ n ,ound pu lses-the ,ound cou ld be coming from the objeCt at the point IL,clf. ,uch u\ a cur cngi ne or a person talking. 8eamformi ng b Ihe electronic equivafelll to poi llltng n hlg flambolic dish in a panlcu lar direction, bU I beamforming require\ no rnovlIIg PUrt,
8 eamforrni ng during the sound genera- I-----:;=========F=~ lion step consi IS of providing starCout appropriate delays to hundreds of tran ducers. Those delays vary depending on lhe foca l point. so they can' l be built into the lIansducers themselves. [nstead. we can place a del ay circuit in front of each LIansducer, as shown in Figure 4.89. For a given focal poim. the DSP Delay writes the appropriate delay value imo each delay circui t. by wriLing lhe delay val ue on the bus labeled de lay_out. Figure U9 Transducer OUtpul dcll~ in-uilS for writi ng the "address" on the lines Iwo channels, fabel ed add r. and enabling the decoder, The decoder will lhu et the load line of one of the OllrDeia . component , fter wri ting to every ueh c mpollcnt. the 0 P stJJ'lS all of them simullJ.lleQ\l>· ~ b) selli ng s ta rCou t to 1. Each OIlIDelll), c mponeOl \\ill. after the _pe<-ilied deJa), put its 0 output, which we'll assume cau es the lransdul'Cr to generate s undoTIte D P \\ auld then sel S ta rt _ out to O. and then Ii -ten for th -ho,
21 -4
4.13 PrOduct Profile: An Ultrasound Machine
Datapath Components s
We C3n implement the Oil/Deia\' compo-
t
nent lIsing a down·counter with parallel load .
as sho\\" n~ in Figure 4.90. The para llel load inputs L and 1d load the down-counter With its count value. The ent input commences the down-CoUilting-when the CQunter reac hes
zero. the coun~er pulses te . The data output of the counter is unused in tbi s implementation. After the ultrasound machine sends out
sound waves focused on a part icu lar focal point. the machine Illust listen to the echo cOllli ng back frolll that focal point. Thi s li stening requires appropriate delays for each transducer to account for the differing distances of each transducer from the focal point. Thus. each transducer needs another delay
010--- te
ent down~
LI--,....
d
Id l- - - Id
coun ter
_
c
<1--< Out Delay
Figure 4.90 Out Delay circuit. start_out ~_~_~
delay_out
d ---,..:...-
circuit for delaying the received echo . ignal. as shown in Figure 4.91. The EchoDelar com-
ponent receive~ on input t the signal from the transducer. which we ll assume has been digitized into a stream of N-bit values. The componen t should output that signal on output t_de 1 ayed . delayed by the appropriate amount. The delay amount can be written by the DSP using the component 's d and 1d IIlputs. We can implement the EchoDelay component using a series of registers. as shown in Figure 4.92. That implementation can delay the OUtput signal by O. I. 2. or 3 clock cycles, imply using the appropri ate se lect line values for the 4x I mux. A longer register chai n. along wi th a larger mux. would support longer delays. The DSP confi gures the delay amount by writing to the top register. which sets the 4x I mux select lines. A more nex ible implementation of the EchoDelay component would instead u e a timer component. Su mm ation Circuits-Adder Tree
r-....,....-_.. to adders
Figure 4.91 Transducer output and echo delay circuits for one channel.
figure 4.92 EchoDelay circuit.
The output of each transducer, appropriately delayed. hould be , ummed to create a single echo signal from the focal poi nt. as wa iIIus· tented in Figure 4.88. That illu tration had only two transducer;. and thus only one adder. What if we have 256 transducers. a~ would be more likely in a real ultmsou nd machine? How do we add 256 values? We could add the value!> in a lincar way. n.~ illustrated on the left Side of Figure 4.93(a) for eight value' . The delay of that cir Ult i, roughly equal to the delay of ,"ven addm. For 256 values. the de lay would roughly be that of 255 adders. That' a very long delay.
215
We can do better by reorganizing how we compute the sum, USing a configuration of adders known as an adder tree. In other words, rather than computing ((((((A+B)+C)+D)+E)+F)+G)+H. depicted in Figure 4.93(a), we could IIlstead compute ((A+B)+(C+D» + ((E+F)+(G+H)). as shown in Figure 4.93(b). The answer comes out the same and uses the same number of adders, bu; the latter method computes four additions in parallel. then two additions in parallel, and then performs a last addition . The delay is thus only that of three figure 4.93 Adding many numbers: (a, adder. For 256 values. the tree 's first l.inearly. (b) using an adder tree. :\me that level would compute 128 additions in both melhods use seven adders_ parallel, the second level would compute 64 addi tions, then 32, then 16. then 8, then 4. then 2. and finally I last addition. Thu . that adder tree would have eight level. meaning a total delay equal to eight adder dela, . That' a lot faster than 256 adder delays-32 limes/asler. in fact. The output of the adder tree can be fed into a memory to keep track of the re ults for the DSP. which may access the results sometime after they are generated. Multipliers We presented a greatly simplified version of beamforming above. In reality. many other factors must be considered durin2 beamfonning. Several of those cons id er~ ations can be accounted for by multiplyi ng each channel with specific constant values. which the DSP a2ain sets individually for each cbannel. -For example. focusing on a point close to the handheld device may require u to more heavily weigh the incoming Signals of transducers near the center of the device. Figure 4.94 Channel e\tended \\i th a A channel may therefore actuulIy include multiplier. a mUltiplier. as shown in Fi2ure 4.94. The DSP cou ld wri te to the ";gister shown. which wou ld represent a constant by which the transducer signal" uld be multiplied Our introduction of the ultrasound ma hine is greaLl~ simplifit'd from real rna -tune. yet even in thi s simplified introducli n, you an see man~ of this chapt r's dat3P'lth xtnponents in use. We used a down-c unter t implemt'nt the OllrD 1<11 'mpon nt • .1nJ severa l registers along with muxes ~ r the EciJoD~la\' component. We u>t'd many 3JJe to sum the in ollling tmn du er , ignals. nJ \\e ust'd a multiplit'f to \\clgh tIK incomi ng !'ignab.
216
4 Datapath Components
4.15 Exercises
217
ultrasound . The req uirement th t f understanding of an r . a a so tware programmer or digital designer have some . app Icallon domam IS quite common. '11 I In the commg chapter yo seq uenti al logic desi ( ' u WI app y your knowledge of combinational logic design, cu its that c . I gn controller deSIgn), and datapath components, to bui ld digital ciran Imp ement very general and powerful computations.
Future Challenges in Ultrasound Over the past two decades. ultrasound machines have, moved from mostl y a~lal og machines to moslly digilal mac hines. The digital syslcmS conSISI of bOlh CUSlom dI gItal CirCUIts and software on DSPs and microprocesso rs. workin g together (0 creHle real -time Images. One or the mai n trends in ultrasound machines involves crcating three-di mensional (3- D) images in realtime. Most ultrasound machines or the I990s and 2000s genera ted twodimensional images. with Ihe qua lity or those images (e.g .. more rocal points per image) improvin o durin g those decades. In contrast to two-dimensional ultraso und. generating 3-D images r:quires ~lie\Ving the region of interest from differen,l perspecti :,es, just li ke people vicw things from lheir tWO eyes. Such generation also requ ires extenSi ve computations to creale a 3- D image from the twO (or more) perspecti ves. The res ult is a picture li ke that in
4. 15 EXERCISES ExerFcises marked with a n asterisk (*) represent especially chal lenging pro blems. bl or exerCIses h . relallng to data pa th components, each problem .Indicates whether the pro em emp aSlzes the component 's internal design or the component 's use. SECTION 4.2: REG ISTERS
Figure -1 .95. Thal's a fetus' face. Impressive. isn'l il ? Keep in mind that image is made solely from sound waves bounc ing into a woman's wo mb. Color can also be added 10 distinguish among different Ruids and tissues. Those computations take time, but faster processors. coupled with clever custom digital circuits, are bringing real-time 3- D ultraso und closer to reality. Another trend is toward making ultrasound mach ines smaller and lighter, so th at they can be used Figure 4.95 3- D ullrasound image in a wider variety of hea lth care situations. Early of a fe lus's face. Photo counesy of mach ines were big and heavy, with more recent ones Phi lips Medical Syslems. comi ng on rollable cans. Some recent versions are handheld. A related trend is making ultraso und mac hines cheaper. so that perhaps every doc tor could have a mac hine in every examination room. every ambul ance could carry a mach ine to help emergency personnel ascenain the ex tent of cen ain wo unds. and so on. Ul trasound i used fo r numerous other medica l appli cations. such as imaging of the heart to detect artery or valve problems. Ultrasound is also used in vari ous other applica· tions. like submarine region monitoring.
~·s ~·J
Trace ' . I the behavior .of an 8-bil ParaJl eI Ioad register W. ith.IIlpUI I. output Q. and load conrrol IIlpUI d by complellng the following liming diagram.
Id
Q
~.2
Trace the behavior of an 8-bit parallel load register with input I. OUtpUI Q. load conrrol input Id, and synchronous clear IIlput clr by completing the following timing diagram.
~
_____________r---l~_____
ctr - - - - - - - -_ _ _ _--.l
L - -_ _ _~
clk
4.14 CHAPTER SUMMARY In th is chapter. we began (Section 4. 1) by introducing the idea of new bu ilding blocks intended fo r common operations on multibit data, wi th those blocks being known as data· path components, or register-tran fer-level component . We then introduced a num ber of datapath components. incl ud ing reg isters. shifters. adder. comparator. counters. multi· pliers, ,ubtractors. arithmetic- logic uni ts. and register fi le,. F r each component, we examined two a pects: the internal design of the component , and the u,e of the compo· nent in applications. We ended (Secti on 4. 13) by describing some ba~ i c principles underl ying the opera· tion of an ultraso und machine, and showing how severa l of th ' datu put h components might be u'>ed to implement pans of such a machine. One thing YOll mi ght n ti e i how de\igning a real ult raso und machine wou ld require ,ome knm ledge o f lhe domnin of
Q ~ .J
)
Design a 4-bit register with 2 control inputs 51 and sO, -1 data inputs I .11. II. and 10. and 4 dala outputs Q3. Q2. Q I. and QQ. When s 150=00. the regisler maint:uns its "3Jue. \\'hen 5150=01. the register loads 13.. 10. When s lsO=I O. the register clem itself ro 0000. When s IsO= II. Ihe regisler complements itself. so, for enmple. 0000 would become 1111. 3ild 10 10 would become 0101. (Componem design problem.)
H
'\ .L .......
Repeat Ihe previous problem. but when s IsO= II. the regisler re\'erses its bits. so 1110 ",auld become 011 1. and 1010 would become 0101. (Component design problmLl -l.S Design an -bit regisler with 2 control inpuls sl and O. data input> I ..lD. and • J;uu outpul>o Q7.. QQ. s lsO=OO means mai nlain the prescnt \·alue. IsO=01 me3n. load. 3ild IsO=lO me>n> clear. s IsO= I I Illeans to swap Ihe high nibble with the 10" nibble (3 nibble is 4 l>il:>\. • 1111 0000 w uld become 0000 11 11. and 11000 101 " ould tx>rollle 010111 . '(',.""1'<"1<'/11 drsig" problelll. )
218
Datapath Components
4.15 Exercises I
•
lice officer is alwa ys outputting;] radar :. i ~ n al and I.n e~s ~ring the
,POass However. when the officer wants to tIcket
-',6. The radar gun used b)
~pcr.:d of
mdar .5 gun
If0j·S
.1
the caf !
~ pc c
d d'I ~ pi")' •• • (ColIIl'Jollellf lise problem.)
SECTION ~.3 : ADDERS '" " . rin o nt the outputs of a 3-bit carry-ripple add\! r for evc~ one full-adder· -'.7. Trace the \ alues .tppe.l e . . h 0 11 Ass um e all inputs were prevIOusly ze ro for a delay time peri od. when adding I II \V II .
long time. . . d d - . I' I f I time unit. compute th e longest tllne req uire to a d two ....8. Assu[11Jng nil gates have n de ~) 0 dd num bers usi ng an S-bi! carry-npple a er. . . . I 0 have;] dclay of 2 lime uni ts. OR gates have a de lay of I lime unit, and -'.9. Assuming AND cates f 3 . e units compute the longest time required to add two XOR 2ateS have a de l:ly 0 tlJll • numbe;s using an S-bit carry-ripple adder. Dcsi2n a
If0j·S
1 0-~t carry- ripple adde r using ~-bit carry-rippl e adders. (Componelll use problem.)
~: :~ De;i:n an odder lhOl com putes the sum of three S-bil number. using S-bil carry-ripple adders. (Co,,~ponelll lise problem.)
If0j·S -l.12
.
.
.
Des ion an adder thaI computes lhe sum of fou r S-bil numbers. uSIOg S-b" carry-npple adders.
(Co117pOllelllllse problelll.) ... 13 Design a digital thermomete r lhat can compensate for errors in the t~mperature sensing . dev i;e 's output T. which is an S-bit in pu.t our system. The com~ensat.l on amou~t can be osi li\'e onl y. and comes to our system VIU Inputs a. b. and c. ~rol11 .1 3-pln DIP switch. Our p system should output the compe"'nsated tempera ture on an 8-blt output U. (Co mpOllelll liSt
t?
problem.)
~ .I ..J Repeal the previous problem. except that the compensati on amo unt can ~e positi ve. or nega-
our system via four inputs a. b. c. and d from a 4-pl.n DIP switch. The co~pensati~n amount is in two's complement form (so lhe . per~on. scttlng the DIP switch beller know that!). Design the ci rcuit. What i the range by wh ich the Input temperat ure can be compensated? (Co mpone11l lise problem). ti ve comino
to
~. 15 We can add three 8-bil numbers by chaining one 8-bil corry-ripple adder 10 the Outpul
of anothe r -bil carry-ripple adde r. Assuming every ga te has a delay of I lline- Unlt. comp~te the longe" delay of this lh ree 8-bit number adder. Hint: you may hove to look carefull y ,"Side the carry-ripple adde", even in; ide lhe fu ll-adder;. to correct ly compute lhe longesl delay from any input to any output. (Compolle11l use problem.)
SECTlO, 4.4 : SHIFTERS
4.16 De; ign an 8-bi t shifter lhat shifts its inpuls lWO bits to lhe ri ght (' hifling in Os) when the shi fter\ 'hift control inpul is I. (Compollelll desigll p lVhlem.)
c-: PLU·S
-I 17 Design a circuit thaI OUlput, the avemge of four 8-bit input' rcpre,enllng binary numbers (not . in two', complement fo rm). (CompOllelll ll le pmhlelll.) ~. 18 Dc"sn a CIrCUit thaI take, an 8-bitlnput D repre<;ent'"g binary number. (not in two's compl<· ment rorm). and outputs two time~ that \
-1.19 De"gn a eircUitthat ou tput, nine tim .. 11' 8-blt ,"put D reprc,enllng blnllry numbers (not in two\ compleme nt form). II lnt: \e:1 ~ hl ftcr and an odder ( o",po"elll 'HI! 11mb/~m.)
219
4.20 Design a special mu ltipl ie r eircuil lhal can multiply ilS l6-bil inpul by I. 2, 4. 8. 16. or 32. speCified by lhree ,"puts a, b. c (abe=OOO means no multipl y. abc=OOl means multiply by I. abc=O IO means by 4, abe=O II means by 8. abe=IOO means by 16. abe=IOI means by 32). H'"t: Use a predefined component deSCribed in lhis chapler. (Component use problem.) 4.21 Trace lhrough lhe exec ul ion of lhe barrel shifter shown in Figure 4.42. when 1=011 00101. x = I. Y= 0, Z = I. Be Sure to show how the inpul I is hifted after each internal shifter stage. 4.22 Trace through th e execulion of lhe barre l shiftershown in Figure 4.42. when 1=1 0011011. x = 0, y = I, Z O. Be sure to show how the input I is shifted after each iniernaJ shifter stage.
=
4.23 Using the ba,:,el shifter shown in Figure 4.42, whal settings of the inpu ts x. ). and z are required to shift lhe ,"PUI I left by six posilions? SECTION 4.5: COMPARATORS 4.24 Trace th rough the exec uti on of the 4-bit magnitude comparator shown in Figure 4.45 '" ben
a= 15 and b= 12. Be Sure to show how the comparisons propagate thought the individual comparators. ~.25 Desig.n a comparator that determines if three 4-bit numbers are equaL by connecting 4-bit mag nitude comparators together and using additional components if necesS3I). ( ComponenJ use problem.)
4.26 Design a 4-bit carry-ripple slyle magnitude comparator that has two outpu ts. a greater-than or eq ual-to output gle, and a less-than or equal-to output lIe. Be ure to clearly sho\\ the equations u ed in developing the individual I-bit comparators and how they are connected to fonn the 4-bit circuit. (Compollellf design problem.) 4.27 Design a S-bil magnitude comparator. (Compollelll design problem.) 4.28 Design a ci rcuit tha I outputs I if the circuit'S S-bit input eq ual 99: (a) usi ng an eq ual il y com parator, (b) using gates onl y. Hint: In th e case of (b). you need only I AND gate and some imeners. (Componem
us,
plVblem.)
4.29 Use magnitude comparators and logic to design
3
circuit that rompme5 the minimum of three
8-bit numbers. ( Componelll use problem. ) 4.30 Use magnitude comparators and logic to design a circuit that compme5 the ma..,irnum of (Wo 16-bil num bers. (Compollelllilse problem. ) 4.31 Usc magnitude comparators and logic to design a circuit thut outputs 1 \\hen an -bit lDput is between 75 and 100, incl usive. (Compoflenr use problt'm.)
-1.32 You are to design 0 human body temperature alarm system for a h pit.!. Your >~ 'tern an 8-bit input repre en ting the temperature. whirh can range from 0 to :.!.55. If the nle:lSured lemper:llu re is 95 or less, you should set omput A to I. If the temperature I> 96 to 10-l. ~ou shou ld set out put B 10 I. If the temperature is 105 or abo\"e. ~ u should set output C t 1. ( Companelll lise problem"
4.33 You are working as It weight gue ~er in an amusement p3.fk. Your job is to tr) to go -- tM weight of an individual before they ~h!P on the scale. If ~ our gue~... i!-' n)( "ithllli n ~ of the individual'S octuulll'cigh t (higher or lo\\er)_ the indh'idual \\In-. pll2 • BUild 3 \\ !$ht gU~!!J analyzer system that OUtputs \\hether the gues~ \\ib "llhin ten P~)uI'hh. 'Th-e \\ l~ht guess ullnl) ll! r has an -bit guc~ input G. J.I1 :'>-bit input from the S('31e \\ \\lth the... ::t \\eight. and a ~i ngle ou tpUt C that is I irthe guc:- ~~ \\clght \\.b \\ ithlO l~ Jeri"'-,\! hmlb of lhe game. (CompoIJt'IJI usr l,mblem.)
220
4.15 Exercises
Datapath Components SECTIO N ~ .6: COlJNTERS 4-bi t up-counte r that hrls twO control inputs: elll enables cOlllllin g up. w hile clear
".J'" Design a
synchronously resets the counter to all Os: (3) using a parallcl IO::ld register as a building block. (b) using flip-flops and 11111XeS directly by following the regiSlef design process of Section 4.2. (Componelll desig" problelll.) .t35 Design a 4-bit down-counter that has three co ntrol inputs: elll enublcs cOll ll li ng up. clear synchronously resets the counter to all as. ;}nd sef synchrono usly sets the coume r to all Is: (3) lIsing 3 parallel load regi ster as a building block. (b) usi ng fl ip-flops and muxes directly by following the register design process of Section 4.2. (Compoll ellf design problem.)
.tJ6 Design a 4-bi l up-cou nter with an additio nal ou tput IIpper. tipper ou tputs a I whenever the counter is within the uppe r hal f of th e counter's ra nge, 8 to 15. Use J bas ic 4-bit up-counte r as a bui lding block. (Compoll elll desigll problem.) -1.-'7 Design a 4-bit up/down-coun ter lhat has four conuol in puts: CIICUP enables counting up. elll down enables counlin£! down. clear synchronously resets the counter to aliOs, and set syn~hronou sl y seLS the cou~ter to all I s. If both counl control inputs cm_lIp and cllt_dow,l are I. the counter will retain its current count value. Use a parallel load reg ister as a building block. (Compon ent design problem.)
~ . 38 Design a circuit for a 4-bit decreme nter. (Component design problem.) ~.39 Design an electronic turnstile system using a 64-bit counter. The input is a bit A, which is I for exact ly one clock cycle whenever a person walks through the turnstile. The outpu t is a 64· bi t binary number. A second input 8 is 1 whenever a reset button is pressed. and should reset Ihe OUIPUIIO Os. Knowing Ihal Californ ia's Disneyland altrac lS aboul 15.000 visilors per day, and assumin g they all pass th rough your one turnstile. how many days wou ld pass before your counter would roll over? (Compone1l1ltse problem.) ~.-lO (a) Using an up-counter with a synchronous clear contcol input, and ex tra logic. design a circuil Ihal OUIPUIS a I every 99 clock cycles. (b) Design Ihe co unler from part (a). bUI use a down-counler wi lh parallel load. (c) Whal are Ihe tradeolTs belween Ihe IWO designs from parts (a) and (b)? (Compone1l1llSe problem.)
4AI (a) Gi ve Ihe counl range for Ihe following sized up-counlers: 8-bils. 12-bils. 16-bils. 20·bilS, 32·bi lS. 40·bils. 64·bilS, and I28-bils. (b) For each size of counler in part (a). assum ing a I Hz clock. indicale how many minules. hours, days, etc .. the counter wou ld counl before wrapping around. SECTION 4.7: MlJLTIPLIER-ARRA Y STYLE ~A2 Ass uming all gales have a delay of I lime·unit. which of the following designs will compule
the 8-bil multiplicalion A' 9 fasler: (a) a ci rcuil as designed in Exe rcise 4.19. or (b) an 8-bil array slyle multiplier with one of ils inpuL~ connecled 10
II
conSlanl value of nine.
4.43 Design an 8·bi l array,s lyle multiplier. (CompOllelll desigll proMem.) ~A4 De;ign a more accurale versio n of the Celsius 10 F"hrc nheil conve rt er from Example 4. 10.
The new conve r$ion circu it receives n digitized temperature in Cebiu us n 16-bit binary number C and OUIPUIS Ihe lemperalure in Fahrenheil as a l6-bil OUIPUI F. Our more accurnle eq ualion for calcul aling an approximate conversion from cl,i ll' 10 Fahrenheil is: F = C'301 16 + 32 . (Compoll elll lise p roblem.)
SECTION 4.8: SlJBTRACTORS 4.45 Creale Ihe internal design of a fu ll. 446 C h ' Sublraclor. (Compollelll design problem) . onvert t e follOWing two's com I . (a) 0000 II II P emenl binary numbers 10 decimal numbers: (b) (c) (d) (e)
10000000 1000000 1 11111111 100 10 10 1
4.47 Conven the following Iwo's co I . (a) 0 1001 10 1 mp ement binary numbers 10 decimal num bers: (b) (c) (d) (e)
000 1101 0 111 0 1001 101 0 10 10 111111 00
4.48 Convert Ihe followi ng IWO's complemenl b' be . (a) 111 00000 Inary num rs 10 deCImal numbers: (b) (c) (d) (e)
01 111111 1111 0000 I 1000000 111 00000
4.49 Convert Ihe following 9·bi l IWO'S compleme I b' b . (a) 0 11111111 n Inary num ers 10 deCImal numbers: (b) 1111111I1 (c) I00000000 (d) I I 00000oo
(e) 11111111 0 . 4.50 (a) Convert 2 Ihe fo llowing decimal numbers 10 g·b·1I I"wo S comp Iement binary ronn: (b) - I
-23 - 128 126 127 (g) 0 (c) (d) (e) (f)
4.51 (a) Convert 29 the followin!!- decimal numbe rs 10 . b'II IWO'S complement binary ronn: (b) 100 (c) 125 (d) - 29 (e) - 100 (f) - 125 (g) - 2
221
222
4.15 Exerc ises
Datapath Components .
~.52 Conve rt the rollowi ng decllllal numbers to
g.bit
tWO' s
complement binary
fOfm :
In puts
(a) 6
(b) 26 (c) - 8 (d) -30 (e) -60 (I) -90 (g) - 120 .. .' "'.53 Convert the followmg deCimal numbers (a) (b) (c) (d) (e) (I)
223
TABLE 4.4 Desired ALU operations.
to
. 9.bil twO's compl ement bin ary fonn:
I - I
X
y
0 0 0 0
0 0
0 0
-256 -255
Operation
0
S-A+B
1
S = A AN D B (bitwise AND)
0
S=A
1
S = A OR B (b it wi se OR )
AN D B (b it wise NAN D)
0
S = A NOR B (bit wise NO R)
1
S = A XOR B (bit wi se XO R)
0
S = A XNO R B (bi twise XNOR ) S = NOT A (bi twise complement )
255
-8
( 0) - 128
th t has three S-bit inputs. A. B, and C , and a single
o
"'.5-& Usin2 4-bit subtractors. bui ld a sublraclO f a bl ) 8-bit....output F. where F=(A-B) - C. (Compollelllilse pro em, . . that di oili zes a temperature int.o a 16-bit binary number K . a .S5 You are given a digital thermometer e 0 a 16-bit Fahrenheit value. Use the fol in Kel vin . Build a system to conve rt that temperalUre ,I * . . lOWing equauon (0 proYI'd e an appro xi m, te co nverSIOn : F= (K-273) 2+32. (Compollellt lise problem. )
SECTION 4.9: ARITHMETIC-LOGIC UNITS-ALUS
~.56 Des ion an ALU with two 8-bit inpu ts A an d B. and co ntrol s ignals x, y, and z. The ALU should support the operation s desc ribed in Table 4.3. Use an 8- blt add er and an anthmeuc!
logic ex tender. (Componefll design problem.) TABLE 43
Desired ALU operati ons.
Inputs X
y
0 0 0 0
0 0
Operalion
0
S=A-B S=A+B
0
S=A " S
0
S = A NAND B (bitwise NA D)
S= A/ 8
0 0
1
S = A XOR B (bitw ise XOR)
0
S = Reverse A (bi t reversa l) S
=NOT A (bitwise compl ement)
4.57 Design an ALU wilh two 8-bit in pu ts A and B. and co ntro l sig ~a l s x. y. an d z. The A ~U sho uld s upport the operati o ns described in Table 4.4 . Usc an 8-blt adder and an an thmeuc!
logic extender. (CoII/ponenl design problem.)
4.58 An instructor teaching Boolean algebra wants to help her students learn and understand basic Boolean opera tor.; by providing the stude nts wi th a calculator capable of perfomling bitwise AN D. NAND, OR. NOR. XOR. XNOR. and NOT operatio ns. Using the ALU specified in Exe rcise 4.57. bui ld a simple log ic ca lculator us in g DIP switches for input and LEDs for output. Th e logic calculator should have three DIP swi lch inpu ts to select which logic operati on 10 perform . (CompOllelll use problem. ) SECTION 4.10:
REGISTER HLES
4.59 Des ig n an 8x32 two port (I read. I write) regi ster fi le. (Compollent design problem) 4.60 Des ig n a 4x4 three port (2 read. I wri te) register fi le. (Compollem design problem_ ) 4.61 Design a IOx l 4 register fi le (one read port. one write port). (Compollem design problem ) 4.62 " Create a speed-dial system for a telephone. Ei ght speci:1l buno n bO-b 7 access each stored number. The most recently dialed number exists as ni ne digits stored in nine 8-bi{ regi rers RO-R . When the phone user presses another button S simultaneously with any bunon bO-b7. the most recently dialed number gets stored in the button's corresponding storage. When the user presses a bu tton bO-b7 by itself. the number in that bu tton 's storage gets read o ut and placed on nine -bit outputs PO-P8. Hint: use nine register fi les and some extra logic. (Componenl use problem. '
224 ~
4 Datapath Components
DESIGNER PROFILE Roman began slUdying Computer Science in college due to his interest in soflware
development.
During his undergraduate
studies. his interests expanded 10 include digilal design and embedded syslems and eventually led him to become involved in research developing new
melhods 10 help designers qu ickly build large integraled circuils (IC). Roman conLinued his education through grnduate stu dies and
recei ved his M.S. in Compu ter Science. after which Roman worked for bOlh a large company designing integrated circuits (Ie) for consumer electron ics as well as a slart-up
10015. and delennine if ex isti ng solutions will help you solve the problems you face as an engi neer." Roman points out that digital design has changed at a rapid pace over the last few decades. requiring engineers to leam new design techniques, leam new programming languages, such as
YHDL or SyslemC, and be able
10
adopl new lechnologies
stay success ful. "As the industry continues to advance al such a rapid pace. companies do not only hjre engineers for what th ey already kn ow, but more so on how well those engineers can continue to expand th eir knowledge and 10
leam new skills," He poinls oUI Ihal "college provides slUdenls wilh an excellent opportunity 10 not only learn the
Register-Transfer level (RTl) Design
essemial infonnation and skill s from their course work but also to learn additional infonnation on their own, possibly
by learn ing differenl programmi ng languages, gelting involved in research. or working on larger design projects."
company focusing on high-performance processing.
Roman is mOli valed by his enjoymenl of Ihe work he does as well being able 10 work with other engineers who
Roman enjoys working as both a software developer and hardware engineer and believes that "fundamentally software and hardware design are very similar. both relying on efficiently solving difficult problems. While
share his interests. "Motivati on is one of the keys to success in an engineering career. While motivation can come from many different sources , finding a career that
good problem solving skill s are important, good learning skill s are also imponant." Contrary 10 what many stu denls may believe. he points au[ that "Ieaming is a fundame ntal activity and skill mat does not end when you recei ve your
know ledge and lechnical advice. Working as a member of
degree. In order 10 solve problems, you often are required 10 leam new skills. adopl new programming languages and
5
you are trul y inleresled in and enjoy reall y helps. Coworkers are also a great source of moti vation as we ll as a team th at communicates well is very rewarding. You are
able
10
mOli vale each olher and use you r strengths along
with the strength s of your co-workers to achieve goals far
beyond Ihal which you could achieve on your own."
5.1 INTRODUCTION In the previous chapters, we've defined the combinational and sequential components needed to build di gital systems. In thi s Chapter, we'lI learn to build interesting and useful di gi ta l sysle ms from those components. In particular. we'lI put LOgether datapaLh components 10 build datapaths, and we'll use controller to control those datapaths. The combinati on of a controller and datapath is known as a processor. Some processors. like Ihose in pe rsona l computers. are programmable-those processors are the focus of Chapter 8. Other processors are custom-designed for a parti cular task. and are nOl programmable-
226
Registe r-Transler LevellRTLI Design
5.2 RTL Design Method
In the combinat ional logic design process outlined in Tabl e 2.5 , . . . I . The first step was to caplllre the desired behavior of the comblll auonal logtc, wit h either a truth table or an eq uation.
227
A fifth step may be necessary, in which one selects a clock frequency. Designers seeking high performance may choose a clock frequ ency that is the fastest possible based on the longest register-to-register delay in the fin al circu it. Implementing the controff er's FSM as a sequenti al circuit. as we learned in Chapter 3, would then compl ete the design.
2. The rcma in ing stcps were to cOllller / th e behavior to a circuit.
In the sequential log ic (controffer) design process in Table 3.2. . . . I. The first step was to caplll re the desired behaV ior of the sequenu al logtc, usmg a finite-sta te machi ne. 2. The remai ning steps were to convert the behavior to a circu it.
Notice that the first step captures the desired behavior, whi le the remaining step that behavior to a circui t.
COII l/ert
We' ll first provide a smaff and simple example as a "preview" of the RTL design method 's steps, before we define each step in more detaif.
It should therefore come as no surpri se th at: .
I. The first step of an RTL des ign method wi ff be to captll re the des ired behavior of
the processor. We' ff introd uce the concept of a hi gh-level state machme for capturi ng RTL behavior. 2. The re maining steps wi ff be to
cOlI l/e rtth e
behav ior to a circuit.
Figure 5. I il lustrates the idea th at the design process ca~ be viewed as first capturing behavior and then convenin o the behavior to structure. That process applies regardless of whether we are performing combinati onal logic design. sequential logic design, or RTL design.
In this chapter. we wiff introduce the RTL design process. also known as the RTL design method. As the process is largely creative, we wiff utili ze numerous examples to iff ustrate the process . We wi ff also introduce several high-level components that are useful during RTL design. including memory components and queue components.
Capture behavior
Convert to circuit
Figule 5.1 The design process.
5.2 RTL DESIGN METHOD
TABLE 5.1 RTl design method.
CapfUre Q.
Description {I
high-level
S(llfe machine
~
cii ;
Crea~e a darapllI/i
<0 ~
COlin eel the datapath
~
10
"
e-
cii
Describe the system's de ired behavior a a high-level state machine. The Slale machine consists of slales and Lran sil ions. The Slate machine is "high-level" because the tran sition condili ons and the stal e actions are morc than just Boolean operations all bit inputs and outputs. Cleate a datapat h to carry out the data opeltltions of the high-level Sla le machine.
a cOli/rolle r
.., Derive 'he cOllfmller 's FSM
Soda machine dispe nser We are (0 design a processor for a soda dispen ser. A coin dClcclOr provides our processor with a I·bit input c mal becomes 1 for one clock cycl e when a coin is detected. and an 8-bit input a indicaling the coin 's value in cents. Another 8.bit inpu t S indi. cates the cos t of a soda (thi s cost can be set by the machine owner). Once the processor has seen coins whose value equals or exceeds the cost of a soda. the processor should se t an OUlput bit
d to 1 for one clock cycle. causing a soda to be dispensed (this machine has on ly one type of soda). The system does not give change-any excess money is kept. Figure 5.2 provides a block symbol of the system .
Step 1 of our RTL design method is to capture the desired behavior of the system. Figure 5.3 shows a
high-level state machine describing the desired behav ior. The first state. Ill il. sets the output d to 0 and initializes a local reg ister tot 10 O. tot will
c_ d_
Soda dispenser processor
Figule 52 Soda dispenser block symbol.
Inputs: c (bit), a(8 bits), s (8 bits) Outputs: d (bit) Local registers: tot (8 bits)
keep track of how many cents the syslem has seen so far. The Slate machine then enters stare Wail.
(Recall from Chapter 3 that a transition with no
RTL des ign is carried out using a wide variety of methods in practice. but it may be useful to defi ne a general method as in Table 5. 1
Step
EXAMPLE 5.1
Connect the datapmh to a controller block. Connect external Boolean inputs and output to the controller block. Convert the high-level state machine to a fini te-,t.te machine (FSM) for the controller. by replaci ng data operations with sctting and rending of control signals to . nd from the dutapath .
condi ti on has an implicit "[rue" condition. and thus
transitions on the nex t rising clock edge.) The FSM stays there as long as no coin is detected and the total cents seen so far is less than the cost of a soda. When a coin is detec ted. th e stale machi ne goes lO
state Add. which adds the coin 's value to t o t. and then returns to stale Waif. Once tot is greater than or eq ual to (in other words. nO( les than) the cost of a soda, th e state machine goes to stale Disp. wh ich dispenses a soda by selling d to 1. The state machine then return s to Slale /"il .
Slep 2 is to create a datapath. We'll need a local regis ler for tot. an adder connected to tot and a to compute tot + a, and a comparator con· ne ted to to t and S to compute tot
d=t Figure 5.3 Soda dispenser high-!e\·.! S t ~lle
m:Jchinc.
228
Register-Transfer l evell RTLI Design
5.2 Rll Design Method
Step 3 is to connect the datapath to a controller. Figure 5.5 shows the connections. Notice that the controller's inputs and outpu ts arc all just one-bit signals.
The previous example gave a preview of the RTL design method. Notice that we started with a high-level state machine, w hich wasn't just an FSM because there were loca l registers dec lared, and beca use there were dat a operati o ns (rather than just Boolean operations) in the states an d o n the transitions. We th en created a datapath to implement those local registers and to carry o ut the data operation. We further needed a controller to contro l that datapath . We defi ned the behavior of that controlle r to be the same as the behavior of the hig h-level state mach ine. except the contrOller's FSM used datapath cont ro l signals to carry ou t and evaluate the datapath operations. Finally, we could design the contro ller using Chapter 3's Contro ller design process. We now disc uss each RTL desig n me th od s tep in more detail, while illustrating each ste p with ano ther example.
Step 4 is 10 derive (he comfoller's
FSM. The FSM has the same states and transitions as the high-level stale machine, but utilizes the datapath 10 perfoml any data operations. Figure 5.6 shows the FSM fo r the controller.
Data path Figure 5.5 Soda dispenser controller
in the high-level stale machine. stale fil iI had a data operarion of tot =
o (tot ment
and datapath co nn ec ti ons.
Step 1-Creating a High-Level State Machine
is 8 bits wide. so tha! ass ignof
a
is
not
a single-bit InpulS: c, toU Cs (bit) Oulpuls: d, toUd, toCctr Ibit)
operation). We replace that assignment by selling tot_c 1 r ~ 1, whi ch clears the tot register to O. State
toUd
Wait's transitions had data opera ti ons
comparing tot
<
s. Now we have
d
a com paralOr computing th aI com-
parison for the controller. so the controller need onl y look at the result
of that comparison
in th e
signal tot_l t_s. State Add had a da!a operati on of tot ~ tot + a. The da!apath computes that addi -
d=l
Controlier
Figure 5.6 Soda dispenser conto ller FSM.
tion for the con troller using the
adder. so the controller merely needs to set to t_ 1d ~ 1 to cause th e addition result to be loaded into th e tot 15
regi ster.
To complete the design, we wou ld implemen t the cont ro ller's FSM as a Slate register and combinational logic. Figure 5.7 shows a partial state table fo r the controller, with the states encoded as /lIil : 00 , Wail: 01. Add: 10, and Disp: 11. To complete the controller design, we would complete the state table.
I-
E
'iii
!:
create a 2-bit Slate register, and crcate a ci rcuit for each of the five
outputs from the tab le. as discussed in Chapter 3. Appendix C provides details of com pletin g the controller'S design. That appendix also traces through the functioni ng of the controller and datapath wi th one another.
229
"0 "0
0'"
c 0 0
0
1
0
1
1
15
1-
nl 0 0 0 0
nO t
d
0:
1
0 0
1
a
1
0 0 0 0 0 0
0 0 0 0 0 0 0 0
sO 0 0 0 0 1 1
0 0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
t 0
0 0
0
0
0
1
1
1
0
0
0
st 0 0 0 0 0 0 0 0
<:
a.
,;:
... 0 ...
1
... 1 ...
0
I-
g t 1
t 1
0 0
0 0
1
0
0
0
Figure 5.7 Sada dispenser contro ller's stute table (panial ).
A hi g h- level state machine is a computation model s imilar to a finite-state machine_ but with add itio nal features th at ena ble the desc ripti o n of computations involving more than just Boo lean data. Reca ll that a finite-state machine (FSM) consists of inputs. o utputs, states_ state ac ti o ns (a mapping of states to o utput va lues), and state transitions (a mapping of state a nd inputs to nex t states). However, the inputs and outputs of an FSM are limited to Boolean types, actions are limited to Boolean eq uati ons, and transition conditions are limited to Boolean ex pressio ns. These limitations make specifying of computations invo lving da ta cumbersome, other than for just si ngle-bit data. Fig ure 5.3 showed a high- level state InpulS: c (bit), • t8 bitsl. s (8 bits) machine describing the behavior of a soda d isOutputs: d (bit) penser processo r. Notice that the state machine is Locat registers: tot (8 bits) not an FSM beca use of the severa l reasons hi g hlig hted in Fig ure 5.8. One reaso n is beca use the state mac hine has inputs that are 8-bi t types, whereas FSMs o nly a llow input and o utputs of Boolean types (a single bit each) . Another reason is because the state mac hine declares a local register tot to sto re intem,ediate data. whereas d=l FSMs don ' t all ow local data storage-the only Figure 5.8 ada dispenser high-le\·eJ "sto red" item in an FSM is the s tate itse lf. A State machine with noo-FSM con.sttucts third reason is beca use the state ac ti ons and tranhi ghlighted. s ition conditions invo lve data operations. like tot = 0 (re member th at tot is S-bits wide). tot < s (there' no .. <_. Boolean operator), and tot ~ tot + a (w here the "+" is addition. not OR. and there's no addinon Boolean operator). whereas an FSM allows o nly Boolean equations and expre
230
Register· Transfer Level (RTL) Desig n
5.2 RTL Design Method
Slich a high-level state mac hine is not the onl y possible ex.te nsion to an FSM . Do~ens of varie tics of ex tended FS Ms ex ist. However. we will be lItlh zlI1g the a bove-descnbed extended FS M varie ty throughout th is chapter. That parllc ula r varie ty o f hIgh-level state . mac hine is someLimes ca lled an FSM with data . or FSMD . We will contin ue to use the following conve ntions fo r hIgh-leve l state machines,
from bunon B
L
231
to laser
Laser·based distance
measurer
S
from sensor
which we also used fo r FSMs: Each tra nsi ti on is implic itl y AN Ded with a ri sing cl ock edge.
Fig ure 5.10 Block diagram of the laser· based distance measurement system.
Any b it output not ex pli c itly assigned a va lue in a Slate is imp lic itly assigned a O. NOIe: this convention does not apply for mulllbJl outputs.
Step I-Create a high-level state machine.
We now prov ide anoLher example of describin g a sys te m using a high-level state mach ine. EXAMPLE 5.2
We can desc ribe the ove rall co mrol of the sys tem using a hi gh-leve l stille mac hine. To facilitate the c reation of the Sia le mac hine, we enumerate th e sequence of eve nts underlying the measurement
system:
Th e system powe rs o n. Initiall y. th e sys tem 's laser is off and the system outputs a distance of
omelers.
Laser-based distance measurer- High-Ievel state machine There are cou llIless app licatio ns thnt req uire one to acc urately measure ~he dis tance of an object from a known point. For example. road buil ders need to acc~ r~lI e l y de te~mlne the .Iength of a stre~ch of road. Map makers need to acc ura tely dete rmine the locat.lOns a.nd. heights of hills and mountainS and the sizes of lakes. A t! iant crane for constructing skyfl sc bUi ld ings needs to acc urate ly deler· mine the dista nce of the s~ding crane arm fro m the base. In all of these applicntions. stringing out a tape measure to measure the....distance is not very practical. A bellcr method involves laser·based distance measurement. In lase r-based dis tance measure ment. a lase r is paimed at th e object of illlerest. The laser is briefly turned on. and a timer is started. The lase r light, trave ling at the speed of light. travels to the object and refl ects back. A sensor de tects the refl eclion of the laser light. causing the timer to stop. Knowing the time T taken by the light to trave l to the object and back. an d knowing that the speed of ligh t is 3x lOBmeters/second. we can com pute the distance 0 eas ily by the eq uati on: 2D T seconds * 3x IO~ meters/second. Laser.bused distance measureme nt is illustra ted in Figure 5.9.
=
The sys tem should then wai t fo r the use r to in it iate measurement by pressing a button. B.
Arter the bUllon is pressed . the system should tum the laser on. We'll choose to leave the laser on for one clock cycle. Aflc r the lase r is pulsed. the system s hould wai l for the sensor lO detcctlhe laser's reflection. Mean whil e. the sys tem s hould count how much lime passes from lime the laser was
me
pulsed un ti l th e reflec ti on is sensed. Aft er the re flecti o n is detected. the system s hould use the amoun t of time passed since the laser was pulsed to co mpule the d istance to the obj ec t o f i nteresL The system should then return to waitin g for th e use r to press the buno n so that a new measuremen t can be taken. The above seq uence guides ou r constru cti o n o f a hi gh-leve l Sla te mac hine. \Ve begi n with an iniLial state. which we call SO. SO 's task i to ensure lh31 when our system powers on. it does nol o utput an in correct distance. and it
does not tu m the lase r on (possibly injuring the
o Objectot interest 20 = T sec . 3xl 08 mlsec
Figure 5.9 Laser·bascd distance meas urement .
Let's design a processor to contro l the lase r and the timer and to compute dislHnces up to 2000 meters. A block diagram of the system is shown in Figure 5. 10. The system has a bit input B. which equals 1 when the ulicr pre~seo;, a bu tt on to stan the meas urement. Anothe r bi t input S comes from the ' en,or. and is I when the rcnected laler is detec ted. A bit output L control. the luse r. turning the la,er on when L i, 1. Finally. an N-bit output D indicates Ihe diltance in binary. in units of meterswe' ll aSlume a dis play converts that binary number into a decima l number alld dis plays the resul~ on ''" LCD for the U; cr to read. D will have to be at lealt I I bitl. sill c I I bits cun re prese nt the num ber; 0 to 2047. and we want to measure dillanCc,1 up to 20()() me tefl. Le t'l make D 16 bits.
uns uspecting user). Speci fying th is behavior as a high-level Slate mac hine is straighlforward and seen in Fig ure 5.1 1. Olice th at the high.
Inpuls: B. S (1 bit each) Outputs: L (bit). 0 (16 bits)
0-? L = 0 (laser off) 0 = 0 (distance = 0)
Figure 5.11 Panial high-level state macnine for measureme nl system: initialization.
leve l state mac hine differs from an FSM in tha t the la te's ac ti ons use u dUla type that is larger than one bit (namely. D is 16 bits). However. the hi gh-level slale machine itself fo llows the convention thai every tr::lOsition i~ implicitly A1 Ded ,,; th a rising clock edge. so th e state machi ne onl y transitio ns during clock edges (just like for an FSMt Note that even though the assignl1lents L - 0 and D= 0 look the same. the assignment L = 0 :L
232
Register-Transfer Level (RTL) Design When B= I. the laser should
Inpuls: B, 5 (1 bit each) Outputs: L (bi t). D (16 bits)
slay on for one cyc le. In olher
words. when B= 1. the state machine should tran sition 10 a Slat e that IUrns the Inser Oil. follo\\'ed by a slate that turns th e
B' (buNon not pressed)
0--8,-,
Jaser ofr. \Vc'lI ca ll the lase r-on
st:lte 52 and the laser-ofr slate 53. Figure 5.13 shows how 52 and 53 afe con nec ted in
state
L=O D=O
B'
mentioned in the earlier sequence the
Inputs: B, S (1 bit each) Outputs: L (bit). D (16 bits) Local Registers: DClr (16 bits)
S
Inputs: B. 5 (1 bit each) Outputs: L (bit). D (16 bits)
lion (S=] ). The SIJIC machine remains in 53 while S=O. As events.
each clock cycle would thus corres pond to one meter. Thus wi th a 300 MHz clock. Octr counts the number of mete~s (hal the lascr beam traveled from the measurer t.o the object and back to the measureLTo CO unt Just the dis tance rrom the measu rer t.o the object, we divide Octr by 2 (algebraic Simpli fication of the equa tions in this paragraph veriry that D = Dc t r /2). We' ll pcrfonn this calcul allon III a state we Will call S4. Our fina l hi gh-level state machine is shown in Figure 5. I 5_
(buNon L=O pressed) D=O Figure 5.12 Parti al high-level slate machine for measurement system : wai ting for a button press.
the
high-level state machine. In Male 53. the slat e machine shou ld wa it until the !\cnsor d e l eC ( ~ Ihe laser's renee-
of
233
5.2 RTL Design Method
Dctr =O
L= 1
S4
L=O 0 = Dctrl2 Dctr = DctH 1 (calculate D)
Figure 5.15 High· level staLe machine for measurement sys tem: calculating the value of D.
mach ine
"0-0,0-8
should meanwhile count th e duration between the laser bei ng pul sed and the laser's reflection
L= 1 L= 0 L=O (laser on) D=O (Iaserolf) Figure 5.13 Partia l hi gh-level state machi ne ror measurement systcm: pulsing the laser for one cycle.
being sensed. From the discussion of timers in Chapler 4. we
know Ihm with a given clock period. we can measure time by counting the number of clock
cycles and multiplying that number by the clock peri od (time = cycles' ( I/clock freque ncy». Thus, \\e use a locrt! register. wh ich we' lI cn ll Detr. to count clock cycl es. Th e slate machine increments Dc t r as long 3S the state machine is wailing for the laser's reflect ion. (For si mplicity. we ignore the possibility that no refl ection is ever detec ted.) We must also initialize Dc t r to D. which we choose to do in State 51. \"lith these modifications. our high-level state machine is seen in Figure 5. 14. Inputs: B, 5 (1 bit each) Outputs: L (bit), D (16 bits) Local Registers: Dctr (t6 bits)
B'
50
51
Dctr = 0 (reset cycle count)
50 is the initial state. In state 50, the state mac hine initializes the laser to off by setting L=0 and se ts the ou tput 0=0 too. The machine then transitions to 5l.
51 clears Dc t r to 0 and then wa its unti l th e bUllon is pressed. When the button is pressed. the machine transi ti ons to state 52.
52 turns on the laser. The machine th en transition to 53. 53 turns off the laser and increments Dctr every clock cycle (with a 300 MHz clock. every cycle corresponds to one meter). The machine stays in 53. incrementing Deo- during each clock cycle, until the refl ec tion is sensed, at which time the machine transition to Stale 54. 54 sets the output 0 to the count ed num be r of cycles di vided by two, which corresponds to th e measured distance in meters. The machine then returns to state 51. which waiLS for the bUllon to be pressed again. A real laser-based distance measurer might use a faste r clock frequency in order distance with a greater precision than just 1 meter.
[0
measUJ'l!
5' (no reflection)
"'8--0,0-~(reflectlon) L= 0 D=0
We can summarize the behavior of the high-level state machine in Figure 5.15 as follows:
B
52
53
L= 1
L= 0 Dctr = Dctr + 1
?
(count cycles)
Figure 5.14 Partial hi gh- level state machine ror measuremen t sy tem : wai ting ror the laser reflec ti on and counti ng clock cycles. Once the rcnec ti on i, detected (5-1 ), ou r high-leve l state mach ine should compute the distance
othat i, being mea,ured. From Figure 5.9: we know that 2*0 = Tsec • 3x 10" mlsec. We also know
that the time T in second, is Octr • ( I/clock rrequency). To 'i mpliry the system's design, let's "" ume the clock rrequency i, )x lO" Hz. or 300 MHz. Since light (fttvcb )x l o" me ters pc r second,
The hi g h-level state machine de cribed above is just one type of FSM \-ariation. A different state mach ine variation that was previo usly qui te popular was called Algorithmic Stale Machines, Or ASMs. ASM are s imilar to flowcharts. except that A M include a no ti o n of a clock that enab les transi ti o ns from one slate to another (a traditional flow hart does no t have a n explicit clock concept). ASMs, like flowchans, comain more "srru lUre" th an a Slate mac hine. A tate mac hine can transition from any Slate to an) other lale, whe reas a n ASM restri ts trans itio ns in a way Ihat cau es the omputation I look more like an algorithm- an o rdered seq uence of instructions. An AS 1 u e ' several type of boxes. including s tate boxe , condition boxe , and output box' . A Ms Iypicall) nls a llowed local data storage and data operations. T he advent of hardware desc'ription languages (see Chapter 9) s~ms 10 hu\c large!) nSlru IS supre pl aced th e use of A Ms. as hardware de cripti n language, contain tht" po nin g algorit hmi c stru ctu re, and much more. Thus, we do not de, critx M ' funh r.
234
5 Register-Transfer LevellRTLI Design
Step 2-Creating a Datapath Given a hi gi1 -lcvc J slate machi ne. we wa nl to crea tc a data path lhat .can im~ l e menl all the
data storage and computati ons on non-Boolean data types present III the high-level state machine_ Doing so will enabl e us to then replace the 11I g h - l e,~e l state machme ~Y an FSM that merely controls the datapath . We can decompose the create a datapath step Into severa l substeps:
5.2 RTL Design Method
(a) Output 0 is a data output (16 bits), so we make D an outpul of the dalapath. as shown in Figure 5. I 6(i). (b) We need a register to implement the 16-bi l local register Dctr. Noting thaI the operations on Dc t r are clear (in Slate SI ) and illcremelll (in state 53). we can implement that register by instantiating a 16·bit up·counter, as shown in Figure 5. 16(ii). Furthennore. as we Want 1.0 control when the output 0 changes (no lice th at we only change 0 in slate 54). we instan.
tiale a 16-bit register Dreg at the OUlpu t D. as shown in Figure 5.1 6(iii). We extend the Dc tr COunter and Dreg register control signals to be inpulS to the dalapath_ wi th each signal having a unique name, as in Fi gure 5. 16(iv).
Step 2: Create a datapath (a)
Make all data inputs and out puts to be datapath inputs and outputs. Dreg_cl' _ t-D_a_ta_p_a_th_________~
(b) Imple ment the data storage by adding a reg ister component into the datapath for
every dec lared regi ster in the high-level state machille. Furthermore, we tYPIcally want to add a reg ister component for every data output. (e)
(iv)
Laser-based distance measurer-Creating a datapath We now continue Example 5.2 by proceedjng to the ,econd ' tep of Ihe RTL design method. Step 2--Crea te a data path We can follow the , ub
Dreg_ld
- 1-- - - -- -------.
Dctr_clr
Methodica lly examine each state and each transition, add in g and connecting new datapath components to implement new data computat ions. We add mUltiplexor.; in front of component inputs as they become necessary III orde r to share a component among multi ple signals th at use the same component in different states. Sometimes we find that a component already eXIsts (e.g., a regIster) but that we need to add a new control inpUlto that component (e.g., a clear input on a register to set the register to 0).
A com mon term used to describe the adding of a component into a design is ;nstantiation . Thus. we say that we "instantiate a new regi ster" rather than we "add a new register."' Using the term "instanti ate' rather than "add" hel ps avoid possible confusion with the use of the term "add" to mean arithmetic add iti on (e.g. , saying "we add two registers ' could otherwise be confu sing). When we instantiate a new component, we should give that component a name that is unique from any other datapath component name. So if we instantiate a regi ster. we mi ght ca ll it "Reg;ster} .'· If we instan ti ate another register, we mi ght ca ll it "" Register2.'· Actually, we should give meaningful names whenever possible. So we mi ght ca ll one register "Telllperatl/reReg.'· and another register "" HI/I//;dityReg."" When we instant iate a new component_ we may create addit ional datapmh inputs corresponding to the contro l inputs of the component. For exa mple, instanti ating a register will create a new datapath input corresponding to the register's load and clear control inputs. We should give unique names to each new datapath control input. ideally describing which component the input controls and the control operati on performed. For example. if we instantiate a register named Register}. we mi ght then create two new datapath inputs named Register}_load and Register! J lear. Li kew ise. we may need to utilize control outputs of a component. li ke the out put of a co mparator. in whi ch case we should give tho. e outputs un ique names 100.
EXAMPLE 5.3
235
Oct,: 16-bit
Detr_cnt
Dreg: t 6-bit
up-counter
register
Q
Q
(ii)
(iii) 16 0
(i)
Figure 5.16 Partial dalapath for the laser-based distance measurer. (c)
Noting that S3 wri tes 0 with Dc t r di vided by 2. we insert a righl shifter between Dc t r and 0 reg
10
Dreg_clr DregJd -
implement th e divide by 2, as shown in Figure 5.17.
t-----------+--, +-----------4.
Detr_el' Detr_cnt
o Figure 5.17 The dmapath for the laser-based distance measuremenl sySlem. The resulting datapath in Figure 5. 17 is
<1
very simple dalapmh. but a d3lapath noneLhel
The previous example did not require any multiplexors_ so we -II illu trate separatel) \\ h) sometimes multiplexors must be instantiated . Consider the ample high-le\eI , tate nla -hine porti on shown in Figure 5. 18(a). Figure S. 18(b) show - the daropnth :lftcr implementing the
236
Reg ister-Tran sfer Level (RTL) Design 5.2 RTL Design Method connect 10 Ihe A Hnd B inputs of that adder. bUI Ihose inputs of Ihe adde r already have conncclio,,, from E and F. We Iherefore need 10 instanliale multiplexors. as shown in Figure 5.18(d). I a lice Ihm we creale unique names for each mu x 's control in put. Local regIsters:
E. F. G. R (16 bils)
add_A_sO add_B_sO-+--='F::.J
237
Step 4---Deriving the Controller'S FSM If we created Our d atapath correctl y, deri ving an FSM for the controller is traightfa rward. The FSM wt ll have the same states and transitions as the high-le vel state machine. We merel y defi ne the FSM 's in puts and outputs (all wi ll now be single bits). and replace any data computations in the actions and conditions by the appropriate datapath control SIgna l values. Remember, we created the datapath specifically to carry OUt those computattons, and therefore we should onl y need to appropriately configure the datapath contro l stgnals to Implement each panic ular computation at the right time. EXAMPLE 5.5 Laser-ba se d distance measurer-Deriving the controller's FSM We continue the previous example by goi ng to slep 4 of Ihe RTL design method. Step 4-Derive the conlroller's FSM.
(a)
(b)
The last ste p is to design the co mroll er's interna ls. We can describe the comroller's behavior by
(c)
refining our high-level Slate machine from Figure 5. 15 inlo an FSM. replacing the "high-level:' (d)
Figure 5.18 1"' lanlialing dalapmh Illuxes: (a) sample high-level Slate mac hine portion, (b) dalapath aflcr im plcmcnling TO's aClions. (e) datapath afler implementing TJ's actio ns. res ulting in two sources for each ;'Idder input. (d) dalapa lh after instantiating muxes 10 handle the multiple sources.
Step 3-Connecting the Datapath to a Controller
ac ti ons and conditi ons. li ke Dc t r""O . by actual controller input and o utput signal assignments and condilions, like Dctr _c 1 r=1. as shown in Figure 5.20. Olice that the FSM does nOl directly
indicate the computations that are happening in the datapath. For example_ 5~ loads Dreg with Dctr /2 . but Ihe FSM itself onl y shows Dreg 's load signal being activated. Thus. the overall syslem behavior can be determined from Ihe FSM by looking also at the datapath. Inpuls: B, S
Oulpufs: L, Dreg_elr. Dreg_fd. Dctr_e1r. Delr_ent
Slep 3 of the RTL design melhod is actuall y quile straight forwa rd . We simply create a controller block ha ving the system's Boolean inputs and outputs, a nd we connect the controller block with Ihe datapalh conlrol in puts and outputs.
EXAMPLE 5.4 Laser-based d,stance measurer-Connecting the data path to a controller COlllinuing Ihe previous example. we proceed
10
step 3 of Ihe RTL design me thod:
Step 3-Connect the datapath to a controller_ \Ve connect (he dalapalh to a controlle r as shown in Figure 5. 19. We connect the co ntrol inputs and
oUlPUIS (B. L. and 51 to Ihe controller. and Ihe dala OUlpUt (D) 10 the datapath. We also connect the con troller to the d"tapath control inputs (Dreg_dr, Dreg_ld, DClr_dr. DCIr_CII/) . Normally we don't draw (he c lock ge nera tor block. but we've explicitly shown the clock gene rator in the figure 10 make
clear that the ge nerator must be exactly 300 MHz.
Controller S
Dreg_elr
10 d'Splay
1>
to laser
f6
-{
Ftgure 519 COOlrollcr/dnWp"th
L=O Dreg_e1 r Dreg_ld Detr_elr Detr_ent
(clear counl)
(laser on)
(laser off) (count up)
Detr elr
300 MHz Clock
=0 =0
=0 =1
L=O Dreg_elr = 0 Dreg_Id = 1 Dell_e1r = 0 Detr_cnt = 0 (load Dreg with Dctrl2) (slap counling)
actio n in each state is shown in itali cs in the bouom row: the c rresponding bit signal assignment th at achi eves thal acti on is shown in bold.
~ HOW DOES IT WORK?-AUTOMOTIVE ADAPTIVE CRUISE CONTROL The earl y 2000s saw the advenl of automobi le cruise Datapath
Dctr_eOl
0
(laser off) (clear Dreg)
L=l Dreg_elr = 0 DreQ.,ld = 0 Detr_elr = 0 Delr_eOl = 0
from sensor
Dreg_Id
r-
L= 0 Dreg_elr=O Dreg_fd = 0 Detr_etr = 1 Dctr_cnl = 0
Figure 5.20 FSM description of the controlier for the laser-based distance measurer. The desired L
from bunon ~ f -
L=O Dreg_elr= 1 Dreg_Id = 0 Detr_cl r = 0 Delr_enl = 0
r- ..>
(proce,~or) de~ign for the laser-based d"tnncc measurer.
control sys te ms that not o nl y maintained n paniculnr
front . One way to me,:uure th:n db-lance u ~ a l~er based distance mea urer. "ith the I~~r and :: n: r
C"'.
speed, but also mainlained a particular dislQrlce from
placed in the front grill of the
the car in front-thus slowing the automobile down
circuit and/or mkroproce sor that rolnputt!'~ th distan e. The distance is then mput to the :rui~ control s~stem. "hich dett!'nlline, \\h n lO irK're~ or decre~e th~ automobilt", ~[k"t'd .
when necessary. Such "adaptive" cruise control thus adapls to changi ng highway Irnflie. Adaptiv. erui e controllers must measure the dislonce to the car in
""nil( -led to •
238
Register-Transfer l evel (RTl) Design
5.3 RTl Design Examples and Issues
Recall from Chapler 3 thaI we typically follow the co n~en li on that FS ~ output signals not explici tl y assigned in a sta te arc implici tly assigned O. F0 1l 0W 1I1 £ that ~o n ve ll t l o n , the FSM wou~d look as in Fi gure 5.21 . We mn y still choose 10 explictl y show th e a,sslgnll1Cnt of 0 (e.g .. L = 0 10 state 53) whe~ that as:-.ignmcnl is a key ac tion of a stale. The key aCllons of each stale were bolded in Figure 5.20.
239
A block diagram of the system is shown in Figure 5.22. Such an arrangement is very simi lar to the arrangement in a desktop compuler, where a mas ter processor can read peripheral processor registers-peripherals might include a disk drive,
a CD-ROM drive, a keyboard, a modem, etc. We have just described what is known as a bus protocol. A bus protocol defi nes a sequence of ac tions over a set of data, address. and control li nes, 10 carry out a data transfer over those lines from one processor to another. A bus interface implements a bus protocol for a processor. Let 's implement the bus interface
Inpu/s: B, SOu/puis: L. Dreg_elr, Dreg_d, Dctr_elr, Detr_cnt
L=O Dreg_clr ~
Dctr clr= 1
1
(Cle;;r counl)
(Iaserolf) (clear Dreg)
L= 1 (laser on)
L= 0 Dctr_cnt ~ (Iaserolf) (count up)
1
Dreg_ld ~ 1 Dctr_cnt = 0 (load Dreg with Dctrl2) (stop counting)
Figure 5.21 FSM descripti on of the controller for the l ase r-b~sed distance .l11 ea~ u:e r, u s i ~g the convention th at FSM outputs not explicit ly assigned a value 10 a state are Implicitly aSSIgned O. \Ve wou ld complete the design by implementing thi s FSM , using a 3·bit state regis ter and combinat ional log ic to describe the nex t stat e and output logic. as was described in Chapter 3.
Figure 5.22 Bus interface example. to/from processor bus rd 0 A
for one of the peripheral processors. Figure 5.23 provides a block diagram for a peripheral di vided imo a main part and a bus interface part. The main part's output 0 is an input to the bus interface. Let's assume the peripheral's own address is
another input. called Faddr, to the bus interface. Fad d r might come from a DIP swi tch. or perhaps another register. The bus interface also has inpuls and outputs that connec t to the bus
signals rd, D, and A. Step J of our RTL design method is to
Peripheral
crea te a high-level state machine. Based on the
5.3 RTL DESIGN EXAMPLES AND ISSUES RTL design involves a certain amount of creati vity and insight. Thus, a good way to begin to leam RTL design is perhaps through seeing everal examples. We now provide additional exampfes of the RTL design method. th rough which we also ex plain some detailed issues.
Processors typically need 10 transfer data to and from other processors. They typically communicate
the bus interface waits For an instruction from the master processor to send data. the bus interface should not interfere with what another processor may be writing to the hared darn lines. D. Thus. while waiti ng for a matching address and rd= 1. the bus interface should drive 0 with no value (known as high impedallce. represemed as "Z"). When the bus interface detects a matching address and rd =1. the bus interfa e should output data from the input 0 (from the mai n part) to the output D. However. we must also ensure that 0 does not change while the master processor is reading from the bus interface. \Ve can keep the \"aJue on 0 stable by storing 0 into a local register Ol. As long as the bus interface is not sending data. the bus interface updates 01 wi th the curre nt
such data over a bus, to reduce wire congestion problems that might oth erwise occur (see Section 4 . 10). Suppose 16 different processors each has a 32-bit outpu t connected to a single 32-bit bus
sending data, the bus interFace does
Simple Bus Interface Design Example
EXAMPLE 5.6
Figure 5.23 Bus interface block diagram. bus protocol we defined. a peripheral's bus interface part sends data only if the address on input A matches the address on input Faddr AND the processor requests a read by sening rd to 1. While
Simple bus interface
named D. Suppa e another processor, a master processor. may want to read the output of any of those 16 processors. (Let's call those 16 processors per ipherals. which is a common term for a processor that is aux.iliary to a master processor). The maMer processor ou tput s a 4-bit addrc s, A. that all the 16 peripherals can read. with each peripheral having its own unique address (0000, or 0001. or 0010, etc.). Because the ma' ter proces>or must always set the 'tddress lines to a value. but might nOt always want to read, the ma' ter processor has another output. rd, that the muster proce"or sets to I when reading, and 0 when not reading. So if the mOMer proce sor wonts to read the value in periphcml number five. the maMer proccs>or wou ld 'et the addres, lines A to 0101 , then 'et rd to 1. The master procc"or would then rcad the datu lines D (perhaps storing the read data into a local regi'ter), and then return rd to O. Additionally, the value on D ,hould not change while the m3)tcr procc\sor i\ reading.
value of O. When the bus interface is not upd3le 0 I and out puts 0 I on D. causing 0 to not change during a send. We cun see that the bus interface's implementation of the bus
Inputs-. rd (bit); a (32 bits); A, Faddr (4 bits) Outputs-. 0 (32 bits) Local register. at (32 bits) ~
_ _ --.'rd·
\
protocol can be described by a highlevel siale machine using IWO states, shown in Figure 5.24: a tate in which the bu s interface waits to be
able
10
o ='"Z" 01
D~a1
~a
send data ( lI'ai/MyAddl"l'ss)
and (\ state in which the bus illlelf~lcc
sends dRw ( eIltIOn/a) .
Figure 5.24 High-le\el st3te mnchine of the sending half of a simple bus inter!'""".
2-10
5,3 RTL Design Examples and Issues
Register·Transfer Level lRTL I Design
Figure 5.25 provide . . timin g
:1
sample
of the !o.t~lIc machine's ~tilnds for state IVail/Hy-
di 32.r3111
beh:l\lor.
tw
Address. SO for Selld Dow ). As long as the system is in the \V state. the system OUlpU IS Z on D. When r d= 1 and
A"" Fa d dr. the system outputs the contents of 01 beginning at the nex t cl ock cyc le's rising edge . The sys te m continue :;. to outpu t 0 1 as long as rd= 1. \Vhen read returns to
O.
rt----"l !
rh :
State [
4------J j 4-I w I w ISO I w I w I SO I SO I w I :
outPu~1~--z--I1 -0-1+1--z-11---0-1-+I--.zI Figu re 5.27 PCI card plugged inlo a PC's PCl SIOL Figure 5.25 Bus interface liming diagram . ~
the system
returns to th e lVailMyAddress slate at
the nex t ri sing cl ock edge and hence outputs Z again .
example. Hu ndreds of OIher "Slan. dard" bus prolOcols ex is!. Designers not needing to interface to other chips often defi ne their own bu s protocol for communication,
clk~ Inputs rd - - - '
241
.
.
.
.
Slep 2 i ~ to c rea lt:: a datnpath . 3S shown on the nght III Figure 5.26. The data path contams a ~. bil equalil y comparalOr 10 compare A and Faddr . a 32·bil regiSler 01. and a 32·bil wide !hree· Slale dri ver 10 enable dri ving of D by nOlhing or by 01. A, Fadd r, and 0 are Ihe dalapa!h 's dala
ALL =5 ARE NOT EOUAL.
Figure 5.24 showed two di stinci uses of !he " _ " symbol. In a stal e's ac tions, ":::" meant "assign the va lue oflhe righl side 10 the lef! side," e.g. , D= 01. On a transi tion, ""," meant "the left and right sides are the same," e.g" A- Fa dd r . Be careful nOI 10 confuse
Ihose two meani ngs of Ihe " - " symbol. Some languages use differe", ymbols 10 distinguish !he two mean ings. For example, Ihe C language uses "=" for "assign" and " ==" for "!he same: ' VHDL uses " : =" (or" <-") for "assign" , and " m " fo r "!he same."
inputs. and 0 is the onl y data out put.
Video Compression-Sum-of-Absolute Differences (SAD ) Design Example EXAMPLE 5,7 Video compression-sum·of·absolute differe nces Inputs: rd, A_eQ_ Fadd r (bit) Outpurs: Q l _ld , D_en (bit) rd
A/ter(12004 flatl/ral disaster ill
Indonesia. a o en = 1
32
Ql _'d =a Controller
L--------------===~,BU S
"D :..;a"ta",p",a:.:th" -_ -I-....J Interface
o
n'
news repo rter
reported from rhe SCCll t! by "camero phone... rhe vid eo
was smoolh as 10llg (IS Ihe scelle
wasil " changing
Figure 5.26 Dalapalh (righl) and co nlroller FSM de!ocriplion (Iefl) for Ihe simple bus inlerface. Step 3 i!o 10 conneCI Ihe dalapa th to , controller, a, show n in Figure 5.26. The controller has one eX lemal comro l inpul. rd, "nd also gels a conllol inpul fro m Ihe d,wpal h, A_ eq_ Fad dr, indio caling whelher A cqual' Fa ddr . The conl roller has IWO cOlllrol OUlPUIS 10 Ihe da lapalh, with L 1 d causing 01 10 be loaded wilh 0, and O_ en co ntro lling Ihe Ihree-Slale dri ve r, S tep ~ i, 10 deri ve Ihe coni ro ller' , FSM. We simply replace Ihe dOl" operalions in Ihe higll· level \lale machine of Figure 5.24 by Ihe appropriale co nlrol , ignal;, . , sh wn on the ler. ide of Figure 5,26. We replace A- F addr by Ihe , ign31 A .eq Fad d r, Ihe aClion, of 0- " Z" and of 0-0 by D en-D and D_en-1. and Ihe acti on of 01 - 0 by 0 1 l d- 1. We would Ihen implemenl the FSM u' '''g a "ale regi"er (in Ih i, case only I bil) and cornbin alionulloglc. You ma y have heard of , evera l popular bu'"" like Ihe P I (Pe ripheral olll ponenl Interface) bu, '" a pef\onal compUle r Thole are Ihe buse, Ihal a PC "ca rd" plug' "" 0 In a pc, like !he canl , how n in Figure 5,27 . You ca n \Co on Ihe card the lI1ewl pad, o f Ihe bu,", IIch pad corresponds to one WlfC of the hUI . The bu, prolocol for PCI " fllr morc tolllpl., Ihan Ihe prolocol in Ihe abolt
o
signijiC(lIIfly, Wh en 'he sum! chat/sed (like
pa1l1liflg across the I01ldscape ), the video became \'el)' jul.) .,
because the camera pholle had to trallsm;t complete piclllres rotller tlltm j llst differences. resulting ill / t'u'er fram es transmilled ol'er tht limited bandwidth a/the
camurl phont".
Digitized v ide~ is becomi ng increasingly commonplace. like in Lhe case of the increasingly popular DVO (see Secllon 6.7 for further infomlalion on DVDs). A slraig hlforward digiti zed video consislS of a sequence of digitized pictures. where each picture is kn own as afram e. However. such distiti zed video resul ts in huge data fi les. Each pi xel of a frame is stored a' everal b)tes. and let's sa; a frame contains about a mill ion pixels. Let's assume Lh en Lh at we requ ire about I Mbyte per frame. and we play approximalely 30 frames per second (a nomal rale for a TV), 0 tha.-s I MbYlelframe • 30 frames/sec 30 MbYles/sec. One minUle of video would require 60 sec' 30 Mb},e sec I. GbYle , and 60 mi nu les would require 108 GbYles, A 2·hour movie would require o'er _00 Gbn es. Thai 's a 101 of dala, more Ihan can be downloaded quickl y O\'er the l",emel, or Slored on a DVD, whi ch can onl y hold between 5 Gbytes and 15 Gbytes. In order 10 make practical use of digitized Video wiLh web pages, digital camcorders , cellular telephones, or even with DVD.., we need to compress those files into much smaJler files. A key technique in compressing "ideo i~ to recognize that successive frames often have much similarity. so instead of sending 3 sequen e of digitized pi rures. we can end one digilized piclure frame (a "base" frame), follo\\ed by dala descrihingju I !he dif. ference be,ween !he base frame and !he nexi frame. We can .end j U' 1 the difference
=
=
2-'2
Register-Transfer Leve llRTLI Des ign
5.3 RTL Desi gn Examples and Issues
243
Inputs: A, B 1256-byte memory); go (bit) Oulput sad 132 bits) Local registers: sum. sad_reg (32 bils); i 19 bils)
!go -~~'--'
SAD Digitized frame 2
Digitiz ed frame 1
Digitized
Difference of 2 from 1
frame 1
~ ~
~ [J
(a l
Ibl
~
~
8 ;::s
1 Mbyte
1 Mbyle
sad
S8
~
1 Mbyte
i<256 sum=sum+abs(A{i]-B(i]) i::i+1
0.01 Mbyte
Figure 5.28 A key principle of video compression recognizes th at successive frames have much
similarity: (a) sending every frame as a distinct digiti zed picture. (b) instead. sending a base frame and then difference data. fro m which the origi nal frames can later be reco nSlfll ctcd. I f we could do this for 10 frames. (a) woul d require I M byt~ · 10 = 10 Nlbyt.s. whil e (b) (compressed) woul d requi re o nly I Nlbyte + 9 • 0.0 1 Mbyte = 1.09 Nlb)' tes. an almoSt lOx size red ucti on. Thu~. the difference of these two pi-xcls is 255 - 255 = O. We might compare the nex t pixels of both
frames in that row. find ing the difference lO be 0 agai n. And so on for all the pi xels in tha t row for both frames. as we ll as the nex t several rows. However. when we compute th e difference of the lefl· most pixcl of the middle row. where th ai black circle is localcd. we see that frame I's pixel wiIJ be black. say wi th a value of O. On the other hand, frame 2's corresponding pi xel wi ll be white, say with a value of255. So the difference is 255-0 = 255. Li kewi se. somewhere in the middle ofthm ro\\. well find anothe r di fference , thi time with frame I 's pixel white (255) and frame 2's pc,.1 black (D)-the difference is again 255-0 = 255 . Note that we onl y care about the difference. not which is bigger or smaller. so we are actu ally looking at th e absolutc value of the difference between frame I and frame 2 pixel. By summing the absolute value of the differences for every pair of pixels. we get a number represen tin g the si milarity of the two frames-D means identical, and bigger numbers means less simi lar. If the resulting sum i ~ below some threshold (e.g., below 1.000). we mighl then appl y the met hod of se nding the difference data . as in Fig ure 5.28(b)-we don't exp lai n how to compute the difference da ta here. as th at is beyo nd the scope of this example. If the Sum is above the thresho ld. then the difference between the block is too g reat. so we might in!ltead send the full digitized frame for frame 2. Thu~. vidco with similarity among frames will ac:hic\c a higher compression than video wi th plenty of d i ffe rcncc~. Actually. mO~1 video compre ion mcthods compute , imilari ty not bc tween two entire frames, but rather be twee n correspond ing 16x 16 pixel blocks-yet the idea is the sn me. Computing the sum of absolute differences is ! of a 16.<16 block of pixe" of frame I. and another 256-byte memory 8. holdi ng the corr.'ponding block of fr:llne 2. Memon., Will be di sc ussed in Secllon 5.6. for now. conSIder Ihe memory a, a regi«er hie. and Ignore dcw ti , of the in terfuce to the memo"e,. Anolher cirCUli input go lell, the circlI lI when to be~ln co mpuling. An OUlput sad will pre,ent the re, ult after 'orne number of clock cyc le'.
(a)
Ib)
Figure 5.29 Sum-of-absolu te-differences (SAD) compo nent: (a) block diagram. and (b) high-level slate machine. S tep I of our RTL design method is to create a hieh-Ieve l state machine. \ e can describe the behavior o f the SAD component using the high-Ie"el ; tate machine sbown in Fieure - 29(a)_ We dec lare the inputs. o utputs , and local regi sters sum. i . and sad_reg. The sum ;;'gister will hold the ru nning sum of differences; we make thi s regi ster 32 bi LS wide. The i re£istcr will be used to index into the current pixel in [he block memories: i will range from 0 to and therefore we'll make it 9 bits wide. sad_reg will be connected to the ou tP~t sad (i!"s good procti e to register your data o utputs). so will be 32 bits wide, like the S ad output. The tate machine initiall) waits for !.he Input go 10 become 1. The state machine then inirializes registers s urn and i to O. The st:Ue machine then enters a loop: if i is less th an 256. the state machine computes the absolute value of the difference of th e two blocks" pixe ls indexed by i (the notation A[ i) refers to the data in "ord i of memory A) . updates the runnjn g sum. increments i. and repeat:s. Otherwise. the stale machine loads sad_reg with the sum. which now represents the fi nal sum. and rerurns to me fin" srate to wait for the go signal to become 1 again.
256.
One poin! to re·emphasize is that the order of actions in a state does not impact the resul . because nil those actions occur si multaneously. Thus. for the tnu: in ide the loop. arranging me ac ti o nsas " Sum: sum + abs(A[i)-8[i) ) :i : i T I"oras"i = i T I: 5 urn = Sun + a b s ( A[ i ) - 8 [ i ) does not impact the results. Either arraneemem u " the old vnlue of ; . Slep 2 of our RTL desig n method is to crea te a darapath.-We see from the high-level - e machine that we' l! need a subtmctor. an absolute-value omponem (\\hich \\e ha\i:~ 001 designed ea rl ier. but is . traightforward to design). an adder, and a comparison of i to 256. We build the datnpath s hown in Figure 5.30. TI,e adder will be 32-bits wide. so the -bil input conling from the abs co mponen t wi ll need to have appended for its high _4 bits. S tep 3 is to connect the datapath to n controller block.. < sho\\ n in Figu!1." 5.30. ~OIe that we've defined the interfnce 10 the A nnd B memories. consisrimz of 9. read line. 3ddre.. ~ 1in~. d data lines. Also note that we hawn't explici tl y listed the inputs a';,d outputs t,r the ntroller'~ ~l . a, they can be secn at the periphery of the controllers blo.:k. S tep -' i, to convert the high-Ie" el stnte machin to an FSM. We 'ho\\ the ~I \1O th I ft "J of Figure 5.30. For comcnicnce. \,e\e shown the original h.i.gh-le\el J. ~tl()lb "ro...~ ,."u). and \\e've ... hO\\ 11 their repl3c~ll1enl b) th~ F t action\".
r'
as
l·U
5 Register·Transfer Level (RTL) Design
5.3 RTL Design Examples and fssues
245
RTl Design Pitfalls and Good Practice Pitfall: Assuming a R . t I Written egLS er s Updated in the Sta te in Which the Register Is Perhaps the most com . k ' . th t '. ma n mlsta e m Creallng a high-level state machine is assuming a a regl ter IS updated in the t . h' . " s ate m w Ich the register is written . Such an assumntlOn IS mcorrect and ca n lead t r . . ' a unexpected behavior when the state machine reads th e register m the same state d I 'k . . .. ,an I eWl se when the state machine reads the reo;qer m a transitIOn condit ion lea' h .,... . I h' vmg t at state. For example. Figure 5.31 (a) shows a simp e Igh· level state mach ' E . Ine. xamme the state machine, and then answer the fol. . Iowmg two questi ons: • What wi ll be the value of a after state A? • What will be the fi nal state: Cor D? sad
Figure 5.30 SAD datapath and controller FSM . To complete th e design. we \\ o uld convert the FSM to a co ntro ll er impleme ntati on (3 state reg· i ~te r and combinati onal logic). as described in Chapter 3.
Comparing Software a nd Custom Circuit Implementations In Example 5.7. we said Ihat the output appears after some number of clock cycles. Lei's determine exact ly how many cycles. After go becomes 1. our state machine will spend one cyc le initiali zing registers in 5 /. then will spend two cycles in each of the 256 loop iterations (states 52 and 53). and finally one more cyc le to update the output register in state 5.J. for a total of 1+ 2*256 + I = 514 cycles. If we executed SAD in software. we wou ld likely need more than two clock cycles per loop iteration. We would need perhaps two cycle to load internal registers, then a cycle for , ubtract. perhaps two cycles for absolute va lue. and a cycle for sum. for a total of six cycle per iteration . The cu torn ci rcui t we buil t. al two cyc les per iteration, is thu about three times faster for computing SAD. as uming equal clock frequencies. We' ll see in Section 6.5 that we could aClually build a SAD circuit that is IIlllCh fasler. ~
DIGITAL VIDEO- IMAGINING THE FUTURE.
People 'Cern 10 have an '"'au able appetile for good quality \ideo. and thu, much allention " placed on de'elopmg f..,1 and/or power-efficienl encoders and de.;ode" for dlgHlll video device,. like DVD players and recorde". dlgH.f VideO came"". cell phone, , upponing d'gH.] "deo. 'Ideo confcrenc'"8 UnlL'. TV,. TV ,.t.top Ix". . .'" It\ ,"",re,I,"S 10 Ihmlloward the fUlUre.. ." umlng "Iden enuxhng/det.:cxhng become, even more p
mighl imagine video di'play (With audiol on our wafls al home or wor~ Ihal conlinuaJly dispfay whm' happening at anolher home (perhaps our mom's house) or al a panner ollice on the other ide of the counlJ)'like a vinuaf window to an Iher place. Or we mighl Imagine ponahJc device; that enahle u; 10 continually \CC what wmcone eJ\C 'Wcann!! n tiny camcm- pcrhnps our child or 'I"'U"''''",. TI,o"", de'elopmcnL' could \ ignlficanlly change nur 11\ 109 p~lItcrn\
The answers may surprise yo u. Local ,egislero. A, 0 (8 brts) The value of a will not be 99; a 's value will actually be unknown. The reason is illustrated by the timing diagram in Figure 5.31 (b). State A configures the datapath to load a 99 into R on the next clock edge. and COn(a) figures the data path to load the value of reg ister R into register a on the next clock edge. When the nex t clock edge occurs. both those loads Occur Silllll/' ralleolls/y. a therefore gets whatever o value was in R JUSt before the next (b) clock edge. which is unknown. Furthermore, the final state will Figure 5.31 High-fe,el sml. machine not be D. but will rather be C. The thai behavcs diffenenl than some people reason is illustrated by the timing may e.'(peC'L due to reads of a reruter in diagram in Figure 5. 3 I (b). tate B the arne tate as ",Tiles to that ;'cister: (al smle m3 hine. (b) timing di3i.un, configures the datapath to load 100 into R on the next clock yele. and config ures the controller to load the next tate ba ed on the transition condition. R is 99. and therefore the transition ndition R
2-16
Register-Transfer LevellRTlI Design A~Slllnin g
5.3 RTL Design Examples and Issues
th at (he designer Q to equal 99 and
actuall y \\ant~ the Iinal swte to be D. then a sol ution is to add an ext ra swte before
Local regislers:
R. Q (8 bits)
reading tbe value of a register that we assi gn. Figure 5.31(a) shows a new st~e 111~~chiJ1e in wh ich the
assi £nmem of Q=R has been mo\:ed 10 state B. after R=99 has taken effect. Fu rthermore. the state machine has a new state. B2.
th at simply allows R to be updated with the new value before we read
that val ue in the transition cond itions.
T he
liming
diagram
(b)
in
Figure 5.32(b) shows the behav ior Figure 5,32 High-level state machine that avoids reading j ust-assigned regis ter : (a) state machine. th;t the designer ex pected. (b) timing diagram. An alt ernative so lution for the transition issue in thi s case would be to uti lize comparison values that take into account that the old value is being used. So instead of comparing R 10 100. the comparisons might instead compare to 99. Avoid ing th is pitfall is the reason that we included state 52 in Examp le 5.7. Pitfall: Read ing Outputs Another common mistake is 10 create a high-level state machine in which an external output i read in the state machine. Outpu ts can only be wrillen and can not be read. For exam ple. Figure 5.33(a) shows an inval id high-level state machine-the read of P in state T is not allowed. If you wish to read an output . then create and use a loca l register. Figure 5.33(b) shows use of a loca l register R 10 avoid reading output P.
Inputs: A, B (8 bits) Outputs: P (8 bits)
(a)
Inputs: A. B (8 bits) Outputs: P (8 bits) Locat register: R (8
bits)
(b)
Figure 5.33 (a) Read ing an output is not allowed. (b) using a local register.
Good Design Practice: Registered Data Outputs fI 's a good idea to always en ure your design has a register at every data ou tput. Doi ng so prevent;, those outputs from displayi ng spurious values. For example. the state machi ne of Figure 5.33(b) could be imp lemented as a datapat h in whi ch output P is directly con· nected to the output of an adder, as shown in Fi gure 5.34. P wi ll therefore output spurious values for 'ome time after R i loaded wi th A. while the addition is being computed. Fur· thermore. If B or A changes in some other states. P will also change. but such change is hkely not the intended behavior of the state machi ne-P should only change when we ex plicitly assign P in a Mate. Another problem is that any proces 'or usin g the P output
-,
-.
-
--
------------
247
must take into account the adder when computing longest register-to-register delays to determine a circuit 's critical path (see Section 5.4). Therefore, we wi ll follow the design practice of always pUlling a register directly before the data output, as shown in Figure (a) 5.34(b). Even if we don 't explici tly declare the register as a local register, we always assume it is there in interpreting the high(b) level state machine, and we always add that Figure 5.34 (a) P will exhibit spurious register when creating the datapath. Alterva/ues. (b) regislering P solves the problellL nat ively, we can explicitly declare that register, and then assume that the output is directly connected to that regi ster-thi s is the approach we took in Example 5.7. in whicb we declared the register sad_reg . !t's good practice to no/ read this register. the register's on ly purpose is to connect to the Output port. Regi stering data ou tputs does have the potential di sadvantage of delaying wriles to the output port by one cycle, depending on the example_
Data-Dominated RTL Design We can consider RTL designs as falljne into one of two Calegorie : contral-dontinated designs and data-dominated designs. A cOlltrol·dom illated desigll is a design whose controller comain mo I of the omplex ity of the design. When creatine such a desi!!n a desi!!T1er focu es mostlv on the design of the controller, meaning design effort -g~e mo ~Iy into defining ~e state behavior of the system. Once the desi!!ner has defined thaI tate behavior. hei be can derive the datapath straightforwardly from that stale behavior. A contral-dominated design typically responds to eXlemal inputs in a precise anlQun! of time. and typi a11~ bas a simple datapath. A data·dom illated desigll is a de ign whose datapath contains mo t of the mplexity of the design. When creating such a design. a designer focu es mostl~ on the design of the datapath. meaning de ign effort goes mostly into instantiating and inrerronnecting datapal.h components. Once the designer has defined lhe dampath. h she an define the controller's state behavior straightforwardly. A data-dontinated d -ign lypi :ally has a lot of para llelism in its datapath. and the datapath ma_ be large. For a d:lla-doffilnated design. de igners oflen ski p the first tep of our RTL d ign method of Table -.1. The laser-based distance mea urer example in the pre\~ou-. uon \\ as an
248
Register- Transfer Level (RTL) Design
5.3 RTL Design Exa mples and Issues
catego ri es. The example of lhe si mple bus interface was an exa mple of a d es i g ~ lhat has a similar amoulll of contro l and data des ign. The VIdeo compressIo n SA D C" c ull , at least the way we designed it. was also a mix of control and d a t ~. . RTL design is very mllc h a creati ve process. Two desIgners may come lip wIth very different desions for the same system. fo llowing perh aps d Iffe rent des Ign methods, wllh those designs~differing in te rms of performance. size, and o Lhe r metrics.
3-tap
FIR Filter Design Example
12
As our previous examp les we re ei ther contro l-domi na ted or a mi x of control and data, we now provide an example of a da ta-dominated design.
EXAMPLE 5.8
249
Notice how lhe data moves to the ri ght on each clock cycle, so that register xtO holds the current mpu t sample, X tJ holds the previous input sample, and x t2 holds the sample before the previous one. For the example, we'll assume data is 12 bits wide. FIR filter
X(I)
x(I-I)
xtO
Xl1
12
x(I-2) xt2
12
y 12
Figure 5.36 Beginning to bui ld the datapalh for the FIR fil ter-inserung and connecting thex(I). x(l -f ). and x(I-2) registers.
FIR filter A. digita l fi lter takes a SLream of digita l inputs and ge nerales a stream of digita.1 ou tpu ts with some
feature of the input stream removed or modified. Figure 5.35 shows a block diagra m of a popular digital filter known as an FIR filter. X and Yare N-b its wide each. such as 12 bits each. As a fi ltering y
x digital fil ter
Now we need another register for each tap to hold the constant value cO . c1. or c2-we·U worry later abo ut how those registers will be loaded. We' ll also need a multiplier for each tap. to mul tiply the tap·s X value by the Constant C val ue. The datapath with the constant registers and multi pliers is shown in Figure 5.37.
12
elk Figure 5.35 General block di ag ram of an FIR fi lter.
x example. consider the following stream of digital tempera ture values on X comi ng from a car engine temperature sensor sampled every second : 180. 180. 18 1. 240, 180, 18 1. That 240 is probably nOf an acc urate measuremenl. as a car engine's temperatu re can nOI j um p 60 degrees in one
clk
seco nd. A digital filter wou ld remove such "noise" from the inpu t stream. ge nerat ing perhaps an
output stream on Y like: 180. 180. 181. 181. 180, 181. An FIR filter (usuaUy pronounced by saying the leiters ··F· ."f"" ··R"). short for ·'Fi nite Impulse Re ponse·· filter. is a popular general digi tal fi lter design that can be used for a wide variety of fi ltering goals. Figure 5.35 shows a block diagram of an FIR fi lter. The basic idea of an FIR fi lter is simple: the present output is obtained by mu lti plying the present input value by a constant, and addi ng that resuh to the previous input value limes a con lant, and adding that resull to the next earlier input val ue limes a constan t. and so on. In a se nse. adding 10 previous va lues in th is manner
results in a weighted ave rage. We describe digital fi ltering and FIR fi lters in more detai l in Section 5.11 . For the purpose of this example. we merely need to know lhat an FIR fi lter can be described by the following equation: y( r) = cOxx( r)
+ c l xx(t- I ) + c2xx(r-2)
An FIR filte r with three term. as in the above eq uation. is known as a J-tap FIR fi lter. Real FIR filter; typicall y have many tens of taps-we u,e only three taps for the purpose of illustration. A filter de. igner using an FIR filter achieves a particular filtering goal s;mply IJY c1r00s;/l8 lire FIR filter 's con.'ilGl/tr. We wi h to de~ ign a ci rcu it to implement an FIR filter. Becau." the FIR filter eq uation is ju t data tran
--
•
~
~
#
~
-
- -- - - - - - - - - -
Figure 5.37 Ex tendi ng the datapath for the FrR filter-inserung and connecting the cO_ c L and c2 regis ters, alo ng with the multipliers. for each tap. For simplicity. clock connections are DOl sho""Il. and all data lines are assumed to be 12 bits wide. The out put Y is the sum of each tap·s prod uct. We can thus insert adders to compute !be sum_ -.38. We have completed the heart of the FIR filter datapath design. We DOW need to pro\"idc: a method for a user to load values into the constant registers cO. c1. and c2. LeCs rn:ate!lIlOlbetin put C to the fi lter. a load line Cl. and a 2-bit address Cal and CaO_ that the filter user an use to load a panicular constant reg ister. Ca I Ca 0-00 indicates that register cO should be loaded I indica tes th at c I should be loaded. and 10 indi ates that c2 hould be loaded_ L ding of the , on input C into th. appropriate register occurs on a lock edge only when CL-l. We <= trnigbtforwardly design the circuit for such loading using a decoder. as shown in Figure _19. ~ address lines Ca I and Ca 0 feed into a 2x4 decoder. thus enabling the appropriate register (JlO{e that address II is unused). The load input CL is connected to the decoder" enable input_ 'Ole that.. -\ 3IS<' added a register at the Y output. \ hich is genernlly good design practi _ i~ such l ~"'ter ensures tlle output doesn· t Ruc luute a intemlediate products and sums are mputed. and rectu.;, the likelihood of the user accidentally extending the riti al path b~ nne<:ting tttrough. \0( of combinational I gic before loadi ng Y il1lO a register. and we can connect th al sum to the aUip Ul Y. as shown in Figure
150
5 Register-Transfer Level (RTU Design
251
5.4 Determining Clock Frequency
~ HOW OOES IT WORK?-VOICE QUALITY ON CELL PHONES_ Cellular telephones have become commonplace over the past decade. Cell phones operate in environments far noisier than regular "Iandlinc" telephones. incl uding noise from 3U1omobiJes. wind. crowds of
x clk
lal king people, elC. Thus. fi heri ng OUI such noise is especially important in cell phones. Your cell phone contains at least one, and probably more like several, microprocessors and custom digital circuits. After co nvertin g
y . th .... output y '111 Ih't.: FIR filler as Ihe Figure 5.38 ComplI lIllg
arc
:J.~')ul1led 10
SlIlll
Our RTL dC'ign me lhod "lVolve, IIVO ' Ieps afl er de, igning Ihe dalap:ll h
10
complete Ihe con-
troller. HO\l.cvcr. thl \ pUrll cu lar dc\ ign doc\ nOI requi re a contro ller. nOI e\en n simple one!
oj a
(/ma- (/OI1lIlUlleti
n,iJ
rle,\ix".
C o mpa rin g Soft wa r e a nd Custom C ircuit /mplemcntation,~ It " Inle rc, tlllg to co mpare the perfo rman ce of Ilte ha rd wa re "np/e me lltati o n of a 3-lap fIR filter with a ,oft"'are imp le mcllIa ti o n. The c riti ca l path goc, fro m Ihe X t and c regi, ter,. throu g h n ne multiplier. and th ro ug h two add.". be fo re rc.lc hlltg the Y rcg ;;tcr yreg.
_~_ _ _ _ _ _ _ _~_
<0
_
audi o
signal
from
the
noi sy environment. and nOlice how much Ic\
noise
you hear Ihan is probably aClUall y heard by the microphone. As circuits continue to improve in speed ize. and power, filtering will likel ) improve further.
Some slate-of-the-an phone~ may even use two microphones. coupl ed wiLh beam forming techniques (see Secti on 4 . J 3). to focus in on a user's voice.
of Ihe I"P prod uclS (all dala lines
Figure 5.39 Finalll.lOg the FIR fi ltcrdalapath wi th circuitry for loading the constalll rcgisters. We've aJl,o added a reg l'~lc r Oil the Y output. which is good dc~ i gn prac tice. The crit icn l pu th- the longest rcg/\ lCHo-rcg/\ lt:r delay- if., <,hown :1... a dotted linc.
l'.\frClI/e l'xm1lph,
analog
microphone into a digital audio stream of bits. part of
be 11 bit:-- "ide).
ewmplt' H "u",.o ed an
the
the job of those di gital syslems is 10 fi ller OUI the background noise from the audio signal Pay anenlion next lime you talk [Q someone using a cell phone in a
Fo r hard ware implementati o n. let's as ume th at the adder has a 2 ns dela). Let' also ass ume that c haining the adders together res ults in the delays adding. SO that ("'0 adders c hained together have a delay of 4 ns (detailed ana ly is of the inte rnal gate of the adders co uld show the delay to actua ll y be sligh tl y less). Let ' as ume the mu ltipl ier has a 20 os de lay. Then the criti cal path . o r lo ngest register-to-register delay (to be di cussed funher in Secli o n 5.4). wo ul d be fro m cO to yreq. going thro ugh the multiplier and two adders as shown in Fig ure 5.39. That path 's length wou ld be 20+4 = 24 ns. , o te that the path from clI o yreg would be eq ua ll y lo ng, but no t lo nger. A critical path of 24 n means the datapat h could be clocked at a freque ncy of I / 24 ns = 42 M Hz. In o ther wo rds. a ne\\ ample could appear 01 X eve ry 24 ns. and new o utput wo uld appear at Ye\'e l)' 24 n . Now let's consider the hardware perfonnan ce of a larger ized fi lter: a 1000tap FIR filte r rather th an a 3-tap filt er. The main perfonnance difference i that \\ e- Il need to add 100 va lues rath er th an just three. Recall fro m Sec tio n 4.13 that an adder tree is a fas t wa) to add many values. One hund red values will req uire a tree wi th seven le\'e ls- - 0 addition _ then 25. then 13 (ro ug hl y). then 7. then 4. then 2. then I . SO the total dela~ wo uld be ~O ns (for the multiplier) pl us seve n adder-delays (7*2ns = 14ns). for a total dela) of 3-1 05. For a software imple mentation. we' ll aSSume 10 ns per instruction. _ -ume h multip licati o n o r additio n wo uld req uire two instructions. A 1000tap filter \\ o uld need a pprox imately 100 multiplication and 100 addi tions . so the to ta l ti me \\ ould be (100 multi plicatio ns · 2 instr/mult + 100 add it ions * 2 instr/add) * 10 ns per in -tru tion = -WOO os_ In other words. the hardware implementatio n wo uld be mer 100 tim' Ia, ter ( 3-1 ns) th an the software implementat io n. hardware implementation uld there fore pm: 100 lime mo re dala th an a software implementation. res ulting in much better tiltenng.
5.4 DETERMINI NG CLOCK FREQUENCY RT L de igll produces a processo r. co nsisting of a datapJth und l controller. in' ld th da tapa th and cont ro ller are registers. a nd reg iste.." reqUI re ad'" , ign:ll . .-\ ... 1.' ' lgn;1] m us t have" panic ular frequen c) . The frequenc~ \\ ill d~tenlllllc ho\\ f,bt th , ) , t III \\(11 exc ' ut e i t~ >pecilkd tlIS" . b\ iou,I) . a 10\\ 'r f~ uenc) \\ ill re,ult III , 1.,\\ ' r \ · Utlc'l\. \\ hile a hi g her frequc nc) \I ill result in a fu>tcr c\ ·utl o n. <'(1\ '" '1~ . J I.trg r period i. , 10\\ <1'. \\ hilc 1I "Illllkr I 'nlxf I' fast'r.
252
Reg isler-Transfer LevellRTLI Design
5.4 Determining Clock Frequency
Desio"ers of dioita l circui ts often (but not always) want their systems to execute as fast as ~~ssible. Ho~'ever. a designer cannot choose an arb itraril y hi gh clock freq uency (meaning an arbi traril y sma ll period). Consider, fo r ex an~ple. thestmple ClrCU !! m Ftgure 5..l0. in which registers a and b feed th ro ugh an adder Into register c. The adder h as a delay of 2 ns. me;ni ng that when the adder's inputs change .. the adder's outpu ts WI ll not be stab le unt il after 2 ns-before 2 ns, the adder's out puts wtll have spunous values (see Section -1.3 for a descrip tion of spurious val ues appearing at an adde r's outpu ts): If the designer chooses a clock period of 10 ns, the circu!! should work fin e. Shortentng the period to 5 ns wi ll speed the execution . Bu t shortening the period to I ns will result in incorrect ci rcuit behavior. One clock cycle might lond new va lues into reg isters a and b. The next clock cycle wi ll load reg ister c I ns Imer (as well as a and b). but the output of the adder won' t be stable until 2 ns have passed. The value loaded into register c will thus be some spurious va lue that has no useful meaning . and will not be the sum of a and b. Thus. a designer must be careful not to set the clock freq uency too high. To determine the highest possible frequency, a designer must Figure 5.40 Longest path is 2 ns. analyze the enti re ci rcuit, and find the longest path delay from any reg ister to any other regi ster. or from any circu it input to any register. The longest reg ister-to-register or input-to-regi ster delay in a circuit is known as the circuit's critical pal". Designers then choose a clock whose peri od is longe r than the circuit's crit ical path . Figure 5.4 1 illustrates a ci rcuit with at least four poss ibl e paths from any register to any other register: One path starts m register a, goes through the adder, and ends at register c. This path 's delay is 2 ns. Another path starts at register a, goes through the adder, through the multiplier, and ends at register d. This path's delay is 2 ns + 5 ns = 7 ns, Another path starts at regisler b, goes through the adde r, th rough the multi plier, and ends al register d. This path', delay is al,o 2 ns + 5 ns 7 ns.
=
The la'l path >tarts at register b, goe, through the mU ltiplier, and ends (It regi"er d. Thi , palh \ delay i, 5 ns.
• CONSERVATIVE CHIP MAKERS, AND PC OVERCLOCKING, Chip makers usually publish their chips' mlL,imum Max (2,7,7,5) = 7 ns
Figure 541 Dctenni nins the critical pOIh.
The longest path is thus 7 ns (there arc aCluall y two ,ueh path,), Thus, Lhe dock penod mU\1 be al lea'l 7 n'>,
--
-
-------------------
253
The above analysis assumes that the onl y delay between regIsters IS caused by logic delays. [n reality, lVires also have a delay. [n Ihe 1980s and 1990s, the d~lay of logic dominated over the delay of wiresWire delays were often negligible. But in modem chip technologIes, the delay of wires may equal or even exceed the delay of log ic, and thus wire delays cannot be Ignored . Wire delays add 10 a palh 's length just as logIC delays do. Fi gure 5.42 ill ustrales a path length calculatI on wllh Wire delays included . Furthermore, the above ana lysis does not consider se!Up times for the regislers. Recall from Section 3.5 Figure 5.42 Longest path is that flip-flop inputs (and hence register inputs) must be 3 ns con idering wire delays. stable for a specified amounl of time before a clock edge. The setup lime adds to the path length. Even considering wire delays and etup times, designers typically choose a clock period thaI is stiliiollger than the critical path by an amount depending on how conservati ve the deSIgner wants to be with respect to ensuring the circuit works under a varie!)' of operating conditions. Certai n conditions can change the delay of circuit components, condilions like very high lemperature, very low temperature, vi bration, age, etc. Generally, the longer the period beyond the critical path, the more conservative the design_ For example, we might determine that the critical path is 7 ns. but we might choose a clock period of IO ns, or even 15 ns, the latter being qu ite con servative, If low power is a design goal , then a designer might choose an even longer periO
clOCki ng frequency somewhat lower than (he real
mMimum- pcrhap 10%, 20"", or even 30% lower. ueh conservatism reduces the chances thn! the chip \\i ll fuil in unnnlicip3loo silualions. such as extremes of hot or Id weather, or slight vnrintiom in Ule chip m!U1ufucturing process, Many pcrnlnal computer enthusiasts have taken nd,".ullOge of such con",,,,,,,hm b} "overclocking" their PCs, meaning to sct the clock frcquenC} higher than J
chip's published mal imum, b} cbanging !he PC's 81 (basic input/oulput S) tem) sening .. NUJ1lcrOUS posl stnoso on !he su ;;es :md f:lil=- of trying to o''erdock ne:ui) .' IJ PC ~_--it the norm is about 10'lhIgher lII.ln !he puNosbod ma:~imum. ' \\ . I don't f'e\"'QnUllef'kJ \erckx: ng ,flY one, you ma~ d:Ull:~e !he ml="""", ,.. due 1(\ O\erhe:lting). but i"~ lOt re.ting tft ~ tb-: '" ~ ~
v..
prescO\..'e of C(l(L~n all\ • dc--.Ign
5 Register-Transfer Level (RTL) Design
5.5 Behavioral-Level Design: C 10 Gates (Optional)
255
int SAD (byte A (256J, byte B (256]) II not quite C syntax { uint sum; short uint i; sum = 0; i =0;
Figure 5.44 C program description or a sum-or-absolule differences
while (i < 256) { sum = sum + abs (A/ij - B(ij); i= i + 1:
computat ion- the C program may be easier to develop and easier to understand th an a state machine.
relu m (sum);
That code is much easier to understand ror mOSI people than Ihe high-level stale machine in Figure 5.29. Thu • ror some designs. C code (or somelhing similar) is the mosl natural tarring poinL To begin the RTL design melhod. we could conven Ihis code to a high-Ie, el lale machine_like thaI in Figure 5.29, and then proceed to complele the RTL design method and hence design the circuiL
Figure 5.43 Crit ical paths throughout a circuit: (a) within a datapa th . (b) within ;] controller,
(c) be",een a controller and d.l. pnth. B. and C. the n the possible paths are: A- >A , A->B, A- >C. B->A. B->B, B->C, C- >,-I. C->B. C->c. for 3*3 = 9 po sible paths. For N=50. there may be up to 2500 pos, ible paths. Because of the large number of possible paths. automated tools ~an be of great assi tance. Timing analysis tools automatically analyze all paths to determlOe the longest path, and may also ensure that setup and hold times are saltsfied th roughout the CIrcUIt.
5.5 BEHAVIORAL-LEVEL DESI GN: C TO GATES (OPTIONAL) As trans i ~t or pcr ch ip continue to increase and hence dc. igners build more complex digital systems that use tho e additional transistors. digita l ystem behavior becomes increasingly diffic ult to understa nd. Frequently. a designer bu ilding a new digital y tern find s it useful to fi r t descri be the de ired system behavior u ing a programming language. like C. C++. or Java. in order to fi rst get that de ired behavior correct. (Alternati ve ly. the designer may use the high-level programmi ng constructs in a hardware descripti on language. li ke VHDL or Veri log. to fi N get the desired behavior correct.) Then. the des igner convens lhat programmi ng language descri plion 10 an RTL design. by following Ihe RTL design melhod Ihal usua lly Sians wilh a high-level Siale mac hine RTL descripli on. Converting a syslem's programming language de!>Criplion 10 an RTL descriplion is known as beha vioral-level design . We-li lOlroduce behavioral-level design tIl,ing an example.
EXAMPLE 59
SUI -of absolute-dlHerences Recall bamplc 5.7.
In
C for video compression
which we crealed a ,um-or-ahsolutc-(hrrcre nce, component. In Ihat eJ;ample. we 'tdrted with ~I hlgh.lc\'cl , late machine-but Ih.1I \ UlI C nmchlllc wa., n 't vc ry easy. to undeN •• nd We can more eaSily descnbe Ihe compulallon of Ihe , um of ab,ol ule d,rrerence, u~,"g C code. a, ,h""n In I.gure 5.4-1 111
Ii is instructive 10 define a Struclured method for converting C code 10 a high-level stare machine. Defining such a method makes clear 10 us thai C code can be autamatically com piled to either software on a programmable proces or. or 10 a cllsrom digiral circuit_ We poi nt Oul lhal moSi designers lhal stan with C code and then continue with RTL design do lIot nece saril y follow a particular melhod in performing such cOI1l·ersion. Howe\er. automated lools do fo llow a melhod having some similarities to the one we now describe. \>'-e also poi nl OUI lhm lhe conversion melhod wiLl somelimes result in "extra" tates that you might notice could be combined Wilh other slales-these extra states would be combined by a later optimi zation slep. though we' lI combine some of them as we follow the method. We consider lhree Iy pes of staiemenlS in C code-as ignment statemenLS_ while loop. and condilion statements (if-lhen-else)-and provide higb- Ie\ el tate rna hine templales for each such Slalemenl. An assignment tatement in C largel = expression: . . Iranslates simply into a stale in a Slate machine. wi th lhe Slate's actions carryi ng oUl lhe assignmenl. as shown in Figure -.45. Figure 5.45 An if-thell 131ement in C trans- statement. lates into a Slme Ihm checks Ihe condilion of Ihe if Slmemen!. and branches 10 lhe sime for lhe thell part if Ihe condi lion is lrue. Olherwi se branchi ng pas l Ihose tutes to .f (cond) { (then Slm II lhen stmts an end hlle. as shown in Figure 5.-16. + We can tranJate an if-rhell -else stmemenl in inlo Il similar -late mac hine wilh a stUiC Ihut c h~'Cl..s lhe onditi on of the if stmemOn! . but
.
Register-Transfer LeveII RTL} Design this time branc hing to states for the + else pan if the if condition is fal se _ as shown in Figure 5.47. if (cond) ( --pond ~ The else pan commonl y con1/ then stmts (then stmts) (else stmts) tains a nothe r if state ment as C programmers may have multiple else ( else if pans in a region of code. II else stmts (end) Finally. a while loop statement in C translates into states simi lar to an if-then statemenl. excepl that Figure 5.47 Template for if-then-else Slnternent. after executing the while's statements. if the while condition is true, the state machine branches back to the condition check. rather than to the end state. as shown in Figure 5.-18. Only when the condition is while (cand) ( false can we reach the end slale. (while stmts) II while stmts Given these simple templates. + we can conven a wide variety of C prog rams to high-level state machines. from which we already know how to create circuit designs Figure 5.48 Templme for while loop statement. following our RTL design method.
~
+ -.-J
EXAMPLE 5.11
SAD C code to high-level state machine conversion We wish to Conven the C program de cription of the sum-of-absolute differences example of Example 5.9 to a high-level state machine. The code is shown in Figure 5.5()(a)_ written as an infinite loop rather than a procedure call. and using an input "go" to indicate when the system should co mpuLe the SAD. The "while ( I )" statement, afler some optimization, translates just to a transition
from the last state back to the first state. so we' lI hold off on adding that transition until we have formed the rest of the state machine. We begin with the statement "while (!go):' which based 00 the template approach translates to the states shown in Figure 5.50(b). Since the loop has no statemeots
We are given the C-like code shown in Figure 5.49(a). which computes the maximum of two data inputs X and Y. We can translale that code to a state machine by first translaling the if-then-else statement to states using the method of Figure 5.47. as shown in Figure 5.-l9(b). We then translate the lhen statements 10 states. and then the else statements. yielding the final state mac hine in Figure 5.49(c).
Output: int sad mainO
if(X >Y) (
r------------,
Max X; : r-----------" =
else (
r------------,
:
Max=Y;
:
r-----------"
(the n stmts) (else
stmls)
:
uint sum; short uint i; ; 1 while (1) { ,,.."
sum = 0; i = 0;
____.1
(':
i=O
:
I
I
:
:
(d)
L_________________ J
I
-~;;~;-(i~-256){- -- - ---- --------i
(b)
¥ go
.go
sum=O
!
!
:
------- --- -- ---- -
I::
!go
!..______
:
!
1---------------, /"
:
! /~
I:'"
(c)
sum = sum + abs(A(i) - Bn)); :
___ L=:.U·_1~ _________________ . _J (. ) !",o,"m
; ______________ J. __
j
l(k256)j . - .
.-.
:
:./'
i
I
L ______ __________
(9)
('~)c?--J
(a)
(b)
(e)
Figure 5.49 Behavioral-level design slani ng from C code: (a) C code for compuling Ihe max of two numbers. (b) translating Ihe if-Ihen-else Stalemenl 10 a high- level 'tnte mac hine. ( ) translaling the Ihen and else ,tatements 10 states. From the stale machine In (c). we could usc our RTL design method 10 complete the deSIgn. Note: max can be Implemenled morc efficie ntly: we u e max here (0
:
!
: while (!go);
i--------------i "
{
j Inputs: uint X. Y OutPUIS: uint Max
:--- ---------!(!g-~)-l,
Inputs: byte A(256).B[256) bit go;
EXAMPLE 5.10 Converting an if-then-else statement to a state machine
:
257
5.5 Behavioral-Level Design: C to Gates (Optional)
~
256
provide an easY-lo-understand example.
Figure 5.50 Behavioral-Ie,'el design of the sum-or-absolute difleren,.., ,'Ode; (3) ongin31 C code, wrillen n~ an infinite loop. (b) lrnnsiating the statement ',\, hile l!g.o):'· to 3. ,Ute :tu~~ (e) simplified stn lc~ for "while (!go):" and states for the !bSignmcm ,tll "ment that (-.: UQ\\~ (d) merging tit two assignment ~t3tcS into one. (e) insening the template fOf the nt" \ t \\hil 10l'P. (f) inserting the SIBle, ~ r th!lt \\ hil' loop. merging (\\ 0 3.~ ignmenl '19.t 'menlS tOto one. ,,) the rirul high-Ievd , tnte ma hine. \\ ith the ',\, hi Ie (I)" inciud,'m the '3>t ,.u~ - t the fin-I SHIlt'. and \\ ith ob\ioll'\l) unnccessat: st..ltc.:o, ~mo\\.'(.L
258
Register· Transfer LevelIRTL) Design
5.6 Memory Components
III the loop bod). \\c;! can simplify the loop 's Slates a.s shown in Figure S.50(c), Fi g l~re 5.50(c) also thl! ~ Iah:: .. for the next IWO S t ~ICI11CI1IS. which are assig nment MalCl11c nt s. SInce I~OS~ two a.. ,i!!nmenb could be done si multanl!ollsly. we merge the IWO Sl~iles illlo Olle, as show n 111 Flgu~e 5.56
259
Random Access Memory (RAM )
~ho\\.s
A RAM is logicall y the same as a register file (see Section 4.IO)--both components are memories whose words (each of which can be thought of as a register) can be individually read and written using address inputs. The differe nces between a RAM and a regi ter file are: The size of M- We typicall y refer to smaller memories (from 4 to 512 or perhaps even 1024 words or so) as regi ster fi les. and larger memories as RAM . The bit storage implementation-For large numbers of word. a compact imple. mentation becomes increaSingly imponant. Thus. a RAM typically uses a very compact implementation for bit storage. rather than u ing a Rip-Rop.
le"el stiJle 1113chine we des igned from sc ratc h in Figu re 5,29. \\'e will need to map the C data Iypes 10 bits at some point. For exa mple: the C code, de~lares i to be a shan unsigned integer. whi ch means 16 bits. So we could dec lare 1 to be 16 bits In the high-level s t3le machine. Or. knowing the range of i to be to 256. we cou ld instead de fine i to be 9 bib (C doesn't have a 9-bil wide data lype). \Ve could then proceed to des ign a contro ller and dalapalh from this stale machi ne. as was done in Figure 5.30. Thu~. we can translate C code to g~ltcs. using a straightforward automatable method.
The memory's physical shape-For large numbers of words, the phy ical shape of the memory·s implementation becomes imponant. A tall rectangular hape will have some shon wires and some long wi res, whereas a square shape will have all medium length wires. A RAM therefore typicall y ha a square hape. to reduce the memory's critical path . Reads are perfonned by first readi ng out an entire row of words, and then selecti ng the appropriate word (column) out of that row.
a
There's no c1ear· cut border be tween what defi nes a regi ster file and whal defines a RAM . Smaller memories (typicall y) tend to be called regis~er files , and larger memorie tend to be called RAMs. But you ' ll often see the tenns used quite interchangeably. A typical RAM is single-ported. Some RAMs are dual·poned. Adding more pons 10 RAMs is much less common than to register files, because a RAM ·s larger size makes the de lay and size overhead of extra pons much more costly. 'everthele . conceptuall~. a RAM can have an arbitrary number of read pons and wri te pons. ju t like a register file. Figu re 5.52 shows a block diagram for a ID24x32 sing le-pon RAM (M = 1024. N =32). data is a 32-bit wide set of data lines that can serve either as input lines during writes or as output lines during reads. add r is a JD·bit input serving as the address lines during reads or wri te. rw is a I· 1024 x 32 RAM bit control input that indicates whether the present operation should be a read or a write (e.g .. rw = 0 means read. rw = l means write). en i a I·bit control input th3t enables the RAM for reading or writing-if we don·t want to read nor write during a particular clock cycle. we set en to 0 to Figure 5.52 IO~J,3~ RA\I prevent a read or write (regardless of the value of r\~). block symboL
Through the previous exa mples. yo u have seen howe code can be convened to a custom dig ital circuit using methods that are full y automatab le. General e code can conta in additional types of statements. some of which can be eas il y translated to states. For examp le. afar loop can be tra nslated to states by first trans· fonning the for loop into a IIhile loop. A 51vitch statement can be tra nslated by tirst translating the 511·itch statement to if·the,,·eI5e state ments. Some e constructs pose problems for converting to a circu it. though. For example, pointers and recurs ion are not easy to translate. Thus. too l that automate behavioral design from e code typica ll y impose re tric tions on the a ll owable e code that can be handled by the tool. Such res tric ti ons are know n as suhsellillg the lang uage. While we have emphas ized e code in thi s sec tion . obviously a ny simi lar language, such as e++. Java. VHDL. Veri log. etc .. can be converted to c u tom d igital c ircu its-with appropriate language subsetting.
5.6 MEMORY COMPONENTS Register·transfer level design involves instanti ating and con· necting datapath components to fonn data paths, controlled by controllers. RTL design often uti lizes some additi ona l compo· nenh Outside the data path and controller. One such component is a memory. A n MxN mem ory is a memory com ponent ab le to . to re M data items of N bit; each . Each data item in a memory i. known as a word. Figure 5.5 1 depicts the storage avai lab le in an MxN memory. We can genera ll y categorize memoric, into two gro up' : RAM memory. which can be written to and read from, and ROM memory, which can on ly be read from. Howcver, a' wc ,ha ll sec. the distinction between the two categoric, is billrnng due to new technologic,.
-- - - - - .
~ ~
::;
§... B
N·b/IS
wide each MxNmemory
Figuro 551 Logical \ lew or a memQry.
~
WHY IS IT CALLED "RANDOM ACCESS" MEMORY?
In the early days of digital de, ign. RA i s did not exist. If you had infomlntio n you wanted your digi tal ircuit to store. you stored it on a magnetic drum. or :l magnetic tape. Tape drives (and drum drives too) had to spin the 13pe to get the head. whi h ould read or write on to the (ope. alx)\'c the de ired melllo!,) location. If the hend wa~ urTCI111y ubo\'c locution 900. and you wanted to wri le t loclllion 999. the tape would hnve to pi n P"'t 901. 902, ... 99 . until location
999 was acce sed its Illost address
under the head. In Nher \\ ords. the tape \\ as requtlJ{ial/y. \\'ben R."'-M \\ ~ firq rei a.cl appealing feature \\J.!. that 3.n~ ''r.lndQ(1)'· auld he a 't'sSt.'iI in the S!lJ11C lJ1l()unt of rune as any other ad~-.s-re-gardles of the- pre'ioo'l~ read addre_· . That" · be<-au: then' '" no ··o.ad-- '" tt' acres. n R. ~ t. and no pinnlll£, of t3~" or drum,
Thus. the Icnn ''rJndoOl JI.: .tnd ha... :-tlll'k to thi:- da~ .
~ •• Illem~ \\3..'
u..ed..
260
Register-Transfer LevellRTLI Design
5.6 Memory Components
Figure 5.53 shows the logical internal structure of an MxN RAM. By " Iogical" structure. we mean that we can think of the structure bei ng implemented in that way, although a real physical implementation may possess a different actual structure. (As an analogy, a logical structure of a telephone incl udes a microphone and a speaker connected to a phone line. al though real phys ical telephones vary tremendously in their implementations. includ ing handheld devices. headsets, wireless connections. built-in answeri ng machines, etc.) The main pan of the RAM structure is the grid of bit storage blocks, also known as cells. A collection of N cells fo rms a word , and there are M words. The address inputs feed into a decoder. each output of which enables all the cells in one word corresponding to the present address values. The enable input en can disable the decoder and prevent any word fro m being enabled . The read/write control input rw also connects to every cell to control whether the cell wi ll be wrillen wi th wdata. or read out to rdata. The data lines are connected through one word 's cell to the next word 's cell , so each cell must be designed to only output its contents when enabled and thu s output nothing when disabled, to avoid interfering with another cell 's output. LetA = 1092 M
i5
"C
'addrIA-l) " clk
rdata(N-l)
rdatalN-21 rdataO
Figure 5.53 Logical internal structure of a RAM . Notice that the RAM in Figure 5.53 has the same inputs and outputS as the RAM block diagram in Figure 5.52, except that the RAM in Figure 5.53 has separate write and read data lines whereas Figure 5.52 has a single set of data lines (a single port). Figure 5.54 shows how the separate lines might be combined inside a RAM having just a single set of data lines.
~~r~:.i'
data(N-l ) dataO Figure 5.54 RAM data inpui/ output for a single port .
Bit Storage in a RAM Compared to a register file, the key feature of RAM tS ItS compactness. Recall from Chapter 3 that we implemented a bit storage block using a D nip-Oop. Because RAMs store large numbers of bits, RAMs utilize a bit torage block that is more compact than a flip-flop. We thus discuss briefly the internal design of the bi t storage blocks inside tWO
------------------
261
popul ar types of RAM-stat ic RAM and dynamic RAM . However. be forewarned that the Internal' deSIgn of those block S 'InVO Ives electrontcs . .Issues beyond the scope of this . book, and Instead IS wi thin the scope of textbooks on VLSI or advanced digital design. Fortunately. a RAM component hides the complexi ty of its internal elecrronics by using a memo~ controlle:, and thus a digital designer's interaction with a RAM remains as discussed In the prevIOus ection . Static RAM Stati~ RAM uses a bit storage block involving two Inverters connected in a loop. as shown in Figure 5.55. A bit d will go through the bOllom inverter to become d', then back through the top inverter to become d againthus, the bit is stored in the inverter loop. NOlice that this bit storage block has an extra line, da ta '. passing through it, compared with the "logical" RAM structure in Figure Figure 5.55 SRAM cell. 5.53. To write a bit into thi s inverter loop, we set the data line to the value of the desired bit , and d a t a' to the complement. So to store a I, the memory controller sets d a t a =1 and data ' =0, as shown in Figure 5.56. (To store a O. the controller would have set data=O and data ' =l.) The controller then sets enabl e=l, which turns on both shown tran- e~~~~e sistors. The data and data ' values thus '---------------------------' appear in the inverter loop as shown (over- Figure 5.56 Writing a I to an writing whatever value was there before). SRAM cell. Fully understanding why thi circu it works involves electrical details beyond the scope of this discussion. Reading the stored bit can be done by first elling the da ta and da ta' line bolh 10 1 (an act known as prechargillg). and then by serting enable 10 1. One of the enabled transistors will have a 0 at one end. causing the precharged 1 on the da ta or da ta' 10 drop to a vol tage slightly less than a regular logic 1. Both the data and data' lines connect to a special circuit called a sellse amplifier that detects wheth~r the \'oltage On d a t a is slightly higher than data' . meaning IOf!ic 1 is stored. or whether the \' Ita!!.~ n data ' is slight ly higher than on data . me~in~ logic 0 is slOred. Again. detail -fthe electronics are beyond the scope of this discussion. Notice that the bit storage block of Figure 5.-7 utili zes ix transistors-{\\O in 'ide each of the two inverters_ and two transistors outside the in\'erters. ix transi_ t rs are fewer than needed inside a D flip-flop. A tradeoff is that special circui~ must be used t read a bit stored in thi s bit storage block. where:!., a D Hip-flop ourput ' regular logic values directly. uch special circuitry slows the access time f the SIOI\.-d bit.
262
Register-Transfer LevellRTLI Design RAM based on a six-transistor bi t storage block. or similar such block, is known as a sIalic RAM. or S RAM. A static RAM mai ntains the stored bit as long as power is supplied to the transistors. Except. of course. when the block is being written. the stored bit does /lot change- it is ~latic (noL changing), Dynamic RAM An alternati ve popu lar bit storage block used in RAM has only a single transi stor per block. Such a block utili zes a (re lati vely large) capacitor at the ou tput of the transistor. as shown in Figure 5.58(a). Writi ng can occur when enable is 1: d a t a ~ 1 will charge the top plate of the capacitortoa L w h ile d a ta~O will make it O. When enable is returned to O. a 1 on the top plate will beg in to discharge across to the bottom plate of the capacitor on to ground (Why? Because that 's what a capacitor does.) However. the capacitor is intentionally designed to be relatively large, so that the disch arge takes a long time, during wh ich tim e
the bi t d is effecti vely stored in the capacitor. Fi gure 5.58(b) provides a tim ing diagram illustrating the charge and discharge of the capacitor.
DRA'v1 ch/fJ'ifirrt appeared Ifl the early 197(}(, ufld
((Ju/d hold only a f~ tlwu wnd bm W{)t!unDRA \tfs ('(In hold tnt",)' hllllon\ of bill
263
5.6 Memory Components
Because the stored bit challges (discharges) even when power is upplied and we are not writing the bit storage block, RAM based on the one transistor plus capacitor bit storage block is known as dynamic RAM, or DRAM. Compared to SRAM , DRA M is even more compact, requiring only one transistor per bi t storage block rather than six transistors. The tradeoff is that DRAM requires refreshing, which ultimately slows the access ti me. Another tradeoff. not alluded to above, is that creating the relati vely large capaci tor in a DRAM requires a special chip fabricati on process. and thus incorporating DRAM with regular logic can be costly. In the I 990s, incorporating DRAM with regu lar logic on the same chip was nearly unheard of. Technology advancements, however, have led to DRAM and logic appeari ng on the same chip in more and more cases. Figure 5.59 graphically depicts the compactMxN memory implemented as a: ness advantages of SRAM over register fi les, and DRAM over SRAM , for storing the sallie number register of biLs. file
word
enabte To sense amplifiers
Figure 5.57 Reading an SRAM. d~ta
word
enable
pi:I
cell
d
Tttapacltor ,/ slowly • discharging ~
(al
data~ enable~
d~ Ibl
Figure 5.58 DRAM bit storage (a) bit storage block. (b) discharge.
SRAM
Using a RAM
DRAM Figure 5.60 shows timing diagrams de cribing how to write and read the RAM of Figure 5.52. The timing diagram in Figure 5.60 shows how to write a 9 and a 13 into locations 500 and 999 Figure 5.59 Depiction of compacrnes during clock edges I and 2, respectively. The next benefits of SRAM and DRAM (not to cycle shows how to read location 9 of the RAM , by setting a ddr~9 . data ~Z , and rw~ O scale). (meaning read). Shonly after r w become 0, data becomes 500 (the value we had previously stored in location 9). Notice that we had to disable our writing of data first (by setting it to Z). so a not to interfere with the data being read from the RAM . AI 0 notice that Lhis RAM's read functiona lity is asynchronous.
Reading can be done by first setting da ta to a voltage midway between 0 and L and then setti ng enable to 1. The val ue stored in the capaci tor will alter the voltage on the data line. and that altered voltage can be sensed by special circuits connected to the data line that amplify the ensed value to either a log ic I or a log ic O. lt turns out that readi ng the charge stored in the capacitor di scharges the capacitor. Thus. the RAM must immediate ly write the read bi t back to the bit storage block after reading the block. The RAM mu t contain a memory controller th at automatically performs such a write back . Because a bit tored in the capacitor graduall y discharges to ground, the RAM must refresh every bit storage block before the bi ts completely discharge and hence the stored bit is lost. To refresh a bit storage block, the RAM must read the block and then write the read bit back to the block. Such refreshing may be done every few microseconds. The RA M must include a built-in memory controller that au tomati ca ll y perform these refreshes.
Figure 5.60 Rending and writi ng a RAM : (a) timing diagroms. (b) setup. hold. and
Note that the RAM may be bUl>Y refreshing itself at a time that we wish to read the RAM . Funhermore. every read must be followed by an au tomatic write. Thu . RAM based on one- Lra nl istor plus capacitor technology may be slower to "ecess.
The delay between our setting the rw line to read and the rend datu stabilizing ut the da ta output is known as the RAM's access time or read tillle _ We now provide ,m example of using a RA t in an RTL design.
,
,
,
1
~
l
,
,
,
ctk~ addr
data ~ 1
rw
1 means " ~ , ,, write ,,:
en~
1/:
h
h
l RA M{9]
:
i RAM{13] i
now equals 500 now equals 999 (a)
ctk~ addr
R
i
~;~~m;>
data rw
setup
500
I
~etup 1
I
time
I
:
aa:ess
I
!
!
1
bine
'
(b ) J<
ss time -
26~
5 Register-Transfer level (RTl) Design
5.6 Memory Components
EXAMPLE 5.12 Digital sound recorder using a RAM Let's design a system that CJ Il record sound. and can pl ay ba~k thai reco rded so~ n d . Such a recorder i!'> found in various toys. in telephone an swering machines. In cell phone ~u~~Otn g announcements, and numerous Dlher devices. \Vc'lInccd an analog-to·digital convener (0 d Ig iti ze the sound, a RAM (0 store the digitized sound. a digital .lo-analog convener to output the digitized sound, and a processor 10 cont~1 both convert ers ~nd the RAM . Figure 5.61 shows a block diagram of the system.
~
4096x16 RAM
A Read-Only Memory (ROM) is a memory that can be read from. but not written to. Because of being read only, the bit-storage mechanism in a ROM can be made to have several advantages over a RAM, including:
If
Compoct/less-a ROM's bit slorage may be even smaller Ihan a RAM's_
speaker Figure 5.61 Utilizing a RAM in a digital sound recorder system.
Speed-A ROM may be faster to read than a RAM. e pecially Ihan a DRAM.
RAM's da ta lines. That state also sets the RAM address
Figure 5.62 State machine for stori ng digitized sound in RAM.
of a. Thus. the transitions compare with 4095. not 4096.) The machi ne returns to Slate T and hence cOnli nues writing samples in ~eq uential memory addresses as long
a=O
, tate K s ou tgoing tran ~ ilion uses the old value of a, not
the incremented value (See Section 5.3 discussion of common pitfallq To playback the stored digititcd .ound. the processor block can implement the high-level Mate machine segment hown in Figure 5.63. After initializing the counler a in stale V. the machine eJ1le r~ Male W St:Jle tV
NO/l voIOlility--A ROM 's bi t storage mai ntains its contents even after the power supply to the ROM i shut off-when turned back on. the ROM's contents can be read agai n. In Contrast. a RAM loses its contents when power is shut off. A memory Ihat loses its contents when power i shut off is known as volatile. while a memory Ihal maintains its contents wi thout power is known as nonvolatile. wIV-polVer- A ROM does not consume power to maintain its contents. in contrast to a RAM. Thus, a ROM consumes less power than a RAM .
To slOrc digitized sound. the processor block can implement the high-level stale machine segment shown in Figure 5.62 . The mach ine fi rst intializes its intern al address counler a to 0 in state S. Next. in sta te T. the machine loads 11 value inlo the analog-Io-digital convener to cause a new analog sample to be digitized. and sets lhe three-state buffer to pass that digitized value to the
as the memory is nOt yet filled (a < 4095). Notice that the comparison is with 4095. not 4096. This is because the action in Slale X of a - a + 1 does nOI occur until the next clock edge. so the comparison of a < 4095 on
dlgJt~I-lo-analog conve rt er, 10 convert lhe data jusl read from RAM to the analog signal. That stale also IOcrements the counter a. The machine return s to state W to continue reading. until the entire memory has been rcad.
Read-Onlv Memory (ROM)
microphone
to the counler a's value. and sets the control li nes (0 enable writing. Th e machine lhen transitions to slate U. whose transitions check the value of a against 4095. That Slate also increments a. (Remember th at the transi tions from U will use the old va lue. not the incremenlcd value,
265
disables the three-state buffer. to avoid interfering with the RAM 's output data that will appear dUflng RAM reads. That state also sets the RAM address lines. and sets the RAM control lines to enable reading. Read data will thus appear on da ta lines. The next state X loads a value into the
Figure 5.63 State machine for playing ,ound from the RAM.
Therefore. when the data stored in a memory will not change. we might choose to store that data in a ROM to gain the above advantages . Figure 5.64 shows a block symbol of a I024x32 ROM . The logical internal structure of an MxN ROM data is shown in Figure 5.65. Notice that Ihe internal structure is very imi lar to the internal structure of a RAM shown in Figure 5.53. Bit storage blocks en form ing a word are enabled by a decoder output. with the decoder input being the addres . However. because a ROM can only be read and cannO! be Figure 5.64 10.4x3. ROM written, there is no need for a rw input comrol to block symbol. specify read versus write. nor for wdata inputs to provide data being written. Also. because no synchronous writes Occur in a ROM . the ROM does not have a clock input. In fact. not only is a ROM an asynchronous component. but in fac t a ROM can be thought of as 3 combinatio/lol component (when we only read from the ROM: we'lI see variation later). Some readers mighl at th is point be wondering how we write the initial ntents of a ROM lhal we then can only read. After all. if we can't write the content of a RO~1 at all. then the ROM is really of no u e to us. Obviously. there must be a \\ 3) 10 write the conlents of a ROM . bUI in ROM terminology. the writing of the initial contents of 3 RO~1 i known a ROM programmillg . ROM types differ in their bit storage bl k implemenmtions. which in lurn causcs differen es in the methods used ~ r RO;\1 programming. We now describe several popular bil slomge block implementations for R ~t.
266
Register· Transfe r Leve l (RTL) Desi gn
i5
LetA = log2 M dO
word l e a i enab ••• ----- - ---
addrO
-0
addrl
u
--- ------
L_
(t__ I
-
,
~~ ---
J
bit storage block (a"ceW' )
word
I
'"addr(A· ' ) ~
word
word
enable-enabi8 data
en
data(N·' )
dala(N·2)
dataO
Figure 5,65 Logical intern al structure of a ROM .
ROM Types Mask-programmed ROM Figure 5.66 illustrates the bi t storage ce ll for a mask- prog rammed ROM . A maskprogrammed ROM has its contents programmed when the ch ip is manufactured . by directly lIIirillg Is to cells that should store a I , and Os to cell s that should store a O. Recall that a "I" is ac tuall y higher-than-zero voltage coming from one of
everal
data line
o
data line
olle-lime programmable (OTP) ROM.
Figure 5.66 Mask· program med ROM ce lls: teft cell prog rammed with 1. right ce tl w ith O.
power input pins to a chi p-thus. wiring a I means wi ring the power inpu t pin directly to the ce ll. Likewise. wiring a 0 to a cell means wiring the ground pin directly to the cell . Be aware that Figure 5.66 presents a logical view of a mask.programmed ROM ce ll- the actual phys ical design of such cells may be somewhat diffe rent-for example. a common design strings several vert ical cells together to form a large NOR-like logic gate. We leave details for more ad vanced textbooks on CMOS circuil des ign. Wires are pl aced onto chips during manufacturi ng by using a combination of light. sensiti ve chemica ls and light passed through len es and "masks" that block the light from reaching regions of Ihe chemicals. (See Chapter 7 for fun her details.) Hence the term "mask" in mask-programmed ROM . Mask-progra mmed ROM has Ihe best compactness of any ROM type. but the con· ten l.~ of the ROM must be known during chip manufacturing. This ROM type is best suited for high-volume well-established products in which compactness or very low cost is critical, and in which program ming of Ihe ROM will never be done after the ROM's chip i, manufactured .
-
267
5.6 Memory Components
Fuse-Based Programmable ROM-One.Time Programmable (OTP) ROM Fi gure 5.67 illustrates Ihe bit storage cell for a fu se-based ROM . A /use-based ROM data line data line uses a fu se in each ce ll. A fuse is an electrica l component that initially conducts from one end to the other just like a wi re, word but whose connection from one end to the enab~le~__-'~__it-t__~~__-tr other can be destroyed ("blown") by pass ing a higher-than-norma l current fuse blown luse th rough the fu se. A bl own fu se does not conduct and is instead an open circuit (no Figure 5.61 Fu se-based ROM ce lts: left ce ll connection). In the figure, the cell on the programmed with t . ri ght ce lt with O. left has its fu se intact, so when the cell is enabled. a 1 appears on the data line. The cell on the right has its fu se blown. so when the cell is enabled. nothing appears on the data line (special electron ics wi ll be necessary to conven that nothing 10 a logic 0). A fu se-based ROM is manufactured with all fuses intact, so the initiall y stored contents are all Is. A user of this ROM can program the contents by connecting the ROM to a special device, known as a programmer. that provides higher than normal currents 10 only those fuses in cells that should store Os. Because a user can program the contents of this ROM. the ROM is known as a program mable ROM , or PROM. A blown fuse cannot be changed back to its initi al conducting form . Thus. a fusebased ROM can onl y be programmed once. Fuse-based ROM are therefore also known as Erasable PROM-EPROM Figure 5.68 depicts a logical view of an erasable PROM cell. An erasable PROM. or EPROM. cell uses a special type of transistor, having what is known a.s a floatin g gate, in each cell . The details of a floating gate transistor are beyond the
~-~
-§~ :g~
data line
data line celt
"''''
~
word enable
scope of thi s section. but briefly-a fl oat ing gate transistor has a special gate in trapped electrons whi ch electrons can be "trapped:' A Lransistor with electrons trapped in its gate Figure 5.68 EPROM celts: left celt stays in the nonconducting siruation. and programmed with L right celt \\ ith O. thus is programmed to store a O. Otherwise, the cell is considered to store a 1. pecial electron ic circuitry convens sensed current · on the data line' a; logic I or O. An EPROM cell initially has no electrons trapped in any fl oating gate transistors. the initially stored contents are all I s. A programmer d \ ice applies higher-than-nonnal voltage to those transistors in cells that should store Os. That high \'olt:\g" 'ause, d trons to IlI/l1le/ th rou gh a slllall insulator into the fl oating gate region. When th' \ Itnge is removed. the electrons do not have enough energy to tunnel ba k. and thus are trapped as shown in the right ce ll of Figure 5.6 .
268
Register·Transfer LevellRTLI Design The electrons can be freed by exposing the electrons to ultrav iolet (U V) light of a part icul ar wavelength . The UV light energizes the electrons suc h that they tunnel back through the small insulator, thus escaping the floating gale region. Exposing an EPROM chip lo UV light therefore "erases" all the stored Os. reslOring the chip lo having all 1s as contelllS. aftcr which the EPRO M can be programmed agai n. Hence the term "erasable" PROM . Such a chip can typica lly be erased and reprogrammed about ten thousand times or more, and can retain its contents without
power for ten years or more. Because a chip usually appears inside a bl ack package thm doesn't pass light. a chip with an EPROM requires a wi ndow in that package through wh ich UV light can pass. as shown in Figure 5.69.
5.6 Memory Components
269
the data to be programmed and the add '. . . wnlmg the EEPROM f h' ress mto mternal regIsters, freemg the circuit that is . programming Modem EEPROMrom avmg to hold th ese va1 ues constant dunng s can be prog d . more, and can retain thel' ramme tens of thousands to millions of time or r Contents While erasing one word t . for .tens t0 one hun d red years or more without power. other applications need to a a tIme IS fine for some applications that utilize EEPROM erase large block f ' . d s 0 memory qUIckly-for example. a digital camera application would . nee to era e a blo k f . pIcture. Flash memory is a Iype of EEP . c a. memory correspondmg to an entire memory can be erased ve ui ROM In whIch all the words with a large block of time. A flash memory ~ q ckly, perhaps sImultaneously, rather than one word at a Many fl ash memories:a: al~o~:~~letely erased by setting an erase control input to 1. erased while other ' y a specific regIon , known as a block or sector. lo be regIons are left untouched.
Figure 5.69 The "window" in (he package of a microprocessor that uses an
EPROM
10
Slore programs.
EEPROM and Flash Memory An electrically erasable PROM , or EEPROM, utili zes the EPROM programming method of using high voltage lO trap electrons in a fl oating gate tranSislOr. However, unlike an EPROM that requires UV light to free the electrons and hence erase the PROM , an EEPROM uses anot her high voltage to free the electrons. EEPROMs thus avoid the need for placing the ch ip under UV li ght. Because EEPROMs use voltages for erasing, those voltages can be applied to specific ce lls on ly. Thus, whi le EPROMs must be erased in their entirely, EEPROMs can be erased one word al a lime. Thus, we can erase and reprogram certain words in an EEPROM wit houl changing the conlenlS of olher words. Some EEPROMs require a special programmer device for programming. However, most modem EEPROMs do not require special voltages to be applied to the pins, and also include internal memory controllers that manage the programming process. Thus, we can reprogram an EEPROM 's contents (or part of its contents) wi thout ever removing the chip from the system that the EEPROM serves-such an EEPROM is known as being in-system programmable. Most such devices can therefore be read and wrillen in a manner very similar to a RAM. Figu re 5.70 shows a block diagram of an EEPROM. Notice that the data lines are bidirectional. 32 just as was the case for RAM . The EEPROM has a --+- data 10 control inpul wri te-vlri te=O ind icates a read ~ ad dr operat ion (when en=1), whi le write=1 indicates _ en 1024 x 32 thai the data on the data lines shou ld be programmed EEPROM into the word at Ihe add ress specified by the address ----.. write linc . Programming a word in to an EEPROM takes _ busy time, though, perhaps several. dozens, hundreds, or I> even thousands of clock cycles. Therefore. EEPROM may have a control OUlput busy to indicate that proFigure 5.10 1024x32 EEPROM gramming is nOI yet complete. While the device is block symbol. bu~y, the EEPROM user should not try writing to a different word. Fortunalely, mOM EEPROMs will load
Using a ROM We now provide examples of using a ROM in RTL designs.
EXAMPLE 5.13 Talking doll using a ROM We wish to design a doll thai s aks lh " . moved. A block diagram of th pc e. message NIce 10 meel you" whenever the doll's righl arm is
e syslcm ISshown in Fioure 5 71 A 'b . . ann has an output V that is 1 when vibr.ltion '. 0 " VI ration sensor In the dolr right then output a digitized version of the "Nice IS sensed. A .~rocessor detects, ~e vibration and houJd attached to a speaker. The "Nice 10 mec " [0 meet yo~ message to a dlguaJ-to-analog converter actress. Because that message 'II t you message wil l be the prerecorded voice of a professional
message in a ROM.
•
WI nOI change for the li fetime of the doll producl, we can store thai
4096 x 16 ROM
speaker
vibration sensor
Figure 5.11 Utili zing a ROM in a lalking doll system.
Figure 5.72 shows a high-level stale machine s.egmen t that plays the message after detecting vibralI on. The machine starts in stale S. inil'i:liizing the ~OM address coun ter a to O. and waiting for vibratIOn ~o be sensed. When vibration is sensed. the machine pr~eeds to Slate T. which reads the current R~M locatIon. The I11Hchine moves on to state U. whIch loads the digital-la-analog converter with the
read value fmm ROM. incremems a. and proceeds back 10 Tas long as a hasn' l reach d -1095 (remember thm the transilion fmm U uscs the value of a before Ihe II1cremenl. so compares 104095. not to -1096).
270
Register-Transfer LevelI RTL) Design
5.7 Qu eues IFIFOs)
Because thi:-. do ll's message wi ll neve r change. we l~l i g hl choose, to usc a l~las~- ~~ogrammed ROM or an OTP ROM . We migiu uti lize OTP ROM dUri ng prototyplllg or dUri ng IIlll1al sales of the doll. :lIld th en produce m3;k-prograllll11cd RO M versio ns during hig h-volume prod ucli on of
the doll. Dtgtta l telephone answe rtng machine using a flash memory
EXAMPLE 5.14
\Ve are to desig n the olltgoing announcement part of a te lep ho ne answerin g mac.hi.ne (e.g .. "We 're Ilot home ri!:!llI now, leave a messnge."). That an nounccmcm shou ld be stored d igit all y. should be
by
recordable the machi ne owner any nu mber of ti mes. and should be saved even if power is removed fro m the illlswering machine. Recording begins immediately after th e owner presses a record buncn, which se lS a signa l rec 10 1. Because we must be able I ~ reco rd the anno un cement. we cannot use a mask·progrnlllllled ROM or OTP ROM. Because removll1g power shoul d not cause the announcement to be lost. we cannot use a RAM. Th us. we might choose 3n EEPROM or a Aash memory. We' lI u5e a nash memory. a ~ show n in Figure 5.73. Noti ce th a~ the fl ash memory has the same inte.rface as a RA1\ll. except tha t th e nash memory has an ex tra Inpu t l~aJl1cd erase. eras~ on t~IS panicular nash memory clears the contents of the ent ire flash. \Vhlle the .nash me mory IS erasmg itself. the fla sh sets an output busy to 1. duri ng whi ch ti me we cann Ol wnte to the fl ash memory.
4096 x 16 Flash
Figure 5.73 Utilizing a fl as h memory in a di gita l answeri ng machine. Figure 5.74 shows a hi gh·level stale machine segment for recordin g the nnnounceme ni. The Mate machine segment begins whe n the record bUlton i pressed. Slate S activates the erase of the nash memory (e r =l ), and then state T waits for the era, ing to complete (bu'). Such erasing should occur in jusl n few mi ll iseconds. so we shouldn' t mi ss any of the spoken an nouncement. The state mnchine then transitions 10 Slale U.
which copies a digitized sample from the analog-
.
_------------------
Notice that. unli ke Examples 5.12 and 5.13. this tate machi ne increments d before the state that checks for the last address (state V) , so V"s Lransilions use 4096. not 4095. We how this version JUSI for varlely. The version in Example 5.12 may be Slightly bener because that version requires that d_ and the comparator, only be 12 bits wide (to represent 0 to 4095) rather than 13 bits wide (to represent 0 to 4096). . Thi~ state machine assumes thal writes to the fl ash occu r in one clock cycle. Some flash memones requi re more ti me for writes, assert ing their busy out put un ti l the write has complered. For such a flash. we would need to add a slate betwee n stat.es U and V. similar to the state T between Sand U. To prevent missing sound samples while wa iling, we mi ght want to first save the entire sound
sample in a 4096x 16 RAM, and then copy the entire RAM contents to the flash.
The Blurring of the Distinction between RAM and RO M Notice that EEPROM and Hash ROM blur the distincti on between RAM and ROM. Many modem EEPROM devices are writable just like a RAM . havi ng nearly the arne interface. with the onl y difference being longer write times to an EEPROM than to a RAM. However. the difference between those time is shrinking each year. Funher blurring the distinction are nonvolatile RAM (NVRAM) device, which are RAM devices that retain their contents even without power. Unl ike ROM. NVRAM write times are just as fast as regular RAM- ty picall y one clock cycle. One type of NVRAM simply includes an SRAM with a bu ilt-in battery. with the battery able to supply power to the SRAM for perhap ten years or more. Another type of VRAM includes both an SRAM and an EEPROM- the NVRAM controller automaticall y backs up the SRAM's contents into the EEPROM . typically just at the time when power is bei ng removed. Furthermore, extensive research and deve lopment into new bit storage technologies are leading to NVRAM s that are even closer to RAM in terms of performance and density while being nonvolatile. One such technology is known as MAGRAM. shon for magnetic RAM, which uses magnetism to store charge. having access ti mes similar to DRMt. but withoUlthe need for refreshing. and with nonvolatil ity. Thus, digital de igners have a tre mendous variety of memory types available to them_ with those types di ffering in their cost. performance_size. nonvolatility_ ease-of-use. write time_ du ra tion of data retention_ and other factors.
5.7 QUEUES (FIFOs)
di gital converter to the fl a'> h memory. writing to the current address a. State U also increments a .
The next 'tate f II) checks to 'ee if the memory i, filled with ,ample, by checking if d( 409 6. returning to ,tate U until the memory is fi lled.
271
Figure 574 State machine for storing di gi ti zed .;;ound in a
fla ~h
memory.
Somerimes our data storage needs specifically require that we read items in the same order that we wrote them, and that reading removes the item from the list. For example, a busy restauranl may mai nlai n a wail ing lisl of customers-the host writes customer names to the rea r of the list. but when a tabk becomes available. the host reads the next customer's name from the fivlII of the list and removes that name from the list. Thus. the fi rst customer wri tten to the list is the first cu -tomer read from the list. A qlleue is
back
write items to back
ofthe queue
from
read (and nemove) Items from front of
the queue
Figure 5.75 C'onc'Cp1ual \ ie" of 3 queue.
272
PLEASE QUEUE FROM THIS
END
Register-Transfe r Leve l lRTLJ Desig n
5.7 Queues {FIFOsJ
a list that i written at the rear o f the list but read from the beginning of the list, with a read also removi ng the read item fro m the list, as illustrated in Figure 5 .75 . The common tenn for a queue in American English is a " Iine"-for exa mple, you stand in a line at the grocery store. with people entering the rear of the line. and being se rved fro m the fro nt of the li ne. In Bri tish English. Ihe word queue is used directly in everyday language (w hich somelimes confuses Americans who visit other English-speaki ng coun tries). Because the firs t item wri tten into the list wi ll be the first ite m read out of the list, a que ue is known as beingfirstill first-out (FIFO). As such, sometimes queues are called FIFO queu es , although that tenn is redu nda nl because a queue is by defin ilion fi rst-in fi rst-out. The term FIFO itself is often used to refer to a queue. The term buffer is also so me limes used. A wri te to a queue is someti mes called a push or ellqueu e, and a read i sometimes ca lled pop or dequeue. We can implement a queue using a 7 6 5 4 3 2 1 0 memory-either a reg ister fi le or a RA M . depending on the queue size needed. Wh en using a memory. the from and rear
:--1: -1 :--1 :--1 :--1 :--1r--1 :--1
::::!:! ,__
l! !1 ii Ii 1
J , __ J , __ oJ ' __ J
I __ J
' __ J ' __ J ' __ J
wi ll move to diffe ren t me mory locations rI 7 6 4 3 0 as the queue is wrinen a nd read, as ill ustrated in Figure 5.76. The fi gure shows an initiall y empty eight-word queue with A--fronl and rear bOlh set to me mory address I O. The fi rst ac ti on on the queue i a write 6 2 o of item A. whi ch goes to the rear (add ress ' II II II '1 II , 0). and the rear increments to address I. I II It II II II I :: :: :: :: :I B A The neX I aClion is a write of item B, B--- :I :: II II II II II 1__ .1 1__ .1 I __ J t__ J 1__ .1 ' __ J whic h goes to the rear (add ress I). and Ihe r I rear increme nts to 2. The next acti on is a 7 6 3 2 o read. which comes fro m the front (add ress 0) and th us reads out item A. and the front A increments to I. Subsequent reads and wri tes contin ue r likewise, except that when the rear or front Figure 5.76 Writing and read ing a queue reac hes 7, its nex t value should be O. not 8. implemented in a memory causes lhe front [n other words. the memory can be thought (I) and rear (r) 10 move. of as a circle. as shown in Figure 5.77 . o Two cond iti ons of a que ue are of interest:
,---,--' ,---,--, ,---,---GG
Unfortunately, notice that the conditions detecting the queue be ing empty a nd the queue beJllg full are the same- the fro nt address equals the rear address. One way to tell the two conditions apart is to keep track o f whe ther a write or a read preceded the fro nt and rear addresses becoming equal. In many uses of a queue, the circuit writing the queue operates independentl y from the CirCUli readin g the queue. Thus, a queue implememed wi th a memory may use a twoport memory havmg separate read and write ports. We can implement an 8-word queue using an 8-word two-port 8x16 register file 16 16 rdat a registe r fi le and additional compo- W data wdata rdata nents, as depicted in Figure 5.78. A 3-bi t up-counter maintains the waddr raddr front address, while another 3-bit I--- ).r rd h up-coun ter mai ntains the rear address. Notice that these counters elr elr fwill naturall y wrap around from 7 ~ I- inc inc to 0, or fro m 0 to 7, as desired 3-bil 3·bil when treating the memory as a ~f+ up counter up counter .2 c ircle. An equality comparator rear Ironl c:0 detects whether the fron t counter 0 ~ ~ equals the rear counter. A coneq troller writes the write data to the I lull register fi le and increments the rear counter durin g a write, reads em PlY the read data from the register fil e L....-
r e
.. -
- --
._-- - - --
~
>
.+ I
>
+I
S-wo rd 16·bit queue
and increments the fro nt counter du ri ng a read, and determines
Figure 5.78 Arehileclure of an S-word l6-bil queue.
whether the queue i full or empty based on the equality comparison a we ll as whethe r the previous operation was a write or a read. We omi t further de cription of the queue' controller, but it can be built by starting with an FSM . A user of the queue should never read an empty queue or write a full queuedepending on the controlle r design. uch an action might ju t be ignored or might put the queue into a misleading internal state (e.g .. the front and rear addre ses may cross over). Most queues come with one or more additional contro l output that indicate whether the queue is half full . or perhaps 80% fu ll . Queue are commonplace in digital system . Some example include: A computer key board writes the pressed keys into a queue and meanwltile requests that the computer read the queued keys. You might at ome ti me ha\'e typed fas ter than your computer was reading the key. in whic h ase >our additional keystrokes were ignored-and you may have even heard beep, each time yo u pre sed addi tiona l keys. indicating the que ue \ as fu ll .
=
-
~
r-
Empty: there are no items in the q ueue. This condition can be detected as fro lll rear, as seen in the topmost que ue of Figure 5.76.
Full: there is no more room to add items to Ihe queue, meani ng there are N items in a que ue of ize N. This comes lIbout whe n the rear wrap; aro und and catches back up to the front. mean ingfrollt = rear.
273
A di gita l video camera may write recently captured video frames into a qUeue. and concurrentl y may read those fmme.! fro m the queue. compre'. them. 3/ld store the m on tape or anotller medium . Figure 5.77 Implementing a queue in a memory lreats the memory as a circl e.
•
A compu te r printe r may store print job in a queue while th se j bs are waiting \0 be pri nted .
27.t
Reg ister· Transfer LevellRTLI Design
275
5.8 Hierarchy-A Key Design Concept A modem stores incoming data in a queue and requests a computer to read .that data. Likewi se, the modem writes outgoing data rece ived fro m the computer tnto a queue and then send s that data out over the modem's outgoi ng medium.
5.8 HIERARCHY-A KEY DESIGN CONCEPT Managing Complexity
A computer network ro uter receives data packets from an input pon and writes those packets into a que ue. Meanwhile. the rou ter reads the packets from the queue. ana lyzes the address information in the pac kel. and the n sends the packet alo ng o ne of severa l output pons. Using a queue
EXAMPLE 5.15
3
Show the internal stal e or a Sword queue, and popped data val ues. after each of the fol-
Through?ut this book, we have bee n utili zing a powerful design concept known as hierarchy. HIerarchy In general is defined as an organi zation with a few "things" at the top. and each thing poss ibly consisting of several other things. Perhaps the most widely known type hierarchy involves a Country. At the top is a country, which consists of many states or provinces, each of wh ich in turn consists of many cities. A hierarchy involvi ng a country,. provinces, and c ities is shown in Figure 5.80. That figure shows all three levels of the hterarchy-coumry, provinces, and cities. Figure 5.81 shows the same country, but this time showing only the top two levels of hierarchy-cou ntries and provinces. Indeed, most maps of a country only show these top two levels (possibly CityF showi ng key cities in each province/state, but cenainly not all the cities}-showing n a ll the cities also makes the map far too CD detailed and cluttered. A map of a province/ CityG state, however, might then show all the ountry ci ties within that state. Thus, we see that hierarc hy plays an imponant role in understanding countries (or at least their maps). Figure 5.80 Three-level hier.rrch y example: a
o
2
Initiallyemply
queue
low ing sequences of pushes and pops. assuming an in itially empty queue:
2
5
7 1. Alter pushing
I. Push 9. 5. 8. 5. 7. 2. and 3.
9, 5, 8, 5,7, 2, 3
1. Pop 3. Push 6
765432
4. Push 3 6. Pop Figure
'"
data: 9
2. Alter popping
5. Push 4
r
5.79
shows
7
the
o
6
L'
tkewise, hierarchy plays an important role in digital design. In Chapter 2, we introduced the most fundamental component in digital systems-the transistor. In Chapters 2 and 3, we introduced several basic components composed from transistors, like AND gates, OR gates, and NOT gates, and then some sligh tl y more complex components composed from gates: multiplexers, decoders. flip-flops,
queue's internal stales. After the
first sequence of seven pushes
3. After pushing 6
(s tep I ). we see that th e rear
address points to addre s 7. The pop (step 2) reads from the front address of O. returning data of 9. The front address increments to I. Note that although the queue might still contain the va lue of 9 in address O. that 9 is no longer
4. Alter pushing 3
accessible during proper queue
5. After pushing 4
7
6
5
3
2
8800080G
lull
rl ERROR! Pushing
a full queue
operat ion. and thus is essentiall y gone. The push of 6 (step 3)
results in unknown state
increments the rear address. which wraps around from 7 to O.
Figure 5.79 Example pushes and pops of a queue.
The push of 3 (step 4) increments the rear address to I. which now equals the front address, push of 4 OCcurs (ste p 5)-this push should not have been performed. because the queue is Full. Thus, this push puIS the queue into an erroneous state, and we cannot predict the behavior of any subsequent pushes or pops. A que ue could of course come wi th some error- tolerance behavior built in, perhaps ignoring pushes whe n full , or perhaps returning some panicu lar value (li ke 0) if popped when empty.
-.
- .--
-------------
cities.
e tc. In Chapter 4, we composed the basic Figure 5.81 Hierarchy showing just the top components into a higher level of compo- two levels. nents, datapath components, li ke registers. adders, ALUs, multipliers, etc. In Chapter 5, we introduced components composed of datapath components, including controllers. datapaths, proces ors (made up of controllers and datapaths). memories. and queues. Use of hierarchy enab les us to manage complex design . Imagine trying to comprehend the design of Figure 5.30 at the level of logic gates-that de£ign likel\' con i IS of several thousand logic gates. Humans can ' t comprehend everal thousand thing at on . But they can comprehend a few dozen things. A the number of things grow beyond 3 few dozen. we therefore group those things into a new thing. to manage the omplexity. However, hierarchy alone is not sufficient- \ e mu t also associate :lJl underst:lJldable meaning to the higher-leve l things we create, a task known as absrrn ti n.
mean ing the queue is now full. If a pop were to occur now, it would read the value 5. But instead, a
-
country, made up of provinces. each made up of
J
276
5 Register-Transfer LevellRTLI Design
Abstraction Hierarchy may not onl y invo lve grouping thi ngs into a larger thing, but may also involve associat ing a higher-level behavior to that larger thing. So when we grouped transistors to fo rm an AND gate. we didn 't just say that an AN D gate was a group of transistorsrather. we assoc iated a spec ific behavior with the AND gate, with that behavior describing the behavior of the group of transistors in an easily understandable way. Likewise, when we grouped logic gates into a 32-bit adder. we didn ' t just say that an adder was a group of logic gates-rather, we associated a specifi c understandable behav ior with the adder: A 32-bit adder adds two 32-bit number . Associating higher-level behavior with a component to hide the complex inner details of that component is a process known as abstractioll . Abslract ion frees a designer from having to remember, or even understand, the lowlevel detail s of a component. Knowing that an adder adds two numbers, a designer can use an adder in a design. The designer need not worry about whether the adder internally is implemented using a carry-ripple design, or using some complicated design that is perhaps fas ter bu t larger. In stead. the des igner just needs to know the delay of the adder and the size of the adder. which are further abstTactions.
Composing a Larger Component from Smaller Versions of the Same Component A common design task is to create a larger version of a
component from smaller versions of the same component . For example. suppose you have 3- input AND gates available to you, but you need a 9-input AND gate. You cou ld compose several 3-input AND gates to form a 9- input AND gate, as shown in Figure 5.82. You cou ld compose OR gates into a larger OR gate, and XOR gates into larger XOR gates, similarly. Some composi tions might require more than two levelscomposing an 8-bi t AND from 2-input ANDs requires Figure 5.82 Composing a 9-inpul AND gate from fo ur 2-input ANDs in the first level , two 2- input ANDs 3- inpul AN D gales. in the second level, and a 2-input AND in the th ird level. Some compositions might end up wi th extra inputs that must be hardwired to 0 or I-an 8-input AND bui lt from 3-input ANDs would look sim ilar to Figure 5.82. bu t with the bOllom input of the bOllom AND gate hardwired to 1. After trying a few examples of composi ng AND gates into larger ones, you can come up with a general ru le to compose any size AND gates into a larger gate: fill the first level with (the largest avai lable) AND gates until the sum of their inputs equal the desired number of inputs, then fill the second level simil arl y (feeding first level outputs to the second level gates), until a level has just one gate (that's the last level). Connect any unused AND gate inputs to 1. Composing NAND. NOR, or XNOR gates into larger gates of the same kind wou ld require a few more gates to maintain the sa me behavior. Multiplexers ca n also be composed together to form a larger mUltiplexer. For example, suppose you had 4x I and 2x I muxes avai lable, but you needed an 8x I mux . You could compose the small er muxes into an 8x I mux as shown in Figure 5.83. Notice that
-------------
5.8 Hierarchy-A Key Design Concept 52 selects among group i 0- i3 and i 4 - i 7 while 51 and 50 select one input from the group. You 'can check that select line values pass the appropri ate input through, for example, 525 150 = 000 passes i 0, 525150 = 100 passes 14 , and 525150 = 111 passes i 7. . One particularly commonly occurring com posi ti on problem IS that of creating a larger memory from smaller ones. The larger memory may have wider words, may have more words, or both. For example, Suppose you have available a laroe number of 1024x8 ROMs, but you want a 1024x32 ROM . Composing the smaller ROMs into the larger one is straightforward, and shown in Figure 5.S4. We' ll need four 1024xS ROMs to obtain 32 bits per word. We connect the 10 address inputs to all four ROM s. Likew ise, we connect the enable input to all four ROMs. We group the four 8-bit outputs into our desired 32-bit output. Thus, each ROM stores one byte of the 32-bit word . Reading a location, say location 99, results in four simultaneous reads, of the byte at location 99 of each ROM.
iO
x iO
i1
i1
277
i2 i3
i4
i5 i6
i7
i3
S1
sO
s2
Figure 5.83 An 8x I mux composed from 4x t and 2x I muxes.
c:
" 8
1024x32 ROM
Figure 5.84 Composing a 1024x32 ROM from 1024x8 ROMs.
32
As another example using ROM. suppose you again have 1024x ROMs a\'ailable_ but this time you need a 2048x8 ROM . So you have an extra addre s line because y u have twice as many words to address. Figure 5.85 haws ho\ to use two 1024x ROMs to create a 2048x8 ROM . The top ROM represent the top half of the memory (10_4 words). and the bOllom ROM the bOllom half ( 1024 words)_ We u e the 11th addre line (a 1 0) to enable either the top ROM or the bOllom RO 1-the other 10 bilS represent the offset into the ROM . That 11th bit feeds into a Ix2 decoder. whose output reed into the ROM enables. Figure 5.86 lIses a table of addresses to show ho\\ the 11 th bit selects among the two smaller ROMs.
278
5.10 RTl DeSign using Hardware Description languages (See Section 9.51
Register·Transfer level (RTlI Design ACllIally. we could lise any bit
to scicct between the top RO I and bOllom ROM . Designers common l) use the lowest-order bit (aO) to se lecl. The lOp ROM would thus represent all evenly add ressed words. the bOllom ROM all oddl y
,...- -- - - -- -- ---- ----- - -------------------,
11'
-0 .,-'-rl~=::;::;;::;_-T1 add,
-g
ROM
ij -....;... ~-------------------' -- - -
will be active at any time. we can 10
5.11 PRODUCT PROFILE: CELL PHONE
L _________ __ __ __ _
fO fm Ollr 8-bit ou tput. as shown in
Figure 5.85 Composi ng a 2048x8 ROM from
1024x8 ROM s.
situ ation. we need bot h to creatc
more words. and wider words. The approach is straightForward: fi rst. create a -l096x8 ROM by using 4 ROMs one on top of the other and by feed ing the lOp two address lines to a 2x4 decoder 10 select the appropriate ROM. and then second. widen the ROM by adding 3 more ROM s 10 each row. Most of the datapath components we introduced in Chapter 4
al0a9a8
aD 0000 0000000 0 0000000001 000000000 10
add,
o1 o1
en
same
type
of
1024xB
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
0000000000 0000000001 0000000010
data
add, 1024xB
ROM 1
o
en
data
1111
Figure 5.80 When composi ng a 2048x8 ROM from
two 1024x8 ROMs. we can use the highest address bit
(0
choose among the two ROMs: the remaining
add ress bits offset in to the chosen ROM.
5.9 RTL DESIGN OPTIMIZATIONS AND TRADEOFFS (SEE SECTION 6.5) Previous sections in this chapter described how to perform reg ister·transfer level de,ign to crea te processors consisting of a controller and a datapath . This section, whi ch phy,ica ll y appears in the book as Section 6.5. de~cribes how to create proce · so r~ that are beller optimized. or that trade off one feature for another (e.g., size for performance). One u~e of this book covers such RTL optimi zati ons and tradeoffs immediately after introducing RTL design. meaning now. Another use introduces them later.
~ ·_oi
.. .
~ _
. _ _ _ _ __
A cell phone, short for cellular telephone and also known as a mobile phone. is a portable wireless telephone that can be used to make phone calls while moving aboul a city. CeU phones have made it possible to communicate with di stant peop le nearly anytime and anywhere. Before cell phones, most telephones were ti ed 10 physical places like a home or an office. Some cities supported a radio-based mobile telephone ystem usi ng a powerful central antenna somewhere in the city. perhaps atop a tall building. Because radio freq uencies are scarce and thus carefull y doled out by governments, such a radio telephone system cou ld on ly use perhaps tens or a hundred di ffe rent radio freq uencies. and thus could not support large numbers of users. Those few users therefore paid a very high fee for the service, limiting such mobile telephone use to a few wealthy individuals and to key government officials. Those users had to be within a certai n radiu of the main antenna, measured in tens of miles, 10 receive service. and that ervice typically didn·t work in another ci ty.
ROM
can be composed into larger ver-
sions of the component.
This section. which physically appears in the book as Section 9.5, describes use of IfDLs during RTL design. One use of this book describes such HDL use immediately after introducing RTL design (meaning now). Another use describes use of HOLs later.
--·-1
':~. - j
Fina lly. since onl y one ROM
Figure 5.85. As a tinal example using ROM. suppose you needed a -l096x32 ROM. but had only 102-lx8 RO Is available. In thi s
5.10 RTL DESIGN USING HARDWARE DESCRIPTIO N LANGUAGES (SEE SECTION 9.5)
1024x8
addressed words.
tie together the out put data lines
,
279
Cells and Basestations Cell phone popularity exploded in the basestation antenna I990s, growing from a few million users to hundreds of millions of users in that decade (even though the first cell phone ca ll was made way back in 1973. by Martin Cooper of Motorola. the inventor of the cell phone), and today it i hard : ..c:: ..' for many people to remember life before \ -~ --- . " ''- ____ ~---.L.....,.- tollrom cell phones. The basic technical idea regular behind cell phones divides a city into ' - - - - - - - ' phone numerous smaller regions. known as city system cells (hence the term ··cell phone·). Figure 5.87 shows a city divided into three cell s. A typical city might actually Figure 5.87 Ph nc 1 in cell can use th same radio frequency as phone _ in cell C. in reasing be divided into dozens. hundreds. or the number of po sible mobile phone u!!ocrs in 3 even thousands of ce lls. Each cell has its city. own radio antenna and equ ipment in the center. known as a basestatioll . Each basestation can u 'e dozens or hundreds of different mdio frequencies. Each basestation antenna only needs to transmit radio signal> po\\erful enough to reach the ba, estation·s cell area. Thu . nonadjacent cell. can a 'tuall~ ll"lSc' the same frequenci es. so the lil11it~d number of radio frequ'ncies ullo\\ro for mob,l phone -
-
280
Register-Transfer l evel (RTl) Design can bc thus shared by more th an one phone at onc tim e. Hence. far more users can be supported. lead ing to reduced cos ts per user. Figu re 5.87 illustrates th at phone! in cell A can usc th e sa me radio frequency as plwI/e2 in ce ll C. because the radi o signals from cell A don't reach ce ll C. Support ing more users means greatl y redu ced cos t per user, and more basestal ions means serv ice in more areas than just major cities . Figure 5.88(a) shows a typical basestntion antenna. The basestation's equiplllc lll Jllay be in a small building or commonly in a sma ll box near th e base of the antenna . The antenna shown actu all y suppon s antennas from tWO di fferent cellul ar servi ce providers-one set on the top. one set just under. on the same pole. Land for th e poles is expens ive. whi ch is why providers share. or sometimes find existing tall Slnlctures on whi ch to mount the anten nas. like buildi ngs. park light posts. and oLher interestin g places (e.g .. Figure 5.8 (b)). Some prov iders try to disgui se thei r antennas to make Lhem more soot hing to th e eye. as in Figure 5.88(c)-th e entire (a) Lree in th e picture is artifi cial. All the basesLations of a serv ice Figure 5.88 Basestations found in vari ous locations. provi der con neCL to a central switching office of a ci ty. The switching office not only lin ks th e cell ul ar phone system LO the regular "Iandline" phone sysLem , bUL also assign phone calls LO specific radio freq uencies, and handles SwiLching among cell s of a phone moving beLween ce ll s.
5.11 Product Profile: Cell Phone
281
indicates that your phone is in cell A. In one Lype of cell phone Lechnology, the swi Lching office computer assigns a specific radio frequ ency supported by basesLaLion A LO the call. Ac tuall y, the computer assigns two frequencies, one for tal king, one for Ii teni ng_ so that talking and listening can OCCur simulLaneously on a cell phone-Iet's call that frequency pair a channel. The computer then tell s your phone to carry OUL the cal l over the assigned channel, and your phone rin gs. Of course, iL could happen Lhat Lhere are so many phones already involved wiLh calls in cell A Lhat basestaLion A has no available frequencies-in thaL case. the caller may hear a message indicatin g Lhat user is unavailable. Placing a call proceeds similarl y, but your cell phone initiate the call , ulLimately resulting in assigned radio frequencies again (or a "system busy" message if no frequencies are presently avai lable). Suppose that your phone is presently carrying OUI a call with base LaLion A, and thai you are moving through cell A toward cell B in Fi gure 5.87. BasesLation A wi ll see your signal weakening. wh ile basestation B will ee your signal strengLhening_ and the two basestaLions transmit thi s informati on LO the switching office. AL some point the switching office computer will decide to switch your call from base Lation A LO basestation B. The computer assigns a new channel for th e call in cell B (remember. adjacent cell s use different sets of frequencies to avoid interference)_ and sends your phone a command (through basesLat ion A, of course) to switch to a new channel. Your phone swi tches to th e new channel and thu s begi ns communicaLing wiLh basestaLion B. Such swi tching may occur dozens of Limes while a car dri ves Lhrough a city dwing a phone ca ll , and is tran sparent to the phone user. SomeLimes th e swiLching fails. perh aps if the new cell has no available frequencies. resulLing in a " dropped" call.
Inside a Cell Phone Basic Components A cell phone requires sophisticated digital circuiLry LO carry OUL call . Figure 5.89 how Lhe insides of a typi cal basic cell phone. The printed-circuit boards include evera! chip implemenLing digiLal circuits. One of Lhose ci rcu its performs analog-Lo-digital conversion
How Cellular Phone Calls Work Suppose you are holding phol/e l in cell A of Figure 5.87. Wh en you turn on the cell phone, Lhe phone listens for a signal fro m a basestati on on a comrol freq uency, which is a special radio freque ncy used for communicaLing commands (raLher th an voice data) between the basestation and cell phone. If the phone finds no such signal, th e phone reports a "No Service" error. I f the phone find s the signal from basestati on A. Lhe phone Lhen Lransmits its own identifi ca tion (10) number to base taLion A . Every cell phone has its own unique lD number. (Actuall y, Lhere is a nonvolatile memory card inside each phone Lhat has Lhat lD number-a phone user can potentially witch cards among phones. or have mu ltiple cards for th e ~ame phone. switching cards LO change phone numbers.) Basestation A communicates Lhis ID number to the cemral switching office's computer, and Lhus the service provider compuLer database now record Lhat your phone is in cell A . Your phone intermitLently sends a comrol ~ i gn al to remind th e swi tch ing omce of the phone's presence. If '>omebody Lhen calls you r cell phone's number. the ca ll may come in over the regular phone sY'tem. which goes to the switching office . The ,witching omce computer database
(a)
(b)
(e)
Figure 5.89 Inside a cell phone: (a) handset. (b) battery and ID card on left.
ke~ pad
JJld
displJ~
in
ccnler. digital ircuilry on n printed-circui t board on right , tc) the two side-s of the prinloo
F
282
Register-Transfer LevellRTLI Design
5.11 Product Profile: Cell Phone
of a voice (or olher sou nd) 10 a signal Slream of Os and 1s, and anolher performs digitallo-analoll conversion of a received digital strea m back
(0
an analog signal. Some of the
circui ls. -lypicall y so ft ware on a microprocessor. exeCUle lasks lhal manage lhe various fealures of lhe phone. such as lhe menu syslem. address book. games, eiC. NOle that any daw Ihal you save on your cell phone (e.g" an add ress book. cuslomi zed ring lones, game high score information. elc .) will likely be slOred on a fl ash memory, whose nonvolalilily en~u res lhe data Slays saved in memory even if Ihe ballery dies or is removed. Anolher imponanl lask involves responding 10 commands from lhe Swilching office. Anolher task carried ou l by lhe digilal circu ils is fi ltering. One lype of filt ering removes the canier radio signal from lhe incoming radio freque ncy. Anolher lype of fillerin g removes noise fro m lhe digili zed audi o Slrea m coming from lhe microphone, before transmitting lhal stream on the outgoing radi o frequency. Let' examine fi ltering in more delail.
Filtering, and FIR Filters Filtering is pe rhaps lhe moSI common task performed in digi lal signal processing. Digilal signal processing operales on a slream of digi lal dala lhal comes from digitizing an inpul si!:mal. such as an audio. video, or radio signal. Such streams of data are found in count-
le;s electronic devices. such as CD players. cell phones. hean monilors, ultrasound machines, rad ios. engine conlrollers. eiC. Filterillg a dala slream is the lask of removing panicular aspec ls of lhe inpul signal , and OUlpulling a new signal wilhout lhose aspecls. A com mon fi llering goa l is 10 remove noise from a signal. You 've cenainly heard noise in aud io signals-ii 's thal hissi ng sound lhal 's so annoying on your slereo, cell phone . or cord less phone. You 've also likely adjusled a fi ller 10 reduce lhal noi se, when you adjusled the "lreble" conlrol of your Slereo (lhough lhat fil ler may have been implemented using ana log mel hods ralher lh an di gilal). Noise can appear in any type of signal, nOI jusl audio. oise mi ghl come from an imperfecl lransmilling device, an imperfecllislening device (e.g., a cheap microphone), backgrou nd noise (e.g., freeway sounds coming inlo your cell phone). eleclrical inlerference from other eleclric appli ances, etc. Noise lypi ca lly appears in a signal as random jumps from a smoolh signal. Anolher common filtering goal is 10 remove a carrier frequency from a signal. A carrier freque ncy is a signal added lO a main signal for the purpose of lransmitting thai main signal. For example. a radio slat ion mighl broadcasl a radio signal al 102.7 MHz. 102.7 MHz is lhe carrier freq uency. The carrier signal may be a sine wave of a panicular freq uency (e.g" 102.7 MH z) lhal is added 10 lhe main signa l, where lhe main signal is the music signal ilself. A receiving device locks on 10 the carrier freq uency, and then fil!e~ oul the carrier signal, leavi ng the main signal. An FIR filler (usually pronounced by saying lhe lellers " P' " I" " R"), shon for "Finite Impulse Response," is a very general filler design that can be used fo r a huge varielyof fillering goa ls. The basic idea of an FIR fi lter is very sim ple: multiply the present inpul va lue by a constan!. and add that re ul! 10 the previous inpul value limes a conslant , and add thai result 10 lhe nexl earlier inpul value limes a con lant. and so on. A designer u ing an FIR filter achieves a particular filtering goa l simply by choosillg Ihe F1R filler 's COllslalllS. Malhematica ll y. an FIR fi lter can be described as foll ow: Y( I ) = cOx.r(t)
+ (' I xX(I - I ) + c2xx( I -2) + c3X .« I -J) + c4 xx(I-4) + ".
i, the pre\enl lime slep. x is lhe inpul signal. and y i, lhe OUlput signal. Each lenn (c.g., CO*X(I)) is ca lled a lap . So the above equation represenls a 5·1ap FIR filter. I
283
FIR ~~I'S ~e some examples of lhe versalilily of an FIR fi lter. Assume we have a 5.tap ter. or slaners, 10 Simply pass a signal lhrough lhe filter unchanged, we sel cO 10 I d . . I ,an hwe el cl=c2-- c3-- c4-0 -. "'0 " amp I'Ify an IOpUI SIgnal, we can sel cO 10 a number arger t an I, perhaps selling cO 10 2. To creale a moothin o fil ler thai OUlputs the averaoe of the . . va lues. we can"SImply sel all the conSlants "10 . Ipresent val ue and lh e pasl ~our IOpUI eq ul va enl valu ~s lhat add 10 I, namely, c!=c2=c3=c4=c5=0.2. The results of uch a filter applied 10 a nOIsy IOpul Signal are shown in Figure 5.90. To smoolh and amplify. we can sel all conSlalllS 10 equi val I h . c!=c2=c3=c4= ' _ enl va ues I at add W omethlOg grealer than I. for example, . c5-1, resultlOg 10 5x ampllfi callon. To creale a smoothing filter thai only IOciudes lhe prev ious lWO rather lhan four inpul values, we simp ly sel c3 and c4 10 O. We see that we can build alilhe above different fillers j usl by changing the conSlanl values of an FIR fi lter. The FIR fi ller is indeed quile versatile. 1.5
1 - - - - - - - - -- - - - - - - - - - - - - , ____ original
1---1Jli/ol!~IIi;;:.----------
---...-
noisy -+- fir_av9-out
Ilil
-{) .5 r------------S)~~-----_~~
-1 r------------~~~~~---~ - 1.5 ' - - - - - -_ _ __ _ _ _ _ _ _ __ _ _ _~
Figure 5.90 R e~u lts ~f a 5·tap FIR filler wilh cO=<:I=c2=<:3=c4=0.2 applied 10 a nois)' signal. The ongmaJ signal IS a slOe wave. The noisy signal has random jump _The RR output (fir_:l\ ~oUl) i m.uch sm~lher than th~ noisy sig.nal. approaching the original signal. Olice that the FLR output i sllghlly shIned 10 Ihe nghl. mean ing Ihe OUlPUI is slightly delayed in time (probably a riny fra rian of a second delayed). Such slighl shifling is usual ly nOI imponanl 10 n particular application. . Thai versalilily eX lends even further. We can actually filter OUI a carrier frequen y uSlOg an FIR filter, by selllllg lhe coefficiellls 10 different value. carefully chosen 10 filter OUI a pani cular freque ncy. Figure 5.91 shows a main signal. ill I . thai we \\ am 10 transmit We can add that to a carrier signal , ill2, 10 oblain the composile ignal. ill _lotal. The SIgnal III_lOra /IS lhe SIgnal lhal would be the signal lhal i transmined by a radio lation. for example. wi lh illl being lhe signal of the mllsic. and ill2 lhe carrier freque nc~ . Now ay a lereo receiver receives that composile signal. and needs 10 filter OUI the carrier signal, so the music signal can be sent 10 the slereo peakers. To delermine h \\ I filler OUI lhe carrier signal. look carefully at the am pies (the small tilled squares in Figure 5.9 1) of that carrier signal. Olice lhal lhe sampling rale i' such that if \\e lake :10' sample. and add il 10 a sample from three time lep back. \\ e !!el O. That's be,:au,e f '" ~ po ilive poil1l. lhree samples earlier wa a negative poinl of the same magnitude. For a negalive poil1l. lhree samples earlier was a positive point of lhe same magnitude. nd for a zero poin!. lhree samples earlier was also a zero poin!. Like\\ ise. adding a "artier .ignal
28~
Register-Transfer Level (RTL) Design 5.12 Chapter Summary 2.5
l in 0,5 1
\
[J j~
oIl..r-ll L\
-0,5
M
H
1.5
1If .l!
'r
~
3
main signa l. iI/I.
R
~
-1 .5 -2 -2.5 Figure 5.91 Adding
.Jr\
(0
-
rI
M
rI \
In th is chapter, we described (Section 5. 1) that much digi tal desig n today involves designing processor-level components, and that design is do ne at what is called the register-transfer level (RTL). We Introduced (Section 5.2) a fo ur-s tep RTL design method for convening RTL behaV ior to a processor implementation, wi th that implementation consisting of a datapath controlled by a Contro ller. The RTL design method made use of the datapath components de fined In Chapter 4, and the contro ller des ign proce s defined in Chapter 3, which buil t on the combinational design process of Chapter 2. We provided several examples .of RTL design (Section 5.3), while poi nting o ut several pitfall and good design praCllces, and dlSC llSSlng the characteristics of control- versus data-dominated designs. We d iscussed (Secnon 5.4) how to set a circuit 's clock freq uency based on the circuit's critical path . We de monstrated (Section 5.5) how a sequent ial program. like a C program. could conceptuall y be conven ed to gates using some straightforward transforma tions that transform the C 11110 RTL behavior, which as we kn ow can then be converted to gates using the fo ur-step RTL deSign method. That demonstration sho ul d make it clear that a di"ital syste m's functionality can be im plemented as e ither software on a microprocessor or ~ a c ustom di g ital circuit (o r even as both). The diffe rences among software and custom circuit imp lementations are not related to what each can implement-they can both implement any fun ctionalit y. The diffe rences are instead related to design metrics like system performance. power consumption, size, cost, design time, and so on. Modem digital designers must therefore be comfon able migra ting fun ctionality between software on a microprocessor and custom dig ital c irc uits, in order to obtai n the best overall implementation with respect to constraints on design metries. We introduced (Section 5.6) several memory components commonl y used in RTL design, including RAM and ROM components. We also introduced (Sectio n 5.7) a queue component that can be useful d uring RTL des ign. We took a moment to di scuss (Section 5. 8) a general technique that we've been using throughout the book. hierarchy, which helps a designer to manage complexiry.
11
JT'U.
r,
'i
\ \' /~
ffll Joi \}
V.
l.-'
a carri er signal. i1l2. res ulting in a composi te signal
ill_fOfa!.
sample to a sa mple three steps later also adds to zero. So to filt er o ut the carri er signal , we can add each sa mple to a sample three time steps back. Or we can add each sample to 112 times a samp le three steps bac k. plus 112 times a sampl e three steps ahead. We can ac hieve this using a 7-tap FIR fi lter wi th the follow ing seven coe ffi c ients: 0 .5. 0, 0, 1, 0, 0. 0.5. S ince that sums to 2. we can sca le the coefficients to add to I, as fo llows: 0.25, 0, 0.0.5. O. O. 0.25. Applying such a 7-tap FIR fi lte r to the composite signa l res ults in the FIR ou tput shown in Fig ure 5.92. The ma in signa l is restored . We sho uld point out that we chose the mai n signa l such that thi s ex ample wo uld come o ut ve ry nicely--{)ther signals m igh t nO! be restored so perfect ly. But the exa mple de monstrates the basic idea, 2.5 r - - - - - - - - - - - - - - - - - --
-
----,
2f---------,--------------- ---- in_total f-----,..r-+\--f+-~------------ __ fir_out
In C hapte rs I through 5, we have e mphasized straightforward design methods for increas ingly complex systems, but we have not emphasized how to de ign those sy terns well. Im proving on Our designs will be the focus of the next chapter.
-1 ~---------~_4+_~~~,~~~~~~
-1.51 - - - - - - - - - - - - - - = ---\:+--I-+---\+_......- - - j -2 ~--------------------------~~~------~
-2.5L---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
285
5.12 CHAPTER SUMMAR Y
____ in_total -
f"+
rI \ fN....1 'J. Jtj \"1 J ' l ~ u u ~ ~ ~
..
-
-+- in1 ___ in 2
5. 13 EXERCISES
---"
Any prob le ms noted with an asteri k (*) represent especially chal lenging problems. Figure 5.92 Filtering out the carrier signal using a 7-tap FIR filte r wi th constants 0.25, 0, 0, 0.5, O. 0.0.25. The slight delay in the outpu t signa l typicall y poses no problem, While 5-tap and 7-tap F IR fi lters can cen ai nl y be found in practice, ma ny FIR filters may con tai n te ns or hundreds of taps. FIR fi lte rs can cenai nl y be im ple mented using software (and often are). but many applications require that the hundreds of llluitiplications and additions for every sample be executed faster tha n is possible in so ft wa re, leading to custom di gital circui t implementations. Exam ple 5.8 ill us trated the des ign of a c irc uit for an FfR filter. Many types of filte rs exist othe r tha n F IR fi lter;. Dig ital signa l fi lte rin g is pan of a large r field known as d igita l signa l process ing, o r DSP. DS P has" ri ch mathematical foundation and is a field of study in itself. Advanced fi lte ri ng me thods are what make cell phone conver>ations as c lear as they are today.
- - _.
-
-
._-----------
SECTION 5,2: RTL DESIGN METHOD
~
PLUS
5. 1 (a) Create a high-level Sla te machine that describes the following system beha\-jor. The '} tem h'15 an 8-bil input A. a single-bit input d. and a 32-bit ompUI S. On every clock C) Ie. if d= 1. the system shoul d add A 10 a ru nning sum and output thut sum on S. If d=O, the system should instead subtract. Ignore issues of overflow and underllo\\ , Oon'l forgel to include an initializa tion sta te. H im: Declare and use an internal register (0 keep the sum. (b) Add u I-bit input rs t to the system. When r s t =1. the system hould dear its sum back to O. 5,2 Crea te a high-level state machine for a simple data encryption/decryption dc\'i c. If:1 bit-input b is 1. the device stores the data from 3 J2-bit input I as \\ hat is kno\\T1 as an off ~( \"3lue. Lf b is 0 and another bit-inpu t e is 1. then the devkt! "en [,)plS" its input I b~ adding the stored olTsc t value to 1. and OUlput$ this encrypted "'title o\er 3 ~2-bil out Ul J. If ifure':.1d anothi'r
286
Register· Transfer LevelIRTL) Design 5.13 Exercises bit-input d i'\ 1. the device should "decrypt" the data on r by subtr
r---. PLUS
5.3
Crca.tc a hi2h-l evc l stale machine for n digita l bath-water conl roller. The syste m has ::J. 3-bil input ra t i-O ind icating the desired ratio of cold wate r to hal wa ter. and a bit input on indicating that (he water should flow. The system has two 4-bit o utputs hfl ow and efl ow,
conlr~ lIin 1! the hal water now rJte and the cold water fl ow rale. The sum of these two rates should ah~'JYs equnl 16. Your hi gh-level slate machine shou ld dClcnnine the output values for h f 1 01,01 and c flo w such that the r3 tio or hot wate r to cold w;lter is as close as possi ble to the desired rrt ti o. while th e total now is always 16. Him: As there are only 8 possi ble rat ios, a rea· sonablc solution may use one statc ror each ratio.
~·S
5A Create a high-leve l Slllte mac hine that initializes a 16x32 register fi le's contents to all Os, beginning the initial iz..llion when an input rs t is 1.
".-....
5.5 (a) Create a high-level state machine that adds each register or one 128x8 register file to the correspond ing registers or another 128x8 regis ter file. storing th e results in a third 128x8 register file. The system should onl y begin th e addit ion whe n a bit-input add is 1. and should not perrOnll the addition again until it has finished adding (onl y adding again if add is I). (b) Extend this system to ei ther add or subtract. using an additional bit-i nput OPt where op = I mea ns add . and op = 0 means subtrac!.
PLUS
5.6
5.10 (a) Use the RTL design method of Table 5. 1 to conVert the hi"h. level stale l1l:lchine in Fig~re 5.94 to a COntroller and a datapath. Design the datapath to Slmcturc. bUI design the controller to an FSM only, as was done in Figure 5.26. (b) "Design the COntroller s FSM down to structure.
287
Inputs: slart(bil), datal8 bilS), addr(8 bits), W wail(M) Outputs: w_dalalB bits). w_addrlB bits), w_.wlbil)
w_wr::1 5.1/ Create an FSM that interfaces w_addr=addr with the datapath in Figure 5.95. The FSM should use the datapath Figure 5.94 High-level stJte machine of bus to com pute the average value of interface with bus wait signal. the 16 32-bit elements of any Ad~ay A;:rray A is stored in a memory. with the first element at address"5 the second at a ress - . ,md so On •.Assum e that putting a new value onto the address line-s addr causes l~el' mcm f ory to almosl lI11mediarcly Output the read data on the M_data lines. leno-re the po i. I lIy 0 overflow. -
M
b
Design a hi gh-level state machine ror a 4-bit up-counter with co unt control input cnt. count clear input C1r . and a terminal count ou tput tc. Use the RTL design method of Table 5.1 to cOI1\'en the high-level state machine to a controller and :l dn tapath. Use a register and incre· mcntcr in the d:lIapath. not :l co unt er itself. Design the controller down to a state register and logic gates.
5.7 Compare th e up-counter designed in Exercise 5.6 with the up-counter design shown in Figure 4.48. 5.8 Creme a datapath fo r the Inpuls: A, S, C (16 bils) ; go, rsllbit) hig h-level state machine in Outputs: S (16 bits) Figure 5.93. Local registers: sum sum<5096 5.9 · Slaning with the soda machine di. penser design described in Example 5. 1, create a block diagram and sum: high·level state mac hine for sum+C a soda machine dispenser Isum<5096)' that has a choice of t\vo soda types. and that also provides change to the consumer. A Figure 5.93 Sample hi gh-leve l state machine. coin detector provides th e circuit wi th a I-bit input c that becomes 1 for one clock cyc le when a coin is detected, and an 8-bit input a indicating the coin's va lue in cents. Two 8·bit inputs s I and s2 ind icate the coS! of the two soda choices. The user s soda selecti on i con trolled by two bUllons b I and b2 that whe n pushed will ou tput I for one clock cycle. If the user has inserted enough change for their
0-
_
.
o' i
~
. . ..
., _
_
_ _ _ __
average Figure 5.95 Datapmh for computing the :lverage of 16 elements of an arm) .
5.12 Using the RTL design method show n in Table 5. 1. create an RTL desien of 3 reaction timer circuit that measures the time elapsed between the illumin3lion of a ligh; and Ih~ pressing of a button by ;1 user. The reaction timer has three inputs. a clock inpUi elk. 3 fCSet input rsl. and :1 bUllon input B. and three OlHpUIS.:1 light enab le output lell. a IO-bit rea tion time output nime. and a slol1' Output ind ic~H ing the lIser was not f:lst enough. The reaction timer \\ orks 3..\ follows. On reset. the reacti on timer waits fo r 10 seconds before iIIuminatine the lieh! b\ scltine lell to I. The reaction timer then measures the len!.!.lh of Lime in l11i11i~e~n
288
Register-Transfer Level (RTL) Design
5.13 Exercises
289
5.13 Usc the RTL design method shown in Table 5. 1 to conve rt th e high-level stal e machi ne in
Inputs : byte a .
Figure 5.74 to a controller and a datapath. Design the dawpa lh 10 structure. but design the controller 10 the poin t of an FSM only. as was done in Figure 5.26.
byte b.
Outputs : byte ged .
bi t
bit go done
GCD: SECTION 5.3: RTL DESIGN EXAM PLES AND ISS ES
whi le(])
For the following problems. design the da tapath to stru cture. bU I design the controller to an FSM on ly. as done in Figure 5.26.
whi le( !go ) : done:
5.1~ Usi ng the RTL design method shown in Table 5. 1. create an RTL dc!\ign thai computes the
0;
While (
sum of all positi ve numbers within a 512-word register Hie A consistin g of 32-biL numbers
!:
if(
stored in IWO'S co mpl ement form .
5.15 Using the RTL design meth od shown in Table 5. 1. create an RTL design that computes the sum of all positive numbers from a set of 16 separate 32-bit regis ters storing numbers in two's complement form. Make the design as fast as possible by performing as many computations concurrently as possible. H im: Thi s is a data-dominated design.
b )
b ) I - b;
el se
(
b - a:
b
~
=
a:
5.16 Using the RTL design method shown in Table 5.1. create an RTL design th at outputs the maximum value found within a regi ster fi le A consisting of 64 32-bit numbers. 5.17 Using the RTL design method shown in Table 5.1. creme an RTL design that outputs a warni ng signal whenever the average temperature over the past fou r samples exceeds a userdefined value. The circuit has a 32-bit input CT indicating the current temperature reading, a 32-bi t input \VT indicating the user-specified temperature at which the warni ng should be enabled. and a button input eI,. that will disable the warning. When the average temperature exceeds the user-specified warning level. the ci rcuit should assert the output W to enable the warning. The warning output should remain high unti l th e elr button is pressed. Him: You can use a right shift to implement the divide within your datapath.
ged
done :
5.25 Use the RTL desig n method shown in Table 5.1 to convert the high-level state machine you c re~tcd in Exercise 5.24 to a controller and a datapath. Design the dalap:llh to structure. but deSIg n the COntro ll er to the po int o f an FSM only. 5.26 Conven lh~ f~lIowing C-like code, which calculates the maximum difference between any two numbers wlthm an array A consistin g of 256 8-bi t values. into a high-level Slate machine.
5.18 Using the RTL design method shown in Table 5. 1, create an RTL desig n fo r a di gital filter that ou tputs th e average of the curren t 32-bit input and the prev ious 32-bit sample. Him: You can usc a ri ght shift to implemcnt the divide within your datapath.
Input s : byte a(256).
5.19 Ass uming an inverte r has a de lay of I ns. all other gates have" de lay of 2 ns. and wires have a delay of I ns. dete rmine the cri ti cal path for the full-adder circu it shown in Figu re 4.3 I.
done:
i
5.21 Assuming an inverter has a delay of I ns. a ll other gates have a delay of 2 ns. and wires have a delay of Ins. detennine the cri ti cal path for a 4x I multiplexer.
if(
if(
-
-
-
-
ali]
max_ diff done -
j -
< min) I >
max)
(
ali]:
- i + 1:
5.24 Convert the following C-like code. which calculates th e greate,t C0l111110n div isor (GCD) of the two 8-bit number~ a and b. into a hi gh-level sta te machine.
-
ali]
max -
SECTION 5.5: BE I-IA VIORAL-LEVEL DES IG : C TO GATES (O(yrIO AL)
-
0:
min = ali]:
(b) Ass uming all gates have a del ay of 2 ns and the 16-b it up-counter has a delay of 5 ns. and wires ha ve no delay, determine the critical path for the laser-bascd distance measurer. (c) Calculate the corresponding maximum clock frequency for the circuit.
-
0:
= 0:
max :
5.23 (a) Convert the laser-based dis tance measurers FSM . shown ill Fig ure 5.21, to a state register and logic.
-
done
min - 255 : II largest 8-bit va lue while( i < 256 ) (
5.22 Assuming an in verter has a de lay of I ns. and all other ga tes have a de lay of 2 ns. detennine the cri ti ca l path for an 8-bit carry-ripple adder: (a) assuming wires have no de lay. (b) assumi ng wires have a de lay of Ins.
•
bi t
while( !go);
5.20 Assuming an invener has a delay of I ns. all other gates have a delay of 2 ns, and wires ha\'e a delay of Ins. detennine the crit ical path for the 3x8 decoder of Fig ure 2.50.
# -
bit go
Outputs : byte max_di ff. MAX _D I FF: whi I e(]) (
SECTION 5.4: DETE RMINING CLO CK FREQUENCY
- -.
1:
]:
max - min:
290
Reg ister· Transfer Level (RTL) Design
5.13 Exercises
5.27 Use the RTL design method shown in Table 5. 1 to conve rt the high-level Siale machine you cr~ated in Exercise 5.26 to il controller and a datilpillh. Design the dawpa(h to structure, but
291
Exerc ise 5.32. convert the revised C code into a high· level state mac hine. Use the RTL design meth od shown in Tabl e 5. J to convert the high-level Sia le machine you created in Lhe previous probl em to a controller and a datapmh. Design the dalapalh (0 structure, but design the controller to the poi nt of an FSM onl y..
design th e controller to the poi nt of an FSM onl y.
5.28 Convert the foll owing C-likc code. which calculates the number of limes lhe value b is found within an array A co nsist ing of 256 8-bi t values. into a high-level stat e machi ne.
5.34 * Con ve rt the while ( i < 256 ) loop with in the C code description of Exercise 5.26 to a for () loop as described in Exercise 5.32. Using the for () loop template you created in Exercise 5.32, conve rt the revi sed C-like code into a high-level state machine. Use the RTL design method shown in Tabl e 5. 1 to convert the high-level stale machine you created in the previous probl em to a controller and a da tapath. De sign th e data path to structure. but design th e controller to the poin t of an FSM onl y.
Inputs : byte a[256] . byte b . bit go Outputs : byte freq . bi t done
FREOUENCY : "hi 1 e( 1) ( while( !go) :
5.35 Compare the time required to execute the following computation using a custom circuit versu using soft ware. Assume a ga te has a delay of I ns. Assume a microprocessor executes one instrucLi on every 5 ns. Assume th at n:::: I 0 and 01::::5. Estimates are acceptable: you need not design the circuit, or determine exactly how many software instructi ons will execu te.
done = 0 : i = 0: freq = 0 : while ( i < 256 ) ( i f ( a [i] == b ) (
for (i = 0 : i
0 : j < m. j++) + c[i]*x[i + j] :
for (j
freq = freq + 1 :
y[ i]
(
s:
l '
done
SECTION 5.6: MEMORY COMPONENTS 5.29 Use the RTL design method shown in Table 5. 1 10 conve rt the high- level st ate machine you created in Exercise 5.28 to a controller and a datapa th . Design th e data path to structure, bUI design the contro ller to the point of an FSM onl y.
5.30 Develop a te mplate for converting a dol state machine.
5.36 Calcul ate the approx imate number of DR AM bit storage cells th at wi ll fit on an IC with a capaci ty of 10 million transistors. 5.37 Calculate the approx imate number of SRAM bit storage ce lls tha t will fit on an IC with a capaci ty of 10 million transistors.
)while loop of th e fo llowing form to a high·level
5.38 Summari ze th e main differences between DRAM and SRAM memories.
do (
5.39 Draw a complete logic internal Slructu re for :l 4:<2 DRAM (four words. 2 bilS each). clearly labeling all intern al components and connecl.ions.
II do while statements ) while (cond) :
5.40 Draw a co mpl ete logic intern al structure for a 4x2 SRAM (four words. _ bits each). dead) labeling all internal components and connections.
5.31 ' Convert th e while ( a ! = b ) loop within the C code descriptio n of Exercise 24 into a doe )",hile loop as described in Exerc ise 5.30. Using the doe Jwhile loop templ ate you created in Exercise 5.30. convert th e revised C code into a high-Icvel statC machine. Use the RTL design method shown in Table 5. 1 to co nve rt the hi gh· level state machine you created in the previous problem to a conlro ller and a da tapath . Design th e datapruh to structure, but design the con troller to the point of an FSM onl y.
SA l * Design an SRAM memory cell with a reset inpUi that when enabled \\ ill set the !TIernoI') cell's con tents to O.
SECTION: READ-ONLY MEMORY (ROM ) 5.42 Summ arize th e main differences between EPROM and EEPRO M memories.
5.32 De ve lop a template for conve rtin g a for () loop of th e fo llowing form to a hi gh· level state machine.
5.43 SUl11marize the main differences between EEPROM and Hash memories.
for(i=start : i
SECTION 5.7: QUEUES (FLFOS) 5.-'4 For an 8-word queue. show the queue 's intemal state and provide the value of popped datu for th e fo llow ing sequences of pushes and pops: (I) push A. B. C. D. E. (2) pop. (3) pop. H) push U, V. W. X. Y. (5) pop. (6) push Z. (7) pop. (8) pop. (9) pop.
1/ for s ta ements
5..15 Create nn FSM describin g the queue controller of Figure 5.7 . Pa~ careful :JHeution t, rcctl y sell ing the full and empty OUlputS.
5.33 ' Convert the "'hile ( a ! = b ) loop within the C code desc ript ion of Exe rcise 5.24 to a f or ( ) loop as desc ribed in Exercise 5.32. , ing the for () loop temp late you created in
-
--
.- -
._----------
j
I.
)r-
292
Register-Transfer l evellRTl J Design
5A6 Create an FSM describi ng the queue con tro ller o f Figure 5.78.
5.13 Exercises bIll
behavior lhal ignores ;1I1Y pushes when the queue is full. and ignores pops of an empty queue (outpuuing 0).
SECTION 5.8: HI ERAR C HY-A KEY DESIG ' CO 'CEPT SA7 Compose a 20- inpul AND ga le from 2- in pu l AN D ga les.
SAS Compose a 16x I IllUX from 2x I l1l uxes. 5A9 Compose
::I
-tx 16 decoder with enable fro m 2x4 decoders with enable.
5.50 Compose a 1024x8 RAM using onl y 5 12x8 RAM s. 5.51 Compose a 5 12x8 RAM using onl y 5 12x4 RAM s. 5.52 Compose a 1024x8 ROM usi ng onl y 512x4 ROM s. 5.53 Compose a 2048x8 ROM using onl y 256x8 ROM s. 5.54 Compose a I024x 16 RAM using only 512x8 RAM s. 5.55 Compose a 1024xl2 RAM us in g 512x8 and 5 12x4 RA Ms. 5.56 Compose a MOx 12 RAM using only 128x4 RAM s.
5.57 *Writc a program that takes a parameter ,and 3utomm ica ll y builds an N-inpul AND gate from 2-inpul AND gotes. Your program mere ly need indicate how many 2-inpu l AN D gales exist in each level. from which we could easily detenninc th e connec tions.
-- -
-
-
------------
293
wilh error-preventing Chi-Kai staned co ll ege as Hi gh-end chips. like those involved in networking, are an engineering major, and quite costly. and requi re careful design. "The software became a Computer design process and th e chip design process are Science major due to his fundamemall y differe nt. Software can afford to have bugs developing interests in because patches can be applied. Silicon is a different algorithms and in net- story. The one time expenses to spin a chip are on the works. After graduating. order of $500.000. If the re is a show-stopping bug. you he worked for a Silicon may need to spend another $500,000. This constraint Valley stanup company means the verification approach taken is quite differentthat made chips for com- effecti vely: there can be no bugs." At the same time, these puter networking. His first chips must be designed quickly to beat competitors to the task was to help simulate those chips before the chips were market. making th e j ob "extremely challenging and buill. For over 10 years now, he has worked on multiple exciti ng:' generati ons of networking devices that buffer, schedule, One of the biggest surpri ses Chi-Kai encountered in his :md switch ATM network cells and Internet Protocol job is the "incredible imponance of good communication packets. "The chips required to implement networking skills: ' Chi-Kai has worked in teams ranging from 10 devices are complex components th at must all work people to 30 people, and some chips require teams of over toge ther a lmost perfectl y to provide the bui lding blocks of 100 people. "Techni calJ y o utstanding engineers are tel ecommunicati on and data networks. Each generati on of useless unless they know how to collaborate with others devices becomes successively more complex." and di ssemi nate their knowledge. Chips are only getting When asked what skill s are necessary for hi s job. Chi- more complex-individual blocks of code in a given chip Kai says "More and more. breadth of one's skill set have the same complexity as an entire chip only a few matt ers more than depth. Being an effective chip engineer years ago. To architect, design. and implement logic in req uires the ability to understand chip architecture (the big hardware requires the ability to convey complexity." picture), to design logic, to verify logic. and to bring up Funhermore. Chi -Kai points o ut th at 'just like any social the silico n in the lab. A ll these pans of the design cycle en tity, th ere are politics involved. For example, people are interpl ay more and marc. To be trul y effecti ve :1I one worried about aspiration for promotion. financial gain. part icular area requires hands-on knowledge of the others and job securi ty. In thi greater context. the team still as well. Also, each requires very different skills. For must work together to deliver a chip:' So, contrary to the example. verification requires good software programming conceptions many people have of engineers. engineers abil it y, while bring up requires knowing how to use a logic must have excellent people skill . in addition 10 strong analy zer-good hardware ski lls:' technical ski lls. Engineering is 3 socia] discipline.
6.1 Introduction A tradeoff impro l'es some criteria at the
6
expellJe of (Jlher criteria oj imerest 101lJ. A"
gate-delays, as shown in Figure 6.2(c). Which circuit is bener. that for Gl or for G2? The answer depends on whether the size or delay criteria is more imponant to us. When we improve one criteria at the expense of another criteria of interest to us. we have performed a tradeoff.
oplimiznlioll
Optimizations and Tradeoffs
improlres (II/ criteria of illlereJI to liS, or improves .wme of rhoJe crirerioll'ir/wllr U'orJellillg ril e
arhers,
14 transistors
Gl
w y z
involve additional criteria. 16 transistors
'il' = D l g ate-delays U
y-
'il'::f'\
r
Fl
4 transistors
1 gate-delay W- D
F2
x-
2°L
~15
.~ .~ "' c
'"
y=-LJ
:::. 5
F1 = wxy + wxy'
F2 = wx
(a)
(b)
e Fl
10
eF2
1
2
3
4
delay (gate·delays) (e)
Figure 6.1 A circuit tran sformalion that improves both size and delay. (hal is, an optimiza tion: (a) original eireui !. (b) optimi zed circuit. (c) plot of size and delay of each circ ui!.
Consider the circuit for the eq uati on involvi ng Fl shown in Figure 6. I(a) . The ci rcuit 's si ze . assumil/g tlVO t/'{ll/ sistors per gate iI/put (a nd ignoring inverters for simplicity), is 8 * 2 = 16 tran sistors. The circuit 's delay, which is th e longest path from any input to the output , is two gate-delays. We could algebraica lly transform the equation into th at for F2, show n in Figure 6. I(b) . F2 represents the same fun cti on as Fl. bu t requires onl y fo ur transistors (in stead of 16) and has a delay of onl y one ga te-delay (instead of two) . The transform ation improved both size and del ay, as shown in Figure 6. 1(c). Wh en we perform transfo rmati ons that improve all criteri a of interest to us, we have performed an optimizatioll. Now consider the circuit for a different fu nction , implementing the equation for Gl in Figure 6.2(a). The circu it's size (assuming 2 transistors per gate input) is 14 transisto~ and the ci rcu it', delay is two gate-de lays. We could algebraica ll y transform the equation Into that shown for G2 in Figure 6.2(b). which result$ in a circuit having only 12 transisto". However, the reduction in transiMors comes at the ex pense of a longer delay of three
--
-
-
------------
G2 = w(x+y} + z (b)
G2
20L: eG l
'§' 15 III ~ .~ '!?? 10
eG2
~ 5
1
2
3
4
delay (gate-delays) (e)
Figure 6.2 A circui t transformation that improves size bUl worsens de lay. lhal is. a Iradeoff:
The previous chapters descri bed how to design digita l circui ts using straightforward techniques. Thi s chapter will describe how to design belle,- circuits. For our purposes, beller means circuits that are smaller. faster. or consume less power. Real world design may
.-
y
z - _ _ _--l
(a)
294
12 transistors
:grgate-delays :~3gate-delays
G1 =wx+wy + z
6.1 INTRODUCTION
295
You likely perform optimi zations and tradeoffs every day. Perhaps you regularly commute by car from one city to another via a particular route. You might be interested in two cri teria: com mute time and safety. Other criteria. such as scenery along the route. may not be of interest to you. If you choose a new route that improves both commute time and safety. you have optimized you r commute. If you instead choo e a route that improves safety at the expense of increased commute time, you have made a tradeoff (and perhaps a wise one at that). Figure 6.3 illustrates optimi zations versus tradeoffs for three different staning designs, with the criteria of delay and size, smaller being beller for each criteria. Obviously, we prefer optimi zations over tradeoffs, since optimizations improve both criteria (or delay at least improve one criteria without detay (a) (b ) worsening another criteria, as shown by the horizontal and vertical arrows on the Figure 6.3 (a) Optimizations, versu (b) tradeoffs. left side of the fi gure). But we can't always improve one criteria without worsening another criteria. For example, if a car designer wants to improve a car's fuel efficiency, the designer may have to make the car smaller-a tradeoff among the criteria of fu el efficiency and comfort . Some general criteria commonly of interest to digital sy tem designers include:
;~: ,~, l~ :~
Performallce: a measure of execution time for a computation on the stem.
Size: a measure of the number of transistors, or si lic n area, f a digital system. PO KIer: a measure of the energy consumed per second f a sy ' tem, direcll~ relating to both the heat generated by the system and t the bane!) encr:,.!) nsumed by computations. Dozens of other criteria exist.
296
6.2 Combinatio nal Logic Optimizations and Tradeoffs
Optimizations and Tradeoffs Optimi zat ions and tradeoffs can bc made th roughout nearly a ll stages of digital design. T his c hapter descri bes some common optimi zatio ns and tradeoffs for some common c ri te ri a. al various stages o f di g ita l design.
297
EXAMPLE 6.1 Two- level logic size optimization using algebraic me thods Minimi ze the nu mber of litera ls and tenns in a two- level impleme ntati on of the equation:
F - xy z + xyz ' + x ' y ' z ' + x ' y 'z Let's minimi ze using algebraic transfonnalions:
6.2 COMBI NATIONAL LOGIC OPTIMIZATIONS AND TRADEOFFS
F - xy ( z + z ' ) + x ' y , ( z + z ' )
In Chapter 2. wc descri bed how to design combinat io na l logic, name ly, how to conven desi red combin ational behavi or into a circuit of gales. There are optimizatio n a nd tradeoff me thods we can appl y 10 make those c irc uits beller.
F
/ " rhe 1970s/
1980s. whe" Transistors were costly (l'.g .. cen ls each).
minimi:arion !!1.fiJ.!J1. si:e
m;";",;:O/ion. which dominated digllal design. Today 's cheaper transistors (e.g .. O.OOO} ufltseach) make
optimi:tJrions of
other criteria equally or more crilical.
We' ll assume every logic gate in put req uires two transisto rs. So a 3-input logic gate (whether an AND, O R, NAJ\fD, or NO R) would req uire 3 • 2 = 6 transistors. The circuits inside logic gates shown in Section 2.4 sho ul d c larify why we assume two transistors per gate in put.
The previous example showed the most common algebra ic transformation us ed to simpli fy a Boolean equation in sum-of-products form , a tra nsfo rma tio n that generally can be wril1en as: ab + a b ' ~ a ( b+b ' ) = a * l = a Let's call this transformation combining terms to eliminate a variable. More formally. this transformation is known as the ullitillg theorem . In the previous example, we appl ied this transformation tw ice, once with xy bei ng a a nd z being b. and a second time with x ' y' being a and Z being b. Sometimes we need to duplicate a te rm in order to inc re ase opportunities for combining terms to e liminate a variable. as illustrated in the next example.
EXAMPLE 6.2
Reusing a te rm dur ing two-level logic s ize opti mizatio n Minimize the number of literals and tenns in a two-level impleme ntati on o f the equation:
F - x ' y 'z ' + x 'y ' z + x ' yz Yo u mi ght notice twO opponu nities to combi ne tenns to eliminate a variable:
We' ll ignore inve n ers when determini ng the number of tra nsistors, fo r simplicity. We can view the problem of two-le vel logic size optimi zation algebraically as the problem o f minimizing the number of literals and terms of a Boolean equation that is in sllm-o!-products form. The reason we can view the prob lem a lgebra ically is because, reca ll fro m Secti on 2.4. we can translate a sum-o f-prod uc ts Boolean equation direcOy to a circuit using a level of AND gates followed by an O R ga te . For exa mpl e, the equation F ~ wxy + wxy ' fro m Figure 6. 1(a) has six litera ls, w. x, y , W, x, and y' , and two terms, vlXy and wxy " for a tota l o f 6 + 2 = 8 litera ls a nd te nn s. Eac h literal and each term translates approx imate ly to a gate input in a c irc uit, as shown in Figure 6. I(a)-the IlIera" translate to AN D gate inputs, and the terms to O R gate in puLs. T he c irc uit thus has 3 + 3 + 2 = 8 gate inpu ts. With two transistors per gate inp ut, the c irc uit has 8 • 2 = 16 transistors. We ca n minimize the num ber o f lite ra ls and te rms algebraically: F - wxy + vlxy' = wx ( y+y' ) - WX , which ha. only two litera ls. W ;lIld x , resulting in 2 gate IOput . or 2 * 2 = 4 tra nsistors. as shown in Figure 6. 1(b). (Note that a one-term equation d oc~n ' t require an O R gale.)
xy *l + x ' y ' * l
There doesn' t seem to be any further min imization we can perform. Th us, we've reduced the circ uit from 12 literals and 4 terms (meaning 12 + 4 = 16 ga,e inputs. Or 32 transi ,ors), down to only 4 literals and 2 terms (meani ng 4 + 2 = 6 gate inputs. or 12 transistors).
Two-Level Size Optimization Using Algebraic Methods Implementing a Boolean function using onl y two leve ls of gates-a level of AND gates followed by one OR gate-usua ll y results in a circ uit hav ing minimu m de lay. Recall from Chap ter 2 that any Boolean equation can be wrille n in sum-of-products fo rm, simply by xyw + xy z . Thus, any "multi plying out" the equation- for exam ple, xy ( w+z ) Boolean function can be implemented using two levels of gates, simply by converting its equation to sum-of-products fonn and then using AND gates for the products followed by an OR gate for the sum. A po pular optimizat ion is to minimize the number of transistors of a two-level logic c ircuit imple mentation o f a Boolean fu nction. Such optimization is tradi tiona lly called twolevel logic optimiw tion , or sometimes two-level logic millimiw tioll . We 'll re fer to it as two-level logic size optimization , 10 d istinguish such optimization fro m the increasingly popular optimizations of performance and power, as we ll as other possible optimizations. To optimi ze size, we need a method to determine the num ber of transistors for a given c irc ui t. We' ll use a simple method fo r dete rm ining the number of transistors:
=
F - xy + x ' y '
I: x 'y'z ' + x ' y ' z - x ' y '
2: x' y ' z +
X'yz
= x'Z
Notice that the 'enll x ' y , Z appears in both opponunities. but that tenn onl y appears once in the original equation. We ll therefore fi rst replica,e 'he tenn in the original equation (such replication does n' t chnnge the fu ncti on, because a :: a + a) so th ai we can use the tenn twice when rombi ning terms to eliminrue a vari nble,:J. fo llows:
F - x'y ' z' + x ' y'z + x ' yz - x ' y ' z ' + x'y'z + x'y'z + x ' yz F - x ' y , (z+z ' ) + x ' Z (y ' +y) F -x ' y ' +x ' z After we have combi ned terms to eliminate a varia ble, the res ulring tenn mi!!ht a1s be combinable wit h other te rms to e liminate a variable. as sho \\ n in the ~ -Uowing exa mple.
298
6 Optimizations and Tradeoffs
6.2 Combinational Logic Optimizations and Tradeoffs
EXAMPLE 6.3 Repeatedly combining terms to eliminate a variable Minimi ze the number of literals and terms in 3 two-leve l implementatio n of the eq uati on:
G : xy ' z ' + xy 'z + xyz + xyz ' \Ve can combi ne the first
IWO
G
=
t
xy ' (z '+ z) + xy(z+z ' ) xy ' + xy
l
We can combine the twO re maining term s to elimi na te a vari abl e:
G
xy ' + xy x(y ' +y)
G:
x
G
t
In the prev ious examples, how did we "see" the opportu ni ties to combine tenms to eliminate a variable'? The examples' origi nal equations happened to be wri tten in a way that made see in g Ihe opportunitic easy-ternls th at coul d be combined were side-by· side . Suppose in; tead the equati on in Example 6. 1 had been written as:
IflaK-map.
adjacell1 cells differ ;1/ ('.welly olle mri(lble.
F : x ' y ' z + xyz + xyz ' + x ' y ' z ' That's Ihe same fu nction, but the terms appear in a diffe rent order. We might see that the middle two ternlS can be combi ned: x 'y ' z + xyz + xyz ' + x ' y ' z ' x ' y ' z + xy(z+z ' ) + x 'y ' z ' x ' y ' z + xy + x ' y ' z ' But then we might not see that the left and right lenns can be combined. We Iherefore might stop min imizing. thinki ng that we had obtained a full y min imi zed equation. There is a visua l method to help us see opportunities to combi ne terms to eliminate a variable. a method we now describe.
K-lIIl1PS enable liS
(osee
opportunities to
combine
le rlllS
to eliminate a mrioble.
A Visual Method for Two-Level Size Optimization-K-Maps Kamal/gil Maps, or K- maps fo r short , are a visual method intended to assist humans to algebraically minimize Boolean equations having a few (two to fo ur) variables. They actu· ally are not common ly used any longer in design practice, but nevertheless, they are a very effective means for l/Iulersf(lIIdillg the basic opti mizat ion methods underl ying today's auto· mated tools. A K- map is essenti all y a graphical representation of a truth lable, meaning a K-map is yet another way to represent a function (the other ways including an equation, truth table. and circu it). The idea underl ying a K-map is to graphica lly place minlenns adjacent to one another if those mintenns differ in one variable only. so that we can actually "see" the opportuni ty for combi ning terms to eliminate a variable.
Three-Va riable K-Maps Figu re 6.4 shows a K-map for the equalion : F - x ' y ' Z + xyz + xyz '
which is the eq uation from Example 6.1 but wi th corresponds notice not terms appearing in a di fferent order. The map has to xyz;ooo, /inorder or x'y'z' eight ce lls, one fo r each possible combination of F yz i vari able values. Let's examine the cell in the top 1t 10 00 " Ot row. The upper-left cell corresponds to xyz:OOO, 0 t 0 0 mea ning x ' y , z ' . The ne., t cell to the right corresponds to XYZ:00 1, meaning x ' y ' z. The nex t ce ll 0 0 1 t 1 to the right corresponds to xyz :011 , meaning ]\, x' yz. And the rightmo t top cell corresponds to '~ -- -- - ---- -------- ----"" trea t left and right xyz:010, meaning x ' yz'. Notice that the edges as adjacent too orderi ng of those lOp cells is 1I0t in increasin o binary order. Instead. the order is ODD. 00 l. 01 Figure 6.4 Three-variable K-map. 010. rather than ODD, 001, 010, 011 . The ordering is such that adjacellt cel/s differ in exactly olle variable. For example. the cells for X ' Y , z (001) and x ' yz (011) are adjacent. and diffe r in exactl y one variable. namely. y. Likewise. the cells fo r x ' y , z ' and xy ' Z' are adjacent. and differ only in variable x. The map is also assumed to have its left alld right edges adjacellt, so the rightmost top cell (010) is adjacent to the leftm ost top cell (00 D)- note those cells too differ in exactly one variable. Adjacent means abutted either hori zontally or vertically. but 1I0t diagonal/y. because di agonal cell s differ in more than one vari able. Adjacent bottom row cells also differ in exactly one vari able. And cells in a colu mn also differ in exactly one variable. We can represent a Boolean function as a K-map by placi ng Is in the cells conresponding 10 the fun ction's mimenns . So for the equation F above. we place a 1 in cells correspond ing to min lerms x ' y' z, xyz, xyz ' . and x' y ' z ' . as shown in Fi2ure 6A. We place Os in the remaining cells. Notice that a K-map i j ust anotller repres;ntation of a lruth table. Ralher than showing the output for every poss ible combination of inputs using a table. a K-map uses a graphica l map. Therefore. a K-map is yet another representation of a Boolean fun cti on. and in fact is another standard representation. The usefulness of a K-map for size min im ization is that. because the map is designed such that adjacent ce ll differ in exactly one vari able. then we know that (\\,0 adjacent 1s ill {I K-map indicate tlia l we can combine the {H'O m;llterms TO eliminate a l'ariable. 10 other words. a K-map lets us easil y see when we can combine two terms to eliminate a variable. We indicate such combining by drawi ng a circle around two adjacent Is. and then we show the resulting term aft er the differi ng variable i removed. We iJlu ITate in the following example.
I
terms to eliminate a variab le. and the lasl Iwo terms also:
G
299
x'y ' z '
EXAMPLE 6.4 Two·levellogic size optimization using a K-map Mi nimize th e number of literals and le m lS in a two-level imp lement~l li on of the equ:.uion:
F
~
xyz + xyz ' + x ' y ' z ' + x ' y 'z
Ole that this is the same equation as in Example 6.1. \Ve creme a K- map represcllI ing the runclion. shown in Figure
6.5. We see adjacent Is at the upper left of the map. so we circle Ihose Is to yield Ihe Icn11 ' y ' -i n olher \\ orus. the circle is II sltorf/Illlld notation for).. y , Z + Y. z I
I
I
F yz
Ot
t1
to
oC
t
1 ) 0
0
1
0
o(
1
00
t
x'y' Figure 6.5 Minimizing vnriabk fun 'tion
""
~
J thm.~
u~ing l
K-m.lp.
300
Optimizations and Tradeoffs '" x ' Y
I.
6.2 Combinational Logic Optimizations and Tradeoffs
Likewi se. we see adjacent 1s at the bottom right circle of the map. so we draw a circle
representing xyZ + xyz ' - xy. Thus. F
~
Sometimes, we need to draw circles Ihat include the same 1 twice. That's okay. For example, consider the equation:
x' y' + xy.
Recall fro m Ex ample 6.3 that someti mes terms can be repeatedly combined to elim-
I
inate a variable. res ulting in even fewe r terms and literal s. We can redo th at example
using a diffe rent order of simpli fi cations as follows:
G G
xy ' z ' + xy ' z + xyz + xyz ' x(y'z ' + y ' z + yz ~ yz ')
G
x(y ' (z ' +z) + y(z+z ' ))
G
x (y ' +y ) x
G
Not ice that Ihe second line above ANDs x wit h the OR of all possible combinations of vari ables y and z. Obviously. onc of those combin ati ons of y and z will be true for any values of y and z. and thus the subex pression in parentheses will always evaluate to 1. as we algebraically affi rmed in the latter lines above. K-maps also help us graphicall y see Ihis situaG yz tion. In addi tion to helping us see when we can combine two mi nlcrms 10 eliminate a vari able.
K-maps give us a graphica l way to see when we can
0
combine fo ur minterms to eliminate two variables.
1
A/nap drau the lar~~SI
Circles
posJtble to £"Over the
1.1 In a K·map.
00
01
11
10
0
0
0
0
1
1
1
1
C
~
We merely need to look for four adjacent cells. where the cell s form either a rectangle or a square Fi gure 6.6 Four adjacent 15. (bul not a shape like an " L"). Thosc four cell s will have one variable the same. and all possible combinati ons of the other two variables. Figure 6.6 shows the earlier function G as a threevariable K-map. The map has four adjacent 1s in the bottom row. The four minterms correspond ing 10 those Is are xy , z ' . xy , z . xy z . and xy z ' - note that x is the same in all fo ur minterms. whi le all four combinations of y and z appear in those minterms. We draw a ci rcle around the bottom four 1s to represent the simplification of G shown in the equalions above. The result is G ~ x. In other words. the circle is a shorthand notation for the algebraic simplifi cation of G shown in the five equ ations above. 'ate Ihat we could have drawn circles around G yz the left IWO 1s and the ri ght two 1s of the K-map. 00 0 1 11 10 as shown in Figure 6.7. result ing in G ~ xy' + xy . Clearly, G can be further simpl ified to 0 0 0 0 0 x (y ' +y) ~x . Thus, we shoul d always draw the 1 1 1 1 biggest circle possi ble. in order to best min imize the eq ualion. xy xy As another exa mpl e of four adjacent 1s, conFig ure 6.7 Nonoplimal circles. sider the equati on:
.Y
It 's OK 10 co\'er a I more thcm ollce
to mi"imi:.e mulliple terms .
o
00
10
0
o
o
o
Figure 6.9 shows the K-map for that equation 's Figure 6.8 Four adjacenl Is. fun ction. We can draw a circle around the bottom four 1s to reduce those four mi nlerms 10 just x. But that leaves the single 1 in the top row. correspond ing to minterm x ' y ' Z . We have 10 include that minterm yz y'z in the minimi zed equation, since if we left that mintenn out, we would be changing the funcl ion. We 01 ) 11 10 00 could include Ihe minterm itself. yielding I ~ x + 0 0 1 0 0 x ' y , z. But that'S not minimized, because the ori oinal equation included mi nlerm xy , z. and xy ' z 0+ 1( 1 1 1 1 x ' y ' z ~ (x+x ' )y ' z ~ y ' z. On the K-map. we x draw a circle around that top 1 that also includes the Figure 6.9 Circling a 1 twice. 1 in the cell below. The minimized function is thus I ~ x + y ' z. It 's OK to include a 1 twice-that doe n't change the function. Think about it: the funcLion doesn't change if we duplicate a minlerm (don 't forgel. a ~ a + a)_and duplicating a minterm can allow for more optimization. In other words: x ' y ' z + xy ' z ' + xy ' z + xyz + xyz ' x ' y ' Z + xy ' z + xy ' Z ' + xy ' z + xy z + xy z ' (x ' y ' z + xy 'z) + (xy ' z ' + xy ' z + xyz + xyz') (y ' Z) + (X) We duplicated a minteml. which resulted in betler optimization. On the other hand. there's no reason to circle 1s more than once if the 1 are alread included in a minimi zed term. For example. the K-map for the equation:
J
Draw the fewest ci,des possible. 10 mi"i",i:.e ,he
"umber of tenus.
Figure 6.8 shows the K-map for that equation's function. Circling the four adjacenl Is yields the min imized eq uati on. H - z.
x ' y ' z + xy ' z ' + xy ' z + xyz + xyz '
yz
~
~
H - x ' y'z + x'yz + xy ' z + xyz
~
H
301
~
x ' y ' z ' + x'y ' z + xy ' z + xyz
appears in Figure 6. 10. There's no reason to draw the yz circle resulting in the term y ' z. The other IWO 00 10 circles cover all the I s. meaning Ihose two circles' xz terms cause the equation to output 1 for all the o required input combinations. The th ird circle JUSt o results in an extra term without changing the function. Thus. we not only wanl 10 draw the large t circles possible to cover all the 1s. but we also want to draw the f ewest circles. We mentioned earlier thot Ihe left and right ides of a K- map are adja nt. Thus. we can draw circles that wrap around the sides of a K-map. For example. the K-map for th equation: K - xy'z' + yz' + ' y'z
302
Optimizations and Tradeoffs 6.2 Combinational Logic Optimizations and Tradeoffs
appears in Figure 6. 11. The IWO cells in the .co r~e rs with Is are adjacenL since the left and nght SIdes of the map are adjacenl. and t h~ rc f~ re we can dra ~v one circle that covers both . resulllllg III the term x z .
K
00
6. I I is an example of such a term .
. A circle in a Lhree- vm'iabl e K-map mu sL Involve one cell. two adjacenL cell s, four adj acenL ce lls. or eight adjacent ce ll s. A circle can lIot involve only Lhree . fi ve. six. or seven cells. The reason IS because the circle l11 ust represent algebraic lra nsform 3t1,OnS lilat elim in ate variables appearin g in all possibl e
combi nations. since Lhose variables can be facLored ouL and Lhen combined La a 1. Th ree adjacenL cells don'L have all combinations of LwO variabl es-one combi nation is mi ssing. Thu s, the circle in Figure 6. 12 would not be va lid. since iL corresponds La xy , z ' + xy , z + xy z. which doesn'L simplify dow n
01
0
Sometimes a I does not have any adjacent Is. In that case. we simply circle the single 1. res l~lttn ~ 111 a term that is a mi ntcfm. The tcrm x ' y ' z 111 Fi gure
0
11
10
0
0
xz:
0
Figure 6.11 Sides are adjacenl.
00
01
11
10
0
0
0
0
0
1
1
1
1
0
Figu re 6.12 Invalid circle.
to one (crm. To cover th at functi on. we would need
F = w' xy ' z ' + w' xy ' z + w' x ' yz + w' xyz +wxyz+,tX ' Yz
Agai n, notice that every adjacent pair of cells differs by exactly one variable. The left and right sides of the map are considered adjacenL, and the top and bottom edges of the map are also adjacent- note that the left and right cells differ by only one variable, as do the top and bOLlom cell s. We COver the I s in the map with the two circles shown in Figure 6. 14, resulting in the terms w' xy ' and y z, so the minimized eq uation is F w' xy ' + y z. A circle covering eight adjacent cells would represent all combinalions of three variables so G yz algebraic manipu lati on would eliminate all three'variwx 00 01 11 10 ables and yield one tenn. For example, the function 00 in Figure 6. 15 simplifies to a single lenn, z, as 0 /, 0 shown.
r;.,
yz
LwO circles. one around the lefL pair of 1s, the oLher around the righL pair. . If all the cells in a K-map have Is. I1ke for the E yz funcLion E in Figure 6. 13. Lhen we would have eighL adj acent 1s. We can draw a circle around those elghL o cell s. Since thaL circle represents the ORing of all possible combi naLions of the funcLion's Lhree vanabies. and ince obviously one of Lhose combillallons wi ll be true for any combinaLi on of inpuL values, Lhe Fig ure 6.13 Four adjacent 1s. . equ ation would min im ize LOJUSL E = 1. Whenever in doubLas La whether a circle is val1d, j usL re member LhaL the circle represents a shorthand fo r algebraic LransfonnaLions th aL combine Lerms LO e l i mi n~aLe a vari able. A circle mUSLrepresenL a seLof F yz Lenns for which all possible combinaLions of some w x 00 01 11 10 variables appear while other vari ab les are idenLi cal in all Lenns. The changing variables can be elimin aLed. 0 0 1 0 00 resulLing in a single Lerm wi Lhout those vari ables. Four- Va ria ble K-Maps K-maps are also usefu l for mini mizing fou r-variable Boolean fun ctions. Figure 6. 14 shows a four-variable K-map for the follow ing equaLion:
303
x'y'z
yz
01
1
1
1
0
11
0
0
1
0
10
0
0
1
0
yz "'--' Figure 6.14 Four-variable K-ntnp.
Legal-sized circles in a four-variable K-map are one, two, four, eight, or sixteen adjacent cells. Circling all sixteen cells yields a function that equals 1. Larger K-Maps K-maps for fi ve and six variables have been proposed, but are rather cumbersome to use effecti vely. Thus, we do not discuss them further. K-maps for two variables also exi st, as shown in Figure 6. 16. However, they aren't particularl y useful , because two-variable functions are very easy to minimi ze algebraically. Using a K-Map Given any Boolean fun ction of three or fo ur variables, the foll owing method summari zes how to use a K-map to minimize the function:
01
0
1
1
11
0
1
1
0
10
0
1\1
1
0
0
,,?
Figure 6.15 Eight adjacent ceUs.
Figure 6.16 Two-variable K-map.
L COl/ vert the fun ction's equation into sum-of-minternls fonn. 2, Place a 1 in the appropriate K-map cell for each mintenn. 3. Co ver all the 1s by drawi ng the 1I1il1i1l1UIII number of largest circle every 1 is included at least once. and write the corresponding tenn.
uch that
4, OR all the resulting tenns to create the minimized fu nction. The first step. converting to sum-of-'ninternls fonn. can be done algebraically. as was done in Chapter 2. Alternatively. many people fi nd it easier to combine steps I and ~ . by converting the function's equation 10 sum-of-products fonn (where each tenn is not necessarily a mintenn), and then filling in the Is on the K-map corresponding to each tenn. For example. consider the fo ur-variable function:
F=
w' xz + yz + w'Xy'l '
The term \< ' xz corresponds to the two lightl haded cdl in Figure 6. 17. so \\0 put Is in tho e cells. The tenn y l corre ponds to the entire dark- haded c lumn in the figure. The lenn w' xy , z ' corresponds to the single unshaded cell shown on the left with a 1.
30"'
Optimizations and TradeoHs Min imi zatio n wo uld proceed by coveri ng Ihe Is wilh ci rcl es a nd ~Rin g allihe lerms. The funclion in Fig ure 6.1 7 is identical 10 Ihe function in Fig ure 6. 14. for w hich we oblained the minimized equation: F : w ' xy ' + yz.
6.2 Combinational Logic Optimizations and Tradeoffs F yz wx
00
01
1t
10
00
0
1\0\
1
0
w'xz
yz
~~
t
1
1
0
tt
0
0
r
0
to
0
0
1
0
EXAMPLE 6.5 Two -level logic size optimization us ing
305
left, yielding the lerm a ' bc. Alternatively, we could have drawn a c ircle that inc luded the 1 above, yielding the term a' c d' , resulting in the minimized equation:
H:
b ' d ' + a ' cd ' + a ' bd
NOI o nl y does th ai equal ion represe nt the same fun ction as the previo u equatio n, that equation wou ld also require the same num ber or trans istors as the previo u equation . Thus, we see th ai Ihere may be mUltiple minimized equations that are equally good.
a three-variable K-map Minimi ze the following equation: a + a ' b ' e ' + b* (e ' + be ' )
G :
Figure 6.17
IV '
Don't Care Input Combinations
xz and yz terms.
Lel"s begin by convening th e equation to sum-of-products:
G:
a + a ' b'e' + be ' + be '
\Ve place 1s in a three-vari able K-map corresponding to each teml. as in Figure 6. 18. The bottom row corresponds
G be a
to the term a. the top left cell to term a ' b ' e ' . and the right colu mn to the teml be ' (whi ch appears (wi ce in the
eq uati on). We then cover the Is using the two circles shown in ~Ring lh t.! resulting tenns yields the minimized equation G = a + c '.
Figure 6.19.
EXAMPLE 6.6 Two-leve l logic size opti mization usi ng
00
01
It
0
t
0
0
1
1
1
t
t
t
10
Figure 6.18 Terms on the K-map.
be
G
a four-variable K-map
o
Min imi ze the following equation :
H:
a 'b' (ed ' + c ' d ' ) + ab ' e ' d ' + ab ' ed ' + a ' bd + a ' bcd '
Converting to sum-of-prod ucts form yields: H :
Figure 6.19 A cover.
a'b'cd' + a ' b ' c 'd ' + ab ' c ' d' + a b' cd ' + a' bd + a ' bcd '
We fi ll in the Is corres ponding to each term, resulting in H cd the K-map show n in Figure 6.20. The term a ' bd correab spo nds to the two cells whose Is are in italics. All the b'd'
other (enns are minterms and thus correspond to one cel l. We cover the Is using circles as shown. One "circle"
00
covers the fo ur comers, resultin g in the tern' b ' d ' . That
01
a'be
11
a'bd
ci rcle may look strange, but remember Lhal the top and
botto m cells are adj ace nt , and the left and ri ght cells arc adjace nl. Another circle results in the term a ' bd, and a thi rd circle in th e term a ' be. The minimized two- level
10
equation is thererore:
H - b 'd ' + a ' bc + a'bd Ole the bolded 1 in Fi gure 6.20. We covered that 1 by d raw ing a c ircle th at included Ihe 1 10 Ihe
-
-
-
~ --------- --
Figure 6.20 K-mop exa mple.
Sometimes, we are g uaranteed that cert ai n input combinatio ns of a Boolean functi on can never appear. For those combinations, we don ' l care whether the functi o n outputs a 1 or a 0, because the function will never ac tua ll y ee th ose input values-the o utput fo r those inputs just does n' l maHer. As an intuitive example. if you became ruler of the world_ would you li ve in a paJace or a castle? Your answer (the output) doesn't matte r. because the inpul (yo u becoming rul er of the world) simply won't happen . Thus, when given a don't care input combination, we can choose whether to o utput a 1 or a 0 for each inpul combination, such that we obtain the best minimization pos ible. We can choose whatever outpul yields the best minimization, becau e the output for those don' t care input combinati ons doesn' l matter, as those combinations simply wo n'l happen. Algebraically, we can use don 't care terms by introduc ing them into an equation durin g a lgebraic minimization 10 create the opportuni ty to combine terms to eliminate a variable. As a s imple example, cons ider a function F : xy ' l ' . for which we are for some reason guaranteed that the ternlS x ' y , z ' and xy , z can each never evaluate to l. We no tice thai adding the firsl don'l care lerm to the equation would result in xy , z' + x ' y ' z' (x + x ' ly ' l ' : y ' z '. Thus, introducing thai don't care term x ' y ' z ' into the equation yie lds a minimizatio n benefit. However. introducing the second do n' t care term does not yield such a benefit, so we choose not to introduce that term. In a K-map, don 'I care input combinations can be easily handled by placing an X in a K-map for each don't care mintenn. We don'l halle to cover the F yz 'fz' Xs with circles. bUI we call cover some X if that 00 01 tt to he lps us draw bigger circles while covering the 1s. 0 X 0 0 0 mean ing fewer literals will appear in the term corresponding to the c ircle. For the above example, we t X 1 0 0 would draw the K-map shown in Figure 6.21 , having one 1 corres po nding to xy ' z '. when the func ti on Figure 6.21 Map with don't cares. lilliS/ o utpu l l, and havi ng IWO XS corresponding to x ' Y , z ' and xy , l, when the function ilia), OUtpUI 1 F yz 'fz' unneeded if thai helps us minim ize the function. Drawing a s ing le ci rcl e results in the minimized equation F : 11 10 00 01 y , l ' . (Be careful in Ihis discussion not to confuse X 0 0 0 0 the uppercase X. corresponding to a don't care. with the lowercase x. corresponding to a variable.) 1 1 X 0 0 Remember, don't cares don 'I ha re to be cove red . The cover in Figure 6.22 gives an example of a Figure 6.22 Wasteful u>e of X
306
Optimizations and Tradeoffs 6.2 Combinational Logic Optimizations and Tradeoffs wastefu l use of don't ca res. The circle covering the botlom X. yie lding term xy ' , is not needed. That tenn is not wro ng, because we don ' t care whether the output is I or 0 when xy ' eva lu ates to 1. But. that term wo uld result in a larger c ircuit. because the resulting equation is F - y ' z ' + xy ' . Since we do n' t care, why not make the output 0 when xy ' Z is I . and thus obtai n a smaller circuit ?
EXAMPLE 6.7 Two-level logic size minimization with don't cares on a K-map MinimilC the fo llow ing
cqu~ l io n ;
F - a ' be ' + ab c ' + a ' b ' e
(Wo
o
Is on the right with- a bigger circle. The res uhing mini-
mized equation is F
~
o
a ' e + b.
Wilhom don't cares. the eq uation would ha ve miniFigure 6.23 Using do n't cares. mized to F = a ' b . c + be ' , Ass uming two transistors per g~lIc input and ignoring invc ncrs, the equation mini, mized wit hou t don't cares would require (3+2+2) * 2 ;;;; 14 Inlllsistors (3 gate IIlputs for the first AND gate, 1: fo r th e second AND gate, and 2 for the OR gale, times 2 transistors per gate input), In contrast. the eq uation minimized with don't cares requires on ly (2 + 0 + 2)*2 ;;;; 8 lransislOrs.
EXAMPLE 6.8
Don't care input combinations in a sliding switch example Consider a sliding switch. shown in Figure 6,2~. lhat can be in one of five positions. with Ihree outputs x. Y, an d Z indicati ng the position in bi nary. So xy Z can lake on the
values of 001. 010 . al l. IDa , and 10 1. The other values for xy Z are nOt possible, namely. the values 000. 11 0. and III (or x ' y ' z '. xyZ '. and xYZ ). We wish to
3 2,3,4, detector
G
Figure 6.24 Slidi ng switch example.
dCiiign combin:uional logic. with x. y , and Z inpulS, that outputs 1 if the switch is in position 2, 3, or 4, correspondin g to xy z vlI lues
of 010 . 011. or 100. A Boolean equntion describing the de'ired logic is: G x ' YZ ' + x' y Z + 2
,(y , z ' . We can minimize the eq uation using a K-map, a, shown in Figure 6.25. The mi nImi/.ed equati on that rC'I ulis is: G .. xy ' l ' + x ' y.
However, if we con~ ider dan', carc~. we can obtain a Simpler minimi7cd cqUlllion, In part ic ul ar. we "'now th'H nOne of the thrce
G yz
0
00
01
11
10
0
0
1
1
0
0
x'y xy'z'
1
1\.1/ '11
G yz
y
o
Although we ended up covering all the Xs in this example.
give n that tefms a ' be and abc are don't cares. Intu itive ly, th ose don', cares mean that be can ~c,cr be 11. \Ve begin by c rc~i1in g the 3·variable K-l11ap in Figure F be a'e 6.23. We place ls in the th ree cells for the functi on's mi n00 01 lenllS. \Ve then place Xs in the two cells for the don't cares. We c;.m cover th e upper- left 1 using a circle that includes an o o X. Likewise. includin2 the two Xs in a circle cove rs the
mimerms x ' Y" l ' . xY l " and xy l can ever be true, because. the switch can on ly be in one of the above-stated five positions. So it doesn't mailer whether we omput a 1 or a 0 for those three other mi nterms. We can include th ese don~t ca,rc input comb inations as Xs on the K-map. as shown III Figure 6.26. When coveri ng the Is in the top fi ght. we can now draw a large r circle. res ultin g in the term y. When covering the 1 at the bottom left, we can draw a large r circl e also, result ing in th e term z'.
307
Figure 6.25 Without d n' t cares.
recall ,that we do not have 10 cover the XS-we onl y use them If they help us COver th e Is wi th laroer ci rcles. The minimized eq ual ion that res ults is: G "" yO + z ' .
Figure 6.26 With don' t cares.
That minimized eq uat ion lIsing don' t cares looks a lot different than the minimized equation without don' t cares. But keep in mind the circu it still works the same. For example. if the witch is in position 1. then xyz will be 001. so G - y + z' evaluates to O. as desired. D OII'I ca res II/IISI be IIsed w;lh call/;Oll. We must balance the criteri a of size with other criteria, like reli able, error-tolerant, and safe circui ts. when deciding whether to use don ' t cares. We must as k ourselves-is it ever possible that the don ' t care input combination II/;ghl occur, even if in an error situation? And if it ;s possible. then do we really not care at all what Our circu it outputs in that situation? Often. we really do care. and will want to ensure Our circuit outputs a panicular value. For example, in the sliding witch example above, perhaps temporary values could appear at the xy z outputs as the swi tch is being moved. We might therefore want to ensure we o utput 0 for the don ' t care values. Several common situations lead to don't cares. Sometimes don't cares come from physical limits on the inputs-a switch can' t be in two positions at once. for example. If yo u've read Chapter 3, then you may reali ze that another common si tuation in whicb don't cares may appear is in controller design, when a controller uses a state register that can represent more states than the controller requires. For exan1ple. a controller with 17 tates may use a 5-bit state register, meaning that 15 of the 32 possible states of the state register would be unutilized. Those 15 states could be treated as don ' t cares (although to be safe. we might actually want to transition back to an initial tate if we ever enter one of those 15 unused states due to noise or some other error). If you've read Chapter 5. then you may realize that another common situation where don ' t cares arise i- in a controller controlling a datapath. If we aren't readi ng or writing to a particular memory or register file in a given state, then we don' t care what address appears at the memory or register file during that state. Likewise. if a mux feed into a register and we aren ' t loading the register in a given state. then we rea lly don' t care which mux data input passes through the mux duri.ng that state. If we aren ' t going to load the output of an ALU into a register in a given statcthen we really don ' t care what function the AL computes during that state.
Automating Two-Level Logic Size Optimization Visua l sc of K-Maps Is Rather Limited Although the visual K-map method is helpful in two-level optimization of three- and four-variable functions. the visual method is unmanageable for functions \\ ith man> more
308
6.2 Combinational Logic Optimizations and Tradeoffs
Optimizations and Tradeoffs variables. One probl em is that we can' t effecti ve ly vis ualize ~naps beyond 5 or 6 variables. Another problem is that humans make mistakes. and mi ght a~cldcntaHy not draw lhe biggest circl e possible on a K-map. Furthermore. the order 111 whic h a deSi gner beginS coveri~;g Is ma y resul t in a function that has more terlm than would have been obtamed using a diffe rent o rder. For example. consider the functi on shown 111 the K-map of Figure 6. 27(a). Starting fro m the left. a designer might first draw the circle Yielding the term y ' Z '. lhe n the circ le yielding x · Y ' . the n the ci rcle yielding y z . and finaH y tlhe wcie yielding xy . for a towl of four terlns. The K-map in :i~ure 6.27(~) shows an a tematlve cover. After drawing the circ le y,eldll1g the le rm y z . the deSigner draws the Circle yielding x · z . and the n the circle yield ing xy. The alte rnati ve cover uses on ly three terms instead of fou r. yz
yz
0
00
01
11
10
1
1
1
0
01
11
10
1
1
1
0
1
1
10
1
1
(b )
(a)
1
00 0
1
y'Z:
1
\\ 0 I x'y'
I
yz
1 I
xy
y'Z:
I x'z
I xy
Figure 6.27 A cover is nOI necessaril y oplimal : (a) a four-Ierm cover. and (b) a Ihree-Ierm cover of the same funclion.
Concepts Underlying Auto ma ted 1\,'o-Level Size Optimization . . . . Because of the above-me ntioned problems, Iwo- Ievelloglc Size optimi zation IS done pnma· rily u ing automated compuler-based tools executing heuristic or exact algorilhms. A heuristic is a problem solving melhod lhat IIslial/y yield a good solull on. which IS Ide~lIy clo e to the oplimal. but IIOt IIecessarily optimal. An exact algo flthm . or Just algomhm. ISa problem olving method lhat yields the optimal soluti on. An .optimatsollltion i as good or better than any other possible solution. wilh respect to the cri teria of Inte rest to us. We firs t define some concepts underlying heuristic and exact algorithms for two· leve l logic ize optimization . We wi ll illustrate lho e concepts graphicall y on K-map . but uch illustration i onl y intended to provide the reader with a n intuition of the conceptsautoma ted tools do not u e K-maps. Recall that a functio n can be written as a um-of-m interm equation. A minterm is a product te rm that includes all the function' variable exactl y once, in ei lher true or com· plemented form . The on-set of a function is the set of minterms that define when the fun ction should F ':y'z yz evaluate to 1 (i.e .. when the functi on is '·on"). For 00 the function in Figure 6.28. the on-set i ~: I x . y' Z. /,y Z, xy Z ' I. The off-set of a functi on is all the o remaining minterms. For the functio n in Figure o 6 .28. the off- et is: I x' y , z ' . x ' y z " x' y Z. I Y , z ' . Jl.y . 1 J. V,jng compact mintcrm' rep re~e n Figure 6.28 Impliennl'. tallon (
309
An implicant is a pd · 'Ibles b . ro uct term that may Include fewe r than all the function 's vari, , ut IS a term that onl I . '. y eva uales to 1 If the function should evaluate lO I -in other Wa rd s, an Implicant of a f . . I unction IS a l.erm that should evaluale to 1 for a panicular set of . bl varia e va ues onl y if at I f ' , . . bl east one 0 the funcuon son-set min terms evaluales to 1 for h lose varia e values F l ' . I' . or examp e, the function F = x ' y ' Z + xyz' + xyz has four ' . . . IInp Icants: X ' Y ' z xy z ' '1 ' , xyz , and xy. Graphically, an Implicanlls any legal [but not necessan y the bi ggest possible) circle on a K-map, as shown in Figure 6.28. All minterms are obViously implicants, but not all implicants are minterms . We ~ay that the implicant xy covers minterms xy z' and xy z of function F. Graphically, an Implicant's circl e enCirc . Ies the i ' . s of the covered mlnlerms. Intuitively, we know that we can replace the Covered minterms by the covering implicant and still obtain the same function. In other words, we can replace xy z '+ xy z by xy. A sel of implicants that covers the on-set of a func ti on (and covers no other min terms) is known as a caver of the function. ~or.the above function. one funclion cover is x ' y' z + xy z + xy z ' : another cover IS X Y z + xy; yet another cover is x ' y ' z + xy z + xyz'+ xy. RemOVing a variable from a term is known as expanding the term. which is the same a ex panding the size of a circle On a K-map. For example, for the function in Figure 6.28, ex panding the term xy z to the term xy (by eliminating z) results in an implicant of the func ti on: Expanding the term xy Z' to xy also results in an implicant (the same one). But. ex pandl,n g xyz to x z (by eliminating y) doe not resu1l in an implicant-xz covers mlnternl xy z , which IS not In the funclion 's on-set. A prime implicant of a function is an implicant with the property that if any variable were elimmated from the implicant, the result would be a lerm coveriJlo a minterm not in the functio n's on-set. Graphically. a prime implicant corresponds to ;ircles that are the largest possible-enlarging the circie further would result in coverin!! as. which chanoes the function. In F~g~re 6.28, X • Y . z and xy are prime implicants. Re;;'O\
=
An essential prime implica"t is a prime implicant lhal is the mIl)' prime intplic3Dt that covers a particular minteml in the fu n tion' on-set. Graphicn!I). an e - ntin! prime IIllp! lcant I the on ly circle (the largest PO' ible. f course. in e the circle rou ' represent II prime Implicant) that covers a parti ular 1. In Figure 6.2 . x· ' l is IlIl e ' ntial prime implicant. II i xy . because each i the only prime impli Wit vering n pani -ular 1. no nessent ial pri me implicunt is a prime implicant \\ hose ,-o\ ered ruintenns are nJso covered by one r more other prime implicllnts. Fig.ure . ~9 shO\,s II different function thnt has four prime implicant. but only two of which are e s ntial . ' 'is an e,' ntia! prime implicant because it is th' only prime impJi ant that o'crs mint-eml \ '_ ':'. _
OptimIZations and Tradeoffs
310
6.2 Combinational Logic Optimizations and Tradeoffs
j" nn c.." ential prilllt! illlplicani bt!cnllsc it is the on ly prime impiicarll that CO\'\!f" minlenn xY Z ' . y' z i~ a
nones ... elllial prime implicant because bo th of ItS
y'z
00
co \cred minh::rm", are cOH~rcd by other implicants
10
o
(lho;e other prime implicants mayor may not be essential prime implicants). Likewise. Xl i
We'lI demonstrate the ap proach for automated two-level logic size optimization with the following exam ple.
not essential
G yz
not
C'!-~entinl. The importance of essentia l prime illlpli-
C3nt" i~ i.l~ roll ow~: we know that we must include all e~~c nti n l prime impiicanls in n function' s cover. 0111-
x'y' essential
xz
xy
not essential
essential
en' i ~e there would be .sO l11e minlcrms that could not Figure 6.29 Essential prime be cove red . We mayor may nOl need 10 include nonimpl icnn t<;, e"emia l primc implicams 10 completely cover the function. but we must include all essentia l prime implicant <. Given the nOlion of prime implicants and essential prime implicants. a simple approach for two-level logic optimization is given in Table 6.1. TABLE 6.1 Approach for automated two-level logic size optimization.
EXAM PLE 6.9 Two-level logic size optimization with the approach of Table 6.1, illustrated on a K-map Figure 6,30 shows a K-map for the function from Fioure 6.27, for which we saw thai different covers yielded°dif_ ferent numbers of terms. The first step is to determine all prime impJicams, shown in the top pan of the fi gure. For each 1. \~e draw every possible circle involving adjacent Is. ensunng that each circle is the largest possible. The second step is to add essential prime implicants to the function's cover. Notice that the 1 corresponding to mi11lerm x ' y Z (the top righl 1) is covered only by one prime impl icant. namely. x ' z. Th~s, ~vc know we' ll need to usc that prime implicant. so we II Include prime implicant x ' Z in the cover. Also
notice that the 1 corresponding to mi11lerm xy z · (the bollom right 1) is on ly covered by one prime implicant. namely,
tep
Description
Deremlifle prime impliclIIw
For e\cry mintcml in the fun ction'", on-set. maximally expand th e tenn (meaning elim inatc literal'i from the (eml) such that the term still onl y covers minterms in the function'~ on-se t (like drawing the biggest circle possible around each 1 in a K·m ap), Repeat for each minterm . If don 't cares ex ist, u ~e them to maximally ex pand mintenn\ into prime implicants (like u:-. ing X's 10 crea te the biggest circles po~')ible for a given I in a K-map),
so we' ll include thai prime implicant in the cover 100. We mark all the 1s covered by these essential prime impiicants. noted by italicized Is in the fi2ure. The last step is 10 cover the remaining Is wi~ the fewest number of prime implicant, There is only one 1 uncovered. and that 1 is covered by two prime implicants, \Ve can choose ei ther prime implicant for th e cover-Iet's choose y Z Thu s, the final cover is: Xl
I
Find any minterms covered by only one prime implicant ( i.e.. by an essential prime implic::m t), Add tho e prime implicanlS 10 the cove r, and mark the minterms co\ered b) tho\c implicanlS as already co vered,
Cm"er remoinint: 11I/ntenllf hil" Co\cr the remaining minterms usi ng the minimal number of remaining prime noneuellliul prune II11pliclllll5
impiicants.
The fir;t 1\\0 "eps are exact. The last tep is a bit tricky. How do we choose which pnme IInplicants to u'e to cover the rema ining minterm5? Reca ll the example of Figure 6.27. in v, hich the cover in Figure 6.27(a) used two prime implicants to cover the two Is that would be left after adding cs;ential prime implicant'. while the cover in Figure 6.27(b) u,ed on ly one prime implicant to cover tho,c remaining two Is . When there are on ly tv,o pO>'ibilitie,. we ca n try each po."ibili ty and pi k the one with fewe t prime implicant; In the fi nal cover. But what if there were million, . or billion\. of possibilities? We may not h:lve enough compute time to try al l tho;e po'~ibi liti es. For large functions v,lth hundred, of mintcrm, and thou,and, of prime Impl lcnnt '. there moy indeed be million, of po;"ble cover, to con;idcr III thc la\l ; tep. If an npproach tnc, :111 ,uch po"ibilllie,. the :Ipproach i, an e~act :ilgorithm . If an approach )U,t tne, a few ,uch po"ibllitie,. the overall two-level ,i/e optimi1.lltion approach may he a hcumtlc (un lc" the approach can guara ntee that the Ignored po sibil1I1C, couldn't IX""bly he pan of an optimal 'olution)
~ #~-
-
-
. _- -
yz
0
':z 1,] 10
00
01
1
1
1
0
1\0
0
v;-
(a )
1
t
y'z' ':y' yz
,
x'z
(b)
,
I
y'z' ':y' yz
(e)
o
I ,
I = x ' Z + xz' + y ' Z · Add euefllial prim€' imp/iclllII_\ to rhe fitllerion's cm'er
311
This example uses a K-map merely to illustr:lte 10 the reader the sleps occurring wilhin an automated tool-such :l 1001 does 1/0 1 use K-maps intemalJy, but rather other means of representing the tenns of a function.
o
y'z'
Figure 6.30 liIuSlrntion of [\\0Ie'el optimization: (a) alJ prime implic3I11S. (b) including e>.><:ntial prime implicartlS in the C'O\er, tel co\ ering remainmg :s..
Automated 1\"o-Level Logic Size Optimization Using the Quine-McCluskey Method The most well-known. and in fact the original. approach for automated t\\ o-Ie,e1 logic size opti mization is the Quine-McCluskey method. sometimes ailed the tabular method. The first step of thi s method finds all prime implicant . The step stan:. \\ ith thl.' function 's minterms- if we are minimizing a three-variable fun tion. then \\e mi2ht 'all these three-variable terms. To find all the prime impli ants. the method first CO~l1pare> ea.:h three-variable teml with every other three-variable teml. and if t\\ O tenus :Ire found that diffcr by onl) one variable. the method adds a new tenn l\\ ithout thl.' dift'ering ..anablel t a new set of two-variable tenm. For example. xy l ' and y: differ b, one ,mabl :. rc. ulting in a new tenll xy being added to the t\\o-.. ariable that differ by only one variable. ~sulting in a :et of one-'mable tel11b. n ';lJ1aN t I11lS can then be compared for teml> that dilTer b) one' ariable. but tf 'u 'h t'1111' .Ire fc'l1nJ.
J 12
Optimizations and Tradeoffs
6.2 Combin ationa l Log ic Optimizations and Tradeoffs
then Ihe funct ion eva lumes si mply to 1. Actuall y. nOI all terms in a sct need 10 be compared-only tho,c terms whose Ililmber of uncompiemcillcd literals differs by one need 10 be compared. For example. x· y z ' and xy z need not be compared. because the number of uncomplemented lileral differs by two. not one. and thus can't be simplified to a new tenn by eliminating a vari able. If at any time in Ihi, step a term can not be combined wi th any olher term. we mark that term as a prime implicant. Thus. after this step, all marked temlS represent all prime implicants. The method thus provides an approach for fi nding prime implicants. more efficient than just maxi mally expanding every term. The second step is 10 add all Ihe essenti al prime implicants to the cover, and to mark as "covered" all minlenns covered by Ihose pri me impl icants. The fina l step is 10 cover all remai ning uncovered mintemls by select ing the fewest remaining prime implicants to cover Ihose mi nterms. Trying all the pOSS ibi lities results in a version of the Quine-McCluskey melhod that is an exact algorithm . Trying just a subset may result in a heuri stic. Methods That Enumerate All Minterms or Comput e All Prime Implicants May Be Inefficient The Quine-McCluskey melhod works reasonably for functions wilh perhaps tens of variables. However. for large r funclion s. just listing all the mintemls could result in a huge amoun t of data. A fu nct ion of 10 vari able could have up to 2 10 mintemls-that 's 1024 mintemls. wh ich is fairly rea onable. But a funclio n of 32 variables could have up to 232 mintemls. or up to about fo ur bi lli on mintemls. Represeilling Ihose mintemls in a table requi res prohibitive computer memory. And comparing those minterms Wilh Olher mintemlS could require on Ihe order of (four billi on)2 computat ions. or quadrillions of computalions (a quad rillion is a Ihousand time a trillion). Even a co mputer performing 10 billion computations per second wou ld require 100.000 seconds to perform all those computation,. or 27 hours. And for 64 variables, Ihe numbers go up to 26-1 possible mintemls. or quadrillions of mintemls. and quadrillions2 of computalions. which could require a month of computation . Functions with 100 input . which are not that uncommon. would require an absurd amount of memory, and many year of computa· tions. Even computing all prime implicants. without first Ii ling all minterms. is computationally prohibiti ve for many modem-sized function s. Iterati ve Heuristic for Two-Level Logic Size Optimization Becau e enumerating all minterm of a functi on. or even ju>t all prime implicant . is prohibitive in temlS of computer memory and computation lime for func tions with many variables. mo t automated tools u e methods that in stead just iteralively transform the original function's equation. in an attempt 10 fi nd improvement 10 the equation . Iterative improvement means repeatedly maki ng small change. to an exisling solution umil we decide 10 , top. perhap; because we can't find a better ,olution, or perhaps beeau e the tool has run for en ugh time. As an exampl e of making sma ll changes 10 an ex isting solution. con"der the equation: F - abcdefgh + abcde gh ' +
j~ l mno p
Clearly. we can reduce th " equation 'imply by omh,nlng the Iirst two term and rcmov lIlg ' anable h. re\ultlllg III F - abcde f 9 + i ~ 1mnop. However, enumerating the mllltcrm" J S reqUired III the carlier-de,cn1x:d ,ile optllnll311on methods. would have
313
in roughly 1000 m'III Ierms and Ihen millions . . . of computations to find the pnme IInp Icants-but such enumeralion and computation are obviously not necessary W minimize thiS equalion . '. . lools therefore don . t try to enumerate aU the . Modem automated logic opt'ImlzaUon millterms for fun ~ li o ns wi th many variables. Instead, those lools start with a given sumof-products eq uation of. the.func t'lon, I'k " l ethe descnpuon for F above. Those 1001 then try to transform the equation little by little into a better equation. meaning an equation with fewer terms and/or fewer lilerals. Those tools repeal, or iterote. until they find no further Improvement or until some maximum time allocated for Ihe 1001'S execution has expired_ . Heun stlcs for such two-level logic optimization III modern tools can be qu ite complex. However a I yz simple heuri stic Ihat is reasonably effective u~es 10 01 11 00 repeated application of Ihe ex pand operation. The o o expalld operation means to remove a literal from a (a) teml and Ihen check whether the new teml is legal. o o Removi ng a literal makes Ihat term cover more ~ntemlS, like drawing a bigger circle on a K-mapr(z xyz Ihus the name ·'expand." For example. consider the yz funclion F = x ' z + xy' z + xyz . We might )(z 10 lry to ex pand the teml x' z by removing x '. or -by o o removing z. Note Ihat expanding a teml reduces the (b ) ~-t::~=:::i-4- )( number of literals-the concept that expanding a o term redllces the number of literals in a teml may xyz take a whi le for you to get used to. Thinkin o of Kr(z map circles may help. as shown in Figure 6.31-1he Figure 6.31 bpan ions of term bigger Ihe circle. the fewer Ihe resulling literal . An , Z in the fuoctioo F = x' z expansion is legal if the new teml covers only minxy ' z + xyz: (a) Ie",,!. (bl 001 terms in Ihe function's on-set. or equivalently. does legal (because the ex~ded tenn cmer.; Os). lIot cover a mimeml in Ihe function's off-set-in other words, an expansion i legal if the new teml i still an implicant of Ihe function. Figure 6.3 1(a) shows that expanding term x' : to z for Ihe given funclion is legal. as Ihe expanded teml covers only 1 . whereas expanding 'z to x ' is not legal . as Ihe expanded teml covers at least one O. Lf an e: pansion is legal. "e replace Ihe ongillal tenn by Ihe expanded teml. and we look for and ~mo\'" an,· OIher lerm cOI'ered by tile expallded term . tn Figure 6.31 (a).lhe expanded term z co\e~ terms xy , z and xy z. so both Ihose latter tenns can be removed. I ote that we illustrated Ihe expand operalion on a K-map merel) to aid in undertandi ng the intuition of Ihe operation-K-maps are nowhere to be found in heuri -[j I'\(}level logic size minimi zation tools. As anolher example. for ti,e earlier inuodu ed function:
.resulted r
~
F - ab cdefgh + abcdefg h '+ j lmnop We might start b trying to expand the fir.;t tenl1. a bcde f gh _ ne "'pan i< n of th t t ml b bc de fgh (i.e" we fCmoved the literal a ). Ho\\e\er. thaI term \ __ the teon a 'b c de fgh. "hi h coven.mintenlls th31 are not in the fun tion' on-: t. $0 thaI ' pansion i~ not legal. We might try other e. pansions. finding them n t I galt~ '. until \\ e n:
6.2 Combinational Logic Optimiza tions and TradeoHs
OptimIZations and TradeoHs aero" the ~xpan,io ll to abcdefg (i.e .. we removed the literal h ). That term strictly abcdefgh a nd abcdefgh '. both of whi ch are clearl y implicants because they appear in the origimll function. and thus the new tcrm Illu st also be an implicant. Therefore. \\e replacc the fir,t ten11 by the ex panded term :
CO\of'
F = abcdefg4
+ abcdefgh ' + jklmnop
and wc also rcmo\ c the second term. s ince that ten11 is covered by the expanded temJ:
abcdefgh
+ a6edcf~R'
+ jklmnop
abcdefg + jklmnop
Thus. lI;;ing j ust the expand operation. we have improved the equation.
EXAMPLE 6.10
Iterative heUristic two-level logic size optimization us ing expand ~linlmile tht: fo llo\\ ing equation. which was also minimized in Example 6.4. using repeated appli-
cation of the ~\pand oper:lIion:
F
=
xyz + xy z'
+ x 'y 'z '
In other \\ orcl<. the on-,et consist.'> of the mintemls:
+ x 'y 'z
17.6. O. I I.
and so th e off-set consists of the
mlillerm" I~. 3. ~. 51 · Let\ expand the !erms from left to righl. so we ll stan with xy Z. We can try to expand xyz to xy. b that a lega l ex pansion" xy covers minterms xy z ' (mi nterm 6) and xy z (minterm 7). both III the on-,el. Thus. the expansion is legal. so we replace xy Z by xy. yielding the new equation:
F = xyz
+ xyz '
+ x ' y ' z'
+ x 'y ' z
We al,o look for implicants cmered by the new implicant xy. xyz ' is covered by xy . so we ehmillate xy Z ' . yie lding:
F = xy
+
~
x 'y'z ' + x ' y ' z
Let\ continue ll)lng to expand that first lenn. \Ve can try expand ing it from xy to x. The term co\ e" mintcrm' xy ' z ' (minlcrm ~). x y' z (minteml 5). xy z ' (m interm 6). and xyz (minIcnn 7). The ICon X thul; covers mintenns "' and 5. which arc not in the on·set. but instead in the ofT-",1. Thu,. that expan"on i, not legal. We can al,o try expandi ng xy to y, bUI we' ll find again the c'(pa n ~lOn I ~ not legal. We ml ghl then c~n"der the neXl term. x ' y , Z ' . Let"' try expand II to X ' Y , . That teren co\." mlllterm' x ' y' Z ' (mi nterm 0) and x ' y , Z (minterm I). both in the on-sct. so the expan"on 1\ leg"1 We thu, replace the term by the expanded ne: X
F -
xy + x ' y '~ + x ' y'z
We ched. fur other term, co\ered by the expanded tenn. and find lhat X ' Y ' z is covered by /. ' I'. '0 v.e rcmO\c x ' y ' Z. Ica\lOg:
F - xy + x 'y'
~
\\e Cdn try c'pandlng the term x ' y ' further. hut ""ll hnd th.1I both PO' Ible expansions (/ •. or y , ) are not legal Thu~ . the above cquJllon rcprc\Cnl the mUIII1lI/cd equati on. Notice rh..at Ihl' hJppcn, 10 he Ihe '<'Ole re,ull ..1\ v..c oht.uncd when we "H",fllI/cli the ~ame muial cquaflon In I '(.Impll' 6A
315
Even .th ough the heu ristic based on expand happened to generate the optimally minimized equallon In the previous exam ple, there is no g uarantee the results from the heuristic will a lways be op timal. . More advanced heuristi cs utili ze additional operations beyond ju t the expand o peralion. One such operat ion i the reduce operation, which can be thought of as the opposite of expand. The redll ce operation takes a tenn. and tries 10 add a lite ral to the tenn _ checking that the equallon wllh the new tenn still covers the functi o n. Addin o a literal to a tenn i like reduc ing the size of a circle o n a K-map. Adding a literal 10 a te";' reduce the number of mlllten11S covered by the tenn , hence the name redllce. Ano ther operation is irredllndantwhich tries to remove a term entirely, checking that the new equa tio n till covers the funclio n. If so, the rem oved term was "redundant," hence the na me irredlllldalll. Heuristic may lIerate among the expand. red uce. irredund ant. and o ther operati ons. uch as in the following heuristic: Try 10 random expans io n operations. then 5 random reduce operations. then 2 irredundant operations, and then repeat (i terate) the who le sequence until no improvement occurs from o ne iteration to the next. Modem (wo-Ievel ize optimization tools differ largely in their orderi ng of operati ons and their number of iterations. Recall that we said that modem heuristics don't enumerate all of a function' minterms. ye t in the previous example we did enumerate aU the mintenns- actualh'. we "'ere given the mimemls in the initial equation. When we don ' l initially kno" the -rninterms. many advanced methods ex.ist to efficiently represent a functi on ' on- et and off-sel without enumerating the mimenns in those ets. and also 10 quick!) check if a tenn covers lerms in the off-set. Those methods are beyond the cope of the book. and in tead the subject of textbooks on digital design synthes is. But hopefull y you no \\ get the basi idea of heuristic two-level minimizat ion. One of the original 100is Ihat performed automated heuri tics as well as exacI twolevel logic o ptimization was called Espresso . developed at the University of California Berkeley. The algorithms and heuristics in Espresso fomled the basis of man,· modern commerci al logic optimi za tio n tools. -
Multilevel Logic Optimization-Performance and Size Tradeoffs We have thus far discussed two-level logic s ize o ptimization. H we\'er_ in pro rice_ \\e may no t need the speed of two levels of logic. We may be \\ illing 10 use three_ four. o r more levels of logic if those additional levels reduce the amount of required log; _ A ' a s imple example. consider the equ ation :
Fl =
ab + acd + ace
This eq uation CHn ' t be minimized. The resulting two-Ie\e!
ircuil is sh \\n in Figure
6. _(a). , e could. howeva. algebraically manipulate the equation a< follo\\s:
F2 - ab + ac(d + e)
=
a(b ... C(
... e
That equation 'Ill be implemented \\ ith the circuit ,ho\\ n in Figtlre tl.32(bl. Th~1 muluIc\d logic implementation re~ults in fe\\er tmn i$tl)~. Jt th \ l~n~ \"f Ill\. gal delays. li.' illustrated in Figure 6.32(c). The multile\ I nnpl'm nUll >n Ihu, rep >'nt, /rc/{/eojJ compared to the t\\ l>-k\'d implemem,niOll_
316
Optimizations and Tradeoffs EXAM PLE 6.12
a ------------------~
,i::L F'
b ------------~
b
.F2
4
a b
~
FI
:. 5 16 transistors 4 gale-delays
I
(a)
2
3
delay (gale-delays)
F2 = a(b+c(d+e)) (b)
= ab + acd + ace
FI - ab ed + ab eef
The ci rcuit corresponding to this equation is shown in Figure 6.33(a). The circuit req uires 22 tran· sistors and has a de lay of 2 gate-delay.
c
F2
d FI
a
°L F'. F2
~ 15
f
F I = abed + abcef
:. 5
(a)
F2 = abc(d + ef) (b)
I 2 3 4 delay (gale-delays) (c)
Figure 633 Mululevel IOglc to tradeoff pe rformance and ,i7e: (n) two-level circuit . (b) multilevel ClrC"'t IIo lih fewer lran, i' tor<. (c) tradeoff of Size ye"u< delay. umbe" in
U",.
The CIrCUli for that equation" ,hown In Figur< 6.3J(b) The CIrCUli requ ire, only 18 transi but hJ • longer delay of ) gate-delay,. The plot In figure (, 13(c) ,ho,", the sile and
performa nce ror ea( h dc~ l gn
--
- --
----------
5
1
F2
= (a+b)c + (cJ+e)lg
2
3
4
(b)
(e)
6.3 SEQUENTIAL LOGIC OPTIMIZATIONS AND TRADEOFFS In Chapter 3. we described the design of equential logic. namely. of ntrollers. Wben creating the F M. and conveni ng the F M to a tate-register and logi _ we an appl~ some optimizations and trndeoffs.
Lran \ l \ to r COUOl\.
We can algebraically manipulate Ihe equauon by factonng out the ab c term from the t~" term\. aco follow\ F2 • abed + abee f - abe(d • e f )
~
Generally. multileve l logic optimization uses factoring (e.g .. abc a b ( e+d)) to reduce the number of gates. Multilevel logic optimization is probably more commonly u ed today than two-level logic optimization. Multilevel logic optimization i also exten ivel) u ed b~ automatic tools that map circuits to FPGAs. FPGA will be discu ed in Chapter .
-W 10 'El '~
b
c e
15
The other paths through the circuit are only two gate-delay . Thus. if we reduce the size of the logic for the noncritical paths and extend those path to three gale-delay . we would nOl ha'.., extended the overall de lay of the circuit. We focus on the noncritical pans of the equation for FI in Fig= 6.34(a); the equation has its noncritical parts italicized. We can algebraically modify the noncritical parts by factoring out the lenn fg , resulting in the new equation and circuit shown in Figure 6.34{b). One of the modified paths is now also lhree gate-delays. so we now have tv.'o equally long critical paths. both havi ng three gate-delays. The resulting circuit has only 22 transistors rompared to 26 in the original circuit. yet still has the same delay of three gate-delay . as illustrated in Fig= 6.34(c). overall. we've pcrfonned a size optimization with no penalty in perfomlance.
al gebraic manipulation . Plot the tradeoff of the initial and size-optimi zed circ uits with respect to
2
L
CD ~ ~ ·cn
delay (gat~elays)
(a)
size and delay.
C1)
F'
-F2
Figure 6.34 Multilevel optimization that reduces size without increasi ng delay. by altering a noncritical path: (a) original circuit, (b) new circuit with fewer tran istors but same dela) . (c) illustration of the size optimization with no tradeoff of delay.
Multilevel logic optimization
a
,,,"'- -
FI = (a+b)c + dIg + elg
Minimize lhe following function 's circuit ize. al the expense of perhaps slowe r performance. using
18 transistors 3 gate-delays
25
-W 20
- 'l!' - - F2 '" c: 10
, g
Automaled heuristics for multilevel logic opti mi zation iterati vely transform the initial function's eq uation. much like for two-level logic optim ization, optimizing one of the criteria at the expense of another.
b
22 transistors 3 gate-delays
Fl
d e
umbers in .. ide gales represent transistor CQunts.
22 transistors 2 gale-delays
26 transistors 3 gale-delays
(c)
Figure 6.32 ~ing muhilc\cllogic to tradeoff performance and ize: (::I) Iwo· lcve l circui t. (b) muhilcveJ circu it wit h fewer transistors. (c) illustration o f the size ve rsus de lay tradeoff.
EXAMPLE 6.11
RedUCing noncritical path size with multilevel logic Usc multilevel logic to reduce the size of the circuit in Figure 6.34(a). without extending the circuit 's delay. Note that the circuit initially has 26 transistors. Furthermore. the longest delay from any input to the output is three gate-delays. That delay occurs through the path shown by the dashed line in the figure. The longest path through a circuit is the circuit's critical path.
'en ~ 10
FI
317
6.3 Sequential Logic Optimizations and Tradeoffs
State Reduction lale reduction . also kno\\n as store minimbttion . i an ptimization th~t redu, < the num ber of F M stme without changing the F ~rs beh'l\ ior. B) mlu -ing th number ~f ;.tates . IYC mny rcdu e th~ size of th~ required state regi,ter that nnplcm nt, th F' ~t .
D
318
OptimIZations and Tradeoffs
tbtl...
rculicing circui t size. Reducing the number of ~ I atc :-. is po",iblc \\ hen Ih~ F ~ I contains
6.3 Sequential Logic Optimizations and Tradeoffs In~p_U1_S:_ . x...:;_O_u...:tP_u_tS" _-'-y_ _ _ _ _ ____ x
x'
U
"'-latc!'> Ih 31 ar ~ eq uivalent 10 one
anolher. For c\ample. consider Ihe FS~ l of Figure 6.35(a). having inpul x and OU IPUI y . Examinalion reveab Ihm ,laIC, 52 and 53 appear 10 be Ihe , a me as SlaleS 50 and 5 /. Rc~ard l ess of whClher we sIan in 50 ';,r 52. Ihe OUlpU!!, will be idemical. For ex ample. if we start in SO and th e input sequence
y=O
y= 1
y=O
y=1
if x = 1,1,0,0
(a)
Ihen y = 0,1,1,0,0
~x' y=O
(c )
Slep
(b )
Figure 6.35 El il11 in::lIi ng redundant "itatcs: (a) ori ginal
10
OUIPUI . A 0
• for all possible sequences of inpuls. the F M OUlpU L~ will be Ihe same slaning from either SlalC. For large FSM,. visual inspeclion can nOI g uara nlee Ihal we've removed all redundant 'laICI-a more ,y'lemalic approach is needed. which we now inlroduce. Implica tion Tables Intuitively. we know Ihal IWO stales cannOI be equivalent if Ihey produce dilTercnt OU IPUIS for Ihe 'a me 'cquence of inpul'. Conl ider the FSM in Figure 6.36. which is 3lmo>l identical 10 the FSM in Figure 6.35 with a Ilighl modificalion in "ale 52, the FSM now OUIPUI' y - I in"ead of y O. Stale, SO and S2 Iherefore clearly are nOI cqulvalcOl. becau,c Ihey have dilTerenl OUIPUI value, Stale, 5/ and 53 produce the 'arne OUlpu!. hUI "'hen we I,"nlilion from either 'WIC 10 the corre'p<>ndlng ne'l ,tale. Ihe OUIPUI dllTc",. FOr c ample. If the FSM Ilan~ 10 ,late S / and x Occamc, r. Ihe nexl 1,lle (S2) oulpul, y . , bUI If
Description
pairs havillg difJerem OlflpUlS as I/onequivalelll
FSM. (b) cqui \a lenl FSM wil h fewer Slales. (c) Ihe for four clock edge, is I. I . O. O. FS 1, arc indi ign Ihe same values
TABLE 6.2 Algorithm for state reduction.
Mark
y= 1
InputS" x; au/putS" y
x'
319
the FSM had staned in 53. Ihe nexl Slale (50) would OUIPUI 1-0. Thus. 51 and 53 cannot be eqUiva leOl , because Ihe same inpul sequence resu lts in a di fferent OUIPUI sequence. If IWO Slates' OUIPUIS are nol equivalent. Ihe IWO slates clearly are not cquivalenL Funhermore, if IWO Slates' next stales are nOl equi valent for a given inpul value. then the IWO Slales are also not eq ui va len t. Using these concepts of nonequivalent talCS. Table 6.2 descnbes an algorilhm fo r reducing an FSM's number of stale.
Slate
States having different outputs ob\'iously
cannOI
be
eq ui valen t.
For each unmarked SUlle pair. write the "ext st{Jfe pairs for the same illPlII \'a lues
For each lIllma rketl state pair. mark slate pairs having nOllequil'lllelll
States with nonequivalem ne~l stales for the same input values can 't be equi\'alent. Each time through
lle.rr·Slate pairs as I/ollequi\'a lem.
this slep is called a pass.
Repeal
Ihis step III/til fl O cluII/ge
OCcurs, or ullIil al/ SUlles are marked.
4 Merge remaining state pairs
Remaining state pairs must be equi\aJem.
When comparing all poss ible pairs of Slates by hand. usi ng a graphical lable en UTe Ihal we don'l miss any pairs. Con sider the FSM of Figure 6.35(a). The F ~I has -I tatcs. Iherefore Ihere are -12 = 16 possible slale pairs. Figu"; 6.37(a) hows those po
) 50 51 52 53
r~~
(b
~
Redundanl
tii
m1
Diagonal
)S1
~
52 53
I
50 5 1 52 ]
50 51 52 53
Figure 6.36 f\ \,trialll of Ihe FS f in Figure (, 15 ~ ,t.lIC' SO and S2 cannO! oc cqlll\,llenl occaulc IhC) OUIPUI dillerclIl \Jluc'. ,lnd 't.lIe, SI alld 53 c.ln 't he equl\lIlcnl Occau-,c they hnH: noncllUI\alent nc'l "'laIc .. lor the ~me
!Oput \ Jim:'
Figure 6.37 Table of ,Iatc 1'-1i",: ta) original labk comp.1ring JII rJII'. lbl ' "url'r tJN ,~ only unique and rclCqUH pain.. (c) una initial rililng. 111 \\ ith ~I ,Iak' inf,-'mlJliCln. Figurc 6.J7(c) sleps throug h the .Iate reduction algorithm of Tabl' (:0.2 t, r the ,:'\1 of Figure 6.35(3).
320
6 Optimizations and Tradeoffs
6.3 Sequential Logic Optimizations and Tradeoffs
Step I involves looking a! every table cell and marking Ihat ce ll with a large " X" if Ihe stales for Ihal cell have diITerenl OUlputS. We refer 10 such cell as bei ng marked. The first stale pair (5/.50) is not equiva lenl because SO OUIPU IS Y - O. while 51 OUIPUIS Y= I. We Ihen look al laic pair (52.50). (52.5 / ). and so on. and finally (53.52). marking state pairs having differenl OUlpUIS. resu lting in the Xs shown in Figure 6.37(c).
(S2,S2) (S3.S1)
Step 2 involves wriling Ihe nex i state pairs for each remaining unmarked cell. There are IWO unmarked cells:
(SQ,S2) (SQ,S2) (S3,SI ) (S3,S3)
(52.50) (ci rcled in Figure 6.37(c»: When x=1. state S2's nex l slate is 53, while state SO's nexl stale is ' I (we see Ihi s by looki ng at Ihe FSM in Figure 6.35(a)). Thus. we write " (S3.SI)" in tha! cell (the order doe n'l mailer). meaning thai for slales 52 and SO 10 be eq uivalent. 53 and 51 muSI be eq ui va lent. We Ihen consider Ihe case when inpul x=O. in which case Ihe nex l Slales are 52 and SO, so we wrile "(52.50)" in Ihat cell also.
so
The method we have ju I employed is known a Ihe implicatioll table method for state reduction. Naturally, not every FSM can have its number of Slates reduced . For example, lei' use the implication table method on the FSM in Figure 6.36. With 4 lale. the FSM's implicalion table will be the same ize as the previous example. as shown in Figure 6.38(a). Step I marks state pairs wilh different OU lpu ts. shown in Fig ure 6.38(a). Step 2 lisls. for each unmarked cell, Ihe neXI tate pairs for identica l inpul va lues. as also shown in Figure 6.38(a). In step 3's first pass. we firSI examine Ihe cell for late pair (52. 51). aturally. Ihe nexI late pair (52. 52) is equi va lent. The neXI Male pair (S3. S I) is unmarked. so we cannot mark (52. 51). We then exam ine the cell for ~ Iale pair (53.51). and find th31 the nexl ~Iate pair (50.52) ha~ il\ cell marked . Thi\ lell, u\ Ihm 3 and I eannol be equi.alelll (because they could transition 10 noneqUlvalent "ate, for the sume inpul value~). ~o we mark the cell for (53.51). Similarly. we mark (53.S2) ,ince its firsl neXI 'tate palf. (50.052). ha~ its cell marked . omplellng ,tep 1\ Ii "I pas re. ults in Ihe table of Figure 6.38(b).
- -
-- - - - - -
62
lable.
x=O. the next states are SO and 52. so we wrile (50.52) in Ihe cell. For x= 1. we wrile (53.51) in the cell.
Step 4 involves declaring the unmarked tate pairs as equivalent. so 52 and SO are equiv, alent. and 53 and SI are equ ivalent. To finalize step 4 of the algori lhm. we combine the equivalent tates in the FSM . After combi ning tales 52 and SO. and com bining tales S3 and SI. we oblai n the FSM in Figure 6.35(b).
61
Figure 6.38 Implicalion lable for FSM in Figure 6.36: (a) table after initial setup and steps I and 2. (b) after slep 3's firsl pass through the table. (c) after step 3's second and final pass through the
(53.51): When
Step 3 involves marking as nonequ ivalent any unmarked cells whose next slate pairs are already marked as nonequivalent. Looking at cell (S2.S0). the nex t slate pair (53,5 / ) is nOI marked. nor is next slate pai r (52,50) (which happens 10 be the current cell), so we can 'l mark Ihis cell. Likewise, for ce ll (53.51), Ihe next state pair (SO.S2) is nOI marked, nor is Ihe next Slale pair (53,S I), so we can't mark thi s cell. Because we made a pass Ihrough slep 3 wi thout any changes. we don'l repeat slep 3. and inslead move on 10 step 4.
321
(a)
Because the table changed during the first pass (we marked rwo tate pairs). we must make a second pass, because changes in the table may affect state pairs that we already looked at and left unmarked. In the econd pass, we again look at state pair (S2.5/ ). Naturall y, the next state pair (S2.52) is equivalent. The next state pair (53.5/ ). however. is now marked, and therefore we mark (52 ,5/ ). With all pair in the lable marked, as seen in Figure 6.38(c), we can conclude that no states in the FSM are equivalent, and thu we leave the FSM unchanged. We now provide another example of stale reduction.
EXAMPLE 6.13
Minimizing states in an FSM using an implication table Consider the FSM in Figure 6.39(a). Unlike previous examples. this FSM has 5
Iates.
resulting in
more possible state pairs than in previous examples. The first task in minimizing the FS.M"s stares is to con struct an implication table so we can compare every state with en h other as a stale pair.
Inputs: x; Outputs: y
x'
y=1
($4.S3)
y=1
(SO.SO)
(a)
S3
(b)
Figure 6.39 I and _.
n
M needing Inte reduction: ta) original
~t. (h)
impl; '31100 t3ble.llt
In step I of our ,tatc reduction algorithm. \\c marl \\11h an X !
nOI cqUi\"3icOl beenu.c Iheir UIPUI dilfer. as ShO\\l' in Figure 6.3'l<,b\.
I~ I
II
6.3 Sequential Logic Optimizations and Tradeoffs
OpttmlZation s an d Tradeoffs In stcp 2, \\ \.' write in all the next ~talc pairs for unmarked ce ll:-. of the implicati on table, as .. ho\\ n in Fi g.ure 6.39( b). Since there arc onl y IWO po:-~ iblc cOlllbin:tti o n ~ of inputs (e ither x=O or \ = 1), each ulll11 arl-.t:d ce ll \\ ill have twO next slate pain-. In sirp J's first pass. we ll1ark each SHitc pair if olle of their next stat e pai rs is marked. During our fi~L pa!\, th roug h the tabl e. we wi ll exa mine four Slale pai rs. Starting wi th (52.51). we see that both of it:.- nl;':'(l Stal e pairs are unmarked. Looking at (53.50). \\ C ~ce one of its nexl Siale pairs. (53.52\' i, marked. so lI'e mark (53.50)'s cell. We also mark (5-1.50) bec,,"se ils neXl state pair (S4,S2) i... marked. \Ve h:~\\ e (5.,f,53) unmarked as both of its next SHih: pairs arc unmarked. th us completing the 11~ t P3"", Figure 6AO( a) re flects thc results or our fi rst pass through the impl icati on table. Becam.e we marked new sta te pairs in the first pass. we conduct 3. second pass th rough step 1 During thaI pas~. we find no new cells to mark. Ic:.wing the table unchanged. We thus move on to step 4. In step . t we decl are the unmarked state pai r (52. 5 I) as equivalent. and the un marked state pair (S';.53 ) ao;; equi valent. \Ve combine states 52 and 51. and we combinc state s S4 and 53. resulting in the nc\\ FS~ I shown in Figure 6...JO(b). Note that the two transitions with conditions x· and X from SO could be repl aced by one IrJllsitioll with no conditions.
Inputs:
(a)
Inputs:
Figure 6.41 A IS-Slate FSM .
323
x: Outputs: z
z=t
State reduction is therefore lypically performed using automated tools. For mailer FSM s, the tools may implement the implication table method. For larger FSMs . the tools may need to reson to heuristics to avoid inord inately large table sizes~or numbers of ne.
x: Outputs: y
(b)
Figure 6.40 Implicalion lable and minimized FS I: (a) impl icalion lable afler firsl pas . (b) minimized "ate machine wilh stales 5 I and S2 combined. and S3 and S-I combined. In Ihi , e.
Sometimes equi valent states may overlap. For ex ample. assume that for some FSM with ' tates {TO. TI . n. n . T·/}. you find that state pairs (TO.TI ). (TI.n) and (n.TO) are equiva lent. How do you deal with the overl apping equivalencies'? The answer is simple: the th ree qates. TO. TI. and n can be combined into a single ~ tate. The impl icati on table method is suitable for hand-optimizing small FSMs such as tho,e introduced in the prev ious cx(lmples. but can qui ckl y become unwieldy for FSMs "'ith more sta te~ . Consider the IS-state FSM in Fi gure 6.41 . I t~ reduced implication table "'ould req ui re 14 row' and 14 column'> . and 105 , tatc pair'> . With two combinations of tnput'> (namely. a = 0 or a = 1), e:lch statc pair would have two I1 c ~t Mate pairs. and. in the "'ON ca,c. wc would need to chcc k 105' 2=2 10 nc t ' tate pair, during our firM pass "lone. What if the ,ame FSM had four input ('>ny. a, b. C. and d ) in,tcad of one? With fo ur tnput'> . there wou ld be 4' = 16 combination, of tnput ' (i .e. a' b ' C ' d '. a ' b ' c ' d, 0' > 'rrj' ... . abed ) and up 10 16 nc" , wte pair, III each cell In the implication IUble. If tn "citd the FS M had. ,ay. 100 ' latc'> ((I rca,> onable number). the implication wble would h,,\c on the order of 100* ' 00 = 10,000 '> tal e Pit" "
State Encoding Stale ellcodillg is the task of assigning a unique bit representation for eacb tate in an FSM . Some state encodings may opti mize the resulting controller circuit b\ redu im! circuit size. or may trade off size and performance in the circuit. We now d.isc~ \ e~ method for state encoding.
Alternative 1inimum-Bitwidth Binary Encodings Previously. we assigned a unique binary en oding to ea h state in an FSM usi ng the fewest number of bits po sible. representing a lII illiIIIUIII -biI",idlh biliary ell odi;; . If there were four states. we used twO bit . ' f there were fi\'e. ix. seven. or ~i!!ht st tes. \\~ used three bi ts. The encoding represented the state in the ontroller's $t:1t ~!!i -ter. lbere are many ways to map minimum-bitwidth binary en odings to :1 ~et of :lal "'$~ 3 \ \\ e J.re given four states. A. B. C. and D. One en oding is .-1:00. B: 1. :1. D: 1 . -. n(,th r encodi ng is A:Ol. 8: 1O. C.· ll. D: OO. In fa t. there :1re 4*3 _ = 4! = _4 p'-'lS, i I encodings into twO bits (4 encoding choice ' for th ' lirst stale. 3 for th ne" 'U~ . ~ for the next. and I for the last state). Freight .'tate•. lh're are " . or o\er 40-<)00. po: " i I' encodings into three bits. For J states. there are N! (.V facto';;,)) IX , il'lk en :-c'Xling, ---a huge \lumber for an) greater than 10 r $" . ne encoding !I1a~ re, ult in I '-'
*'
324
Optimizations and Trad eoffs
6.3 Sequential LogiC Opllnuzotlons and Trodeoffs
combi nati onal logic than another encoding. Automated tools may lry several different encoding' (bu t not all N! encodings) to redu e combinm ional logic in the controller. EXAMPLE 6.14
EXAMPLE 6 15
\\ hl ch
n:pc.ltctJl)
grill.: inpuh (ignoring
invencr... ), We can try In,tcad the ;Iltcmauve binary cncmling \ huw n 10 Figure 6.42. Table 6.3 pruvide, Ihe "aIC lable for Ihe new cnc(xllng. , howlng the difference ... from obtain the fol ·
lowing CClulIlion' for the three combinational
Figure 6.42 La"cr timcr ~aatc diagrnm with altcmall\'C binary ,Iatc encod ing.
If sl-lor sO-I ) nl - 51 ' sOb ' '51 ' sOb + slsOb ' + slsOb nl - sO nO - sl ' sO ' b + 51 ' sOb + 51 ' sOb ' nO - sl ' sO 'b + s l ' sO b + sl ' sOb + 5 I ' sOb ' nO - 51 ' b(sO ' + sO) + 51 ' sO(b + b ' )
TABLE 6.3 State table for laser timer conlrolier with alternative encoding Inputs
nO - sl ' b + 5 1' 50 1l1C resulting circuit wou ld have on ly 8 gate inpulS:
2 for x. 0 for n 1 (n I i< connecled 10 sO direclly wilh wire). and 4 + 2 for nO. 11,e 8 Snle inpul is ignificanlly less Ihan Ihe 15 salc inpuls needed for Ihe binary
Off Onl On2
-On3
x. 1
x_1
TABLE 6 4 StOIO lable usillU hillory encedlllg Inl)UIS
.2
A
0
0
n2 - 5 I nl - sO
/J
0
I
nO - s3 - 53 + s2 + 51
/)
n3
OutPU15
0
51
sO
b
x
nl
nO
0
0
0
0
0
0
0
0
I
0
0
1
Figure 6.4-l \how\ Ihe rc,ulllllg clrcuiL,
for each encoding. -Inc binary ellcooillS Yield, more gate" but more Hnponol11ly. requ ire, Iwo le'Ol, of logic 11,e one-hOI cncoolll8 III Ih".example require, only one bel of I08 ic . II
0
I
0
1
1
I
0
1
1
I
I
1
I
1
0
1
1
0
1
1
I
1
I
1
0
0
I
0
1
0
1
1
0
NOllcc Ih ~H the logiC 10 gc ncrJle the ncxt 'LUle I ') jus t Wire!;! in th" example (olhcr example,
0 0 0
may require \Omc logic). Figure 6.44(c) lliu,lraleS.lhal lhe one-hOI encoding ha, les, delay,
OUlputs
s I sO nl nO
lion' arc
nl - 51 ' sO + 5150
x_ 1
Figure 6,43 FSM II" gi\' ' II ,cqucllec.
The one-hOi cncod lllg rc\uh, III the: t.lle lable ' h"" n III Tuhle 6.5 Inc ""ulling
logic output . . of a controller:
x - s I , sO (nole from Ihe lahle Ihal x-I
x 0
nU lllul
n1 - 51 'sO + 5150 ' nO - sO' x I + sO
the original CI1COdlllg. \\C
the
,"quence 0_ 1. 1. 1. 0, 1. 1. 1. elc "
00. Ihen 0 l. Ihen 10. nnd Ihen II. The
From the \trw.: table.
gcncnHe
'IrJlghtforn.lrd I1llnlln.1I blll
In Example 3.7. we encoded "laic' u.,mg a ~ lr:tiglllr()rw"rd bln~lry encoding .... truting with rc ... ulting dC'lgn hud I
InpulS- non , 0u!pu1S:,
Con
Alternative bll1ary encodll1g for three-cycles-high laser timer
325
One-hot encodll1g example
0
I
I
0 I
0
0
0
TABLE 6,5 Stale toble uslnu Olio-hOI ollcoding, Output.,
Input "
53 52 51
sO n3 n2 nl
000
I 0 0 001
o o I o o o 1 o o o 0D - - -_ _...L-_ 11
0 0-
nO
1 0 0 - 0-
0 ]-
0 0 1 0- -
mcanlOg we could Uf\C. a fa\ter clock fre. quency for that ci rcuit
encoding of Example 3.7. This encoding reduces size wi thout any increase in delay. thus repre enling an op tillli ~l1 i o n .
One-Hot Encoding There is no requirement that we encode a set of states using the fewest number of bilS. For exa mple, we could encode four states A, B, C, and D using three bits instead of just two bils. such as A:OOO, B: Ol1. C:llO_ D:llI. Using more bits requires a larger state register. but possibly less logic. A popular encoding scheme is called olle-hol encoding. wherein we use the same number of bit for encoding as there are states, and each bit corresponds to exact ly one state. For example, a one-hot encoding of four states A, B, C, and D uses fo ur bi ts, such as A:OOOl, B: OOI 0, C: Ol 00, D: 1000. The main advantage of one-hot encodi ng is speed- becau e the state can be detected from just one bit and thus need not be decoded using an AND gate, the controller's next state and output logic mal involve fewer gates and/or gates with fewer inputs. resulting in a shoner delay.
Figure 644 OnehoI encooing can reduce delay: (a) minimum binary
encooing, (b) onchOi encooing. (c) though 10lal sizes may be roughly equal (one-hoI encooing uses fewer gales bUI more flip-flops). one-hOI yields a shoner eri lical path.
, 2 3 4 delay (gale-delays) (e)
326
6 Optimizations and Tradeoffs
6.3 Sequential Logic Oplimiza lions and Tradeoffs
EXAMPLE 6.16 Three-cycles-htgh laser timer using one-hot encoding In Examp le 3.7. we encoded stales
Some problem descriplion. require us 10 generale a particular ,cq uenee of va lues On a el of OUlpUIS. For example. a problem mighl require u, 10 repctllcd ly oUlpul the following sequence on a I" " r of OUIPUIS x and y : 00. 11. 10, 0 1 .. W~ can caplure Ihe behavior using Ihe Inputs: none; Outputs: x, y xy=O l FS M wllh lour slales, A. B, . and D. as shown xy=OO in Figure 6.46. A siraighiforward binary encoding for Ihosc Slates wo uld be; 11: 00. 8: 01. C:I 0, D:l1. liS shown in Figure 6.46. WI~en we design a COntroller for Ihi s syslem. we II have a Iwo-bil SIaIC regisler. logic 10 delennll1e Ihe neXI MaIC. and log ic 10 generale xy=l l xy= 10 Ihe OUlpul from Ihe present slllle. BUI might il
using a . . traightforward binary encodi ng. ~ta rtin g with 00. lhen al. then 10 . and then 1 1. Herc. we'll pafonn a one- hOI encoding of the four !-laICS. requiring four bits. as shown in Fi gure 6.-l5.
Tabl e 6.6 shows a !- Iale wble for
the FSM of Figurc 6,45. using the on e-hoI encodi ng of the stales. We don', show all possible rows. since the table wou ld bl.:! 100 large. The 1a~1 step b to design the combillruional logic. Deriving eq uations for each output direct ly from the table (assuming all oth er input combinations Jre dOlfi-cares). and minimili ng th ose equat ions ~)Igcbra icalJ y. results in the fo llowing:
x -5 3 + 52 + 51 n3 n2 nl nO
-
Thi s
would
InpulS
0111 0112 require
3+0+0+2+(2+2) = 9 gale inputs. Thus, lht.! circuit has fewer gate inputs Ihan the original binary encod ing's 15 gate inpuls-but one must also consider thm a one-hOI encod ing uses more
make more sense 10 u ~c a !'lIme encoding that is
TABLE 6.6 Slale lable for faser timer conlroller wilh one-hoI encoding.
Off
52 5I 50*b 50*b ' + 53 circui t
Figure 6.45 One-hot encod ing of laser limer.
53 52 51
0113
327
O UlpUI Encod ing
Oulputs 50
b
x n3 n2 nl nO
a a a 1 a 0 a a a 0 a 0 1 1 a a a 1 a 0 1 0 0 1 0 1 0 a a 1 a 1 1 0 1 a a 1 a a a 1 1 a a 0 1 0 0 1 1 1 a a 1 a 0 a a 1 a a a 1 a 0 0 1 1 0 a a
1
0 0 0 0 0 I 1
nip-nops. M ore importantly. the ci rcui t with one-hot encoding is slightly fas ter. The critical path for thlll
circu il is nO : 50*b ' + 53. The crilical path for the circuil with regular binary encoding is nO • 51 ' 50 ' b + 5 150' . The regular binary encoded circuil requires a 3-inpul AND gale
EXAMPLE 6.17
Sequence generator using output encoding
feeding into a 2-i npul OR gate. whereas the one-hal encoded circuit has a 2-input AND gate feeding
Example 3. 10 involved design of a sequence gener-
in a 2-i npul OR gate. Bccause a 2-input AND actually has slighl ly less delay tha n a 3-inpul AND
ator. in which we we re
gate. Ihe one-hot encoded circuit has a shorter critical path.
000 I. 00 11. 11 00. 1000 on a sci orrour out pUIS.
For exampl es with more states, the cri tica l path red uclions from one-hoI encoding may be even greater, and reducl ions in logic size may also be more pronounced. AI some poinl, of course, one-hOI encoding results in 100 big of a slate register-for example, an FSM wilh 1000 Slales wo uld require aiD-bit Slale register for a bi nary encoding. bUI would require a looo-bil Siale register for a one-hOI encoding, which is probably too big 10 can· sider. In such cases, we mighl consider encod ings using a number of bi ts in belween thai for a binary encoding and thai fo r a one-hot encoding.
Figure 6.46 FSM for given sequence.
idenlica l 10 Ihe OUlpul va lues in each Male? If we use such an encod ing. Ihen we will slill have a Iwo-bi l sWle regisler. and we will still have logic 10 generate Ihe nexi Mme. bUI we wo n' t have log ic 10 generate the OUlput fro m the prcselll Slate. Inslead. each OUIPUI will si mply be connecled by a wire to a bit in Ihe slate regisler- Ihus reducing Ihe requi red number of logic galc •. If an FSM has at Icasl as many OU IPUIS :t~ needed for a binary encod ing, and if each Slale has a unique OU IPUI combinalion. Ihen we may consider usin g a st.lie ·s OUIPUI combination as Ihe Slatcs enCoding. Such an encoding may reduce Ihe amount of logic required. by eliminat ing Ihe need for log ic 10 generale Ihe OUlputs from Ihe present Slate encoding-Ihal log ic is reduced 10 jusl wires. OUIPUI encoding requires Ihal Ihe syslem have al leasl as many outpulS as il has bits in a minimal binary encod ing. olherwise the OUIPUIS ca n'l re present enough encodi ngs 10 un iquely idenlify each Slate. Furthermore, we can' l usc o utpul e ncoding if the desi red outpul equenee contains Ihe same OUIPUI va lues in IWO different stales, since every tate's encoding musl be unique. For example. if we wish to repeated ly generate the seq uence 00, I I. 01. I I. we cannol use OUIPUI encod ing. because if we did, then two tates would have Ihe same encod ing. Even in such a silumion. though, we might try to OUlput encode as many slates as possible.
10
gCllcm te the sequence
as shown in Figure 6.47. 111 that example. we encoded th e states lIsing a two-b it bin ary encodi ng. wilh II being 00. B being 01. C being 10. and D
being 11. In this example. we ll inslead use OUIPUI encod ing. The OUIPUIS have enough bit>. four. whereas we need at least two bi ts to encode the four Slates. The sequence also has a different output combination for each state. Thus. we can consider output
encoding for Ihis example.
none; Outputs: w, x, y, z wxyz=OOOt wxyz=tOOO
tnputs:
y
wxYZ=OOll
Wxyz=ll00
Figure 6.47 Sequence generator FSM.
.328
Optimizations and Tradeoffs Table 6 .7 ~hO\\ ... a panial ,tatc U1ble for the ,cquencc:: generator. u~ing an output cncooinf!. Notice th:!! the outputs them· ...e!'e' w~ x. y. and z . don't need 10 appear in the table. a~ tht.!) \\ ill be the sa me as 53.
6.3 Sequential logic Optimizations and Tradeoffs TABLE 6.7 Partial state table lor sequence generator controller using output encoding. Inputs s3
n2
nl
A
0
0
0
I
0
0
I
I
B
0
0
I
I
I
I
0
0
C
I
I
0
0
I
0
0
0
0
I
0
0
0
0
0
0
I
52 . 51. and sO. We u,e a partial table to avoid ha\ i1H~ 10 ~ ho\ all 16 rows. and we
assume Lh:lI~ all un~pct' ificd row~ represent
From the table. we derive equa ti ons for c:H.'h output J~ roll ow~:
n3sl+s2 n2 - 5 I nl - 51 ' 50 nO - 51 ' 50 + 5352 '
Outputs
52
sl
sO
n3
\\le obtained those equations by looking al all the Is for a particular output. and visuall\ dClcrminine a minimal input equation
nO
~ ~;;:
~~~
~
th;t "ould gene-rate those I s and Os for the other ,ho\\ n column enLries (all orner output
\alues. not shown. are don 't cares). Figure 6A8 ~ hows the final circu it. Notice that there is no output logic-me outpuLS \01 . X. y. and Z connect directly to the Slate register. >-Compared 10 the circuit obtained in 53 s2 st sO E,ample 3.10 u'ing a binary encoding. the output encoded circuit in Figure 6.-l8 actually appear; to use morc transistors. In olher elk State register c:
Recall the standard controller architeco c." ture of Figure 3.48, reproduced in Figure 0 _ ", ~~ 6.49. The architecture shows one block of combinational logic, responsi ble for convening the present state and external inputs into the nex t state and external outputs. Because a Moore FSM 's outputs are solely a fun ction of the present state (and not the external inputs), then we can refine the archi tecture to have two combinational Figure 6.49 Standard controller arc hitecture-general view. logic blocks: the lIexl-Slale logic block convens the present state and external inputs into a next state, and the outpullogic block convens the preseot stale (but nOI the ex ternal inputs) into external outputs, as shown in Figure 6.50(a). In contrast, a Mealy FSM's outputs are a funclion of both the present stale and the external inputs. Thus, the output logic block for a Mealy FSM takes both the present State alld the external FSM inputs as input, rather than ju t the present state_ as bown in Figure 6.50(b). The next-stage logic is the same as for a Moore, taking as input both the present state and the external FSM inputs.
o
c."
0i5 '" SoS:
'"
H-J
---b
I
n3 n2 Whether one-hot encoding, binary Figure 6.48 Sequence generator controller with enCoding, output encoding, or some output encoding. \ariation thereof re"ult~ in fewe t transisto" or a ,honer critica l path depends on the example itself. Thus, modern tools may try a variety of different encodings for a given problem to sec which works best.
Moore versus Mealv FSMs Basic Mealy A rchiteclure The FSM, dc'Cribed In this book have thus far all been a type of F M known as a Moore FSM A Moore FSM b an FSM who c outputs arc n function of the FSM's state. An alternatIVe type of F M " a Mealy F M. Mealy FSM is nn FSM who e outputs are a funClton of the FSM\ ,tates alld illl'lIIf. Sometime, a Mealy F M resu lts in fewer SUItes than a Moore I-SM. rcprc-.enttng an opt.mtlallOn Sometime' tho'e fewer states come at the c'pcn,c of liming comple~ ttie, that mu\{ be handled, repre,cnting a tmdeoff.
329
Figure 6.50 Controller architectures for: (a) a Moore FSM. (b) 3 Meal) FSM. Graphically. the FSM output assignments of a Mealy FSM wou ld be listed with ea h transition. rather than each tate. beenu e each transistion represent a present state and a particul ar input value. Figure 6.5 1 hows a two-state 1ealy F M with an input b and an output When in state 0 and b-O , the F M outputs =0 and stays in state O. as indi 'atcd by the transiti n labeled "b' I x-O". \ hen in state 0 and b = 1. the F M output. - 1 and ~oe to state I. We usc the .. r ,impl to sepn;'ue the tran iti n'$
Inputs: b: Outputs: x
Figure 6.51 A Me31) output:.. \\ lth tmnoMti
330
OptimizatIOns and TradeoHs
6.3 Sequential logic Optimizations and Tradeoffs
r
input cundi tions from the output assignments-the .. does not mcan "di vide". here. Becal"e the tran>ition from 5/ to 50 IS taken no mattcr what the In put value. we list the
. The Mealy state diagram in Figu re 6.52(b) uses a convention similar to the convention we used for Moore FSMs (Section 3.4). namely. that any outputs not explicitly aSS igned on a tranSlLlon are implicitly assigned a O. As with Moore FSM . we till Ii tan assignment to 0 ex plicitly if the assignment is key to the FSM - behavior (such as the ass ignment of d=O in Figure 6.52(b».
tran~ilion simply a~ "/x'='O :' meaning there's no input conditi on. but there is an output
assIgnment. ~ leah' FS~ Is ~ lay Have Fewer lales The ~eeming l Y minor difference between a Mea ly and a Moore FSM. namely. that a ~Iealy F ~I \ output is a functi on o f the state alld the current inputs. can lead to fewer ;tatc, for some behaviors when implemented as a Mea ly machine. For example. conSider the ,i mplc ,oda dis penser controller FSM in Figure 6.52(a). Setting d= 1 di spenses a >oda. The FSM stans in Slate /Ilir. which se ts d=O and sets an output C 1ea r~ 1. which we a,;ume clears a device keeping count of the amoun t of money deposited into the soda dispenser machine. The FSM transit ions to state \Vail. where the FSM waits to be informed, throu2h the enough input. that enough money has been deposited. Once enough money ha; b~en deposited. the FS M transiti ons to state Disp . which di penses a soda by setting output d= 1. and the FSM then returns to state /Ilil. (Readers who have re~d Chapter 5 may notice this example is a simplified ve rsIOn of Example 5. 1: famili ari ty with that example is not req uired. tho ugh. fo r the present diSC US IOn .).
331
EXAMPLE 6.18
Beeping wristwatch FSM using a Mealy machine Create ~111 FSM for a wristwa tch that can display one of four register by setting two outputs S 1 and 5 O. which contro l a 4x I l11uhiplcxer that passes one of the four registers through. The four registers correspond to lhe walch 's present time (sls0=00). Ihe alann seILing (01). the dale (10). and a stopwatch (11). The FSM should sequence 10 the nexi regisler. in the order listed above. each time a bUlIon b is pressed (assume b is synchronized wi th the clock as 10 be high for only 1 clock cycle on each umque. bUllon press). The FSM should SCI an OUlput p 10 1 each time the bUllOD i pressed_ c
s1 , sO. P b'/s 1SO=OO.
Inputs: b; Outputs: 51 . sO. P
p=O
Time
b'
b 5150=00. P=O
Inpuls: enough (bit) OutpulS: d. clear (bit)
InpuIS: enough (bit) OutpulS: d, clear (bit)
c:w
b'/51S0=01 , p=O
/ d=O, clear=1
5150=00. P=1 b'
(a)
b'!S150=10. p=O b'/s1S0=11.
p=O
d=1
clk~ Inputs: enough
Slale:
~ It Iw lw!
D! I
OutPuIs:clea;~
elk Inputs: enough
...ruuiJuul
-----t-i-L-I
Slale: OUIPuIs:clea;
I
~
(a)
111
; t.,O'. (b) Mealy
FSM ha~ acllon, on Iran'lition\, rc5tu ll ing in Ihi" cn"'c In fc",cr ,tatcs.
(Jlt..~
"'"h
F\\,I\.
!.((lflrr
kf'/oIlIlK
11'll1/ unuUIF/nt·"
'Jurpuli In II "Iftl/.,I ~t.1
d ,t.Jf r UlJ1urr ITYJpIUIi/\ aU'j(flt'(/(1
-
- -
---
,It",.
Figure 6.53 FS ,I for 3 wristwatch with beeping beh.vior (p= I) when bUlIon is pressed (b= 1): (3)
Mealy. (b) MoofC.
(b)
Figure 6.52 FS I, for q)(la di'pcn..er controller: (a) Moore FSM h., action,
'hI" f (ln~"n1"m
(b)
Iw I Wit I
Figure 6.52(b) .. how . a Mea ly FSM for the .. nme cont roller. The initi al slate /lIil has no attlon .. iL<,elf. but rather ha, a conditionle,' tran
Figure 6.53(a) shows a Mealy FS~I describi ng the desi",d beha\'ior. 1\oti -e thai the ~Ieah FSM e.lsil y caplU ~' the: beeping ~h3vior. simply by setting p-1 on the tr.ln~itions th:n :'Oln!spond to bUlIonllfc".s. Inlhe ~I oo", F ~I of Figure 6.53(bl. \\0 had 10 add an c,tra "at< 1I1 rem n ea.:b pair of M:ttC~ in Figure 6.53. with each t:'.xtra state haying the action p-l and ha\ ing a C\'\[ldio\. nI $~ Ir:ln~ilion
to the IlC\( slate.
I a lice that lhe Menl) FS ~I h~ fc\\a M:Hes than th~ ~toore ma..:hioc.:\ dr.l\\ txk: b that \\ gunr:lIlla::d Ih ~lI a beep \\ illla~1 al least ont' lock C) ck. due to ttming i~ue, that \\ e will :n
.:mm't
Ti min!,! Issues \\ illt l eu l~' F i\ ls Icul), F 1 ou tputs are not ,,~nchronized \\ ith ci<:l<:k Ig~,_ bUI rather 'un 'hang in l~ t\\' ce n dod edges if an iltput l'h,l1tge~ . For e\JlIlrle. )It, id'r Ih lImtng dt.\gr.ull
331
OpllmlZations and Tradeoffs
6.4 Datapath Component Tradeoffs
sho\\n in Figure 6.52(a) for a soda dispcnse r s Moore FSM . Note that the out put d become, 1 1I0r rig hr (lfter the inpu t enough became 1. but rather UII rhe fi rSI clock edge ajrer enough became 1. In cont rast. the timing diagram for the Mealy FSM in Figure 6 . 5~tb) ,hows that the output d becomes 1 righl (1{ler the input eno ug h becomes 1. ~ I oore outputs arc synchroni zeu wi th the cl ock: in panicu lar. Moore outputs onl y change on entaing a new , tatc. which means Moore outputs only change slightly after a rising clock edgc loads a new state into the state register. In contrast. Mealy outpu ts can change
EXAMPLE 6.19
TABLE 6.8 Mea ly state table lor soda
Implement ing a Mealy FSM We create a controller imp lementing a Mealy dispenser FSM in nearly the identical way that we created a In puts Outputs controlle r for Moore FS Ms in Section 3.4. using sO enough nO d cle ar the method of Table 3.2. The only difference is that whe n we create a state table. the FSM out- Inil 1 0 0 1 0 puts ' values fo r all the rows of a panicu lar Slate 1 0 1 1 0 won -t necessarily be identical. For examp le_ Table 1 0 0 1 0 6.8 show~ a state table for the Mealy FSM of 110;1 0 1 1 a 1 Figure 6.52(b). Notice that the output d should be a in state Wail (50=1 ) if enoug h-a . but should be 1 if enough= 1. In contrast. in a Moore state table. an output"s values were identical wIthin a given state. Given the state table of Table 6.8, we would proceed to implement the oll1binational logic in the same manner as descri bed in Section 3.4. \'''''/fllt Int' lit
'-100ft"
(}HI
""/tt'M/In!
11'
mu hdp
HuJt's flU
rt'mrmhu /lUll W.,.,rr F51,,/ I ,~
114"'.f Of
U
IJ' tn
1~1'il'''1 ... 1,,/,.
\ 1,./11 "on Ilu' Il/lIlllillft
Combining 100re and Mea ly FSMs Dc, igne" often utilit.e FSMs that arc a combination of Moore and Mealy types. Such a comblllatlon allow~ the de\igner to specify some actions in tate _ and others on transi11 0n'>. Sueh a combination provides the reduced number or state advantage of a Mealy FSM. yet avoid, having to replicate a , tatc', action. on every ou tgoing trnnsition of a Itate_ Thl l , implificatlon i, rea ll y ju,t a convenience to u designer describing the FSM: the underl YIng implcmentatlon wi ll l i ~cly be thc arne as for the Menly FSM having repheated actionl on a 'tate'" ou tgoing tranl;ti nl
. . usmg a combined Moore/Mealy machine FIgure 6.54 shows a combined Moore/ Mealy FSM state diagram describing the InpulS: b: Oulpuls: s 1_ sO, P b'/p:O beeping wnstwatch of Example 6.18. The F~M has th e same number of states as
did the Mealy FSM in Figure 6.53(a)_ because the FSM sull associates the beep behaVIOr p= 1 W i th transitions. avoiding
not just on entering a new S I ~He. but also any lime an input changes. because Mealy
outputs are a fun ction of both the state and the inputs. We took advantage of this fact to eliminate the Disp state from the soda di spenser s Mealy FSM in Figure 6.52(b). Notice, howe\cr. in the timi ng diilgrall1 that the d output of the Mealy FSM does 1101 SlaY lfor a complele clock c.\'Cie. If we are unsure as to whether d's hi gh time is long enough, we could inc lude a Disp state in the Mealy FSM . That state would have a single transition, \\ith no condition and wi th action d=1. poin ting back to state Illil. In that case, d would be 1 fo r longer than one clock cycle (but less than two cycles). The Mealy FSM feature of outputs being a function of states and inputs, which enables the reduction in number of states in some cases. also has an undesirable characteristic-the outputs may glitch if the inputs glitch in between clock cycles. A designer u,ing a Mealy FSM shou ld determine whether such glitching could pose a problem in a panicular circuit. One solution to the glitching is to inse n flip-fl ops between an asynchnr nou Mealy FSM's inputs and the FSM logic. or between the FSM logic and the outputs. uch flip-fl ops make the Mealy FSM synchronous, and the Outputs will change at predictable interva ls. Of course. such flip-fl ops introduce a one clock cycle delay.
333
Beepmg wristwatc h FSM
b'/p=O
the need for ex tra Sla tes to describe the b~ep . BUI the combined FSM Slale diagram IS easier to comprehend than the
b'/IT-O
Mealy FSM state diagram, because the assignments to s I s 0 are associated wi th each ~tale, and not duplicated on every
b'/p:O
ou tgoing transition.
Figure 6_54 Cambinin. Moore and Mealy FSMs yields a simpler wri twalch FSM_
6.4 DATA PATH COMPONENT ffiADEOFFS ~~e:~d~: 4, we created several components that are useful in datapath . In that chapter. we describe m basIC, easy to understand versions of tho e components. In this section_we et s to bUI ld faster or smaller versions of ome of those components.
n;,:
Faster Adders Add"1I1~ two numbers is an extremely common operation in digital circuits, so it mak ~:n se_ .or us to try to cr.eate an adder that is faster than a carry-ripple adder. Recall that a
rry npple adder reqUIres that the carry blls ripple throu2h all the full-adders bef.ore all ~e outputs are co:r~ct. T~e longest path through the c; uit, shown in Fi2ure 6_- -. i ~nown as the CirCUli s crlflcai path . Since each full- adder has a delav of ( \\"0- 2ate-delav en a 4-bll carry-npple adder has a delay of 4 • 2 = 8 "ate-delay -A ~~ - bl' t -I' add ' d I . 3? ' '= -' ~ -npp c er s e ay IS ~ 2 =. 64 gate-delays. That 's rather slow, but the nice thin2 -about a carry-npple very- man)' '=oale ' If a fuji -add h 4 b" adder IS thal li doesn't require . . er uses- - !!at - , t en a - 11 carry-npple adder reqUIres only -l • 5 = 20 2ate . and a 3_-bit --ri I ruT) pp e adder would on ly require 32 • 5 = 160 gates.
-c·- -
J
a3 b3
a2b2
_
ao bO
at bt
51
Figure 6 55
~ -bit
carry-ripple adda_\\ith th,' I,>ng sl P.1th (th,' ,-nl1,'all'1thl ,oo\\n.
..
Q
3J~
l
OptimIZations and Tradeoffs \\oldd like to de,i~n an addcr thut i, much closcr to the dday of just a few gates, pcrhap . . abollt 5 or 6 gatc-dda)!'-. at the po~~ibl c l!xpcn~c of morc gales.
6.4 Oatapath Component Tradeoffs
335
We
T\\ o-Level Logic Adder One ob\ iOll':" way to
crC(l tc
a faster adder at the expense
or morc
gates is to Li se our
earlier-deli ned two- level combinational logic design process. An adder designed using twO Ie"el> of logic has a delay of onl y twO gate-de lays. ThOl 'S certa inl y fast. But recall from Figure ~ . 15 that buildin g an N-bit adder using twO leve ls of logic results in excesshe ly large ci rc uil~ as N increases beyond 8 or so. To be ~lI rc you gel thi s point, let's
a3b3 coul
a2 b2
__ cm
al bl aObO cin 4-bit adder 53 52 51 sO
carries: c4 B:
A:
+
caul
(a) a3 b3
a2 b2
c3
c2
b3 a3 53
cl
cO
b2
bl
a2
al 51
bO aO
52 (b)
sO
al bl
res tate the previous sentence sli ghtly: Building an tV-bit adder 1I,ing twO levels of logic re~ lIlt~ in sJ/Ock i,,~/y large circuits as N incre~c~
be) and
or so.
For example. we estimated (i n Chapter ~) that a two- level 16-bit adder would require about 2 milli on transistors. and that a two-Icvel 32-bit adder would requi re about 100 bi II ion transistors. On the other hand. building a ~-bit adder using twO le"el, of logic results in a big. but reasonabl y sized adder-about 100 gates. a was sho\\ n in Figure ~ . 15 . We could bui ld a larger adder by cascading such fast ~ -b it adder> together. Say \: c wa nted an 8-
a7 a6 as a4 b7 b6 b5 b4
a3 a2 al aO b3 b2 bl be
a3 a2 al aO
b3 b2 bt be ci
(c)
Figure 6.57 Adding 1\\'0 binary numbe b
co Figure 6.56 8-bil adder built from
"
looks ~1 all earlier bi ls and computes w~e~e~ ~h~\'e me~~ci~nt carry-lookahead scheme-each rage delay ISslage 3 which has 2 100 ic I I f carry In bUIQ mal stage "QuId be a 1. The lon
fast 4-bi t adders.
bit adder. We cou ld build this by cascading "'0 fast ~ -b it adders together. as shown in Figure 6.56. If eacb 4-bit adder i, built from two le'cls of logic. then each 4-bit adder has a delay of 2 gate-delays. The -I-bit adder on the right take 2 gate-delays to gcnerllle the , um and carry out bits, after \\hich the ~-bit addcr on the left take another 2 g31 e-dclay~ to gencrate it outputs, re~ulting in a IOta I delay of 2 + 2 = 4 gate-delays. For a 32-bit adder bu ilt from eight -I-bit adde". the delay wou ld be * 2 16 gate-delay,. and the -ize would be about 8 • 100 gates = 800 gates. That's mucb bener lhan the 32 * 2 = 6-l gate-delays of a carryripple adder. though lhe improved speed co m c~ at the expen,e of more gates than the 32 - = 160 gate, of the carry-ripple adder. Which de,ign is bcner? The answer depends on your requirements-lhe de,ign w.ing two- leve l log ic 4-bi t adders i bener if you require marc ,peed and can afford the ex tra gate" whe re,,, the dc,ign using carry-ripple -I-bit adde" i, better if you don'l need the speed or can't afford the ex tra gates. It' a tradeoff.
of only four ga;e-delays.
e
S
or the lookahead. and 2 for the full-adder. for a total d;lay
A Naive Inefficient Carry-Lookahead Sellen . of carry-lookahead is as fo llows. Recall that~' One Impk but nOt "et) effi ient way II1pUlS a b and c ad e output equauon for a full-adder ba\ino . . . n outputs co and s . are: =-
s = a xor b xor c
=
Carry-Looka head Adde r A carry-Iookahead adder imp")\c; on the ,peed of a carry-ripple adder. but without using as many l!ate, as a t"o-Ievel logic addeL The baSIC Idea" to "look abead" into lower stages to determine whelher a carry "ill be cremed in tbe pre,elll , tage. -1l1i, lookabcad concept i 'cry elegant and general lie, to other problem,. We will therefore 'pend ,ome time introdUCIn!! the IntUIlU)I1 unoerlYlng lookabead on,"der the ,"dellt"on of t\\O 4-bit numbers ,h,,"'n In I lgure 6.57(b). WIth lhe carne, In each column I.,hclcd O. ( I. t2. e3. and e4.
eve
CO = bc
ae + ab
So we know that lhe equations for el. e2 . and e3 in a ~-bit adder will be: el e2 e3
coO col co2
bOcO + aOeO + aObO blel aIel + albl b2e2 + a2e2 + a2b2
In words. the equation for the carry ' ta a pano. ular stage i- the same a- the equa. other r ' -In t,on ,or the carry-out of the pre"ious stage. We can substitute the equali n ~ r e-l ,'nt e 2 - equati II. resulling in: e2 - blel + aIel + albl e2 - bl(bOeO + aOeO + aObO) ~ al(bOcO T a c2 - blbOeO + blaOcO + blaObO ~ albOeO ~ albl
cO
~ aO
\ e can thell ,ub,tilllte the equ:lli n for c2 into c3 ', equal1oll. re,uhlOg in:
336
6 Optimizations and Tradeoffs
6.4 Datapath Component Tradeoffs
e3 : b2e2 + a2c2 + a2b2 e3 = b2(blbOeO + blaOeO + blaObO + albOeO + alaOeO + alaObO + albl) + a2(b lb OeO + blaOeO + blaObO + albOeO + alaOeO + alaObO + albl) + a2b2 e3 = b2blbOeO + b2blaO eO + b2blaObO + b2a lbO eO + b2alaOeO + b2alaObO + b2albl + a 2b l bOeO + a2blaOeO + a2blaObO + a2albOeO + a2alaOeO + a2alaObO + a2albl + a2b2
carries: c4 c3 c2 cl
::I· :~ : cout
-
aObO + (aO xor bO)eO albl + (al xor bllel a2b2 + (a2 xor bZ)eZ (a3 xor b3le3 a3b3
lE ljl:'
1
,''''
!
1 "
:
1 ']01
1
i .:!i...:J....:
-- ~ 1
,,'
1---t . ~bO -
o ~_ao
+ 1
' ,:
i'-~ObO =l' then cl = 1 (call thiS G: Generate)
-+~~
0
0
if-~O xor bO t then cl = 1 ~ cO = 1 (call this p . Propagate)
=
,J"·:~~:::U~---J -f~ - - - - - - ~ ij.~ L f~
,
G'
"
cO
...
1
0:
a3 b3
00
_____
~
.•. --- ... •. • - -. - ----.---_.
cout P3 G3
53
52
(bl
.J
sO
PO GO
r
"1~"1Jft(jl~lI~~~~il~li~~~~~~;;~~~:t~~
" "
"" ::
"" """" """ """"
A more efficient carry· lookahead scheme is as follows. Consider again the addition of twO 4·bit numbers A and B. hown in Figure 6.58(a). Suppose that we add each column's tWO operand bit (e.g .. aO + bO) using a half.adder. ignori ng the carry·in bi t of that column . The resulting half·adder outputs (carry.out and sum) give us some useful informati on about the carry for the next stage. [n panicular:
cl e2 c3 e4
~. .
al l aO ;
51\SO/
(a)
A ll Efficient Carry-Lookahead Scheme.
In other word~ , el wil l be I if aObO-l. OR if aO xor bO - 1 A D eO- !. So we get the following equation, for the carry bits:
Cl---
' ..../
We'lI omi t the eq uation for e 4. in order to save a few pages of paper. We could create each stage with the needed inputs. and include a lookahead logic component implementing the above equations. as shown in Fi gure 6.57(c). Notice that there is no rippling of carry bits from stage to stage-eac h stage computes its own carry· in bit by ""looki ng ahead"" to the val ues of the previous stages. While the above demonstrates the basic idea of carry· lookahead. the scheme is not very efficient. e I requires .j gates. e2 requires 8 gates. and e3 requires 16 gates, with each gate requiring more inputs in each stage. If we count gate inputs . e I requires 9 gate inputs. e2 requires 27 gate inputs. and e3 requires 7 1 gate inpu ts. Building a larger adder. sayan .bi t adder. using this lookahead scheme wou ld thu likely result in execs· sively large size. While the pre ented scheme is therefore not practical. it serves to introduce the basic idea of carry·lookahead: by having each stage looking ahead at the inputs to the previous stage and computing for itself whether that stage's carry.in bit should be I, rather than waiting for the carry·in bit to ripple from previous stages, we get a fo ur·bit adder with a delay of on ly 4 gate·delays.
If the addi tion of aO wi th bO resul ts in a carry·out of 1. then we know for sure that e I will be 1. regardless of whether cO is a I or O. Why? Because considering adding aO+bO+eO . then 1+1+0=10. and 1+1+1 - 11 (the ""+" represents add here, not OR}-both cases generate a carry·out of I. Recall that a half·adder com· putes its carry·out as a b. If the additi on of aO with bO re ults in " su m of 1. then e I wi ll be 1 only if cO is 1. In panicular. con idering aO+bO+eO. then 1+0+1 - 10 and 0+1+1-10. Recall that a half·adder computes i L~ sum as a xor b.
53 s2
/~ ........ cin : \
bl 1 bO :---- _______ ~
337
'. "" " "
: :
/I
,
l~=== ============~~~~~=~~~=== =...------------------~~.~P:-~~ ,-._. -------------cl = GO + POcO c2=Gl +P1GO PfPOcO c3 = G2 + P2Gt + P2PtGO + P2P1POcO cout;, G3 + P3G2 + P3P2Gl + P3P2P1GO + P3P2P1POcO (cl
Figure 6.58 Adding IWo binary numbers using 3 fasl cam ·Iookah d h . ' propagate and -. ea "" eme. (al ,dea of genernte tenns. (b) computing lhe propagate and c.ener-He U!mh .lookahe..1d logic. (e) using Ihe prop.1gale ';;d gene"';;e lerntS I
Ihe c;rrY c~mes or each olumn. The correspondence bel\\een e I in 10
cn'CIcs connected by the line: ~imilar ('o~pondences
eAist
-ill
d
.
'IO
a
~
q~':h ~~ ng::;m
fi2Urt"
tel and bl -·sOO
fo; c ... and C .
~
I'
~
put. wn b~ ~o
Let's include a hnl f·ndda in en h tage to add th~ ( \\ 0 """mnd b'I" t' tha I
338
UJn
Optimizations an d Tradeoffs
'/UHCIWmt'.\'
\\ 'ht'1/
clObO=J . lit'
kfl(}\I\lt'sllould gel/ frail! d I felr c/. H ht'II"Oxor
6.4 Oatapath Component Tradeoffs
half-addcr'$ ~ l11l1 Olltput with the colu mn 's carry-in bit to compute that col umn's sum bit, because Ihe sum bil fo r a column is jusl a xor b xor c (see Secli on 4 .3. page 188). Let"s re name Ihe earry-ou lpUI of Ihe ha lf-adde r gel/ erate. symbolized as G-so GO mean, aObO . Gl mca ns alb!. G2 mea ns a2b2 . and G3 means a3b3 . Le l's a lso rename Ihe sum OUlpU I o f Ihe half-adder as propagate-so PO means aO xor bO o PI means al xor b!. P2 means a2 xo r b 2. and P3 means a3 xor b3. In sho rt:
bO= 1.11£,1..,1011 propagate lhe cO fa/m'l/rcllt' I'll/lit' oJcl. mf'Cl1Img c / sholild t'qlUlll,.'O.
Gi ~ aibi (gel/erale) Pi ~ ai xor bi (propagme) When we pe rfor m carry- Iookahead. ralher Ihan look ing direc ll y al Ihe operand bils of previous slages as we did in Ihe naive look ahead scheme (e.g .. slage I looking al aO and bOlo lel 's look inslead at Ihc half-adder oulPUIS of Ihe previous slage (e.g .. slage I looks at GO and PO). Wh y? Because the lookahead logic wi ll turn OUI 10 be simpler Ihan in the nai ve lookahead scheme. We ca n Iherefore rewrile our equations for each carry bil as fol lows: cl c2 c3 c4
GO Gl G2 G3
+ + + +
POcO Plcl P2c2 P3c3
Substiluling like we did for Ihe na ive sche me, we gel Ihe fo llow ing carry-Iookahead cl c2 c2 c3 c3 c4
GO Gl Gl G2 G2 G3
+ + + + + +
POcO Gl + Pl(GO + POcO) Plcl PIGO + PI POcO G2 + P2 ( GI + PIGO + PIPOcO) P2c2 P2Gl + P2P1GO + P2PlPOcO P3G2 + P3P2Gl + P3P2PlGO + P3 P2PlPOcO
ai * bi, Pi ~ ai Re me mber. Ihe P and G symbo ls represent simple lerms: Gi xor bi . Figure 6.58(c) shows the circuits implementing Ihe carry- Iookahead equations for compuling each slage's carry. Figure 6.59 shows a high-level view of Ihe carry- Iookahead adder's design from Figure 6. 58(b) a nd (c). The four blocks o n Ihe lOP are responsible for generating the sum, ~
Figure 6.59 Hlgh· level view
Or" 4·bil earr)'-Iookahc:rd adder.
propagale, and generate b' I ' 6.58(b) thaI each SPG b ns- el S call1hose "SPG blocks," and you'll recall from Figure use the pro lock conSIsts of JUSI three gates. TIle 4-bn carr)'-Iookahead logic using only I paglate a nd generale bils 10 precompute the carry bits for high-order stages. wo eve ls of gates. The complele 4-bil I Ihe nonlookahead 10 ' carry- ookahead adder require onl y 26 gates (4 *3=12 gate for g lC, and Ihen 2+3+4+5= 14 gates for the lookahead logIC). TIle d e Iay of IllIS 4 bil dd . - a er IS onl y 4 gale-delays- I gale Ihrouoh the half-adder 2 gates Ihrough the carry lookah d I . " . ea OgIC, and I 10 finally gene rate Ihe sum bil (we can see thos I . F I de gah es tn Igure 6.58(b) and (c». An 8-bil adder buill usi ng the same carry-lookalea sc eme wou ld still hav . d I f e.r e ay of onl y 4 gate-delays. bUI would require 64 gate (8*3-?4 I gales or Ihe nonlookahead logic. and 2+3+4+5+6+7+8+9 = 44 gales for the 100k I a lea 0lgd'C). A .16-bil carry-Iookahead adder wo uld still have a delay of 4 gate-delays. b wou- 6 requIre ?OO gales ( 16*3 =4 8 gates for Ihe non lookahead 10glc. . 2 ul3+4 and 3 + . +)+ +7+8+9+ 10+11+12+1 3+ 14+15+16+1 7= 152 gates fo r the lookahead logic . A 2-bn carry-lookahead adder would have a delay of 4 gale-delays. but would require 656 gates (32*3=96 gales for the nonlookahead logic. and 152+18+19+20+21+22+23+24+25 +26+27+28+29+30+3 1+32+33=560 gales). Unfort unately. Ihere are prob lems thaI make ,, the size and de lay of large carry-Iookahead ,,, adders less attractive. Firs!. Ihe above analysis ,, ,, counts gates, bU I nO! gale inputs. whereas gale ,, tnpUIS belter lell us the number of lransistors ,, , needed . NOlice in Figure 6.58 that the gales keep : ~~:::::=:!""'-.J ,,, getting wl~er in higher stages. For example, stage , 3 has a 4- tnput OR gate and 4- inpul AND gate. ,,, wh tle slage 4 has a 5-inpul OR gate and 5-inpul ,, ~ ~~~~_~J AND gate as hi ghlighted in Figure 6.60. Siage 32 of a 32-bil carry-Iookahead adder wo uld have 33Figure 6.60 Gate size problem. input OR and AND gates, along wilh other large
-d
r _
equatio ns:
339
____ __ ___ _ _ _ _ _ ____ _ _ _
___ ____________________
gates. Since gates with more inpuls need mo;e transistors, Ihen in lerms of tran istors. the carry-Iookahead design is actuall y quite large. Furthermore, those huge gales would nO! have Ihe same delay as a 2-input AND or OR gale. Such huge gates are Iypically built u ing a tree of smal ler gates. a we would ha\'e more gate-de lays.
Hierarchical Carry-Lcokahead Adders. Building a -I-bit or even -bil carrv-lookahead adde r using the previous sec lion·s method may b; reasonable with respecl I~ gale sizes. bUI larger carry- Iookahead adders begin to involve gates with 100 many inputs. We can build a larger adder by connecting smaller adders in a carry-ripple manner. For example. suppose we have 4-bil carry-Iookahead adders available. We can build a 16-bit adder by connecling four 4-bil carr)'-Iookahead adders. as sho\ n in Figure 6.61. Lf each 4-bil carry-look ahead adder had a -I-gale-delay. then the lotal dela) o f the l6-bit adder wou Id be 4~+4~ = 16 gale-delays. Compare this to the delay of a 16-bil :lIT) -ripple adder-if each fu ll-adder has a IWO gale-delay. then a 16-bil calTy-ripple adder would ba\e a delay of 16*2 = 3_ gate-delays. Thus. Ihe 16-bil adder built from ~ ur !lIT) -1
3-'0
6 Optimizations and Tradeoffs
6.4 Data path Component Tradeoffs
(Actually. careful observat ion of Figure 6.55 reveals that the carry-out of a four-bit carrylookahead adder would be generated in three gate-delays rat her than fo ur. resulting in even faster operation of the 16-bi t adde r built from four carry-Iookahead adders-but for simplicity. let's not look inside the compone nts for such detai led ti ming analysis.) Sixteen gatedelays is good. but can we do bener? Can we avoid having to wait fo r the carries to ripple from the lower-order 4-bit adders to the higher-order adders? bl l.bB
cout
s15-s12
a7a6a5a4
b7b6b5b4
a3a2al aO b3b2blbO
sll·s8
Figure 6.61 l6-bit adder implemented using fo ur 4-bit adders connected in a carry-ripple manner. In fact. avoidi ng the rippling is exactl y what we did in developing the 4-bit carry-lookahead adder itself. Th us. we can repeal Ihe Sallie cany- Iookahead plVcess all/side of the 4-bit adders. to quickly prov ide the carry-in value to the highe r-order 4-bit adders. To accomplis h this. we add another 4-bit carry-Iookahead logic block outside the four 4-bit adders. as shown in Figure 6.62. T he carry-Iookahead logic block has exactl y the same internal design as was shown in Figure 6.58(c). Notice that the lookahead logic needs propagate (P) and generate (G) signals from each adder block. Previously. each input block output the P and G signals j ust by ANDing and XORing the block's a i and bi input bits. However. in Figu re 6.62. each block is a 4-bit carry- Iookahead adder. We therefore must modify the internal desig n of a 4-bit carry- Iookahead adder to output P and G signals. so that those adde rs can be used with a second level carry-Iookahead generator. b11-b8
a7a6a5a4
b7b6b5b4
341
To understand these equ [' • ~olumn should e ual th ~ Ions, recall that propaga te meant that the o utp ut carry fo r a the COlumn) F qh e '"put carry of the column (hence propagau ng the carry through stage of the ~-:i: ~da~ to be the case for the carry in and carry out of a 4-bit adder, the first ' . er must propagate Its '"put carry to its output carry, the second sta"e must ropagate Its '"put ca t ' e [ othP d rry 0 Its output carry, and so on for the third and fou r stages n er wor S each internal . I . P3P2P1PO. ' propagate signa must be 1. hence the equation P that g enerate meant that the output carry of a column should be a 1 Likewi se • recall . . the first stage generates ( Ilence generating a carry of 1) . Generate should thus be 1 If G a carry ( 0) and all the higher stages propa"ate the carry through (P3P2Pl) yield' the term .P3P2P1GO . G enerate s houId also be" a 1 .If the second stage ge nerates ' a carry Lng a nd a ll hlgher stages propaga te the carry through, yie lding the te rm P3P2Gl. Likewise for the third stage, whose term is P3G2. Finall y, generate should be 1 if the founh stage generates a carry, represented as G3. ORing all four of these terms yields the equatio G - G3 + P3G2 + P3P2G1 + P3P2P1GO. n We ~ould then revise the 4-bit carry-Iookahead logic of Figure 6.58(c) to include two additIOnal gates in stage four, one AND gate to compute P - P3 P 2 P 1 PO. and one OR gate to compute G - G3 + P3G2 + P3P2G1 + P3P2P1GO (note that sta"e four a lready has AND gates fo r each term, so we need only add an O R gate to OR the ~erms). For conCiseness, we 0 11111 a fi gure showing these two new gates. We can introdu ce additional levels of 4-bit carry-lookahead gene rators to create even larger adders. Figure 6.63 illustrates a high-level view of a 32-bi t adder built using 32 SPG blo?ks and three levels of 4-bit carry-lookahead logic. otice that the carry-lookahead logiC form a tree. Total delay for the 32-bit adder is only two gate -delays fo r the
a3a2a l aO b3b2bl bO
Figure 6.62 l6-bit adder im plemented usi ng four CLA 4-bit adders and a second level of lookahead. Thus. le t\ extend the 4-bit carry-look ahead logic of Figure 6.58 to o utput P and G signals. The equations for the P and G outputs of a 4-bit carry-Iookahead adder can be written as follows : P - P3P2PIPO G - G3 + P3G2 + P3P2Gl + P3P2PIGO
Figure 6.63 Vicw of multilevel carry-lookahead. showing tree stru lure. \\ hi h erutbl with reaso nable numbers and sizes of gUles. En h level adds nly 1\\ gate-
fast
.
n
3~2
Optimization5 and TradeoH5
6.4 Oatapath Component TradeoHs
SPG blocks. and two ga te-delays for each level of can'y- Iookahead (CLA) logic. for a total of 2+2+2+2 = 8 gate-delays. (Actuall y. c loser exami nati on of gale delays within each component wo uld demo ns trate thm total de lay of the 32-bit adder is actuall y less than 8 ga te-delays.) Carry- Iookahead adders buill from mul tiple le ve ls of carry-lookahead logic are kn own as IIIlIltile,'el or hierarchical carry-Iookahead adders . In summary. the carry- Iookahead approac h res ulLs in faster add itions of large binary numbers (more than 8 bits or so) than a carry- ripple approach. at the ex pense of more gates. However. by c lever hie rarc hical design. the carry- Iookahead gate size is kept reasonable. Carr y-Select Adders AnOlher way to build a larger adder from smalle r adders is known as carry-select. Consider bui lding an 8-bit adde r from 4-bit adders. A ca rry-se lect approac h uses two 4-bit adders for the hi gh-ord e r four bits. whic h weve labe led H14 _ 1 a nd H14_0 in Figure 6.64. HN_ I assullles the calTy- in w ill be I. whi le HI4_0 aSSllllles the carry-i n wi ll be O. so both ge nerate s table o utput at the same time that LO.J ge nerates stab le o utput-after 4 gatede lays (ass uming the -I-bit adde r has a de lay o f four gate-dela ys). We use the L04 carryo ut value to se lect among H14_ 1 or HN _O. using a 5-bit-wide 2x I multiplexer-hence the tenll carry-selecl adder. a7a6a5a4
343
se lect. USing a multiplex h . er. t e appropnate adder for Nibble I. Nibble I '5 selected carryo ut would the n I wo uld fin all y sel;~t~~~ t:e app~opnate adder for Nibble2. Nibble2's se lected carry-out be 6 gate-dela 5 ~ N' ppropnate adder for Nibble3. The del ay of s uch a n adder would de lays for Nib~le3?: I, bblel . plus 2 gate-delays for Nibble2 ' election. plu 2 oateadders would hav se eCllon-for a total of on ly 10 gate-del ays. Cascading fo ur 4-bit select . e required 4+4+ 4+4 = 16 gates-delays. The peedup of the carryverSIOn over the cascaded version wo uld be 16 / 10 = 1.6. TOlal size would be 7*26 = 182 gates. plus the gates for the three 5-bit 2x I muxes. That 's • ca rry·lookahead prenyefficient size fo r prelly good speed. • multilevel . F'gure 6.65 illustrates the tradeoffs amo ng adder carry-lookahead . '" ~ deS igns. Carry-ripple is the smallest but ha the longest delay. Carry-Iookahead is the fastest but has • carry-select • carrythe largest size. Carry-select is a compromise ripple between the two. involvi ng some lookahead and delay some rippling. The choice of the most appropriate adde r for a des ign de pends on the speed and size constra tnts of the design. Figure 6.65 Adder tradeoff .
b7b6b5b4
Smaller Multiplier-Sequential (Shift-and-Add) Style a3a2al aO
b3b2bl bO
ci
An array-s tyle multiplier can be fast but may require a 101 of aa te Cor 'd b ' . . . ' e W I e- It\vldth I ' I' mu tiP lers. itke 32-blt mu lti pliers. In this section . we c reate a sequential I '· . t d f b" mu Ilplier ttlS ea 0 a com ttlallonal one. in order to reduce the size of the multiplier Th 'd . I '" . e I ea of a sequentla mult'piter IS to keep a running sum of the panial products and compute ea h pantal. product one at a time. rather than computing all the pani al produc t at once d UIll.llllll g
co 57565554
53525150
Figure 6.64 8-bil carry-seleci adde r implemented usi ng Ihree 4-bil adders. The de lay of a 2x I mu x is 2 ga te-delays. so the lota l de lay o f the 8-bit adde r is 4 gate-delay; for H14_ 1 a nd 1-114_0 to ge ne rate correCI sum bits (L04 executes in parallel). plu~ 2 ga te-delays for the mu x (w hose se lect line is read y after o nl y 3 gate-delays). for a tOlal of 6 ga te-delays. Compared w ith a carry- Iookahead imple me ntation usi ng two 4-bit adder~. wc've reduced the total de lay fro m 7 gale-de lays down to 6 gate-delays. The cost is one ex ira 4- bit adder. If a 4-bi t ca rry- Iookahead adder requires 26 ga tes. then lhe design with two
them.
an
Fi gure 6.66 provides an example of 4-bit multiplication. As ume we s tan with a runlltng of SUIll of 0000. Each step corresponds to a bit in the multiplier (the second number). In step I. we com pUle the partial product a 0110. which we add to the runnin a sum of 0000 to obtattl 00 II O. In step 2. we compute the panial product as 0 I 10. which we add to the propercolumns of the runmng sum of 00 11 0 to obtain 010010. In ste ' P . we compute the pantal product as 0000. which we add to the proper co lu f . L' k ' . runs 0 the runlltng sum. I 'eWlse for step 4. The fi nal runlltng sum is 00010010. whi h i correct product of 0110 and 0011. the
Step 1 0110 x 001 1 o000
I" 00 1 lO
~~ o0 t 10
Step 2 0110 x 00'1 r
x 0011
0 10 0 10
I" 00 1 0 0 1 0
~~ ~OOOO 0 10 0 10
Step 4 0110
Step 3 0110 x 0 0 11
00 1 00 1 0
(running Sum)
~ ~OOOO
(P8noalptOduct) 0 0 0 1 0 0 1 0 (new runlllng sum)
Figure 6.60 Multiplication done by generuling n p:u-tial produ'l for ~3l-h bil in the multipher (the number on the boIlOI11 ). nccul1lulatlllg the part ud products III a rulllllllg ~um.
344
Optimizations and Tradeoffs
6.5 Rll Oesign Optimizations and Tradeoffs
Computing each partial prod uct is easy-we just AN D the current multiplicand bit with every bit in the multiplier to obtain the partial product. So if the current multiplicand bit is 1. the AND creates a copy of the mult iplier as the partial product. If the current multiplicand bit is O. the AND creates 0 as the partial product. We need to de termine how to add each partial product to the proper columns of the running sum. Notice that the partial product should be moved to the left by one bit relative to the running sum afte r each step. We can look at this ano ther way-the running sum shou ld be moved to the right by one bit after each step. Look at the mu ltiplication illustration in Figure 6.66, unti l yo u "see" how the ru nning sum moves one bit to the right
mdld mrld mr3 mr2 mr1
mrO rsload rsclear
relative to each partial prod uct. Therefore. we can compute the running su m by in it ia lizi ng a n 8-bit register to O. In each step we add the partial product for the current multiplicand bi t to the leftmost four bits of the runni ng sum. and we shift the ru nning sum one bi t to the ri ght, shifting in a 0 into the leftmost bi t. So the run ni ng sum register should have a clear functi on, a parallel load function. and a shift right fu nction. A circu it showing the run ning sum reg ister and an adder to add each partial product to that register is shown in Figu re 6.67.
rsshr
start figure 6.68 FSM describing the conlroile r for the 4-bil multiplier. In terrnsof performa nce, the sequenti al multipl ier requires two cyc les per bit. plus I cycle for IOItlall zatlon. So a 4-bi t multiplier would require 9 cycles. while a 32-bit multiphe r would req uire 65 cycles. The longest regis ter-to-register delay is from a n!gister through the adder to a register. II we built the adder as a carry-Iookahead adder havin a o nl y 4 gate-delays, then the total delay for a 4-bit multiplication wou ld be 9 cycles * ;; gate-delays/cycle = 36 gate-delays. The tOlal delay for a 32-bi t multiplication would be 65 cycles.* 4 gate-delays/cycle = 260 gate-delays. While slow, notice that this multiplier's size IS qUIte good, requiring only an adder, a few registers, and a state-register and some contro l logic for the controller. For a 32-bit multiplier, the size would be far smaller than an a rray-style mu ltiplier requiring 3 1 adde rs. The mult iplier's design can be further improved by using a shifter in the datapath, but we omIt details of Ihat improved design.
multiplier
~
e
c: 8
345
mrld mr3
6.5 RTL DESIGN OPTIMIZATIONS AND TRADEOFFS
mr2
mr1 mrO
f----':rs:::foa:::d~---------_1load f----':rs:'c:;:le'7a"-r_ _ _ _ _ _ _ _ _--4~clear f---~ rs~s"h~ r _ _ _ _ _ _ _ _ _ __1 shr
In Chapter 5, we described the process of RTL design. While creating the datapath durina RTL design, there are several optimizations and tradeoffs that we might make to creat: smalle r or fas ter des igns.
running sum
register (8)
Pipelining start product f igure 6.67 Internal design of a 4-bit by 4-bit sequential mu lt iplier. The last thing we need to figu re o ut is how to con trol the circu it so that the circuit does the right thing during each tep-that 's exactly what conlro llers are for. Figure 6.68 hows a n FSM describing the desired controller behavior of o ur seque ntial multiplier.
Without pipelining: Microprocessors continue to become smaller. faster. a nd less expensive. and Ihus designers use microprocessors whenever possible to implement desired digital system behavior. But designers continue to c hoose 10 build thei r own digital circu its to implement desired behavior of ma ny digi tal systems. wi th the mai n reason for that c hoice being speed. One method of obtai ning speed from digital circuits is thro ugh the lise of pipelini ng. Pipelilling means to break a large tusk down into a sequence of stages
With pipelining:
I WI I W2 I W3 1 . Stage 1" §] §] Ej . Stage 2 " Figure 6.69
pplying pipelining [0
d~sh\\ashmg-washing and ~;ng
dIShes can be done
n WTentl) .
3~6
Optimizations and Tradeoffs
6.5 RTl Oesign Optimizations and Tradeoffs
such Ihat data moves th rough lhe stages like parts move Ihrough a factory assembl y line. Each stage produces output used by the next Slage, and all stages operale concurrently, resulting in beller performance than if data had to be fu ll y processed by the lask before new dala cou ld begi n being processed. An example of pi pelin ing is washing dishes wilh a friend. wilh you washing and your friend drying (Figure 6.69). You (the fi rsl slage) pick up a di sh (di sh I) and was h it. Ihen hand il to your friend (Ihe second stage). You pick up Ihe nexl dish (dish 2) and wash il cOl/currelltly 10 your friend drying dish I. You then wash di sh 3 while your frie nd drys dish 2. Di shwashing Ihi s way is nearly lwice as fasl as when wa shing and drying aren' t done concurrent ly.
Consider a syslem wi lh data inputs H. X, Y. and Z. lhal should repealedly outpullhe sum 5 = \, + X + Y + Z. We could impl emelll lhe syslem using an adder tree as shown in Figure 6.70(a). The fastesl cl ock for thi s design must not be faster lhan the longesl path bel wee n any pair of reg islers, known as lhe crilica l palh . There are four possible palhs from any regisler OUIPUl 10 any regisler inpul , and each path goes thro ugh two adders. If each adder has a delay of 2 ns. then each path is 2+2 4 ns long. Thus, the crilical path is 4 ns. and so the faslesl clock has a period of at leasl 4 ns, meaning a frequency of no more lhan I 14 ns = 250 MH z.
=
347
Latency versus Throughput The lerm "performance" ne d b fi F 670 b e s 10 e re ned due 10 lhe pipelining concept. NOlice in ~g~e . . () .lhallhe firsl result 5(0) doe n' t appear umil after IWO cycles. whereas I e eS lgn 111 FIgure 6.70(a) outputs Ihe fi rst res ull after only one cycle. Thal's because data mu st now pass lh ro uoh . c. <> an eX ira row of regISters. The term latency refer to delay . . lor new II1pUl dala 10 res ult · B '. 111 new OUIPUI data. Lalency IS one kll1d of performance oth deSIgns 111 Ihe fi gure have a lalency of 4 ns. Figure 6.70(b) also hows that a ne~ value fo r 5 appears every 2 ns, versus every 4 ns fo r Ihe design in Figure 6.70(a). The term throughput refers 10 the rale at whi ch new dala can be input to lhe sy tern and slm.ll arly, lhe rale al whi ch new oUlpulS appear from Ihe syslem. The th roughpUl ;f the deSIgn In Fl gur.e 6.70(a) IS I sa mple every 4 ns, while lhe lhroughpul of lhe desion in ~gure 6. 70(b) I I sa mple eve ry 2 ns. Thus. we can more precisely describe the p:rforance Improvemenl of our plpehned de ign as hav ing doubled the throughpllt of lhe deSIgn.
EXAMPLE 6.20
Pipeline d FIR filler Recall the 100-lap FIR fi lter from Example 5.8. We estimated that implcmcnl31ion on a microprocessor would req uire 4000 ns, while a custom di caital circuit implementati on would requ ire only 34 115. That custom digi tal circ uit utili zed an adder trce, wi th
elk
elk
So mininum clock
~~~~O_~!~~_~~ elk - 1 L - - i L
S~ (a )
S(O)
~
* ~
So mininum clock period is 2 ns ,-----,
elk~
S~ (b)
Figure 6.70 Nonpipelined versus pipelined dmapalhs: (a) four regisler-Io-regisler palhs of 4 ns each, so longe'l palh is 4 n . meani ng minimum clock period is 4 ns. or 114 ns = 250 MHz, (b) six
seven levels of adders-50 addilions. Ihen 25. then 13 (roughly), then 7. Ihen 4, Ihen 2. then I. The IOlal delay was 20 ns (for Ihe multiplier) plu seven adderdelays (7*2ns= 14ns), for a lotal delay of 34 ns. We can funher improve Ihe Ihroughpul of Ihat fi lter using pipel ining. NOlicing Ihal Ihe multipliers' delay of 20 ns is roughly equal 10 Ihe adder lree delay of 14 ns, we might decide to insen pipeline registers (50 of them since there are 50 mullipliers feed ing into 50
N Q)
0>
'"
;;;
adders at Ihe lOp of the adder tree) belween Ihe multipliers and adder tree. resulling in dividing the compu tation task into two stages. as shown in Figure 6.71. Those pipeline regislers shonen the critical path from 34 ns down to only 20 ns. mean ing we can clock the ci rcuit faster and hence improve the throughput.
Figure 6.71 Pipelined FIR filter.
rcgisler-to-regi ster paths of 2 ns each, so longest palh is 2 ns, meaning mini mum clock period of
The Ihroughpul speedup of Ihe unpipelined design
2 "', or 112 ns = 500 MHz.
co m par~d t~ the mi c.rop~ocessor i l1lpl emcntali~n was. 4000/3.4. ;;: 117. while
the throughput speedup
of Ihe plpehned deSIgn IS 4000/20 = 200. QUJle a nice nddJllOnnl speedup for jusl insening orne Figure 6.70(b) shows a pi pelined version o f lhis des ign. We merely add regislers belween lhe fi"l and second row of adde rs. Sin ce Ihe purpose of lhese registers is solely relaled to pipelini ng, lhey are know n as pipelil/e registers. though lheir internal des ign is Ihe sa me as any ol her register. The compul atio ns bel ween pipeline regislers are known a, stages . By inserting lhose regi sters and lh us c reating a lwo-slage pipeline, we've reduced Ihe critical palh from 4 ns dow n 10 on ly 2 ns. and so the fastesl clock has a period of al leasl 2 n,. mea ni ng a freque ncy of no more Ihan 112 ns = 500 MHz. In olher words. jusl by inserting lhose pipeline regi lers. we've doubled the perfo rmollce of our de,ign!
registers! Although we could pi peline the adder tree also, that would not gain u higher throughput. since the multiplier stage would still represent the critical path. \ Ve call' t cI k a pipelined ~)stem an\ fas ler than the longes t stage. since otherwise that stage would fail to load COrre't \aJues into th~ stage's outpu t pipeline registers . The I.Hency of the nonpipclined design is one cycle of 34 ns. or 34 n:-. totai. The latenc~ of the pipclincd design is two cycles of 20 ns. or 40 ns total. Thus. we ~ee IhJt pi~lining impro\~s the throughput at the expense of hHt:n y.
J.l8
6 Optimizations and Tradeoffs
6.5 RTL Desig n Optimizations and Tradeoffs
Concurrency A key reason for de igning a c ustom digi ta l c ircuil , ralher than wri ling software that exec utes on a micro processor. is 10 ac hieve improved performance. A common method of ac hieving perfomlance in a custom dig ital circ uil is th rough conc urre ncy. COllcurrellcy in digital design means to divide a las k into several independent su bpans, and then to execule those subpan s simultaneo usly. As an ana logy, if we have a stac k of 200 dishes to wash. we mighl di vide the slack into 10 s ubslac ks of 20 di shes each, and then give 10 of ou r neighbors each a subsl3ck. Those neighbors simultaneo usly go home, wash and dry their respecti ve substacks, and return 10 us the ir compleled dishes. We wou ld get a ten times speedup in dishwas hing (ignoring Ihe time to di vide the slack and move substacks from home to ho me). We have used conc urre ncy in several examples already. For example, the FIR filter datapalh of Figure 5.38 had three multipliers executin g conc urre ntl y. LeI's use conc urren cy to creale a fasler ve rsion of an earlier example.
EXAMPLE 6.21
Sum-of-absolute-difference component with concurrency
349
The data path consists of 16 b . su tractors operating concurrentl y on the 16 pixels of a row. followed by 16 ab olute I ue res ult ge ts added 'thvalh components. The 16 result ing differences feed into an adder tree, whose WI . e present sum for w 'f b k '
pares its COunter i with 16 since . n Ing ac. Into the sum register. The datapath comdifference between rows 16' . there are 16 rows In a block, and so we must compute the
ences of each row and th ~'m~s. The contro lling FSM loops 16 times to accumulate the differ.' en oa s the final result into the register sad reg. whkh connects to the SAD component s output sad. . In
Exa~ple 5.:, we esti mated that a software solution would require about six c des
r '
i~;6c~;i:nson. Sillce there are 256 pixels in a 16x l6 block, the software would r~uire is6~~~ J
s to compare a pmr of blocks. Our SAD circui t with concurrency instead requires only 1
~y~ e It~:lom~~e ea~h row of 16 pixels. which the circuit must do 16 times for a block resulting in ny = . eye es. Thus. the SAD circuit's speedup over software is 1536 I 16 =' 96. In other words, the .relatlvely Simple SAD Circuit using concurrency runs nearly 100 times faster than a soft ware solulion. Thm son of speedup eventually translates to beller qu ality digitized video fro~ whatever Video appliance we are designing.
Pipelining and concurrency can be combined h' to ac teve even greater performance improvements.
In Example 5.7. we designed a custom circuit for a sum-of-absolute-difference (SAD) component, and we estimated that component to be three times faster than a so ftware-an-m icroprocessor solution. We
can do even bener. Notice that comparing one pair of corresponding pixels of two frames is independent of compari ng another pair. Thus, such comparisons are an ideal candidate for concurrency.
We firsl need 10 be able 10 read the pixels concurrentl y. We can do this by redesigni ng the block memories A and B. whic h earlier were designed as 256-byte memories. Instead, let's design them as 16 word memories. where each word is 16 bytes (the total is still 256 bytes). Thus, each memory read corresponds to reading an entire pi xel row of a l 6x 16 block. We can then concurrently determine the differences among all 16 pairs of pi xels from A and B. Figure 6.72 shows a
new data path and controller FSM for a more concurrent SAD component. AO 80 Al 81 A14 814 A15 815
Component Allocation When the same operation is used in two different states of a hi gh-level state machine, we can choose to ell her tnstanUale two functional units. one for each s tate. or one functional uOJt: whtch Will be shared .among the two states. For example , Figure 6.73 shows a poruon of a state machtne with IWO states . oper. . . ' A and B, that each ha ve a mu I' ttp li catton auon. We can choose 10 use IWO dlSttnct multipliers as shown 'tn F'tgure 673( . a) (we " aSS ume the t vanables represent regtsters). The figure also shows the control si !ffials that wou ld be sel tn each Slale of the FSM contrOlling thaI datapa th. with the t 1 reoi;ter bein2 loaded tn the first state (tll d-I), and the t4 register beino 10 d d ' th e (t4l d= I) . " a e to e second state
"0---8
t = t2 • 13 14 = t5 • t6 F5M-A: (tlld=l) 8: (t4Id=1)
iii
¥¥
=1 ~2
d i ll16 - -A8_rd=1 53 sum Id=1 i Ino; l 54
sad_regJd=l
.~ .,
e2mul e1 mul
(8)
ConI roller
Figure 6.73 Two different component allocations: (a) two multipliers. (b) one multiplier (c) the one multiplier allocation represents a tradeoff of smaller size for slightly more delay. .
Dalapalh sad
Ftgure 6.72 SAD datapalh using concurrency fo r speed. along with Ihe contro ller FSM .
However. because a slate machine can ' t be. in. IWO s tates at the ame time_ then we know that Ihe FSM wtll perform only one multtphcation at a time. 0 we an
350
TI,e
6.5 RTl Design Optimizations and Tradeofts
Optimizations and Tradeofts
remlS
"opu(I!or" {/rid "oper-arion"
refers 10 belial'ior; like addition or lIIuttiplicatioll, TI,e/enll "compolllfli/"
(aka 'jimcriollal
unit") refers 10 hard\\'ore, like (III
adder or (I multiplier.
a 101 of gates. A datapath wi th on ly one multipli er appears in Figure 6.73(b). In each state of the state machine. the comrolle r FSM wo uld confi gure the multipl exer select lines to pass the appropriate operands through to the multiplie r. as well as loadin g the appropriate destination register as before. So in the first state A. the FSM wo uld set the select line for the le ft Illultiplexer to 0 to le t t2 pass through (s 1=0) and wo ul d set the select line for the righ t multi plexer to 0 to le t t3 pass through ( S r=O). in addition to selling tll d=l to load the result of the mutliplicati on in to the t 1 reg iste r. Likew ise. the FSM in state B sets the muxes to pass t5 and t6 . and loads t4. Fi gure 6.73(c) illustrates that the one-multiplier design wo uld have smaller size. at the expense perhaps of slightl y more de lay due to the multiplexers. A component library mi ght consist of numerous different functional units that could pOlenrially imple ment a desired operation- for a multipli cation. there may be several mu lti pl ie r components: MULl might be very fas t but large. while MUL2 might be very small but slow, and MUL3 ma y be somewhere in between. There may also be fast but large adders. small but slow adders. and several choices in between. Furthermore. some components might support multiple operations. like an adder/s ubtractor component. or an ALU. C hoosing a panicu lar set of fu nction al units to implement a set of operations is kn own as compoll ellt allocatioll . Automated RTL design tools conside r dozens or hundreds of possible component a llocations to find the best ones that represent a good tradeoff among size and performance.
Of course the tas ks of co . demo If we ail ocate onl y one mponent allocallon and ope rator binding are interdepencomponent. If we allocate tw component, then all operators mu t be bound to that allocate many components. t~e~o:~~~:~t% then we have some choices in binding. If we will perform allocation and binding s· I any mlore bllldlllg chOIces. Thus. some tools Imu taneous y, or the tools will iterate a th two tasks. TOg,ether. component allocati on and operator binding are sometimes r~~:~d t e as reSOurce S IQrll1g . 0
Operator Scheduling Given a high-level state machine, we may in troduce add lliona '. I sta tes to enable u to create a sma II er datapath. For example consider the h'gh-I I '.. 675( ) Th h' • I eve state machine III Fl oure . a . e state mac lIle has three states. with State B having rwo multipl ications. Since
'"0---0--0
Operator Binding Gi ve n an allocation of components. we still have to choose whic h operations to map to which components. For example. Fi gure 6.74 shows three multiplication operations. one in state A, one in state B, and one in state C. Figure 6.74(a) shows one possible componen t bind ing to two multipli ers. resulting in two multiplexers. Figure 6.74(b) shows an alternative binding to two multipliers. whi ch results in onl y o ne multipl exer, since the same operand (t3) is fed to the same multiplier MULA in two differe nt states and thus that mUltip lier's input doesn' t require a mu x. Thus. the second binding results in fewer
351
gates. wi th no performance loss . . . - an opuml za uon. as shown in Figure 6.74(c). ote that that bindin o not onl y maps operators to components. but a lso chooses wh ich operand to map to which co d t3 mponent IIlput · If we had Figure 6.74(b). the n MULA w • mappe to the left o perand of MULA in M " ould have reqUi red two muxes rathe r th an just one . I . applllg a give n set of operations to a operator billdillg. Automated to I . II partlcu ar component allocation is known as given component allocation. 0 s typlca y ex plore hundreds of different bindings for a
(some tl = t2 • t3 operat ions) 14 = 15 • t6
(some operations)
(some operations)
11 = t2 • 13
~
t4 = 15 • 16 _______ _
(some operations)
3-state schedule
•
•
4-slate schedule (a)
delay (e)
t4 = t5 \\t6
t5
t~,~,~~/ t3
~ t8~\ (f 6 f 3
Figure 6.75 Schedu ling: (a) initial 3-state schedute requires two muttipliers. (h) new 4-smte schedule requires onl y one multiplier. (c) new schedule trades off size for delay (extra late). • Binding 1 • Binding 2
sl - T ii f s r
~~~,
(a)
Figure 6.74 Two different operator bindings: (a) binding I uses two muxe., (b) binding 2 uses only one mu x. (c) binding 2 represents an optimization compared 10 binding I .
those two multi plications occur . be a . . in the .same state. and we know th a t eac h state Will slllg ie clock cycle. then we wIll need two mUltipliers (at least) in the datapath to u the two Slltlultaneous multiplications III state B. But what if we 0 n Iy h ave enouoh ppon . . Oates for o ne muluplier? In that case .. we can reschedule the operations so that there i " at 7no t onl y one multiplication needed III anyo ne state. as in Figure 6.75(b). Thus. when we allocate compone nts. we need ? nl y allocate one multiplie r as hown. a nd as was also done in Figure 6.73(b). The result IS a smaller but slower destgn. a illustrated in Fioure 6 That schedulin g example a sumed that the computation of t4 uld no t be moved '" ). t . Sl3te A or state C. perhaps because .those states already used a multiplier. r perha beenu t 5 and t 6 were not ready yet III state A. and the new re ult in t4 \\ as no ed0 d P se III ' tate C.
352
Optimizations and Tradeoffs 6.5 RlL Design Optimizations and Tradeoffs Convening a computation fro m occurring concurrent ly in one state to occurring across several states is known as serializing a computation. Of course, the inverse resched uling is also possible. Suppose we staned with the high-level state machine of Figure 6.75(b). If we have plenty of gates avai lable and want to improve our design's perfomlance, we might reschedule the operations such that we merge the operations of state B2 and B into the one state B, as in Figure 6.75(a). The result is a faster but larger design. requiri ng two multipliers instead of one. Generally. introduc ing or merging states, and assigning operations to those states, is a task known as operator scheduling. You may have noticed that operator scheduling is interdependent with component allocation. which yo u may recall was interdependent with operator binding. Thus, the tasks of schedu ling, allocation , and binding are all interdependent. Modem tools may combine the tasks somewhat. andlor may iterate among the tasks several times, in search of good designs.
EXAMPLE 6.22
353
A dalapalh for this Slate h' . h . . mac Ine IS s own III Figure 6.77. The data path requires only one mul. I' d up Jer an one adder beca th . . . . . use erc IS at r:nOS( one multl~hc.atl on and one addition in any given state in Figure 6.76. The' panlcular configurallon of Ihe multlpher. adder. and register in Figure 6.77 is
ex tremely .common In single p~ocessing circuits. and is generally known as a multiply.accumulaJe (MAC) unll. The dalapalh multIplexes the inputs 10 the MAC unit.
Smaller FIR filter using ope rator sc heduling Consider the 3-lap FIR filter of Example 5.8. That design had no controller. meaning the high-level state machine actually had just one state containing aU the datapath actions. as shown in Figure 6.76(a). We could reduce Ihe size of the datapath by scheduling the operations across several stales. such that at most one multiplication and one addition occurs per state. as shown in Figure 6.76(b).
The first stale loads the x registers with samples-note that the ordering of those actions nextla the state doesn '( matter si nce all the actions occur simultaneously. That state also clears a new register named sum. which
~ve
had to introduce to keep track of the intermediate tap sums to be compUled
in the laler Slales. The second state compules Ihe firsl lap of Ihe filter resu lt. the neXI stale computes the second tap. and the next Slate computes the third lap. The laSl state OUlputs the result, and then
Figure 6.77 Serial FIR filter datapath. The components in Ihe dashed box comprise whal is known as a multiply-accumulale (MAC) component.
the state machine returns to the first state again. Inpuls: X (N bits) Oulpuls: Y (N bits) Local registers:
xtO. xtt . xt2 (N bits) xtO =X xt1 = xto xt2 = xt1 Y = xtO' cO + xt1 ' c1 + xt2· c2
W 51
Inputs: X (N bits) Outputs: Y (N bits) Local registers:
xtO. xt1, xt2. sum (N bits) sum =0 xto = X xt1 = xtO xt2 = xt 1 sum = sum + xtO· cO
(a)
sum = sum + xt' · cl
One fu nher difference belween this datapalh and the concurrent datapath of Example 5.8 is Ihat Ihis datapath has load lines on the XregiSlers and on yreg. The conCUrrent design loaded those registers every clock cycle. but Ihe serial design onl y loads those registe rs during particular tatesother Slates compu te intermediate results.
We estimated Ihe performance of the concurrent design of Example 5.8 assuming I os per gate. 2 ns per adder, and 20 ns per multiplier. The design had a critical path of 20 ns for the multiplier aod then 4 ns for two adders In senes, for a total of 24 ns. That was al 0 the time between new results being laken in al tlle inputs and generated al the output: 24 ns. Using the more precise performance measures of lalency and throughput defined in Section 6.5. the concurrent design has a lmeney of 24 ns (delay from inpul 10 OUlput), and a throughput of I sample every 24 os. The serial d iro has a critical palh equnl to Ihe delay through a mux. multiplier, and adder. Assuming two gate-
Figure 6.76 High-level state machine for 3-tap FIR filter: (a) original one-state machine, (b) fi ve-stale machine with at moSl one add and one multiply per state. We ignore the writing of the constant registers (c O. c 1. c 2) for simplicity in the example.
sum = sum + xt2·c2
Y = sum (b)
we look at an FIR fi lter with more laps. We estimated the latency of a concurrent lOO-tap FIR filter in Sectioll 5.3. after Example 5.8 to be 34 ns (the delay I grealer than the concurrent 3-tap filter becau Ihe lOO-tap fi lter needs an adder. ,:"e). The senal desIgn would till have a _4 os ritical path. but would require 102 states (I to lIuuahze, 100 10 compute the taps. and I to oUlput). for a lateOC) f 102 • 24 ns =2448 liS. Thus. Ihe latency speedup of the concurrent design would be ~44 1 34 = _. We should also consider the size difference between the serial and ncurrent design . Let's ass ume for illustralive purposes Ihat an adder reqUIres nppro"matel) 500 gates and a multiplier
35-1
Optimizations and Tradeoffs
6.6 More on Optimizations and Tradeoffs
require ... 5000 gates. The se ria l design' s o ne lllulti~l ic: and one .ad~ler wou ld thu s require only 55?O ~at~!! . For a 3-tap FIR filter. the co ncurrent des ig n s 3 muillpi lers and 2 a~d~rs would r~q~lfe
5000*3 + 500*2 = 16.000 gates. For a IOO-tap FIR filt er. the concurre nt design s lOO multlphers alone \\Quld requ ire 100*5000;. 500.000 gates- I00 times more gates than the sen al deSign. Intu itive ly. these numbers make sense. A concurre nt dcsi2.n ror 100 lapS uses about 100 limes more gates (du e to usin~ 100 multi plie rs instead of just I) compared to a serial design. ye t achieves about 100 limes bc tl cr performa nce (due 10 compu ting 100 multiplicati ons concurrentl y rath er than computing one multiplication at a time). .
Depe ndin g on our pcrfonn ance need s and Size consLIaints. wc mi ght co nsidcr designs in betwee n the two ex tremes of se rial J nd co ncurren t. s uch as a design with two multipliers. whi ch would be roug hl y tw ice as big and tw ice as fasl as Ihe serial design. o r len multiplie rs. whi ch wou ld be roughly ten tim cs a~ big an d ten tim es as fast as th~ serial design. Fi!2 ure 6.78 illustr.1tcs tradeoffs among se n al and con;urrent~designs for an FIR filte r.
1
• concu rrent FIR
compromises senal
355
compared to ~oncurrent operations in a single state. Example 6.2 1 and Example 6.22 both ".Iust~ated senal versus concurrent computation tradeoffs. for an SAD circuit and an FIR CtrCUIl. respectively. Trading off between serial and concurrent computation is a fundamental concept spanmng all leve ls of dig ital design. As a general rule, a concurrent design is faster but larger, whde a sert al design is smaller but slower. Typicall y, numerous design options ex ist that span the ranae in between fully serial and fu lly concurrenl designs. <> Optimizations and Tradeoffs at Higher versus Lower Levels of Design
- FIR delay Figure 6.78 FIR design tradeoffs.
The above sections should have made it quite clear that RTL design presents an enormous ran2e of possible soluti ons to the designer. A single hi gh-level state machine can be impleme;ted as any of a huge variely of possible implementations thai differ tremendous ly in their sizes and performance. M oore versus M ealy Hi gh-Level State Machines
In the same way that we can create either a Moore or a Mealy FSM (see Section 6.3), we can create Moore or Mealy high -level state machines. In Ihe case of a high-level slate mach ine. a Moore Iype can only have actions associaled with the states, while a Mealy type can have actions as ociated with the transiti ons. As was the case wilh FSMs, a Mealy type may result in fewer stales. Mi xing Moore and Mea ly types IS commonly done in high-level state machines.
6.6 MORE ON OPTIMIZATIONS AND TRADEOFFS Serial versus Concurrent Computation
Having seen in this chapler numerous examp les of Iradeoff techniques at various levels of design, we can detect a common theme underl ying some of Ihose Iradeoffs. The common Iheme is that of serial ver us concurrent compulali on. Serial mea ns to perform lasks one at a lime. COllcurrellt means 10 perform lasks aI Ihe . ame lime. For example. in combinalional logic design , we can reduce logic size by faclOring out teml~. By factoring OUI lerms. we are essenti all y seriali zi ng the compulalion. by compUling the factored out terms firsl. and then combining Ihe resul ts with other terms. In datapalh componenl design, we can improve an adder's speed by compuling carries cancurrenlly. rather than wai ling for the carry to ripp le !.eri all y. In RTL design, we can schedule operation, across ,evera l . Iates . scri aliling Ihe opcralions 10 reduce size
As a general ru le, the.optimi zations and tradeoffs made at the higher Ie els of design may have a much greater tmpaci on design cri leria than the optimizations and tradeoffs made at lower levels of design. For example, imagine wanting to dri ve to a city on the other side of the country in as lill ie time as possible. We could reduce time by reduci ng the number of stops we make to eat. meaning we carry our own food in the car. We could also reduce time by reduci ng stops for fue l, meaning we use a car wi th the lonee t driviD e capacity per gas lank . Some people (nO! you. of course) might even consider driving faster than Ihe legal speed limit. But those are nO! Ihe fir t things you typically think of when trying to reduce driving time for a cross-country trip. The most important decision is which route to lake. One route might be 4000 miles long. while another route may be onl y 2000 miles. The high- level decision of which route to take has far more impact than all the lower- leve l decisions mentioned previously. Those lower-level decision are only really useful 10 us if we made the ri ght hi gh-level decision, and then if we till want to reduce the time furt her. In digi tal design, optimi zation/tradeoff deci sions at the higher levels (e.g., RTL decisions) may have a much larger impact than decisions at Ihe lower level (e.g .. datapath component decisions or multilevel logic decisions). For example, the RTL decision to bui ld a serial or concurrent FIR fi ller delay land (a) (Example 6.22) wi ll have a far (b) greater impacl on circuit size and Figure 6.79 Higher- \'e~us lower-level deci"ions: perfonnance than Ihe datapath- (n) higher-level decisions (denoted by the larger two component- level decision 10 use a circles) focus the design into a region. while 100\cr-lc\'c l carry-ripple or carry-Iookahead decisions tune withi n the region. (b) spotlighl analog~ . adder, or Ihe combi nalional-Iogiclevel decision to u e two-level or mullilevel logic. Those lower-level decision mereh rune the size and performance of Ihe higher-level decision. Figure 6.79(a) illustrates thi co-n cpt. An analogy might be a spotlight shining down on land. illu trated in Figure 6. 9(b>movin a Ihe spotlightlefl or right at high altitude (higher-level decisions) has a larger impact on which land region (possible solutions) is illuminated than d I wer-allitude mo\ emems (lower-level decisions).
_ _ _ -..,..,.._....--
--c'-
.__
__
~
__
356
6 Optimizations and Tradeoffs
6.6 More on Optimizations and Tradeoffs A faster algorithm for searching
Algorithm Selection When attempting to implement a system as a digital circuit , perhaps the highest-level design decision. havi ng therefore the most signficant impact on design cri teria like size. performance. power. etc .. is the selectio n of an algorithm . An algorithm is a set of steps thai solve a problem. The same prob lem can be solved by different algorithms. Algo· rithms for the same problem, when implemented as a d ig ital circuit, may result in tremendously different perfomlance andlor size. Some algorithms may simply be bener than mhers (optimization without much tradeoff). while other algorithms may represent tradeoffs between perfomlance, size, and other criteri a. Se lect ing an algorithm for a digi tal desig n problem is perhaps the highest level of design, and ca n have the biggest impact on desig n criteria. For example, earlier examples showed various implementations of an FIR filter. But Lhere are many other algorithms for fi ltering very different from the algorithm used in FIR. Some algori thms may provide hi gher-quality filteri ng at the expense of more required computation. others may provide lower quality but need less computation. We illustrate algori thm selection using an example.
EXAMPLE 6.23
Data compression using different table lookup algorithms We wish ( 0 compress data being sent over a long-distance computer network in order to achieve faster communicalion by sendi ng fewer bilS. One method for such compression is to use short codes for frequently appeari ng data values. For example, suppose each data item is 32 bits long. We mighl analyze the data we expect to send and fi nd the 256 most frequently appearing data values. We could then assign a unique g·bit code to each of lhase 256 values. When send ing data over the network, we first send a bit indicating whether we are about (0 send an encoded 8-bit data item or a raw 32-bit
data item-if the first bil is 1. that might mean encoded. and a a might mean raw. If all the data ilems being sent happen to be among the lOp 256 most frequent ones. then we'd be sending 9 bits per data item ( I bit indicating wheLher encoded, plus 8 bits of encoded data) raLher than 32 bits per data itcm-3 compression of nearly 4x, which could translate to about 4 limes fasler communication. We might design the encoder usi ng a 256-word memory that stores the 256 most frequent values in sorted 0: OxOOOOOOOO order. from smallest to largest in binary. The code would 1: OxOOOOOOO1 then be the address of Lhal word in the memory. Figure 6.80 2: OxOOOOOOOF shows sample contents of such a memory, in hexadecimal. 3: OxOOOOOOFF The contents vary depending on the commu nicating application s we are considering.
One algorithm for searching a list of values in a memory is known as linear search . Starting at address O. we compare each memory word's contents wi th the data item we are
96: 128:
OxOOOOOFOA OxOOOOFFAA
357
r f. . ~ ISla Items In a memory is known as binary search . We
first sort the list and th h ' en store l e list In the memo (\ . d I . we start in the middle of the memo . ry \Ie nee on y son once). To look up an Item.
the key. If the content's val ue is les ry. mealllng add ress 128. and compare that word'~ contents with s than 128. Ihen we know that the key. If 1\ eXists III the memory. must bc somcw here between 0 and 127 S and aga'ln com If h . 0 we go to the middle of that range, meaning address 64. pare.. h t e value 65- 127 So afl ' there is less th an the k·ey. we search 0 to 63; if greater. we search h k 'I' b cr cae companson. we decrease the remaining possible range of addresses in which t e ey les y one half. Halving 256 repeatedly can onl y be done 8 times' ?56 128 64 32 16 8 4. 2. I. In other words. after at most 8 o · . . .- . . . . . . to 1, meanin the ke can' be . c mpansons. w~ ve eIther seen the key, or shrunk the range . g y t found III the memory. Billary search is 256/8 = 32 times faster than
Im,car ~earch when the key does nO{ exist in the memory. and roughly th at much faster when the key eXIsts 10 the memory too. : ct binary search only requires a slightly smarter controller.
. We sec Ihat the chOice of the ri ght algorithm makes a big difference in performance for thiS example-m uch bigger a differe nce than determined by. say, the speed of the comparator belllg used.
Power Optimization Power is becoming an important design cri teria, both in high-end computing as well as in embedded computtng. The un it of power i watts , which represents the energy per second (I.e., Joules per second) .. ln high-end computi ng. like desktop PCs. servers, or video-game consoles. the chtps tnstde a computer consume a 101 of power. causing the chips to become very hoI. For example, a typical chip inside a PC may consume 60 wans-thiok abo ut touchtng a 60 wat! Itght bu lb (but don ' t actually touch one) to understand how bot that is. Designing low-power chi ps reduces the need for expensive chip cooling methods beyond si mple fans in hi gh-end computing, and also reduces the eleclriciry costs. which can be quite significant for companies operating large number of computers. In embedded computing, even simple cooling methods like fans are often not available-for example, your cell phone does not hav; a fan (if it did. people might find their tie or scarf getting stuck in that fan). Portable embedded devices might have chip that run at only I wa tt or less. FurthemlOre, portable devices typically get their energy from batteries, and Lhus low power chips are necessary to extend battery life-espe8 cially consideri ng the fact that batteries are not 0 energy improving fas t enough to keep pace with ~ demand increasing power consumption. By some mea- .S; sures. energy demand per chi p is doubling abo ut ~" every three years (going along with Moore' banery energy Law). Figure 6.8 1 plots such energy demands ,.,
"
look.ing for (known as the key), incrementing the addre", and ~ repeating unLil we find a match. at which point we treal the '"~ add res at which there was a match as the encoded value. If 255: OxFFFFOOOO c we get to address 255 and don't find a match. we will transmit :0 256x32 memory the raw data. The linear search algorithm is a slow way to search a sorted list in memory. The algorithm requires 256 reads and compares for data items that aren 't in the memory. Figure 6.80 Searching a sorted which may translate to 256 cycles. For data items that arc in memory for the key OxOOOOOFOA - linear search requi res 97 reads! the memory. we would require on average 128 reads. compares. binary search onl y 3.
. " .
"
compared to battery energy densities improving at their present rate of only about 8% per year. The increa ing gap shown translates to shorter battery lifetimes for a device like a cell phone. or translates to bigger batteries. The most popular IC technology today use CMOS transistors. and the biggest contributor to
~
~ 2
c
" 2001
03
05
07
Figure 6.81 Battery energy densit), is impro\'ing slo" er than the in reasing energ) demands of digital chips.
358
Optimizations and Tradeoffs
6.6 More on Optimizations and Tradeoffs
power consum pti on in CMOS is the switching of values from 0 to 1. The reason for this is thm wi res aren't perfect. having capaci tance (we don't put a capacitor there on purpose-it is simply a result of the fact that wi res aren 't perfect conductors of electricity). Switching the wire from 0 to 1 requires charg ing that capacilOr. Switching from 1 back to 0 causes that charge to be discharged to ground. That switching results in power being consumed. This power is known as dY ll amic power. since thi s power comes from the changing of signals (dynamic means changing). Dynam ic power consumption of a CMOS wire is proportional to the size of the capacitance (C) of the wire. multipli ed by the voltage (V) squared. multiplied by the freque ncy at which the wire switches (f), namely:
359
ri sing clock edge Preventi no the I k d fl' fl . Id' . o · C oc e ge from appearing keep the same values in the IP- ops. Yle . II1g the same net result-the register's COlllents don't change. ' th'at d'IgllaJ . desloners . . Clock gmll1g. IS not someth II1g ryplcally do themselves. Rather. modern sYlllhesls tools may aII ow us to speC .ify clock 0 . enable and disable u ing pecial commands 111 each state These t I . . . . 00 s must u e extreme cautIOn. becau e addin e a gate on delays the clock signa. ' I resulting ' .111 clock Signals . .111 different parts a . clock slonal . .0 . of the C" cull bell1g slightl y different from one another, an effect known as clock skew. The tools must perform carelul tim ing analysis to ensure that the clock skew doe not chanee overall C"CUIl behav ior. Furthermore, pUlling gates on a clock sional can reduce the sharpness of the clock cdoes and. so must . be done careFull y. somellmes 0 . . . • 0 ." uSll1g speCial gates. Nevertheless. the technique IS widely used by low-power tools in practice. We de monstrate clock gati ng with an example.
(equati on for CMOS dy nami c power consumption) where k is some conswn t. To compu te the dyna mic power of a circuit. we would add up the power computed by the above equation for every wire. Looki ng at the above equation. one can clearl y see that lowering the voltage will cause the grealC t reduction in dynamic power. because of the vo ltage having a quadratic (sq uared) contribution 10 dynamic power. Low-level circuit designers seek to reduce power by creating transistors that operate at the lowest vollage possible. 10 reduce the V term. and that have the smallest wire capacitance poss ible. to reduce the C term . Digital designers can therefore choose to uti lize gates that operate with a lower voltage. Unfort unate ly. lower voltage gates have a longer delay than hi gher voltage gates. resulting in a tradeo ff between power and performance. Another way 10 reduce the dynamic power consumed by a circuit is to reduce the circuit's clock frequency. which obviously reduces the f term for all the clock wires in the circuit. as we ll as for the many other wires that chan ge on each clock edge (like register wires and the logic connected to those registers' output s). But again. reducin g the clock Frequency slows performance. resul ting in a tradeoff between power and performance. The chief technica l officer at a major ch ip des ign company IOld me in 2004 that, for thei r company. " Power is enemy number one." The reason is that they had scaled their voltage down nearly as low as poss ible. yet are pUlling more transistors on each IC every year due to the shrinking of transistor sizes. meaning more wires switching. And capacitance i n't decreasi ng at the same rate as transistor sizes. The resull is that an Ie consumes more power as we put more transistors on the IC. which can result in problems due 10 100 much heat and due to fast banery energy consumption.
EXAMPLE 6.24
Serial FIR filter with clock gating to reduce power We designed a serial FIR fi lter in Example 6.22. A five-Slate state machine controlled
the dalapath. The state machine loaded the three X I registers only in me first slale. tale SI . and loaded Ihe y reg regisler only in the
last Slate. state 55. Yet. lhe design routed the clock signal 10 all four registers utilizing four wires. labeled n I-n4 in Figure 6.82(a). Notice from lhe liming diag~ at
the lOp or the figure Ihat n1-n4 change identicall y a the clock signal changes. and remember that every such change consumes dynamic power.
Clock Gating (Ad va nced Technique) Assumi ng the C and V term have been reduced to the ex tent possibl e using transistor-level de ign techniques. power can be reduced furt her by reduc ingf . the Freq uency at which wires swi tch. One method for reducing such power is known as clock gating. Clock ga/i/lg is the disabling of the clock signal in regions of the ch ip that we know are not computing anything at a given time. Clock gat ing aves power because a signifi cant percentage of the wires sw itching in a chip are the wires that distribute the clock to all the reg isters and flip-flopsperhaps 200/c-30% of the power consumption is due to the clock signal switching throughout the chip. Clock gati ng reduce f without slowing the clock frequency itself. In clock gating. the clock ~igna l is di sab led by A Ding the clock signal with an enable signal that is ~et in the ~la t e machine. Recall that a register with paralle l load internally reload, the ,ame va lue from the regi' ter', flip -fl ops back into the fl ip-flop on a
Figur.6.82 Clock gating: (n) the lock
-'rL
n4 _ _ _--' "--_ _--' '--_ _
j
signal switches e\ el) cycle n all the heJvily bolded \\ ires. but the \ t reQi ters are only loaded in state J.:J.IlO the Yreg~in SI31C 5-so mm·t of Iht.~ doc\... ~\\ Itchin2. is \\'Ilsled: (b) gnling the dock redu 's th~ ~\\'it hing on the lock. \\ In:,.
360
Optimiza tions and Tradeoffs
6.7 Produ ct Profi le: Digital Video Player/Recorder
Figure 6.S2(b) shows 0 design using clock gati ng. The controller gates th e clock to the xt registers by selling si lO a in all states bu t 51. Likewise. the controller gates the clock to the yreg register by scning 55 to 0 in all states but 55. Notice the significant dec rease in signal switching on Lhe clock's wires n} - n4. shown at the baLtom of Fig ure 6.82. Low-power gates o n noncritical paths at a ll gates are equa ll y ras t. E ngineers th at buil d gates rrom tra nsistors can make a gate faster by increasing the s ize of the gate's tra ns istors, o r by operating the gate at a higher voltage, or by any or several o ther means. Thus, one two-i npu t AND gate m ight have a I ns de lay, w hile another two- in put AND gate might have a 2 ns de lay. • hig h-power gates T he laner AND may consume less power, due 10 its
smaller size or lower voltage. If we want 10 reduce the power consumed by a circui t, we can build the e nti re circu it using lowpower gates 10 achieve low power a t the expense of slower perfomlance. as ill ustrated in Figure 6.83. Altematively. we can put low-power ga tes o nl y on the no ncritical paths. suc h that we lengthen th ose paths 10 have delays no longer th an the c ri tica l pat h, as shown in the fo llowi ng example. EXAMPLE 6.25
Q)
~
• low-power gates
on noncritical path
a.
low-power • gates
Figure 6.83 Using low- power gates
Reducing noncritical path power with multilevel logic In Example 6. 12. we reduced the size of a noncriti cal pat h by usi ng multilevel logic. In this example. we instead reduce the power co nsumed by the noncritical path by usin g low-power gales. A ssume that nonnal ga les have a delay of I ns and consume I nanowatt of power, and that lowpower gates have a delay of 2 ns and consume 0.5 nanowatts of power.
The left side of Figure 6.84 shows the sa me circuit from Example 6. 12. havi ng a critical path of 3 gate-delays. Assume that all the gates are nom1a l gates, meani ng the critical path delay is 3 ns, and th e IOtaI power consumption is 5 nanowallS.
d
e
Figure 6.84 Using low-power ga tes on noncritical paths. Numbers inside a gate represent the gate's delay in nanoseconds, and the gate's power consumplion in nanowallS.
The bottom two AND gates lie on two noncritical paths having delays of only 2 ns. We can thus replace th ose AND gates by low- power A D gates. The res ult is that the two paths' delays lengthen to 3 ns. so become equal to the criti cal path delay, but not longer. The result is also that th. total power becomes onl y 4 nanowatts instead of 5 nanowatts (a 20% reduction).
361
6.7 PRODUCT PROFILE: DIG ITAL VIDEO PLAYER/RECORDER Digital Video Overview In the 1990s, the di git izat ion of video became practical due to faster, s maller, and lowerpower dig ital circuit . Previously, video was large ly captu red, stored, and played using a nalog methods. Di gi tized video works by samp li ng an a nalog video signal and transfo rmtn g the samples to digital values. Such d igitizati o n is simil ar to the audio digitization exa mple fro m Figure 1. 1, but with some add itional wo rk. A video is ac tu all y a series of qui ckl y displayed still pictures, known as frames, as shown in Figure 6.85(a). One second of video might consist of abo ut 30 frames-the human eyes and brain see such a rapid sequence or frames as a (a) smooth, conti nuo us video. A d igital display may be di vided into several hund red th ousand tiny "picture ele ments," or pixels. A typical size m ig ht be abou t 720 across and 480 down. For each fra me, a d igitized sam ple 1 P P captures several values fo r each pixel, li ke the intensity of the red, blue, and (b) green compo nents of the light at th at Figure 6.85 Video: (a) is a series of pictures. or pi xel, convening analog measure ments frames, with muc h interframe redundancy. (b) of th ose intensities into di gital num bers. can be constructed from I (intra) frames and P The res ult is the represe ntation of a digi(predicted) frames. shown with relative bit ti zed frame as a (large) series of as and encoding sizes. Is, and the representat ion of a dig itized video as a large seri es of digitized frames. Digitized video can be transmined. stored. re played, and copied with much hig her quality than analog video. Funhennore. digitized video can be compressed, resulti ng possi bly in higher quality video than analog video transmitted or sto red using the same medi um.
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-.
•
DVD-One Form of Digital Video Storage Di g ital video d iscs (also known as d igital versatile discs). or DVD . store video in a di gi tal form at. First sold in 1997. DVDs replaced the analog video technology known as VHS tape. DVD players appear in ho me e ntenainment centers, personal computers. automobi les (es peciall y fa mil y-orien ted vehic les). and even as stand-alone portable units. In 200 I , consum er electro ni c companies introduced the first DVD recorder to market. a llowing ind ividuals to record television shows to special recondable DVD . The popularity of DVDs compared to the prev iously popular analog-based VH technology terns from several advantages. including bener q uality video. no deterioration in "ideo quaJit) over time. and the abili ty 10 jump directly to panicular pan in a ideo without having to seq uentially forward or rewind.
-- - - -- -== .".- -.
-----
~-
-
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Optimizations and Tradeoffs 6.7 Product Profile: Digital Video PlayerlRecorder DVDs store large amOu11ls of data on a thin reflective layer of metal. Although the metal layer with in a DVD looks fl at From our perspecti ve. there are actu ally billions of tiny pi ts on the meta l layer that store the data. These pits, or lack of pits (called lallds), store the binary data on the DVD. Figure 6.86 shows how a DVD player reads the information off a DVD . Using a very prec ise laser. the laser's light is focu sed onto the metal layer withi n the DVD . The metal layer refl ects the light onto an optical sensor that can detect iF the light is reflected off of a pit or a land . By detecting the difFerent regions, the optical sensor creates a stream of binary values as it reads the DVD. Optical Pickup
... 010 100101 100
---_.-/ figure 6.86 How a DVD player reads a DVD. The DVD player's optical pickup element shines a laser on the surface of the DVD. The DVD refleclS the laser back to an optical sensor. and the optical sensor use the intensity of the reflected laser to output the sequence of Os and Is stored on lhe DVD. A video decoder circuit convens lhe bi nary data
(0
a sequence of frames that humans
interpret as a moving picture.
The DVD's binary data is organized into a eries of tracks that spiral outward from the center of the DVD. As the DVD player is reading the data, the laser and optical sensor must slowly move outward from the center of the DVD to the outer edge. [f a DVD is dual-layered. the data on the disk 's second layer is stored in a spiral that moves from the disk's outer to inner edge. The motivation for the second layer'S reverse spiral is to prevent the laser and optical sensor from need ing to reposition itse lf to the center of the disk after focusing on the second layer during a layer change. (You may have noticed a DVD pause momentarily at a certain point in a movie during a layer change.) A single-layer single-sided DVD can store 4.7 gigabytes of data (meaning 37.6 gigabits), but that amoun t i not enough for a movie unl ess the dala is compressed. Consider a video wi th a resolution of 720 pixels by 480 pixels, using 24 bi ts of information per pixel. and di splayed at 30 frames per second. One frame would require 720*480*24 = 8,294.400 bits. or abou t 8 Mbits. One second of video. or 30 frames. would req uire 30*8.294.400 = 248,832.000 bits, or about 250 Mbits. A 100-mi nute movie would thus require abou t 250 Mbits/sec · 100 min • 60 seclmin = 1500 Gbit . But a DVD can only hold 37.6 Gbits. To 'tore a movie. a DVD must ~tore the video in a compressed format.
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A DVD is only one of many different digital video storage media. Digitized video may be stored on any storage media capable of storing Os and 1S in some form. such as on tape (~sed rn many digital video cameras). on a fl ash memory (used in digital cameras and cell pones wtth Video recordlllg capability), on a CD. or on a computer hard drive. All such med ia are typically still quite limited and thus require compression methods.
MPEG-2 Video Encoding-Sending Frame Differences Using 1-, po, and B-Frames MPEG:2 video compression was defined and standardized by the Motion Picture Expert Group 111 1994 (as an Improvement over the 1992 MPEG- I standard). and is used in DVDs digi tal television, and numerous other digital video devices. MPEG-2 compression ratio~ range from 30: I to 100:1. or more. The compression ratio i determine by dividing the number of btts of the dtgtttzed Video before compression, by the number of bits after compression. So if a digitized video requires 400 gigabytes uncompressed but only 4 gioabyles compressed. the compression ratio would be 400/4 = 100: I. ate that packing 1500 Gbits of a movie into 37.6 Obits would require a compression ratio of 1500 Gbitsl37.6 Gbits = 40: I. . The key observation leading to MPEG-2's compression method is that typically very htlle dtfference eXlsts between two successive frames in a video--in other words. video typically has much interframeredu ndancy. For example. a frame may consist of a person standlllg 111 front of a mOuntalll, as in Figure 6.85(a). The next frame (which represents perhaps 1/30 th of a second later) may be almost identi ca l to the previous frame, except that the person's mouth has opened slightl y. The next frame may till be almost identical. with the person's mouth opened lightly more. And so on. Therefore, MPEG-2 does not merely encode each frame a a distinct picture. Instead. to take advantage of the interframe redundancy, MPEG-2 may choose to encode each frame as one of the fo llowing: An I-j rome, or Intracoded frame. i a complete picture. A P-jrame, or Predicted frame, is a frame that merely describes the difference between the current frame and the previous frame. Thu . to derive the picture for this frame, one must combine the P-frame with the previous frame. For example, Figure 6.85(b) shows P-frames that contain only the differences from the previous frame. A P-frame will obviou Iy require fewer bit than an I-frame. Example frame sizes might be about 8 Mbits for an I-frame. but only 2 Mbit for a P-frame. Thu . instead of representing 30 frames as 30 complete pictures (30 [-fran,es). a compre ion method might represent those frames using the following equence of frames: I P P P P P P P P P P P P P PIP P P P P P P P P P P P P P. The compression ratio in this example would thus be 8 Mbits * 30 I (2 • 8 Mbtts + 28 • 2 Mbit ) = 240 I 72 = 3. ': 1. Obviou Iv. a picture created by combined predicted frames with a previous frame won't be a perf~t representation of the ongrnal ptcture, espectally tf there is a lot of motion in the video. MPEG-2 thu s trades off some quality for compression. To achieve even further reduction . MPEG-2 uses a third frame type : • a B-jrome. or Bidirectional predicted frame. is a frame that can store difference from previous and jl/Illm frames. B-frames can thus be even smaller than P-frames. just I Mbit.
n example B-frame size might be
31H
6 Optimizations and Tradeoffs
EXAMPLE 6.26
Computing compression ratios involving 1-, P- and B-frames Assume a 30-frame MPEG -2 sequence has Ihe following frame sequence: I B B P B B P B B P B B P B B I B B P B B P B B P B B P B B. Assume average frame sizes of 8 Mbils for I-frames. 2 MbilS for P-framl?s. and I Mbit for B-frames. Compute the compression raLio. The compression ralio in Ihis example would be 8 Mbils • 30 I (2 • 8 Mbils + 8 • 2 MbilS + 20' I Mbils) =240 I 52 =~.6: I. The example sequence of frames is in faci fairly Iypical for MPEG-2 video. wilh I-frames occ urring abou t every 12- 15 frame s.
MPEG-2 video e ncoders may seek 10 c reate abo ut 30 frames per second. With hundreds of Ihousands of pixels per frame that must be compared with another frame, MPEG-2 encoding requires a large amo unt of computation to determine which frames shou ld be I. P. and B. and what should be the values for the P- and B-frames. Furthermore. much of tha t computation will consist of the sallie computation performed between corresponding regions of two frames. Thus, many MPEG-2 encoders utilize custom digilal ci rcuits to parallelize those computations at the expense of more hardware size. For example. Example 6.2 1 built a sum-of-absolute-differences circuit using more paralleli sm Ihan in Example 5.9. at the expense of a larger circ uit size. Such a circuit would be useful in a video encoder needing to quickly determine w hether a frame should be e ncoded as a P- or B-frame. or instead should be encoded as an [-frame. Addi tional circuits migh t compute the actual values of P- and B-frames. Likewise. an MPEG-2 video decoder mig ht use circuit s to quickly recompose 1-, Pand B-frames back into full picture frames-although decoding MPEG-2 video is easier than encod ing because the ac tual determination of P- and B-frame conte nts is only done duri ng encoding; decoding merely needs 10 combine P- and B-frames with their surroundi ng frames.
Transforming to the Frequencv Domain for Further Compression DCT-Discrete Cosine Transform We saw in the prev ious secti on that sending a frame (P or B) that is just the difference from a previou or fu ture frame can result in some compression. However, the compression ratios ac hieved we re o nl y about 4; I. Reca ll earlier that a OYD needs perhaps a 40; I compre ion ratio to slOre a full le ngth movie. Thus. funher compression is needed. MPEG-2 therefore funher compresses each 1-. P- and B-frame individually. The compression method invo lves appl ying what is known as a d iscrete cosine transform to SxS blocks of pixel values within each frame. The discrete cosi ne transfornl is also used in the well-known ]PEG standard for compressing still images. like those in a digital camera. The discrete cos;lle trall sform . or DCT, transform s infonnatio n from the spatial domain to the frequency domain. (The OCT is similar to another popu lar technique known as the Fast Fourier Transform , or FFT, also used for translating to the freq uency domai n.) Trans lating to the frequency domain is a powerful concept. which is widely used in digital signal processing. To understand thi s concept. consider wa nting to digital ly store the analog signal shown in Figure 6.S7. using the fewest bits possible. The signal is a I Hz cosine wave with an amplitude of 10. To store the signal digitally. we could sample the signal at frequent interva ls. perhaps every mi llisecond . and record the measured signal value
6.7 Product Profile: Digital Video Player/Recorder as a binary number, perhaps S-bits wide. One second would thus result in 1000 • S = SOOO bits. On the other hand. we could just store the fact that the signal IS a ~osme wave with a frequency of I Hz and an amplitud~ of 10. If we store each of those numbers as a~ S-bl,' value, then we only need to store S + S = 16 bIts. Sixteen bits is far less than SOOO bits. . Of course. nol all signals that we want to digittze are SImple cosine waves . But-and this is the key idea underlying freque ncy domain representa-
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time (s) Figure 6.87 Digitizing signals by translaling 10 the frequency domain.
non-lVe. call applVx;lI/Q/e allY origillal sigllal as a SII/II of cosille lVaves of diffe I freqllell cles alld all/plillides. If we break the original signal into small regions we ob: even better a '. F ' n a I . pproxltnat lon. or example, we might approx imate one region as the sum of Hz. cosme wave of amplitude 5 plus a 2 Hz cosine wave of a mplitude 3. We mioht approxImate another region as the sum of 50 differe nt cosi ne waves of different frequ;ncles and amplitudes. The smaller the region we consider. and the more different cosine wave frequencIes we conSIder, the more accurate wi ll be ou r approximation to the real sIgnal. Rather than storing the actual frequencies along with the ampli tudes of the cosine waves. we could mstead deCIde only to consider using panicular frequencies. such as: I Hz. 2 H~. 4 Hz, S H z, 16 Hz, and so on. Then. we can simply send the amplitudes of those pmlcular cosme waves: (5, 3, 0, O. 0, ".). Let's refer 10 these amplitudes as coeffiCIents. . The OCT in MPEG-2 convens an input 8xS block, whose val ue represent pixel IntenSItIes. to an Sx8 block representing the coefficients of predetennined " frequencies ."' In the VIdeo domam , each frequency represents a di fferent block pattern . with low frequency bemg an almost constant pattern and high frequency being a changing pattern (li ke a checkerboard). The OCT determines a set of coefficients such that adding the predetemuned patterns together wi th each pattern multiplied by it coefficient yields ODe resultmg pattern very similar to the ori ginal input block. The equation for a two-dimensional OCT applied to an 8x8 block of numbers i : 8
F(II , v) =
~(Il) C(v) I .r
8
I
D[x. )'lcos (lt(2~; I )Il)c0s ( lt ( - .'; ; I) \')
=0)' =0
f ~, h = 0 11. olherw;se
C(hJ
The input is an 8x8 block. Drx. yj. The outpul is another x block. \ ith F(II," ) computing the coefficient at row u. column I' for the output block. An MPEG-2 encoder may utilize custom digital circuit' for fa t OCT computati n Notice tlmt computing each coefficient requires evaluating the rightmost teml (let' that term the inner ternl) 64 times. and that must be done for each of the IH c ffi ien
ali
...
-
-- . ---
-
--
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Optimizations and Tradeoffs 6.7 Product Profile: Digital Video Plaver/Recorder mea nin n M *6-1 = -1096 eval uatio ns of the tenll . And that inne r term itse lf requires several multipl ~ati ons. Funhermore, the OCT ope rates on 8x8 bloc ks. bu t in a 720x480 I-frame there will be 5-100 such bloc ks. Thus. the OCT for one I-frame could require 5400*4096 = 22 millio n computations o f the inner te ml. And that e ncodin g may have to occur at 30 frames per second . You can begin to see why an MPEG-2 e ncode r may need to use CUStolll digita l circuit s to compute the OCT quic kl y. using exte nsive para ll e lism and pipelining to obtain the necessary performance. The OCT computation can be sped up funh er by precomputing the cosine terms of the inner term . Notice that the OCT computes two cos ines based on the input values of /I and x and the in pu t values of v and y. However. because the OCT operates on 8x8 blocks, lhe vari ables Ii, v, x. and y only range in value from 0 to 7. Therefore, we can precompute the M poss ible cos ine va lues needed for the OCT computati on and store those values in an 8x8 table, whi ch may be programmed into a ROM . We can then rewrite the OCT transfoml as follow s:
After quanti zation, the 64 va lues in the 8x8 block are treated as a list of 64 numbers Those 64 numbers are then run-length encoded. RIIII-leng th ellcodillg is a compres io~ method that reduces consecutive occurrences of zeros by a numbe r indicating the number of consecuti ve zeros rather than representing those zeros the msel ves . For example. conSider wanung to represent the following 5 numbers: 0, 0, 0, 0, 24. If each value is 6 bits the 5 number require5 *6 = 30 bit . On the other hand, we could just send a pair of numbers, the first IIldlcatlng the number o f leading zeros, the second indicati ng the non zero number. So 0, 0, 0, 0, 24 would be e ncoded as (4, 24)-4 leadi ng zeros. followed ~~ the number 24. If each value is 6 bi ts. the run-length e ncoded version requires only - 6= 12 blls. Any seq~ence of numbers could simil arl y be replaced by a sequence of number p3lrs, each pUlr replacing a sequence of zeros and a numbe r. The seque nce O. O. 0, 0,24, 0, O. 8, O. 0, 0, O. 0, 0, 16 could thus be replaced by three pairs : (4, 24). (2. 8), (6, 16), reducing the number of bits fro m 15*6=90 down to 6*6=36 bits. Note that the number of zeros at the beginning of the sequence or in between nonzero numbers may be zero, and the last number may be zero. For example, the sequence 2, 0, 0 , 63. 2, 0 , O. O. 0, 0 could be encoded as (0,2), (2,63), (0,2), (4,0).
8
F ( II. \.) =
~C(II)C(V)
LL
D[x, y ] eos [ x. lI] cos [ y,
vl
x = 0)' = 0
Using a ROM to store the precom puted cos ine va lues speeds up the computation of the inner term of the OCT. Quantization Trans lating to the frequ e ncy domain using the OCT does not directl y perform compres· sion-we merely conve n ed a n input 8x 8 block to a n output 8x8 block . That output 8x8 block represents amplitudes o f panicu lar cos ine wave frequ e nc ies. We can achieve com· press ion by rou nding those amplitudes. such that we use fewe r bits to represent the amplitudes. For example. suppose we use 8 bits to re present the amplitude, meaning we can represe nt amplitudes ranging from 0 to 255. Suppose we only represent even ampli· tudes . mea ning 2. 4, ... . 254. In that case, we can drop the lowe t order bit. in the representation o f the amplitude. resulting in onl y 7 bits. The decoder would merely append a 0 to the 7-bit number to obtain an 8-bit number again . For example, the 8-bit numbe r 00001111 would be compressed to the 7-bi t numbe r 0000 111 with an implicit 0 in the eighth bit. The decoder would ex pand that 7-bit number back to the 8-bit number 0000 111 O--not ice that the decoded number is sli ghtl y different tha n the original , being 1-1 rather tha n the origina l 15 (a n example o f why MPEG-2 compression loses some im age quality) . We could take thi s rou nding concept furth e r, onl y re presenting amplitudes that a re multiples of 4 (thu dropping the two lowest order bits. yie ldin g a 6-bit represen· tati on). or a re multiples of 8 (dro pping the th ree lowest o rde r bits. yie lding a 5-bit representatio n). 0000 IIII mi ght be re presented as 0000 I wi th three implicit Os, tilu decoded bac k to 00001000. The decoded num ber o f 8 is diffe re nt from the original number 15 due to the ro unding. The rou nding described above. ach ieved by droppi ng low order bit s to ac hieve com· pression. i, known a, qIlQl/ti1.l1tiol/ . otice the Iradeoff- mo re ro undin g yie lds more compre"ion. at the expense o f acc uracy. Fort unately. 11//l1/{/lIs dOli 'tllotice sl/eh rolllldillg ill the hix hlreqllellcy COIIIIJOIIeIll.1 of the pict"rc-Qur vi,ion ju,t i'I1 ' t Lhat precise. We
367
a lso don' t notice mino d ' f~ . . . . r I erences In the high-freq uency components of sound-Qur h eanng Isn't that precise Th ' k f " . In 0 a very high-pitched sound, so hig h it could perhaps b uk I re ' g ass .. You probabl y couldn ' t tell the difference be tween two s uc h high-pitched ounds of slightl y different f ' . . . . . requencles-they are both Just hi gh. LikeWise. Our eyes can't detect sli ght rounding of color values in a highl y complex scene. So MPEG-2 applies quanti zatIOn more aggressively on the OCT output block 's high-frequency coefficients than on the low-frequency coefficient .
Run-le ngth encoding achieves good compress ion only if there are many 0 in the sequen ~e of numbers. Fonunate ly, the nature of the OCT leads to man y 0 nu mbers (not all cosme Jrequenc,es are need~d to approximate a signal reg ion. 0 tho e freq uencies
wlil have 0 coeffiC ients). espeCiall y after quanti zation (many coefficients are 'ust mall numbe rs. whic h become 0 during quanitization). Thus, applying run-Ienoth J enCoding after quanti zation leads to funher compression. e
EXAMPLE 6.27
Computing compression ratios involving Quantization and run-length encoding Continuing Example 6.26. assume that the 30-frame MPEG-2 sequence has the same frame sequence and average sizes as that example. bUI that each frame is further compressed by OCT conversion to the frequenc~' domain fol!owed by quafllizati o ~ and run ~ lenglh enCoding. A Sume the
DCT OUlput block conSIsts of 64 8·bll numbers. thai quantization reduces the average number size to 5-bil numbers. and that run -length encoding reduces the resulting number sequence ize to 30% of its size.
The compression ratio would be 8 Mbits * 30 I 5/8 * 0.30 *(2 • I Mbits) = 240 19.7 = 25: I.
1bilS +
* _ Mbi + ~O •
Huffman Coding After run-Iengtll encod ing. each block consists of a sequence of numbers. me numbers wi ll occur in that equence more frequently than others. HUffman codillg i a method of red uc ing the num ber of bll. reqUIred to represent a et of values, by creating shoner encodings for the frequentl y occurring val ue~ . and longer encodings for the Ie ' ~uet1! \-alue.
368
6 Optimizations and Tradeoffs Huffman codi ng. a form of encod ing known as entropy encoding, is another powerful concept in digital data compression. Suppose you wish to represent an original sequence of 16 numbers O. 3. 3. 31. O. 3. 5, 8, 9. 7. 15, 14.3. O. 3. O. Assuming 5 bits per number, a straightforward binary encoding would be: 00000 000 11 000 11 11111 00000 000 11 00 1 a 1. and so on. for a total of 16*5 = 80 bit . We can reduce this total by first observing that there are on ly 9 unique symbols: 0, 3. 5, 7, 8. 9, 14. 15, and 3 1. We really only need 4 bits to uniquely identify each symbol. We cou ld thus assign the nine unique sy mbols to 4-bit encodings using the fo llow ing de finiti ons: 0=0000, 3=0001, 5=0010, 7= 00 11, ... , 3 1=1001 (note that the encod ings are no longer the binary number representations of the origin al numbers). Thus. the ori gi nal sequence of numbers (0, 3, 3, 31 , 0, 3, 5, ... ) would be encoded as 0000 0001 0001 1001 0000 000 1 0010 etc. , for a total of 16*4 = 6-1 bits. The key observation here is that we can encode numbers using any arbitrary uniq ue bit patterns we desire, as long as the encoder and decoder are both aware of the encoding defin itions. We can take this definitions concept a step fu nher. by using encodings of different lengths. Observing that 3 and 0 occur more frequently than the other numbers, we might give 3 and a shoner encodings. So we might create the following encodi ng definitions: 0=00. 3= 10. 5=010. 7=0110 .8=0111, 9=11 00.1 4=1101. 15=111 0.3 1=1111. How these definitions were created is just beyond the scope of this discussion, though it's really not hard to learn. Notice that the encodings are such that the shoner encodings do not appear at the left of any of the longer encod ings. For example. 00 does nOl appear at the left of any of the longer encodings, like 010, 011 0,0111, etc. This feature allows the decoder to know when it has reached the end of the code word-when the decoder has seen 00, it knows it has found an encoded a (because no other encoding stans wi th 00); when it sees 10. it knows it has found a 3 (because no other encoding stans with 10). But when the decoder sees 01, it must look at the nex t bit, and if it sees 010, it knows it has found a 5 (because no other encoding stans with 010). Using this variable-length encoding scheme, the original sequence (0. 3, 3, 3 1. O. 3, 5, ...) wou ld be encoded as 00 10 10 1111 00 10 010 etc. We have insened the spaces just for readabili ty; the actual encoding would just be 001010 1111 00 1 00 1 0 etc. The total number of bits wou ld be 4 * 2 (for the four Os, encoded with the two bits 00) + 5 * 2 (for the five 3s, encoded with the two bits 10) + 1*3 (for the one 5, encoded with the three bits 010) plus 6*4 (for the six remai ning numbers 31, 8. 9, 7. 15, and 14, each encoded as 4 bits), totaling 45 bits-much reduced from the original 80 bits required by the straightforward binary encoding. Huffman cod ing achieves good compress ion when some numbers occur much more frequently than other numbers in the sequence of numbers to be encoded. Fonunately, thi s is indeed the case after OCT, quantization, and run -length tasks are performed on a block of a frame. For examp le, there may be plenty of as, Is, 2s, etc. , and fewer occurrences of higher numbers.
EXAMPLE 6.28
Computmg compression ratios involving Huffman codll1g Continuing Example 6.27, assume that pairs of numbers after quanlizalion and run- length encoding are Huffman coded, and that such encoding reduces the number of bil'> by 50%. The compression ralio would Ihus be 240 I 0.50' 9.7 = 50: I.
6.7 Prod uct Profile: Digital Video Player/Recorder
369
Summary Summarizing MPEG-2 video enCod ing: The use of 1-' P-, an d B-f rames achIeves ' . compres Ion by nOl resending redundant . f . 10 ormatIOn of Successive frames, but rather JUSI sending the differences.
~ OCT transform s 8x8 blocks of frame to the freq uency domain . which doesn' t ac leve compression itself, but rather enables compression in lhe next steps. Quanti zation achieves funher compression by reducing the number of bits needed to represent the OCT coefficients, through rounding.
Run-length encoding achieves further compression by replacing sequences of zero coeffiCients by a number indicating the number of such zeros. • Huffman cod'109 ac h'leves funher compression by encoding frequently occurring . coeffiCient numbers with shorter encodings than less frequently OCCurring coefficient numbers. The sequence of steps is shown graphically in Figure 6.88. ... 010t0010t100101010 --.J ,----...._1 0101111010101001oot - ! OCT .. !§ t001001oo0t010t11101 L--;====,--.!., ~ ~ .§ 101010001000t0111011...
~
*
~
g~ §
Uncompressed digital video
~~Q
L~~~:::::!.....!.,
MPEG-2 video (compreSsed)
L.....:.:..=.."'--_r-...0101OO1011OO..
Figure 6.88 MPEG-2 video compression encoding overview. Our example compression ralio calculations yielded a ratio of about 50: I. In fact, the compressIOn ratio can be varied by varying each of the above steps. We can use fewer I-frames to achieve even hi g ~er compression at the cost of degraded video quality. or more I-frames for Impro.ved Video quality at the cost of more bilS. Likewi e. we can vary the amount of quantization to trade off quality and compression ratio. Becau e a typical movie Will have some slow-changi ng scenes and other rapidly changing cenes. and some complex colored frames and other si mpler frames . the compres ion ratio for different parts of a video may actually vary. Notice lhe permeating presence of cradeoffs (primaril y between quality and compression ratio) throughout MPEG-2 encoding.
h
--------.l Huffman =-:-:-::::l decoding .010tool0ltOO....L ~~=':=::!..,,!., MPEG·2 Video (compressed)
I R~e~:~~~hJ~t InvelSe 1-1 . .Ot0100t0110010t010 Iquantization InvelSe L- tOOtOOtOOOtOt011110t I. OCT I - t010tOOO1000tOlttOt1 . Uncompressed digital video
r-o8' fl
~! ~ ~, ~- ~I-"I
tOt011t1010tOt00100~_ !§ ~ 'is Q> ~
Figure 6.89 MPEG-2 video decoding overview.
Cl
8
L.....:.-
[IJ
a
00
=
370
Optimizatio ns and TradeoHs 6.9 Exercises
An MPEG-2 decoder merely needs to appl y the above steps in reverse, as ill ustra ted in Fi gure 6.89. to convert an MPEG-2 strea m of bit s back into a series of
6.3 Perform two-level logic s"
371
".
K E Ize optmllZatlon for the equati on F(a.b.e) = a + a'b'c + a'e using a -map. xpress the answer as sum-of-producLS. 6...4 Perform [wo-Ievel louie s' ' "
pictures . or video.
0 lze optllnlzallon for the equation F(a bed) + a bd using a K-map. Express the answer as sum-of-~rodu~ts. 6.~ :~r~~r;, two-level logic size optimization for the equation F(a . b . e . d)
b 'd'
Clearly. MPEG-2 encodi ng and decoding require a lot of computations performed at speeds fa st enough to create smoot h-looking. good-quali ty video. Custom digital circuits can help achi eve those requ ired speeds.
a' be '
+
ab
+
_ a e
usmg a K-map. Express [h e an~we r as sum-of-products.
6.6 Perform two-level logic size opti mization for the equa tion F( a . b . c) - a' b ' c + a be. assummg t,hm IIlput combinntions a ' be and a b ' c can never occur (those two mintenns represent don t cares). Express the answer as sum-o f-products.
6.8 CHAPTER SUMMARY In th is chapter. we introduced (Section 6.1 ) the idea that sometimes we can improve a particular design cri teri a without hurting other cri teri a (optimi zation). but usually we can improve one criteri a at the ex pense of another cri teri a (tradeo ff). We descri bed (Section 6. 2) the problem of two-level size minimi zation. int rod ucing K-mups as a visual method, and then describing auto mated heuristi cs for two- level as we ll as multi level logic size minimization. We discussed (Section 6.3) methods for optimi zation and tradeoffs in
~os
never both be 1 at the same time (i.e., there arc don' t cares).
6.8 Consider the equation F(a, " be) : a ' e + a e + a ' bU' K d . . f h f II . _ . ~Iflg a -map. etennme whI ch o ,t :
6.9 Repeat the previous problem. but this time determ ine which of the terms are prime impiicams of the function.
versus Mealy type FS Is. We highl ighted (Section 6.4) several alternati ve methods for implementi ng some datapath components. incl uding a faster adder using carry-lookahead, and a sma ller multipli er using sequenti al multipli cation. We described (Section 6.5) methods for RTL optim izations and tradeoffs. including the powerful concepts of pipelini ng and concurrency as means of achieving para llel execution-a key purpose of custom dig ital design. We also described the RTL methods of component allocation, operator bind ing, and operator schedu ling. We briefl y menti oned (Section 6.6) some higher-leve l methods. includi ng the general idea of serial versus concurrent computation, and the selection of e ffi cient algorith ms. We also introduced some basic concepts of
6. 10 Forthe equation F(a . b . c)
6.11 Forthecquation F(a . b . c . d)
a ' e + a e + a ' b. delermine all prime implicanlS and all 3
ab ' e ' + abe ' d + abed + a ' bed + a ' bed'
determ ine all prime implicants. and all essenti al prime implicanlS.
.
6. 12 F~r th e prev ~ou s problem, u~e the heuristic method of Table 6. 1 to obtain a two-level size optimized equation expressed in sum·of-products form . 6.1 3 Use repeated applicati on of the expand operation to heuristi cnlly mi nimize the equation
F(a ,.b.' c)
:
a ' b ' e + a ' be + a be . Try expanding each term for each variable. Give
the mlnlll1lzed equati on in sum-of-products form .
6. 1-' Use repe:lIed applicmion of [he expand operation to he uri Ii ally mi nimize the equation
A yo u can see from thi s chapter. there are many methods fo r im prov ing our design . Yet. thi s chapter just scratched the surface of such methods. An entire mul tibillion-dollarper-year industry exists that specializes in mak.ing automated tools for converting behavioral descriptions of desired system functionalit y into highly optim ized circuit impl ementations- that industry is known as Electroni c Design Automation (EDA) or as Computer-Aided Design (CAD). Thi chapter hopefully gave you enough exposure at least to understand the basic idea behind circuit optimi zati on at various levels of design abstraction. ranging from the gate level up to the RTL leve l and beyond .
F(a .b . e . d . e) = a bede + abede ' + abed ' e'. Try expandingeachtermforeach variable.
6. 15 Using algebraic method s. reduce the number of gate inpu ts for the fo llowing equation b} cre-
ating a multilevel circuit : F(a . b . e . d . e . f . g) abede + abed ' e ' fg + a bed ' e ' f ' 9 , . Assume onI)' AND. OR. and OT gates will be used. Draw the circuit for the original equation and for the multile\'el ci rcuit. and clearl y list gate inputs for each circuit.
me delay and
number of
SECTIO N 6.3: SEQ UE T IAL LOG IC OPTI:M IZATIONS AND TRADEOFFS
Do.
PLUS
6.1: INT RO DUCTIO N
=
essential pnme Impl lc3nts of the function.
power red uction. incl uding clock gating, and using low-power gales.
SECT IO
? o\\, l ~ g ~e rms are implicants (but not necessari ly prime irnplicanls) of the equation:
abe . a b . a ' be . a ' e . e . be . a ' be ' . a ' b.
designing sequential logic. including state mini mizati on. state encoding, and Moore
6.9 EX ERCISES
6.7 Perfo nn Iwo-Ievel logic size opti mization fo r the equation F(a bed) : a ' be ' d + a b ' cd ' . assuming that a and b C'in never bOlh be 1 at the sam~ li~le: and thilt e and d can
6. 16 Reduce the number of stales
for the FSM in Figure 6.90 b)' eliminating redundant s l ~lI e s by using an implic3lion table. xy=OO
xy= 10
6. 1 Defi ne the tc rm ~ "optimization" and "tradeoff." and provide everyday examples of each. SECTIO
6.2: COM BI ATIO AL LOG IC O PTIM IZATIO S A D TRA DEOFF'S xy= 10
6.2 Perform two- level logic , ize optimization for the equation F ( a . b . c) - a b ' e + abc + a ' be + a be' u, ing (a) algebraic method•. (b) a K-map. Ex pre" the an" ver, as sum·of· product,.
Figure 6.90 FS I e\ rullple.
-
-
~
---.-..
-
xy=Ol
372
Optimizations and Tradeoffs
6.9 Exercises
6.17 Reduce the number of states for th e FSM in Figure 6.91 by using an implication tnble.
Inpuls: x: OulpulS: y
6.24 Conve n the fOll owi ng Mealy FSM to the nearest Moore equivalent
373
Inputs:s,r.
Outputs: u,y
().IS Reduce the number of Slates
for the FSM in Figure 6.92 by using an ill1p l i c~lI i on tab le. fi.19 Compare the logic size (as number of ga le inputs) and lhe
delay (as number of gatede lays) of a straightforward l·bit bi nary encod in g of the FSM in Figure 6.93 with a
6.25 Conven the follow in g Mealy FSM to the neares t Moore equi valent. Figu re 6.91 Sequence detector for bit pattern s "01"' and "10"
Inputs: g,r Outputs: x,y, z
3-bit output encoding and with a one-hoI encoding of the same FSM . 6.10 Compare the logic size (as number of gate input s) and
the delay (as number of gatede lays) of a minima l bit wid th state encoding and an output
encoding for laser-based dis-
g'r'/xyz=0 10 glxyz= 111
tance measurer FSM shown in
Figure 5.20.
Figure 6.92 FSM exa mpl e.
6.2 1 Compare the logic size (as number of gate inputs) and tlle delay (as number of galedelays) of a minimu m binary encoding (if not possible. ind io cate why). ou tput encoding. and one· hot encoding of the FSM in Figure 3.39.
SECTION 6.4: DA TAPAT H COMPONENT TRADEOFFS
~ Inputs;::e: out:
: w,X ,Y r---.
~ wxy=OOO
wxy=100 wxy=010 wxy=001
6.26 Trace the execut ion of the 4-bit carry· lookahead adder show n in Figure 6.59 when a = II and b = 7. 6.27 Trace the exec uti on of the 4-bit carry-lookahead adder shown in Figure 6.59 when b = 4.
a = 5 and
6.28 Trace the exec uti on of the 16·bit carry-lookahead adder shown in Figure 6.59 when a = 43690 and b = 2 1845. Do not trace internal behavior of the indi vid ual 4-bit carry-lookahead adders.
Figure 6.93 FSM example.
6.22 Conven the Moore FSM fo r the code detec tor circuit show n in Figu re 3.46 10 the nearest Mealy FSM equivalent. 6.23 Conven the following Moore FSM 10 the nearest Mea ly FS M equivalen t.
Inputs:S,r Outputs: a,en
6.29 Design a 64-bit hi erarchical carry·lookahead adder using 4-bi t carry-lookahead adders. Wbat is the total delay through the 64-bi t adder? How mu ch faster is the carry-lookahead adder co mpared to a 64-bit carry· rippl e adder (co mpute as slower ti me/faster time). fi.30 Design a 24-bit hi erarchical carry-lookahead adder using 4-bi t carry-lookahead adders. 6.31 Design a 16· bit carry-select adder using 4-bit ri pple carry adders.
SECTION 6.5: RTL DESIGN OPTlMlZA TlONS AND TRADEOFFS 6.32 The adder tree shown in Figure 6.94 is used 10 co mpute the sum of e ight inputs on every clock cycle. where the sum is S - R + T + U + V + W + X + y + Z.
a=O
en=O
37~
Optim izations and Tradeoffs (a) Design
6.9 Exerc ises pipcli ncd version
I nput s : byte a [256 ] . byte b[256] . byte ey
of th e adder tree (0 maximize th e speed at which we
Ou t put: by t e su mx . by t e sumy . byte e[256]
J
MULT_OR_ADD:
can operate our clock input
elk . (b) Create a timing diagram.
i nt i -O : i nt s umx i nt s umy whi le( i < if ( a li ] e [i] = s umx = el se e[i J sumy
elk
6.33 Assume the delay of an adder is 3 IlS . How fast can we execut e the ndder tree shown in
Figure 6.94 and how fa st can we execute the pipelined adder tree des igned in Exerc ise 6.32? 6.3~
L - - - -- _l> s
What are the latency and throughput of the pipelined
Figure 6.94 Adder tree used to compute the sum of
adder tree YOli designed in
eight inpUls every clock cycle.
6.35 (a) Convert the following C-l ike code
lO
I npu t s : byte a[256] . b [ 256]
create
by t e sum . byt e e[256 ]
e[i ]
= =
=
0;
<
a [ i] * ( b [i] + ey) : s umy + e [i ] ;
di fferent
minimum circuit size. Be
256 ) {
ali]
two
designs: onc design optimized for minimum circuit speed and one design optimized for
i nt i =0 : int s um
256 ) { 128 ) I al i] * b[i ] : su mx + e[i ] :
>
6.38 Redesign the datapath and controller designed in Exercise 6.37 by allowing up to nine concurrent additIOns and inserting pipeline registers 10 data path and updating the controller if necessary. Assuming a comparator has a delay of 4 ns. an adder has a delay of 3 ns. and a multiplier has a delay of 20 ns, how long wi ll the circuit take to fini sh its computation? 6.39 Give n the high-level state machine in Figure 6.95.
MUL T:
wh il e ( i
0;
a high-level slate mach ine .
(b) Use the RTL design process shown in Table 5.1 to convert the high-level tate machine for the C code to a controller and a datapath. Design the datapath to structure, but design the controller to the point of an FSM only. (e) Redesign your datapath to allow for concurrency in which four multiplications and two additions can be performed concurrentl y. Out put:
0:
i++;
Exercise 6.32?
sum
375
*
sO = sO· cO
51 = 51 +sO"cl s2 = sO· x2
53 = 52+s0· c1 54 = 50· c1
F = 53· 54-c2
Figure 6.95 High-level Slate machine for Exercise 6.39.
sure to clearl y indicate the component allocation. operator binding. and operator scheduling used [0 design the two circuits.
b[ i] ;
sum + e[i] :
i ++:
SECTION 6.6: MORE 0 6.~0
6.36 Redesign the data path and controller designed in Exercise 6.35 by allowing up to four concur· rent additions and inserting pipeline registers to your da tapa th and updating the controller if necessary. A suming an adde r ha a delay of 3 ns and a multiplier has a delay of 20 ns. how long will the circuit take to finish its computation? 6.37 (a) Convert the following C-li ke code to high-leve l state mac hine. (b) Use the RTL design process hown in Table 5. 1 to convert the high-level state machine for the C code to a controller and a datapath. Design the dawpath to structu re, but design the contro ller to the point of an FSM only. (C) Redesign your datapath to allow for concurrency in which three comparisons, three additions. and three multiplications can be performed concurrent ly.
OPTIMIZATIO SAND 'ffiADEOFFS
Trace through the execution of the binary search algorithm when searching for the number 6 in the following sorted list of 15 numbers: I, 10,25. 62. 7~. 75. 80. 4. 5. 6. 7. 100. 106. III, 121. How many comparisons were req ui red to find the number u ing the binllr) search and how many comparisons would have been required using a linear search?
6A I Trace th rough the execution of the binary search algorithm when searching for the number 99 in the fo llowing list of 15 numbers; I, 10.25.62.-74, 75 . 80. 4. -. 87~ 99. 100. 106. III. 12 1. How many comparisons were required to look for the number u ing the binllr)' search and how many comparisons are required using
II
linear search?
6A2 Trace through the execution of the binary search algorithm when searching for the number L I in the list of numbers from the previous example. How many comparisons were required to find the number using the binary earch and how many comparisons are required using a linear
search? 6AJ Using the list of 15 numbers from Exercise 6.41. how many numbers ould \\e find faster using a linear search algorithm compared with the binary search algorithm?
376
Optimizatio ns an d lra deoHs 6.9 Exerc ises
SECTION 6.7: POWER OPTIMIZATIO N 6A-l Given (he logic gates shown in Figure 6.96, optimize the followin g circ uit by reducing power
consumption without increasing the circuir's dclny.
a b
d Figure 6.96 Log ic gal e li brary. 2/0.5 format means 2 ns delay/O.S nw power.
(l A5 Given the logic gates shovm in Figure 6.96. optimi ze the following circuit by reducing power
consumpti on wi thout increasing the circuit's delay.
b
6..t6 Given the logic gates shown in Figure 6.96. optimi ze th e followin g circuit by reducing power con sum pti on without increasing the circuit 's delay.
a
b
h
6A7 Gi ve n th e logic gates show n in Fig ure 6.96. optimi ze the fo llowing c ircuit by reducing power consumption without increasing the circuit's delay.
a
b
~
377
DESIGNER PROFILE
Smila has degrees in Electronics Engineering .md in Computer Science. and has worked in the dig ital design fi eld for nearl y a decade. She spellt a lot of time thinking about the choice of a co ll ege maj or. ··Wh al major should I in vest my focus. energy. hean. and soul for what will be some of the 1110 St produc tive years of m)' li fe?" She chose engineering. for severa l reasons. ·'First. engineerin g is a career in itsclfunlike some other majors. jobs speci fi cally for engineering majors arc out there. With engineering. I would le:ml the 1110 S1 va luable and universal of ski lls: problem solving. Second. engineers have many options. because engineers are highl y va lued for their problem solvi ng ski lls by other pro fessions, such :'IS management consulling. marketing. and investment banking. And elec trical and computer engineers cun choose from a mnge of industri es in which to work: telecommunications. image proccssing. mcdical devices, Ie fabrication. and even banking. This was a phenomenal discovery for me!" Smit
team are also my friends and it's a lot of fun to work with th em." I n her decade of work so fa r. Smita has taken on some management responsibi lities. "As manager of one of the four products that my company deve lops. I playa variety of different roles. I wo rk with my team of 7 software developers to determine what features to build in the product and how best to build those features. I work with the marketing and sales team to understand what the customers need and how best to message and position our prod uct. Finall y, I work with other groups that are involved in releasing a product - technical publ ications. application engi neering. and product engineering. The diversity of my job makes it very interesting. Smita enjoys the respect thm engineers receive. "As an enginee r. I am highly respected by custo mers , partner companies, and by our market ing and sales organizations beca use I have a deep understandin g of our products. I rea ll y know my stulT since I bu ilt it and I get recognized for it: · And regarding the pay: '·1 get compensated very we ll for my skill s:· She also likes the lifestyle: "I get in to work around 10 a. m. and leave around 7 p.m. I don't have earl y morning meetin gs unlike the folks in marketing and sales, and I can work from home once a week or more often if I wish. Thi s is also a great career for women - I can take time off and return to my job without much penallY when I have children. I can tailor my work hours as I Deed as my children are grow in g up. Lastly. I realize that I can move from engineering to other functions such as marketing and sales. but not the other way around ! That's a great benefi t of be ing an eng inee r - more option :. Smita recommends engineering and computer science students focus on certain thing~ while in college. ··Fi rst. ge t a good unde rstanding o f both hardware and so ftware. Systems are highl y integrated today and there are very few compani es that develop one witho ut payi ng very close attention to the other. For instance. though I write so ftware. I need to completel y understand the hardware for which il will be used. My husband. o n the other hand. designs telecommunication chips but works very closely with hi s oft ware team. especially during the ini tial design stages when they decide what to implement in hardware versus software and how to design the hardware interface so that the software algorithms work efficiently:· ··So, wh at do I mean by a good understanding of hard ware and so ftware? In software. 1 think it is mosl important to deve lo p good software ··habits·. Treat your program li ke a well-landscaped garden-you want it
378 ~
6 Optimizations and Tradeoffs
DESIGNER PROFILE (continued)
beautiful and weed- free. Understand claw ~lruc tures we ll
"Other than these hardware and soft ware skills, become
and know when ant: is morc appropri ate than th e ot her.
adept at math and analysis. Learn to frame problems and
Organize your code, be disciplined. cross the Ts and dOl the h. document diligently. have your code reviewed by friends. and fina ll y. don'! be afraid to throwaway code
and rewrite it if yo u disCQVC! f a better way,"
"In hardware. understand the b'1Sics of logic design and then make sure you also understand the capac iti ve. inductive. and resisti ve propertie s of circuits since these play a big role in designing the high-speed circuits of today."
break
them
down
until
you
can
sol ve
them.
Be
7
experimental and try diffcrcllI tools and methods. Have a
hypothesis and thcn go about proving or disproving it. If YOll haven' t already, you wi ll soon discover thai cngineering is nOI onl y fun . bUl also provides you with many fulfilling career opportun.ities-so stick with it and make th e mos t of it !"
Physical Implementation 7.1 INTRODUCTION A digital circuit design lhat we've created bUl just drawn out . perhap wilh pencil on
paper or as.a 6gure in this book. is just a drawi ng. Somehow. we must event ually implement that dtgttal circuit dc ign on a real phys ical device. so that the de vice can then be placed In some electronic product to BeltWarn carry out the desi red fun ction. owadays, such a device is usually some form of in tegrated ci rcuit, Or IC. also known as a computer chip, or just chip. In other words, looking at Figure 7. 1, how do we get from (a), the seat belt warning light ci rcuit we designed in Chapter 2. to (b). a physica l impl ementat ion using an IC? Physical Digital circuit implementation design In th is chapter, we will describe (b ) (al several popul ar physical implementati on Figure 7.1 How do we get from (aJ to (hJ? technologies for digi tal circuits.
7.2 MANUFACTURED IC TECHNOLOGIES If we are willing to wait weeks or months fo r a physical implementation of our digital circuit design, and iF we are willi ng to spend tens of thou ands of dollars to million of dollars for that physical implementation, lhen we might consider implementing our circuit using one of several technologies that involve the manufacture of a custom or semicustom Ie.
Full-Custom Integrated Circuits One physical implementation technology is known as a custom Ie. A!ull-CIIstOIll Ie is a chip created specifically to implement the gates (actually. the transistors) of the desired digi tal circui t design (Figure 7.2). We digital designers wouldn't usually build full-custom ICs ou rselves, but rather we would send our desired digital circuit design out to a group or company that specializes in transforming digital de igns into custom IC . Engineers. assisted by computer-aided de ign (CAD) tools. conven our desired digital circuit de ign 379
380
Physical Implementa tion into a c ircu it o f tran sisto rs. and then decide where to place each transistor on the surface of the c hip. how to orie nt each transistor (e.g .. left to right. ri ght to left. top to bottom , ClC.). how big to make each transistor, etc. All that infomuHion abou t how the transi stors should be layed out on a chip's surface is known as a layol/t. Then. the fu ll-custom IC engineers send that layout inform ation to a special factory lhat speciali zes in fabri cating ICs. known as a fabri cation plant. or Jab for short. Fabricating an IC is often re fe rred to as a sili con spill . Fabricating an IC is an extremely costl y. de licate. error-prone process, uti-
Accordmg (oot/e sun'(')',
on!., about
/00/.- 0/2002 digital circuits were Implemellted aJ CUSlOm tCf.
7.2 Manufac tured Ie Technologies
38 1
Gate Arrays
BeltWarn _
- - - - --
Custom layout
Fab
months
Ie Figure 7.2 Full-cuslom Ie design.
lizi ng state-of-Ihe-art photographic, laser. and c hemica l equipment that costs hundreds of milli ons of dollars. The fabrication process may take many weeks or even months, because transistors and wires are formed as layers on the surface of a chip, and each layer may take hours or even days to form through chemical processes. Implemen ting a digital ci rc uit on a full-custom IC is a complex and ex pensive task. Costs for setting up the fabri cation of an IC, known as 1I0llreclIrrillg ellgilleerillg (NRE) costs. can easi ly exceed many millions of dollars for a full-c ustom Ie. Furthermore, that setu p takes time. perhaps months, and that time ma y be costl y to us too-the product for whi ch we are fabri cating the chip may be losi ng market share to a competing product a lready completed and being sold while we wai t for o ur chip to be fabric ated. Once we've set up the details needed for fabri cation, the fabrication process itself is less expensive. But because we c ustom designed everything, the probability is high that we made a mi sta ke somewhe re in the transi tors or wiring. Therefore. after fabricating a full-custom Ie. we may find e rrors that necessitate refabricating the Ie. known as a respill . Respinning may happen two or three times. each time requiring weeks or months, thus costing us even more. We ought to ei the r be making millions of c hips, or c harging large amounts of money per chip. to earn back the large NRE costs. Needless to say. full-custom IC fabrication is not extremely common. Designe~ choose to implement a digital c ircuit on a full-c ustom IC when they know they will produce the c hip in ex tre mely high volumes , such as a mass- produced chip found inside calculato rs or wristwatches, or a mass-produced microprocessor chip like a Pentium. Hi gh vo lumes in the te ns of millions or more are needed to offset the cost and time needed to produce a custom Ie. Alternatively, desig ners may choose to implement a digital c irc uit on a custom IC if cost is not ti ghtl y constrained but maximum perfonnance is a must. as mi ght be the case in military or space applications.
Semicustom (Application-Specific) Integrated Circuits-ASICs Because physical imple mentation on full-cu stom ICs is so costl y a nd time-consuming, semic ustom technologies evolved during the 1980s and 1990s that reduce the costs and the time of fabricat ing a ch ip, known as Applicatioll-Specific Illtegrated Circuits , or ASICs. Two popular AS IC techno logies are gate a rray and standard cell.
The hard~st pan of custom IC design is designing and fabri cating Ihe transistors that will go onto t e surface of the chip. Designing and fabri cating the wires that connect those trans Istors IS somewhat simpler. Gate array ASIC techno logy utili zes a chip who e transis tors are predesigned to form rows (a rrays) of logic gates on thc chip. as shown in =Igure 7.3. Gate arrays are sometimes re ferred to as sea-oj-gates. To imple ment a desired Igltal Circuit on a gate array chip, we mere ly need to c reate the I"ires that conneci those gates. Creatlllg the wires represent just the last steps of fabrication. and thus gate array technology e liminates much of the time and cost of fabricatin g a cllip for a partic ular deSign. A gate array company predesi gns and mass-prod uces the gate array chi p, and then c ustomizes some of those chips for each clie nt's c ircuit- the c hip i somewhat customI zed ~ h~nce the term sellliCI/SIOIII . and the c ustomizatio n is for a particular circu it appitcatlon. hence the ternl afJfJlicatioll-specific. Figure 7.3 illustrates how we might Implement our seat belt warning light circuit (Figure 7.3(a» using a gate array chip (FI gure 7.3(b». Figure 7.3(c) shows how we might map the desired 3-input AND gate to two 2-lIlput gate array AND gates. and the inverter to one of the gate array inverter . The figure also shows how we might imple me nt the desired wi ring among the gate array's pillS, the gate array AND gate, and the gate array inve n e r. The remaining gate and pins on the gate array chip would be unuti lized . Fabricating these wires would re ult in the IC be ing customi zed to our seat belt app licat ion (Figure 7.3(d» .
Figur.7.3 Gale array lechnology: (a) desired circuit. (b) gate array before wires are added. (c) gale array after
w
wires are added. thu implementin g
Ihe desired circuil, (d) fabricaling Ihe wires completes the Ie. NOle: real gate arrays hnve many thousands or millions of gates. not just a fcw.
We point out that the actual mapping of our desired di gital cir uit to a gate array would typicall y be carried ou t by an au tomated tool. Designers rarely. if eve r. carry out that mapping manuall y, and in fact usua ll y don ' t even see that mapping in any fonn-the mapping is a ll done by tools, resulting in huge data files that can be processed by other tools at a fab to control the fabrication process. We also poin t out that a typical gate array chip may hold lIIallY thol/sal/ds or milliolls oj gates: the gate array shown in Figure 7.3. having less than ten gates, is trivially sma.! I and is for illustratio n purposes only-gate arrays wilh ol//y 10 gales do 1101 exis/. Furthennore. we would typically not u e gate arrays unless our design contained thousand of gates or more. For de' igns with only a few gate. we would instead use logic ICs: see cetion 7A.
384
Physical Impleme ntation
7.2 Manufa ctured Ie Technologies co = ab
NOI ice thm our standnrd cell implementalion places the cell such thai wiring is
N NT~ implement an AND gate using NAND gates, we can subslilute the AND gate by a Ah . gate fOll owed by a NOT gale (which we know 10 be a two-i npul NAND gate wit Its IIlputs tied together), as shown in Figure 7.8. Thi s works because given in puts a. b, Ihe first NAND compu les (a b ) , , and Ihen the NOT gate computes (a b) " _ Figure 7.8 Implemenl ing an AN D gale usi ng a b, wh ich is AND. NAND gales. To implement an OR gate using NAND gates, we can substiwle the OR gate by a NAND gate wi th each input invened, as shown in Figure 7.9. This works because given F=(a'b')'=a"+b" tnputs a, b, the circuit of NAND =a+b gates in Figure 7.9 computes Fi gure 7.9 Implemenling an OR gate using ( a ' b ' ) ' . which by DeMorgan's AND gates. Law is a " + b" , which simpli fi es to a + b - which is OR . When we replace a circuit originally consisting of A D/OR/NOT gates by a circuit with NAND gates only using the above substitutions. we may fi nd that certain Signals get double-tnverted- the signal feeds into an inverter and then immedialely feed into another invener. Double-inverti ng a signal yields the original signal, so double inversions can be replaced by ~ just a wire, as shown in Figure 7.10. ~ Such eliminali on red uces the transis- Figure 7.10 Double inversions can be eliminated. tors needed without changing the circui t's funct ion .
5 = a'b + ab'
minimi zed. whereas the gate array implementation of Figure 7.4 requi red u S to run the wi res to
a
the pre-existing gate I OC~ll ions. resulting in longer wires. Thus. the tandard cell implementa-
b
co
tion may be faster than the gate array implementalion. si nce shaner wires lypica lly
have sha ner deb )'.
Implementing Circuits Using Only cell row NAND Gates You may reca ll from Chapter 2 that CMOS Figure 7.6 Half-adder usi ng standard cells. transistors lend themselves more readil y to creating NA D and NOR gates rather than AND and OR. The stated underlying reason was that pMOS transistors conduct Is well but not as. while nMOS transistors conduct as well but not Is. In any case, gate arrays typicall y contain plenty of NAND aneVor NO R gates. rather than AN D and OR gates. And standard cell designs will also be more effic ie~t if implemented using NAND or NOR gates rather than AN D and OR. Furthermore. creating a gate array is much eas ier using just one type of gate, like just NA Ds, or just NORs. rather than having to decide how many AND gates, OR gates, and NOT gates to pre-instantiate in the arrays . Given the ready avail ability of NAND or NOR gates in CMOS ASIC tec hnol ogies, we therefore want a method for converting AND/OR Circuits to NAND circuits or to NOR circuits. Fortunately, converting any AND/OR circuit to a NAND-onl y circuit is possible because NAN D is a uni versal gate, as was menti oned in Section 2.8. A tllliversal gale is a logic gate type that can implement any Boolean fun ction usin g gates of that one type only. One way to understand NAND's universa li ty is to recogni ze that we can implement a NOT gate, an AN D gate, and an OR gate by substituting each by an equivalent circuit of AND gates. Therefore any circuit of NOT, A D, and OR gates can be implemented using NAN D gates only. To implement a NOT gate using AND gates, we can sub titule the NOT gate by a two-input NAND gate with its twO inputs ti ed together, as shown in Figure 7.7. The truth table in the fi gure shows that the Inputs Oulput NAND gate with its inputs tied together acts x a b F the same as an inverter. When the input X is 0 0 0 1 0, both inputs of the NAND gate are 0, 1 t t 0 causi ng the NA ND gate to output 1. When the input X is I, both inputs of the NAND Figure 7.7 Implemenling a NOT gale using a NAN D gate gate are 1, causi ng the NAND gate to outpu t O. Alternatively, we could simply connect X to one NAND input. and a 1 to the other NAND input. Then if x is 0, the NAND outputS 1. and if x is I, the NAND output 0, achieving the desired OT gate behavior.
385
~+b "
K}-
.
EXAMPLE 7.3
Implementing a half-adde(s sum circuit using NAND gates Figure 7. 11 (a) shows the sum circuit for a half-adder (sec Seclion 4.3). usi ng AND. OR. and Nor gates. We can implement that circuit using AND gales only by subs tituting each gale with an equivalent NAND ci rcuit. as shown in Figure 7. II{b). Aflcr the substitutions. we note that there are two signals that are doublc·invcncd. Eliminating the double inversions resu lts in the circuit shown
in Figure 7.II (c). double inversion
~~ (a)
a
a double inversion (b)
~ (e)
Figure 7.11 Implemenling a half-adder's sum circuil usi ng NA D gales only: (a) original ANDIOR! NOT circuit. (b) circuit oblaincd after SUbSlilUling equivalent (c) circuit after eliminat ing double inversions.
A D circui~ for e3ch gate.
386
Physical Implementation
7.2 Manufactured Ie Technologies
When conven in g A D/OR/NOT circuits by hand 10 NAND ci rcuits. some people find it easier 10 simply draw inversion bubbles rather than the NAND-based inveners. as shown in Figure 7.12. Then. double inversion bubbles on a signal cancel. Any remaining isolated inversion bubbles become a NA D-based NOT gate. Thus, lhe ci rcuit in Figure 7.12 wou ld end up identical 10 the ci rcuit in Figure 7. 1 I (c), If NAND gates with a fi xed number of inputs are available. such as 2- input NAND gates onl y, we can first modify the AND/OR circuit 10 use only 2-input AND/OR gates (by composi ng larger gates from smaller ones-see Seclion 5.8), before convening 10 NAND gates.
double inversion
double inversion
a b
b
b double inversion (a)
double inversion
Figure 7.12 Drawing inverters as
lransforming
circu it
a-{)x>-a.
---
Gate array and standard cell libraries typically inc lude additional components. beyond just NAND or NOR gates, that have efficient CMOS implementations. For example. a popular such component is known as AND-OR-INVERT. or AOl for shon . Such a component has two 2-i nput AND gates (thus four inputs total). feeding into a 2-input NOR gate. That circuit can be efficiently designed using CMOS transistors. Thus, we would want to utili ze AO I components, and other si milarly compact available components in a library, as much as possible. The task of convening a general logic circuit to a circuit using onl y components from a panicular technology 'S library (e.g., a particular gate array library or standard cell library) is known as tecllllology mapping. The task of determining where to place tho e components on a chip is known as placement. and the task of connecting tho e components by wires is known as routing. All three tasks, collecti vely known as physical design , are typically done by automated tools today.
into
EXAMPLE 7.4 Impleme nting a half-adder's s um circuit using NOR gates Earlier. we demonslrated how to represent the half-adder's sum output with NAND gates; we can just as easily implement the sum output using NOR gates. The half-adder's sum circuit is shown agai n in Fi gure 7.14(a). We replace each NOT. AND, and OR gate by its equivalent NOR circuit in Figure 7.14(b), using inversion bubbles instead of NOR-based NOT gates for convenience. We eliminate double inversions. and replace stand-alone inversion bubbles by OR-based NOT gates, as shown in Fi gure 7.14(c).
(e)
The half-adder's sum circuit was implemented with fewer NA D gates than NOR gates. Depending on the original circuit, the reverse cou ld be true. We saw that NAND gates were well-suited for circuits in the sum-of-products form. NOR gates are best used when a circuit is in product-of-sums form (a level of OR gates feeding into a single AND gate).
a-c[>-a.
NOR gates replaced each AND, OR. and NOT gate wilh equivalent NOR-based circuits, as shown in Figure 7. 13. We can replace a NOT gate Wilh a Figure 7.13 NOR gate equivalencies. two-input OR gate with the inputs tied IOgether (or alternati vely, by a two-input NOR gate Wilh one input tied 10 0). We can replace an OR gale wilh a NOR gate followed by an inverter. yieldi ng (a+b) " = a+b. We can substitute an AND gate with a NOR gate having inverted inputs, yielding ( a' +b' ) , a ' '*b' , a b (notice the use of DeMorgan 's Law).
(b)
. Figure 7.14 Implementing an A D/OR/NOT circuit using NOR, onl y: (a) original circuit, (b) circui t obtained by substituting AND/ORINOT gates by equivalent NOR circuits. using inversion bubbles :or ea~e of drawing. (c) final circuit after elimi nating double inversions and replacing standalone inverSion bubbles by NOR-based NOT gates.
inversion bubbles during conversion to NAND.
Implementing Circuits Using NOR Gates Converting AND/OR/NOT circuits 10 NOR gate circuits is similar to convening to NA D circuits, as a NOR gate is also a universal gate. The process of
387
EXAMPLE 7.5
Implem enting the seat belt warning light on a NOR -based gate array Implement the Bel/Warn circuit of Figure 7.15(u) using the NOR-based gate array of Figure 7.15(a). Noticing that the gate array has only 2-Input NOR gates. we first conVert the Bel/Warn circuit to usc AND/OR gates wi th 2 inputs only. as shown in Figure 7. 15(b). We then convert the ANDIOR circuit to the NOR-only circuit in Figure 7.15(c). using the equivalencies in Figure 7.13, and using inversion bubbles rather than NOR-based inverters. We then see a double inversion on the wire from input S. so we eli minate those two inversions. Note that we do not
eliminate the double inversion between points 3 and 4 in Figure 7. 15(c). be ause the first in"ersian is part of a NOR gate-eliminating that first inversion would convert the OR 2.3.te to an OR. defeating our goal of havi ng NOR gates onl y. After converting remaining stand-a1~ne inversions to OR-based inverters. we map the circuit to the gate array's _-input lOR 2ates as in Figure 7.15(d)-we numbered the OR gates of Figure 7 .15(c) and (d) to show the ~rre pondence between the two circuits.
388
1 Physical Implementation
1.3 Programmable Ie Technology-FPGA Fil'ld·
prog rammable gale arrays (FPGA s) h l1v(' "gale a rrays "
DD-DDD-DD-D-D-
110
iI/side 'hemthe I/(lm e is there due 10 historical
reasons,
--- - - - -- - - - --- -- --------
--
(b)
w
P
389
The words "gale array" are lhere in the name because, when FPGAs firsl became popu lar in the mid- 1980s. they were marketed as an alternative to gate array technology, which was very popular allhal lime. Thus, an FPGA was a semicustom IC (nearly synomous with gale arrayal lhal lime) thaI could be programmed in the field instead of at a fabrication plant. However, be forewamed Ihat the inlernal design of an FPGA chip looks nothing like a gale arraY-lhe naming is somewhal unfortunate. The two basic Iypes of components inside an FPGA are lookup lables and switch matrices. Those components are replicaled hundreds of limes in regular patterns inside an FPGA. We now describe each type of component.
------ -- - - --- -- - - -----
(a)
Lookup Tables
(c)
(d )
Figure 1.15 Implementing the BelllVa,." circuit on a NOR·based gate array Ie: (a) original gate array. (b) - (c) convening (he des ired circuit LO two- input
OR gal e!' only. (d) final gate array with
wires.
7.3 PR OGRAMMABLE ICTECHNOLOGY- FPGA ManufaClUred IC technologies require at least a few weeks. and usually more like several months. to canven a desired di gital circui t design into a physical Ie. What if we are developing a circuit that we want to implement roda,,? In that case. we can utilize one of several programmable IC technologies. In a programmable Ie techllology. we tmplement a desired circuit simp ly by writing a panicular sequence of btls tnto a memory (or number of memories) contained in the Ie. Using a programmable IC technology has the drawback of worse performance. size. and power compared to custom or semicustom Ie technologies. But we get our implementation today. and the benefits of that fact may out· wei gh the drawbacks. -The most popular form of programmable IC technology is known as a Field-Programmable GoteArray. or FPGA . An FPGA company prefabri cates an FPGA chip, meaning that the chip contains all the transistors and all wires that the chip will ever have. We buy lhose FPGA chips. and then program the chip to implement our desired ci rcuit. To program in lh is context mean imply to download a series of bits into lhe chip's memories-not to be confused with writing high-level oflware proFigure 1.16 FPGA chip>. grams like C or C++ code. Such programming .. . OCcurs in lhe fie ld. meaning in our lab. or offi ce, or home. 3.', opposed to tn a fabn atton plant. Hence the words "field-prog rammable" in Ihe FPGi\ nallle. Funhermore. program· ming typica lly takes only seconds. or perhaps minules at most. Figure 7. 16 show. SOllie FPGA chips. The chip al Ihe top. wilh iL, front and back shown , mea.,ures ahoul 3/4 tnch on each side. The chip on the bottom measures just over I inch on each side.
Tlte key idea underly ing FPGAs is '''m tI memOf)! wilh N'addre,'is lines COfl implemenr 1Il1y combi,wliollal !1If1Cliofi wilh N· i"pIIIS,
A basic idea underl ying FPGAs is lhal a memory can implement combinatioltal logic. More specifically, a I-bit wide memory with N address lines. and hence 2N words, configured 10 read the word corresponding to the present address. can implement any Boolean combinational func tion of N variables. Recall that a memory configured 10 be read will outpul the contents of the word correspond ing to Ihe present address al the memory's address lines. So if a 4x I memory's address lines a 1 a 0 are 00, the memory wi ll outpul the contents of word O. If the address lines are Ol. lhe memory outpulS the contents of word I. Likewise, 10 reads word 2. and 11 reads word 3. Implementing a Boolean function wilh a memory can therefore be done simply by connecting the funclion 's inputs to lhe memory address lines, and storing a 0 or 1 in each memory word to match the desired funclion OUlput for each combination of inpul values. For example, consider lhe function F( x . y ) = x ' y ' + xy . The truth table for the funclion is shown in Figure 7. 17(a). To implement the example fu nction, we can connect x and y to a 4x I memory's address lines a 1 and a 0, respectively. and based on the truth table. we store a 1 in word 0, a 0 in word I. a 0 in word 2. and a 1 in word 3-in other words. we slore lhe trulh lable OUIPUIS in the memory. The memory then implements the d ired function, as shown in Figure 7. I7(b). For example. when xy=OO, we wanl the output to be 1. Figure 7.1 7(c) shows thai when xy-OO, the memory's address lines will be 00. and thus the memory will outpul lhe contents of word O. which i the value 1 , as desired. F =x'y' +xy 4x 1 Mem.
x Y
F
0 0 0 0
1
------
0 0
0 0
----J
a1 aO
1
0
1 2
x=o
~ al
y=O
aO
3
0 \ 0 , 1, , 0:
F=1
+F (8)
F =x'y'+xy G = xv'
,
l ~ rd
- --~
xy-
4x 1 Mem.
--I ';
l~rd
(b)
(c)
x Y 0 0 0
F G (1 O'{ 0
0
: 0 1 : \ 1 0 :
1
4x2~.
/1
°i
"---"
(d )
F G (e)
Figure 1.11 Implementing logic functions using a memory: (3) _-input fun 'li n truth table. to) corresponding memory contc,llls and 'onnectlo,ns. (c ) the propt!r outpUt appe3f'S for the gi\cn input values. (d) two functi ons h~\\,11lg the same two mputs. (e) mcm I) l.."Ontents for the '\\ Q functions.
390
Physical Implementation 7.3 Progra mmable Ie Technology-FPGA A 111~1110ry with JII bits per word. rather than just I bi t per word. can implement M runctions. as long as all those M functions have the same inputs. For example. consider
thetworunctions F(x . y) = x ' y ' + xy and G(x , Y) - xy '.The tmthtableror the e two functions is shown in Figure 7. 17(d). A 4x2 memory. which has 2 bits per word. can implcmcm those two functions. as shown in Figure 7. 17(e). A memory used to implement a combinational circuit is known (in FPGA terminol ogy) as a lookup table. When used as a lookup table. we typ icall y rerer to the memory by the numbcr of iI/pillS (address li nes) and the number or out pu ts (bi ts per word), rather than by the number or \I'onls and the num ber or out puts. For exampl e, we would refer to an 8x2 mcmory being used as a lookup table as a "3- in put 2-output lookup table," rather than as an 8x2 lookup table From this point forwa rd. we' ll assume Ihe memory is configu red for read, and thus we \\,on't show Ihe read line sellO 1.
EXAMPLE 7.6 Implementtng the seat belt warning light with a lookup table Use a lookup lable 10 implemenl Ihe seal belt
p s
warn ing light circuit from Figure 7.1. whose
0 0 0 0 0 0 0 0
circuit appears in Figure 7. 18(a) and whose equation is:
,
,
,./ = kps ' \Ve generate the truth table for the fune·
tion . as shown in Fi gure 7.18(b). Because the
circuit has three inpu ts. we kn ow we' ll need
,
0 0
, 0
a 3- inpul I-oulpul lookup lable (memory). \Ve connect the inputs 10 the memory's
address lines. and store the truth table in the
memory. as shown in Figure 7.18(c). Ihus implementing the desired runction . Ir the 3-
o
0
,
0
2
0
o o o
input I-output memory is an Ie. then we are done implementing our design. and can insen the Ie into the electronic system Wilh
,
7
"hich Ihe Ie should inleracl. (c)
Ie
0 0
----(b)
w
!0 ' iO
:0 :0 :0 :0 :,
391
16-word memory a 16 . . Id · ' -tnput functIon would require a 64 K word memory; a 32-input func tio nthwou. reqUIre a 4-billion-word memory. The needed memory size grows the same as e size or the f ' . . · numb ff . . unction s truth table, whIch we know grows as 2'v . where N IS the . . . er 0 unclton tnputs I h ' t' < f . . n SOrt, a tmth table IS 1101 an effiCIent Boolean function represenl a Ion .or unctions . h ' . WIt nu merou tnpu ts, and thus a lookup table IS not an efficient imple ' mentatIOn ror runctions with numerous inpu ts. Partltlomng a funct' ' . . Ion s CirCU it among multiple lookup table can yield more effi. . cIent Implementations ~ I . . . f or arger fun ctIOns. Consider the extended eat belt warning CirCUI t ro m Example 28 L ' . " . " et s eX lend the ci rcui l even more by addin a a third "diagnostlc IIlput called d th r . 0> . . al orces the warnlllg light 10 tu m on when d=l-perhaps a mechamc IIlvestigating a raulty warning light mighl want to force the warnina liaht on to Isolate whether the lighl has blown OUI or to help determine ir a seat bel~ se~sor has The ex. tended circul't 's . . can . t be mapped to a fatled. . I ShOwn .III F'Igure 7. 19(3). That CirCUit 3-lIlput I-output lookup table because the circui t has 5 inputs, bUI the circuit could be mapped onto a 5-lIlput I-output lookup table. Alternatively, we could implement the CIrCUIt by UStng a 3-input I-ou lput lookup table connected to another 3-input l-output lookup table, as shown in Figure 7. 19(c). We do so by partitionina the oriainal circuit iOlo two groups. such thaI the fi rst group has 3 inputs and I output. a~d the s~cond group has 3 IIlputs and I output. as ci rcled in Figure 7.19(b). The fir t group's output. whicb we've labeled as x, has the eq uation x = kps '. The second group 'S output has the equation vi = x + t + d. We would program the lookup tables to implement these functions_ as shown III FIgure 7.19(c), thus implementing the desired circuit using two lookup tables.
I
:0I ' ~~
..
BeltWarn
BellWarn
8x' Mem.
,
- .... 0
Programming .
(seconds)
k
X
You've ju t seen an example of a very w imple programmable IC technology-a memory. We can use a memory chip Figure 7.18 Lookup lable implemenlation. with N address lines and hence 2N wo rd ,. and with M biL~ per word . to implement M dirrerent Boolean functions of the sallle N inputs. We can purchase a memory chip before we need it for our design. and then we can "program" the memory chip in our lab to implement 3 desired Boolean function .
Partitioning a Circuit among Lookup Tables Unr rtunatc ly. u,i ng a memory to implement a Boolean function doc not work well for function, with numerou, input,. For exa mple, while a
P (a)
3 inputs
3 inputs
, oulpUI x=kps' (b)
0 0 0 0
ax, Mem. o
,
0
2
,
, OUIPUI
0
w=x+t+d
0
__ ..... 7
o
t d
w (c) Figure 7.19 Partilioning a circuil onlO IWO lookup lables: (a) desired circuit. (b) circuil partitioned inlo !!fOUpS with 31 l11os13 inpuls and I OUlpUl, (c) groups mapped 10 IwO 3-inpul I-oulpul lookup lables. -
Notice that the implementation with two lookup tables has a total of + = 16 1V0rds, compared to 32 words that 1V0uid have been present with a 5-input lookup table. Thus. partlllol1lng a CIrcUIt among small lookup tables an re -ult in better effi ienc\ than using one larger lookup table. This efficiency can be seen even more dramatically f r e,amples \\ ith rn re inputs. For example. the runctlon F - abc + de + ghi . , h \\n in Figure 7.20(a). has 9 inputs. Implementing the funcli n on a single lool..up tabk \\~uld
392
Physical Implementation
7.3 Programmable Ie Technology-FPGA 29
require a table wi th = 5 12 words . Ho wever. we can partition the c ircuit into groups such that each gro up has 3 input s and I o utput- th e firs t g roup wou ld compute abc, the second def . the third ghi, and the fourth would OR th e o utputs of the first three groups to ge nerate the o ut put F. Each gro up co uld be implemented us ing a 3-input I -output lookup table. meanin g 8x I memories. The res uitin g implementation wou ld have four such lookup tables. as shown in Figure 7.20(b). The to tal words for that fo ur-table implementa ti o n wo uld be a me re 8 + 8 + 8 + 8 = 32 wo rds-fa r less than the 512 words required for a si ng le 9-i nput look up ta ble. Figure 7.20(c) compares the relative si ze s of a 5 12-word and four 8-word memories. Notice the tremendous reduc tion in size.
!~, (a)
__ - ------------
8x2Mem. 0 00 00 00
8x2 0 1 2
393
Mem. 00 10 00 10
e- -_ _"""'~___..l (b )
a---.r::::;::::::::---, d- ' -r---....
e
~::!~:===(
512x l Mem.
~ 3-1 u a§ f
b C- r -'-.-/
F
d~ ~ _ 3'1
(e)
F 8xl Mem.
h (a)
(b )
(e)
Figure 7.20 Dividing a many- input circuit amo ng smaller lookup tables reduces totallooirup table size: (a) 9-input ci rcuit. (b) ci rcuit mapped to 3-input I-out put lookup tab les. (c) size savings compared to 9-input I-output lookup table.
Figure 7.21 Partitioning a circuit onto two lookup tables: (a) original cireuit. (b) transfonned circuit 4-IOput AND gate IOto two smaller ga tes ' and then that haws the 3-Input . I -output that breaks the . ) . groupIOgs. (c mappIOg of each group to a lookup table, with the group's function converted to programmed btls 10 the lookup table. Italicized bits are unused. In the previous example, notice that we did not use one of the columns in the first Ilook up table, and dtd. not use o ne of the columns in the second lookup tabl e el'th er. U· smg
ookup tables sometttnes results in unused me mory cells. Us ing lookup tables also somettmes results In unused loo kup table words, as illustrated in the follOwing example.
EXAMPLE 7.8 Mapping a 2x4 decoder to 3-input 2-output lookup tables Parti tio nin g a function amo ng sma ll look up tab les is m o re efficient than implementing a function o n o ne large look up tab le . But what is a "s mall" lookup table-a tab le with 2 inputs . 3 inputs, 4 inputs. 7 inputs. o r maybe even 10 inputs? Research e rs have conducted numerous s tudi es on large numbe rs of typical circuits, a nd found that 3- input o r 4-input lookup tab les seem to work best for most circuits. Furthe rmore . resea rc hers fou nd that 2-output lookup tables a lso seem to work weli for mo t examples. Thus. we' ll use 3- input 2-output lookup tab les from this point fo rward .
Let's implement a 2x4 decode r. without enable, using 3-input 2-ourput look'llP tables. A 2x4 decoder has two inputs..11 and 10. and four outputs, dO. d 1. d2. and d3. A mapping i shown in Ftgure 7.22. The equauons for each ou tput are dO = i 1 . i 0 '. d 1- i 1 . i 0, d2- iIi 0'. and d3=111 O. The lookup tables tmplement those eq uations using the top halve of the tables' words' the bouom halves are unused. .
EXAMPLE 7.7 Partitioning a circuit among 3-input 2-output lookup tables Implement the circuit shown in Figure 7.21 (aJ u ing 3- input 2-output lookup tables. We begin by trying to partiti on Ihe ci rcuit into groups such that each gro up has at most 3 inputs and 2 outputs. However. the 4-input AND gale prevents us from successfully perfonning such panitioning, because whatever gate Ihat group is in will have at least four inputs. To remedy this problem, we decompo,e Ihat gate into two smaller gates. while maintaining the same functionality. as shown in Figure 7.21(b). We can then partition the circuit into two groups. each wi th 3 inputs and l output, a,
0 il iO
tl
iO (a)
8x2 0 1 2 3
Mem. 10 01 00 00 a2 00 al 4 aO 5 00 6 00
0
dO dl (b)
8x2Mem. 0 00 1 00 2 10 3 01 a2 al 4 00 00 aO 5 6 00 00
d2d3
Figure 7.22 Mapping a 2x4 decoderto tw~ 3-input _-output lookup table : la) desi!\'d ireuit.lb) mapping to two lookup tables. ltaltCized btl are unused.
39~
Physical Implementation 7.3 Programmable Ie Technology-FPGA
An FPGA may come wit h tens. hundreds. or even thousands of lookup tables. and thus can implement large amoullls of combinational log ic.
We repeal Example 7 8 here us h FPGA h . inpUlS 10 Ihe fi rs t lookup lable :~; ~a:e as in Eo~vn 'In
external in ut ;0
Progra mmable Interconnects (Switch Matrices)
inputs
~::~~: t'h;:,~tg~';O~as~~sh Ih~ou.gh 10 swilch
P6 P7 -""
I-
iOS 1 sO i1 4x1 d~ Ii2 mux i3
(a)
malri x .output 00. which means Ihat eXlemal
0 0 i1 iO
2-bit
FPGA (partial) 8x2 Mem. 0 00
8x2Mem. 0 10 01 2 00 3 00 a2 a1 4 00 aO 5 00 6 00
memory
Switch matrix
c;,J
00
iOS 1 sO i1 4x1 mux i3
mO m1
10 d3 d2
1m3
--I-
00
1~~~d1
n
®
iO
(b)
(a)
Figure 7.23 A imple FPGA architecture: (a) an FPGA Ihal includes a swi lch matrix, and (b) the Ii " itch matri x's internal s , howing two 4x I muxes controlled by twO 2-bit registers. Note: real FPGA, have hundreds of lookup tables and swilch m3lrices, nOI jusl " felV.
OO~
11
"
1051 sO
~ i~ ~~~ df-2.l I~ i3
input~~
connect 10 the nghl lookup tables InpU ' Is. we ' ve successfully connected external inpuLS if and fO to IEhe second lookup lab I . Ie's in pu I's. as d' e Ire d. We program the Iwo lookup tables as we did in xamp e 7.8. Thus. external OUlpUIS dO-dJ can be found at the FPGA eXlemal pins as shown in FIgure 7.24(a). .
t t
_____
y connectmg . external input iI . and
. WI, C ma ln~ Outpul 00. We ach ieve thaI configuration by programmin 10 into ~~. to: 2-bl~ register In Ih~ switch ~aLrix , as shown in Figure 7.24(b). Likewise, we con~gure me li C :xt ~l. atnx ~~Ch tha t switch matnx ~npul 1113 pa sses through to swi tch matrix output 01. meaning ,ema. Input ~ passes through to switch matrix output 0 1. \Ve achieve that confi ouraLion b rogramlllJllg 11 I~to the boltom 2·bit register in the switch matrix. Because the switch matrix o~tputs
t t
mO m1 m2 m3
~i~U~ 7.23(a). We Coan easily gel the proper
x mp e ..
.
2-bit
00 00
.
FPGA .
memory
L~~~======l: pgP8
P4•. ~==~~ P5l:
.
I~e SeC:~d,~e ~ppropnale FPGA InpUIS. as shown in Figure 7.24(a). To gel the proper
Switch matrix
FPGA (partial) 8x2 Mem.
0
10
h ~ up tabl e, we first connect ex ternal input if and external input ;0 to the . 1," Puts t at reed 1010 the switch mmri x. We then configure the swi tch matrix such thaI swi
In the previous examples. we have been creating custo mi zed connections between lookup tables. However. the point of FPGA s is that the ent ire chip is prefabricated-including the wires . FPGAs therefore come with programmable illlereolllleels. sometimes called swilch molriees. which allow us to program the conneclions among lookup tables. Figure 7.23 shows a simple FPGA chip having six inputs (PO-P5), IWO 3-i nput 2-output lookup lables. one -l-input 2-ou tput sw ilch mat rix. and four OU lPU IS (P6-P9). All three of the left lookup tab le's inpuls come from the eX lernal inputs Pl . P2. and P3-that lOOku p table's inputs can ' t be changed. However. two of the right look up wble's inputs may come from eilher the left lookup wble's outputs. or from Ihe external input P4 and P5. The switch matrix determines which of those connecti ons will be made.
8x2 Mem. 0 00 1 00 2 00 PO 3 00 P1-t:~ 4 00 ~;1: aO 5 00 6 00 00
395
EXAMPLE 7.9 A 2x4 decoder on an FPGA with a switch matrix
~
iOS1 sO
L-.
il 4Xl
:E-!
I:;rtx
'-------'(b)
Figure H4 Implementing a 2,4 decoder on the FPGA fabric having a witch malrL': (a1 e.'temal co ~nect l ons. and pro~rammed bits In the lookup table - and switch matrix. and (b) a look inside the ~\V ltc h matnx. showmg the programmed connections between the Outputs and input . Italicized bilS
In the lookup tables are unused. The swilch matrix's internal design appears on the right of Figure 7.23. It consi ts of two 4x I multiplexers. The lOp mux connect Ihe sw it ch malri x output 00 to one of Ihe matri x' s four input, . The bottom mux connects thc output 0 / to onc of the matrix 's four inpui s. A two- bit memory (whi ch is ac tua lly a 2-bit register. but ca lled a memory for con· sistency with the memory in\ ide a lookup lable) holds Ihe two bits that set each mux' two select line . Thu,. we can program the de;ired connection; simply by writing the appropriate bil ~ into Iho\O two 2-bil me morie;,. otice that each ,witch matrix outpul can be configured independently of the other. In facl. we could even make Ihe same inpul appear at both output, . though that's probabl y not u~eful in tim FPGA desig n. We' lI illLl, trale the use of the switch matnx With an CX;1I11plc.
EXAMPLE 7.10
Extended seat belt warnmg light on an FPGA We arc, to i.mplcment the, ex tended seat belt warning light system f Example ~ . t't on the FPGA ShOW ~l In Figure 7.2~. (Figure 7. 19 showed how to partition a similar circuit in 1\\0 groups. \\; th
equations X c kps. and w + t + d. For this example. W + .) \\'e connect • . p. and 5 to the FPG Plll~ gOll1g to th~ len lookup lable. and \\ e progrnm thut lookup I,ble to implement the .fullcllon kps : tl!' shown In FIgure 7.2-. \Ve connect an utpul of the left lookup mble. rcprcsentlllg x . 10 the nght lookup table!. b) programming the ~\\ Itch man;" to ("(lnnect 0 to 0 . \Ve connec t t to the right lookup tnble also. b) connecting to an e\l~mJI pin lnn (tXt h..' ~\\ ilch Illtllrix input m2 . and then b) onfiguring the ~\\ itch Il1nIrh to ,,"onnl.: "'\ m2 t 0 1. \\"e then pn gram the right lookup tnblc to il11plcl1lcl1Ilhc function \ + t . as S.ho\\l1 in Figure -~ . -
396
7 Physical Implementation
Bx2 Mem. 0 00 t 00 2 00 3 00
:r' 0
s
7.3 Programmable Ie Technology- FPGA FPGA (partial) Bx2 Mem. 0 00 01 01 3 01 :~ 4 00 aD 5 00 00 6
aD 5 6 7
00 00 01 00
FPGA
w PO
---7 --Bfr-
01 DO
01 DO matrix
CLB oulput flip·flop '
6' (a)
397
(b)
m2 m3 Switch matrix
configuration n~
N
~ ~
Notice that. in the previous two examples, we implemented two differelll circuits using the sallie FPGA chip. To implement the two different ci rcuits, we merely had to program different bi ts inlO th e lookup tables and swi tch matrices. That's the appeal of FPGAsthey implement our circuit just by programm ing.
In the previous section. th e illustrated FPGAs were missing a critical element needed to implement general circuits. namely.jlip-jlops. Without flip-flops, FPGAs could not implement sequenti al ci rcuits. FPGAs may include a flip-flop w ith each output of a lookup table-two flip-flops in th e case of a 2-ou tput lookup table. The lookup tabl e and its flip-Oops IOgether are known as a configurable logic bLock. or CLB. A simple CLB i shown in Figure 7.26. Each confi gurable logic block has a 3-input 2-output lookup table, and has two outputs and two flip-flops. Each flip-Oop is loaded every clock cycle with the correspond ing lookup table output. Each output of the CLB can be con fi gured to either come from the output's flipfl op. or direct ly from the carre ponding lookup table output. That configuration is done by programming a I -bit memory (which itself is a flip- Oop, but we' ll call it a memory to avoid confusion), shown in Figure 7.26, thai controls a 2x I mu x for each CLB output. The output flip-flops enable us 10 implement cquential ci rcuits, that is, circuits having registers, on Ihe FPGA .
@laO
~?@l01
CLB Bx2 Mem. 0 00 1 00 2 00 00 00 00 00
l·bit CLB outpul-
Figure 7.25 Implementing the extended seat belt warning light circuit on the FPGA fabri c having a \\ itch matrix : (a) external connections and programmed bils. (b) n look inside the switch matrix, showing the programmed connec ti ons. Italicized bils in the lookup tables are unused.
Configurable Logic Block
CLB Bx2 Mem. a 00 00 00 00 00 00 00
~~~=tP7 N N
Figure 7.26 An FPGA 'th o· WI can fi gurable logiC. blocks. which contain flip-flops along with a looku table W ' .
EXAMPLE 7.11
e ve put
S In all the configuration memory bi t cells in the figure.
p
Implementing a sequential circuit on an FPGA W . h . 7'6 W firs e WIS 10 Implemenl Ihe circuit shown in Figure 7.27(a) on the FPGA of F connect a and b to the left lookup tabl e. and C and d to the right I k bl Igure .-. e . t 7 ?7( 00 up ta e throueh the SWlt h matrix as shown' F b' .h . In Igure .- c). We program the left lookup table to output the fun;oons a ' and . as s own In Figure 7.27(b). Likewise, we program the right lookup table to output C and d We program all the configurable logic block outpulS to connect to their flip-Hops by pro . . 1 mto the CLB Output configur::uion memories. as shown in Fi gure 7.27(c).·
grnmnung
s
398
7 Physical Implementation 7.3 Programmable Ie Technology-FPGA FPGA
. CLBs and switch matrices in commercial FPGAs are mo re complex than described tn thiS Chapter. For example. CLBs may contain two lookup tables. or direct connections to adJacenl CLBs to support carry chain . Switch matrices may contain more inputs and output and more flexible swi tching Options. Furthefl11ore. commercial FPGAs may also tnclude large embedded RAM memories for data storage. and embedded mUltipliers or multiply-accumulate units for fas t multiplications.
CLB
CLB
8x2 Mem.
o
00
Ot to
o o
y
w
Programming an FPGA
a
(a)
We ha ven ' t said anything ye t. about how we actually progra m the lookup table. witch ma tn x configuration memones, and CLB-output config urati on memories; in panicular, how do we get the program bits into the configuration memories? The configuration memories are all the lookup table memories. the swi tch matrix memori es, and the CLB -output configuration memories. Conceptuall y. programming is e nabled by the FPGA having all the configuration memory bit storage cells connected asone big shift reg iste r. That shift regi ster' bit storage cells are spread out acro s the c hip. so don' t represent a traditional register whose bits are u uall y in one place. but thtnktng of them as a shift register helps unde rs tand thei r connectiviry. Actually. storage cells connected as a shi ft regi ster are typically referred to as a scan chain . The FPGA will have an extra input pin for programming that erves as the hift input for the shift register. Another extra input pin ind icates that programming is taking place . During progra mming. we shift in the bits necessary to implement our de ired ci rcuit. Remember that the configu ration memory cell s onl y get wri tten during progra mming of the FPGA-during normal FPGA operation. those configuratio n memory cells become read-only. Thu , one can conceive of FPGA s whose configuration memories are made from programmable read-onl y memory technology (PROM . EPROM. o r EEPROM) , although today most FPGAs use RAM and flip- fl op components for configuration memories. RAM and flip-fl ops are used probably becau e those components need to be programmed quickly using the scan chain method. easily achieved using RAMlflip-flop components. but not 0 ea ily using EPROM or EEPROM components.
b
Leh looku p lable a2
0 0 0 0 0
at
aO b
0
Dl
399
DO
,
w=a' x=b'
0 ,/f 1 1 0 \ 0
i
\ Q----
l ',,
o ""r
,
"
1 ,
9-/'
below unused
w
(b )
(c)
. a sequenlW. . I Cifelli · ., on,·,n FPGA·. (0) Figure 721 ImplcmCnlllH! • desired sequenlial . .circuit. .. Ibl left CLB"S lookup table program bi ls. (e) programmed FPGA. Unused b'IS arc naltclzed Care sho uld be take n 10 avoid confus ing the o utPUI. nip-flops the mselves ~nd the CLB OUIPUI configura tion " memories··-the configu rall on memones s ~ore blt~ that program the FPGA to implement the desi red ci rc Uit. ~efore CirCUit op~rallon . while the OUlput flip-flops store the bits tha t the circui t loads dunn g CirCUli o pe ratio n.. The storaoe clements for the lookup table. the CLB OU IPUI configuration, and the '" itch matrice~. arc collectively known a an FPGA's cOllfigllrotiollmemory, although that "memory" is comprised of numerous smaller memories a nd even reg isters or flip-flops.
Automated tools that prog ram FPGAs usually start wi th a file containing the bits to be shifted into the FPGA c hai n-that file is known as a bit file . The tool that creates the bit file obvious ly mu st know the number a nd purpose of every bit ell in the FPGA scan c hain. so uch too ls will generate a different bit file for different FPGA devices.
Overall FPGA Architecture G rid of C LBs and switch matrices A commercial FPGA contains hundreds or even thou'and, of CL B, and switc h malrices, arra nged in a regular pallem on the c hip. A smllple arra nge ment i, shown in Fig ure 7.28. CLBs connec t with horito nWI a nd vert ica l rou ling chan nel,. whic h connect to ,witch matrices. A ,ample connec ti on of a CLB to the ro uting c hanneh i, , hown for the top cenlc r LB . The rou ling channe l, con,i" o f ten, of wires. represented in the Ilgure ju" as \Ingle bolded wire,.
EXAMPLE 7.12
Programming an FPGA This exa mpl e demonstrates programming nn FPGA for th e FPGA and de Ired circuit shown in Example 7. 11 . Figure 7.27 from Example 7. 1t showed Ihe required con lent of the c "figunuion mem ory on th e FPGA to implement the desi red ircuil. \\'c replicate the C' Oleots in
Figure 7.29(a). Ihis lillie illustraling the llIanner in
\I
hi h Ihe FPGA h3, the configllr:lti n
memory bits co nnected 3;:.. a scan chain. Figure 7.2:9{b) :-.ho\\ s h \\ that SClD ' haLO 'on epru-
Figure 7 28 FPG
arc hilecture.
ally forllls a ~ O-bil shift register. Figu,"" 7.29( ) .ho\\ $ Ihe ,'onlenl, of .1 bil rile thlt could be used to program th e FPGA to im plement (hI! desi~d circuit. \\'r ,:re:lled thJt bit til ~iJUpl~ b~ follOwing the d3Shcd line that represent!'. the scan ·hain. placing Is Jnd O ~ into the- bl( lile a.., we sec them in the figun! .
7 Physical Implementation 7.4 Other Technologies r -______________,FPGA
CLB
-
CLB
Pin
~
Pclk 0 0 a b
(a)
401
report FPGA size by saying a particular FPGA h "d . " 100 000 tica l " as a enslly of 100.000 system gates" or report' d yp be gates. These numbers are approximations, and many people view such e num rs very skepllcally (be ' . FPGA v d ' . cause somettme companies like to exaggerate). en ors mtght also descnbe FPGA size as the number of "10' bl ks" " lookup t bl " h' h . . gIc DC or a es, w tC tS useful when comparing sizes of FPGA h . th of logic blocks or lookup tables. s avtng e same type
FPGA versus ASICs and Microprocessors FPGAs arc less efficient than AS ICs in terms of de lay size and powe F I th " r. or examp e e . . f F CIrCUtt 0 tgure 7.22(a) could be implemented with a delay of ju t one gate-delay 'in a custom or semtcustom IC technology. However, when mapped to the FPGA of Fi e 7.26, thal CtrCU IL w tll have a longer delay- the inputs must pass through the left lookup lable (whIch may have a delay of two gate-delays), th rough tbe left CLB 's output muxes (another two gate-delays), through the switch matrix (another rwo gate-dela 5) through th~ nght CLB's lookup table (another two gate-delays). and finally thro ugh Yth~ nght ~LB s output mu xes, resulling in a total of ten gate-delays. In terms of size an ASIC Implementation of the circuit of Figure 7.22(a) would require about ?O Iran . ' whereas the FPGA implementation using two CLBs and a switch matrix ;;'0 Id StSlOrs. several hundred transistors. u reqwre
Ct':-s
Pin
-
Pclk L _____-=.:::======+-~===.i==+===~-__'.;;__'
Figure 7.29 Programming an FPGA : (a) all configuration bi t cells ex ist in a scan chain, (b) a scan chain conceptuall y is a big shift register. (e) a bit fil e's contents would be shifted in during programming-some relati onships between the file' s bits and configuration bit cells are shown.
How Many Gates Docs an FPGA Implement? We usually think of a di gital ci rcuit 's size using the noti on of "gates" to represent design ize. A design with 3000 gates is like ly bi gger than a design with 2000 gates. Of course, whether that state ment is true de pends o n the type of gate5 used in each design (e.g., because XOR gates are bigger than NAND gates, 2000 XOR gates may actuall y be bigger tha n 3000 NAN D gates), as well as the num ber o f inpu ts to each gate (a 20-i nput gate is bigger than a 2-i nput gate). Thus, a common method o f indicating de ign size for a circuit approximates the Ilwllber oj 2-ill/1l1t NAND gates tha t wo uld be required to implement the ci rcuit. So whe n we say lhat a c ircui t consist, of 3000 gates or 2000 gates, we typically mean that if th o~e c ircuiL~ were implemented using 2-i nput AND gates, they would require 3000 2-inpu t AND gate, and 2000 2- inpul NAN D gales, re5pectively. FPGA~ have lookup lab le, and swi lCh malrice'> in, ide, not gate" FPGA sizes are therefore typically reported by con,ide rin g how large of a ci rcuit made up of 2-inpul AND gale, could be implemented using the FPGA ;orc hilcc lurc. FPGA vendo may
An FPGA implementation of a circuit will therefore be slower and bigger than an ASIC ~mplementattOn of the same Ctrcutl. Some studies have shown that FPGA are approXlmately .1O t~mes slower, and 10-30 times bigger, than ASIC implementations of the same ctrcu tl. SlIntiarly, a circuit implemented on an FPGA may Con ume about 10 ttmes more power than when implemented on an ASIC. But the advantage of being a ble to program FPGAs immediately and for almost no cost. rather than hav ing to wai t weeks or months while spending tens of thousands of dollars. often o~rweighs those dt sadvanlages. . Despite the perfomlance, size, and power overhead compared to ASIC. FPGAs are sltll much faster than software on a microprocessor for many tasks. in pan because FPGAs can effectively implement concurrency. pipelining. and bit-level operations. Thus. FPGAs possess the programming fl exibility of software on a microprocessor. Yet approach the performance of an AS IC. representing an excellent implementation option for many designs.
7.4 OTHER 1ECHNOLOG IES In this section, we describe other technologies for physically implementing digital irc uits. Some of Iho e technolog ies are older technogies that are still useful for p~cuJar situations. Others are newer technologies that are beginning to gain popularity.
Off-the-Shelf Logic (SSI) IC Sometimes we need onl y implement a circuit having just a few gates. In these cas _ r milli os f using an FPGA may be overkill. as FPGA typicall. upport th usand gates. Likewise, u ' ing an SIC would al 0 be overki ll . For es "here" e only need a
.102
Physical Implementa tion 7.4 Other Technologies
vee
few 2.ates. we might instead use one or more. off-
the-,Ilelf lo!!ie I s. A logic IC typicall y contains a few. perhap: ten or less. gates connected directl y to the les pi ns. as shown in Fi gure 7.30. The IC shown has four AN D gates and 14 pins. One pin IS for power 10 the IC (known as VCC). the other for 2round (eND ). The re maining pillS connect 10 the fou r NO gates in the Ie. as shown in the figure. Diffe rent logic ICs have gate types other than AN D. such as OR. NAND, NOR , or NOT. To budd a small ci rcuit from these off-the-shelf logiC ICs. we would simpl y pl ace the ICs on a board and connect the appropriate pins. ICs wit h o ~'l y a few gates are known as Small-Scale IlIlegratroll chips. or 551 chips. 7.jOOlCs The most popular off-the-shelf SS I IC are know n generall y as 7400series ICs. A 7-100 IC ty picall y contains fo ur to six logic gales. and aboul 1-1 pins. A particul ar 7400 IC is hown in Fi 2ure 7.3 1. The IC measures about 112 inch across. The IC package shown has two rows. or line s, of pins, and is thus known as a dllal-illlille package. or DIP. 7-100 ICs fi rst became avail able in the earl y I 960s. The original 7400 chip had fou r NA 0 gates, and cost about S looo each. in 1962. That's riaht-S looo And that's in 1960s d~lIar . when' a U.S. engineer earned only abou t S I O.ooo/year. The price dropped igni fi cantl y during that decade. Lhanks in large pan to the u e of huge nu mbers of the devices by the U.S. Minuteman Mi ssile and Lhe Apoll o rocket programs. and has continued to drop since Lhen due to cheaper tra n iMors and huge vo lumes. Today. you can buy 74oo-series ICs for Ju~t ten~ of cents each. Parts with different gates have different pan numbers. Table 7. 1 , hows \ome commonly used 7400 pan l from
114 113 112 111
11
12
13
14
110
19
15
16
18
17
GND
Figu re 7.30 Example logic Ie.
403
Fairchild's 74LSoo subfamily of the 7400 series. In addition to basic gates. the table hows an IC wiLh 0 flip-fl ops. fu ll-adders, or a magnitude comparator. Pans also exi I for XOR. XNOR, buffers, decoders. multiplexers, up-counters, up-down-counters, and more. There are several different subfamilies of 74oo-series pan s-pans from a subfamily can be used with other pans from the subfamily, bUI generally not with pans from other subfamilies. The reason is Ihat Ihe voltage and CUrreOi sening of a subfamily are designed such that the ICs can be connecled without worrying about adjusling the voltage and current between ICs. The 74 series (e.g. , 7400, 7402. etc.), is the basic subfamily. based on a type of Iransistor known as TTL-designers using logic ICs today only use 74-series Ie if they must integrale WiLh old designs, and typically don ' t use the series for new designs. The 74LS subfamily (e.g. , 74LSOO, 74LS02) uses a special Iype of TTL technology known as ScholLky Ihat results in lower power and Slightly higher speed than the 74 series-the "L" in the name means low-power. the "S" means Schottky. The 74HC subfamily use high-speed (denoted by the "H") CMOS (denoted by the "C') Lransi lors. The 74F subfamily was introduced by FairChild, consi ting of fast (hence Ihe "P') advanced Schon.ky TTL logic. Numerous oLher 7400 subfamilies exist, with new subfamilies SLill being inlroduced. Funhemnore, additional series of off-the-shelf SSI ICs also exist in addition 10 the 7400 series. Another popular series is the 4000 series of ICs. a CMOS series thai evolved in the 19705 as a low-power alternaLive to Ihe TTL-based 7000 series. More series exi 1100.
EXAMPLE 7.13 Seat be lt warning implementation using oft-th e-shelf 7400 ICs Figure 7.31 7400-series Ie. TABLE 7.1: Common ly used 7400-series ICs. Description Pins Part 74LSOO
Four 2-inpul NA D
14
74LS02
Four 2-input NOR
14
74LS().I
Six invert ers
14
74 LS08
Four 2- input A
14
74LS 10
Three 3-input NA ND
14
74LSII
Three 3-input A D
14
74LSI 4
Six inveners (Schmil1 LTigger)
14
74LS20
Two 4-inpul NAND
14
74 LS27
Three 3-inpul NOR
14
AND
14
74 LS30
One 8- inpul
74LS32
Four 2-i npul OR
14
74 LS74
Two D fli p-nop. positi ve edge triggered. with preset and reset
14
74LS83
4-hll binary full-adder
16
4-blt 11Iagnllude comparator
16
74 L 85 \""'"
JI'I~ .. l '11
Usi ng 74LS-series ICs shown in Table 7.1. physicalJy implement the sea! belt warning ligbl circuil of Figure 7.1. shown again in Figure 7.32(a). We could implememihe invener using a 74LS~. The 74LS08 has 2-inpul AND gates. and we need a 3-input AND gate. A simple solution is 10 decompose Ihe 3-i nput AND into two 2-inpul ANDs. as shown in Figure 7.32(b). The final implementation is shown in Figure 7.32(c).
(a)
Figure 7.32 Implementi ng the seat belt warn ing circuit wilh 74LSseries ICs: (a) desired circuit. (b) circuit tran sform ed 10 lise 2-inpul
AND gates. (c) circuitmnpped 10 two 74LS I s. Additional connections not shown would be power 10 the 11 4 pin, and ground to the 17 pins on ench Ie.
(b)
(e) ____________________________________ .J
40-1
Physical Impleme ntation
7.4 Other Technologies
Preferably. we \\Q uld implement the circuit usi ng j U ~1 onL' IC. (0 reduce board size. cost. and power. onvcning the circuit to use only one type of gatl!. like AN D gates onl y, or NOR gUles onl y. could result in just one IC. For example. if we could t:onvcrt to 3-i npul OR gales. we could use the 74LS27 chip. \Ve s lart by conve ni ng the circui t to NOR~ onl y. as in Figure 7.33(1.1). We remml! the doub le in\'e rsion. and replace the si ngle in ve rsions by 3-i npul NOR gates. The im plementation u~i n g a 7-tLS27 Ie is shown in Figure 7.33(c),
'-:±'= i---f'-~,:-'-'-'-'''-'-''-'---''l figure 7.34 A basic example of a programmable logic device. (AND gales are wired·AND.)
, },--
) programmable node
~ r;~ , ~ ,
01
Figure 7.33 lmplementing Ihe seal belt warning circui t with one 74LS
IC. namely. the 74LS17 consisting of three 3·inpul NOR gales: (a) desired circuil transformed 10 OR gales with inversion bubbles. (b) circuit wiLh double inversio ns eliminated and si ngle inversion.s
,.'~-f]" unblown" fuse
" blown" fuse
(a) j - ---- -- ----- - -- --- i
:0
:
,
i
,
'
'w
replaced by I·input OR gales. (c) circuil mapped to a 74LS27 chip.
,,, ,
Additional conneclions not shown
"ould be power to the 11 4 pin. and ground to the 17 pin.
405
11 12 13
p :
i ~=f11==~t2~=t~3--lt4~1t5--lI6r--t7r ~'-._-4~-..-<_~""._-._-.-_.""'.~.....__.....J.~mmm ...
l __
(c )
... - -- - - - ------ - - --- -..! (b )
Simple Programmable Logic Device (SPLDI A programmable logic device. or PLD. is an IC tha t can be configured to implement a varielYof log ic functi ons. ranging from tens to thousands of gates. PLDs became popular in the I970s (thus predati ng FPGA s). as they could implement far more functi onality in a si ngle IC than pos ible usi ng SSI ICs. A PLD device comains a prefabricated circuit wi th a set of external inputs feeding into a large AN D·OR circuit structure. with the special feature that the user can configure (via "programm ing") which external input connect to the AND gates. For example, Figure 7.34 shows a basic PLD with three inputs feeding into three AND gates followed by an OR gate. The inputs feed into the AND gate in both true and complemented fomls. Each wi re feedi ng into each AN D gate pas es through a programmable node. which can ei ther pass the node's input to the node's outpu t. or di sconnect the node' input from the node's output. Thus. by programming the programmabl e nodes. we ca n program the PLD to implement a llY 3·term functi on of three inputs. The programmable node des ign varies among t y pe~ of PLD;. Figure 7. 35 shows two types. The type shown in Fi gure 7.35(a) is based on a fu ,e. A fu ,e conducts like a wire, un less we "b low" the fu se. meaning we pa;s a higher· than· norm al current through the fuse. causing the fuse to literall y burn up and break . A blown fuse obviously does not conduct electricity. The type .. hown in Fi gure 7.35(b) i, baloed on memory and n tran· sistor- we program a 1 into the memory to ca u,e the tran,i \lor to conduct. and a 0 to cause the transiMor to not conduct. We omit the detai l.. of how to program the fu ses or program the memOrI e, th e m ~e l ves. Memory· based PLD, ca l) u,uall y be reprogrammed, in contra" to fuse · ba ed PLD, that ca n only be programllled once and are known as
..-.------.+-...__._._..__ ~~~_~c;j programmable nodes
figure 7.35 Two Iypes of programmable nodes: (al fuse based. (b) memory based.
olle·time programmable (OTP) devices. Fuse· based PLDs are po I . I . . 1' " ". pu ar In e ecmcally nOIsy app Icatlon~, ltke space apphcauons, smce memories can have their contents changed from radl3uon In space. Th~y are also popular in applications demanding b.igh securIty, smce mahclous enemIes can t reprogram the device. Memory·based devices are more common. however. SInce they can be reprogrammed and thus reduce costs when we make deSIgn ~ h a nges . The memones used are almost always nonvolatile. meaning the memones don t need power to retam theIr stored bits. (See Section 5.6 for more info-nna. tlon on nonvolatIle memones.) . You might be wondering how those AND gate work when the programmable node IS programmed to dIsconnect an Input-how does the AND gate treat an input with no conneclt on? As a O. as a 1, or a something else? Actually. PLD don't use nonna! AND gates. Instead. they tYPIcally use what IS known as ·'wired·AND." Explaining how wired AND works .IS beyond the scope of thIS book, and instead the Subject of a COllISe on tran. slstor:level Clrcutts. For our purposes, we can thmk of a wired·AND gate as an AND gate that SImply Ignores unconnected Inputs. Real PLDs have more than just three t1 12 t3 inputs. three AND gates, and one output. PLD structure drawi ngs thus need a more concise way of drawing the ci rcuits. A concise method or drawi ng PLDs is shown in Figure 7.36. Such a drawing docsn't show the progrdm· mabie nodes. and simply utilizes an "x" to 01 indicate a connect.ion. In the drawing. wires that cros. each other are 110 1 connected unless ,,, an "x" exists at the cros ing. FunhernlOre. PLDIC : such a drawing uses a singk wire to repre em all the A D gate inputs. representing the figure 7.36 implified PLD dr:l\\;ng.
-H.. .;IO+.-oI"'.-c.--,. ,-; ------- -----]
-----------------------..!
~06
Physlcallmplementallon
7.4 Other Technologies
\\ in~xl · AND. T he li ~ lIre shows how we would use such n drawing to indicate the connec·
tion; needed to gCJ~crate the term 13* I 2 ' . The "x" on the left represe11ls 12 ' feeding into the top AN D gale. The " X' on the ri ghl ind icales 13 feed ing i11l0 Ihe lOp AND gale. EXAM PLE 1.14
Seat belt warnlllg light using a sim ple PLD
p
-- --- --- ----------------------.
\\'~ a r~
to impkllll.! nt the ~ ent belt warni ng light !:iv ... tem of Fi2ure 7. 1 1I ~i 1l 2 the PLD of Figure 7.36.
\\.~
ca n do ..,~ b) progral~ llling th e PLD as show n in Fi gure 7.37. \Ve ge nera te the des ired ten ll kps by p;og ram mi ng th~ con necti o ns ror the top A ND 2atc J!) shown. \Ve wa nt the botto m tWO AND gates ou tput 0, so th :lt th e OR gate' s ou tput equal s the top AND gatc'!:i output. We can achieve Os by ANDing an input with il.~ co mplement- the result of a*a ' I.!o. al\\3)!! O. The fig ure shows two ways of ~}(.· hic\in2 O!!. " iIh the mi dd le gate usin g j ust one I
w
;0
of lhe inpu~~. Jnd the bottom gale using all th ree inputs-the re ... uh is lhe same.
Figure 7.37 Seat beiJ warning system on a simple PLD.
PLDs Iypicall y have more than j ust one OUIPUI. Figure 7. 38(a) shows a PLD wilh IWO outputs instead of just one. Each ompul is an OR of up W Ihree terms. , . Many PLDs have a D flip-flop thai stores each OUIPU I s bl!. and Ihe PLD s oulpUI pill can be programmed 10 connecl from the OR gale oUlput or Ihe flip-flop OUiPUI, known .as combi nali onal or re2 istered outpul, respeclive ly. A PLD supponlllg comblllalionaUreglstered OUIPUI is show~ in Figure 7.38(b). 11
12
11
13
12
13
------ -- ---------- -- - - ------- --,'
:-~-~~~;~7
, ,
,,
: :01
!
PLO Ie :
1 __ - ______________________ _ _ _ ...
(a)
Figure 7.38
(0)
-------------------(bi----
PLD wilh IWOoUlpu15. (b) PLD ",ilh programmable regislcrcd OUlputS.
AnOlher eXlension is to allow Ihe PLD oUlput 10 be either the tnJe or complememed .alue of the OR gale or fli p-fl op output. using a 2x I mux controlled by a progr:llnmable bit Yet anOlher eX lension is for the oU lput 10 feed back 10 Ihe input array. One use of feedback is to implemem fu nclions wi lh more lenns. achieved by feeding bac k Ihe combi national OUiPUI val ue. Another very common use of feedbac k. achle"ed by feedlllg back Ihe
407
reg islered OU lput. is 10 implemem a slate regisler and control logic (i.e., a controller}-Ihe AND array gelS ils inputs from Ihe regislered oUlputs and eXlernal inputs. and Ihe OR gates then generale Ihe eXlernal outputs and Ihe next values for the state register. Some PLDs nOi only have a programmable AND array, bUI also have a programmable OR array, meaning Ihe OR gale can gel its inputs from any of Ihe A D gates. SPLD versus PAL versus GAL versus PLA Li ke so many names in Ihe rapidly evolving field of high lechnology, names for PLDs are a bil blurred and confusing. Originally ( 1970s). PLDs consisted of programmable AND arrays and programmable OR arrays, and were known as programmable logic arrays. or PUs . In Ihe mid- 1970s, a company named AM D (Applied Micro Devices. lnc.) developed PLDs Ihal instead had OR gales with fi xed rather Ihan programmable inputs. as in Figure 7.38 and Ihe OIher PLD fi gures we've shown, and referred 10 such device as Programmable Array Logic, or PALs ("PAL" is a regi stered trademark of AMD). PALs were origi nally fuse-based and hence one-time-programmable. A company named Lattice SemiconduclOr Corporalion developed a PLD using a memory-ba ed programming approach ralher Ihan fuses, resulting in reprogrammability. and referred to such device as Gelleric Array Logic. or GAL (which are registered trademark of Lattice Semiconduclor Corporalion). As PLDs became more complex (a well di cu in the next seclion). PLDs based on PAL or GAL architectures (PLA archi tectures seem to be prett), rare) became known as Simple PWs. or SPWs. to conlraSlthem with the more complex PLD varielies. Today. numerous companies manufacture SPLDs. and often state Ihat Iheir SPLD archilecture is based on "PAL" or "PAUGAL" architectures. wilh Ihe distinction bel ween PAL and GAL nol seemingly relevant in that comexl. SPLDs Iypicall y support lens 10 hundreds of logic gates.
Complex Programmable Logic Device (CPLD) As IC rransislor densilies grew in the 1980s. companies began to build PLDs 10 suppon thousands of gales. However. the PLD archilecture described in the previous ectioD does nOI scale well 10 thou ands of gate -who needs one big huge circuit of two-Ie"el logi 0 Inslead. architectures evolved Ihat consisted of numerous SPLDs on a in21e de,; e. connected using switch malrices (also known as programmable imer onnec~)-see e tion 7.3 for delails on swilch matrices. These devices today are lenO\\ n as Complex PWs, or CPWs. CPLD can Iypically implemem designs with thousands of gUles. SPLDs versus CPLDs versus FPGAs What's Ihe dilference among SPLDs. CPLDs. and FPGAs' In general. Ihe tenn PLD is used for devices thm support lens 10 hundreds of gates. CPLD for devices Ihat suppon thousands of gales. and FPGAs for devices Ihal suppon tens of thousands f gates 10 million of g31 • ~ Funhemlore. loday. SPLDs and CPLDs are almo t always nonvolatile. me:min; Ihe\ can store their program even after power is removed. whereas FPGAs are aIm ' t ;:;Jway~ volati Ie. meaning Ihey lose their program when power is remO\ ed--and thu~ must in lude external circuitry thOi lores the program in nonvolatile mem ~ and that progrnn ' Ih FPGA from IhOi memory on po\\ cr up of Ihe FPGA. FPGAs toda~ are likely, Iatile because of the wlIy Ihey are programmed using a s an chain. \\ hi -h is easy using flip-flops and RAM cells. bUI would be diflicull u ing nom lalile mcm ~ bit: . Ho\\ 'cr.
hysical Implementation 7.5 IC Technology Comparisons • 409 ,'unceptuall), any of SPLD" CPLDs and FPGA s could be made to be volatile or nonvolatile, and une might 'lI1tic ipate thai fulure FPGAs wi ll include FPGAs that are nonvolatile, ~ -to - ASIC
cOlllain custom. di gi tal c·IrCUI'ts having . hardware optim ized for high-speed low-power 'd VI deo compress . (k nown as eodees )-such pl atforms often contain ~ '. ion and. deco mpresslon co ecs or a Wide vanety of protocol s (e.g, MPEG 2 MPEG 4 H 264 ). th pl at form co Id b d ' .. ' , ,. , etc, ,Since e . h N u . e u e In different products supporting di fferent standards, An example IS t e ..expena platform from Philips. Furthermore, some platform SOCs contain FPGA In add ll ion to one or more microprocessors and custom di gital circuits on the Ie Exampl es mc lude the V,nex II Pro platfoml from Xilinx and the Excalibur platform from Ahera. DeSigners mig ht uti lize a platform SOC to prototype an ASIC, or to physically Illlplement a syslem In a fin al product.
Flows
An interc"ing new tec hnology that has evolved in the earl y 2000s is Ihat of creating an AS IC from an FPGA- ba,ed des ign, Many designers usc FPGA s for AS IC protolyping, The) 'hC auto malcd too ls 10 implement Iheir circ ui t on FPGAs, and Ihey then extensively lest Ihe ci rcuit in Ihe circ uit 's enviro nmenL for example, in a prolotype DVD player, The FPGA-based prolotype implementali on may be larger, costl ier, and more power-hungry Ihan an ASI C-ba,ed implementation, but can be very use rul for detecting and correcting err()r~ in the circuit. (IS we ll ;)~ for demonstrati ng the event ua l producl. Once satisfied with the circui t. dc~ig n e rs mi ght then use aUl o l11 ~lt ed tools to rci l11 plement the circuit on an AS IC. The AS IC imple mentation traditionall y did not ul ilil e any informalion from the FPGA implementat ion. Implementing large ci rcuits on AS ICs is a diffi cul t lask, even with automated tools. Nonrecurring engineering costs may exceed hu ndreds of thousands or even millions of dollar>, and fabricat ing the IC may take many week, or monlhs. Furthermore, any problem \\ ith the fa bricated AS IC may require a second fabri calion cycle, requiring additional \\cck, or month" Pro blems may arise in Ihe AS IC Ihat didn ' t appear in the FPGA due to the completely new implementati on of the circui t as an AS IC- perhaps timing problem, might arise, for example, due to the circuit being placed and routed in a complete ly different fash ion Ihan was the case in the FPGA . To ea,c the migration of a circui t From FPGA 10 AS IC, some FPG A vendors offer a 'truclUred AS IC approach. In a siruelllred A S IC approach, an automated tool converts the FPCA illlplelllell/(llioll to an AS IC imp lemenlat ion, in conLrast to converting the origillal circuil to an AS IC impl ementation. In oLher words, a truclU red AS IC will refl ect the lookup table and ,wi tch matrix truclUre of the original FPGA . However, the structured AS IC will nOI be programmable. and thu will have faster lookup tablCe and faster switch matrices, becau~e Ihei r conte Ill;, will have been "hard wired" in to the AS IC. The structured ASIC's cell~ can be preplaced . with only wires left to be completed to implement a part.icular circuit. The re,u lt i, les, I RE cost (tens of Lhousand!. of dollars rather than hundreds of thou,and, or mi ll ions) and le;s time-to-s il icon (weeks rat her than mOlllhs), as well as less chance of unfore~cen problems, The drawback is that the ASIC will be larger, slower. and more power-hungry than a tradi tional AS IC. bu t ti ll bellcr than un FPGA.
The advent of IC, contain ing a billion tran,btor has led 10 I ;, Lhat contai n what used to exi,t on multiple ICs, Thu;. a single I may contain dozen, or hundred, of microproces'Of>, cU'lOm digita l ci rcuits. memories, bw,cs, elC, An I with numerous processors, CU\i()m circuits. and memories is known as a System -oll-a- Chip , or S Oc. While many SOC, are creatcd by dc,ignw, for a pa nicular application (e.g" for a particular DVD player), other SOC, are crealed to be uscd in a variety of diffe rent appli· cauons . Such platform S OCs might conlai n prOCe"Of\ and ell ' tom circ ui ts specifically (or an apphc:lllon domain. For e~am pl e. a platform SO for Ideo processing mighl
7.5 IC TECHNOLOGY COMPARISONS Relative Popularity of IC Technologies
/" 2002 alolle. m'ari), 80 billiun l e s (o[ on /)'{Jes) were prodllced.
(Source: Ie '"sig/us McClean He{Ja r/. 200J.)
TABLE 72.: Sample 'to of new We've described numerous technologies in this implementations in various chapter. In this section, we' ll give you some idea technologies. Total is more than 100% of the relative popularity of some of those technol- due to overlap among categories, ogies. Table 7.2 provides the relati ve percentage of Technology % deSigns that were physically implemented in various technologies in 200 1, based on a particular ~S:-ta_n_d_ar _d_c_e_Il_ _ _ __ ___-_5_%_ study. The table considers each new unique design Gate array 5% only once, meaning that it doesn't mailer how :S=-y-ste-m---o-'-n--a---C-h- i-p------3-Q% many copies of the same design were manufaclUred. That table's data does not include off-the- :F::U::II-:-C:-U -:s:-to_m c:-_ _ _ __ ___'_w _"'_ shelf SS I ICs or SPLDs (both represent only a tiny CPLDIFPGA I O~ fraction of the IC market from a total dollars per- ~O=-t:-he-r-----------specli ve, and are thus often excluded from such 5'lsurveys). A different study describes 2002 IC reve- Sou ,t:<: Synopy , DAC 2002 panel. nues (as opposed to unique designs) totaling $11 billion as follows: standard cell 5~ Sb, fuji custom 20%, gate array 10%, PLDIFPGA 17%, and other 5% (source: WSTS, lC Insi2hts), Yet anoLher study lists 2002 ASIC revenues at S I 0.9 billion, PLDIFPGA revenue at- _billion, and SOC revenues at $7.6 billion (source: Busi ness Communications Company, 2003). Num bers from different studies vary: we provide these numbers just to !rive you a general feel for the popularity of the various technologies. Some general trends seem to include the increasing popu larity of FPGA . the increasing use of structured ASIC approaches, and the increa ing appearance of y remon-a-chip. The 10015 used to map digital designs to phy ical implememations, ollecti\elv known as Eleelronie Design Alltomation tools, or EDA , themselves fom) a market with re ve nu e~ of $3 billion in 2002. $3,6 billion in _003. and predi ted re\'enues of billion in 2006 (source: Ganner DataquesL 2(04).
Tradeoffs among IC Technologies Figure 73 9 i llusLrat~s the general tradeoffs anlOng the key I techn I gies dc_ -ribed in this chupter. Technologies toward the right an be more customized t a parti ulac d ired drcui t, and thus may have fustcr perfomlance, higher density (smaller chip for a giw n dn:uitt
b
-110
Physical Implementation
7.5 IC Technology Comparisons
lower PO\\cr. and larger chip capacil y (more circuils on " single chip). BUI such customized lechnologies \\ ill be more cosil y 10 design and wi ll lake time 10 design. Technologies loward Ihe Icfl are less cuslOmized 10 a particular desired circuit. and Ihus may be more quick ly a\ ail able and have lower design COSI. bUI al Ihe expense of slower performance, less densi lY. higher power. and less chip capacilY (fewer of our circu its on a single chip). More generally. lechnologies loward Ihe righl allow for more oplimizalion. Technologies to the left yield less oplim izalion. bUI yield easier design.
, ~t
~---~ l
E:
• FPGA • PLD
!!' ,
• Full-custom • Siandard cell (semicuslom) • Gale array (semicustom)
0>' e:
5}i ~:
Quicker availability .......-Lower design cost ......-
----.. Faster performance
- - Higher density ----... Lower power
- - Larger chip capacity
Figure 7.39 Tradeoffs among sc\eral lC technologies.
Easier design
More optimized
Furthermore. FPGAs and PLDs nOl only enable easier design , bU I may be reprogrammabie. a feature Ihat enab les changes 10 the circuit lale in Ihe design cycle, or even after the circui!"s IC has been deployed in a fina l product. Choosing an IC lech nology for a parti cular design wililherefore depend on the constraints imposed on Ihat design. If a design needs 10 gel 10 market quickly, Ihat constraint fa"ors PLD and FPGA lechnologies. If a des ign must be extremely fast, that constraint favors emicuslOm or full-cu Slom technology. If a design must consume very little power or lake up "ery little space. Ihose constrainls favor emicu 10m or full-cus tom technology. If changes 10 the ci rcuil are likely_ thai constraint favors PLD and FPGA technologies. Choosing the besl lechnology is a hard problem , requiri ng careful consideration of numerous compeling con traints.
Ie Technologies versus Processor Varieties IC technologies and proces or varieties are onhogonal imp lementation featu res. Two implementation feat ure are orthogol/al if we can seleci each independen tl y (in mathematics, orthogonal means forming a right angle). We know Ihatlhere are severa l proce sor varieties thai can each implement a desired system function . including a custom proce sor, or a programmable processor. Fi gure 7.40 ill ustrates that Ihe ch ice of processor variety is independent of the choice of IC technology. Point 1 illustrates the choice of implementing desired system fu nclionality using a cu tom processor circllit wi lh a fu ll -cu 10m IC technology. That choice re,ult, in a highly optimized de ign. Point 2 illu>lrates Ihe choice of implcmenting a cu'tom processor ci rcuit on an FPGA. While the ci rcuit may be optimized, the FPGA I lechnology results in a less-optimi7.ed implemcntalion (compared to fullcu"om) but an c;"ier de~ign . Point J illustrates the choice of implementing de ired system funcllonality as ,oftwarc execuling on a programmable procc\Sor, where the programmable
411
processor is implemen ted in standard cells. Point 4 illu trates the Custom .,/ • ( 1) .(2) choi ce of implementing software processor More optimized on a programmable processor, where the programmable processor is aClually implemented Easier design on an FPGA. Wh ile that concepi / ' may seem strange, a programmable processor is jusl another Programmable • (3) circuit, so Ihat circuil can be processor· (4) mapped to an FPGA just like any other circuil. Programmable processors mapped to FPGAs are in Gale Siandard Full-cuSlom fact becoming increasingly poparray cell ular. because a designer can Figure 7.4ll Ie lechnologies and processor varieties are choose how many proces sors to
onhogonal implementation features. Four of the ten
put on a single IC (perhaps the possible choices are shown. desioner wants 9 proorammable 0 . 0 o · processors on one IC), and because a designer cao put sln)e-purpose processors alongside programmable proces ors-all withoul havin2 to fabrlcale a new Ie. Of course, programmable processors can often be purchased as off-the- helf ICs. so a deSigner uSing a programmable processor may nOl have to worry aboul the processor's IC lechnology. But increasi~g l y, des igners must place a programmable processor within their own IC. coexlstlllg with other processors. When a programmable processor coexists on an IC along with other processors (program mable or custom)_ that pro!!Tarnmable proces or is often referred 10 as a core. Our discus ion of IC teChnologies and proce sor varietie has thus far assumed just one type of each Item (e.g., one type of FPGA). In reality. each type it elf has maoy varieties. For example_ dozens of differentlYpes of FPGAs are available. varying in their size. speed. power. co t. elc .. Likewl e, dozens of different rype of programmable proces 011; are avru lable. also varying In those features . And we know thai we can create different Iypes of cuslom processors, varying also in their size_ speed. power. etc. Thus_ each point II~ Figure 7.39 and Figure 7.40 IS actually a large collection of points that spread out in different dtrecllons on Ihe plots. and may even overlap with other types_ Funhennore_ other IC lechnologles as well as proces or varieties exist and continue to e\"ol"e_ We also point out Ihat a single IC may actually incorporale se"eral different IC technologies. So a single IC may have some circuits created u' ino full-custom technol02Y. and other circuils created using AS IC or even FPGA lechnolog~. Like\\ i' e. a single p;;;' cessor may h a~e dl.fferelll parts Implemented in different IC technologies. F r example. a common situation IS for a programmable proce sor 10 ha\'e it ' datapath implemented in ful l-cuslom technology. but ils controller implemented in ASIC technolo~\-the rens n being that the datapal h is very regular. while the ontTOlier is mo ' th uns~- rured combinational logic. In summary_ designers have a hllge number of choices in ch ' ing proc :;sor \':llielies and IC Ie hnologies to implement their s:nem' .
·H 2
1 Physical Implementation
1.6 Product Profile: Giant Video Display
Ie Technology Trend-Moore's law Under,tandi ng thc trends or IC technologies requires ~n o\V l edg e ~'" 100.000 of ~ loorc ', Law. il'l oore's LAw ro ugh I) state; that IC capac it y I to.ooo double, evcry 18 mo nth;. Figure Q; 1,000 Cl. 7.-1 I plots , uc h do ub ling. begi n!!? nin g with about 10 millio n tOO ';;' tran, istor, pCI' IC in 1997. The c 10 plot u,os a logarithmic ,ca lc fo r ~ the l'· ax is-each tick mark represcnl~ 10 {ime~ more than th e prc\ ious ti ck mark . The g row th Figure 1.41 The (rend of incrc than the 1997 Ie. In other words. the 20 15 IC is as powerru l as aboUl 1000 1997 IC,. Thi s increas ing capac it y trend has also resulted in the cost per tran· !-l istor dropping at nearl) the same astounding rate. The IC capacity trend has man y implications. One implicat io n is that digital designers ca n creale Illilssively paralle l designs that usc huge num bers of functional units and reg is ter>. to create high-perro rmanee systems not previous ly practical. The number or required tra nsisto rs ror suc h des igns might ha ve bee n considered abs urd just a decade ear· lier. Another implication is that the s ize overhead of FPGAs compared to AS ICs (about lOx) become, Ie,s rel evant . making FPGA s an increas ingly popu lar c ho ice in mo re sys· tem s. Ye t another implicatio n is that des igners increas ingl y need automa ted too ls to help build the ~e multimilli o n Lransistor circu its. and Illay increas ingly wish to use RTL and even hi g her l eve l ~ o r design (e.g .. C-based des ign ) as the method ror desc ribin g circui ts, Iea \ ing the re mai ning design to tools. A t ~ome point. Moore's Law must come to an end. because trans istors cann ot shrink to an infi nite ly ~mall ize. When th at end wi ll occur has bee n a s ubject of deba te ror many yea". Some people ha\e predi cted Moore 's Law wi ll continue a couple decades into Lhe
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LEOs have long been used to di play s im ple device status (e.g. , on or off) ..tex t messages. or even simple graphi CS. However, until recently. LEDs were o nl y ava ilab le in white. yellow. re~ . and green colors, Hnd were not very bri g ht. Thus. earl ier LED video displays were typica ll y small , used onl y a Sing le color. and were designed for IOdoor lise. However, wi th the deve lopment of the blue LED in 1993 . and the develop ment or brighter LEOs. ru ll color LED d isplays evolved that can
Traffic
lig hllt fin~
illclIlIdesceflllig
ill
(Illd red plastic em'er
413
Traffic light made from se\'eral hllfldred red LEDs
figure 1.42 LEOs arc replacing incandescent bulbs in Iraffic lights. as we ll as other areas.
disp lay video in much the same way as a computer monitor or te levi ion. even in unny o utdoor ~n vlro nm ents .. In ract. LEOs. being a semico nductor technology. have been IIn provlO" at a rate sllnd ar to transistor (w hich also use semico nductor technology). The Improvement has followed what is known as HailZ's LAw (the LED equivalent o f M oore 's Law), statll1g that the LED " nux per package" doubles every 18-2-1 mo nths. which has been the case ro r several decades. Due to thi s improvement. man y people predict that LEOs WIll repl ace incandescent lig ht bulbs ror home and office lighting. LEOs ha"e a lready begun to replace lOeandescent bulb in traffic lights. as illustrated in Figure 7.-12. . Fig ure 7.43(a) shows a large LED video display capable or display ing full-color Video on a 15 x 8 ~a rd scree n. Beca use each LED is relati vely large ( 1/8th of an inch Wide. fo r exa mple) In comparison to the pixe ls or a computer monitor. one has to tand several feet away from the LED d isplay to view the image wi th out notiCing the indi\'idua! LEOs. Ir we look closer at the LED disp lay. as seen in Figure 7.-l3(b). we can see the IOdl vld ua l lines or the displays. Ir we loo k even closer at the di splay. we can finallv the indiv idu al LEOs wi thi n the display. as shown in Figure 7.-13(c). That figure sho\\'~ ;:~ the LEOs are cl ustered Into groups or red. green .. and blue LEDs-each cluster represents o ne pIxel. For the LED Video d isplay shown 10 FIgure 7.-13 . each cluster or LEOs consi ts of five LEOs: two red. two g ree n. and o ne blue LED. Giant video displa~ are indeed Inte nded to be viewed from a dis tance. 0 mo t viewers don't see the indi\ idual LEOs.
2()()(h.
7.6 PRODUCT PROFILE: GIANT VIDEO DISPLAY In the late 1990, and 200(h. g iant co lor video di s play, became popu lar a t s port stadi ums. car dea le" hip'. ca, ino<;. rreeway bi ll boards. and various othe r locat i ns. Most s uch video d"play, utillLe a huge g rid or light-emitting di odes (LED,) driven by digita l ci rcuits. A light-emil/iug diode (LED ) is a semicondu ctor device that eilli ts lig ht when current pa,<'c, through the device. In conLras t. a traditio nal " incande,ccnt" lig ht bu lb em its light when c urrent p""e, throug h the bulb " internal filame nt. which i, a hi gh-res istance wire that heat' up and glow' w he n c urre nt fl ow' Lhrough the wire- the wire, however. doesn't hurn bc~du,e II " cnclo,cd in a vacc um or ine rt ga, "ithlll the bulh. BeclIu, c LED light come, rrom a ,em lcond uctor material and no t Imm a ho t g lowlIlg hl'lnlent in tl bulb. LEDs U'>C Ie" rower, ia't longer. ;lnd ca n ha ndle vihration' that would brea~ u regular light bul b.
one pixel (a)
figure 1.43 LED video di>pla) : (al a large LED di phI) (aboul 10) ard< \\ ide and - ~ ards tam. [h) a do,cr \ ie\\ ~ho\\ ing :lOoUI I ~qllan: yanl. (c) :l \ C'r) cl "e \ le\\ 'ho\\ mg ahout I 'Quare incn--Ib "pi ch" can be ,cell. each pi\cI h ~l\ ing :2 red l UPJXr-Il'f~ J.~ld lo\\t:r-nghll.'Ir pl \ "1 . ~ gre 'n \UPf"t.~ right and Itl\\ "r-Ieft of pi,el). and I blue LED (\'ellll'r 01 PileI).
~I~
Physical Implementation
7.6 Product Profile: Giant Video Display
A>sume we wan l to creme an LED video display capable of di splaying a nOx480 pixel video. where each pixel simply consists of one red. one grecn. and one blue LED. If each LED cluster has a width of just over 3/8 inch ( 10 millimelcrs) and a heighl of 3/8 inch. our displ ay will be rough ly 2-1 feet wide and 16 feet hi gh. Furthermore. our display wi ll contain over one million indi vid ual LEOs. because 720 * 480 = 345.600 pixels. and the LED, per pixel results in 1.036.800 LEOs. Controlling every LED using a single digital circuit wou ld require millions of output pins and miles of wire to connect all of the LEOs. Insteael. as depicted in Figure 7.44. an LED vieleo display is construcled of smaller and smaller co mponents. The LED display consists of an arrayal' small er components call ed /lollels. shown in Figure 7.44(a). The panels are large display components typica ll y designed in a modular fashion such that displ ay manufaclUrers ca n easily create custom-size video displays and repair broken components within a display simp ly by replac ing individual panels. The LED display panels are further div ided into LED lIIodllles that control the physical LEOs. shown in Figure 7.~{b ). An LED module is the basic display component and. depending on the design of the module. can cont rol anywhere from a few hundred to a couple thousand LEOs. For example. in designing a nOx~80 pixel di splay. we may want 10 use an array of 6x6 panels. where each panel consists of an array of 5x5 LED modules. Each LED module would then need 10 control an array of 24x 16 pixels. where each pixel is composed of three LEOs. The LED video display functions by div iding the incom in g video stream into separate strea ms for each panel. The pane ls furt her process the video stream by dividing the incom ing video strea m into even smaller streams for the LED modules. Finally. the LEOs modules display the video frames by controlling the LEOs to output Ihe correct colors for eac h pi xel. or LED cluster. LED Module The LED module controls the individual LEOs wi thin the video display by turning the LEOs on and off at the proper times 10 create the fi nal color images. Because each LED module can consist of thousands of LEOs. directl y controlling each LED would require too many wires. In stead. as shown on Figure 7.45, the LED within the LED module are connected in a matrix with a single control wire fo r each row and three control wires for each column (one wire for each colored LED within the LED clusters). In the fi gure. the LED module controller control s an array of 2x3 pixe ls, where each pixel consists of three indi vidual LEOs. for a total of 18 LEOs. But as shown. the controller u es only 9 wires 10 control those 18 LEOs. The wire aving using this row and column approach becomes even more significant fo r more pixels. An LED mod ule with 24x 16 pixel s and three LEOs per pixel would have 24* 16*3 = 11 52 LEOs. but the controller would requ ire only 16 w i re~ (one per row) plus 24*3 wires (three per column). for a total of onl y 88 wires.
,,
Panel Panel
Panel Panel
Module ,
Panel Panel
Panel
"\\
...
0
Module
...
...
0
000 000 ...
000 Panel
Panel
Panel
415
Panel
(b)
Q
Blue
Red
~~~
Green (e)
(a)
Figure 7.44 LED video displays are designed hierarchically: (a) Ihe LED d'lsPI . larger panels. which can be composed to create different sized displ"ys d ha~ conSIsts of several . d' . .. . an w lch can be In IVldually replaced to repair broken panels. (b) each panel consislS of several smaller LED modules. responsible for controlhng the IndiVidual pixels. and (c) each pixel . Con ISIS of a cluster of red. green. and blue LEOs. The LED module controller displays a video image by sequenlia lly scanning. or enab ling. each row and di splaying the pixel va lues for each
LED Module
column within the video image.
Controller
Us ing this teChnique. only one row of LEOs is illuminated at
Rl R2 R3
C2 C2 C2 (R) (G) (B)
any given time. However. the
The largest LED displtl}' in 2004 was J jeel wide by 26 feet wl/.
35
buill
fI.fillg
10
large FI'GA s, 323 lIIo(/erale-si:.e
FPGA.r. 333 flash II/l' lIm rie ,f, 1I11l1
3800 PLDs. (Sou rce: Xedl j (mmal. Wiml"
21JO.1).
LED module scans the rows fast Figure 7.45 LED module circuit consi ting of a matrix of enough such that the human eye red (R). green (G). and blue (8 ) LEOs controlled b\ the perceives all rows a being LED modu le controller. R IIR2IR3 are row I thro~eh 3. illuminated. and el fe2 are columns I and 2-thus the matri.• sh~wn is The LED module must 2x3 pixels. or 6 pixels total. with 18 LEOs total (3 LEOs con trol the LEOs to create the per pixel). desired color for each pixel. Each pixel wi thin a video frame is typically represented usinoe an RGB co Ior pace. An RGB (red/greenlblue) color space is a method to create any color of li2ht b dd' 0 'fi' .. . h f d ya tn . speCt c 1I1tenSllles. or bng rnesses. are. green . and blue colors. Each pixel within a -video frame may be represented as three 8-bi t binary numbers. where each -b'tI num be r peCt. fies the intensity of the red. green. or blue colors. Thus. for each alar. the LED od I 111uSt be able to provide 256 distinct brighlness levels. However. an LED by itse7f o~~ supports IWO values: 011 and off. or full Inlenstly and no intenSity. . . To support 25.6 brightness levels. the LED module controller u e pul e width modulal1 on. In pulse IIIld,h lIIodulatlOlI (also known as PWM). a controller dri\es a wire \\ ith a 1 value for a specific percentage of a time period-the signal being 1 is kno\\ n as a pulse. the duration of the 1 is known as the pulse s width. and the pen:-enta2e of the period spent at 1 is kno\ n as the dilly cycle. When thm pulse drive ' an LED: a \\ ider pulse causes the LED to appear brighter 10 the human eye. Figure 7A6 illu>t:rates ho\\ the LED module controller uses pulse width modulation to suppon \ ariou, brighrn -, le\eIs for the LEOs. To illuminate an LED at full brightne s. the controller 'impl~ Jri\C, the
416
Physical Implementation 7.8 Exercises LED with I for the entire period . as shown in Figure 7.46(a). To illuminate the LED at half brightness. the controller uses a pulse with a 50% dUl y cycle. as shown in Figure 7.46(b). For 25% bri ghtness. the controller sets the pul se to I for 25% of the period. mean ing a 25 % dut y cycle. as shown in Figure 7.46(c). For an LED video di splay. the LED module cont roll er divides the length of time each row is scan ned into 255 time segments. and cont rols the brightness of the LEOs by tu rni ng each LED 0 11 for 0 to 255 time segments. thereby support ing 256 levels of intensity.
,
(a) ~ (b )
(C )-{l
Period 1
,,
.. 1'-
Period 2
,,
"i·
,,
Period 3 "
: III
r r r
Period 4
.,
download ing a bitstrcal1l into the FPGA I device. One might notice the , imi larity of tlwt task wllh the t~. k .01' implement ing functionali ty on a microprocc>sor. which also involve, down ioadlllg bus Into an Ie device. Thu,. Ihe diff Tence between so ftw:lfe on a microprocessor and cu, tom digitnl ci rcuits continue, to be blu rred "pec iall y when one can. iders that modern FPGA., can al,o incl ude one or several l1l icrop rocc;.sor. with in the sa llie I . For more IIlfOrmallon n the blu rri ng. ;.ec "The Soft ening of Il ardware." F. Vahi d. IEEE COlllplller. April 200
,,
~
7.8 EX ERCISES SECTJOI 7.2: ~ I A N U IOA CT U R E D I C TEC II NOt.OG I ES
~·S 7. 1 Explain why gale nrray I lechnology.
OJ gale ar~IY Ie hav i." g th ree rows. the firM row IHl vi ng f( ur 2-illplil AND sale.... lhc ~ccolld :OW h~v lng ~our 2-lllplil OR gale ... , and Ihe th ird row huv ing lour OT gale!'.. Show how to IIlSla n li atc wm:~ 10 the gate array to implcmclIl the lum:lion F (d b e) - ab +
7.3 Omw
a'b' c'.
7.4 A" ulnc
Gs 7.5
it
. .
~~tlndard cell library h,n...
;1
2: inpu l A D g Ule. n 2-inpul OR gale, und a NOr
C
g UIC.
Usc ;:1 dr;:I\\.I.11lg 10 , how how 10. 1I1 . , ~an ~ta l e and place M:mdard cc ll ~ On ;:IIl I :.tnd wire Ihem ~ oge lhc r ,to Implement the function 111 Ex ercise 7.3. Draw yo ur cl.! l1 ~ thl.! ~all1e ... i ll.!!.i~ Ihe galc~ 111 Exercl!)c 7.3. and be ~ u rc your row ... ;:Ire of equal ... i/c.
Ie
Draw II gal e ;:1"::1)' Iw vi.ng three rows, Ihe fi rst row havin g four 2-illpUI AND gales. lhe sccond r~w ha~ lI1g f~u r 2-lIlpul OR galC!), unci the third row havi ng fOllr NOT gUles, Show how to Illslanllalc wires t Ihe galc arra), 10 implcmclll the equtlliull F (a , b , c .d )
a ' b + cd + c ' . 7.6 As ume " "Iandard cell li brary ha, a 2~ i nput A D gate. a 2-il1l>ut OR gate. and a NOT gate. Usc a dr:)\vlIlg 10 ~how how 10 II1:,wnlm Lc and place ... tandard ce ll ... on an I and wire Ihem IOgcth er to implcmcnl Ihc runction in Excrcil"c 7 .5. Be ... urc to draw yuur cell , Ihe '3me 'lizc a!o. the gnlc~ in Exc rci ... e 7.5. and be "'lIre your rows ure o f equal ')i/c. . -
7.7 CHAPTER SUMMARY In th is chapter, we discussed (Section 7. 1) the idea thai we must map our circuits to a physical implementati on so that those circuits can be inserted into a real system. We introd uced (Section 7.2) some technologies that require th at a new chip be fabricated to implement o ur circuit. Full-custom technology gives the most optimi zed implementation, but is expensive and time-consuming 10 design. Semicustom technologies give very good implementati ons while costing less and taking less time 10 des ign. through the predesignin g of the gates or cell s that will be used on the IC. We described (Section 7.3) the increasingly popul ar technology of FPGAs. and showed how a circuit could be mapped onto a set of programmable lookup tables and switch matrices. We highlighted (Section 7.4) several other technologies, including off-the-shelf SSI/MSI ICs. and programmable logic devices. We gave some data (Section 7.5) showing the relati ve popularity of the technologies described in the chapter. An interesting trend in physical implementation is the trend toward programmable ICs (FPGAs in particul ar). Impl ementing functionality on an FPGA involves the task of
technology ha... II :-.honcr prmJucliulI lime thull fu lJ.CU ... lol1l I
7.2 Ex~lain why Ihe u,c of NAND or lOR gale' illu CMOS gmc ttrray clfell il ill1pl cmc l1l~ili on i ~ IYPlc:lily preferred o\er all AI O/OR! OT 1ll1plcIl1Cnial lUil 01 :t 1:11"CUll .
Figur. 7.46 Pul se widlh modulation can be used 10 create various LED brightness levels: (a) for full brightness. the LED is always on. (b) for half brightness. the LED i" tumed on 50% of the time. and (c) for quarter brightness. the LED is turned on 25% of the time. Because an LED module cont roller must prov ide precise ly timed signals at a fast rate. custom processors are commonl y used rather than just microprocessors. FPGAs are a common choice for impl ementing those custom processor circuits in LED video di pl ays. due to several reasons. First. FPGA s are fast eno ugh to support the required scan rates. Second, the circuit on the FPGAs can be easil y changed, making it possible for the di splay manufacturer to fix bugs in the c ircui!. and even upgrade the circuit, without req uiring the high cost of creati ng a new AS IC. Third , the di splays themselves are fairly large. expensive. and consume much power. and therefore the larger size. higher cost. and more power consumption of FPGA s compared to AS ICs do not impact the overall display's size. cos!. and power 100 signifi cant ly.
.j 17
7.7 Consider the imp lcmenlalions or a Imlf-addcr wil h a gale array in Figure 7.4 ;:lI1d with Mundard
cells in Figure 7.6. A" ul1w each gate or cell (including inverte",) I"" a delay of I n". Abo assume th?t every II1 C ~ of w ire ( ~or each II1ch .111 your draw.ing. nOl an an (lcilial I ) h~ a delay of 3 11 ... (wire:, arc re lall vc ly ~ I ow 111 the Cr.l of li ll y fa l,l lran"'I'o tor\ ). Li l11~l t c the delay of the gate array and the standard ce ll circu its.
Gs 7.8 For your soluti?ns to Exerci"es 7.3 and 7.4. ' " ume that cuch gate and cell ha, a delay of Ins. and Ih;'1( evcry Inch .of w ire ( for ench II1ch 111 your dm wlIlg. not on an actuu l Ie ) co rresponds to n delay of 3 ns. E~llInat e lhe del ay~ of the gme arra y and ~Ianda rd cell circuits. ~
P LUS
7.9 Draw a circui t using AN D. OR. and OT gates for the following equation: F( a . b . c) a ' be + a be ' . Place inversion bubbles on that circuit to conVert the circuit to: (a) NAN D gates onl y. (b) OR gate, only.
_
7.10 Draw a ci,,;uit u s i~g AND; OR. and OT gates for the following equation: F( a . b . c) _ a be + a + b + e , Pl ace II1vers lon bubbles on th at circuit to con\'ert the circuj t to: (a) NA D gates only. (b) NOR gates onl y.
r
.U S
Physical Implementation 7.B Exercises
7. t I Ora\\' ~I circuit using AND. OR. and NOT gales for the following equation: F( a . b. C) "" (a b + c) (a ' + d) + c '. Convert the circuit (0 a circuit using: (a) lAN D gates only. (b) NOR gnles o nly.
7.12 Draw a circu it usi ng A 'D. OR. and NOT gales for the following equation: F ( w . x . y . z) "" (\'1 + x) (y + z) + \'/Y + X Z. Convert the circuit to a circu it using: (a) NAND ga tes o nl y. (b) NOR gates onl y. 7.13 Draw:l circuit Ll silH! AND. OR. and NOT gates for the following equat ion: F ( a , b , C , d ) =(a b) (b ' + c) ~+ (a d + c ' ). Con ve rt th e circuit to a circ uit using: I
(a) NAND ga tes o nl y. (b) NOR gates o nly.
7.14 Create
J
template for convening a 3-inpul AND gate to a ci rcuit using only 3-input NAND
gates .
7.15 Create a template for converting a 3-inpul OR gale to a circui lllsing onl y 3-input NAND gates. 7.16 Crea te:1 Icmplale for converting a NOT gate to a circuit using only 3-input NAND gates. 7.17 Ass ume a standard ce ll library consisting of 2-input and 3- inpu t NAI D gates with a delay of I ns each. 2-input and 3-i nput A D and OR gates with a delay of 1.8 ns each. and a NOT gate wi th a de lay of I ns. Compare the number of transistors and th e delay of an implementation using only ANDIOR! OT gates with an implemen tation using only NAND gates for the function: F ( a . b , c) =a b ' c + a ' b. For calculating the size of an implementation. assume each gate input requires IWO transistors. 7.18 Ass ume a s tandard ce ll library consisting of2-in put AND and OR gates wit h a de lay of Ins each. 3-in put AND and OR gates wi th a delay of 1.5 ns eac h, and a NOT ga te wi th a delay of I ns. Compare the number of tran sistors and th e delay of an implementation using only 2- input AND/OR gates and NOT gates with an implementatio n using o nl y 3-input AND/OR ga tes and NOT gates for the functi o n: F (a , b , c): a be + a ' b ' e + a' b ' e '. For calculating the size of an implementation. assume each gate input requires two trans istors.
7.22 Show how to implemcllI on Iwo Bx2 Mem. 3-input 2-ou tput lookup tab les the fo llowing function : F (a . b . e , d) a ' bd + b' cd ' . Assumc the two lookup tables arc connccted in the manner shown in Figure 7.47. You may not need to use every lookup -... a2 table Output. -... al 7.23 Show how to implcmen t on two 3-inpul 2-ou tput lookup tables the following function s: F(x , y . z) : x 'y + xyz ' and G(w , x . y , l) : w' x ' y + vi' xy Z ' . Assume the two lookup tables are connected in the manner shown in Figure 7.47.
419
Bx2 Mem.
a2
a1
-"" ao d1 '-----"r---';
d1
dO
Figure 7.47 1\"0 3-input 2-outpu t lookup tables Implemented using 8x2 memory.
7.24 Show how to implement on two 3-input 2-ouput look up tables the following function s: F ( a , b . e . d ) - abe + d and G "" a'. You. mu~t implement both F and G with only two lOOkup tables connected in the manner shown In Figure 7.47. 7.25
I m~lement a 2-bi t comparator that compares two 2-bi l numbers and has three outputS indicating greater-than, less-Ihan, and equal-to, using any number or 3-input 2-output loo"-.'1Ip tables and Custom connections among the lookup tables.
7.26 Show how to implement" 4-bi t carry-ripple adder usin g any number of 3-input 2-inpu t loo~-up tables and cll stom connectIOns among the lookup tables. Hint: map one full-adder to each look up table. 7.27 Show how to imp leme nt a 4-bi t carry-rippl e adder using any number of 4-input t -oUtpUl lookup tables and custom connec ti ons among th e lookup tables. 7.28 Show how to implement [1 comparator that compares two 8-bit numbers and has a sin21e equal-to output. using any number of 4-inpul I-output lookup tables and custom onnecti;ns among the lookup tables.
7.19 Ass ume a stan dard ce ll library co nsisting of 2-i nput NAND and NOR gates with a delay of I ns each. and 3-i nput NAND and NOR ga tes with a delay of 1.5 ns eac h. Compare the numbe r o f transis tors and th e delay of an implementati o n usin g on ly 2-inpu t AN DINOR gates with an implementation using only 3-input NANDINOR gate s for the function: F ( a , b , C): a ' be + a b' e + a be ' . For calculating the size of an impleme ntation. a~s ume each gate input requires two transistors.
7.29 ~how the bi t file necessary to program the FPGA fabri c in Figure 7.29 to implement the functi on F (a , b , e ,d ) = ab + cd. where a. b. e. and d are exte rnal inputs.
SECTIO ' 7.3: PROG RA MMABLE I C TECHNOLOGY-FPGA
7.31 Show th e bit file necessary to program the FPGA fabric in Figure 7.29 to implement the function F (a , b, e, d) = a ' b' + e ' d. where a. b. e. and d are external inputs.
7.21) Show how to implement o n a 3-input 2-output lookup tabl e the function F (a , b , c) :
a
+
be . 7.2 1 Show how 10 implement on tWO 3-input 2-output lookup tab les the function F (a , b , e ,d ) : ab + cd. A ~s ume you can connect the lookup tables in a custom manner (i.e .. do not use a switch matri x. jU~1 directly connect your wire ).
7.30 Show the bit file necessary to program the FPGA fabric in Figure 7.29 to implement the funcIton F (a , b . e . d) : abed. where a. b. e. and d are external inputs.
SECTION 7.4: OTHER TEC HNOLOG IES 7.32 Use any combination of 7400 ICs listed in Table 7. 1 to implement the function F (a . b , e . d)
: a b + cd. 7.33 Use any combinati on of74oo ICs listed in Table 7. 1 to impleme nt the functi on F( a , b . e. d )
= abc + ab'e' + a ' bd + a'b ' d ' . 7.34 By drawing XS on the circuit. program the PLD of Figure 7.38(0) to implement a full-adder. 7.35 By drawing Xs o n the circuit. program the PLD of Figure 7.38(a) to implement a ~-bit equality compara tor. Assume the PLD has an addi tional 14 input. 7,36 *(a)Design a PLD device capa ble of supportin g a 1-bit carry-ripple adder. B, drn\\ing ·s on your PLD circuit. program the PLD to implement the 1-bit arT) -ripple adder -
J
.UO
Physical Implementation (b) Using a CPLD device consist ing of several PLDs frolll Figure 7.38 and <.Issu ming you can connect the PLDs in a clistom manner. impJcmcllI the 2-bit c:1rry-ripple adder by drawing
Xs on Ihe PLDs. (c) Compare Ihe size of your PLD and Ihe CPLD by delermining Ihe gales required for bolh designs (make sure you compare the number of gales within the PLD and CPLD and not the number of gates used for your implementation).
SECTION 7.5: IC n:CHNOLOGY COMPA RISONS
Programmable Processors
7.37 For each of the sy stem constraims below, choose the 1110S1 appropriate technology from among FPGA. standard cell. and full-cu stom Ie technologie s for implementin g a given circui t. Justify your answers.
(n) The system must ex ist as a phys ical prolOlype by next week. (b) The sys tem shou ld be as small and low-power as poss ible. Short design time and low cost are /lat priorities. (c) The sys tem should be reprogram mabi e even after the final product has been produced.
(d) The sy lem should be as fasl as possible and should consume as lillie power as possible. subjec t to being completely implemented in just a few months. (e) Only five copies of the syslem will be produced and we have no more Ihan S 1000
10
8.1 INTRODUCTION
rDigital h
circuits des d ..c' . Igne to pell ornl a slJ1gle processlJ1g ta k. such as a seat belt warning Ig t. a pacemake r, or an FIR fi lter, are indeed a very common cia s of digital circuits. We ;Ighl refer to a circuit perfornling a single processing task as a sil/gle-purpose processor. IJ1gle·purpose processors represent a class of di gital circuits enabling tremendously fast or power·efficlent compulation. However, another class of digital circuits. known as programmable processors, is a lso extreme ly popular, as well as being more widely known. The progra mmable processor is largely responsible for the computing revolution that has take n place in the past severa l decades. leadi ng to what many call the infonnation age. A programmable processor. also know n as a gel/eral·purpose processor, is a digital circuit whose panlc ular process ing task is stored in a memory. rather than being built into the CirC Uit Itself. The representat ion of that processi ng task in the memory is I...11own as a program . Figure 8. 1 illustrates single·purpose versus general-purpose processors. We could creale a custom digi tal circuit for a seat belt warning light system (Chapter 2) or an FIR filter system (C hapter 5). or instead we could program a general-purpose processor circuit 10 Im plement those systems.
spend
on all Ihe ICs. 7.38 \Vhi ch of the following implementations are "at possible? (I) A custom processor on an
FPGA . (2) A cuslom processor on an ASIC. (3) A cuSlom processor on a full,cuslom IC. (4) A programmable processor on an FPGA . (5) A programmable processor on an AS IC. (6) A programmable processor on a full -custom Ie. Explain your answer.
3'lap FIR filter
Other
program
programs
Seat belt warning lighl single·purpose processor
3'lap FIR Ii Iter single·purpose processor Figure 8.1 Single.purpose versus geneml'purpose processors.
General·purpose processor
-'22
Programmable Processors 8.2 Basic Architecture Some programmab lc processors. like thc well-known Intel PCllIium processor or Sun', Spare proce"or. are illlended for use in dcsktop computers. Other programmable proces,ors. l i~c ARM. MIPS. 805 1. and PIC processors (whi ch arc widely known in the design community bu t kss known by the ge nera l public). arc illlendcd for embedded sys· tems. like ce llul ar telephones. automobiles. video ga mes. or even tennis shoes with blinki ng lights. Some programmable processors. like the PowerPC. arc intended for both de -ktop and cmbedded domai ns. A benefi t of a progra mmabl e processor is that its circuit ca n be mass-produced and then programmed to do almo. t anything. Thus. the same programmab le desktop processor can fun \Vind ows 98. \Vindows XP. Linu x. or whateve r new operating system program co mes aboll l. Likewise. that same processor ca n run appl ica ti on programs like
word processors. spreadsheets. video games. web browse rs. ctc. Furthermore, the same program mable cmbedded processor can be used in a cel l phone. automob ile. video game. or tenni, shoe by programming the processor for the des ired process ing task. Mass-production resu lts in low costs due to amorti zat ion of design costs (sec '"Why such cheap calcu lators"" in Chapter -' fo r a discussion of amortization). Of course. because programmab le processors arc ma s- produced and then used for a wide \'ariety of applications. there aren't as many unique programmable processor designs as there arc single-purpo e processor desig ns. It follows then that there are far fewer programmable processor designers than there arc single-purpose processor designer.
evertheless. even th ough you may never desig n a programmable processor as
part of your job. it i interesting and enlightening to understand how such a programmable processor works. Some people argue that people who understand how a processor works are even better software programmers. And tec hnology trends have led to the situation of des igners being able to create semi custom processors ("appl ication-specific" processors) that have ju t the right archi tecture fo r one or a mall number of applications, making knowledge of programmable processor designs important. Finally, there are indeed peop le who do de ign programmable processor architectures. and you never knolV if you might end up being one of them. In this chapter. we show how to design a simple program mable proces or using our prc\iously-described digital design method Our purpose is mainly to demystify these device~ and to provide an intu ition of how programmable proce sors work. We point out that real mass-produced proces ors are designcd using different methods. and their designs can be much morc complex than the de ign described in this chapter- learning about those proce. so,,' designs is the subject of many textbook. on computcr architecture.
8.2 BASIC ARCHITECTURE A programmable prOce%or consist of two main parts: a datapath and a cont rol unit. We' ll provide a genera l imrodu ti on to those two parts in thi , ,ccti on. then we'll provide a more detailed look at tho,c parts in a subsequent scction.
423
Trallsformin g that data. meaning perfomling some computations with that data that result 111 new data. and Storillg the new data. meaning writing the new data to some output locations.
h ~or example. a SCat belt warn ing sy tern reads bit data from sensors representing w et er a seat belt is fastened and whether a person is sitting in a eal. transforms that data by com put1l1g a new bit indicati ng whether to tum on a warning li oht. and writes that new. data to a warning I"Ight. An FIR fi Iter read data represenllng . thee most recent set of ' Input SIgnal samples. tran form s that data by performing multipli es and add. and writes new data to an output representing the filtered signal. A data memory holds all the data that a programmable processor can access. as input data or output somehow r-------~ connected data-for now. assume the word in that data memory to the are somehow connected to the outside world (e.g .. to outside the seat belt sensors or to the FIR input and output world SIgnals). To process that data. a programmable processor needs to be able to load data from data memory into one of several registers (typically a reoister file) within the processor. need to be able ~o feed data from some subset of registers throuoh functional units that can perfoml all ;os ible trallsformatioll operations (typically an ALU) we might consider wit h results stored back into a register. and needs to be able to srore data from a regi ster back into data memory. Therefore. we ee the need for a programmable processor to inc lude the basic circuit shown in Figure 8.2. showing a data memory. regi ster
fil e. and ALU. That circuit is known as the programmable processor s datapat" . The basic datapath shown in Figure 8.2 can perform the following po _ sible datapat" operatiolls in a given clock cycle:
Figure 8.2 Basic datapalh of a programmable processor.
Load operatioll: Thi s operation loads (reads) data from anv location in the data
memory into any register in the register file . A load ope';tion is illustrated in Figure 8.3(a). ALU operatioll: This operation tran form s register data by p sing am two fegi -ter through the ALU configured for any of the ALU' supponed -ope~tions . ",;"d
back 111tOany regtster of the regIster file. An LU opcrmi n is illustrated in Figure 8.3(b). Typical ALU op~rations include addition. subtraction. logical A..;U. logical OR. etc. Store operatiol1: This operJtion stores (write) dara from an~ regi -ter in the regi.ter fi Ie to an)' data 111e1110ry location. A store opemtion is illustrated in Figure '.3( ).
Basic Datapath We can view procc"lI1g generally as: data. meanll1g reading the data on wh Ich we ",i,h to work from some Input locution,.
Lnlldllll(
These possible datapath .operations are ill ustrat~d in Figure .:. E:tch ,uch opcnti n requires the appropnaw setllng ot the c?ntrOl I11putS f the uara mem 1\ . I11U'. re!!i~ter file. and L - those control 111pUtS wlil be sho\\n shortl~. For n(\\. Just familiarize
Programmable Processors
8.2 Basic Architecture
, ourse lf \\'ilh Ihe basic dalapalh's abililies. NOlice Ihm Ihe dmapalh in Figure 8.2 cannol direcll Y oper:lIe on dala memory locmions wilh Ihe ALU in one clock cycle. because lhe dOIa n1l,,1 firsl he read inlo Ihe regisler file . which ilse lf requires a clock cycle, before lhe dala can be opcralcd on by Ihe ALU. A dalapalh Ihm requires all dala 10 firsl pass through Ihe regiSicr lik before Ihal d:lIa can be Iransformed by Ihe ALU is known as a load-store architecture .
425
Basic Control Unit Suppose we walll 10 use Ihe basic datapath of Figure 8.2 LO perfonn the simple processing lask of addmg dala memory local ions 0 and I logelher, and wriling the resull in data memory locallo~ 9-m olher word, we WamlOcompule 0[9} = O[OJ + O[ I J. We can achieve this processmg lask by "inslrucling" the dalapath lO perfonn the following operations:
load datapalh memory localion 0 LO regisler file regisler RO (i.e., RF[OJ = O{O/), load daLapmh memory lOCation I lO regisler file regisler R I (i.e. , RF{ I) = O{ I /), perform an ALU operation lhat adds RO and RI and wriles the resuil back into R2 (i.e., RF{2/ = RF[O/ + RF{ I J), and
Slore R2 into data memory localion 9 (i.e., 0[9) = RF[2J).
(a)
(b)
(e)
Figure 8.3 B"ie dalapalh operalions: (a) load (read). (b) ALU opcr:lIion (transform). and (c) "ore (wri le).
EXAMPLE 8.1 Understanding data path operations Which of Ihe following are valid single-clock -cycle dalapalh operalions for the datapalh of Figure 8.l? I. Copy daw from a data memory location inlo a reg iMer file localion. 2. Read dala from two d:U3 memory loca ti ons into IWO rcgi,(cr file localions.
3. Add data rrom IWO data memory locat ion... and l)IOre the result in a register fi le location. ~.
Copy dma from one regi
5. Subtrac t data in a rcgi'lcr file localion rrom a d::!la memory loc:lIion. storing the result in a register fi le location.
( I) " a valid operalion. "nown a, a load opermion. (2) is 1101 1I valid operali n. We cannol read more Ihan one daw memo!) local ion during a dmapmh operalion (for Ihi s dUlaplllh). and we cannOI wrile 10 more th:.m one regi\ lcr fi le loca ti on during:1O operati on. (3) b ,w/ :1 va lid operati on. Not only can we nm rCild from two data memory l oca l ion~ during onc opt:ru tion. but wc cannot reed the read
,alue, dlreclly inlo Ihe AL 10 perform Ihe add- we mu" fi rsl perronn opemlion Ih.1 read Ihe duta lIem; II1tO reg"ler hie lac.lion;. (4) is. v" lid oper,"ion. We can configure Ihe ALU operalion 10 'Imply pa" one of ," "'PUb Ihrough to .he QUIPUI (perhap' by adding 0) and slore Ihe re,uil in Ihe reg"l« hie. (5) "/lor a valid operal.on. We cannOI feed a read duw memory lacOlion directly 10 Ihe AL -Ihere " no such co"neelion .n Ihe d.II.'pmh Vulue; read fr m dala memory mu I be loaded InlO Ihe rC~"ler hie hr.1
NOle lhal we could have used any regislers in the regisler file, rather than RO, RI. and R2. If 0 [0/ contained Ihe value 99 (in binary, of course), and O[ I J contained the value 102, lhen afler carryi ng oUllhe above operalions, 0[9J would cOnlain 201. You mighl lhink lhal having 10 instrucl the datapath lO perfonn four distinct operalions is a rather cumbersome way of adding IwO dala items. If you could build your own CUSlom digilal circuillO implemenl 0[9/ = 0[01 + O[ I }. you would likely just feed OlOI and 0[1 J lhrough an adder whose ompul you would conneCl LO 0[9J, thus avoiding Ibe four operalions involving the regisler file and ALU. We see the basic tradeoff of singlepurpose versus programmable processors-programmable processors have the drawback of compulalion overhead because Ihey have to be general, but they provide the benefits of a mass- prod uced processor lhal can be programmed lO do almo l anything. Somehow we need 10 descri be the sequence of operations-RF[OJ = OlOJ, Iben RF{ I }=O{ I}, lhen RF{2/ = RF{O/ + RF{ I}, then 0 [9J = RF{2/-that we desire LO execute on the dalapalh. Such a description of desired processor operations are known as instructiOIl S, and a colleclion of instruclions is known as a program . We will tore Ibe desired program as words in anOlher memory. cailed the ins/rue /ioll memory. We'll describe how 10 Instruction memory I represenl lhose instructions Ialer. 0: RFIO]= DIO] For now. assume lhat the four 1: RFlll= Dll] 2: RFI21= RFI01+R F(1] instruclions are somehow slored 3: DI9]= R Fj2l in locations O. I. 2. and 3 of Ihe inSlmction memory I. as shown in Figure S.4. ow is where the comrol unil plays a role. The cOllfrol lilli/ reads "'Ich insll1Jclion from insll1Jclion memory. and lhen execules lhm inslmclion on the dalapalh. To execule our simple program. the conlrol unil would begin by perfonning Ihe folControl unit lowing lasks. known us stages. to Figure 8.4 Tho control unil in 3 programmable p arry OUI Ihe firsl insinl lion:
·'16
Programmable Processors 8.2 Ba sic Architecture l. Fetch : The con trol unit wo uld stan by reading l i D} into a loca l register, a task know n a, fe tching . Thi s stage requ ires one clock cyc le.
1. Decode : The control unit wou ld then determine what opcration this instruction is requc,ting. a task known as decoding . Thi s stage also req uires one clock cycle.
3. Exewte: Seeing th at thi s inslructi on re luests the datapath operation RFIO} = 010}. the cOlll rol unit wo uld set the cOlllrol lines of the dalapath to read DIO}, pas; the read data th rough the 2x I mux in fron t of the reg ister fi le. and write that da ta int o RIO}. The task of carrying out the operation is know n as exeClilillg. Most operations arc datapath opermion s (such as a load operat ion. ALU operation, or slOre operation). but not all operati ons require thc datapalh (an example is the ju mp instructi on to be discussed later). Thi s stage requires one clock cycle. Thus. the basic stages the control unit carries out for th m first instruction are: fe tch, decode. and exeellle. requiring three clock cycles to compl ete just thm first instruction. The local register in which the control unit IOres the fetched instruction is known as the illstructioll register. or fR . a shown in Figure 8"+. NOIice thm the cOl1lrol unit needs 10 keep track of the locati on in instruction memory from which to fetch the next instruction. Since the in struction locations are usually in sequence. we can use a simple upcounter 10 keep track of the currelll program instruction-such a counter is known as a program COli liter. or PC for sha n . The processor stans with PC=O, so the instruction in flOJ represents the fir t instructi on of the program. Figure 8.5 illustrates the three stages of executing the instruction RFfOJ = DIO} stored in flO}. Assuming PC was previously initi ali zed 10 O. Figure 8.5(a) shows the first
------------------------------------------------1 :________ I
~ _-_-
__ -------1--------------------------:
InstructIon memory I 0: R F[O]=D[O] 1: RF[1 ]=D[t] 2. RF[2]=RF[0]+RFP] 3: D[9]=RF[2]
: ,_________ - - --- --- - -- __ L --- --- ----- - -- -- --- ------,
i Instruction memOlY I i 0: RF [O]=D[O]
427
flOj' s co ntents, the 'Instruct ion RFIO}=OIO}. into fR . Figure 8.S(b) shows stage fetching h d tl ~dsecon state decoding the instruction and thus determining that the instruction is a 0" II1structlon F,oure 8 5{c) h . h ." . sows the controller executing the in lruclion by confiourlng t ~ ~atapath to read the value of 010} and storino that value into RF/O]. If D/OJ contall1e 9. then RIO} wi ll contain 99 after completion"of the execute stage. After proces II1g the instruct ion in IIO}, the control unit would fetch the in lruction that IS 111 III J. decode that instruction, and exeCUle that in truclion {lhus executing RF/ I} ~ Of I J), requiring another three cycles. Next, the control unit would fetch the II1strucllon that i in 1{21, decode that instruction, and execute that instruclion {thus executing RFI2} = RFIO} + RFlf Jl, requ iring anOlher three cycles. Finall y. the control unit wo uld fetch the instruction that is in 113}, decode tltat in lruction . and execute that IIlstructl on (thus executing 019} = RF/2J), requi ring anolher three cycles. The four IIl structl ons wou ld require 4*3 = 12 cycles 10 run 10 completion on the programmable processor. Tlte control unit wi ll require a controller. like those de cribed in Chapter 3. that in this case repeated ly performs the fetch. decode. IR=I[PC] and execute steps (after having initialized PC ~_~_/ PC=PC+t 10 O)-nOle that a controller appears inside the control unit in Figure 8.4. An FSM for that controll er appears in Figure 8.6. Tlte controller increments the program counter after fetchin g each instruction in state Fetch. so tltat the next fetch state wi ll fetc h the next instructi on (nOlice tltat PC gets incremented at the Controller end of tlte fetch stage in Figure 8.5(a)). We ll Figure 8.6 Basic controller states. describe the actions of the Decode and Execllte states later. Thu , the basic pans of the control unit include the program counter Pc. the in auction register fR , and a controller. as illustrated in Figure .-I. In previous hapters. our nonprogrammable processors consisted onl y of a controller and a datapath. Notice that the programmable proce sor instead contains a control unit. which itself consi IS of some regi sters and a controller. To summarize. the comrol unit processe each instruction in three tages:
: 1: RF[l]=D[I] : 2: RF[2]=RF[0]+RF[1 ] j 3: D[9]=RF[2]
l. first fetchillg tlte instruction by load ing the current inslTUction into fR and in cementing the PC for the next fetclt.
Conlrolier
2. next decodillg the inslnlction to determine its operation. and 3. fina ll y execlltillg the operation by setting the appropriate ontrol lines ~ r the datapath . if applicable. If tlte operation is a datapath operation. the oper~tion ma~ b
Lc~o~n~t~fo~l~u~n~ll______-l _____ ~
(a)
(b)
.
__
:L __=_C::_~_~_.!_~~_:-:-_,.. . --=_ ,,_-=' _
__ (c )
f,gure 85 Three tage, "f p"J<:c",ng nil' on,'ruWnn (a) fetch . (h) decode. (e) e,cnll"
···
__-_-_J.J··
~~~~-_-_-_-_-_-
one of three possi ble type : (al/oorlillg a data memo I) locmion into a register fi le location. (bl tmn,rorming
-
~
--
-...--
-
-'28
8 Programmable Processors
EXAMPLE 8.2
8.3 A Three-Instruction Programmable Processor
Creating a simple sequence of instructions
O. R131; 0101
the bits r)r2rlrO' For example, the instrucLion "0000 0000 00000000" speci fies a move of data memory location 0, or DIOI. into register file locaLion O. or RFfO/~in other words. that inslruction represenlS the operation RFfOI ; DfOf. LikeWise, "0000 0001 00101010" specifies RFfll=Df42f. We've inserted spaces between some bits for ease of read ing by you the reader-those spaces have no other significance and would not exi sl in the insLruction memory.
I. RI.JI; 0111
Store instruction-OOOI r)r2rlrO d,d6dSd,d)d2dldo: Thi s instrucLion specifies a
Crt'a{(' a 'l't of In,tmction, ror the.: proccs~or in Figure MA to compu te 0/3/ = 0/0/ + Df 1/ + Each in!-tnlclion mu,t f\!prC'Cnl a valid ~i nglc·clod.-cyc l c d;lI:lp~lIh ope rati o n.
\Vc might ... lan \\ ith location,:
thr~e opl..'J"alions
D12/.
th at read th e data memory locati ons in to register file
2. Rlcl; 0121
NOlI..' lhat \\(' intcllIionall y rcgl'ler:-..
In
c ho~c
arbitrary regi ster IOC;lIiolls. to make clear thaI we can use any
Ne\t. we need to ;Idd the three va lu es a nd s tore the res ult ill a reg is ter fi le locati on. say R/ Jj. other \lord,. \Ie wanllOperronn ille rollowing opermion: Rill; RI21 + RI31 + R141. However,
the datapath of Figure.: SA cannot ;Idd three register file locations in a single operati on. but rather can an i) add the
1\\0
location .... Instead. we can describe the desired add it io n comput ati o n by dividing
computation into 1\\ 0 dmapat h ope rations:
J . Rill; RI21 + RIJI ~.
Rill = Rill + RI.JI
Finall). \Ie ,\[il< Ih< re,uil inlO 0131: 5. Df3I ; Rill Thus. our program c:onsisls of the six instruc tion s appearing above. whic h we might store in instruc· tion memo£) location ... 0 through 5. <411
EXAMPLE 8.3
429
Evaluating the time to carry out a program Deh!mline the number of clock cyclc~ required for the processor of Figure 8.4
10
execute the si.x·
instruction program of Example 8.2. The procc"i\or require'\ 3 cycle\ (0 process cach inst ructi o n: I cycle to fetch the instruction. I (0 decode! the fetched in~truction. and I to execu te the in~ t ruction . A t 3 cycles per instruction. the (olal cycle\ for 6 in\LnJClion~ i\: 6 in\lr * 3 cyc leslinstr 18 cyc l c~.
=
8.3 A THREE-INSTRUCTION PROGRAMMABLE PROCESSOR A First Instruction Set with Three Instructions Thc v. ay v.e repre,ent in,tructions in the in!>lruction memory. and the list of allowable in,truction,. arc known as a programmable p roces~or's illstrtlctioll set . Let's assume that a processor uses 16-bi t instructions. and that the instruction mcmory I i 16-bits wide. In,truclion set, typically r~se rve a certain number of bit s in the instruction to denote whal operation to perfonn. The remaining biL, pecify any additi onal infonl1ation needed to perform the operalion. ,uch a, the source or destination reg isters. We define a simple, three· In,truction ,el. with the most significant (meani ng leftmost) 4 bi t identifying the appropriate operation and the lea,t ,ignificant 12 bi t> containing register fi le and data memory add re"c,. fo\low,:
'l'
i1Jod In'truclion 000 rJ r 2r l r O d, d6dSd,dJd2dldo: Thi, in;truction specific a move of daw from the dilt ~1 memory local ion whose addre<,<, is speci fied by the nih d~"d,d"d,dldld" into the regl,tcr hie rcgi,tcr who,e loca tion is specified by
move of data In the opposite direction as the instructi on above. meaning a move from the register file to the data memory. So "0001 000000001001 " specifies DI91;RFIOf.
Add instruction-OOIO ra)ra2ralraO rb)rb1rblrb o rc)r~rclrco: Thi in truction
speC ifies an addition of two register file registers specified by rb3 rb1rb lrbo and rc)rc2 rclrc O' with lhe result stored in tile register file register specified by ra)ra1ralraa· For example, "00 10 0010 0000 0001" specifies the in truction RFf21;RFIOI+RF{ II. Ole that add is an ALU operation .
None of these instructions modifies the contents of the instructions' ource operands. In other words. the load instruction copies the COnlents of the data memory location to the specified register, but leaves the data memory location itself unchanged. Likewise. the Slore instruction copies the pecified register to data memory. but leaves the register' contents unchanged. The add instruction reads its band c registers without changing them. Using this instruction Desired program set. we wou ld describe our 0: RF[O]=D[OI earlier program that com1: RF[l]=D[l] 2: RF[2]=RF[0]+RF[1] putes Df91;DfOI+Df I f as 3: D[9]=RF[2] shown in Figure 8.7. Computes Not ice that the first 0191= 0101+0111 Instruction memory I four bits of each instrucLion 0: 0000 0000 00000000 are a binary code tilat indi1: 0000 0001 00000001 cates the instruction's 2: 0010 0010 0000 0001 3: 0001 0010 OOOOtOOl operation. Those bit are known as the instruction's operation code. or opcode for shan. "0000" means a move from data memory to register file. "0001" means a move from register fi Ie to dat a mcmory, and "0010" means an add of two reg isters. bascd on the instruction set defined in the bullcted list above. The remaining bits of the Figure 8.7 pn.lgram illal ,-ompUl<' D['I);D[O]+D[II. in tnlction represent operu:;ing a 2h"en instrul'li n set. \\'~'\e IOsened ~P'k-~ allds. which indie,lle what be t\,"'t'eo"'lhC: instRu:tion memof) 's bits for re3dJbllH~ onl~-Iho:.e Sr:ll~!'> donOt e\i~t 11\ tht' n~mof) . dma to operate on.
•
~
----
·no
Programmable Processors
8.3 A Three·lnstruction Programmable Processor
We cou ld \\ ritc a different program u~ing the ~aJ11C lhrec- in:'lfucti on instruc-
lion set. For example. we could write a program that compute, DI51 = D[51 + D16} + DI7f. We mu,t perfonll tha t computation lIsing instru cti ons chosen fr0 111 the three-instruction instruction se t. \<\Ie might \\ rit e the program as sho\\ n in Figure 8.8. The number before the colon represents the instruct ion's addrr" in the instruction memory I .
The text following the two fo rward
/I RF[OJ ~ 0[5J /I RF[1J ~ 0[6J /I RF[2J ~ 0[7J /1 RF[OJ ~ RF[OJ + RF[1J /I which is 0[5J+0[6J 4: 0010000000000010 /1 RF[OJ ~ RF[OJ + RF[2J /I now 0[5J+0[6J+0[7J 5: 0001 0000 00000 101 /I 0[5J ~ RF[OJ
0: 0000000000000 101 1: 0000 000100000110 2: 0000 0010 00000 111 3: 0010 0000 0000 0001
The
co mputer
executes
instructions
beginning at address O. which usuall y has an instruction that jumps to a built-in small program that loads the operating system (the small program is often called the bas ic input/output system, or BIOS). Most computing dictionaries Slate that the term "boot"
D/5/=D/5/+D/6/+D/ 7/ lising the three-
ori ginates from the popular expression "to pull oneself up by one's bootstraps." whic h means to pick yourse lf up wi thout any help. though obviously you can' t do thi s by grabbing onto your own boot traps and pulling-hence the cleverness of the expression. Since the computer loads its own operating system. the
instruction instructi on sel.
:\Iachine Cod e versus Asse mbl y Code As you have seen. the instructions of a program ex is t in instruction memory as as and Is. A program represented as a s and Is is known as machille code . Writing and readi ng programs represented as Os and I s are tasks that humans are not panic ularly good at . We humans can't understand those Os and Is easil y. and thus will li ke ly make plent y of mistakes when writing such programs. Thus. earl y computer prog rammers developed a tool , known as an assem· bier (wh ich itse lf is just another program ). to help hu ma ns write othe r programs. An as embler allows u to write inst ructions using IIl1l emoll ics. or symbols. that the assembler automaticall y translates to machine code. Thus. an as e mbler m ay tell us that we can wri te instrUction, from o ur three-instruction instructi on et using the fo llowing mnemonics:
Load in stru ction-I\(OY Ra. d : pec ifie the operati on RFlaj= Dldf. a must be 0. I ..... or 15-so RO means RF/Oj. R I means RFII f. etc. d must be O. I ... .. 255.
Store in,tntction-MOY d. Ra : specifi cs the o pe rati on Dld}=RF/af. Add instruction-ADD Ra, Rb, Rc: s pecifics the operati on RF[a}=RFlbl +RFl cf. ~ COMPUTERS WITH BUNKING LIGHTS. Big computer., shown in the mo\ies often have many
computer.
Figure B.8 f\ program to co mpul e
slnshes (1/) represe nt commen ts. and are not part of the instru ctions. Ole how that program ultimate ly computes the de ired sum . Thi s migh t be the first time that lOU have had to think o f computations in terms o f low- level programmable proces,or instructions. Think.ing in te rms of suc h registe r- leve l o pe rati ons can be difficult at firs!. but become easier as you see and develop mo rc programs at that level.
ro'" of ,mall bltnking light,. In the carly day, of compuung. computer programmer; progrummed u"ng machine code. and they cntered that code tnto the tn,trucUon memory by nipptng "''' tehe, up and down to repre",nt 0, and h To enahle dcbuggtng of the program. a., "'ell "' to ,how the computed data. tho", earl y compute" u\Cd row, 01 Itghh-on Itght' meant
Turning on a personal com pUler causes the opera ting system to load, a process known as "booting" the
1,. off light' meant 0,. Today. nobody in their ri gh t mind wou ld try writing or debugg ing a program by u,ing machine code. So computer, today look like big boxes-with no row, of light,. But big plain boxes don't make for IOlcre~lIng bac"gro und~ in movies, so movie make" continue to U\C rnO\, II.: prop, wi th lots or bhnl.ing Itgh t' tu rcpre,ent computc,,- lights that IlrC u clc"", bUI cnh;r1i.H11 IIlg.
431
computing a long time claims a different origin. One way of loading a program inro the instruction memory of earl y computers was to create a ribbon with rows of
holes. Each row might have enough room for say 16 holes, thus each row would represent a 16-bit machine instruction-a hole meant a O. no hole a 1 (or vice
versa). A programmer would punch holes in the ribbon to store the program on the ribbon (using a special hole-punching machine). and then feed the ribbon in to a compUlcr's ribbon reader. which would read the rows
help. The term bootstrap eventuall y got shortened to
of Os and 1s and load those Os and 1 s ima the computer" instruclion memory. Those ribbons might have been several feet long. and looked a lot like the straps of a boot. hence the term bootstrap. hortened to boot. Whichever is the actual origin. we can be fairly sure the term "boot" comes from the bootstraps on the
boot. A colleague of mine who has been around
boots we wear on our feet.
computer is in a sense pi ck ing itself up without any
Using those mnemonics. we could rew rite the program D{9}=D[O}+ DII} as follows : 0: MOY RO, 0 I: MOY RI. I 2: ADD R2, RO. R I 3: MOY 9. R2 That program is much easier to understand than the Os and Is in Figure .7. A program wri uen using mnemonics that will be translated to mac hine code by an as ernbier is known as assembly code. Hardly anybody writes mac hine code direclly these day. An asse mbler wou ld automaticall y translate the above assem bly program to the mac rune code shown in Figure 8.7. You might be wondering how the assemble r can distinguish between the load and store in tructio n above, when the mnemonic fo r both instrU tions i the ame-"~(O ." The assemb ler di stinguishes those two types of instruction by looking at the first character after the mnemonic "MOY"-if the first character i an "R." then that operand i a register, and thus thut instructi on must be a load instrUction.
Control Unit and Datapath for the Three-Instruction Processor Fro m the definition of the three-instruction instrUction set and an und rs!anding of the basic Oturol unit and datapath archi tecture f a programmable proces' or as -ho\\ n in Figure .-1 . we can desi gn a complete digital circuit for a three-instru lion progrnmmable processor. The de 'ign process is actuall y vet') similar to the RTL de 'ign proces i hap tcr - .
432
Programmable Processors
83 AThree·lnslrucllon Progrommoblo Procossor
We begin wilh a high· level Slale machine descriplion of the syslcm . show n in Figure 8.9. Assume Ihal 01' i, , hon · hand ro r IRI I S.. / 2/. meaning Ihc leflmosl four bil;' of Ihe instruction rcgi~tcr. Likewise.
a,s ume Ih al ra i, . hOrlhand IRIII ..8 1. rl> i, shonhnnd I RI 7.. .JI. rc is , horlhand IRI 3..01. and d i, , hOrl hand
for for for fo r
IR/ 7.. 0/.
Recall Ihal Ihe nexi SICP in Ihe RTL design process was 10 High- level Slalt! maclllne dc ... riplion of::t crellle Ihc dalapalh . We already thrcc!-in tnlction progmll1mablc procc,,",or. erealcd Ihe daaapaah in Figure .4. which we refine lO , how every cOnlrol ; ignal from the comrollcr. a. hown in Figure 8. 10. The relined dalapath ha, comrol signals for cach read and wri lc pon of Ihe regi ler file (sec Chapler 4 for informaaion on regisler file;). Thc regisler fil e has 16 regislers because Ihe inslrllelions have on ly 4 bils wi lh which 10 add ress rcgisle",. The dmapmh has a conlrol signal 10 Ihe ALU called a 1 u_s O-we' lI ass ume Ihc ,i mplc AL adds ils inpul when a 1 u_s O- I. and jusl passes inpul A whcn a 1 u 50 =0 . The cialapalh has a ,c1eellinc for lhe
433
2x I mux in front of Ihe re' ,. . . gl Icr hie , 'HHe dm.1 pon . hllall). \I . IIl1\e uh u includ '.1 Ihe conlrol " I ' . Igna , lor Ille dOlJ m'~l1lol"). \\ III h \\C J"UIIlC ha, .1 'llIg.!.: addr'" pon . tlml 'nn I IIU suppon .onl) a read or a \I rile. hIII IIlJ1 rolll '1IlIllil.llleou,1 . Tile FS I. \ e Inc- 1 can do Ihi, 'imighlforwurdl) b replacing the high· Ie, cI aClion of the :...HlIC machine
in Figure 8.9 by BIKlle:m opermion, on Ihe Con • lroller', inpu l and oUIPUI lines. 3; ,hown in Figure 8. 11 . (Remember Ihal Of'. d, ra. rb. and rt: arc , honhancl -AF{11tr-otdl D{dl RFtr'lAFt"'~Ftrb,"", o addr~d o oddr d - AFjreJnOlalion, for IRIIS.. 121. o rd. 1 o wr I RF Rp oddrerb IRI 7.. 01. IRI 11 .. 81. IRI 7.. -l I. AF s. 1 AF 6 X RF Rp rd ~ 1 and IRIJ..OI . re'peclively.) AF Ap oddr ,ro RF Waddr. r. RF 9- 0 AF W wra l RF Rp rd I RF Rq addrerc We could Ihen fini,h Ihe RF Rq rd~ 1 con troller's design by con· RF W addr. ra veni ng the FSM 10 a ,laiC RF W wr. l alu sOlZ l regiMer and combi nalionnl logic, using Ihe mClhod, Figure 8.11 .. M for fhe IhrcC ~ III\ lrUCIHIIl prucc" ur\ confrollcr. rrom Chaplcr 3. We would have Ihu;, de,igned a programnwblc proce"or. leI's trace lhrough Ihe comroller\ FSM behavior 10 ,ec how a program would execule on Ihe Ihree· in; lrucli n proce~,or. A, II rcminder. remcmber Ihlll we follow Ihe FSM convenlions Ihal all Ira n ~ili on ;, are implici ll y A Ded wi lh a ri , illg clock edge. and ihal any comrol ;ignal nOI explicilly a"igned a va lue in a SlalC i;, implicill y as;,igned a O. The FSM inilially Sian, in Male Illit . which SCi, PC c 1 r - I, cau, ing Ihe PC reg· iSler 10 be cleared 10 O. The FSM on the neXI clock cycle enlcr;, the Fetch SlaIC. in which Ihc FSM reads lhe inslruelion memory al address 0 (because PC i, 0) and loads Ihe read value inlo IR-lhal read value will be Ihe inWuclion Ihal wa... ' IOrcd ill 1/01. Allhe same lime. the FSM incremenls the PC's value.
Figure 8.10 Refi ned dalapalh and control unil for the three·inslruction processor.
The FSM on the nexl clock cycle enlers Ihe Decode SlaIC, which has no aClions bUI which branches on the nexi clock cycle to one of Ihree ; lales. Load. Store , or Add. depending on Ihe value of Ihe highe; 1 four bilS of Ihe IR regisler (lhe currem instruclion' opcode).
.B~
Programmable Processors In the L{I(/d ,tatc. the 10 M sets the data memory address line, to the low eight bit of the IR and ,ets the data memory rcad enable to 1. setS the 2x I mux's select line to pa" thc data memory output to the register fil e. and sets the register fil e write addrc" to IRIII .. BI and the write enable to 1. causin g whatever gets read from the data mcmory to be loaded into the appropriate register in the register fi le. Likewise. the Sto re and Add states set the control lines as needed fo r the store and add operations. Finall y. the FSM rctllrl1S to the Felch state. and begins fe tching the next instructi on. NOtice that becau,e the Sture state does nOt write to the register fi le. then the value of rhe registe r fik' ~ mux se lect lines don't mUHer. so we've ass igned signal RF _ s=X in thai ~ tate. meaning the signal's value does not maLler. Using slIch don't care values (see Section 6.2) ca n help u 10 min imize log ic in the controller. You may wonder why the Decode state is necessary when that state contains no action ~--co liid we not have j ust had Decode' s transiti ons originate in stead from state Ferch" Recall fro m Section 5.3 that register updates listed in a state do not actually occur until the nex t clock edge. meaning that transitions ori ginati ng from a state use the pre\" iou register \alues. Thus. we could not have originated Decode's transitions from the Ferch , tate. because those transitions would have been using the old opcode in the instruction register IR. not the new value read durin g the Ferch state.
8.4 A SIX-INSTRUCTION PROGRAMMABLE PROCESSOR Extending the Instruction Set Clearly. having onl y a three-instructi on instruction set limits the behavior of the programs that we can wri te. All we can do with those instructi ons is add numbers. A real programmable processor wi ll support many more instructions. perhaps 100 or more. so that a "ider variety of programs can be written. Let's extend our programmable processor s instruction set with a few more instructions. in order to give yo u a slightly better idea of how a programmable processor with a full instruction set would look . We'll begin by introducing an instructi on able to load a constant va lue into a register file register. For example. suppose we wanted to compute RFIOI = RFI I I + 5. The 5 is a constant. A cO llsta ll1 i, a va lue that is part of ou r program . not somethi ng to be fo und in data memory. We need an instruction that all ow uS to load a constant into a register, after which we could add that regiMer to RFf II using the ADD instruction . T hu s. we introduce a new instructi on with the fol lowing machine and ",sembly code representations: Load-collslall l in\truction--{)OI J ' j ' Z'1 ' 0 c, c"csc. CjCZC lco: specifies that the
binary number represe nted by the bit ' C,c6clc.CjCZCICO . hou ld be loaded into the register specified by rl rZrlrO' The binary number being loaded is know n as a co,,· \10111 . The mnemonic fo r thi s in,truction i, :
\IOV Ra, #c- 'pccifies Ihe operati on RVlal=l'
8.4 A Six-Instruction Programmable Processor
435
a can be 0, I , ... , Or 15 A . , . c can be - 128 - 127 . ssumlng two s complement representation (see Section 4.8). instruction f ' . ...• O•...• 126. 127. The "W' enables the assembler to distinguish this rom a regular load Instruction. . . We continue by introd ucin ters similar t dd " g an lI1StructlOn for perfonning subtraction of two regis• . 0 a iliOn of two registers. having the fo llowing machine and assembly code representatIons: SlIbtracl. instruction-1l100 f , a),aZ,al,a o rbj,b, rblrbo rCj r~ rclr
su.bthractlon 0 two reoe ister fi le ' registers speci'fi cd -by rb)rb, rb,rbo and rC3rc,rc trco· h WII t e ~:s u lt stored in the reg ister fi le register specifi~d by ra3ra, ralr~. For example, 0100 0010 0000 0001" specifies the instruction RFlil= RFfOIRFI II . The mnemoniC for thi s instruction is: SU B Ra, Rb, Rc-specifies the operation RFfal=RF{bl - RFlcl Let's also introduce an instruct 'Ion l,at I aII ows us to Jump . to other parts of a program: llllllp-if-zero instruction-1l101 raj raZratra O O,06050.0j010100: specifies thai if th~ contents of the register specified by ra3raZra i rao is O. we should load the PC W I ~ Ihe current value of PC pl us o,06050.030Z0tOO' which is an 8-bit number in two s complement fonn representing a positive or negative offset amount. The mnemonic is:
J MPZ Ra, ofTset-specifies the operation PC = PC + offser if RF{al is O. By using two's complement for the jump off et. which allows representation of positive or negati ve numbers. the program can jump backwards in the program, thus implementing a loop. With an 8-bll offset, the instruction can specify a jump forward by 127 addresses, or backward by 128 addresses (-1 28 to + 127). Table 8. 1 summarizes the sixTABLE 8.1 Six-instruction instruction set.. instructi on instruction set. A programmable processor typicall y comes with a Instruction Meaning databook that lists the processor's MOY Ro. d RF[a] = O[d] instructions. and the meaning of each MOY d. Ra O[dl = RF[a] instructi on. using a fonnat similar to the fo rmat of Table . I. Typical program- ADD Ra. Rb. Rc RF[ol = RFIb]+RF[ 1 mable processors have dozens. even MOY Ro. #C RF[al = C hundreds. of instructions. SUB Ro. Rb. Rc RF[al = RFIb]-RF[ 1 l MPZ Ro. ofrset
Extending the Control Unit and Datapath
PC=PC+<>ffset if RF[a]~
The th ree new instructions req uire some extensions to our control unit and datapat h of Figure 8.1 0. with those extensions shown in Figure . 1_. Fin;!. th~ load con ranI instruction req ui res that the register file be able to load data from IR{ .. OJ. in addition to data fro m data memory or the LU output. Thu . we \ iden the register file" ' multiple,.r from 2x I 10 3x I. add another muX control signal. and al 0 create 3 ne\\ signal oming from the ontrol ler labeled RF_III_tflllo. whi h will onnect \\ith lR{ .. OJ-these banges are high lighted by the d", hed circle labeled .. r' in Figure . I~ . e ond. the ' ubtract
.
-'''-~.--~-
-'36
8 Programmable Pr ocessors
8.4 A Six- Instruction Programmable Processor
rd
addr
% 16
data
I
:I I ~R Id
u
~I
16
f
~I
I
D addr S
ID
ALU operation
0
pass A through
1
A+B
t
0
A-B
-
D
addr rd wr
rd
frDwr
~~
s1 sO
o o
256x 16
.•......... p' w·aar~·'I'l'·Ela!~ '.
..',
/~F_W
I
t
dataS
...
I
i1~ 51 '/ ~ •
".
f1 6
~
2 1 0 .: 51 16.br\ ••, sO 3x 1 •••••
~RF_s6·········· · ·· ······T6
Controller
RF W addr
4
RF W wr RF Rp addr
4
RF Rp rd RF Rq addr
4
RF Rq rd
....j;;
W data W_addr -
Control unit
alu sO
:
Rp_addr Rp_rd Rq_addr Rq_rd
16x 16 RF
l.~ Rp dala
~6
••••• •• ~... Datapath
RF _Rp_addr=rb RF_Rp_rd=1 RF_sI=O RF_sO=O RF_Rq_add=rc RF_RQ..rd=1 RF_W_addua RF W wr=1
RF_s1= 1 RF _sO=O RF W addr=ra RF=W=wr= 1
alu=sl~O
Rq data
~.
__ ....~I~.~.i ':::'~~"'''''r-_-!l A_1_6_1-!:B_16_..., :
D_addr=d D_wr=1 RF_sI=X RF_sO=X RF _Rp_addr=ra RF_Rp_rd=1
alu_sO=1
W _wr
RF _Rp zero • ~
>
437
ALU 16
Figure 8.12 Control unit and datapath for the six·instruction processor.
instruction require that we use an ALU capable of subtrac ti on. so we add another ALU control signal-highlighted by the dashed circ le labeled '"]" in the figure. Third, the jump-if-zero in truction req uires that we be able to detect if a register is zero, and that we be able to add IR(7 .. 0( to the Pc. Thus, we insen a datapalh component to detect if the register file's Rp read pon is all zeros (that compo nent wo uld just be a NOR gate), labeled as dashed-ci rcle "3a" in the figure. We also upgrade the PC reg ister SO it can be loaded wi th PC plus IR(7.. 0j. labeled as "3b" in lhe fi gure. The adde r used for thi s also subtracts I from the sum . to compen;ate for the fnct that the Felch state already added I to the Pc. We also need 10 extend the FS M for the conlro lle r within lhe control unit to handle the three additional in'>tructions. Figu re 8. 13 shows the exte nded FS M. The Illil and Felch stales ,tay the same. We added three new transitions from the Decode state for the three new ,",truction opcode... We made a minor revision to the UllId, 1Ore. and Add tates' action (the new action, are italicized) s ince the regi ~te r file mux has a mux with two select lines ,",tead of ju,t one. Likewise. we revised the Add ,tatc action .. to confi gure the ALU with two conlrol hne, '"'tead of one. We added four new ,tate.,. /"I}(/(/-('oll'
RF_Rp_addr=rb RF_Rp_rd=1 RF _s1=0 RF_sO=O RF _Rq_addr=rc RF _RQ..rd=1 RF W addr=ra RF=W=wr=1 alu 51=1 alu=sO=O
RF _Rp_addr=ra RF _Rp_rd=l
e '"d a: ...1
a:
Figure 8.13 COnlrol unit and dat.path fo r the six-instruction processor.
JUlllp-iJ-zero, and JUlllp -iJ-zero-jll1p, for the three new instructions. The new in truction
states perfoml the following funclions on the data path: In Ihe Load-cOI/Slalll state, we configure the register file mux to pas the RF _W_da ta signal. and we configure the register file to write 10 the addres pecified by I'a (which is IR( 11 .. 8]). In Ihe Sublracr Slate. we perfonn the same action a in the Add tate. except that we configure lhe ALU for subtraction instead of addition . In Ihe Jlllllp - iJ-~ero state, we configure lhe register file 10 read the register peeified by ra onto read pon Rp. If the value of the read register Rp i all 0 . RF _Rp_zero will become 1 (and otherwise). Thus . we in lude two transitions from the JlIIl/p-iJ
a
Notice Ihal with Ihe addi tion of a JUlllp- iJ-~ero instru tion. the proce or may take up to four cycles 10 complete an instruction. nmely. when the ra regisler of a JIlTllp-(t:~em instnlction is all as, Ihen an extra slate is needed to I ad the PC with the address f the instrucli n 10 \Vhi h 10 jump.
-'311
8 Programmable Processors
8.6 Further Extensions 10 the Programmable Processor •
lhose labels, such as "ski I" .. .. .. ,... .., live labels lhal hel p and done. or Fred and George. It s best, lhough. 10 u e descripA P people readll1g lhe a sembly code 10 undersland the program. n assembler wou ld . Figure 8.14(b). For aUlomallcally convert lhe assembly code 10 the machine code shown in type by I k' each as~embly IIlstrucuon. the as~embler detenmnes the speCific instruction prime 0 ~ 1n ~. at the mn~monic as well all the operands if necessary. and thcn outpu ts the approassen blpe e Ils (four blls) for lhat inslruclion lype. as defined in Table 8.2. For example the 1 er would look al lh fi ' . . e rSl II1s1rucllon "MOV RD. #0" and lhu know from the fi rst lhree leuers "MOV" lhat " oper d . thiS IS one of the data movement in st.ructions~ the assembler wo uld look at the "RO" wouId know thiS . .IS either . fina l!an s, h and . seeing . a regular load or a load-constant ins truction; putt" y. t ~ assem bler would see the "#" and conclude this is a load-constant instru cti on, thus out. St mg. t e Opcode " 00 11" for a load-cans ram instruction. as shown in the first machi ne In ruCllon of the figu re.
8.5 EXAMPLE ASSEMBLY AND MACHINE PROGRAMS Usi ng the ,i x-in, lrucli on inslruc lion sel o f lhe previo u, $eclion. we no\\ prov ide an ex ample of a~st! lllbl y- lan guuge programm ing lI ~ ing the six-inslructio n proce ~so r to perform a pa rti cul ar tas k. and we show how the " " cmbly code wo uld be conve rted 10 machine code by an a"e mble r. n a»c mbler wo uld make use of lhe tab le shown in Tab k 8,1. which maps inslruc li ons 10 opcodes.
EXAMPLE 8.4 Asse mbly and machine programs for a simple program \Vritc a program that COll n t.;; the number of words that arc n OI equal to 0 in daw, mt!l11ol) l oc~\l iom, ...j. and 5. and that stores the result in da ta memor) location 9. Thu ~. the possible res ult s that
TABlEB.2 Instruction opcodes. Instruction
Opeode
MOV Ra. d
0000
10V d. Ra
000 1
A DD Ra. Rb. Rc
00 10
MOV Ra. #C
0011
SU B Ra. Rb. Rc
0 100
JMPZ Ro. offsel
0101
439
"00;;° :ssen~ble~, co~~ertS lhe operands 10 bilS also, converting "RO" of the firsl instruction 10 . and #0 10 00000000 ," as shown in lhe firsl machine inslruction of the figure ' requ .ires some extra handling. The assembler rccogni zes this as a Jump. if The ' JMPZ ins lruellon
\\Qu ld be ~(ored in location 9 arc Lero. one. or two. U\lI1g the in-,tfuction ... et of Table 8.2. we can write an a~:-.c mbl y program as shown in Figure .I..l(a). The progrJm maintain.., the count in register RO. which the progra m initializes to O. The
~.~~~ Ins~ruclion ~nd lhus OUlPUlS the opeode
program mil} need to add I to lh b register latcr. so the program loads the value I into register RI. The program nex t load, data mem ry locmion 4 inlO regi:-tcr R2. The program then jumps 10 the in,tTUClion labeled ~~ "lab I" if the \'alue of R2 is zero. If R2 i:-. not l Cro. the program will ex.ec ute an add imlruetiOn that add ... one to register RD. and will th en proceed to the instruction labe led "Iabl" ... inee that in"'lruclio n i~ the nex t instructi on. The instruction labeled "Iab l" loads data
labl. ' as lhe assembler hasn' l reached lhal instruclion yel in lhe program. To solve lhi problem many assemblers ac tuall y make I WO passes over the assembly code: durin g th e fi~t pass. the assem~ b~er creales a lable of all labels and lheir addresses. and lhen on lhe second pass the as embler ? (PUlS. machine code. Such an assembler would th erefore kn ow durin g the second pas thal th II1S1rucllon label:.d "la.~ I.' · is al ~n add ress lWO addresses beyond lhe first JMPZ in truclion-specif~ I c~ lIy. ~hat the lab l instructi on IS at address 5. whlie the JMPZ III truclion is at address 3 (assuming lhal lhe firsl inslruclion is al address O. nOl I). Thus. lhe assembler would amp t off,sel of 2 10 jump forward 2 addresses. I alice lhal lhe labels "Iab l" and "lab?" do nOl ap u an lhe mac h'me cod e-thcy are merely a convenience construct thai the assembler - provides pear 111 fo r the asscmb l y~langu uge programmer. ~
MOV AO, #0; /I initialize resuil lo 0 MOV Rl , #1 ; II constant 1 for incrementing result MOV R2, 4; /I get data memory location 4 JMPZ A2, labl ; II if zero. skip next inslruction ADD AO. AO, Al ; /I not zero, so increment result tabl :MOV A2, 5; /I get data memory location 5 JMPZ A2, lab2; /I if zero, skIp next inslruction ADD RO, AO, A1; /lnol zero, so incremenl ,esull lab2:MOV 9, AO; /I store result in dala memory location 9 (a)
0011 0000 00000000 0011 0001 00000001 0000 0010 00000100 0101 001000000010 0010 0000 0000 0001 0000 001000000101 0101 001000000010 0010 0000 0000 0001 0001 0000 00001001 (b )
Figure 8.14 A program 10 counl lhe nu mber of nonlero numbe" in Df.Jj and Dj5 j. sloring lhe r",uil 10 Dj9j: (a, ""embly code. and (b) corre_ponding mac hine code generaled by an assembler. The "pace~ In Ihc machine code\ 16-bi t i n ~ lruc ti on '" nre lherc for your cOlwcniencc as you read this hook; actual machine code h a~ no , lIch \ p3Ce\, memory locallon 5 1010 reg"lcr 112. The program jump' 10 lhc in' lruclion labe led "lab2" if Rl is 1\ not fCro. thc program execute' an add in"truclio ll that add, one L O rcgi ter RO. and lhen proceed' to lhe neXl '"'lrucllOn. "hich i, the in' lruelion labeled "lab2." ThaI ilm ruclion SIOres the conlcnl\ 01 rcgl\ICr RO to data memory l oc~'lIon 9. In ,""rltlng the .' ......emhl)' program. we arbllr~m l y cho ... e tIll! regl\ tcf' th aLwe used to ~tore the rc'\ull. the e,:un ... t,lOt I. ~nd the u'ila memory locatinn COI)Y. We coul d h;,ve u... cd any registers for thoCi.C purpn\C,. r'or example. we could huvc u\cd r~g l ... tcr 1<7 10 ho ld the rc\uit . meani ng all occur· renl:C" of RO In the codc would In\lcnd h.lve neen }(7 h n1 hcnTIorc. In writing the assembly p"'gr .. m "c ,lfhll,"n ly eh .. ," lhe label' "Iabl" "nd "1,lh2," We cou ld have pIcked olher nu,"c\ for
fero. II R2
"0101 . " The assembler converts lhe firsl operand.
. 10 00 10 . The as emblcr then reaches lhe second operand. "lab I." and does not know ~7 hat ~llS to output. since the assemb ler does n't yet know the address of the instruction labeled
~
8.6 FURTHER EXTENSIONS TO THE PROGRAMMABLE PROCESSOR
Instruction Set Extensions EXlending the instruclion sel wilh further instructions would require similar ty pes f eX le nSlons and mod ifications 10 the control unil. datapath. and FSM . A prog:ramm b~ processor mighl contain dozens more dolo movemelll instructions. which between data memory and lhe reg isler file. or belween regislers. Fo r example. a processor 1llIghi have in lruclions for copying lhe contenlS of one regisler 10 another (e .g .. !\IOV RO. R I. which would copy RJ' contents into RO). a nd would ca rry out that instru tio n uSlIlg a tale thal reads lhe source reg ISler. pas es .the read \'alue through the AL unchanged. and wriles the ALU oulPUl 10 the desllnatlon reglsler. A s ano ther exam Ie mighl ha ve inslruclions lhm would use lhe COnlenlS of a regi ' ler as the from wh Ich to read data memory. known as IIld,reC( addre' slIlg. programmab le processor would also conlain dozens I' arilhmeticflogic in lions. whi h perf nn arilhmelic and logi operalions on registe rs in the register example. a processor mighl include nol ju ' t add, and sublracl instru ti ns . \.luI a lso i~ : menl, complemenl. decremenl. AND. OR. XOR. shIft left. shift right. and o the r insllllctions that could be carried OUI by an AL .
~Q\e ~at:
I:rocesso~
a:~
file~
_
_ _ _ _ _ .....
-.J_
,
Programmable Processors
8.7 Chapter Summary
A programmable processor would furtherlllOre ~olllllin sevcra IJlow-of-colltrol illstructiolls . \\ hich detenninc the next value o f the Pc. I-or example. a processor IHlght lOciude not ju,t a jump-if-lcro insLnlction: but also a jump- if- not -z~ ro . lin un.condlllonal jump, an indirect j ump. and perhaps e\en jump-Ji -negall vc and sImIl ar such InstruCllons. Furthermore. a proce»or may include instruc tions that can jump farther than j ust a small offset fTom the c urrent Pc. and perhaps even to an absolute address rather than an offset address.
Input/Output Extensions
==::
256x16 D
Section 1.3 in trod uced a basic mic roprocessor ~:dr htl\ in2 ei~ ht inputs 10. II . .... 17. and eight wr outpu7s PI . .... P7. We ca n extend the basic programmable processor of Fi gure 8.1 2 to implement such exte rnal inputs a nd outputs .. One method for such an exte nsion wou ld ullhze a 240: . o6~~~. I 10 241: ' 00:y:)~11 'pecially designed data me mory. In that data memol). we mi ght re place the last 16 words of 248:: . II-......,.-+~ PO the memory by direc t connections to the input and output pins. as illustrated in Figure 8.15. II-......,.-+~ P7 255:' The data memory stores locati ons 0 through 239 in a normal RAM. Location 240. howeve r. is aCLUally a special wo rd whose high 15 bits are all Os. and whose lowest bit comes from a OIPFigure B.15 Connecting to flop loaded every cycle with the value on ex ternal pins. externa l input pin /0. Thus. reading locati on 240 will ""uil in eithe r 0 0 . .. 0 1 (i llleger I). or 00 ... 00 (i nteger 0). depe nding on the va lue appearing at 10. Likew ise. location 24 1 is connected to pin II . location 242 to 12, and so on. Wi th locallon 247 connected to 17. Location, ~.j8 through 255 arc connected to pins PO thro ugh P7. except the pms are can· nected to tho.e locati ons' flip-flop outputs rather than input • . For example, writing to location ~55 \\ rite the Oip-fl op with either 0 or 1 (onl y the low-orde r bit matlers during the \Hite). and lhat flip·Oop drive external output pin P7. Thu.,. an a"cmb ly- Ianguage progra mmer can read or write a mic roprocessor's external data pin' ,impl y by readi ng or writing parti c ular data memory locations.
PO.
!~ 23gB
..
441
Performance Extensions O ne difference between real processors and the basic processor architecture in this chapter IS lhat many real processor are pipelined (see Section 6.5 for an introduction to plpeltnmg). The basic. three-instruction arc hitecture uti lized a controller with three stages: ferch, decode. and exeClIIe. By inserting appropriate pipeline registers througbout the deSign and mod ify ing the controller app ropri ately. we could pipeline the fetch, decode, and execute stages. In other wo rds, as the control un it decodes instruction I. the control unit could be simultaneously fetching instruction 2. Next. as the control unit executes lnstruction I, the control unit could be decoding instruction 2. and felching InstructIOn 3. Thus, rather than processing one instruction every 3 cycles, the control unit could be processing one instruction every cycle. Each instruction still takes 3 cycles to process (3 cycle latency), but the pipelining resu lts in single cycle throughput. The net result wo uld be that programs wo uld execute three times faster. Another extension involves creating deeper pipelines. Thu . rather than just three stages (fetch, decode, execute), we might break the stages down to stages of even finer granul ari ty (e.g., fetch. decode, read operands. execute. store reSUlts). Creating finer grained stages may shorten the longest register-to-register delay. which enables a fasler clock freq uency. The net result would again be faster program execution. Another extension involves having multiple ALUs in the dalapath. The control unil may then perform mUltiple ALU operations simultaneously in the datapath. One fonn of this extension involves a processor whose instruction set use in tructions with multiple opcodes and associated operands in a single instructi on. known as a Very Large Instructioll Word (VLlW) processor. Another form uses a processor with a control unit that reads in multiple instructions simultaneously and then ass igns those instructions to execute sim ultaneously on available ALUs, known as a superscawr processor. A high-end des ktop processor may support perhaps 5 simultaneou instruction . with per~p 10 stages of pipelining. Thus. at any moment. such a processor may be in the middle of processing 5*10 = 50 different instructions. Needless to say. modern proces or architectures can become quite complex. This chapter described the basic idea of how a programmable proces ors d ign works and how the design cou ld be extended to support a fuller instruction set. We lea:'e the ro le of describing a complete processor. as well as modern processor de i!!n lecbniq ues for improved performance (such as pipelining. caching. elc.). to lext~ks on computer architecture.
EXAMPLE 8.5 Motion·tn-the-dark detector in assembly language Secll()n 1.3 IIleluded an example. ill u'lwted in Figure 1.13. Ihat ulili/.cd to microprocessor to imple· menl a mOllon ' IIl'lhc-dar~ deteclor. That ,coli on utili7ed C code 10 c mpulc the expression PO • [0 && ! [1 In th" example. we ,how thc underlying ""cmbl y code Ihm would implemenlthat C ex pre,,,on. A"umlllg lhat the lIlicroproce"or', eXlemal pin' 10.. 17 'II1d PO.. 1'7 are mapped to Uo.s ltJ memory hx:atlon ... a.,
o
10
Figure 8 15. we can program Ihe c"' pre,\lOn 111 a"'5,clllbly as follows:
MOV RO. 240 /I move 0/240/. whIch" Ihe value at pin 10. IIll0 RO MOV R I. 241 /I mOve 0/241/. will h " that va lue at pill II . into RI '(JT R I R II/compute 'II . ""unllng e,,'lencc "f a complemenl instruction AND RO. RO. R II/compute 10 && ' II . ""ullll ng '"I AND I", truction \110\ 24K. KO 1/ move re,u lt 100/248/. wh,ch" pill PO
8.7 CHAPTER SUMMARY III this chap ter. we stated (Section 8. 1) that programmable processors are \\idel)' u"ed for implementin g a system 's desired functionality. due in part to their easy :\\'ailabilil\ and short design ~ime (namely. writing software). We provided (ection ·- l the basic ~hi tec ture of a programmable processor. consisting of a general-purpose datapath ha"ing a register file and ALU: a ol1trol unit having a controller. Pc. and IR: and memories ~ r storing the program and the data. The control unit would fetch the ne~( in tru tion from nfiguring program memory. de ode the instruction. and th.en execut~ the I~Stru U n b~ the datapath to carry alit the instru tiOIl 'S peCltied perau n. \\e then de ' igned t tion
442
~
8 Programmable Proc essors
8.3) a simpl e Ihree·i nstruclion prog ra mm able processor. and showed how a program wo ul d be re presented as Os and Is (machine code) in the processor's program memory. We wenl fu rther 10 des ign (Sectio n 8.4) a six· in struc tio n processor. a nd discussed how further eXlensio ns could be made to add mo re instructio ns and hence achieve a more rea· sonable processor arc hilecture. We provided (Secti on 8.5) an example of assembly and machine code for Ihe six·instruc ti o n processor. We discussed a rew ex te nsions to the pro· grammable processor a rchitecture (Section 8.6). Programmabl e processors are typicall y produced in huge quant ities (nu mbering in the tens o r milli ons. or even bi ll ions). a nd so tre me ndou s a!te nt ion is given to thei r design. Readers should rea lize that the programmab le processor des igns in this chapte r are ex tre mel y simp listic and used for illustration purposes on ly. Ye t, seeing even the si m· pl istic desig ns, yo u hopefully now have an understandi ng o f the principle of how a programmabl e processor works. Modern comme rcial processo rs are based on the same principles-instruc ti ons arc stored as machine code in program me mory, control units felc h. decode. and execute Ihe instructions. and datapaths support the operations of the instrucli ons using regis te r liles a nd ALUs. Modern processors just do a muc h better job, usi ng conc urrency. pipelining. and ma ny othe r techniques to o btain high ciock freq uen.
8.8 Exercises ... 443 SECTI O 83' A THREE I ST . . " . R CTi ON PROG RAM~ I RLE PRO ESSOR 8.6 If :1 processor's in struction has 4 bilS for thl! 0 'f '. processor Suppan? pcode. ho\\ many 1>O~' lblc 1Il 'llnl tion., can the 8.7
\~hat does the following a\SCl11bly pro mill which
II
.~
.
'
'.
MOV R5 19' AgD' toe, the th rcc- IIl!'oo lruCIi On Ili stme ti o n SC I of . " D R5. R5. R5: MOY 20. R5. 8.8 Whal doe, Ihe following , . bl . thi s eh a ~CIll y program . which u 'c~ Ihe Ihn.:c-i ll ~ lrlU': li on in!<.lruc( . r . 'On SCI a . apler. COm pUle? MOY R4. 20: MOY R9 18' ADD R4 R4 Rl). R4, R5: lOY 20. R9. '" . . MOY R5. 30: ADD R9. Ihl s chapter. com pUle')
8.9 Using th e three-instructi on ill~lnlclion .sct of Ihi!- chapter. wri te updales Ihe (lain memory D as follow.: DIOI = DIOI + Dill . 8.10 Using Ihe Ihree·· I ' " .
Ull
th~cOl '.
I
b y program Ihal
'" inS nlCIl 11 II\Mructl on ~c l of 1111:-' chupler. write nn a~,c l1l bl )r . Update' Ihe dala memory D a' follows: DI41 = DIII. 2+ D1 21. y I ogr,II" Ihal
8.11 ~ol1\'c n. the following :I\scmbl y program 10 machine code ba,,"-cd on the Ih . ' . "" Irucllon ,el of Ihis chapler: MOY R5. 19: ADD R5. R5. R5: MOY 20. R5. rce·m,lruClion 8. 12 Lisl Ihe b'Isic regl!-. . IcrI memory IrJnsfcrs and opcmlion... Ihut OCcur duri ng each clock c " the followlflg progmrn.
ba~cd on the Ihrce-ill \ truclion i ll~lntClion ~CI of Ihi
I: MOY RI. 9: ADD RO. RO. RI.
.
J
'
yclc for
lOpler: MOY RO.
cies and fast program execlItion .
SECTION 8.4: A SIX· INSTR U TlON I'ROG RAMMA IJ LE I'ROCE SO R 8.13 Li !o.I the basic regbtcr/mclllOry transrcr~ and operali on) Ihal occur during c'lch
J k on the \ ix-instruction il1 \ tnl clion \ct f thi s' h-C oc - cycle for Ihal Ihe COl1lenl or DI 91 i,• O.' MOY R6.#• I' MOY R5. 9'• JM""Z '5. " I I>0 II' : cADD ,'pIer. ,-,- 1, R5"",uming R
Ihe follOwing progmm.
8.8 EXERCI SES
bn~cd
label I : ADD R5. R5. R6. Whal b Ihe vallie in R5 after Ihe program Compieles? SECTION 8.2: BASIC ARCHITECT URE
t;;:";J.S
8.1
If a proce ssor's program counter is 20-bits wide, up to how many \,,-/ords can the processor's instructi on memory hold (ignoring any special tricks to ex pand the inslruc tion memory size)?
~.s 8.2
Wh ich of lhe fo llowing are legal single·cycle dalapalh operalions for Ihe dalapalh in Figure 8.2? Explain your answer. (a) Copy data from a memory location into another memory location. (b) Copy two registcr loca ti ons into two memory locations.
(c) Add dala from a regisler fil e localion and a memory localion. sloring Ihe result in a memory loca tion.
r---. PLUS
8.3
Whi ch of the follow ing are legal single-cyc le datapath operations for the datapalh in Figure
8.2? Explain your answer. (a) Copy data from a reg ister fi le locat ion into a mcmory locati on. (b) Subtract data fro m two memory location s and store the result in another memory location. (c) Add data from a register fi le localion and a memory location. storin g the res ult in the same memory location . 8.4
Assume we are using a dual-port memory from wh ich we can read two locations simulta-
. 5. R6:
8.14 Add u new j ll ~truclioll to the ~ i x-i n structi on in~tnlct ion \Cl of thi ... dl'lpler Ih ' ' al perfo b' ' . II wlse AND of two registers and stores the rC5ult in .a third rcgiMcr E:
8.15 Add a ~l~W in ~ tructjon to thc six-instructi on in~ truct i oll :-oct of this ch3ptcr that rfom ' uncondlt,onal Jump Uu mps always) 10 a location specified by a 12.bil on,cl E pe IS an palh, control un il, and Ihe controller's FSM as nceded. . Xlend Ihe dala· 8.16 ~dd a new. instruction to the six-instruction in truction sc t of this Ch3plcr th at perform.s
.
,f Iwo reglSlers are equal. 10 a localion specified by a 12-bil offset. EXlend lhe d:.J ~mp control un'l. and Ihe cont rollers FSM as needed. lapalh.
8.17 Us i~g the six-instruction instructi on set of this chapter, wri te .111 assembl y program for th
10wll1g C code, which com pUles Ihe sum of Ihe firsl N num bers. where D191 . Hillt: Usc a regisler 10 fi rsl SlOre N.
is an h e fol· Ol er name for
i -l : sum-O : wh i Ie (i ! ~ N)
neously. Modify Ihe d3lapath of Ihe programmable processor of Figure 8.2 10 support an
sum
instru cti on that performs an ALU operation on any two memory locations and stores the re ult in a register fil e locati on. Trace through the execution of thi s opera ti on. as illustrated
i
3
sum + i; i + l:
in Figure 8.3. 8.5
Delerm ine Ihe operalions requ ired 10 instrucl the datapalh of Figure 8.2 to perform Ihe opera· lion: DI 81 = (D[4] + D15J) - D[71. where D represents the data memory.
8. 18 Using Ihe eXlended inslruclion sel you designed in Exercise 8. 16. wrile an 35sembl for Ihe C code in Exercise 8.17. Y program
44-'
Programmable Processors SECTIO N 8.5: EXA MPL E ASSEMBLY AND MAC HINE PROGRAMS
8.19 Define
twO
new daw movement instructions for the . . ix-i nstruction
inSlruction sel
of thi
chapter. Extend the datapath. con tro l unit. and the controller's FSM as needed.
8.20 Define two new arilhl1lcLic/logic instructions for the six-instruction instruction set of this chapter. Extend the datapath. control unit. and the controller's FSM as needed.
9
8.21 Define two neW now-or-control instruc tions for lhe six-instruction instruc tion se t of lhis
chapler. Ex.tend the datapath. contro l unit. and the con tro ller's FSM as needed. 8.22 Assuming th at the microprocessor's ex tern al pin s 10.. / 7 and PO.. P7 are mapped to data memory locations as in Figure 8. 15 and an AN D instruction has been added to the six-instruction instructi on ~et of this chapter. create an assembly program th'll will output 0 on P4 if all eight inputs 10.. 17 are is.
Carole grew lip in 3. country where the best swdcnts went to engincering school. as engineeri ng was highly respected. "1 W:lS good in school. so engineering secmed like a natural option. I \Vas also very interested in building things. and very curious abou t how one bu ilds new thing s-so I was attrac ted to engineering aI an early age. around 10 years of age." Carole has worked at Intel for 15 years. She was Olle of
the original architects of the popular MMX (Multimedia Extension of the Intel Architecture) pan of Pentium processors... It was fascinaling to learn the algorithms used to compre s video and audio, and to inven t new instructions for th e Intel Arch itecLUre to run these applications efficiemly. It is not always easy for processor architects to quantify the benefi ts of new fCJlUres, and to motivate the expense in si licon area (or chip die size) for new instructions. In the case of mu lt imedia applicutions. the benefits are well understood: running a video clip at a few frame s per second. or running it in real time (about 30 frames per second) makes a huge. vis ible difference to everyone:' As is the case with so many engineers. she is
very proud of what she accomplished: "When the first Pentium processor with MMX came up. it was really rewardin g 10 think th3t a sma ll piece of my mind was in all of these machines running video rea l time popping up everywhere."
Carole was also one of the architects on the Intel I Hewlett·Packard tearn that defined the Itanium computer
architecture. "This was a unique opponunity to define a processor 'from scratch.' Technically thi s was a very challenging project. and working with so many top notch architec ts was very enriching. But I also learned what it takes to bui ld somethin g big. involving a very large team, and two large companies. The two companies had different
cultures. diffe rent methodologies, and reconciling the differences was sometimes more challenging than solving
the technical problems. But this is all pan of 'building th ings: and th is was a gre.u lesson in leadership." \Vha( Carole likes mos t about her career is "the constan t change. After 22 years as a computer architect, I a111 still doing new things every day. Computer science is a work in progress. and it offers new opponunities that one has 10 grab. and run with . Thi s is where the fun is."
Asked to give some advice to students. Carole suggests two things:
"Stay at school as long as possible. Get a PhD if you can. To be able to adapt to constant change, you will need a very robust. and theoretical foundation. Only learning how to do things is not enough; it will get you a job for 2 years. but then yo ur skills wi ll be obsolete." "Be open for change. It is imponantto build an in-depth expenise in one area. in my case, it is computer architecture. But one has to be ready to use thi s expertise in
many differe nt projects. with different people, and more and more in different pans of the world. Fifteen ye"" ago multimed ia applications were the focus of many computer architects. Today it is bioinformatics and data mining. Change requires a lot of work to learn new domains. but not adapting to change is not an option."
Hardware Description Languages 9.1 INTRODU CTION ! DoorOpener In thi s book, we have been drawi ng the circu it. that we destgn. . For exam . , pIe. .III Chapter 2. we deSIgned an aUtO~lall ~ door opener circuit and drew the circu it shown til F,gure 9. 1. A drawi ng has more in formatlon .than is really necessHry to descri be the ci rcllit. In particu lar, the drawing gives information about the Figure 91 D . locatton of the inputs and outpUts: in the draw ing or Ftgure 9.1. the inputs are on the Icft, the output on . ruwn clfcuit. the n ght, and the c input is on the top, the h input in the midd le. and the in bottom . The drawlIlg also gives infomlation about the size alld I . P put on the . I . . . . ocm lon of th nents III tle Clrcull: the IIlvertcr IS Ht the top the OR gate below tl ' e compoD h ' , ' l C IIlvcner th " ate ' e I1. Th, e . on . ft e nght " . and each component is abollt a half inch by ,a1I alf II1 d A. D gtves til ormation abo ut the wIres tOO' the wire from the inverter e rawlllg . ' goes to the ri h h d h . own, t .en to the nght agalll. for example. However, all that information . g t. t en drawlIlg tS really Irrelevant, and has nothing to do with how the des ign will be a~out the tmplemented. We . P ystcall Il ' hy . had to draw the circuit somehow. so we chose to dr'I' \V th e CIrCU III t e manner s hown III the figure. But we could have drawn the circui t many oth er ways too. A drawlIlg of a circuit is commonl y referred to a a ci rcui t schematic. A problem with drawing all our ci rcuits arises when we deal with large . . . . F" r CtrcullS Does tlle sc hema~c III tgure 9.2 mean anythlllg to you? That schematic has J'u t a couple .d components-what if there were a couple t1lOusand eomponelllS. as is ' oZen qUlle commo ? . . . ' n. D rawlIlg a large CtrCUIl would reqUIre tremendous effort on Our pan to fig . ' . ~=~t P ace each componelll 111 the drawIIlg. and how to route Wires among the co v 0 ' fI mponenLS A d t . a tool generated the circuit, the tool wou ld have to spend compute time to fio . n vtsually-appealing way to draw the circuit (rather than a paghctti-like me ) "ure OUt a I . 5S . and ueh . . . . d '11 com put all on tS tlme·consumtng an Sll may not resu ttll a good drawing. Funhenno ti les used to store such schematic would be very large. as those tiles would re, the . I . d' f eontmn a ll . <. th at ex tra lIl/ormallon about the prectse ocallon an SIze 0 every component . All th at extra I Substamial content or thischapter was contributed by Roman Lysccky.
44S
--------
---
-
446
9.2 Combinalional Lo . D " . glc escrlptlon USlllg Hardware Desc ription Languages ... 447
Hardware Descriplion Languages
10 describe the slruclural illlerconnections . descri be Ihe beh ' r • or componelll,. hUI abo II1clude melhods for t" 10 aVlor a componelll Ihen I ' Mod . . . the use or HOLs al ' II . 1>e Vo,. em dlgllal de"gn relics heavily on . . ,t tage; of de.-.:,cI, on . after Chapler 3. eClion 9.4 aft er hapler 4. and ection 9.5 c11'1pters' F i r Il1e,e sections muy be covered all at onCe "rler compleling Ihose earlier ' r S· un 1ermmore. each seclion hus three pa riS. one ror VHOL one ror Verilog and one lor ystemC Each of Ih se n.-, " d " . '. . pa I 111 ependcllI or Ihe mher paris or Ihe seclion ;0 " rea der II1leresled only 111 one or Ihe HOI " '1 . , ' h . " -'. say ven og. can rend only Ihe Verilog part' or eac seCllon, Sklppll1g Ihe VHOL Or SyslemC pan,. HDLA ;ea~er II1lere ted in comparing Ihe three HOI., may ",,,d Ihe ,ecli ons of " II Ihree '1 . s. ~ . oll1g so. YOllmay nOllce Ihat Ihe HDL, have ,i milar capabililies di frering prim.tn hY IIlHI eII' symax. Tilli , after leaming One HOL th ro ughly. a de'igne; can likely le" ~ 0 1 er OLs qUickly. '
Figure 9.2 Schematics become h.. rd to read beyond a dozen or so components-the graphical inronllation bccolllc!ol a nuisance raLhcr than an ai d.
efron. file size. and lime. would be needed for somelhi ng Ihal is reall y nOI very u erulhumans can'l comprehend circuil drawings or more Ihan perhaps a hund red or so gale. so what 's Ihe poim or drawi ng such circuils? What we reall y wanl is a way 10 just describe the ci rcuil ilse lr- whal arc Ihe in puts and outpulS. whal components ex isl. and what are Ihe conneclions? Ideall y. we wou ld do this description in a texwal language, a that we humans could Iype such descri pli ons wilh a compuler keyboard. just like we type email messages and C programs. We coul d Iherefore describe Ihe circuit in Fi gure 9.3(3) using Ihe lex tual language or English as shown in Figure 9.3(b). We've given names to each gate in the circuil and 10 the illlernal wi res in Figure 9.3(3). (aJ
(b)
We'll now describe a circuit whose name is DoorOpener. The external inputs are c, h and p, which are bits. The external oUlput is I, which is a bit. We assume you know the behavior of th ese components:
An inverter, which has a bil inpul x, and bit output F. A2-input OR gate, which has Inputs x and y, and bit output F. A2-input AND gate, which has bil inputs x and y, and bit output F. The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists 01: An inverter named Inv_1. whose input x connects to
Figure 9.3 Describing a circu il using a tcxtual language rather than a graphical
drawing: (a) schemalic. (b) lextual description in the English languagc.
external input c, and whose oUlput connects to n1. A 2-input OR gate named OR2_1. whose inputs connect to external inpuls hand p. and whose outpul connects to n2. A2-input AND gate named AND2_1, whose inputs connect to n1 and n2, and whose oUlput connects to external outpul I. That's all.
or cou rse, Engli sh is not a good language ir you want to use a computer tool to read in the descripti on-a computer tool requires a language with a precise syntax and precise meaning ror every language construcl. CompUler-readable languages thus evolved in the I970s and I980s ror describing hardware circuits. Such languages became known as hardware descriptiol/ lal/guages, or HDLs . Hard ware descripti on languages not only enable us
~ 9.2 COMBINATIONAL LOGIC DESCRIPTION USING
HARDWARE DESCRIPTION LANGUAGES Structure This chapter's introducli on soughI 10 describe a circuil lIsing a lex wal language. We now show how so~ e dlrre r~m HOLs descnbe a circll il. The lerm stTllcture is somelimes used 10 rerer to a CII'CUII. wllh slructure meaning an interconnecti on or componenl.
VHDL Fi gure 9.4(c) shows a VHOL descripli o~ of Ihe DoorOpeller circuil or Figure 9.4(a). For convellience, we've 3 1. 0 shown the Eng" h descri plion in Figllre 9.4(b), and Lhe correspondence belween Ihe English descnpllon and Ihe VHDL de cripLion. Th ~ d ~cripl i on begins with an elltity dec laralion, which defin es the de ign's name and Ihe deSign s IIlpUts and outpulS. known as ports. An entilY declaration says nothing aboul Ihe IIllemals or Ihe deslgn-:-Just the deSign's .name and interrace. The description lists the port names and defi nes thCll' Iype. which III thiS case is Iype s td _ l og i C. That type es enliaJiy means a bil, bUI isn'l bui ll imo VHDL (Ihe predefined bit type in VHOL is too limiled, for rea ons beyond our scope here). To use s td_l 09 i C, we aCluall y musl include Lhe stalements: " library ieee ; use ieee . std_logic_1l64.all ; " a1thelOp oflhe fi le. The description continues wilh an architectllre definiti on, which descri bes the intemals of the design. We named Ihe archilecture Circllit. bUI we could have named il anything we wanted; DoorOpellerCircllit, DoorOpellerStructllre, Structllre. or even Fred, although we want a name Lhat is helpful in underslanding Ihe architeclure. The architecture lans by declaring what components the design will be uSing-Lhose components must be defi ned elsewhere, perhaps earlier in Ihe description's file. or perhaps in another file. We' II discuss those componenls' definiti ons later- for now, as ume they are omehow already defined. Each componenl declaration mUSI define the inputs and OUlputs or each componenL and those inputs and OUlpUIS mUSI match the component 's entity declaration (found el ewhere) exactly.
448
9 Hardware Description Languages
9.2 Combinational Logic Description Using Hardware Description Languages
The bold words in the desc"Ip t'IOn represent reserved words. abo known", keywords YHDL. We cannot use reserved \YOTdr ... .. . S lor names of entit ies. arch itectures. signal:::, 1I1stantlated components. etc.. as those words have spec ial 1l1eaning that guide YHDL tool to understand Our descriptions. .
DoorOpener tnv_'
111
.
library ieee i use ieee.std_logic_1164.alli .... entity DoorOpener is ........... / / port (~c, h, p : in std_logic; (a) ... "/,,,_... _... ---~~. f : out std_logic We'll now describe a circuit whose name is DoorOpener, ..................... -- .J, ;. •.. The external inputs are c, hand p. which are bits .......... .' .• nC:! DoorOpener; The extemal output is f. which is a bit. ---------------- .' architecture Circuit of DoorOpener is
We assume you know the behavior of these components: _------ component Inv . An inverter, which has a bit input x, and bit output F. ----port (x: in std_logl.c:
A2-,nput OR gate, which has Inputs x and y. ____
F, out
Summarizing. the YHDL structuml description has an entity that de crihcs the design's na1l1e, "'puts. and OUlputS: a declaration of what componen ts wi ll be u,ed: a dec1amtion of 1I1tem31 s t g~a l s: and finally, nn in !antialion of all component,. along with their Interconnecti ons .
The entity thm we've just defined could then be used as 11 component in another enti ty. Ycrilog Figure 9.5(c) s h ~ws a Yerilog description of the O()orOpeller circuit of Figure 9.5(3). For conven ience. we ve also hown the English description in Figure 9.5(b). and the correspondence between the Engli h deSCription and the Yerilog descri ption .
st,,-logie 1:
and bit output F ---end component : A 2-input AND gate, which has bit inputs x and y, ........ ------- component OR2 and bit output F. ......... port (x. y: in stcLlogic; .... F : out std_logic): The circuit has internal wires nl and n2, both bits..... .......... end component ; .. ........ component AND2
DoorOpener Inv_'
------~::>....
The OoorOpener circuit internally consists of: port (x, y: in std_logic; An inverter named Inv l ,whose input x connecls 10 .. ""'.. ...... F: out std_logic); external input c, and-whose output connects to n1 . "'.. '" .......... end component ; A 2-input OR gate named OR2_" whose inputs ........ ''''''',""'... signal nl, n2 : s td-log ic; - - in ternal wires connect to external inputs hand p, and whose oufPul... ',' connects to n2. .. ........... ' .. ~egin A 2-input AND gate named AND2_' , whose inputs -___ ......... ' Inv_l : Inv port map (x=>c. F=>nl); connect to nl and n2, and whose output connects 10 ---... _...... ". OR2_1: OR2 port map (x=>h. y=>p. F=>n2) ; externaloutput f. --'AND2_1: AND2 port map (x=>nl,y=>n2.F=>fl; That's all. ____________________________________________ end Cireui t; (b )
(c )
Figure 9.4 Describi ng a circuit using a textual language ralher than a graph ical draw ing: (a) schematic, (b) tex tual
description in the English language. (c) textual description in the YHDL language . Bolded words are reserved words in YHDL. The description then includes a declaration of the des ign's internal sigllals, which are essentially internal wires. Next to that declaration, the description includes an example of a YHDL comment : "-- i nterna 1 wi res". Comments start with "--" followed by any tex t we want on the rest of the line. That text is ignored by YHDL tools, but is useful to us humans who must read the descriptions. Fi nally, the descri ption instanti ates the circuit 's components and defines those components' connections. For example, the description instanti ates a component named 11111_1, which is a component of type 11111 (which we declared earlier in the YHDL description), and indicates that 1/l1I_l's input x connects to c, wh ich is an external input. An alternate, more concise port map notation omits the port names . Using this notation, we cou ld instantiate ou r inverter by writi ng "Inv_l: Inv port map (c . nlJ :". The order of the signal s in the port map of IlIv corresponds to the order of the ports in the component definition of Illv. We wi ll use this alternate notation in subsequent examples.
(a)
, m04u1. tnv(x. F): input x; output F: I I deta i 1s not shown " \ " \ endmodu1. We assume you know the behavior of Ihe~'CfOmpo~lt~tt: \_ .. - .a4ule OR2 (x. y. F); An inverter, which has a bit input x, and bit ou.tput F.Al-......... \ input x. y; A 2-inpul OR gate, which has inputs x and y, ~('---- \ \ output F; andbiloutpulF \ \ \ /1 details not shown A 2-inpul AND gate, which has bit inputs x and y, ~, ___ :~ \ .ndmodu1.
We'll now describe a circuil whose name is DoorOpener. \ ,/ The external inpuls are c, hand p, which are bits,,' \ I The external output is I, which is a bit. , ~/
and bit output F.
~~-"',\lDOd.u1e AND2lx, y.
\ \
The circuit has intemal wires n1 and n2, both bits. "
\
\
\
\
F);
input x. y; output P;
\
' ....,. '" \ ~ ....~ ~ .. details not shown The DoorOpener circuit intemally consists 01: ., \ \~~ul. An inverter named Inv_1, whose input x connects to ........" \ \ \ external inpul c, and whose output connects to nl ......, .. ' .... ~U1. DoorOpener(c, h, p,
A2-input OR gate named OR2_' . whose inputs '_,
-__ '" \ 'input e. h. p:
connecllo external inputs hand p, and whose output ... _... ...., ..' ....: output f; connects to n2. --...... " .. wire n1. n2;
-"<
A2.input AND gate named AND2_', whose inputs-____ Inv Inv_l (e. n11: connectton' and n2. andwhoseoutputconnectsto ----____ OR2 OR2_1(h. p. n21: extemal output f. --AND2 AND2_1(nl. n2. fl: That's alf. ____________________________________________ ' - u l e (c)
(b)
Figure 9.5 Describing a circui t using a textual language rather than a graphical drawing:
(a) schematic. (b) textual description in the English language, (c) textual description in the Yerilog language. Bold words are reserved words in Yerilog .
.
•'
~
__
w_
J
-
f);
450
9.2 Combinational Logic Descrlptlon . . USing . Hardware Desc ription Languages ~ 4S I
Hardware Description Languages Tbc description begins by defi ni ng modules for an inverter 1111'. a 2- input OR gate OR2. and a 2-input AND gate AN02. We' ll skip discussion o f tbose modules, and begi n our discu"ion wi th tbe defini ti on of the founb modu le OoorO"eller. T be dcscription declares a modllie named OoorO"eller. The module declaration defi nes a des ign's name and the names of tb at design's inputs and outputs. known as pons. Tbe modu le declarati on says nothin g about tbe intcrn als of the design or the pons-just the design" name and interface. Tbe descript ion tben defi nes tb e type of each pan , assigning the types illplI l and
DoorOpener Inv_'
.include , .include /, 'include :/ , .include
0"11'"1 in thi s example.
desc~be
Tbe descrip tion tben i ncludes a declaralion of tbe design's internal wires. named II I
stand our descriptions. Summarizing. the Veri log slructural description has a mod ule th at describes the des ign name. lists the module's inputs and OUlpu ts, and spec ifies the type for each input and output : a dec larati on of intern al wi res: and fi nally. an instanti alion of all components, along with lheir il1lercon nection s. System C Figure 9.6(c) shows a SystemC descripti on of th e OoorOpener c ircuit of Figure 9.6(a). For conven ience, we've also shown th e Engli sh descripti on i n Figure 9.6(b), and the correspondence between the English descripli on and the SystemC descripti on. The SystemC language is built on top of th e C++ programming language, but it is not necessary to be an expen C++ programmer LO use Systemc. However, it is imponantto keep in mind that cenain restrictions ex ist as a result , such a not using C++ keyword s to name modules, ports. signal . etc. Before defin ing th e circuit behav ior. we musl include th e statement "IIi n c 1ude " sy s t emc . h"" at the top of each SystemC fi le. The description begins with an SC_MODULE declarati on, which defines the design's name, in thi s case OoorOpeller. The
:: /
·or2.h· 'and2 .h'
ooo-rop-e-n-e-r~---iY· ~C_MODOLB
We'll now a circuit whose name is (OOorOpenQr I The exlernalmpuls are c, hand p, which are bits. -- - ----~L.---- -- .o 10< The external output is I, which is a bit _________ ___ __ .c=out::~~~~~> C i h, p:
(tl _______
and 112. Finall y. tb e dcscripti on instantiates th e circuit 's co mponcnts and defines th ose componenls' connecti ons. In tbe OoorO"ell er modul e. tbe descripti on instantiates a component named 1111'_ / . wbicb is a componenl o f type III I'. T be connecti ons to the inputs and outputs of tbe i nstantiated components arc specified in tbe order in wbich the component's modu les declare th e inputs and outputs. In tb e instant iati on of 1111'_1, the input c is con nected to the in pu t x of the IIII' component. In Veri log, th e module does not need to specify the interface of a component witbin tbe mod ule instanli aling th e component. For example. the OnorO"eller modu le does not inc lude a declarati on o f which components it wi ll instantiate or any informati on regardi ng tb ose components. The components, of course. must be defined elsewhere. perhaps earlier in th e same fi le as shown in Figure 9.5(c). or perb aps in anotb er file. For reference purposes. tb e example shown here provides incomp lete speci fi ca tions for tb e III I'. AN02. and OR2 components in order to clearly show the pons and inter face For lhese component s. In place o f speci fying lhe interna l bebav ior of th ese components. we simply included an example of a Veri log comment. Com ments stan witb •. I I" and th en any tex t we wa nt on th e rest o f th e line. The bo ld words in th e descriplion represent reserved word s. also kn own as keywords. i n Veri log. We cannot use reserved words for names of modules. pons, w ires, instantiated components. etc .. as those words have spec ial meaning that guide Veri log tools to under-
(a)
• systemc . h·
"inv.h"
f
We assume you know the behavior of these components' ~ / i~ter~al wire~ An inverter. which has a bit input x and bit output F ' ,/ I ;-~o:n- ~.~-dog 1c> n2; A2·inp~t OR gate. which has mpuls x and V, . ,I'I' lnv Ine~7en cc arat ons and bIt output F. / OR2 OR2 l' A 2"nput AND gate, which has bit Inputs x and y, / lIND lIN02 and bIt output F. // II compo;;e~t instantiations T .. . / " SCS'l'OR tDoorOpenerl . Inv 1 (' Inv 1'1
nt·
i·
he CirCUIt has Internal wires nt and 02, both bits/
1') ,-/ , -C'/ OR2 - 1 ('OR2 '
The DoorOpener circuit Internally consists of: , /" /, .. ,:, :. lnv 1 x (c I . An inverter, named Inv_l, whose input x connects to ..!'~:::~~ -~;;"'"F (n1 eX,ternallnput c, and whose output connects to nJ......... OR2_1. x (h) j A 2'lnpul OR gate named OR2_'. whose Inputs .<, _____ ~;r OR2_1. y (pi;
<_______
lnv:1:
i
AND ' 2-1
-
('
-2
.'
AND _1 )
j
connect to externallllputs hand P. and whose output /
OR2_1 . F (n2) ; / ________ N-ID2_1. x I nIl; A 2'lIlput AND gate named AND2_' , whose Inputs ,~-------lIN02_1 . Y(n2 I ; connect 10 01 and n2, and whose output connects to AND2_1 . F (f) ; c~n nec l s to n2 .
~xterna l output f. Thats all. -------------------------------- ------------.....'-),:.. . _ _ _ __
Ie)
(b)
Figur~ ~.6 ~csc ribing a circuit using a tex tunl language rather than a graphical drawing: (:'1) \C hClmllic. (b) textual ~escnpl1on In the English language. (c) Icx lUal dc\criplion in the SY~lcm language. Bold word" arc n.!\crved words In
Systcmc. module declaration says nothing aboutlhe intern als of th e de,ign- justthe de; ign's name. Within the module descri ption, the input and ou tput pons of the design are specified. using the sc_ill<> and sc_olIl<> statements respecti vely. The descripti on li sL~ the pon names and defines thei r types. which in this CHse is type 5c_ 1 og i c. which speci fies a si ngle bit. The description then includes a declaration of th e des ign' internal signal , specified as sc_s iglla/, which are essenli ally intern al wires. Next to that declarati on, th e descriplion includes an example of a SystemC comment: ,. I lin te rna 1 wi res". Comments stan Wi lh "I In and then consist of any text we want on th e rest of th e line. The module then decl ares what components the design will be using. The SystemC module does not need to specify the interface of the component , but ralher ju t the type of component as well as a unique name for each component wi thin th e design. The module defines a constructor functi on SC_CTOR that is responsible for instantiat ing and connectin g the components within our SystemC design. The conslructor fu nclion
__ ...: . . . -...I"l._ .... -
..
--
-'52
Hardware Description Languages
9.2 Combinational Logic Description Using Hardware Description Languages
takes as an arg ument the name of the curre nt Syste mC module. wh ich is in this ca e DoorOpener. Following the SC_CTOR statement after the colon is a list of component instantiations. The Systc mC module's instantiations arc used to ca ll the constructor funclions of each componcnl bei ng instantiated. However, we poi nt out that the connections between the individual component are nO! specilied at this point. Instead. the state ments within the constructor fi na ll y define the connections between the components. For example, the inve rter 11II'_ I's input x is conne ted 10 c. wh ich is an exte m al input. In SystemC, the module does not need to specify the interface of a component within the module. The components. o f course. must be complete ly defi ned e lsewhe re. perhaps earlier in the same file, or perhaps in another fi le. In our SystemC DOO/'Opener desc ription, the desc riptions for the h II'. AND2. and OR2 components are pec ified in other Syste mC li les. In order to use those components. we must include a state me nt at the beg inning of the current file indicating where we can find this descript ion. For example. our DoorOpener description includes the statement "1/ i nc 1ud e "i n v . h "". and the descri ptio n o f the component Illv can be found wi thin this fi le. The bolded wo rds in the descript ion represe nt reserved words. a lso known as keywo rds. in Sys temC and C++. We cannO! use reserved words for names o f modules, ports, signals. instantiated components, e tc .. as those wo rds ha ve spec ia l meaning that guide Syste mC and C++ 100is 10 understa nd our descriptio ns. Summarizing. the Sy temC structural desc ription has: a module that defines the design name: a list of inputs and outputs o f the module specify ing the ir types, a declaration of internal signa ls: a decl aratio n of compone nts prov iding the name for each compone nt. a constru ctor function insta ntia ting the module's co mpo ne nts, and fin ally, the compone nts' interconnecti ons.
Combinational Behavior HDLs typically suppon the ability to describe the internals of a design as behavior rather than as a c ircuit. This abi lity enables us to de cribe the bOHom-level building-block components that we use in a des ign. such as the behavior of a n AN D gate or OR gate . VHDL Figure 9.7 contains a behaviora l description of a 2-input OR gate. whic h you'lI recall we used as a compone nt in Figure 9.4(c). The de cripti on begins wi th the declara ti ons necessary to use 5 td_l og i C. It then decl a re the e ntit y with the na me OR2 as ha ving two input ports x and y. and having output pon F, a ll of type 5 d log i c . whi ch means bit. The de, cription then defines an a rc hitecture named behavior for OR2. That architecture con'I S!!' of a process. whic h i, the VHDL con,truct that describes behavior. The proce" decla ration he re i
library ieee; use ieee.std_logic_116 4 . all; entity OR2 is port (x, y: in st
end OR2;
arcbi tecture behavior of OR2 i. begin proce •• (x. y) begin F <::0 X or y: en4 proce •• ;
end behavior;
Figure 9.7 Behavioral VHDL de,criplion of an OR gate.
453
"process(x . y) ". which mean the process should execute from beginning to end whenever there's a change on x or y-in other words, the process is seflsitive to x and y. A process body (the part between the process's begin and e nd) can contain sequential state ments, just like sequential statements in C, but with a different syntaX. The process shown has onl y one such statement. assigni ng the value of "x or y" to F. "or" happens to be a built-in operator in VHDL, making the internal description of the OR gate imple. As another example of a behavioral description, let's revi sit our DoorOpener example from Figure 9.4(c). for which we created a n arc hitec ture havi ng a structural description. We can alternatively create an architecture having a behav ioral descriptiona VHDL entity may have multiple architecture descriptions for that same entity. Assuming the same entity declaration as in Fi gure 9.4(c). we show an alternative architecture definition in Figure 9.8. The behav ior consists o f a process that is sensitive to Inputs c, h, and p. When the process executes (w hich is whe never c. h. or p changes), then the process executes its one statement, which updates the value off In designing the DoorOpeller circuit, we might start with the behavioral descriparchi tecture beh of OoorOpener i . lion, and run a simulation to ve rify correct begin process (c. h. p) behavior. We migh t then create a structural begin description, and run simulation again to f <= Dot (c) and (h or pi; veri fy that the circuit has the sam~ funcend procells ; tionaliry as the behavior. In fact, tools exi st end beh; that automatically convert such behavior to a circu it. Figure 9.8 Behavioral VHDL descriplion of When writing a VHDL process the DoorOpeller design. describin g a combinational CirCUli S behavior. care must be taken 10 include all the circuit's inputs in the proces 's sensiti,~ty li st. Omitting an input is not a VHDL error. but such o mission results in different behavior than combinational behavior-wi th an input omitted, the output does not change when that input changes. meaning there must be some storage in the circuit. Verilog Figure 9.9 contains a behavioral description of module OR2lx.y.F); a 2-input OR gate, which you'lI recall we input x. y; output F; used as a component in Fi gure 9.5. The reg F; description begins by declaring the module named OR2 and specifyi ng that the modu le a1wa.ya @ (x or y) begin has three ports named x, y. and F The descripF <= x I y; tion the n defin es that the ports x and yare end both inputs and the port F is an output. The enc!module description the n defines the output F to be a Figure 9.9 Beh., ioml Veril02 reg output. In Veri log, all ports are by default description of an OR gate. assumed to be a wires . whic h do not store va lues. Instead . wires can onl y creme connections between components. If we want to assign a a lue to an output pon. we mu t defi ne the port to be a reg. which indicate the output pon stores the value - we i20 to the port. The Vcrilog code for our design continues with an always procedure that
454
Hardware Description Languages
9.2 Combinalional Logic Descri ption Using Hardware Descri ption Languages
delines a bloc k of code Iha l wi ll be rc pealedl y c xcc uled w hcnever a c ha nge occurs on an input in Ihe block', inpul li s t. The a lways procedure declaralio n is "a 1ways @(x or y ) ". which Illeans Ihe procedure should exec llIe from begi n ni ng 10 e nd w he never Ihere is a change on x or y-in olher words. Ihe proced ure is sellsitive to x and y. The always procedurc's Sialements (Ihe pan bel ween Ihe procedu re's begill and elld stalemen l) can contai n seq uential Slalements. j us l like seq uemial state me nls in C , bUI with a different sy11lax. The block s hown has on ly o ne suc h Siale me nt. ass ig nin g Ihe value of " X I y" lO F. w he re I is a buil t- in Veri log operali o n 10 compute an OR. As a no lher examp le of a behaviora l descriplio n. lel's revi s il ou r Doo rOpelle r module DoorOpener (c, h, p, f) ; example from Figure 9.5(c). for w hi c h we input c, h, Pi output fi c realed a s lruclural verilog de cripli o n. We ea n reg f: alienlalive ly creale a behaviora l description. Figure 9.10 presems a behavioral Veri log always @(c o r h or p) begin de cription of Ihe DoorOpeller c irc uit. The f <= (-c) & (h I p); module declaralion is s imilar lO Ihe struclural end descriplion of Figure 9.5(c). but in Ihe behavendmodule ioral description we need 10 declare lhe outpul Figure 9.10 Behavioral Veri log f as a reg. The beha ior consis ls of an a lways descriplio n of Ihe DoorOpener design. procedure sen . itive 10 inputs c. iI. a nd p. When
descriplion. We can a ltern atively creale a behav io ra l descripti on. Figure 9. 12 presents a behav io ral SystemC description of the DoorOpel1 er ci rcuit. The module declaration is the same as lhe slructural descriptio n of Fig ure 9.6(c). The behavior cons iSIs of a single process. named comb/ogic, Iha! is sens ilive to inputs c, II , and p. W hen the process execules (which is whe never c, ii, or p chan ges), Ihen the process executes ils o ne statement, which upd ales Ihe value of f by ass ignin g lhe value
the procedure execules (wh ich is w he neve r c. iI. or p changes). Ihen lhe procedure execu les a si ng le s lateme nl thai upd ales lhe value off, by ass ig ning Ihe value .. (-c) & ( h I p) ". w he re - . &. a nd I perform the inven , AND. and O R o peralion s. res pective ly. In designing lhe DoorOpelle r c ircuit. we mighl sian wi lh Ihe be hav ioral descriplion, and run a imulation 10 verify correCI behavior. We mig hl lhen creale a slructural desc ription. and run a simulati o n again lO veri fy Ihal Ihe ci rcuil has lhe ame fu ncti onality as the behavior. In fact. tools exist lhm aUlomalicall y conve n such behavior to a c irc uit. SystemC Figure 9.1 1 contain~ a SyslemC behaviora l de criplion of a 2-inpul OR gate. which you'll recall we used as a compone nt in Figure 9.6(c). The SystemC description declares lhe module wi lh the name OR2 and has IWO inpul pons x and y and one OUIPUI pon F. all oflype sCl ogi c . indi cati ng each inpul and outpu t is a n individual bi!. Thc modulc defines th c conlructor function SC_CTOR that consisls of a ~ingle proce" named comh/ogic defined a' a SC...METflOD . SC...METflOD is o ne Sy'tcmC con'lnlct lhat describes behavior. The proces~ declaration here i~ ··SC.METHOD (comblogic); s en S i i v e ~ < /, << y; ". which mean' Ihe
"(-c . read(»
& (h.read()
I
Bc_ in<8c_ logic> c, h, p; sc_ out<8c_ logic> f: SC_ C'I'OR (DoorOpener) (
SC_METHOD {cornblogic) ; sensitive « c « h «
Pi
vo i d comblogic () (
.write ( I-c. read ()
&
(h. read ()
I
p. read i ) ) ; )
);
FiIgure 912 . I S YSlemC deSCription of . Be h,vlora the DoorOpellerdeSlgn .
p . re ad() )", where - performs an invert o peralion . & performs an AND operation. and I perfomls an OR operation . In designing Ihe Door?petler circuit, we might stan Wilh the behavioral description. and run a SImul atIo n 10 venfy correct behaVIor. We mIght then creale a tructura] des . ti o n, and run s imulation again 10 verify lhat lhe circuil has the s:u."e functionality .:~ behaVIor. In fac l, lools exist lhat automati cally conven such behavlOr to a circuit.
'include ·systemc hSC_ MODOLE (OR2)
(
Bc_ in x, y 8c_ out F:
455
process wi ll exec ule the c· . beh ' .. . orcUI[ aV IOr desc nbed on the funcuon comb/ogic w henever there . h IS a c ange o n x or y. In other words, the process is sellsilive to x a nd y. The process body i defined on the funcllon comb/agic and is declared as "v 0 i d comb 1 09" c ( ).. The f . (h . process unCUon t e pan belwee n the open brace " {" and close brace "}" ) can contain sequential sta!emenlS, JUSI li ke seq uential sta!emenlS in C or C++. bUI somelimes requires different synt ax. The process shown has onl y one such Slalement. writing the value of " X . re a d () I y . rea d ( ) ~' 10 F, where I exec ules an OR operalion . In SystemC, one can read the c urrent value ~f an onput pon using Ihe readO function and can wri te a va lue to an o utpul pon using lhe wn leO funcllon. Wh ole we can use other melhods of accessing lhe inpul and Outpul pons lhe readO and wrile() functi ons are recommended. ' As anDlher examp le o f a behavioral description, let's rev isil ou r Door'include • systemc. h· Opel1er exampl e fro m Fig ure 9.6(c), for ~C_HODOLE (OoorOpener) w hi ch we crealed a slruclural SystemC
i
Testbenches SC_ METHOD (comblogic) ;
sensitive «
x «
Yj
void comblogic () (
P . writ. (x. read ()
I
y. read !));
)
};
Figur.9.11 Behavioral Sy'lcmC de.'criplion of an OR gale.
One of Ihe main uses of an HDL is Ihal of si mulating a new design to ensure that th desig n is correcl. To simulate a design, we need 10 sel Ihe de ign 'S inputs to certru:: va lues, and then check lhal the design's o utput values are whal we expecl them to be. A syslem Ihm sets inpul values and checks output value IS known as a leslbellch . \ e now show how 10 create an HDL test bench to test our DoorOpeller circuit.
~56
Hardware Description Languages VHDL Figurc 9. 13 shows a VHDL leslbench for Ihc DOOl'Opeller design of Figure 9."(c). I mice that the entilY. named Tesrbellch. has no pons- the entilY is self-co ntained. req uiring no inputs and generating no out-
pUIS. The archilccillre dec lares Ihe componelll Ihat we plan 10 Icst-namely. the DoorOpeller component. The architecture instantiates one instance of the DOOIOpellercomponent. which we named DoorOpeller /. A single process in the architecture sets the inputs of the component and checks for correct output. This testbench tries all poss ible cases of the three inputs. of which there are eight cases. Many components have too many inputs to Lry all possib le cases-in that situ ation. we might try border cases (e.g .. all Os. all 1s) and then some random cases.
9.2 Combinational Logic Description Using Hardware Description Languages
457
Verilog library ieee;
use ieee. st.d_logic_1164. all; entity Testbench is end Tes tbench;
architecture behavior of Testben ch i8
component DoorOpener port ( c, h, p: in std_logic ; f: out std_logic );
end component : signal c, h, P,
f : std_logic;
begin
DoorOpenerl: DoorOpener port map (c, h, p, f 1 ; process
begin -- case c <= '0'; h <= ' 0 '; p <= '0'; wait for 1 n8 ;
assert (f=' 0') report -Ca se -- case 1 c <= '0'; h <= '0' i P wait for 1 ns ; assert (£='1') report -- (cases 2-6 omitted -- case 7 c <= '1' ; h <= . 1 '; p wa it for 1 ns ; assert (f=' 0') report
a
failed-
i
<= '1' ; ·Case 1 failed from figure)
M ;
<= '1'; "Case 7 failed
M ;
wait ; -- process does not wake up again end process ;
end behavior; Each case sets the three inputs of the component to a panicular input combinaLion. Figure 9.13 Behavioral VHDL descriplion of DoorOpeller and waits for those values to lestbench. propagate through the component-we arbitrarily wai t for I ns of simulated time, but could have picked any time, since we didn ' t actually create a time delay within the component. But we do have to wait for some Lime. as VHDL simulation is defined such that no signal is updated instantaneous ly. but rather after an infi nitely small period of simulated time. After waiting, each case checks for the correct value on the output!. using an assert statemen t. If the condition of the assen statement eva luates to lme, simulation proceeds to the next statement. But if the condition evaluate to fal se, the corresponding error me<;sage Wi ll be reponed and the simulati on will terminate.
Figure 9.14 shows a Veri log testmodule Testbench: bench for the DoorOpeller design of reg c, h. p; wire f; Figure 9.5(c). Notice that the module, named Testbellch, has no OoorOpener DoorOpenerl (c. h. p. f ) ; pon s-the module is self-contained initial requiring no inputs and generatin~ begin no outputs. The module fi rst II case 0 declares three registered signals c, c <= 0; h <= 0; P <= 0: . 1 $dioplay (" f = %b". f); h, and p and a single wire f. The II case 1 Signals c, h, and p are declared as c <= 0; h <= 0 ; p <= 1; t l $dioplay (" f = tb". f); reg because we must assign values II (cases 2-6 omitted from figure) to the signals that wi ll be connected /I case 7 to the inputs of the design we are c <= 1; h <= 1: p <= 1; 11 $dioplay (" f = tb". f); testing. However, because we do end not need to assign a value to the endmodule output we are monitoring, the Figure 9.14 Behavioral Verilog deSCription of signal ! is declared as a wire. The DoorOpener testbench. test bench then instantiates one instance of the DoorOpeller component : named DoorOpeller/ , and connects the inputs and outputs of the component t our Internal ignals. The testbench then contains an initial procedure that defines 0 block of code that will be executed onl y once when executi on of the te tbench begins~ The IIlIHal procedure sets the inputs of the DOOiDpeller component and di splays the resulting value of the component'S output. This testbench tries all po sible cases of the three Inputs. of which there are eight cases. Many component have too man Inputs to try all possible cases-in that situation, we might try border case (e.!! .. Os, all Is) and then some random cases. . Each ca e sets the three inputs of the component to a particular input combina_ lion , and waits for those values to propagate through the component-we arbitrarij wait for I unit of simulated time using the delay contTol statement "1/1". but we cOUI~ have picked any length of time, since we didn ' t actually create a time delay within the component. The Veri log language does not define standard. time unit. uch as nanoseconds. but Instead simply defines lime 111 term of lime uruts. which a de . . . . W d h can use wit. h'111 a sm1Ulallon environment. e 0 ave t 0 waH. f or some time. asIgner the ass ~g nm e nt s within the testbench are nonblockmg statements that are not Updated untll the current simulation time completes. After wUlung. 7.ach case outpUts the value of the output ! USlllg a $disp/ay statement. The statement $dlsplaY ( "f lb" flU outputs the value of! in binary. For eXal~ple. If the value of! is l. then th~ di splay . tatement will output "f = 1.... The display stalement consist of a format slnng followed by a comma-separated hst of wIres. regl ters. or pons . \ nil th L the '7cb' indicates thut the value of.u,e 111I!!nal e format . strint!_ of our display statement. . . . . speCified after the format string Will be displayed m bmaf)'. After SImulation has pleted. we can compare the values output during simulation to the expe ted \ lue omdetermine if our ircuit is working correctly. .t
at;
458
Hardwa re Description Languages
93 Sequenual Logic Description USing Hardwaro DeScription LangUBgos
SystcmC Figure 9.15 , how' "Sy'lem Ic'tbe nch for the Doo,.Opel/cr de,ign of Figure 9.6(c). I olice that Ihe module. nam ~d Tellbel/ch. h,,' three ou tpul port'>. C_I. h_l. and 1'_1. and one inpul purt JJ In Sy"cm . we de
corr"polltling outpu l port . Likewise. for every outpu t port on
II
the circuit we arc leMing. OUf tcM-
bench wi li have a corresponding in put port. The t"tbench module define"> a I\inglc proce"
nallled
~59
Ilt!\( MalClllcnt. But if the condition c\~\luntl" '" tahl' , "IHulnlmn \\111 ' lOP and the corre'ponding emIr m~"ug~ \\ III be reported In Y,lem . '"llI~' ",ch." 0 "nd I ,Ire Intc~~r ',lluc' "nd IIut logl' ' UlliC'. 1", lcild. Sy'tcmC define' thc ,,,Iuc' ·CJOGIC .O"nd . _IOGle I Ih.1t corre'I","d h'lhe logic ,alue, of 0 nnd 1. re'pcl·tI\
to the
'include ·systemc. hse_ MODULE (Test.bench) {
8C_ out < 8C_ logic > C_t. h_t. p_t;
8c_ in<8c_ logic > f_t; SC_ CTOR (Tes tbench) (
se_THREAD (testbench...,proc) ;
9.3 SEQUENTIAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES Register
void testbench-proc () (
II case 0 c_t .write ISC_LOGIC_O); h _t . write ISC_LOGIC_O); p_t . write ISC_LOGIC_O) ; wait l!. SC_NS); a •• ert ( f_t. read () =.: SC_LOGIC_O ); II case 1 c_t. write I SC_LOGIC_O) ; h_t. write (SCLOGIC_O) ; p_t. write ISC_LOGIC_l) ; wait ll. SC_NS);
le.HIJel/ch-Ilro C. Th e tes tbe nc h proce s;. is defined a, an SC_TNREAD . which is sim il ar to sssert ( f_t. read () == an SC_METHOD process excepl / I (cases 2-6 omitted from fi9\lre) that Ihe SC_THR EAD ali ows LI S to / I case 7 lise Ihe ",aitO function within Ihe c_t. write ISC_LOGIC_11 ; process body to control Ihe timi ng h_t . write I SC_LOGIC_11 ; p_t . write I SC_LOGIC_l I ; behavior of Ihe process. In contraSI. wait ll. SC_NS); SystcmC doc;. not allow us 10 usc assert ( f_t. read () == SC_LOGIC_O ); the waitO function within an SC_METHOD process. The lest) bench process controls the inputs of I; the circuit we arc testing and checks for correct output. Thi s testbench Figure 9.15 Behavioral SYSlemC description of tries all poss ibl e cases of the DoorOpe1ler tcslbench. Doo,.Opel/e,.·,. three inputs. of whi ch there arc eight cases. Many componellls have too many in puts to try all possible cases-in that situalion. we might try border cases (e.g .. ali Os. all Is) and then some random cases. Each case sets the Ih ree inputs of the Doo,.Opeller circuit to a particul ar input combination. and wai ts for lhose values to propagate through the component-we arbitraril y wai l for I ns of simu lated time , but could have picked any time, si nce we didn't aCluall y crea te a time delay within the component. But we do have to wait for some time. as SystemC si mulation is defined such thai no signal or pon is updated instantaneously. but rather after an infinitely small period of simul ated time. After waiting, each case checks for Ihe correct output by reading the portLt using an assen statement. If the condition of the assert state ment eva luates to true, simul ation proceeds
The mo;.t bo" componenl basic regi,ter 111 IIDL, .
111
I-IDL Figure 9.16 ,ho\\, " ba\lc 4-bit register m I IDL. The register is identical In that dC\cribed In Figure 3.30. The entll}
equentlal Inglc I' a rc!,!"la. We no\\ , 11,,\\ h'"
Hbrary i .
I
u..
_lovlc 11f.4.all,
10
llIodel II
entity R V4 1.
P
I I
rt
in d loQle velar I J downto 01: . out td lOQlc v clot () CSownto 0): lk in ld 1000Ie
);
en4 Pf!lg4: architeoture
"'hl)v~or
of Rf"U4 1.
begin proc ••• tcUc:)
begin it (elk '1' and clk' ev. ne ) t hen
o
< 1: _"" U ; • .04 proc •• I :
• .04 behevior:
Figure 9.16 BchavlO,"1VIIDL UC"'"P""" 0[" 4-bn rcgl"cr. clemen IS. For example. Ihe 0)" dehne, a 4·bil vector of type dec laration "s td 1ogi e vee or (3 down SId_logic clement. where the bit po~i ti on s within the vector arc numbered from 3 to O. The dowllto statement defines the ordering of the elemenl s within the vector. indicati ng that element 3 is located in Ihe leftmo,t po\it ion. The ,wtcment "I <- . 1000 ·" would thus assign the value '1' to position 3 of the veclor I (lnd the value '0' to the remaini ng three posi li ons. When assigning a value to a .f ld_logic"ector. the vector'b value I1lU ~t . be specified within double quotalions. For example, the deCimal value 5 would be specified as a 4-bit sl(U ogicveclOr as "0101". . . ' . The architecture describe the register behavlonllly, u, ms a proce,s Matement. rhe process is sensitive to its elk input only-because the proce~, should only update i t~ output during a rising clock edge. the process need not execute If mput I changes. If elk change. th ocess begins executing its statements. The first statement checks If the process began ex::~ting due to a rising clock edge (0 to 1), as opposed to a fallin g ~Iock edge (1 to 0). The statement checks for a ri ing edge by cheekmg If the elk mput Just changed
°
.-.~~.---.
-'60
Hardware Description Languages
9.3 Sequential Logic Description Using Hardware Description Languages
(c 1 k ' e V en t) and that change was 10 a 1 (c 1 k= ' 1 ' ). If the process began executing due
value must be specified wi thin double quotations. For example, the decimal value 5 would be specified as a 4-bit sc_lv as "0101". Notice that in defining the input port for I , we included a space between the two closing angle brackets, >, the space being required in SyslemC. The module consists of a single process, named seq_logic, that is sensitive to the positive edge of the elk input. specified using the sellsilive..JJos statement fo r defining the sensiti vity li st- because the module should only update its output duri ng a rising clock edge, the seq_logic process need not wake up if I changes. On the positi ve edge of the clock. the register updates the regi ter's coments using the statement ·'O . write(l.read(»". In Systemc. output ports are a type of signal, and signals have memory. Thus, assigning I to Q causes Q to retain the new value, even when the process is done executing, thus implementing the storage part of the register.
a rising clock edge. then the process updates the reg ister's contems using the statement " 0 (= I ". For a fa lling clock edge. the process will begin executing, check the i{statement condition. and then reach the end of the process and hence stop executing, without updating Q. Ideally. YHDL wou ld have a way to beg in executing a process only on a rising clock edge. but YHDL has no such feature. In VHDL. output ports are a type of signa l. and signalS have memory in simulation. Thus. ass ign ing I to Q causes Q to retain the new value. even when the process stops executing, thus implement ing the storage part of the reg ister.
10
Yerilog Figure 9. 17 hows a basic 4-bi t register in Verilog. The module Reg4 (I. Q, elk); register is identical to that described in Figure 3.30. The input [3, OJ I; input elk; module defines the data input I and the data output Q , output [3 , OJ Q ; as weli as the clock input elk. The input I and output Q rell [3,OJ Q; of this design correspond to a 4-bit value. Instead of always @ (poaedge elk) using eight individual inputs and outputs, the module's begin I and Q ports are defined as veClOrs. For example. the Q <= I; type declaration " i npu t [3 : 01 f" defines a 4-bit end endmod.ule input vector where the bit positions wi thin the vector are numbered from 3 to O. The [3:0] defines the ordering of the elements within the vector, indicat ing Figure 9,17 Behavioral Veri log that element 3 is located in the leftmost positi on, The descri ption of a 4-bit register. statement "I <=4' blOOD" would thus ass ign the value 1 10 po ition 3 of the vector I and the value 0 10 the remai ning three positions, When assigning a value to vector. we must specify the number of bi ts wi thin the value we are as igning, the base in which we are specifying the value, and the value itself. For example, the decimal value 5 would be specified as 4-bit binary value 4 'bO IOI, The module describes the register behaviorally, using an always procedure, The procedure block i sensi tive to the positive edge of the elk input , specified using the posedge keyword-because the modu le shou ld only update its output during a ri sing clock edge, the always procedure need not execute if I changes, On the pos itive edge of the clock, the procedure update the register's contents using the statement "0 <= I ", Because we defined the output Q as a reg, ass igning I to Q causes Q to retain the new value, even when the procedure is done executing. thus implementing the storage part of the register, SyslemC Figure 9, 18 shows a basic 4-bit register in Systemc. The register is identical to that described in Figure 3.30. The module defi nes the data input I and the data output Q, as well as the clock input elk. The input I and output Q of this design correspond to a 4-bit value. Instead of using eight individual sc_logic inputs and outputs, the module's I and Q ports are defined as sc)v logic vector. An .fc_fl· is a vector of multiple se_logic elements. For example, the type declaration "5c_l v<4)" defines a 4-bit vector ofsc_logic elements where the bit positions within the vector are numbered from 3 to O. In Systemc. the orderi ng of the elements within the vector is defined such that the leftmost position i the most sign ificant bit. For example, the statement "I <= " 1000 "" wou ld thus aSl>ign the value 1 to position 3 of the vector I and the value D to the remaining three positions. When assigning a value to an sc_lv. the vector's
461
.include ·systemc.h-
SCJ
8c_ in<8c_ lv<4:> > I; 8c_ out <8c_ lv<4> :> 0; 8c_ in <8c_ logic> elk;
SC_ METHOD (seQ....-logic) ;
aenaitive-P08 «
elk;
void seCLlogic () (
Q. write (I. r ead ()
;
I I;
Figure 9.18 Behavioral SystemC descriplion of a 4-bit register.
Oscillator YHDL The register presented in Figure 9.16 has a clock inpu!. We thus need to define an oscillator component that generates a clock signal . Figure 9. 19 illustrates an oscillator de cribed in YHDL. The entity defin es one output , elk. The architecture consists of a process. but notice that process does not have a sensitivity lis!. By default . such a proce executes irs tatements as if they were enclosed in an infinite loop. So the process sets the clock 10 O. leeps until iO ns of si mulated time passes. sets the clock to 1. sleep another 10 ns of simulated time, goes back 10 the first statement in the process that ets the clock to O. and so on. The output waveform for such an 0 cilialOr will be identical to the waveform shown in Figure 3.17. library ieee; The wait/or statement in YHDL tell the us. ieee. std....logic_1l64 .all; simulator the amount of simulated time that entity Osc i. the proce s should not execute. A proce s port ( elk: out stCLlogic ); end Osc; w i lho l/I a sensitivity list IIIlISI have at least one wait statement. otherwise the simulator will architecture behavior of Ose i . never fini sh simulating that process (because begin proceS8 the process is in an implicit infi nite loop). and begin thus the simu lator will never get a chance to clk<='O'; update outputs or to simulate other proces es. wait for 10 n.a ; elk <= '1'; On the other hand. a process lI'ilh a sensitivity wait for 10 n.a ; li st call/IOI include wait statements. because end proce8. ; by defi nition. the sensitivity list defi nes when end behavior; the process should execute. Figure 9.19 HDL oscillator description.
462
Hardware Description Languages
9.3 Sequential Logic Description Using Hardware Description Languages
Verilog
The register prescntcd in Figure 9. 17 has a cl ock input. Wc thus need to define an osc illator component that gcnerates a clock signal. Figure 9.20 illustrates an oscillator desc ribed in Verilog. The module defines one output. elk. The modu le consists of an olll"Q."s procedure. but notice that the always procedure does not have a scnsitivity list. By defau lt. such a procedure executes its statements as if they were enclosed in an infinite loop. As suming we arc using a time scale of nanoseconds, the always procedure sets the clock to O. delays for 10 ns of simu lated timc. scts the
modu1e Osc (e lk) ; output elk ; re~ elk ;
463
simulator will never fi1I11' Sh Simu lating that process (becau se the process tS ' III . an infinite I oop), and thus the simulator cannot update outputS or simul ate other processes .
Controllers
a lways
begin elk <= 0;
81 0; elk <= 1 ;
#1 0; end endmodu l e
clock to 1. delays for anot her 10 ns of simulated time, goes back to the first statement in the procedure that sets the clock to 0. and Figure 9.20 Veri log so on. The output wavefonn for such an osc ill ator will bc iden- osc illator description . tica l to the waveform shown in Fi gure 3. 17. The delay control statement. specified with the # character. tell s the simulator the amount of simulated time that the procedure should not execute. A procedure lVilhol/l a sensitiviry list 1111151 have at least one delay cOnLrol statement, othcrwise the simulator wi ll never fini sh simulating that procedure (because the procedure is in an implicit infinite loop), and thus the simulator will never get the chance to update outputs or to simulate other procedures. On the other hand . a procedure lVilh a sensitivity li st COIIIIOI include delay control statements, because by definition the sensitivity list defines when the procedurc should awake. SystemC #include "s ystemc h" The reg ister presented in Figure 9. 18 has a clock SC_ MODULE (Osc) input. We thus need to define an oscillator com( ponent that generates a clock signal. Figure 9.2 1 illustrates an oscillator described in Systemc. The module defines one output. elk. The module consist of a single process, named seq_logic. SC_THREAD (se~ logic) ; implemented as an SC_THREAD . By default. an SC_THR EAD prace s is only executed once. In v oid seCLlogic () order to ensure the process executes continu( ously, we enclose the statements within the while (truel { elk . write (SC_LOG IC_OI; proce s in an infinite loop. implemented using wait (10, SC_NSI ; the tatement "\01 h i 1e ( t rue )". Thus, the loop elk. write (SC_LOGIC_ll ; wait (10, SC_NS I; will execute the statement included withi n the braces forever. During exec ution , the process sets ) the clack to 0, suspends execution for 10 ns of ) ; simul ated time, sets the clock to 1. sleeps another Figure 9.21 SystemC oscillator 10 ns of simulated time, l>ets the clock to 0, and description. so on. The output waveform for such an osci llator will be identical to the waveform in Figure 3. 17. The wail() functi on in SystemC tells the simulator the amount of simulated time that the process :,hould not execute. For exa mple. the statement "wa i t ( 10 . SC_ NS); " will su pend the execution of the process for 10 nl>. An SC_TfIREAD process explicitly implementing an infinite loop IIIU.51 havc at least onc wa it sWtCl11cnt . otherwise the
Recall that a common type of sequential circuit is a controller which implements a finite-stat~ machine. The controller consists of a state register and combi national logic. VHDL
Figure 9.22 shows one way to model a controller in VHDL. The controller modeled is described by the FSM shown in Figures 3.38 and 3.39. The VHDL en tity, named LaserTIlller , defines the controller'S inputs and outputs. The VHDL architecture describes the behav ior of the entity. The archi tecture consists of two processes, one modeling the state register, the other modeling the combinational logic, that form the standard controller archi tecture from Figure 3.47. The first process descri bes the controller's state register. That process, named stafereg. is sen ilive to inputs elk and rsl. If the rsl input is enabled, then the process asynchronously sets the Cllrrell/s/{/Ie signal to the FSM 's initial state, S_Ojf. Otherwise, if the clock is rising, the process updates the state register with the next tate. Figure 9.22 Behavioral VHDL
library ieee; use ieee. st~logic_1164 .all entity LaserTime r is port (b : in stCLlogic; x: out std_logic;
elk. rs t: in std logic I; end LaserTimer; arc hitecture behavior of LaserTimer i . type statetype is (S_O ff, S_Onl, S_On2, S_On3);
signal currentstate. nextstate: statetype; begin
statereg: proceaa (clk, rst) begin
if (rst= '1') then -- int.ial state currents tate <= 5 Off· e1aif (clk= ' !' and clk' e';'8Jlt ) then endc~~ ~entstate <= nextstate; end process ; cornblogic : procesa (currents tate , begin
bl
case currents tate ia when 5_0f f => x <= '0'; -- laser off i f (b='O' I th"n nextstate elae
nextst.ate end if ;
x <= '1'; -- laser on nextstate <= 5_On2; when 5_002 =>
~e::s~!~~ when 5_0n3 => x <= '1';
nextstate
::
;~~~; still
on
laser st.ill On S_Off;
end case ; end process ; end behavior;
desc ripli on of the LLrser7imer controller.
The c"rrell/stale and lIexlstale signals are defined as a u s~r-defi ned type. named The statetype is defined by the type. statement and speCIfies the po ible values a signal of that type can represent. In SpeCtfYlllg slatelype . whIch repre ents the tates of an F M, the Iype declaration consists of the names of all the states in Our controller s . pecifically S_Ojf. S_OIlI. S_01l2. and S_O/l3. slatelype.
464
Hardware Description Languages
9.3 Sequential Logic Description Using Ha rdware Description Languages
The second process describes the cont roller's combinational logic. That process, named cOlI/btog ic. is sensitive to the input s to the comblllatJOnal logtc of FI gu re 3.47, namely. the external inputs (in Lhis case. b). and the state regts~e r outputs (curreIlISIGle). When either of Lhose items change. the process sets the FSM s outputs, In thts case x, with the appropri ate value for the current state. The process al so detenlllnes what the next state should be, based on the current state and the va lues of lllpu tS (Le .. the condllJOns on Lhe FSM transitions) . The next state will be loaded into the state regtster by the state register process on the next ri sing clock edge.
Notice that the architectu re declares two signals, CUrre/llSlOle and lIeXISlate. Signals are visible across all processes in an architecture.
The
CUrreJ1fstate
signa l
represents the actual storage of the Slale register. The ll exfs(Q te signal represents the value coming from the combinationa l logic and going
to the state register. Notice also that the architecture declares those signals as rype slOl eryp e. defined in the architecture as a rype whose value can be eiLher S_OiJ. S_OIlI. S_On2. or S_01l 3. Verilog Figure 9.23 shows one way to model a controller in Veri log. The controller modeled is described by the FSM shown in Figures 3.38 and 3.39. The Veri log module, named LaserJimer. defines the controll er's inputs and outputs. The module consist of two procedu res, one modeling the state regi ster. the other modeling the combinational logic, that togeLher form the tandard controller archi tecture from Figure 3.47. The state register procedure is sensitive to the po itive edge of Lhe rSI input and the positive edge of the elk input. The sLaLe regi ter has an asynchronous reset signal and in order to model the asynchronous reset. the staLe register procedure must be se n~iLi ve to the positive
module LaserTimer {b, x, elk. rst); input b. elk, rst; output x;
reg x; parameter 5_0ff 5_0nl 5_0n2 5_0n3
2 'bOO. 2 'bO l, 2 ' blO, 2 ' bll ;
reg [1 : 0] currentstate; reg [1: 0] nextstate; / / state register procedure always @ (posedge rst or posedge begin if (rst==!) / I initial state 5_0ff ; currents tate else curre n ts tate nextstate i end II combinational logic procedure always @ (currents tate or b) begin case (currents tate) S Off : begin -x <= 0; II laser o ff if (b==OI nextstate else nextstate end S On1 : begin -x < = 1; / I laser on nextstate <= 5_0n2; end S On2: begin -x <= 1; II laser st ill on nextstate <= 5_0n3; end S On3: begin -x <= 1 ; /1 laser still on
nextstate
elkl
S_Off;
end endcaee end enc1module
Figure 9.23 Behaviora l Vcrilog description of the Loser7imer controller.
465
edge of the rSI input. On the positive edge of the rSI input , the procedure wiII wake asynchro nously and sets the currelllSIGle signal to the FSM 's initi al state, S_OiJ. On the ri sing edge of the clock input, elk, if the reset input is not enabled, the procedure updates the state register with the lIeXISlme value determined by the combinational logic procedure. In Verilog, we must explicitly specify the size of the state registers as well as define the values associated with each state within the FSM . With in the LaserTimer module we declare four parameter values, namel y, 5_0ff, 5_0111 . S_01l2. and S_ 01l3. whi ch specify 2' bOO" the values assigned to each state within the FSM . For example. "5_ 0 f f defines the state name S_Off and assigns the 2-bit value "00" to this state. We can then refer to thi s state th ro ughout the modul e using S_Off instead of using spec ifi c bit val ues. Whi le not required to define a state machine, using para meters increases the readability of our design and makes revisions to the FSM much easier. As the LlIserTill/ er s FSM has four states, we need a 2-bit state register. and we therefore declare the currelllSlale and lIexlstale signals as 2-bit registers. The second procedure is the combinational procedure implementing the control logic of the FSM. That procedure is sensitive to the inputs to the combinational logic of Figure 3.47, namely, the external inputs (i n this case. b). and the state regi ster OutpulS (cllrrelllSlate). When either of those items change, the procedure sets the FSM 's out pulS. in this case x, with the appropriate value for the current state. The procedure also determines what the next state should be, based on the current state and the values of inpulS (i.e .. the conditions on the FSM transitions). The next state wi ll be loaded into the state register by the tate register procedure on the next positi ve clock edge. Notice that the modu le declares two signals, CllrrelllStale and lIeXISlale. Signals are visible across all procedures in a module. The c"rrelllstale signal represenlS the actual storage of the state register. The /l exlstale signal represents the value com ing from the combinaLional logic and going to the state register. SystemC Figure 9.24 shows one way to model a controller in Systemc. The Controller modeled is described by the FSM shown in Figure 3.38 and Ftgure 3.39. The module. named LaserJimer. defines the controller's inputs and outputs. The module consists of two processes. one modeling the SLate regi ster named sralereg, the other process modeling the combinational l og~ named comblogic. that too ether form the standard controller architecture from Ftgure ~.47 . o The state register process is sensiLive to the positive edge of the rSI input and the po _ iLive edge of the elk input. The state register has an asy~chronous reset signal. In order to model the asynchronous reset. the state regtster process IS senSlllve to the po itive edge of the rSI input. On the positi ve edge of the r~1 Input. the process wtll wake ~synchronously and sets the Cllrrell/sta le signal to the FSM s mlllal state. S_OiJ. On the nSIng edge of the clock input, elk, if the reset input is not enabled. the process updates the state regi ster wi th the /l eXISlllle value determined by the combmallonal logtc proce 's. The cllrrelllstale and lIeXlslate signals are defined as a u:er-defined type, na me
~-~
----~
-'66
Hardware Description Languages
9.4 Datapath Component Description Using Hardware Description Lang uag es
The second process. named cOll1blogic. is se nsitive to the inputs to the combinational logic of Figure 3.-'7. name ly. the externa l
inpu ts.
and
the
state regi ster ou tputs. When
either of those items change. the process sets the FSM 's out puts. in this case x. with the appropriate value for the cun'ent state. The process also determines what the next state shou ld be. based on the current state and the val ues of inputs (i.e" the condition s on the FS M transitions). The next state will be loaded into the state register by the state regi ster process on the next rising
clock edge. With in the fi rst state. we determi ne the next state depending on the value of input b by performing the compari son " b . read() SC LOG I C_O ". Note that the compar iso n for equality uses
the
syntax
"== "
467
~ 9.4 DATAPATH COMPONENT DESCRIPTION
.include "systemc.h"
USI NG HARDWARE DESCRIPTION LANGUAGES Full-Adders
SC_ MODULE (LaserTimer) {
sc_ in b, elk. rst; Bc_ out x; sc_ signal currents tate . nextstate;
Recall that a full-adder is a combinational ci rcuit that adds three bits (a, b. and ci) and generates a Sum (5) and a carry-out (co) bit. Th is secti on shows how to describe a fu lladder behav iorally in an HDL.
SC_ CTOR (LaserTimer)
VHDL Figure 9.25 shows a I'u lllibrary ieee; adder described behavuse ieee.stcLlogic_1164 . all; iorall y in VHDL. The entity FullAdder is full- adder design correport ( a, b, ci: in std_logic; sponds to the full -adder s, co: out std_logic ); described in Figure 4.3 1. end FullAdder: The VHDL entity, named Fill/Adder, defin es the arc bitecture behavior of FullAdder i . begin full -adder's three inpllls process (a, h, eil a. b, and ci and two beg in outputs s and co. 5 < = a xor b xor ci; co <= (b and cil or (a and cil or (a and bl; The architecture end process ; describes the behavior of end behavior; the full -adder. The architecture consists of a Figure 9.25 Behavioral VHDL descri ption of a fu ll-adder. single process describing the combinational behavior of the full -adder. TIle process is sensitive to all three inputs (a. b, and ci ) of ule full-adder. When any of the inputs change. the process executes its two statements updating the values for the sum (s) and carry-out (co).
{
SC_ METHOD (statereg) ; sensitive-pos « rst « elk; SC_ METHOD (comblogie) ; sensitive « currents tate « b;
void statereg () { if ( rst. r ead () currentstate else eurrentstate
SC_LOGIC_l) S_Off; I I initial state nextstate;
void comblogic ( ) switch (eurrentstate) case S_Off: x. write (SC_LOGIC_O); II laser i f ( b .read () == SC_LOGIC_O nextstate S_Off; else nextstate = S_Onl; break ; case S_Onl: x . write (SC_LOGIC_l); I I laser nextstate S_On2; break ; case S_On2: x . write (SC_LOGIC_l); I I laser nextstate S_On3; break ; case S_On3: x. write (SC_LOGIC_Il; II laser nextstate = S_Off; break ;
off
on
st ill o n
stil l o n
Instead. if we accidentall y used the syntax " =", which is a valid statement. our ) design wo uld function ); incorrectly. Notice that the modu le Figure 9.24 Behavioral SystemC description of the Ltlser7imer conlroller. declare~ two sc-""igl/a/s. currentSlale and nex/sltl te. Signals are visible acros~ all proce, 5es in a module. The currell istale signal represents the actu al storage of the state register. The lIeXl.\IlIIe signa l represents the va lue coming from the combinational logic and goi ng to the state register. Notice also th at the arch itectu re declares those signals as a type ,f/alelype. defined in the architecture as a type who,e va lue can be either S_OjJ. .5_0"1 . S_01/2 . or S_01l3.
Verilog Figure 9.26 haws a fu ll-adder module F-ullAdder (a. b, ci, 5, co); described behaviorally in Veri log. input a, b, cit output s, co; The fUll- adder design corresponds reg 5, co; to the full -adder descri bed in always @ (a or b or eil Figure 4.3 1. The Veri log module, begin named FIIIlA dde r, defines the full 5 <= a b ci; adder's three inputs a, /l. and ci and co <= (b & cit I (a & ei) I (a & b); elld two outputs s and co. endmodule The modu le describes ule behavior of the fu ll -adder and Figure 9.26 Behavioml Vcrilog description of a consists of a single always proce- fu ll-odder. dure descri bing the combinational behavior of the full -adder. The procedure is sensi ti ve to all three inputs (0. b. or ci) of the fu ll-adder. When any of the input Change, the procedure execute its two statements updating the value for the sum (s) and carry-out (co). A
A
.~--.
468
Hardware Description Languages
9.4 Data path Component Description Using Hardware Description Languages ~ 469
SystemC Figure 9.27 shows a full-adder de~cribed behaviora ll y in Systeme. The fu ll -adder design corresponds to the full-adder described in Figure 4.3 1. The SystemC module. named FIll/ Adder. defines the full-adder s three inputs C/, b. anel ci and two outputs s and co. The module describe the behavior of the full -adder and consists of a single process. named combiogic. describ ing the combinational behavior of the fu ll -adder. The process is sensitive to all three inputs (a, b. or ci ) of the full -adder. When
#inc1ude
"systemc.h~
SC_MODULE (FullAdder) {
Be in a, b. ci; sc= out s. co:
SC_ CTOR (FullAdder) ( SC METBOD {comblogic); se~8itive « a « b «
ci;
void comblogic () 5
,write(a. r ead ()
"" b. read () " ci. read (»;
co .write ( (b. read () & ci. read {)I (a . read { 1 & ci. read (1I (a .read () & b. read ( III;
I I
)
);
Figure 9.27 Behavioral SystcmC description of a full-adder.
s m (s) and ca -out (co) any of the inputs change. the process execu tes its two statements updating the values for the u rry .
Carry-Ripple Adders We now show how to structurally describe a 4-bit carry- ripple adder using the full-adder we designed in the previous section. VHDL
Figure 9.28 is a VHDL descri ption of a 4-bit carryripple adder with a carry- in, as appeared in Figure 4.33. The VHDL emity, named CarryRippieAdde r4 , has two 4-bit in puts, C/ and b, and a carry-in input. ci. The carry-rippl e adder outputs a 4-bi t su m, s, and a final carry-out co. The architecture structurall y describes the carryripple adder composed of four full-adders. The archi tecture begins by declaring the component Ful/Adder,
library ieee ; use ieee. std_logic_l164. all ; entity CarryRippleAdder4. ia port (a: in std_log~c_vector( 3 downto 0); b: in std_logic_vector(3 downto 01; ci : in std_logic; s: out std_logic_vector (3 downto 01; co: out std_logic
end '~arryRiPPleAdder4; archite cture structure of CarryRippleAdder4 i. component FullAdder port ( a, b, ci : in std_logic; s, co: out std_logic
I; end component ; signal col, co2, co3 : std_logic ; begin FullAdderl: FullAdder port map (a 101. b(OI. ci, 5 (01. col) ; Fu llAdder2 : FullAdder port map (a (11. b(ll, col, 5 {ll, c021; FullAdder3 : FullAdder port map {a{21. b(21. co2, 5 (21. c031; FullAdder4: FullAdder port map {a {31. b{31. eo3, 501. col; end structure ;
Figure 9.28 Structural VHDL descript ion of a 4-bit carryripple adder.
which was described in the previous section. TIle design has three internal signal, co l. co2. and c03, that are used for internal connection between the full-adders. The architecture then instantiates four Fill/Adder components. In VHDL. each instantiated component must have a unique name. The four Fill/Adder components in this design are uniquely-identified by the names FIII/Adderi. FIII/Adder2, FIII/Adder3. and FIII/Adder4. In VHDL. the std_logic_vector type provides a convenient method of specifying pons or signals consisting of multiple bits. However. a design may need to access the individual bi ts of these vectors. The individual bits of a s{(Clogic_vector ca n be accessed by specifying the desired bit position with in parentheses after the vector's name. For example, to access bit 0 of the 4-bi t input {( of thi s design. one would use the syntax "a (0 )". In defining the connections to the instanti ated components in the carry-ripple adder. indi vidual bits of the inputs a and b and output s are 'lccessed using this yntax. The first full-adder, FIII/Adderi. connects bit 0 of the inputs a and b as well as the carryripple adder' carry- in , ci, to the full-adder's three inputs. The s output of FlIllAdderl is connected to bit 0 of the 4-bit adder's sum output. s. represemed as s(O) . The design then connects the carry-out bit of FIII/Adderl to the internal signal co l , whi ch is ubsequently connected to the carry-in input of the next full -adder. FIII/Adder 2. The component COnnections of the remaining three full-add ers are connected in a imilar faShion. with the exception of the last full-adder in the carry-ripple chain. The carry-out from that last full adder. FIII/Adder4 , is connected to the carry-out output (co) of the carry-ripple adder. Verilog Figure 9.29 is a Veri log description of a 4-bit carry-ripple adder with a carry-in, as appeared in Figure 4.33. The Veri log module, named CarryRippieAdder4 , has two 4-bit inputs. a and b, and a carry-in input. ci. The carryripple adder outputs a 4-bit sum, s, and a final carry-out co. The module structurally describes the carry-ripple adder composed of four full-adders . The design has three internal
module CarryRippleAdder4 (a. b, ci, s, CO); input (3:0) a; input (3:0) b; input ci; output (3 :01 .: output co;
wire col, co2, co): FullAdder pullAdderl{aIO).
bioI , cit
s(O) • col) ; FullAdder FullAdder2 (a (1)' bill •
5(1) • co2) ;
COl.
FullAdder FullAdder3 {a (21 • b(2) • Co2, 5(2) • c031; FullAdder FullAdder4 (a(3), b(3) . co3, • (3!. co) :
._ule
wires, co l , co2, and c03, that are Figure 9.29 Structural Verilog descriplion of a 4-bit carry_ used for inlernal connection ripple adder. between the fu ll-adders. The " . module instantiates four Fill/Adder components. In Venlog. each IIlstanttated component . must have a ul1lque name. The four Fill/Adder components III thI S deSIgn are uniquely_ 'fi ed by th e names FIIIIAdderl , FIIIIAdder2. FIII/Adder3.. fand . Identl . FIII/Adder4.. In Veri log. vectors provide a convenient method of SpeCI Ylll~ ports or SIgna] coosisting of multiple bits. HOlVever. a design may need to a~ce:s the l~tvldUa] blls ~f these vectors The individual bits of a vector can be acce se y SpeCI ymg .the de Ired bit .. ' 'th ' brackets after the vector's name. For example. to access bit 0 of the 4-bit position . IIIdestgn, . a ofWttillS one wou Id use the syntax "a [0 J". In defi ning the connection to the input
470
9.4 Datapath Component Description Using Hardware Descri ption Languages • 471
Hardware Description Languages
The module structurall y describes the carry-ripple adder composed o f four full -adders. The desIgn has three internal signals, co l , co2, and c03. that are used for interna l connectIon between the full -adders. The module first instantiates four Fill/Adder components. In SystemC, each instantiated component must have a unique name. The four FlIllAdder components in this design are uniquely identified by the names Fill/Adder_I . FlIllAdder 2 FIII/Adder_3 , and FIiI/Adder_4. - . Prev iously, we de fin ed multiple-bit inputs as an input vec tor using the sc_lv ty pe. However, SystemC does not support connecting individ ual bits within a s igna l o r POri of type sc_l v 10 a struc tural description . In our Can)'RippleAdder4 design. we instead defined the inputs and outputs, (I, b. and s, as arrays of sc_l ogic wi th four e leme nts each, rather than using type sc_lv. The indi vidu al bits of the array ca n be accessed by specifying the desired bit positi on wit hin brackets after the array's name . For examp le, to access bit of the 4-element input array a of thi s design, o ne wo uld USe the sy ntax " a[O ]". In defining the connec tions to the in sta nt iated components in the carry-rippl e adder, indi vidual bits of the inputs a and b and o utput s are accessed us ing thi s sy ntax. The first fu ll-adder, Fill/Adder _1, connects bit o f the inputs a and b as well as the carry-rippl e adders carry- in . ci, to the full- adders three inputs. The s o utput of Fill/Adder _ I is connected to bit 0 of the 4-b it adders sum ou tput . s. represented as s{O). The design then connects the carry-out bit of FlIllAdder _ 1 to the internal signa l co l that is subseq uentl y con nected to the carry-i n input of the ne x t full-adder, Fill/Adder_2 . The compone nt connections of the re maining three fulladders are connec ted in a simil ar fas hi on, with the excepti o n o f the last full-adder in the carry- ripple chai n. The carry-o ut from the last full-adder. Fill/Adder _4. is COnnected to the carry-o ut output (co) of the carry-ripp le adder.
instantiated componcl1ls in the carry-ripp le adder, indi vid ual bits o f the inputs a and b and ou tput s are accessed using this symax. The first full -adder. Fill/Adder I , connects bit 0 of the inputs (1 and b as well as the carry-ripple adder's carry- in. ci. to the full -adder's three inputs. The s outpul of FIII/Adderl is connected to bi l 0 of the 4-bit adde r's sum output, s, represented as s{O). The desig n then connects the carry-o ul bi t of FIII/Adderl to the internal signa l co l. which is subseq ue ml y connectcd to the carry- in input of the next full-adder, FIII/Adder2. The component con nections of the remaining three full-adders are connecled in a simil ar fas hi on. with the excepti on of the las t fu ll -adder in the carry-ripple chain . The carry-out fro lll Ihe last full -adder. F"IIAdder4. is connected 10 the carry-out output (co) of the carry- ripp le adder. System C Figure 9.30 is a Syste mC desc ription of a 4-bit GUTy- ri pple adder wil h a carry-in, as appeared in Figure 4.33 . The Sys temC mod ule, named CarryRippleAdder4, has two 4-bit inputs. a and b. and a carry-i n inpu t. ci. The carry-ripple adder o utputs a 4-bi l sum , s, and a final carry-out co.
a
a
#inc1ude ·systemc.h#include • fulladder. hSC_ MODULE (CarryRippleAdder4) (
sc_ in a[4]; sc_ in< sc_ logic > b [4] ;
sc_ in ci; sc_ out 5 [4) ; Bc_out CO;
FullAdder FullAdder FullAdder FullAdder
FullAdder_l: FullAdder_2; FullAdder_3 ; FullAdder_4;
SC CTOR (CarryRipple4) :
FullAddecl I "FullAdder_I") , FullAdder_2(MFullAdder_2-), FullAdder_31"FullAdder_3"), FullAdder_4 I " FullAdder_4" ) FullAdder_l.alaIO]): FullAdder_l.bl bIOI): FullAdder_l.ci(ci): FullAdder_l.s(s[O] ); FullAdder_l . co(col) ; FullAdder_2 . a (a II] ): FullAdder_2. blbll]): FullAdder_2 . ci Icol); FullAdder_2 . sis II] ); FullAdder_2 .co(co2); FullAdder_3.a la (21); FullAdder_3 . blb(21); FullAdder_3.cilco2): FullAdder_3.sls12]): FullAdder_3. co (co) ;
Figure 9.30 Siructural SY' teme de;cri ption of a 4-bi l carry"pple adder
FullAdder_4 . ala(31); FullAdder_4 . blbI3 1); FullAdder_4.cilco3); FullAdder_4.sls13]); FullAdder_4. co (co) ; )
);
Up-Counter
VHDL Figure 9.31 is a VHDL de cription of a 4-bit up-counter, a appeared in Figure 4.48. The VHDL entity, name UpColllller, defines the counter's inputs and outputs. consisting of a clock input elk, a counl enable control input CIII, the 4-bit count value C. and a terminal count OUlput tc. The UpCOIlllter's architec tu re slructurally describes the de ign consisting of three compone nts, namely Reg4, IlIc4. and AND4. Reg4 is a 4-bi t parallel load register with a load contro l inpul Id. IIIc4 is a 4-bit incrementer. AND4 is a fo ur- input AND gate u:at will output 1 if and onl y if all four inputs are I. The archi tectures furthe~ speCifies two signal . tempC and incC, used as internal wires within the structural deSCription .
• -In
9 Hardware Description Languages
9.4 Datapath Component Description Using Ha rdware Description Languages library ieee; use ieee. std_logic_1164 . all ; entity upCounter is port ( elk: in stcLlogic; cnt: in sed-logic; C : out stc;Llogic_vector (3 downto 0); tc: out stcLlogic );
end UpCounter;
architecture structure of upCounter ia component Reg4 port ( I : in stcLlogic_vector(3 dowuto 0); Q: out std_logic_vector() dcrwnto 0); elk, Id : in stcLlogic );
end component ; conwonent Inc4
port ( a: in std_Iogie_vector(3 downto 0); s : out st~logic_vector (3 downto 0) );
end cOl!lPOnent ; component AN04 port ( w,x,y,z : in std_logic : F : out std_logic );
end component : signal tempC: std_logic_vector(3 downto 0); signal incC : std.....logic_vector (3 downto 0): begin Reg4_1: Reg4 port map {incC, tempC. clk, ent); Inc4_1: Inc4 port map ( tempC, ineC); AND4_1 , AN04 port map ( t empC(3) , tempC(21. tempC(l). tempC(O) . tc);
Figure 9.31 Structural VHDL description of 4-bit up-
outputC : process (tempC) begin C <= tempC; end process ; end structure:
counter.
The architectu re i nsta ntiates each of the three components and spec ifies the connections between them. Reg4 is the only seq uenti al component w ithin the up-counter and thu s the elk i nput on ly needs to be connected to the clock input of the register. We co ntrol the up-counter 's counting by connecting the count enable input, CIII, to the load enable. Id, of the regi ster. The output Q of Reg4 _ I is co nnected to the internal signal tempC, whic h connects the register 's output to both the IlIc4_1 and AND4_1 components. In c4_1 receives the current count from the tempC connection and ou tputs the incremented cou nt on its ou tput s, which is connected to the other internal signal illcC. The illcC signal connects the incremented count fro m IlIc4_1 to the parallel load input I of Reg4_ 1. The curren t count is al 0 co nnected to the four inputs of the AND4_ 1 com ponent. The AND4_l' s ou tput F is then connec ted to the counter's termina l cou nt output IC.
473
. In the UpColllller design. we need to connect the output of the 4-bit regi ster to the Incrementer. the A D gate. and the cou nter' s output port C. VHDL does nOt allow us to connect multiple signals or ports withi n the port map of an instanti ated component. Therefore. the architecture uses the tempC signal to connect Reg4 _ I's output to both the AND4_1 and Il/ c4_1 components. We still need to con nect the register's Output to the output pan c.. The architecture makes thi s connection by specifyi ng a proces , named OItlPll tC. that IS used to connect the output of the regi ter to the output pon C. The OWPlItC process is sensiti ve to the signal tempc. previous ly used as an internal wire between the three components. Whenever tempC changes, wh ich corresponds to a chanae in the up-counter'S stored count, the OlltPlItC process assign s the new count to the outP~t port C. Vcrilog Figure 9.32 is a Veri log descripti on of a 4-bit up-counter, as appeared in Figure 4.48. The Veri log module, named UpColllller. defines the counter's input and ou tputs. consisting of a clock input elk, a count enable control input CIII . the 4-bit count value C, and a terminal count output tc. The UpCollnter 's module structurall y describes the design consisting of three components, namely Reg4, II/c4, and AND4. Reg4 is a 4-bi t para llel load register with a load control input Id. II/c4 is a 4-bit incrementer. AND4 is a fourinput AND gate that wi ll output 1 if and only if all four inputs are 1. The mod ule furth er speci fi es two 4-bit wires, tempC and il/cC, used as intern al wires within the structural description. The module instantiates each of the three components and speci fies the connections between them. Reg4 is the only sequential component w ithin the up-counter and thu s the elk input only needs to be connected to the clock input of the register. We control the up-counter' s counting by connecting the count enable input. CIII . to the load enable. Id, of the register. The output Q of Reg.J_1 is
-
~
module Reg4tI. Q. elk. ld); input (3 :0) I; input elk. ld; output {3:0] Q; II details not shown
endmodule module Inc4 (a,
5);
input (3,01 a; output [3:0) 5;
II details not shown endmodule module AND4(w.x,y,z.F); input w, x, Y, output F;
Z;
II details not shown endmodule
~:!:tU~~~~~~~Clk,
cnt,
C.
tc);
output (3,0) C; reg 13 , 0) C; output tc;
wire 13,01 tempe; wire (3 : 0] incC; Reg4 Reg4_1 lince, tempe, clk. cnt). Inc4 Inc4_1 (tempC, incc); . tempe 12) tempe Ill. tempCIOI: te);
AND4 AND4_1 (tempe 13).
alway. @(tempC) begin C <= tempC; end endmodule
Figure 9.32 Structural Veri log des ription of ~-bit
up-coumer.
=---~
--_ ..
47~
Hardware Desc ription l ang uages
9.5 RTl Design Using Hardware Desc ription Languages • 475
connected to th e internal signal lempC. w hich connects th e register's output to both the IlIc-l_1 and AND-I_I co mponents. IlIc-l_ 1 receives the current count from th e lempC connect ion and ou tputs th e incremented count on its output s which is connected to the other intern al signa l illcC. The illcC signa l connects the incremented count from IlI c4_ 1 to the para llel load input I of Reg4_1. The current count is also connected to the four inputs of th e AND-I_I component. The AND 4_ l' s output F is th en connected to th e counter' s terminal cou nt out put Ic. In th e UpCo llll le r des ign, we need to connec t th e output o f th e 4- bi t regi ster to the incrcme nt er. th e AN D gat e, and th e counter' s output port C. Therefore, the module uses th e l empC sig nal to co nn ec t Reg4_ l' s o utput to both th e AND4_ 1 and IlI c4_ 1 components. We still need to .include ·systemc. h" connec t th e reg ister 's output ff:include "reg4 . h" to th e output port C. The #include "inc4 . h" modul e makes thi s conneC#include "and4 . h" ti on by specify ing SC_ MODULE (UpCoun ter 1 procedure th at is used to ( connec t th e ou tput o f th e sc_ in elk. cnt; s C_ out > C ; register 10 th e output port C. The procedure i sensitive to th e signal lempC. prev iously sc_ signal > tempC, ineC; sc_ signal <8c_ logic > tempC_b [4] ;
used as an intern al wire between th e three compoWh enever lemp C nents. changes. whi ch corre sponds to a change in th e upcounter's stored count. th e procedure ass igns th e new count to the output port C. System C Figure 9.33 is a SystemC description of a 4- bit upappeared in counter, a Figure 4.48. The SystemC modul e, named UpCol/llter. defines th e counter's inputs and outputs, consistin g of a cl ock input elk, a count enable control input ClII, the 4-bit count value C, and a tenn in al cou nt output Ie. T he UpColllller 's module th e structu rally descri bes design consis ting of three components, namely, Reg4, IlIc4. and AND4. Reg4 is a
Reg4 Reg4_1; Inc4 Ine4_1; AND4 AND4_1; SC_ CTOR (UpCou nter)
Reg4_1 ( " Reg4 _ 1 " ) , I n e4_1 ( "Ine4_1 ") , AND4_1 ( "AND4_ 1 " )
(
Reg4_1.I{ineC) ; Reg4_1 . Q{tempC) ; Reg4_1. elk (elk); Reg4_l.ld{ent) ; Inc4_1. a (tempC); Ine4_1. s (inee) ; AND4_1 . w (tempC_b [0 J ); AND4_1. x (t empCb 11 J) ; AND4_1 . Y (temp C_b 12 J ) ; AND4_1. z ( tempCjJ [31) ; AND4_1. F (te) ; SC_ METBOD (eomblogie) ; sensitive « tempC;
void eomb l ogie ( ) tempC_b [0 I tempC . read () ternpC_b [11 tempC . read () tempC_ b [2 J tempC . read () ternpCjJ 131 tempC . read () C. write (tempC) ;
4-bit parallel load register with a load control input lei. IIIc4 is a ~ - bit incrementer. AND" is a four-input A ND gate that will output 1 if and onl y if all four input' are 1. The module further specifies two 4-bit signals. lempC and illc , u"cd as interna l w ires within Ille structural descripti on, Additi onally. the module defi nes a four-element array of ,c_log ic signals. named lempC_b. u ed to access the individual bits within the 4-bit Vec tor lempC. T he module first instantiates each of the three c mponelllS and th en specifies the connecti on between them. Reg" is the only sequent ial component w ith in the up-counter and thu s the elk in put only needs to be connected to the c lock i nput o r the reg ister. We contIol th e up-cou nter's counting by connecting th e count enab le input . CIII , to th e load enabl e. Id, of th e register. The outpu t Q of Reg4_ 1 is connec ted to the in tern al signa l tempC, which connects the register' output to IlIc4_ 1. IlI c4_ 1 receives th e current count from the lempC connecti on and outputs the incremented count on its output " w hich is conne ted to the internal signal illcC. The ill cC signal connects the incremented count from 111('4 I to the parallel load input I of Reg" _I . The current COun t is aL connected to the fo~ r inputs of the AND4_1 component using th e lempC_b array to access th e individual bits. The AND4_l's output F is th en connected to th e counter 's termin al Count outputlC. In the UpCol/lller deSIgn. we need to connect th e output o f the 4-bit register to the incrementer, the AND gate. and th e counter's output port . Therefore. the module uses th e lempC signal to connect Reg4_ l's output to the IlIc4_ 1 component and uses the lempC_b array to connect Reg4_l's output to the AND4_ 1 component. Thus, we still need to connect the register's output to th e output port C and as" ign th e indi vidual bits of the register'S output to th e tempC_b array. Th e. ~lodu l e makes th ese connections by definin g a process, named comblog lc, that IS senSlll ve to the signa l lemp . Wh enever tempC changes. which corresponds 10 a change III th e up-counter's 5t red count. th e comblogic process assigns th e new count to the output port C. Additi onall y, the process assigns the bi ts withi n vector tempC w the ,"d, vldual sc_log ic signll is w ithin the lelllpC_b llrray. In order to access the IndIVIdual bIts of the Vector SIgnal lempe. we use the syntax . MtempC.read()[O) " .
~ 9.5 RTl DESIGN USING HARDWARE DESCRIPTION LANGUAG ES We now show how 10 create RTL descripti ons using HDLs. We w ill show HDL description s o f the startin g point of RTL deSIgn, namely. high-level state machines and of the ending point of RTL design, namely, connected controllers and data path s. RT L de igners w i ll common ly create a testbench to test the hIgh- level state machine description, and then use th at same testbench fo r th e comroller/datapath descripti on, thu s helping to verify that the designer created a correct controller/datapath IlTIpl emcnti on.
High-level State Machine of the laser-Based Distance Measurer [0 J [1 J [2 J [3 J
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figure 9.33 Slructu ral SystemC description of 4-bit up-counter.
VHDL Figures 9.34 and 9,35 present a V HDL descripti on o f a hi gh -level state machi ne for the laser-based distance measurer shown tn FI gure 5. 15. The entity, named Laser· DislMeasli rer. defines the ,"puts and output , II1cludin g a u ser- pre ed bunon input B. a la er sensor input S, a laser control output L, and a 16-bit o utput D fo r the distance measured.
476
9 Hardware Description Languages
9 ~ Rll Design USIOg Hardwaro 0 cnphon Languagos
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librazy ieee; u •• ieee . std_logic_l 164 .all; u •• ieee.atd_lOO'ic_arlth.41I;
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U .Dtity LaserDistHeasurer i . port ( elk. rst: in std_I09ic: B. 5; in std_logic; ~; out std_Iogic; 0: out unsigned(15 downto 0)
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Figure 9.34 Behavioral VII DL dc'eripliol1 of 3
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InSlead of using a 16- bil ."d_logic_ ,'eclOr. we defined the OU lput 0 as ullsigned. For log ic operati ons. an ullsigli ed behaves the same as a sIlClogic_,'eclor. However. we can also perform ari lhmelic operations on ullsiglled values. Whenever u ing unsigned. __ e musl include the Slalement ··use ieee . 5 td_1 og ; c_a ri th. all; ·· at the lOp of our YHDL descriplion. The use slatement spec ifies which package we will use within our design. The package ieee.sld_logic_arilir defines Ihe ullsig lled type as well as a set of operati ons and functions we can perform on ullsigll ed value. The entity also defin e a clock inpu l elk and resel inpul r SI . We assume that the clock input is 300 MH z. as was assumed in the laser-based distance measurer design shown in Fi gure 5.19. We omil delails of generating Ihe 300 MHz clock (see Section 9.3 for an exampl e of describing an oscillalor). The YHDL archilecture describes the behavior of the entity. Instead of using IWO processes as shown in Figure 9.22. the archilecture consists of a single process describing Ihe behavior of our high·level state machine. The high-level state machine process. named slO lelllacirill e, is sen itive to inputs elk and rsl. If the rSI is 1 , then the process asynchronously selS the slate signal 10 the state machine ' initial state, SO, and initializes
Figure 9.35 Beh3>I<'I1I1 HI)l. descnpli n of. hl&h·l",el ,laiC machine of lhe I.",r·b ",d
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the OUlpUt!>. Land O. and the ,"Iemal cmmler "~"IJI . /)//, . Ie) Ihell d ·fallh vIIIII ,. '111e default value, hould corrC5poncJ 10 Ihe va lue, "'''g'' cJ III Ihe "~rllll' IIIlIhlll the lI1i" ,,1,Wlc of our high.le\el 'tale machine. olice thm we defined U (0",1,1111. nllliled (J 11-.110. colre· sponding 10 the 16--bll I/IIJ'gned vnlue "f l ero. When Ihe 11,,1 e"ahled. "" Ih ' ri,i " clock. the proce ~ evalume, the current ,wte. ;I\"lln\ Ihe "pproprinle Ulilput, fnr Ihe currenl state. determine the nexl ,wte. and updale, Ihe , lute reg"ler "gnu!. \ 1/11" . In uur III B.h level Slale machine dcscrip"on. we only need a "ngle tale reg"ler" n"l ln l1",del Ihe behuvinr of our tate machme, in ~lead of the two ,'gnal, c urmllllale and IIr>lI ll1le we prevlllu\ly used in the controller design hown '" Figure 9.22. The high·level Ulle mach me for Ihe IU'lCr·ba'ICd d"wnce meawrer perfnnm IwO arithmetic operalions. addilion and ,hi fling . By u\ing Ihe /II"i/l,wtl lype. 10 lI"remenl Ihe counter signal OClr in stale 53. we use the 'yntax. "Dc l r ( Dc t r + 1; .'. 'I h" stale· ment will add one to the cu rrent value of OCIf and \lore the re\ult in Ik/r. In ,tute S4, we calculale Ihe di \tancc. 0 , by dividing Ihe value of J)( If by 2. Iluwever. we perform Ihi. division u ing a righl·shift-by-one operation. To perfom) Ihe , hlft "nd a"igll the vulue 10 the outpul O. we use the M31ement "0 (- SHR( Dc lr, U ONE) ; ". The funclion SHR() , defined within the; eee. 5 td_1 og ; c_a rl h package. \ hifl ~ the fi"t paramo eler. OClr, by the amount specified by the second parameler. V_ONE, where V_ONE i ~ a constant we defined earlier in Ihe architecture.
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Verilog Figures 9.36 and 9.37 presenl a Yerilog description of a high· level \tate machine for the laser-based distance measurer shown in Figure 5.15. The module, named Laser· DislMeasurer. define Ihe inputs and outpuIS, including a user·prc s~ed bullon inpul B. a
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Figure 9.36 Bch3\ ioral VHDL de,criplion of n hlgh·lel'el
m:u.:hillc·s initial ~Ia I C . O. and inilializes Ihe QUIPl" '. L and D. and Ihe imernal cou mer regisler. DClr. 10 lheir defauh value. The defauh valu shou ld correspond 10 Ihe values as igned 10 Ihe ignal \Vilhin Ihe ini li al late of our highlevel SlalC machinc. When the rSI is nOI enabled. on the rising clock. the procedure evaJu· ale, Ihe curre nl 'laiC. assigns the appropri ale OUlput for the curren! stale. delennin the neXI SlalC. and updales the laiC regislcr. In our high-level stale machine de criplion. \Ioe onl, nced a si ngle late register signal 10 mode llhc behavior of our Slale machine. instead of Ihe IWO rcgi slcr signal s CIIrr elllSfGle and lIe.tlSfGle we previously used in the controller design shown in Figure 9.23.
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S" lem(' Igure' 'l ~H alld I) W rrc'<'n! il S~'ICI11 de...:"pu!>n III ,I hl!!h·le'cl ,I;Ile IIIJlhan' tnr Ihc IJ\Cr·ha'Cd UI,lJIleC mea K U1'1IOO I • • mMI"'hlnt!'I , urer ,hown an IIFure ~ I~. ..n.ltt •• PO' « r. 1 I The module. n.lloco 1..1.11/ r· 1J'flMwlllrrr. dchnc lhe anpul' and oUlrUI,. ancluu," a uler'pre \Cd hunnn anpul H f r ' re&d O • S<.' 1.oGIC I I ( " write ..LOCI 01 B. a l3.ler len",r anJlllI .S, J write 13....:r control OlIlpUI L. Jnd J at , II 'ni~i.l a (I' 16.bll oulpul D for Ihe d,,· ) lance mea~ured. .1 •• ( The module 31\0 dehnc' ..itch • ' J c ••• a clock inpul elk and rc\C1 L. write I 1.oGie 01: II I •• ~r of! inpul r.l/. We a"ume Ihal Ihe o, wri.e lOI, II c1"'o. r 0 tAt.#> clock inpul i\ 300 MH7, a\ bred ; was a,sumed an the laler, ca •• Ot: r O. 1/ cleat coun b3.\Cd di,wncc me3.\urer H fB. rea4 11 • SC LOGIC 11 design ,2; We omil detail; of generaung (conbnuod in FI(1UfO 9 39) Ihe 300 MHl clock (~e Seclion 9.3 for an example of Figure 9.38 8th,"!>..JI Sy\ltm dClCflpulln of a high-level \laic machlllC of lhe 1.o,c;r·ba.\Cd d"tance me" Uf.r describing an O\Cilialor). ('I
480
Hardware Descnpllon Languages I he S} 'ternl module beh,,, ",retll} de,enbe, Ihe l..ill,.,!)"/il" ,{/, ,,,,,r', high· bel 'tate m.lehlne . In"e
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lI1ach lne', Inll i.tI ",lIe. SII. and 11111 ",II Ie' Ihe "UlpU". L ,", d !). and Ihe InlCrIlu l wunle r "gmll. nur. III Ihcor IklJuh \.llue, The ddauh \alue , llOuld corre'pond (() Ihe v" lue' ." "gned 10 Ihe Ignal, \\ lIhl11 Ihe 111111al ,I.IIC of our high· leve l ,I: ll c lIladllf1e. When Ihe /'II " nul cn"bkd. on Ihe mlng dod. Ihe proce' C' aluJlc Ihe curre nl ;.Ialc. a" lgn, Ihe "ppropn'lle OU IJ1UI' for Ih . eurrelll "a'c. determine, the nett ;'Iale. and updale' Ihe -talc reg l-ter ,ignal. \1111 ... In our hlgh·le\tl 'laiC machine de nplion. we onl ) need J , ingle 'lUle reg"la 'Igllal 10 model the heha\lor of our laic nwchille. in, lead of Ihe 1\\ 0 ' Iglla!> l'IIrr""/.lIl11t' .tnd ",'\/\/(/1/' we prc\iou,l) u<,Cd III I~ w lli roller de,ign , lll1\' n in Figure 9.24 . The 11Igh· b 'e l ,Wle machi ne for Ihc la,e r·b"ed dl,tance llleJ'urer perform, 1\\0 anthmClic opemli on;.. addill on and 'hifling. To incremenl Ihe counler o Clr III ,late 3. "c U Ihe ,) Illa \. "D c r Dc r . read () + 1: ". Thb ;'(Ulcmelli ,,, II ndd one 10 Ihe urren! va lue uf o ("/r and -tore Ihe re,uh in o C/r. III 'talc 5-1. \\C calcu lmc Ihe di'lancc. D. b~ di, iding Ihe ,aluc of DC11' h) 2. Howe\ er. we perfo rm Ihi, di,i,ion u illg a nght , hl ft b} ~ ope ,,"ion. To perronn Ihe , hif! and ,,,sign the va lue 10 the Ulpul 0 , we u c the , lalemeOi " D. wr i t e ( Dc t r . read ( ) »1 ) : " . where » perfonns a ri ght hil'l opeml ion.
Controller and Datapath of the Laser-Based Distance Measurer VUDL Fi gure 9.40 is 3 HDL descriplion of the laser-ba. ed di slance measurer hown in Figure 5. 19. The emit )'. named ulseroislMeasllrer. defin es the inpuls and outpulS. including a user-pressed butt n inpul B. a I a.~e r sensor inpul . a laser conlro l outpul L. and a Iii-bit OUlput 0 for the di slancc measured. The entil)' also defines a 300 MHz clock input cl and re el inpul rSl for the design 's controller.
Figur. 9.40 SlnKtu",1 de'iCripllon of Iop-k\d VHDL de\Cflptton or II",r· ba..cd dl lance mea urer The LosuDIJlM~Ufurer" ilfchltecture ItJUCIUroJly de n he' the ,onneellnll' of Ih ' conoroller and dalapath component, 1llc :.rChllectUlc In'ta01 l11tc, Iwn elllllr<1rICI1t\. WM Com roller I I lhe controller for the IU'lCr h.l\Cd d"wnee men",rer ano WM=oalOpmh_' IS the daUlpalh for thl\ de"gn The arehlletlurc Cflnnctt' Ihe enllly" ( lie. rSI. B. and 5 inpuls 10 Ihe inpull of WM_ on/mll, r_I "nd eonnetl, Ihe coni roller', l a~c r control OUIPUI to the corresponding OUlpul por1 L. Addill!mully, Ihe four "gnul ,. /)I"('II-"Ir. Dreg_ld. DC1r_clr. and Del'J nt, connect the controller' four conlml "gnal, 111 the ruur inputs of WMflalOp(lI"_I . 1llc l.lllrrDIfIMeaUlrrr dlllapalh ha, u \l nglc !)Ulput IJ , providing the distance mea.wred. that I~ connected to the outpul pon () of the cntny. Figure 9.4 I is a VHDL descriplion of the La.JrrDwMell fl""" " duwpalh comr
-'82
9 Hardware Description Languages
9.5 RTL Design Using Hardware Description Languages ... 483 library ieee; use ieee. std_logic_1164 . all; entity LD}LDatapath is
port ( elk: in std_logic; Dreg_clr, Dreg_ld : in std_logic: Detr_clr. Dctr_cnt: in std_logic; D: out stCLlogic_vector(lS downto 0) );
end LDtoLDa tapa th i
a rchitecture structure of LDM_Datapath is component UpCounter16 port ( elk: in stdlogic; clr. cnt : in std_logic; c: out stcLlogic_vector(lS downto 0) );
end component ;
component Reg16 port ( I: in std_logic_vector(15 downto 0); Q: out std_logic_vector(lS downto 0). clk, clr, ld: in std_logic );
end component . component ShiftRightOne16 port ( I : in std_logic_vector(IS downto a). S: out std_logic_vector(15 downt o 0) );
Figure 9.41 SlruclUral VHDL descriplion of Ihe laser-based dislance measurer's dmapi.llh .
end component ; signal tempC std_logic_vector (15 downto 0); signal shiftc : std_logic_veetor(15 downto 0) ; begin Dctr : UpCounter16 port map (clk, Dctr_clr, Detr_cnt, tempC); Shi ftRight: Shi ftRightOne16 port map (tempC, shifte) ; Dreg! Reg16 port map (shifte, 0, clk, Oreg_clr, Dreg_ld); end structure;
parallel load register with a register load control signal Id and a register clear signal elr. ShijlRighlOllel6 is a 16-bit right shifter that shift s the input I ri ght by one posi tion and assigns the shifted va lue to the outpu t S. The architecture instantiates an UpColllllerl 6 compone nt named Delr, a Regl6 co mponent named Dreg, and a ShijlRighlOne l6 component named ShijlRighl. Delr's in stant iation co nnec ts the datapath's DCII'_elr and DCII'_ClII inputs to DClr's clear and count control inputs. Delr's co unt output C is then con nected to the arch itecture 's internal signal lempC that co nnects the count value 10 the ShijlRighl shifter's input. The shifted coun t is thcn connected to the input of the Dreg regi ster using the internal signa l shijte. The instan tia tion of th e Dreg regi ster connects the register's clear and load control inputs to the datapath's Dreg_ell' and Dreg_ld input ports. Fina ll y, the register's data output Q is connected to LDM jlatapalh' s measured di stance ou tput D .
Figure 9.42 and Figure 9.43 are the VHDL description of the laser-based distance measurer's FSM controller described in Figure 5.2 1. The entity, named LDM COlli roller defi nes a clock i~put elk. ~ reset signal rSI, a user-pressed button input 8. a laser sensor input S, and five output control signals, L, Dreg_cit; Dreg_ld. DCII'_el,; and DClrJ III. The output L is used to turn the laser on and off, where if L is 1, the laser is on. The four other output signals are used 10 con trol the RTL design's datapath components. The VHDL architecture describes the behavior of the enti ty. Si milar to the controller design sholVn in Figure 9.22. the architecture consists of two processes, one modeling the stale register, the other mod-
library ieee; u.e ieee.stc;Llogic_l164.all; entity LDM Controller is port ( ~lk. rst: in std.-logic; B. S: in stcLlogic; L: out stcLlogic; Dreg_clr, Dreg_ld: out std_logic; Dctr_clr, Dctr_cnt: out std_logic );
end LDM_Controller; architecture behavior o f LDM_Controller i . type statetype ia (SO, 51. S2, 53, S4); signal currentstate, nextst8te: statetype; begin statereg: proce.s (clk, rst) begin if (rst='l') then currentstate <= SO; -- initial state elaif (c!k='!' &nO elk'event) then currentstate <= nextstate; enO if ; end proce •• ; comblogic: proce •• (eurrentstate. B. begin L <= '0'; Dreg_clr <= '0'; Dreg_ld <= '0'; Detr clr <= '0'; Dctr=cnt <= '0': ca.e currentstate is when SO => laser L <= '0'; clear Dreg_clr <= '1'; nextstate <= Sl; when Sl => clear Detr e!r <= 'I' it (B;' 1 .) tbeD 52; nextstate
5)
eling the combinat ional logic. off The state register process, Dreg named stalereg, is sensitive to inputs elk and rSI. If the rSI is count enabled. then the process asynchronously sets the Cllrrelllstale signal 10 the FSM 's init ial 51; nextstate state, SO. Otherwise, if the end if : clock is rising, the process updates the state register wilh (continued In Figure 9.43) the next state. The second process, Figure 9.42 Behavioral VHDL dcscriplion of laser-based named comb/ogie. is sensiti ve distance measurer's controller.
to t.he inputs to the combina. tional logic of Figure 5.21. namely, the external inputs 8 and S. and the state regIster output c"neIlISlale. When either of those items change. the proce sets the FSM's outputs. in thi s case L. Dreg_ell; Dreg_"'. DClr_el,; and DClr-,"I, wilh the a~propri ate value for the current state. In the controller example of Figure 9:22. the FSM s output x was defined within the case statement for all possible states. ~lIh five output that mu t be defined in the LDM COlli roller and five possible states. as Ig~lIlg the values to all outputs in eac h stat e would be cumbe rso me. Fu rthermore, find In g a mI stake and makmg
484
Hardware Descriplion Languages
95 RTL Des'gn USing Herdware Descnpllon Languagos
correcli on, or modificalion, 10 Ihe (contmued from Figure 9 42) com roller would become very di rwhen 52 => L <::: '1'; -- laser on fkul! in a larger FSM con,iqing nextstate <= 53; or more Slale, and having many when 53 :::;> more oulpul ,. The comblflgic L <= '0'; laser off Decr_cnt <= . 1 • ; count up proces, u,e, a dirrerenl approach if (5.'1') then in which a derau ll va lue for Ihe nextstate S4; OUIPUIS is Or>! as,igned and only .1 •• nextstate <= 53; Ihe deviali ons from Ihe deraul!, end it ; arc a. , igned laler. The comblogic whe n 54 => process fir" as,ign, a deraull load Dreg Dreo_ld ·1' ; Detr_cnt <= • 0' ; stop countino value or 0 10 all five OUIPUI . The nextstate <= 51; prates, Ihen eva luale Ihe currenl end ca •• ; ~ lalC and a~, i gn' Ihe.! value... to end proce •• ; Ihe OUlpU!> only when Ihc OUIPUI e nd behavior; , hould be 1. The prace" aha as,igns Ihe va luc 0 10 ,eve",1 Figure 9.43 Beha, 101111 VHDL de,cnpliOIl or la'er-based di,tn ncc I11Ctll.,UrCr', controller (cofllillll('d). "ignal" wilhin Ihe "," ell "WICmen IS.
howc;ver.
Ihc~c
a~~ign-
melli' arc included on ly 10 clearly indica le Ihe behavior or Ihe cOlllrolier (Ihey arc redundalli. bU I help make Ihe descriplion easier 10 unde"wnd). Thc process 01,0 delcnnincs whal Ihe nexl "ale shou ld be. based on Ihe currenl slme and Ihe v:llues or inlulS Band S. The neXI 'laIC will be loaded in lo Ihe slmc regisler by Ihe slalC regi, lcr process on Ihe neX I ri sing clock edge. Vcri log Figure 9.4-1 is a Veri log descriplion of" Ihe laser-ba cd di lance measurer shown in Figure 5.19. The module. named
ulSerDisrNfeasllrer.
module LaserDistMeasurer(clk. rst. B. S. L. D); input clk. rst. B, S; output L;
output 115,01 0; wire Dreg_clr. Dreg_Id; wire Detr_clr. Detr_cnt ;
defines Ihe inpuls and oulLD~Controller pUIS. including a user-pressed LD!-l_Controller_l (clk. rst. S, S. L. Dreg_clr, Dreg_ld. bUllon inpu l B. a lasc r cnsor Dctr_clr. Dctr_cnt); inpul S. a laser control OUlpul LDM_Da tapa th L. and a 16-bil oulPUI 0 for LD1-COa tapa th_l (clk. Dreg_clr. Dre9_1d. Dctr_clr. Detr_cnt, 0); the dislance measured. The module also defines a 300 endmodule MH z clock inpul elk and Figure 9.44 Slruclura l descriplion of lop-level Veri log resel inpu l !"SI ror Ihe design·s descri ption of laser-bnsed distance meilsurer. con troller. The LaserDislMeas/lrer structurally describes Ihe conneclions or Ihe controller and dalapmh componenls. The mod ul e inslantiales IIVO componenls. LDM_Colllroller_ 1 is Ihe cOnlrollcr ror Ihe laser-based dislance measu rer and LDM_Dataparh_ 1 is the dalapath for Ih is design. The archileclure con neCIS the module·s elk. r SI . B. and S inpuls 10 the inpuls of LDM_Collfroller_ I and con neCIS the con lroll er's laser control OUIPUIIO the cor-
-ISS
responding OUlpUI port L. ddilionnlly. Ihe rour imcnwl wire,. Ol\'g_clr. D"",~ _ltI. Dcrr_elr. and DcrrJ ill. connc I the cOntroller' ~ ur cOlllrtJl ,ignnl' 10 Ihe rour inpulS or LDM_Dawpmh_l . Thc ulserDislA/PtU'If"l'r dillupmh hu, (I 'inglc OU lpUI D. providing Ihe dislance mea ured. Ihal is connecled 10 the OUlpUI port I or Ihe modulc. Figure 9.45 i a Vcrilog descriplion or Ihe lIOdulo IIpCounter16 (elk, eIr, cnt, e): LaserDislMecwlfu·s dUlaiopu,t elk. clr. cnt: palh componcOl shown in out""t 115,01 C; If detalla not Ih '" Figure 5. 17. TI,e modu le. named LDM_D{//lIJI{l/h. defi nes a clock inpul elk, _ 1 . RegI6(I, 0, elk, elr. Idl, i"""t (15,01 1/ rour control inpuL~ DregJlr. iJ>put elk, elr. ld, Dreg_ld. DClrJ lr, llnd out""t 115;01 0, DClr_CIII. and a 16-bil di~ I detail. not .hewn lance OUIPUI D. The dmapalh consist; lIOdul. ShHtRlghtOne16 (I, 51, iJ>put 115;01 I; or three componenls. a out""t 115;01 5; 16-bil Up-couOler. a 16-bil /1 detaill not Ihewn regislcr. and a 16-bil righl shiner Iha! hin, righl by LOll_De apath(elk, Oreq elr, Dug ld, one position. Up OlllllerDc r_cl r, Detr cn . 0): 16 is a 16-bi l up-counler i"""t elk; i"""t Dreg_cl r , Dr.g_Id, wilh a counl control inpul laput Octr_clr, Delc, cnt j elll and a counl clear inpul out""t (15;01 0, elr. Reg l6 is a 16-bil parwire (15,01 tempC, ahlttC, allel load regislcr wilh a regisler load control "ignal UpCounter16 Dctr(clk. Detr_cle. Dc c_cnt, Id and a regiSler clear tempCl, ShiftRlllhtOnel6 ShiftRlqht (tempC, ahlL LCI : signal elr. ShiftRighlOlleReg16 Dreg(shiltC, 0, elk, Orell_elr, Dreg_ld), 16 is a 16-bi l righl shifter eDdIIo4ul. thaI hi rls the inpul 1 righl by one poSlI,on and Figure 9.45 Slruclural Vtrilog de
_1.
.1IdIIodul.
_1.
_1.
486
Hardware Description Languages 9.5 AlL Design USing Hardwaro Dascnptlon Languages
Figures 9.46 and 9.47 arc the Veri log de criplion of the laser-ba ed di tance measurer's FSM controller de;cribcd in Figure 5.21. The module. named LDM_Colllroller. defines a clock input elk. a re~el ignal nl, a u..cr-pr« cd bUllon inpul B. a laser ensor input S, and five OUlput control signa l;. L. Dreg_clr. Dreg_id. DCfrJir. and DcrrJIII. The OUlput L i used to !Urn the laser on and off, where if L is 1. Ihe laser is on. The four oLher output signals arc used to conLrol the RTL design' datapaLh components. module LOM_Controller (elk, rst, B. S. L. Dreg_elk. Dre9_1d. Deer_clr, Deer_cnt) ; input elk, rst. 8. S: output L; output Dreg_elk. Dreg_ld; output Deer_ elr. Decr_cnt; reg L; reg Dreg_elr. Dreg_ld; reg Decr_clr . Octr_cnt;
parameter SO 51 52
53 54
3'bOOO, 3·b001. 3 'b010, 3 ·bOll. 3'blOO;
reg (2:0J currentstate: reg [2:0J nextstate; alway. @ (po.edge rst or po ••dge elk) begin
(rst==ll
if
currentstate
so; II initial state
el ••
currents tate
nexcstate;
end
always @ (currents tate or B or 5) begin L <= 0;
Dreg_elc <= 0; Dreg_ld <= 0; Detr_elr <= 0: Dctr_cnt <= 0: case (currents tate) 50, begin L <= 0;
Figure 9.46 Behav ioral Verilog description of laserbased di stance measure r's con troller.
Dreg_clr <= 1; nextstate <::: 51; end
II laser off II clear Dreg
(continued in Figure 9.47)
The Veri log module behaviorally describes the LaserDislMeasllrer's FSM. Similar 10 Lhe controller design shown in Figure 9.23, the module consisLs of IWO procedures_ one mode li ng the sLaLe regisler, the olher modeling Ihe FSM's control log ic. The state regiSler procedure is sensi li ve 10 the po ilive edge of the reseL inpuI, r SI , and the positive edge of the clock inpuI, elk. If the r SI inpul is enabled, Lhen the procedure asynchronously sets Lhe ClirrellISIGle signal 10 Ihe FSM 's inilial sLaLe, SO. OLherwise, on the rising edge of Lhe clock, the procedure updaLes the Slale regisler wilh the neXI stale.
-'117
The se ond procedure i, sensiti ve to the inputs to the (conhnll6d from FtgUre 9 46) Sl, be9in combi naLional logic of Figure Octr .c1r < 1; II clear count 5.2 1. namely, the ex ternal inpul~ i f 10 I) Band S. and the ~t ate regi ter next.tAt.e.. 52: _1 •• output ClIrrelllSlate. When either n xtat . . . SJ: of those items change, the proceeD4 dure et the FSM's ou tpu l~. in S3, be9in L <- I; II I ... r on this case L, Dreg_clr. Dreg_ld. nex .tat..... S3; DCIrJ lr. and DCIr_CIII . \ ith the eD4 S3, bGQln appropriate value for the current L .. 0: /I lUG, oCt state. In the controller example of Oc:tr cot 1; II Count up Figure 9.22. the FSM', output .f i f (S I) was defined within the ca>e SlUten xt.tate 64: _1 •• ment for all possi ble states. With n xt.tate S3r five outputs thm mu>! be defined oDd S4, be9in in the LDM_Colllroller and five Dreg ld < t, /I load Dr 11 possible tates. as ign ing the Dc r ~cn < 0: II .top countinQ values to all ou tputs in each SLate next.tate <_ 51, oDd would be cumbersome. Funher_040 ••• more. finding a mistnke und oDd making corrections or modifica- e~ul_ Lions to the controller would become very difficult in a larger Figure 9.47 Bchflviom l Veri log de,cription of In,er-bused FSM consisting of more states dbt.n c ",casurer\ conlrolier (mlllilillcd). and having many more outputs. Instead. the procedure uses a diffe rent approach in which a default va lue for all the ou tputs i, fir" assigned "nd only the deviaLions from the defaults are assigned later. The procedure fi rst aSlignl a default va lue of 0 to all five outputs. The procedure then eva luates the current blate and assigns the va lues to the outputs only when the output shou ld be 1. nle procedure also assign!> Lhe value 0 10 several signals wi Lh in Ihe case SLa lemenl~. however, Ihese assignments are included only to clearly indicate Ihe behavior of the controller (they ure redu ndant, bUI help make Ihe descriplion easier 10 undersland). The procedure also deLermines what the neX I Slale should be, based on the current staLe and the values of inpuls B and S. The nex i Slale will be loaded into the SLale regisler by the Slale regisLer proced ure on Ihe nexl posi live clock edge.
"'ss
Hardwa re Desc ription Languages SystemC Figure 9.-18 is a SystemC descrip'include "systemc .h" tion of the laser-based distance linclude ·LDM_Co ntroller . h" 'include "LDM_Datapath . h" measurer shown in Figure 5. 19. The module. named w serDislSC_ MODOLE ( LaserDistMeasurer) Measurer. defines the inputs and ( sc_ in elk. rst; ou tputs. including a user-pressed sc_ in B. S; bUlion input B. a laser sensor sc_ out L; input S. a laser control output L, sc_ out > 0; and a 16-bit outpu t D for the dissc_ signal Dreg_cIr, Dreg_ld; tance measured . The module also sc_ signal <8c_ logic > Detr_cIr. Detr_cnt j defines a 300 MH z clock input LDM_Controller LD~Controller_l ; elk and reset inpu t rsl for the LDM_Datapath LDt-LDatapath_l; design 's controller. The w serDislMeasurer strucSC_ CTOR (LaserDistMeasurer) : LDM_Controller_l (-LDM_Control ler_l-). rurally describes the connections LDM_Datapath_lt·LDM....Datapath_l · ) of the controller and datapath co mpo nents. Th e architectu re LDM_Controller_l. clk (clk) ; LDf>CController_l. rst (rst) ; in stanti ates two co mponents. LDM_Controller_l.B(B) ; LDM_Colllroller_1 is the co nLDM_Controller_l. S (5) ; troll er for the laser-based di stance LDM_Controller_l . Dreg_clr (Dreg_c lr) ; LDM_ Controller_l. Dreg_ld (Dreg_l d) ; measurer and LDM_Datapalh_1 LDM_Controller_ l . Dctr_clr (Dctr_ clr) ; is the datapath for thi s design. LDM_Controller_l. Dctr_cnt ( Dctr_cnt) ; Th e modul e co nn ects th e LDM_Datapath_l. elk (elk) ; module's elk, r SI , B, and S inputs LDM_Datapath_l. Dreg_clr (Dreg_clr) ; to th e input s of LDM_ LDM_Da tapa th_l . Dreg_ld (Dreg_ld) ; COlllroller_ I and connects the LDM_Datapath_l . Dctr_clr (Dct r_clr) ; LDM_Datapath_l . Dctr_cnt (Deer_cnt) ; comroller's laser comrol output to LDM_Datapath_l.D{D) ; the corres ponding output pon L . ) Additionall y, the four internal ) ; wires, Dreg_elr. Dreg_Id, DClr_ elr. and DClr_cllI, connect the Figure 9.48 Structural description of top-level SystemC controller's four control signal s to descripti on of laser-based di stance measurer. the fo ur inputs of LDM_Datapalh_ l . The LaserDislMeaslirer data path has a sing le output D, providing the distance measured, th at is connected to the output pon D of the modu le.
9.5 RTl Design Using Hardware Description languages
489
. Figure 9.49 is a SystemC descrip.include • systemc. h· tIon of the ulserDislMeasllrer's 'include ·upcounterl6 . hdatapath component shown in Figure .include ·regl6.h· 5. 17. The module, named LDM 'include ·shiftrightone16 hDawparh, define a clock input C/k~ four comrol inputs Dreg_c/r, Dreg_Id, DClr_elr, and DClrJIII, and a 16-bit 8c_ in<8c_loglc > elk; 8c_ln<8c_ logic > Dreg_clr. Dreg_ld; distance output D. 8c_ ln<8c_loglc> Dctr_clr. Detr_ent; The datapath consists of two 8c_ out <8c_lv<16> > D; components, a 16-bit up-counter, a 8c_ 81gnal <8c lv<16> > tempC; 16-bit register, and a 16-bit right 8c_ 81gnal <8c:=lv<16> > shiftC; shIfter that shifts right by one posiUpCounter16 Detr; tion . UpCollll lerl6 is a 16-bit upReg16 Dreg; counter with a count control input ShiftRightOne16 Shi ftRight; CII I and a count clear input clr. Regl6 SC_ CTOR (LDM_Datapath) : is a 16-bit parallel load register with Detr(-Detr-). Dreg(·Dreg·). a register load control signal Id and a ShiftRight (. ShlftRight·) register clear signal elr. ShifrRighl Dctr.clktclk) ; 0llel6 is a 16-bit right shifter that Detr .clr (Dctr_clr) ; shi fts the input I right by one posiOctr. cnt (Detr_ent) ; tion and assigns the shi fted val ue Dctr.C(tempC) ; to the output S. The datapath module ShiftRight. I (tempC) ; in s ta nti ates an UpCo lllll er l 6 ShiftRight.S (shiftC) ; component named DClr, a Reg l 6 Dreg. I (shiftC) ; component named Dreg, and a Dreg . Q{D) ; ShijrRigh rOlle l6 component named Dreg . clk{clk) ; Dreg.elr(Dreg_clr) ; ShifrRighr. The modu le con nects the Dreg .ld IDreg_ld); datapath 's DCTI'_elr and DClrJIII ) input to Dcrr's clear and count ); control inputs, respect.ively. The Figure 9.49 Structural Sy temC de cription of the cou nter's cou nt output C is then conlaser-based distance measurer' datapath. nected to the 16-bit intemal signal rempC that connects the count value to the ShifrRighr shifter'S input. The shifted count value i then connected to the input of the Dreg reg ister usi ng the intemal signal shijrC. The module connects the Dreg register's clear and load control inputs to the datapath's Dreg_elr and Dreg_Id input pons. Finally, the reg ister's data output Q is connected to LDM_darapalh's measured distance output D.
-'90
Hardware Description languages
9.5 RTl Design Using Hardware Description Languages
Figures 9.50 and 9.5 1 are the SysLemC descript ion of the laser-based distance measurer's FSl\'1 controller described in Figure 5.21. T he modu le, named LDM_Colllrolle r, has a clock input elk. a reset signa l rSI. a user-pressed bUllon in put 8, a laser sensor input S. and five output conLrol signals. L. Dreg_el,; Dreg_ld, Dell·_clr. and Dclr_clll . The output L is used to turn the laser on and off; where is L is 1, the laser is on. The fo ur other output signals are used to control the RTL des ign's daLapaLh components. .include "system.h anum statetype { SQ, 51, 52, 5). 54 }; SC_ MODULE (LDM_Controller) (
sc_ in elk. rst, B. S; sc_ out < sc_ logic > L;
se out Dreg_clr. Dreg_ld;
sc=out Detr_clr. Detr_ent; 8c_ signal. currents tate. nextstate; SC_ CTOR CLDM_ Controller) (
SC METHOD (statereg) ; se~sitive-P08 « rst «
elk;
491
sets the curren/state to the FSM 's initial state, SO. Otherwise, on the rising edge of Lhe clock, the process updates the SLate regisLer with the llextslOle. The second process, named eomblogie, is sensitive to the inputs to the combinaLional logic of Figure 5.21 , namely, the external inputs 8 and S, and the state regi ter output eurrelllstale. When ei ther of those signals change, the process sets the FSM 's outputs, in Lhis case L, Dreg_ell; Dreg_ld, DClr_c1r, and Delr_ClI/, with the appropri ate value for Lhe current state. In the controller example of Figure 9.24, the FSM's output x was defined wiLhin the case statement for all possible states. WiLh five ou tputs that we must define in Lhe LDM_Collllvller and fi ve possible states, assigning the values to all outputs in each state wou ld be cumbersome. Funhermore, finding a mistake and making corrections or mod ificati on to the controller would become very difficult in a larger FSM Con isting of more states and having many more outputs. Instead, the process uses a different approach in whi ch a default value for the all Outputs is fi rst assigned and only the deviation from the defaults are assigned later. The process first assigns a default value of 0 to all five outputs. The process then evaluates the current state and assigns the values to the outputs only when the output shou ld be I. The process also assigns the value 0 to several signals within the eose statements; however, Lhese assignments are included only to clearly indicate the behavior of the controller (Lhey are redundant, but help make the description eas ier to understand).
SC METHOD (comblogic) ;
se;;:sitive «
currents tate «
void statereg () { if ( rst .read (1 curren ts tate else eurrentstate
B «
S;
(continued from Rgure 9.50) caae Sl Octr_clr .write (SC_LOOIC_1); i f (B. read () == SC_LOGIC_ll nextstate S2; e18e nextstate 51;
==
SC_LOGIC_l 1 SO: II initial state
nextstate;
II clear count
break :
eaa. S2 : L. write (SC_LOGIC_l); nextstate .: S3;
void comblogic() { L. write (SC_LOGIC_OI ; Dreg_clr. write (5C_LOGIC_O) ; Dreg_ld .wriU (SC_LOGIC_OI; Detr elr. write (5C_LOGIC_0); Detr=ent. write (5C_LOGIC_O);
Figure 9.50 Behavioral SystemC description of la er-based distance measurer's controller.
caae S3: L. write (SC_UX;rC_O); Detr cnt. writ. (SC_LOGIC_l ) ; i f (S. read () == SCLOGIC_11 nextstate 54; e1a. nextstate = S3;
switch (eurrentstate) { case SO : L. write (SC_LOGIC_OI; II laser off Dreg_clr. write (SC_LOGIC_OI ; II clear Dreg nextstate .: 51; break ;
(continued in Figure 9.51)
The SystemC module behaviorally describes the ulse rDis lMeasllrer 's FSM. Sim ilar to the comroller design shown in Figure 9.24, the module consists of two processes, one modeling the SLaLe regi ter, the other modeli ng the FSM 's conLrollogic. The state reg ister process. named slolereg. is sensitive to the positi ve edge of the reset input . rSl, and the posiLive edge of the clock input, elk. If the rSI is enabled, the n the process asynchronously
II laser on
break ;
II laser off II count up
break ;
Figure 9.51 Behavioral SystclllC description of Inser-based distance I1lca~ urcr 's controller
caae S4: oreg_ld. write (SC_LOGIC_11; Detr_cnt. writ. (5C_LOGIC_O) ; nextstate = 51;
1/ load Dreg I I stop counting
break; } )
I;
(collfill"edj.
. what the next state should be_based on the current state Thc process also detmnme b d . 111e next st3te will be loaded into the taLe regisLer y and the values of inputs B an .. Lpo -ttlve lock edge. the statc rcgista process on th~ nex ,
-'92
9 Hardware Description Languages
9.6 CHAPTER SUMMARY In this chapter. we stated that hardware desc ription languages (HOLs) are widely used in modem d igi ta l des ign. We provided brief introductions to several wide ly used HDLs, namely. VHOL. Veri log and Systemc. We introduced those HDLs primarily through the use of examples. illustrating how each HOL might be used to describe combinational logic. sequential logic. datapath compo nents, as well as RTL behavior and structure. To become proficient at the use of HOLs, a more thorough study of a particular HOL might be helpful. This c hap ter a lso illustrates the po int that different HOLs have several commonona lilics.
9.7 EXERCISES The following exerc ises can be completed using any of the HDLs described in this chapter. SECTIO 9.2: CO IBINATIONAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LA GUAGES
9.1 Create a structu ral HDL description of the binary numbe r to seven-segment display described in Example 2.23. consisting of the simple logic gates. lllv. AND2, and OR2. Be sure to include combi national behavioral descriptions of the simple logic gates. 9.2 Create combinational behavioral HDL desc ript ions for each of the following two-input logic gates. where each logic gate has two inputs. a and h. and a single output F: (a) NAND2. (b) NOR2, (c) XOR2. (d) XNOR2. 9.3 (a) Create a combinational behavioral HDL description of the three Is pattern detector of Example 2.24. (b) Create a testbench that checks that your description works properly. 9.4 (a) Create a combinational behavioral HDL description of the Numbe r-of-ls counter shown in Figure 2.4 I, by describing the combinational behavior of both outputs x and y in sumof-minterms form. (b) Create a testbench that checks that you r descriptio n works properly. 9.5 Create an HDL description of the 2x4 decode r shown in Figure 2.50, as: (a) combi national behavior. (b) structure. (c) Create a testbench to test either description (the same testbench can test either description). 9.6 Create an HDL description of the 4x I mult iplexer descri bed in Figure 2.55, as: (a) combinational behavior. (b) structure. (c) Create a testbench to test either description (the same testbench can test either description).
9.7 Exercises ~ 493 9.7 Create a behavioral HDL description of a 2x I
multIplexor described in Figu re 2.54. Then. create a s lruc tur~J HDL description that combines
three 2x I muluplexors to create a 4x I multiplexor as shown 10 Figure 9.52. 9.8 Create a combinational behavioral HDL descriptIon . of an 8-bll 4x I multiplexor. Be Sure to specIfy the design input and output pons using a multIple bll data type. 9.9 Clearly ex plain the difference between a structural HDL description and a behavioral HDL description. Explain the benefits of using both klOds of descriptions. 9.10 Explain why a combinational behavioral HDL description must include all the combinational ci rcui.l's inputs in a sensitivity list. In particular.
4xl
~ iO - f- iO il - f - il
di \ sO
I
~I i2 -
iO
i3 -
it
d
U
s~
L
~ iO
d-
/ il
- d
,.....!!~
SI
Figure 9.52 4x I multiplexor composed of three 2x I mUltiplexor.;.
explatn why omitting an input actually descri bes a sequential circuit. 9.11 Create a behavioral HDL description of a 16x4 priority encoder. The priority encoder has 16 1OPUts, d l 5, dl 4, :... dl. dO, and four outputs e3, e2. el. eO. The priority encoder outputs a 4-bllblOary number IOdlcaMg whIch of the 16 inputs is a 1. If more than one input is a 1, the pnonty encoder will outpu t the bmary number for the highest numbered input. SECTION 9.3: SEQUENTIAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES
9.12 (a) Create a behavioral HDL description of a 32-bit parallel load register. (b) Create a testbench to test the description. 9. 13 (a) Create behavioral HDL description of the FSM controller for the improved code detector described in Figure 3.46. (b) Create a testbench to test the description. 9.14 (a) Create a behavioral HDL descri ption of the button press synchronizer described in Fieure 3.53. (b) Create a testbench to test the description. 9.15 (a) Create a behaviroal HDL description of the secure car key controller described in Figures 3.57 and 3.58. (b) Create a testbench to test the description. SECTION 9.4: DATAPATH COMPOl'l'ENT DESCRIPTION USL'iG HARDWARE DESCRIPTION LANGUAGES
9. 16 (a) Create behavioral HDL description of an 8-bit parallel load register with register clear input e1r. (b) Create a testbench to test the description. 9.17 (a) Create a behavioral HDL description of an 8-bit parallel load register with a clear 10\\ input cJr_1 and a set high input s~l_h. When the e1r.) input is 1. the register contents should be cleared to "00000000 . When the stU, IOputs IS 1. the registers contents should be set to "11111111". If both inputs are I. the lear low input has priority. (b) Create a testbench to test the description.
-
--
-19-1
Hardware Description Languages 9.7 Exe rcises 9.18 Create a behavioral HDL descriptio n of an 8-bit register with IwO control inputs sO and sl wi th the following control behavior described in Figure 9.53.
9.19 Create a structura l HDL descri ption of a half-adde r. 9.20 Create a structural HDL description of a 4-bit carryripple adder wi thout a carry input. First create a
behavioral description of a fu ll-adder, and then use the fuJI-adder component in your carry-rippl e adder description.
sl 0 0
sO 0 1
0
Operation Maintain present value
Parallel load Shift right Rotate right
Figur. 9.53 Operation table of the S-bit register fo r Exercise 9. IS.
9.21 Create a behav ioral HDL descripti on of th e approxi lllnte Celsius- to-Fahrenheit convener
described in Figure 4.40. 9.22 Create a behavioral HDL description of an approx imate Fahrenheil-lo-Celsi us converter using
the following approxi mation for the conversion: C ;
the time as a 10-bit binary numbe . Ore the user presses the button B. outputting r on rtlme. if the user did l . L. b . . I second (1000 milliseconds) the react" . . no press ",e utton Wtthln on rrill/e. Assume a clock fre~uency or'~n~~mer wlil set the output slow to 1 and output 1000 level state machine in an HDL (b) C z. (a) Start by captunng the design using a highpath descripti on in an HDL.
·
onven the high-level state machine to a controUer/data-
9.35 Starting from the C description shown in F 9 Common Divisor (GCD) calculator that tak::~ein:u~' t:~a:~ ~t RTL design of a Greatest d input go, and a 16-bit output D. When the go is '1' the GC~' ;np~ts a an h, an enable greatest common di visor and output the GCD on th." output D Scta cu atohr whlil cholmpute the h"
HD
.
while ( a
! = b )
ifla>b)(
9.25 Create a structural HDL description of th e up-dawn-coun ter circui t described in Figure 4.55. Be sure to firs t creme a behavioral HDL description of each component used in your structural
b = b - a;
HDL design.
a = a - b; else (
return(a) ;
9.26 Create a structural HDL descriptio n of a 4-bit down-cou nter with parallel load. Be sure to first create a behavioral HDL descripti on of each component used in your stru ctural HDL design.
9.27 Create a structural HDL descript ion of the RGB to CMYK conve rter described in Figure 4.68. Be sure to first crea te a behavioral HDL description of each component used in your structural
HDL design. 9.28 Create a structu ral HDL description of a CMYK to RGB converter. Hint: Use the information presented in Example 4.20 desc ribing the RGB to CMYK conve rter to assist in designing the CMYK to RGB converter. 9.29 Create a structural HDL description of a 4-bit adder/subt.ractor circuit. Be sure to first create a behavioral HDL description of each component used in you r structural HDL design. SECTION 9.5: RTL DESIGN USING HARDWARE DESCRIPTION LANGUAGES
9.30 Create a behavioral HDL description of the high-level state machine for the simple bus interface shown in Figure 5.24. 9.31 Create a structural HDL description of the controller/datapath for si mple bus interface shown in Figure 5.26. 9.32 Create a behavioral HDL description of the high-level tate mac hine for the sum-of-absolutedifferences component shown in Figure 5.29. 9.33 Create a structural HDL description of the contro ller/datapath design of the sum-of-absolutedifferences component shown in Figure 5.30. 9.~
a
~int GCD(uint a, uint b) II not quite C syntax
Create a behavioral HDL description of a 32-bit equality compara tor with three 8-bit inputs a, h. and c.
9.2~
an W it
Create an RTL design of a reaction timer circuit that measures the time elapsed between the illumination of a light , and the pre sing of a button by the use r. The reaction timer has three input" a clock input elk. a reset input rst. and a button inpu t B. and three outputs. a light enable output lell. a IO-bit reaction time outpu t rt;me. and a .'ilow ou tpu t ind icating the user was not fast enough. Th e reaction timer works as follows . On reset. the reac tion timer wa its
for 2 seconds before illuminating the light by ;elti ng lell to l. The reaction limer then
Ig -
evel state
mllac I ~e. In an I L. and then create an HDL implementation with a datapath controller and a thclr Intema components. . ,
(F - 32) /2 .
9.23 (a) Create a behavioral HDL description of a I-bit comparator. (b) Create a structural description of a 4-bit comparator. using the I-bit comparators.
495
measures the length of lime in milliseconds be~
Figure 9.54 C program description of a greatest common divisor calculator.
A.2 Switching Algebra 4 497 (i) a + (b . c) = (a + b) . (0 + c) (ii) a . (b + c)
A
= (a . b) + (0 . c)
P3: The set B has two disti nct identit ele y ments, denoted as 0 and I, such that for every element in B (i) 0 + a
(ii) I . a
Boolean Algebras
=a +0 =a =a. I =a
The elements 0 and I are called the additive' d n I 'd n I . I en t ye ement and the multiplicati ve t en t ye ement, respecti vely. (These elements should t b f . . no e con used wl Lh the Inte· gers 0 and I.) P4: For every element " e B there exists an element a' called th I f a, such that . e comp ement 0
This appelldix is reproduced lVilh permissioll from Ihe l exlbook " IIlIIVduClioll 10 Digita l Syslems" by £rcegolloc. Lallg. alld Morello, ISBN 0·471-52799-8, Johll Wiley alld SOilS
(i) a+a' = I
publishers, 1999.
(ii) a · a' = 0
Boolean algebras is a n imponant class of algebras that has been studied and used extensively for many purposes (see SecLion A.5). The switching algebra , used in the description of switching expressions discussed in Section 2.4, is an instance (an element) of the cia s of Boolean algebras. Conseque ntl y, theorems developed fo r Boo lean algeb ras are also applicable to switc hing algeb ra, so they can be used for the tra nsfo rmati on of switching ex pressions. Moreover, cenain ident iti es from Boolean algebra are the basi s fo r the graphical and tabular techniques used for the minim ization o f swi tching ex pressions. In this appe ndix. we present the definition of Boo lean a lgebras as we ll as Lheorems that are use ful for the Lransformation of Boolean expressions. We also show the re laLionsh ip among Boolean and switching alge bras; in panicular. we show tha t the sw itching algebra satisfies the postulate of a Boolean algebra. We also sketch othe r examples of Boolean algebras, which are helpful to funher understa nd the propenies of this class of algebras.
A 1 BOOLEAN ALGEBRA A Boolean algeb r a is a tuple {B. +, . }, where
B is a et of elements:
+ and . are binary o perat ions applied over the elements of B, saLi sfyi ng the following postulates:
. The symbols + and • should not be confused with the arithmetic addition and multi. pltcatlOn sym b~ls. However, for convenience + and · are often called "plus" and ·'times.'· and the expressIons a + b and. a· b are called "sum" and "product ,,. respecuve . Iy. M oreover, + and · are also called "OR" and " AND," respectively. The elements ~f the set B are called constants. Symbols representing arbitrary elements of B are variables. The symbols a, b, and c in the postulates above are variables. whereas 0 and I are constants. A precedence orderin g i defi ned on the operators: • has precedence over +. therefore, pare ntheses can be eliminated from product . Moreover, whenever single symbols are used for van abies. the symbol · can be eliminated in products. For example. a + (b· c) can be written as a + bc
~
A.2 SWITCHING ALGEBRA Switching algebra is an algebraic system used to describe swi tching functions by means of switching expressions. In this sense. a switching algebra serve the same role for switching func tions as the ordinary algebra does for arithmeLic functions. The switching algebra of the set of two elements B = {O. I}. and two operations AND a nd OR defined as fo llows: AND 0
o
0
OR
0
o
0
o
PI: If a, b e B, Lhen (i) a (ii)
+b= b+a
a .b = b .a
That is, + and · are commutati ve. P2: If a, b. c e B. then
496
These operation ' are used to evaluate switching expressions. as indicated in ;,cuon ~.-I . T heorem I The switching algebra i a Boolean algebra. Proof We how that the switching algebra saLisfies the postulate of a B
lean al"ebra.
-'98
A Boolean Algebras A.3 Important Theorems in Boolean Algebra • 499 PI: Commutativity of C+). C, ). Thi s is shown by inspect ion of the operation tables. The commutativi ty property holds if a table is sym meLric about the main diagonal.
Theorem 2 Principle of Duality Every algebraic idenLity deducible from th if e postulaLes of a Boolean algebra remains valid
P2: DistributivUy of (+) and (' ). Shown by perfect induction. thaL is. by considering al l poss ible values for the elements 0 , b, and e. Consider the fo llowing table: abc
a
+ be
(a
+ b)(a + c)
000
0
0
00 1
0
0
010
0
0
011
I
I
100
I
I
101
I
I
11 0
I
I
II I
I
I
Lhe operati . . ons + and· are interchanged Lhroughout; and Lhe IdentIty elemenLs 0 and I are at so mterc · hanged throughout Proof The proof follows at once from Lh f h anoLher one (Lhe dual) that is obtai ned by . ~ acht L at for each of the postulaLes there is m erc angmg + and . as well as 0 and I . Thi s Lheorem is useful because it reduces the nu be f . be proven: every theorem has its dual. m r 0 dIfferent Lheorems that must Theorem 3 Every element in B has a unique complement. Proof Let a E B ; let us assume that a' I and a' 2 are bOlh complements of a. Then. . uSlOg the postulates we can perfonm the following transfonmaLions: a' t = a 'i' I
= a']
Because a + be = (0 + bleb + e) for all cases. P2(i) is saLi sfied. A similar proof shows that P2(ii) is also saLisfied. P3: Existence of additive a nd multiplica ti ve identi ty element . From the operation Lables
by P3(ii)
+ a'2)
(identity)
by hypothesis (a'2 is the complement of a )
a + 0 '1 . 0'2
by P2(ii)
(distributivity)
=a . a'i + 0'1 . 0 '2
by PI (ii)
(commutativity)
= 0 + a'l . a'2
by hypothesis (a'i is the complement of a)
= a'i . 0'2
by P3(i)
=
0+ 1=1+ 0=
. (a
0 '1 .
(identity)
Therefore, 0 is the additive identity. Similarly 0 · 1 =1 · 0=0
Changing the index I for 2 and vice versa, and repeating all steps for a' 2' we get 0'2 = 0 '2' 0'1
so that I is the multiplicative identiLY·
= a'l
P4: Existence of the complement. By perfect inducLion: and therefore a' 2
. a'l
by PI (ii)
= a'i .
a a' o +a' (J-a I
0
I
0
0
J
J
0
The uniqueness of the complement of an element allows considering operation called complementation.
Conseq uentl y, I is the complement of 0 and 0 is Ihe complement of I.
Theorem 4 For any a E B:
Because all postulates are saLisfied , the sw itchi ng algebra is a Boolean algebra. As a result. all theorems true for Boolean algebras arc also true for the switching algebra.
2. a · 0
l.a+ l=
Proof
A.3 IMPORTANT THEOREMS IN BOOLEAN ALGEBRA We now present some importam theorems in Boolean algebra; these theorems can be applied to the lran,forma tion of sw itching expressions.
=0
Using the postulates. we can perfonm the following rransfomlations:
as a unary
SOO
A Boolean Algebras A.3 Important Theorems ,n Booloan Algobra
b) a+1 = I · (11+ I )
P·l(i)
=
P2(,)
(I
+ (a'· I)
=a+a
P3(II)
= I
P-l(,)
C"," (2): a
PJ(i,)
= (11+11') (II + I )
0+«(1 · 0)
0
(II
=
1I
=
1I
(1')+(11 0)
(a')' = tl Proof From the defi nili n f no !cmelll " by Theorem 3. Ihe complement of p I (II) ,ond (J arc bolh coonpl 'l1\ nh of II ' • OUI. nn c eonenl " un'que. "h,eh prove.' Ihe Ihcorelll . Theorem HAbsorption Law For every pair f elemen15 a. b E B.
by
1.(I+ o · b=o
P3(i)
2. (I · (a+b)
P-l (II)
(11'+0)
P2(II)
II'
1'3( ,)
=a
Proof ( I ):
b (I
+ ab = lI ' I + tlb
P4 (,i )
= 0
=a( I + b)
C '.' e (2) can al,o be proven by me:,," of en,e ( I ) and the principle of dualil) . Theorem 5 The complemenl of Ihe clelllent I i, O. and vice \er;J. That ". I. 0'
2. I '
=I =0
SO l
Theorem 7 Involulion La" For every a E 8 .
P3(i ,)
1'2(i ,)
= a(b+ I )
PI(i)
= (1· 1
Theorem 4 ( I )
=
P3(ii)
1I
(2): dualilY
T heorem 9 For every pai r of elemenls a, b E 8.
I'roof Oy Theorelll 4 . 0+ 1 = I and
O· I = 0
J. (I+o ' b = (I+b 2. o(a' + b)
Because. by Theorem 3. Ihe complement of an elcment is unique. Theorem 5 follows .
= ab
Proof ( I ):
Theorem 6 Idem polen I Law For eve ry a E B
by a+a ' b
I. a+a = (I
2. o · (I = a
= (a +lI')(a+b )
P2(i)
= I · (a +b) =a +b
P3(ii)
P4(i)
Proof ( I ):
by 0+0=(0+0)· 1 = (a+o) · (a+a')
(2) : dualily
P3(i i) P-l(i)
= ( a + (a . a'»
P2(i)
=a +O
P4(ii)
=0
P3(i)
(2): dualilY
Theorem 10 In a Boolean algebra, each of the binary operalions (+ ) and (. ) is associalive. ThaI is. for every a, b, e E 8 , I. a+(b+e) = (a+ b)+e
2. a(be)
= (ab)e
The proof of this Iheorem is quile lenglhy. The interesled reader should consult Ihe further read ings suggesled al Ihe end of Ihis appendix.
.. •t
11
B d i Ion I u r1 b S
In
[XAMPLE B 1 (\'II\l'll Ih,' 1I11111"'r
I II ,,'r-llll 11 thl
,.
,.
pomt to re~nt the number In a tinHe number of bl~ auJlablc III
need to be truncated and the b1n.wy
y
508
B Additional TopIcs In Binary Number Systems
B.4 Floating Point Representation
B.3 FI XED POINT ARITHMETIC If " e tix the bi nary point of a real number in a certain posiI I I I tion in the number (e.g .. after the -lth bit). we can add or 00 1 subtrac t binary real number by treating the numbers as inte111 + 00 1 gers and adding or subtracting normally. In the resulting sum 1 1 ° 1 . °°°1 or differen e. we maintain the binary point's positi on. For examp le. a!.sume we are worki ng with S- bit numbers with figure B.4 Adding two half of the bits used to represent the fract ional part of the (i x"d poinl numbers. number. If we wat1led to add 1001. 00 10 (9. 125) and 0011 . 1111 (3.9375). we can simply add the two number a if thev were it1le2ers. The sum. shown in Figure B.4. Can be converted back to a rea l numb~r by maint;ining the binary poit1l's posi ti on within the sum . Converting the sum to decimal verifies that the calcul ation was correct: 1*23 + 1*22 + o*i + 1*20 + 0*2. 1 + 0*2" + 0*2.3 + 1*2-4 = 8 + 4 + I + 0.0625 = 13.0625. Multiplying binary real numbers is also straightforward 01.10 and does not require that the binary poit1l be fixed. We first x 1 1.0 1 multiply the two num bers as if they were integer. Second. we 1 1 place a binary point in the product such that the precision of the ° ° ° ° product i the sum of the prec isions of the multiplicand and 1 1 + 1 1 multip lier (the two numbers being multiplied). just like what is 1 00 . 1 1 1 done when we multiply twO decimal numbers together. Figure B.5 shows how we might multiply the binary numbers 01.10 figure B.5 Multiplying ( 1.5 ) ard 11.0 1 (3.25) using the partial product method 111'0 fixed poinl numbers. described in Section 4.7. After we calculate the product of the two numbers. we place a binary point in the appropriate location. Both the multiplier and multiplicand feature two bit. of precis ion. therefore the product must have four bits of prec ision. and we insert a binary point to reftect thi s. Convening the product to deci mal veri fie that the calculation was correct : 0*23 + 1*22 + 0*2 1 + 0*20 + 1*2. 1 + 1*2" + 1*2.3 + 0*2-4 = -l + 0.5 + 0.25 + 0. 125 = 4.875. The pre"i ou, examp le was convenient in that we never had to add four Is 1110.1 multiplicand IOgether in a column when we summed up x 1 1 1.1 multiplier the pani al product; . To make the caleula1 1 101 pat1ial product 1 (ppl) + 11101 pp2 lions simpler and to all ow for the partial 1010111 ppshppl+pp2 product ; ummation to be implemented +11101 pp3 u> ing full -adder,. which can onl y add three 71 -71";0'-:0:-'1:-0::-:-1-=-1- pps2 ; pps 1 + pp3 I , at a time. we add the pani al products :;:+..;.1-,;1,..;1,..,0;.-;,.1"...,-..,-_pp4 1 1 0110011 pps3 ; pps2+pp4 incrementally in>tead of all at once. For ;,-+-7°.0;°,-;°;-:°",,°;-;;--;;-;..,-_ pp5 exa mple. let\ multiply 1110 . I ( 14.5) by 01 101 100.1 1 product; pps3+ pp5 (C' III . I ) 7.5. A ~ , een in Figure B.6. we begtn by generattng panial products as we Figure B.6 MultIplying IWO fixed poinl did earlier However. we add partial prodnumbe" u,ing inlCrrl1cdtnlc partial product'. Utt; Immed iately Into p,lnial prod uct ~um>. labeled PI" In the fi gure. Eventually. we "ind that the product i, 0110 1100 . 11, whi h corre'JlIlI1d, to 'he correct an >wer. 108.75. You may want to try adding the five partial
°
°°
°
°
° ° °° °°
°
509
products together at once instead of using the intermediate panial product sums to see why this method i useful. Before proceeding to binary real number division, we will introduce binary integer division. which was nOl discussed in previous chapters. We can use the familiar process of long divi· sian to di vide two binary integers. For example, 1 1 1 quotient consider the binary division of 1011 00 (44) by divisor 1 Ojl 01 10 dividend 10 (2). The full calculation is shown in Figure B.7. NOlice how the procedure is exactly the 1 same as decimal long division except that the -0 numbers are now in binary. 1 1 Dividing binary real numbers, like multipli-1 cation, also does not require that the binary point 1 be fixed. However. to simplify the calculation, we ~ shift both the dividend and divisor's binary point right until the divisor no longer has a fractional -0 pan. For example. consider the division of 1 . 01 2 o remainder ( 1.25) by 0.1 2 (0.5). The divisor. 0 . 12' has one digit in its fractional pan. therefore we shift the Figure B.7 Dividing Iwo binary dividend and divisor binary points right by one integers using long division. digit. changing our problem to 10. I, divided by 1, . We now treat the numbers as integers (ignoring the binary point) and can divide them u ~ing the long division approach. Trivially. 101 /1 2 is 101 2 , We then restore the binary poin7 to where it was in the dividend. giving us the answer 10 .1 2 or 2.5. Why does shifting the binary pomt not change. the. answer? Ln general , hifting the radix point ri ght by one digit is the sam~ a . multlplymg the number by its base. For binary numbers. shifting the binary pomt rtght IS equivalent to multtplytng the number by 2. Dividin o twO numbers will give you the rallO of the two numbers to each other. Multiplying the~wo numbers by the same number (by meansof ~hifting the binary point) will nOl affect that ratio. since doing a IS equivalent to muillplytng the ral10 by I. Fi 'ed point numbers are simple to work with. but are limited in the range of numbers that they can represent. For a fixed number of bits. tncreastng the preci ion of a number comes at the ex pen e of the range of whole numbers that we can use. and vice versa. Fixed point numbers are suitable fo~ a variery of appltcan~n~ ,. uch as a digital the~om eter. but more demanding appllcaltons need greater ftextblhty and range in tbetr real
° °°
~tJ ° °
°
°
° °°°
number repre~e ntation . .
B.4 FLOATING POINT REPRESENTATION \ hen " orking "ith decimal numbers. we often ~.present vcry large or very small ~c I' clllific n tation. Rather than wntmg a googol as a I with a hundred numbers by t"lng o . f' . '" c~uld "rite 1.0' JOI!Xl. Ins~ead of - 99.79 _A - m/s. we could write the , ,I tcc II. C S • 1 99 ' 10' or even 299. * 10". , 'cd of light u, .1.0*10 m/, . as - ' ' . , pe . ' . Id be transl3ted into btnary. we would be able to tore a mu h II <11 h nOllltlon (au . ' , fi . be urlll if the bm~ POlllt "ere xed. What feature of thiS notagrealcr range! of ntlm
lion need
I\)
~.
be l·:tptured In
• . .
:1
blnar) rep
re entari n'!
510
B Additional TopIcs in Binary Number Systems
B.4 Floating Point Representation
--'"
First is the whole and fractional pan of the + 3.0 * 108 number being multipl ied by a power of 10. which is called the malllissa (or sigllificalld). as shown in \ \ exponent Figure B.. We do not need to store the whole pan sign mantissa base of the number if we make sure the number is in a cenain fonn . We call a number wrillen in scientific Figure B.B Parts of a number in notat ion lIormali:ed if the whole part of the scientific notation. number is greater than 0 but less than the base. In the previOl;s speed of light examples, 3.0* 10 8 and 2.998* IOs are norma li zed since 3 and 2. respectively. are greater than zero but less than 10. The number 299.8* 106• on the other hand , is nOl normalized. If a binary real number is nomlali zed. then the whole part of the manti ssa can onl y be a 1. To save bits. we can assume that the whole pan of the significand is I and slOre onl y the fractiona l pan . econd is the base (somet imes referred to as the radix) and the exponent by which the mantissa is multiplied. shown in Figure B.8. Calling 10 the base is no accident- the number is the same as the ba e of the entire number. In binary. the base is naturally 2. Knowing thi s. we do not need to store the 2. We can simply assume that 2 is the base and SlOre the exponent. Th ird. we must capture the sign of the num ber.
;
I
2. If the mantissa bits are nonzero, then the number is nOl whole pan of the mantissa is a binary zero and not a one
I· .
.
.
~:,~~I~z:~i ~at
. IS, the
When the exponent bits are all 1s, two possibilites occur: I. If the ~ a nti ssa bits are all as, then the entire number evaluates t
a + or
dependmg on the sign bit.
_ . fi . m , mry,
2. If the manti ssa bits are nonzero then the emire " b r" . . number (NaN). ' , num e IS clasSified as not a . There are also speci fi c classes of NaNs, beyond the scope of tho used in computations involving NaNs. tS appendtx, that are Wi th this we can conven decimal real numbers ta ft oatmg · pomt . num. information, . bers.. Assuming the' deCimal number to be convened is not a spect'al vaIue In ., fl oatIng ' . pomt notation, Table B.2 descnbe how to perform the conversion. TABLE B.2 Method for converting real decimal numbers to floating point
The IEEE 754-1985 Standard The Institute of Electrical and Electronic Engi neers (IEEE) 754- 1985 standard specifi es a way in which the three values described above can be represented in a 32-bit or a 64-bit binary number. referred 10 as single and double precision. respectively. Though there are other way to represent real numbers. the IEEE standard is by far the most widely used. We refer 10 these numbers as f/oa tillg poillt numbers. The IEEE standard a signs a o cenain range of bits for each of bit l31 130 129 1. 124 123122 121 the three val ues . For 32-bit numLSi-g-n-'-......J-e-xLp-o-n-e.Lnt-..J...-L......J.-m-'a-n-t~is-s... a-L...-' bers. the fi rst-most significantFigure B.9 Bit arrangement in a 32-bit Hoating point bit >pecifie; the sign. followed by number. bit for the ex ponent. and the remaining 23 bits are ued for the mantissa. Thi arrangement is piclUred in Figure B.9. The sign bit is set to 0 if the number is positive. and the bi t is set 10 I if the num ber is negative. The mantiCu,'>Cd In Section 4.8)? Becau,e itlUms out thai biasing the exponent resulL< in impler circuitry for cornpanng the magnilUde (absolute value) of IWO noming poinl numbers.
511
The IEEE standard defines cenain special values if the . are u",form. When the exponent bits are ali a ' . contents of the exponent bits s, two poSSibilities occur: I. If the mantissa bits are all as then the ent'Ire nurn be r evaluates to zero
2
3
Step
Description
Convert the 'Illmher from base 10 to base 2.
Use the melhod described in Seclion B.2.
COIwert 'he "umber 10 1lormali:ed scientific notatioll. Fill ill the bit fields.
Initially multiply the number by i'. Adjust the binary point and exponent so that the whole part of the number is I,.
Set the sign. biased exponent. and mantissa bits
appropriately.
EXAMPLE 8.2 Converting decimal real numbers to floating point Conven the following numbers from decimal to IEEE 754 32-bit floating point: 9.5. infinity. and -52406.25 • 10". Let's follow the procedure in Thble B.2 to convert 9.5 to. floating point. In tep L we COm'en 9.5 to binary. Using the subtracuon method. we find that 9.5 IS 1001 . 1 in binary. To com-en the number to scientific nototio~ per "';I' 2. we muluply the numbe: by 1'. giving 1001.1 • _0 (for readabilit), purposes. we WIlte the 2 pan In base 10). To nonnahze the number. we must shift the binary poinl left by three digilS. In order to not change the value of the number after movino the binary point. we change the 2's exponent t.o 3. After step 2. our number becomes 1 _00 11 • } In step 3. we put everything together Into the properly fonnalled sequence of bits. The ion bit is set to O. indicating n positive number,.The ~~"(ponent bits are S~l t~ 3 + 127:: I ' '0 (we must bi:s the exponent) in bina,). and the mantissa bllS areset to 0?11 ". which IS.the fra tional part of the manti>sa. Remember that the 1 to the left of the blnar)' pomtlS Imphed In e the number is normalized. TIle properly encoded number is hown m Figure B.IO.
rna-
511
B AdditIOnal TopICS in Binary Number Systems B.4 Floating Point Representation Nm\ let':, conven infi nity 10 a Step 1: Conven to binary Hoallng po lill number. Since infinity 9.510 <=> 1001.1 2 IS.I special \alue. \\c cannol employ the method" e used 10 om'en 9.5 10 Step 2: Conven to normalized scientilic notation 1001.1 <=> 1001.1 • 20<=> 1.0011 ' 2 3 floaling point. Rather. we 1111 in Ihe three bit Iklds with :,pcc ial values indicating tha t the num ber is infinit y. To normalize. move binary From the discussion of spec ial values point 3 digits left & add 3 to exponent abo\c. we know th at the exponent bits shou ld be all Is and the mantissa bits should be aliOs. The sign bit shou ld be 0 since infinity is positive. Therefore. the equivalent fl oating poin! number is 0 11111111 .Q. 10000010 00110000000000000000000 mantissa sign exponent 0000000000000 0000000000 . 2 (biased) Conven ing -52-l06.25 ,. 10to floating poin t is stra igh tforward Figure B.l0 Represenling 9.5 as a 32-bit Roating point u,ing the method in Table B.2. For number. most significant bit first. step I . \..'e conven the number to binary. Recall that we represent the sign of the number using a single bit and not using two's complement representation. so we only need to com'en 52406.25 * 10" to binary and set the sign bit to indicate that the number is negative. The number 52-106.25 * 10" evaluates to 524.0625. Using the subtraction or divideby-2 method we know that 52-1 i 1000001100 in binary. The fractional part. 0.0625. is con\'eniently 2-<. Thu 52-1.0625 is 100000 11 00 . 0001 in binary. In step 2. we write the number in scientific notatio n: 1000001100 . 0001 * 20. We must also normali ze the number by shifting the binary point left by 9 digits and compensating for thi s shift in the exponent: 1 . 000001 100 000 1 * 29. Finall y. we combine the sign ( I since the original number is negative). biased exponent (9+ 127= 136). and fractional part of the mantissa into a noating point number: I 1000 1000 00000110000010000000000.
~
Step::;~
EXAMPLE B.3 Convertm g floating pomt numbers to decimal Comen the numbe r 1 100 10 11101010100000000000000000 from IEEE 754 32-bi t fl oating point (0 decimal. To perform thi ~ conversion. we first split the number into its sign. exponent. and mantissa pan.<: I 1001011 1 0 1 010100000000000000000. We can immediately see from the sign bit that the number is negative. Next. we convert the 8-bi t ex ponent and 23-bi t manti ssa from binary to decimal. We find that 1(1)101 I I IS 151. We unbi as the ex ponent by subtracting 127 from 151. givi ng an unbiased exponent of 24. Recall tha t the mantissa in the pattern of bits represen ts the fractional part of the manu"a and I< 'tared Without the leading 1 from the whole part of the manti ssa (assuming the oTl glnal number wa, normalilOd). Restorin g the I and adding a binary point gives us the number J.f)JOIOI()()()()(){)OO(. whic h is the ,arne number as 1.010101. By applying weig hts to each di git. "'. ,ee that 1.010101 = + 0*2" + 1*2.2 + 0*2'] + 1*2-< + 0*2' s + , . 2.6 = t ]2~ 12 5 Wi th the oTlglnal Ign. exponent. and mantissa ex tracted. we can combine them into a single numlle r - I 327125 • 2". We can multiply the number out to -22.265.462.784 . which is equivalent tll -2221)5-162784 If)'
The form at for double preci sion (64- bit) floating point numbers i similar, with three fields having a defined number of bits. The first mo t significan! bit represents th~
1
I· ..
Iso I.
513
I 1
bil [ 63 62 161 1 53 152151 ··1 1 0 Sign exponent mantissa Figure B.ll B" number. II arrangement in a 64-bit Roating point
sign of the num ber. The next I I bits hold the biased exponent and the remaining 52 bi hi ' . ts 0 d the fractIOnal pan of the mantissa. AdditIOnally. we add 10?3 to th exponent. This arrangement is picl~red in ;i:~:~e~: . Instead of 127 to form the biased F loaling I'oi nt Ari th metic . . Floating poin! arithmelic is beyond the scope of this text, but we'l vtew of the concept. Wt I prOVIde a bnef overFloating poin! addition and subtraction must be performed b fi " fl oating point numbers so that their exponents are I F Y rst aitgllmg the two the two decimal numbers? 5?* leY + I 44* 10' S. equa. Or example, consider adding -. . . Ince the exponents d ''''' h 2.52 * 10 2 to 0.0252* 10" Adding 0.0252* 10' and * ' IlIer.we canc ange 10 gIVes us the answer I ..46 )-2* 10' . S·Iml'1arl y, we could have changed 1.44* I 0' 1.44 t 144* 0 2 . o > * ' . 2 0 I . Addm 144* 10-and 2.52 10- gtves us the sum 146.52*10. which is the sarne be 0 I " num r as our first set of calcu. IatlOns. An ana ogous situatIOn occurs when we work w'th fl ' . o~ung PO'"t num~rs. Typicall y, hardware that performs Hoating poin! arithmetic O'ft . . '11 d" ' en re.erred to as aJWatmg pO/l11 1/1111. WI a Just the manttssa of the number with th all '. e sm er exponent before . . addtng or subtracting the manussas (with their implied I s res d) . . tore to ooether and preservtng the common exponen!. Notice Ihat before the addition or subtraction is performed. the exponents of the two numbers are compared Th' . . .. " . . tS COmpanson tS facilitated through the us: of Ihe sIgn bit and the biased exponent as opposed to re reseorino the exponen t In twO s complement form. p e . Multiplication and division in Hoating point require no uch alignments. Like in deCimal multiplication and d"" ton of numbers in scientific notation: we multi I or divide the mantissas and add or subtract the two exponent depend ' th pY . . . mg on e operauon. When multIpl ying. we add exponents. For exao:ple, let's multiply 6.-14* 107 by 5.0* I 0-3. Ins tead of trying to multiply 6-1.-100.000 by 0.00). we mUltiply the two m U· a th 644*- O ' 32? . an ssas tO"e er a nd add the exponents. . ). IS . - and 7+(-3) tS -I. Thus the answer is 3_.2 * 10'. \ hen di\ iding. we subtract the exponent of the e1ivi or from the e1i\ 'd d' . d' 'd 3 1 - * 10'" (d" d d) I' ~ en exponenL For example. let s IVI e . ) tVI en by 2.0' 10- - (divisor). D ' v'di 031 - b b . h d" , I I n_ .) y 2.0 g ives us 15.7) . u tmctlng t e _1\' tS~r S e>;ponem from the dividend's- gives us - 1-{- 12)=8. Thus the an wer IS 15.7) * 10 . Floating point divi ion defines ";ults for several boundary Ilses u~h as d,vtdlng by O. \~hich evaluates to po iti"e Or negative infinity. depending on the ~ tgn of th.e diVidend. Dlvtdtng a nonzero number bv infinity is defined :l, O. othet'\\ ise d,vldmg by tJlfimty tS -
,·za
•
514
B Additional Topics in Binary Number Systems
B.5 EXERCISES SECTION n.2: REAL 'UMBER REPRE ENTATION I.
Convert the following nUl11bcr~ from decimal
(0
binary:
1.5 (b) 3.125 (c) 8.25 (d) 7.75 (a)
2.
Convert the following numbers from decimal to bi nary: (a) 9.375 (b) 2.4375
Extended RTL Design Example
(c) 5.65625
(d) 15.5703 125 SECTION n.3: FIXED POINT ARITHMETIC J.
Add Ihe fo llowing IWO un;igned binary numbers u ing binary addition and convertlhe result to dec imal:
1011 1. 001 + 1010.110 (b) 01101 . 100+10100 . 101 (c) 10110.I+llO . Oll (d) 1101. 111 + 10011 . 0111 (a)
SECTION B.4: FLOATI G POINT REPRESENTATION ~.
Convert Ihe foll owing decimal numbers to J2-bil noating point: (a) - 50.208 (b) ~2A27523 · 10' (c) - 24.55 1.152 · 10'"
(d) 0
5.
Convert the follow ing 32-bit naming point numbers to decimal: (a) 010011000101 10110101 100001011 000 (b) 01001100010110 11 0101001000000000 ~) 01111111111000 11 00000000000 00000 (d) 01001101000 110101000101000000000
C.l INTRODUCTION In Chapter 5, we performed RTL design of a soda dispenser processor. We ,tuned with a high-level state machine, created the datnpath's structure, and then described tile o ntroll er using a finite-state machine. We did not further design the controller to s!nle turc. as such deSign was the subject of Chapter 3. and we did not wish to clutter hnptcr S"S RTL design discussion with too many details of previously learned material. In thi s appendix , we'll complete the RTL design by designing the controller's F M down to a state register and gates, resulting in a complete custom-processor implementation of u controll er and a datapath. We'll then trace through the behavior of the complete implementation. The purpose of demonstrating this complete design is to give the reader a clcar understanding of how the controller and datapath work together. The block symbol for the soda dispenser processor appears in Figure C. I. Recall thut the soda dispenser features three inputs, c. S, and a. The 8-bit input S represents the cost of each bOltle of soda. The I-bit input C is 1 for one clock cycle when a coin is inserted. Addi8 tionally, the value on 8-bit input a indicates the value of the coin that was inserted. The soda disSoda penser features one outpUt, d, used to indicate dispenser when soda should be dispensed. The I-bit processor output d is 1 for one clock cycle after the value of the coins inserted into the soda dispen er is Figure C.l Soda dispenser greater than or equal to s. The soda dispenser block symbol. does not give change. In Chapter 5, we developed the high-level state machine seen in Figure C.2. We s ubsequently decomposed the high-level state machine into a controller (repre ellled behaviorally as an FSM) and datapath, shown in Figure C.3. The datapath supports the data operations necessitated by the high-level state machine. includtng res~tung the value of ror (ror =0 in the Illir state), comparing if ror is less than S (for the tran~'t'?ns from the Wair state), and adding lOr and a (in the Add tate). The controller FSM IS slmtlar to the SIS
maw
516
Extended RTL Design Example hi gh-Ieve! qate machine. but " modified to control the d.llapath and accept ,wtu, Input from the datapath (I e. to t i t , ) rather than perfonlllng d:lw opcraW)ll' t1irectly. The controller and dawpath arc ,hown In h gu re '.3.
Input c (bfls). a (8 bfls). s (8 bits) OurputS' d (bll)
Local reg/siers
lot (8 bits)
C2 DeSigning 1/10 SOds Olspln 01 Controller SI7 Encode the tate . . 0 slr:ughtfoN nrd en,ndl frill : O. IInit: 0 I. dd. 10. and DIJp: II nil 0' the ""'.1 .11'1 'II'a\ hlllr 't.IIC, " Create tire tate Table F .• . tOnl Ule controller 'h . we kn 0\\ thm the Itnte table UI\ ttC
Figure C2 Soda dl'pcn",r hlgh - Ic~cl
... t..lte mtichlOc
d=\
.1
0 0 ~ 0 0 0 0 ~ 0 0
Inputs c. tOI It s (bit) OutputS' d. tol Id. tot clr (bit)
'"
:s
Controller
<0:
(b )
(a)
Figure CJ Suda tlI'pcn,cr; (a) controller (de,,,,bed beh.l\ lora lly) and (b) datapalh ("ru ture) .
!
C.2 DESIGNING THE SODA DISPENSER CONTROLLER U,ing Ihe tilc -~ t cp controller de;ign procc" Introduced in the de, ign of the controller. The five steps are as follows : Captll re the FSM.
The F
hapter 3. we can complete
I for the soda
displ..'n:-.cr"s controller \Va, crea.ted during
step ~ of the RTL dc,ign method . The controller's FS~I is shown in Figure C.3(a). Captllre the A rchitecture. As indicated by the controller's F M. the tate machine's architectu re require at least 2 inputs (C and tot _ I s) and J ou tputs (d. to I d. and to . CI r). Additionally. we will usc two bits 10 represent the controller's states. which adds an additional two in puts (the current state sls0) and two outputs (the next state n 1 n 0) 10 the controller architecture. The corresponding controller architecture is shown in Figure CA.
Combinational d
toUd
logic
Illputl c
0u\pU1I
toI
0 0
0
\
0
\
1
1
0
1
0 0
1
\
0
\
1
~_.
d
tOl Id tot clr nt
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0
1
1
1
0 0
0
\
0
1
0 0 0 0
1
1
1
\
0
1
1
1 1
1
1 1
0 0 1
0
1
1
1
1
1
1
1 1 1
1
1 1 1 \
1
t \
1
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 \
nO \
t 1 \
1
0
\
\
0 0
1
0 0 0 0 0 0 0 0
1 \
1 \
0 0 0 0
Figure C.5 The soda d"pcnscr conlroller" >tate wblc . By examining the outputs pecified '" the comroller FSM. duplicated for convenience to Figure C.6, we fill in the corre~pond tog d. tot_I d, and tot_CI r columns in the state table. For example, in Figure C.6, we see that when the controller FSM is in the filii state, d-O, tot_CI r-1. and tot_ld is implicitly O. Thus. for rows in the state table that correspond to the fil i i state namely, the four rows where sls0-00 si nce we chose "00" as the encodi ng for the In i/ state - we set the d column to O. the t ot_CI r column to I, and the to Id column 10 0 .
Figure C.4 Standard controller architecture for the soda di penser.
sO 0 0 0 0
-
tnpul. c. lot It • (bot) OutpulS' d. tot Id, lot clr (b.t)
Figur. C.6 Soda dispen,,:r conlroller FSM WII/1 ' tate encoclins-,.
We fill in the nex t state columns. nl and nO. based on the the transitions specified in the controller FSM and the stale encoding we chose in an earlier step. For example. con ider the Wait state. As indicated in Figure .6. the FSM transition to the Add state when coL Thu ~. for rows where s !sOc-Oll
5 18
C Extended RTL Design Example
C2 Deslgnmg the Soda Dlspensol ContIolior
(s 1 sO 01 corre'pond, 10 Ihe \Vall ~Inlc). we CI Ihe n 1 column 10 1 and the rO col umn 10 0 (n I nO 10 corre'pond, 10 Ihe Add ,laiC). When ~-O. Ihe F 1\1 Imn,II1 n., 10 Ihe D/ p 'Wle If o. I 0 eOl the Iran'"I011 fr011l Wall 10 01\(1 In Ihe talc lable bj \ClUng r 1 10 I and nO 10 1 (D/.rp) in lhe row II herc S 1 0 0 I (\~lIt) . O. and ;) 1 O. 111I1Iarl). I\e repre'>ClII the tr.IIl Ilion fr011l \~lIt back lO \Vall by wnllOg P I ~O 1 1\ here 51 0-01. r -0. and o I , 1 Wc Ihcn C"'11IllIC Ihe rem;,,",ng "<1n\1I10n, 10 a "mllar I\J). filling In Ihe appropriale valuc, lo r n 1 alld nO UIIIII all Imn'"10n' arc ,Iccoun led for The compleled , laiC table" , hown III Figure c.s.
\I,'"
Im plem elltthe C{)mbilloti{)llal t oxic. For each of Ihe ,laIC 1.lble \ OU IPUI . we IHlle lhe corre'pollding \3oulean eq uullnn . From the \l,lIe table lie oblaln Ihe follow 109 equollon .
51 a Id - sls0 ' clr - sl 'sO' n1 - sl ' sOc ' 0 1 d
o o
s'
s l' sOc
nO - 51 ' sO' sl'sOc ' + sls0' nO Sa ' + sl ' sOc' NOle Ilwl Ihe tiN four equallon, derived fro111 Ihe Malc lable arc nlready minl11llled . The fifth equalion. corresponding 10 nO. can be mlnlmi/ed 10 sO' + s I' sOC ' Ihrough algebraic mClhod~. or by u,ing a K-map t" ,howII III Figure .7. K-map' nre di,cussed in Seclion 6.2.
G slsO
c
o Figure C.B Fin al implementallon
SI 'sOc'
sO'
Figure C7 K -map for the inlllru cquallon for nO .
519
sing lechnique; di cu."ed '" ha I , inio an equi l olcnl III G-Icl cl gUie-ll'l-cd p rr -. lie ~lIl11e" the Jh.."c 1l<~\lc.,,\ elll""" 11\ lhe Boolean equalion, li e are c nl II'('UII Th" '1 01 cr."," I' 'Ir.l1l1ll1lc"\\.,,,1 ''''<0 e"'"8 .11\: olreJoI 10 I I equenl inl controller circuli Qnd the d . 'U11l\'p"", hll1l\ I he Figure C. . Jlup.llh fm Ihe 'I 1.1 Yhf'CII\CI " ,h,1IIll III
of Ihc "Xla mllCh,"c controller 1 1~1Ir< (' lell) Wll h dlllllpl1l h
",,"1
520
C Extended RlL Design Example
C.3 Understanding the Behavio
. r of the Soda Dispenser Controller and Data path
521
C.3 UNDERSTANDING THE BEHAVIOR OF THE SODA DISPENSER CONTROLLER AND DATAPATH In this section. we will look closely at how the controller and claw path we designed for the soda di spenser interact to form a working implementation of our initi al hi gh-level Slale mach ine.
Figure C.9 ill ustrate, the behavior of the soda dispenser controll er and dalapmh , including initi ali zati on and how the soda di spenser behaves when the user inserts a quaner into the system. The 5 cloc k cyc les shown are labeled I through 5 in the figure . We' ll assu me thm the cost of a soda ca n is 60 cents and thm the soda dispenser's controll er is in the /Ilir stme during the firs t cloc k cycle. Let's examin e what occu rs in each clock cycle: Initi all y. in clock cycle I. the controller is in the /Ilil stale. shown in Figure C.9(b). When in state /Il il. the controll er sets d to O. tot_ l d to 0, and tot_cl r to 1. Additiona ll y. the cont roll er sets the nex t state signals nInO to 01. corresponding to the H~,i' state. In the dawpath. the va lue of 101 and lOi+a is unknown. denoted by ''??''. Notice that eve n though the cont ro ller set t ot _ cl r 10 1 during thi s clock cycle. the 101 register wi ll not be cleared immediately (asy nchronously). Rather. 101 will be cleared shonly aFter the nex t cloc k cycle, a synchronous behavior. Finally, notice thm the price of the soda, s. is set to 60 cents and the coin input signa ls. C and a. are initi all y 0 and O. respectively. Figure C.9(c) shows the soda dispenser in clock cyc le 2. The contro ller is now in the iVail state . Accord ingly. the controller sets d, tot_ l d. and tot_c 1 r 10 O. The va lue of 101 is cleared. and shonly afterwards. two signals. tot_ l t_s and IOI+a. take a know n va lue. The datapath 's comparalOr sets tot_ l t_s to 1 since the total . O. is less than the price of soda, 60. The datapath 's adder sets intermediate signal 10i+a to 0 since 101 and a are now known. The nex t state signals remai n set 10 01 (IVa it) since c is 0 and tot _ l t _ s is 1. Figure C.9(d) shows the soda di spenser in clock cycle 3. During the third clock cycle. the user insens a quaner inlO the soda di spenser. as indicated by C becom ing 1 and a becomi ng 25. Shonly after a changes, the adder's output 101+a changes to 25. the sum of 101 and a. Since c is 1. the controller sets the next state to 10 (Add). The va lues of d. tot_l d. and toCc 1 r remain the same since the controller's stale has not changed since Ihe previous (2 nd) clock cycle.
(b)
elk slate (5150)
"'c:
<0
nexl state (ntnO)
Ol
'in
d
~
(a)
eE
C
loUd
o
()
~;=~:;~~~~~G;~~~~~~~~== n--hr~--T-
__+.==:::::ii;---+---
: n
__
h' =---+----I---......w
"'c:
<0
Ol
'in
.c:
OJ a. OJ
'"
0
101
tol+a
??
25
25
25
25
60
In cl oc k cyc le 4, shown in Fi gure C.9(e), the conlroll er is in the Add stale and sets tot_ l d 10 1 while keeping d and tot_c 1 r at O. As was Ihe case wilh tot_clr during Ihe /Ilil stale. 10 1 will nol be updaled until Ihe neX I clock cycle. The controller will uncondi ti onally relurn 10 slale iVail . selling nInO 10 01 (Wail ).
00
00
Figure C.9 Soda dispenser operation from initialization to inserting a quarter: (a) timing diagrnm. (b}-{e) signal values during clock cycles 1-4.
m
522
C Extended RTL Design Example
C.3 Understanding the Behavior of th S . e oda Dispenser Controller and Datapath
In clock cycle 5. shown in Figure C. IO. the cont roller sets d. to t _ l d, and tot_c 1 r to 0 since the controller is in the Wa it state. The tot register loads the value of IOt+G. storing 25. Shonly afterwards, lOt+ a changes to 50 to refl ect the new value of lOt . however, 50 is not loaded into to t as tot will only perform a load synchronous to the rising edge of the clock signal. The addition procedure de monstrated in clock cycles 3 through 5 is repeated for each coin insened unti l enough change has been insened to cover the cost of a soda, a indicated by inpu t signa l s.
Figure C.10 Operation of the controller and data path: clock cycle 5 from Figure C.9(a).
523
52~
C.3 Understanding the Behavior of the Soda Dis penser Controller and Datapath
C Extended RTL Design Example
525
Fig ure C. II de tai ls the behavior of the soda di,pe."er when the user has inserted enough change in to the machine to merit a soda being di spensed. In the timing diagram
shown in Figure C. II (a). we dupl icate clock cycle 5 from Figu re C.9(a) as a point of reference. During the nex t few dOlen clock cycles. we assume that the user has inserted a nickel followed by a quarter. As a result. the reg ister 10 1 will contain the value 55 (25 + 5 + 25 cents). Lct"s examine the behav ior of the soda di 'pense r when the user inserts
e
1->0
a dime into the machine :
In Fi gure C. II (b). corresponding to cloc k cyc le 100. the socia dispe nser' S controller is in the IVa il state. Assum ing the user insert s a d ime into the soda dispense r. the c input will become hi gh for one clock cycle and the a input will change to 10. the value of a dime. Short ly after a changes, the intermediate signal 101+0 changes to 65 (55+ I 0). With c asserted . the nex t state signal s nInO become
~
10 (Add). (b)
In clock cycle 10 1. shown in Figure C. II (e). the contro ller is in the Add state and assert to _I d. The regi ter /0/ will not load a new total until the ri sing edge of lhe next clock cycle. The controller uncondit iona ll y sets the nex t state to 01
(e)
Clk~ " ' ~
( \\'ail).
Figure C.I I(d) shows the status of the soda di spense r in clock cycle 102. where the controller is in the IVail Slate . As ind icated by the arrows in Fi gure C.II (a). tot_l d being asse rted on the rising edge of the cloc k ca uses 10 1 to load the value on its inpu t. which i, 65 . Shortl y aft er 101 loads a new va lue, the comparator's output to t_l t_5 changes from 1 to 0 to re fl cct the fac t that 101 (65) is not less than 5 (60). Since the controller is in the Wail state. and since both c and tot_l _5 are O. the cOl1lroller sets the ncx t state signal; to 11 (Disp). Notice that prior to the nex t state ignals settling on the Disp statc. the next state was Wail for a brief period of time. Depending on the time requ ired for signal s to propagate through the datapath and controll er. certa in signals may initia ll y contain unexpected value,. but the ~e signa ls wi ll eventu all y settl e to their expected values. We can avoid any problems a soc iated with thi s peri d of uncertai nty by selecting a clock period that is long enough to allow our circuit 's intermcdiate signals to ; ettle into a , tablc state and stay stable long enough to comply wit h any setup time, requi red by ou r circuit's sequential component" In Figure C. II (e). the controller is in the Dis!, Sln te. The cOl1l roll er asserts d, indi cating to ,orne outside component th at a soda should be di' pcnsed. The controller will unconditionall y tran. iti on to the /Ilil state. where the initi ali zation procedure shown in Figure C.9 is repeated (partia ll y show n in clock cyc le 104 of Fi gure C.1 1(a) ).
'"c: 'in '" 0;
state (s l s0)
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(.)
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next state (nl nO)
55
65
I
65
I
65
10
10
10
,
10
,
10
65
65
75
,
75
, 75
60
60
60
I
60
, 60
t
'_°-l ~a ~
.-l-_ _ _ _
lO la
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We ,ee that lhe controller and datapath work together to implemen t the behavior of the origi nal high-level ,tate machine.
(d )
Figure C.ll
(e)
oda J"pcn"'r opec.ll1M \\ hen ,ullic.en! change has been i=cd: (3) timing diagram. (bHe\ signal
, alue, dunllg clock c)clc, IOC Ill.\
Index ~
I nd ex =.
:!~I
SdlSpla) , tatement. ~5 7 6 HC II microprocessor. 2 1 7~F subserie- ICs. ~03 7~ H C subseries ICs. ~0 3 7~LS ,ubseries ICs. ~03 ~OOO series ICs. ~ 03 7 ~OO series ICs. ~02-1().1 8051 microprocessor. 21. 422
A Abe." compone nt (A L-extender). 203 Abo\e-mirro r display (exa mple ):
with 16 32·bi l registers. 20-+-207 "ith 16,32 regi ster file. 208 \\ Ith parallel-load registers. 155- 156 with shift registers. 159. 160
with up-counters. 183 Absorption Law. 501 Abstraction (in RTL design). 276 Access time (RA M). 263 Active-high input. 136 ACllve-Iol> input. 137 Actuator. 9
Adaptive cruise comro!. 237 Adder(,). 165- 173. 197
building a SUblI3clor using. 197-200 carry-lookahead. 33.\-342 carry-ripple. 166-173.339-340.468-471 carry-;elect. 3~2-3~3 creallng faster. 333-343 deSIgn examples using. 171-173 .+-bit carry-ri pple. 169-171 full-. 168-169 h.lf-. 167-168 "·bu. 165-166 t"'o-Ievel logIC. 334 Adder tree. 215 add ,",tructlon. ~19-131. 434 Addlllve Identu} elcment. 497 Addll1ve '
of logic, 504 of sets. 504 switching , 496. 497 Algebraic meth ods, in two-level logic size optimi zation . 296-298 Algorith ms: Espresso too l in. 3 15 exac t. 308 selec tion o f. 356-357 fo r state red uct io n. 3 19 Algo rithmic state machin es (AS Ms), 233
Ahemalive minimum-bidwidth binary encoding, 323-324 ALUs. see Arithmetic-logic units always procedure, 453-454 A mpe res, 3 1
Analog ci rcui ts. 5 Analog phenomena, encoding of. 9 Analog signals, 4 Analog-la-digital converte r, 9 AND gates. 43-44, 404-407 AN D operato r, 38-40 Application-S pecific Integrated Circ uits (AS ICs). 38G-388 cell arrays. 383 FPGAs vs., 40 1 gate arrays, 38 1-382 implemen ting. usin g NO R gates. 386-388 impleme ntin g, using o nl y AND gates, 384-386 standard ce lls. 382-383 structured. 383. 408 Architec ture. 447
Arithmetic: fixed point. 508-509 Roati ng point. 5 13 A rithmeti c/logic ex te nder (AL-exte nde r). 202-203 A rithmeti c/logic instru cti o ns. 439 A rithmeti c-logic units (A LUs). 20 1-203 multi -fun ction calculator using. 203 operati o n. 423-424 A RM microprocessor. 2 1. 422 Arrays. Sec a lso Field programmable ga te arrays (FPGAs) ce ll ,383 gate, 38 1-382. 389 programmable logic. 407
ASCII. 10 ASICs, see Applica ti o n-S pec ifi c Integrated Circuits ASM s (a lgorithmic sta te mac hines). 233 Assemble r progra ms, 430 Asse mbl y code. 431 assert (term ). 137 asse rt stateme nt s, 456, 458-459 Assoc iative propert y. 50. 50 I Asychronous circ uits. 102 Asyc hronous inputs. 133 Asyc hronous reset inputs, 135 Asychro no us se t in pu ts, 135 Atria (of heart), 138, 139 Audio, dig it ized. 6-8 Audi o recordi ng, 5-7 Automation
with Quine- McClus key method, 3 11 -3 12 of two-leve l log ic size optimization, 308-3 15
B Bardeen. Jo hn. 33 Bases tati o ns (cell pho nes), 279-28 1 Base ten. 11 - 12 Basic input/ou tpu t system (BIOS), 431 Ba ic SR latch. 97-99 Beamforrners. 210-213 princi ple of. 210-2 11 in ultrasound machines. 2 12-2 15 Behav ioral-leve l design. 254-258 Bell. A lexander G raham. 8 Bell Labora tori es. 33 Bell Telephone. 8 BeltWam c irc uit. 387-388 B-frames. see Bidirectio nal predi cted frames Biased expone nt. 5 10 Bidi rectional predicted frames ( B-frames), 363-364. 369 Binary numbers. 11- 17.505 Binary num be r systems. 05-5 13 fi xed poin t ari thmetic in. 50 -509 Roating po int represcntation in. 509-513 real num ber represe nt ati o n in. 505-507 Binary poi nt. 506 Binary rcprc c nl3li ons. 4 Binary sear h. 357 BIOS (basic input/ou tput ,y tem). 431 Bit. 4 Bit file, 399 Bit storage. 96. ec also
BOOlean algebra, 38, 47-55 496-504
e.valualing expressions in '48-49 hterals in. 50
.
operators in. 38-39, 48-49 product terms in, 50 Properties in. 50-55 sum-of-products in, 50 SWllchmg, 497-498 terminology, 49-50 theorems in. 498-503 Variables in, 49 Boolean functio ns, 55-{i7 canonical form , 63-{i5
ClrCUlls fO.r re~resenting, 56 and cO~bmatlOnal circuits, 65 conversIon of. 58-{j() defined, 55
equations for representing, 56 truth tables for represe nting, 56-58, 62-{i3 BOOlean logIC gates, see Gate(s) ~oolean ?perators , see Operator(s) Boollng ' computers, 43 1 Brattain. Walter, 33 Buffers, 206, 272 Bus (i n registe r files). 206 Bus interface, 238-241 Bus protOCol, 239 Button press synchronizer (example). 123-124 Button sensor. 10
c
C (program langu age), 19-20, 254-258.388 C++ (program language), 254. 258. 388 Calculators, 200 Calculus. propositional. 504 Cameras. digital. 22-23 CAN (controller area network). 160 Canonical form (Boolean functions). 63-65 Capture (step in combinational logic desiga). 67-{i9 .. Carry-lookahead adders. 334-342 efficient example. 336-339 half-adders in. 337-339 hierarchical. 339-3~2 inefficient example. 335-336 Carry-ripple adders. 166-173 in dntapath component description. ~ -171 8-bit. 173 -l-bit. 169-17_ full·adders. 168-169 half-adders. 167-168 and hierarchical arry-lookahead adders. 339-~ Carry-ripple style magnitude comparator. 17 -I 0 ClUT)-sclc t adders. 34l-3~3
528
Ind ex
Cas.elle '"pes. 5- 6 Cell arrays. 383 Ce lls (cell phone region<). 279 Cells. stand ard (AS IC), 382- 383 ellul ar telephones. 7. 279- 284 co mpone nts of. 28 1- 284 voice qua lity on. 25 1 Cc b ius, 175 han nc b (in transduce rs). 2 10 Chec kerboard. co mput cri led (ex ampl e). 156- 158 Chips. ~cc Silicon chips Cincx I componenl (AL -cxlcndcr). 20~ C irc u i t ~ :
analog. 5 asychronous. 102 and Boolean functi on" 56 building. usin g gmcs. 44-l7 c lock divider. 187 co mbinati onal. 30, 65. 85. 95
crit ical path in. 252- 25-1 defi ned. 22 digital. 4-5.2 1- 22. 38-10. 2 13- 2 15 integrated. 33-35 mathemati cal formali sms in design. 130 and notati on simplification. 69- 72 panitioning. among lookup tables. 390-394 sense amp lifier. 26 1 seque ntial. 30. 85- 86. 95 simplifying drawings of. 130 state of, 95 sy nchronous. 102 CLBs. see Configurablc logic bloc ks Clear in puts. 134 C lock di vider. 187 Clock frequen cy, 103.25 1- 254 Cloc k gating, 358-360 Cloc k signal. 102- 105 Cloc k skew. 359 CMOS transistors. 35-37, 41. 42. 357-358 CMY color space. 192- 194 CMYK color space. 194 Codecs.409 Code detector (examp le). 11 7- 11 8, 129- 130 Color pace co nvener-- RGB to CMYK (example). 192194 Co mbin ati onal c ircui ts, 30. 85 multiple-output, 65 output of, 95 Combin ational logic descripti on: gate behav ior in. 452-455 stru ctu re in. 447-452
Index test benches in, 455-459 us ing hardware languages. 447-459 Combinati onal logic design, 67-72, 168- 169 Combin ati onal logic optimizati on, 296-3 17 multilevel logic optimizati on, 3 15-3 17 two- level logic-size optimizati on. 296-3 15 Combining le nn s 10 eliminate a vari able, 297 Combl ogic process, 455, 464-466 Communication: serial , 160 wireless. 161 Commutative propeny, 50. 498 Co mparator(s). 177- 18 1 equalit y, 177- 178 exampl e using, 180- 18 1 mag nitude, 178- 180 Compensating wei ght scale (exa mple), 173 Co mple ment (s).4 . 194-1 97, 497 defined, 195 ex iste nce o f, 499 unique, 499 Compl e mentation. 499 Compleme nt propeny. 51 Compl ex it y, managing (RTL design), 275 Co mplex programmable logic devi ce (CPLD), 407-408 FPGAs vs .. 407-408 SPLDs vs .. 407-40 Component allocation, 349- 350 Compre sion. 7 and computation of ratios in video, 364, 367, 368 in digital video. 363- 369 quantization in, 366-367 , 369 and transforming to frequency domain. 364-366 Compute rs, 4 with blinking lights, 430 booting. 43 1 Compu terized board games (example), 156-158 Computer monitors. 192 Co ncurrency (i n RTL design), 348-349 Concurrent computat ion, 354-355 Conductors, 36 Configurable logic blocks (C LB s) grid of. in FPGAs, 398- 399 output configuration memory in, 399 as progra mmable ICs, 396-398 Configuration (in RTL desig n), 245 Configuration memory, 398, 399 Congestion, 204 Constants, 434, 497 Constructor functions, 451-452 Control-dom inated design, 247 Control input, 3 1, 32. 150. See a lso Gate(s)
Contro ller(,). III. 11 9- 130. 135- 140 behavi or of. in soda machine di spenser example, 519525 co mmon pitfalls with, 128- 129 connec ti on of dot apath to. in RTL design . 236 defined. III deri va ti on of FSM for. 237. 238 de ign examples using, 116-117, 120-1 2 1. 123- 127 design o f. in soda machine di spenser example. 516-5 18 design process for, 120, 126 and implementation of FSMs. 122 initial state of. 135- 136 in laser-based di stance measurer example, 480-491 in LED module, 4 14-4 16 negative logic in. 136-137 output glitches in. 136 in pace makers. 138- 140 in equential logic description. 463-466 tandard architecture for, 119 Controller area network (CA ), 160 Control unit. 424-428 in six- instruction programmable processors, 435-437 for three-instruction programmable processors, 432-434 Conversion(s). 58 am ong Boolean functions. 58- 60 from any base to any ot her base, 15- 16, 60 from binary to decimal, 12 from circui ts to equati ons. 58- 59 from c ircuits to truth tables, 60 decimal to binary, 13- 15 from eq uations to truth tabl es. 59 as step in combi national logic de sign, 67- 69, 72 from truth tables to circui ts, 60 from truth tables to equations, 60 Convener(s): analog-to-digital. 9 digital -to-ana log, 9 of FSMs to circui ts , see Controller(s) RGB to CMYK (example), 192-194 Core, 41 I Cosine waves, 364-366 Counters, 181 - 188 down , 18 1, 183 exa mpl es usi ng, 183, 184, 186- 188 N-bit, 18 1 parallel load, 185-187 as timers, 187 up, 181-183 up/down, 184 Cover (term). 309 CPLD. sec Complex programmable logic device Critical path (in circuits), 252-254, 3 17, 333
529
rui e control, adapt;'c, 237 Crystals. pielOClectnc, 210 CUlT'
o communi Ali n. 161 Data-dominated design, 247- 250 defined, 247 example using, 248- 250 Data input, 150 Data memory, 423 Data movement in\ lructiOIl\, 439 Datapath, 423 24 0313
conn~cti on ~f COntroller to, In RTL de' i~ n , 236 ~reauon of, In RTL de'ign, 2 236 In laser-based di stance measurer (example), 480-49 1 fo r programmable procc«o". 422 24 :n Six-instruction progrnmmable proce,IO"', 435 37 soda machine di ' penICr (example), 519- 525 or three-instruction programmable proce"or , 431-4 Datapath component description: and carry-ripple adde"" 468-47 1 and full-adders, 467-468 up-Counters in, 471-475 usi ng hardware lunguages in, 467-475 Datapath components, 15 1 and faster adders tradeoff, 333- 343 and smaller multipliers tradeoff, 343- 345 Datapath operntions, 423-424 OCT. see Discrete cosine lransfonn Detr. sec Local registers Debugging, 33 Decimal point, 506 Decimal to binary conversion: di vide-by-2 method, 14-15 subtraction method, 13-14 Declaration(s): enum, 465 process, 452-453 type, 463 Decoders, 77-79, 395 Decoding stage, 426-427 Decrement (in counters), 181 Decrementer, 183 Deep Blue (computer), 157 Delay (i n gates), 85 Delay circuits. 213-214 DeMorgan's law, 52, 502, 503 DemUltiplexers, 85 Dequeue, 272
r"
b
530
Index Indo
Dc,igner proli le,. 29. 9-1. 22-1. 293. 377- 378.444 Dc~ i gning cOl11bin~ltional logic. 67-72 and circuli notal ion". 69- 72 ,Iep' in. 67- 69. 72 DC!'Iign proce ..... :
ror cOlllroller>. 120. 126 for rcgi~lcrs. 163 Detector ~ys le l1l ,,/app l il.:~Hl on'. 17-19.21 Dcterior:lIion. 6 D nip·liop,. 103- 109 edge-Iriggered. 10 107 -I-bil. 109
and It!vcl-!"cn:,itivc D latch. 103- 1().l
Digital camcm .... 22- 23 Digi lal circuit,. -1--5. 2 1- 22. 38--10. 213-2 15 Digital filter. 2-l8. See ;l lso Finite impulse rc"pon'\c fihers (FIR ) Digil:ll phenomena. encoding of. 9- 10
Digilal , ignal procc;
Digilal sound recorder (exampk). 26+-265 Digi lal ,yslems. 4. 17- 18 Digital telephone an!o.wcring machine (example). 270-27 1 Digital thermometer converter (example). 175 Digital -Io-analog converter. 9 Digil~ll video. 2-l-l
Di gital video discs (DVDs). 36 1-363 Digilal video player/recorders. 36 1- 370 compression in. 363-369 discrele cosine Iransrorm in . 36+-367. 369 and DVDs. 36 1-363 and hurrman coding. 367-369 MPEG-2 encoding and. 363-366. 369-370
6-8
Digiti zed audio. Digililcd pictun.:s. 8 Digiti zed video. DIP, see Dual Inline Package switch
DIP-switch-based calculator (examples): adding. 171 - 172 add ing/sublracling. 191-192. 198 multi-runction wi thout using ALU s. 20 1
using ALU. 203 Discrele cosine transrorm (DCT). 364-367. 369 Discrete transistors. 33 Display Slalemenls. 457 Disp stale. 330 Distance measurer. laser-b3sed. see Laser-based distance measurer
Distribuli ve propeny. 50. 498 Divide-by-2 melhod. 14-15.505 Divide-by-n melhod. 15- 16
D lalch. 103- 106 maSler. 105- 106 ,"rvanl. 105- 106 Don'l care inpul combinations. 305- 307 Down-counlers. 181. 183 dowTlto \;\tatcment. 459 Drain (OUlpUI). 35. 36 DRAM. see Dynamic random access memory Driver>. 206 DSP. ,ee Digilal signal processing/proces.ors Dual lnline PaCkage (DIP) swilch. 171- 172.402 DualilY. principle or. 499 Dual -poned regi'ler filc, 208 DVD<. sec Di gi lal video di,cs Dymunic microphone. 5 Dynamic power. 358 Dynamic random access memory (DRAM). 262-263.271
E EchoDelay circuilS. 214 Economy or scale. 200 EDA (eleclronic desig n automalion). 409 Edge-triggered D liip-nop . 10-1--107 defined. 105 musler/servanl design. 105- 106 EEPROM. sec Eleclrically erasable PROM 8-bi l carry-ripple adders, 173 Electricall y erasable PROM (EEPROM ). 268-269. 27 1 Electronul.gnctism. 5 Eleclronics. 31 Electronic design automalion (EDA). 409 Eleclronic focusing (or sound). 2 1I. 2 12 Embedded syslems. 4 Enable (decoders). 77 Enable inpul. 101 Encoders. 85-86 Encoding. 9- 13 of anal7,g phenomena. 9 or digilal phenomena. 9- 10 emropy. 368 huITman. 367-369 minimum-bilwidth binary, 323-324 MPEG-2.363-366 of numbers. 1(}-13 one-hOI. 324-326 OUlpUI. 327-328 run-Ienglh. 367. 369 in sequenlial logic opl imizat ion. 323- 328 E lAC (compuler). 33 Enqueue. 272 emily declaration. 447 Entropy encoding. 368 enum declaration, 465
cnum stiltcmcnl. -t65
EPRO I. see Erasable PROM EqualilY comparator. 177- 178 Equalions. 56 Equivalenl slales. 318 Erasable PROM (EPROM). 267-26 Espresso (heurislic (001). 315 E semial prime implicanl. 309-3 10 Exacl algorilhm. 308 Excalibur plalrorm (A llera). 409 Execuling slage. 426-427 Exi tence: or add ili ve idenlit y elemenl. 498 or complemenl . 499 of mulliplicalive idenlilYelemenl. 497 Expanding (Ierm). 309 Expand operal ion. 3 13 Exponenl. biased. 5 10
F Fabricalion planl (rab). 380 Fahrenheil. 175 Falling edge-Iriggered flip-fl ops. 107 Fanoul. 204 Fa. I Fourier Transrorm (FFT). 364 Feedback. 96-97 Felchng slage, 426-427 FFT (Fasl Fourier Transrorm). 364 Field programmable gale arrays (FPGAs). 377. 388-40 1 archlleclure or. 398-40 I AS ICs vs .. 40 1 configurable logic blocks with, 396-398 CPLDs vs .. 407-408 lookup tables wilh. 389-394 microprocessors vs .. 40 I programming or. 399-400 SPLDs vs .. 407-408 swilch malrices wi lh. 394-396 FIFO (firsl-in firsl-oul). 272 FIFO que ues. 272 Fillering (in digi lal signal processing). 282 Finile impulse response fillers (FIR). 282-284 wilh clock galing. 359-360 example using. 248-250 and pipelining. 347 using operalor scheduling. 352-354 Finile induclion, 503 Finile-slate mac hines (FSMs), 11 3- 119. 128-130 behavior in, 11 8- 119 comroller archi lecture ror. 11 9 convening circuillo, 126- 127 wi lh data (FSMD). 230 defined. 11 4
derivulion of ~
. Or Com roller '>7 '18 ~,gn ,,-
ICrs. sec FlOlie 1I1l.pul •
Firsl-in firsl-oul (FIFO) 'e rc'llOl"C lille" Firsl-in fi"l. . 272 Fi"'l . , OUI (FiFO) queue,. 272 . pll« (slale redUCllon) 1 0 )11 ~lXed-poill! llrilhmeli .508- 50<) -Hush memory. 269 . F1lghl c 11 -bUllon (cxnm ple) 10K I~ ' Ii 'lIIend'''" ,a Ip- 0ps. 96-111.130-135 • clock signnl, '". 102- 10) D. 103- 109 and D latche.. 103- 104 and reedback in bil Slomgc 96-97 lK.131 ' . IDlche. vs.. 107 non- ide~1 behavior in, 131- 134 and r:glSlers in bil Slomge. 109-1 II resel mpul' in. 134-135 sel inpUIS in. 135 SR. 108. 131 and SR Inlches. 97- 10 1 T. 131 F1oOling-poin! arilhmelic. 513 FioOl~ng poin! numbers. 510 FloDl~ng poinl rcpresen!a!ion. 509- 513 Fioallng poinl unit. 513 Flops, 108. Sec also F1ip-lIop, Flow-Of-conlrol inslruclion" 440 Focusll1g (of sound). 21 1, 212 4-bil carry-ripple adders, 169-172 4-bH D liip-Hops. 109. Sec also Regisler(s) FPGAs. see Field programmable gale arrays Frames. 241.361.363-364.369 Frequency: clock. 103. 251-254 sound waves. 210 FSMs. see Finile-slale machines Full-adders. 16&-169.467-468 Full-cuslom ICs. 379-380 Fuse-based programmable ROM . sec One-lime programmable (CYrP) ROM
G GAL (generic array logic). 407 Games, compulerized board. 157 Gale(s), 35. 36.41-44.73-76 A D.43-44 building circuilS u ing.44-47
53 1
t
532
Index
G"le(~) «('Olilirllled)
and combinational behavior. -t52~S5 d~lay~
with. 85 and FPGA,. 400--l01 10\\ -power. on no ncritical paths. 360 NA D.73-75 NOR. 73-75 NOT. 42 number of possible. 76 OR. 42-13 unhersal. 75 XNOR. 74. 75 XOR. 74. 75 Gate arrays. 3 1-382 .389. See also Field programmable gate arrays (FPGAs) Gating. clock. 35 -360 General-purpose processors. -1.21 . See also Progra mmable
processors Generate (in carry-lookahcad adders). 338. 340-34 1 Generator(s): I Hz pulse generator (example). 183 . 186-187 sequence generator (example). 124- 125. 327-328 Generator. sequence. see Sequence generator Generic array logic (GAL). 407 Generic variables. 503 GHz (gigahenz). 103 Giant video display (product profil e). 4 12-4 16 Gigahenz (GHz). 103 Glitcheslglitching. 100. 136 Google. II
H Haitz's law. 413 Half·adders. 167- 168 in carry-lookahead scheme. 337-339 tmplementing on a gate array (example). 382 Implementing urn circuit using NAND gates (example). 385 Implementing sum circuit using NOR gates (example). 386-387 Implementing using standard cells (example). 3 3-384 Hardware description languages (HDLs). 446-447 Hardware languages: in combi national logic description. 447-459 in datapath component descrip tion. 467-475 In reg"ter-transfer level (RTL) design. 475-49 1 In ,equential logic description. 459-466 HDLs. -.e hardware description languages HDTV (h,gh-definilion TV). 94 Hean. human. 138 Heru (HZ), )03 Heumllc,. 308. 3) 3-3) 5 E'prc"o too) In. 3 15 Ilerallve. 312
Hexadecimal numbers (hex). 16- ) 7 Hierarchical carry-)ookahead adders. 339- 342 Hierarchy (in RTL design). 275- 278 High-definition TV (HDTV). 94 High impedance. 239 High-Ieve) state machine(s). 229- 233 in laser-based distance measurer (example). 475-480 and Moore vs. Meal y. 354 Highway speed measuri ng system (example). 187- 188 Hold time (in flip-fl op inputs). 131. 132 Hu ffman coding. 367-369 Hz (hertz). 103 ICs, see Integrated circuits
Idempotent Law. 52. 500 Ide ntity comparator. see N-bi t equality comparator Identity elements, 497 Identity propeny. 50 I-frames, see Intracoded frame s
If- then-else statements. 255-256 If-then statements, 255 Impedance. high. 239 Im plementation(s): physical , see Physical implementation as step in combinational logic design. 67-69, 72 two-level logic. 67 Im plicant (term), 309 Im plication tables, 31 8-322 Improvement, iterative, 3 12
Inc rement (counters). 181 Incrementer. 182- 183 Inductance. 188 induction : finite, 503 perfect. 498 Inducti ve loop. 188 Initial state (controller ), 135- 136 Init state. 330 In put(s): ac ti ve-high. 136 ac ti ve-low, 137 asynchronous. 133, 135 clear, 134 in combinational logic description. 450 conditions. 11 4 control . 150 data. 150 enable. 101 reset. 134- 135 synchronous, 134-135 Input/output extensions (progra mmable processors), 440 Instantiation (i n RTL dc;ign). 234
Instructions. 425-428. See also specific instruCtions arithmellcfloglc. 439 data movement. 439 now-of-control. 440 Instruction memory. 425 Instruction reg ister (lR ). 426 Instruction set: ~ n six- in~ lru c li o~ programmable processors, 434-435 m three~m s trucllo n p~ogramma ble processors. 428-431
Instrucllon set extenSIOns (programmable processo ) 428. 439-440 rs . Insulators. 36 In-system programmable EPROMs. 268 Integrated circuits (lCs). 33-35 fu ll-custom. 379-380 semicustom (AS ICs), 380-388 Integrated circuit (lC) technology(-ies). 379-412 CPLDs as. 407-408 FPGA as, 388-40 I FPGA-to-AS IC conversion as. 408 manufactured. 379-388 and Moore's Law, 4 12 off-the-shelf SSI ICs as. 40 1-404 and proces or varieties. 410-41 I programmable. 388 re lative popu larity of, 409 SOCs as. 408-409 SPLDs as. 404-407 tradeoffs among. 409-410 Intel,2 1 Intracoded fram es (I-frames). 363-364, 369 Inverse. 48
Inverters. 42 Involution Law. 52, 50 I lR (instruction register). 426 Irredundant operations. 3 15 Iterate (term). 3 13 Iterative improvement. 31 2
J Java (program language). 254. 258 JK Hip-nops. 13 1 jump-if-zero instntction. 435-437
K Keys. secure Cnr (example), 11 6-1 17. 125- 126 Keyboands. computer. 7 1 Kilohertz, 2 10 K-maps: four-variable. 302-303 three-vnriable. 298- _99 and two-leve l logic ,ilo optimi7atiOll. 19 306
Index . 533
L Lands (on DVDs), 362 Laser(s):
for surgery. 112 m three-cycles h" h . 120- 122, 3z,;, ~g26tl mer (example). 111 - 11 2, 11 5, Laser-based distanc 230-238 e measurer (example), connecting the data ath
COntroller in, 480-4~ 1
to a COntroller in. 236
datapath in, 234-236. 480-491 den vat IOn of COnlI II . high-level state 0 er s FSM in, 237. 238
LatChes, 97-101 , ~;~~;~~~O;29-233. 475-480 basICSR. 97-99 flip-flops vs. , 107 level-sensitive D. 103- 106 level-sensitive SR, 99-101 Latency (in pipe . I'Ine registers). 347 La yOUl (of transistors on chips) 380
~~~s (Liquid Crystal on SilicO~) chip. 94 , see Llght-enuUtng diode Level-sensitive D latch. 103-104 Level-sensitive SR latch, 99-10 I Lights. blinkin •. 430 LLighh t-emitting diode (LED). 171-172 41?-416 . Ig t sensor, 10 Light sequencer (example). 184 Lmear search, 356 Liquid Crystal on Silicon (LCoS) chip 94 Luera/s. 50, 296-298 . load-constant instruction. 43-1-435, 437 Loadmg (data). 151 load instruction. 428-131. 434 Load operation . 423-124 Load/shift registers. 160-163 Load-store architecture. 424 Local registers (Dctr), 232-233 Logic: next-state. 329 output. 329 Logic block. configurnble (CLB). 396-39 logIC gates. see Gate( 1 Logic Ie. 40_ Lochhead (in omputer games). 157 Lockup t. bles. 3 9-394 "an'ples using. 392-394 parritioning a cin:uit among. 390-394 Lo\\ -PO" er gat . 360 LT 1000 ' .ntil.tor. 2. 3
534
Index
M MAC (multiply-accumulate) unit. 353 ~I achine code. ~30 Magnetic RAM (MAG RAM ). 27 1 'Iagnitude comparators. 178- 180 MAGRAM (magnetic RA M). 27 1 Mantissa. 510 Manufactured integrated circuits (ICs). 379-388 AS ICs. 380-388 full-custom ICs. 379-380 Mark 1I (computer). 33 Mars Cli mate Orbiter. 175 Mask-programmed ROM . 266 Master latch. 105- 106 Maxterm. M Mealy FSMs. 328-333 example using. 331 high-level state mach ines. 354 with Moore FSMs. 332-333 timing issues in. 33 1-332 1ean time between failures (MTBF). 134 Medium-scale integration (MS I), 34 Megahertz (MHz). 103.210 Memory. III. See also Sequential circui ts configuration. 398 data. 423 fl ash. 269 in LrUction, 425 MxN.258 nonvolatile. 265 random access (RAM). 259-265 read-only (ROM ). 265-271 in RTL design. 258--271 volatile, 265 Metastability, 131-134 Metastable state, 132 Meucci, Antonio. 8 MHz (megahertz), 103,2 10 Microphones. 5. 210 Microprocessors: defined. 18 digital circuits in, 4-5 FPGAs vs .• 40 I software in. 18--21 Millimum-bitwidth binary encodi ng, 323-324 M,nterm, 63. 308 MIPS microprocessor, 21. 422 Mnemonic instructions. 430 Module: III combillalional logic description, 450 In LED,. 414-416 SC. 450-452
°
Monitor(s): RGB.I92 in ultrasound machines. 213 Moore. Gordon. 34 Moore FSMs. 328-333 high-leve l state machines, 354 with Mealy FSMs, 332-333 Moore's Law. 34, 35. 4 12 MOS (ternl). 37 Motion-in-the-dark detector applicat ion, 17- 19, 21 , 440 Motion sensor, 9 Motorola, 21 MP3 fornlat , 7 MPEG- 1. 363 MPEG-2 encoding, 363-366, 369-370 MSI (medium-scale integration), 34 MTBF (mean time between fai lures). 134 Multifunction registers. 160-163 Multilevel carry-Iookahead adders. 342 Multilevel logic. 360 Multilevel logic optimi zation. 3 15-317 Multiple bit storage. 109- 11 1 Multiple-output combinational circuits, 65 Multiplexers (m uxes), 79-83 internal design of, 79- 80 N-bit Mxl , 8 1-82 Mu ltiplicative identity element, 497 Multipliers: in beam formers. 2 15 in binary num bers. 189- 190 sequential , 343-345 Multiply-accumulate (MAC) unit. 353 Multi-ported register file , 208 Muxes, see Multiplexers MxN memory, 258 MxN register file. 204
N NAND gates, 73- 75, 384-386 Nanosecond (ns), 100 Nanowalls, 360 N-bil adders, 165- 166 N-bil arithmetic-logic unils, 20 I N-bil barrel shifters. 176 N-bit counlers, 18 1 N-bit equalily comparalor, 177- 178 N-bit magnitude comparalors, 178- 180 N-bil regislers, 151 N-bit shifters. 174 N- bit subtractors, 190-19 1 Negative edge-triggered nip-na ps. 107 Negalive logic, 136--137 Negalive numbers. represenl ing. 194- 197
Network rouler, 92 New Year's Eve counldown display (exam Ie) 18 Nexpena plalform (Ph ilips), 409 p , 6 Nexl-stale logic. 329 nexlSlale signal. 463-466 NMOS .Iransislors. 35. 36, 42-44, 73 Noncnlical paths, 360 Nondelerministic FSM, 128 Non-ideal b ehavior (in flip-flops), 131 - 134 Nonrecumng engll1eering (NRE), 200, 380 Nonvolalile memory, 265 Nonvolalile RAM (N VRAM ). 27 1 NOR gales, 73-75, 386--388 Normalized num bers, 5 10 Nolalion(s): in Boolean algebra. 48-49 simplifyi ng circuit. 69-70 simplifyi ng for FSMs. 115- 116, 130 NOT gales. 42 NOT operalor. 38-40 NRE, see Nonrecurring engineering nS (nanosecond), 100 Null elements. 52 Numbers: bi nary, 11 -17 encoding of, 10-13 hexadecimal, 16-- 17 OClal, 17 represenling negative. 194- 197 subtractors for positi ve, 190- 191 NVRAM (nonvolatile RAM). 27 1 NxN multipliers. 189
o Octal numbers. 17 Off-sel. 308 Off-the-shelf logic (SSI ) IC. ~Ol-l().l Ohm 's Law. 3 1 I Hz pulse g~ nerator (example). I 3. I 6--1 7 One-hot encod ing. 32+.326 One's complement . 196 One-time programmable (OTP) RO 1. 267. 405 On-set. 308 Opcode, 429 Operands, 429 Operation(s): bitwi e. 20 1 expand. 313 irredundnnt . 3 15 reduce. 3 15 Operalion ode. 429 Operator(s): AND. 3 -40
Index in BOOlean al eb NOT, 3S-40 g ra, 38--39, 4S-49 OR,38--40 Operator binding 350Operator sched I: 35 1 Opticom s Uing, 351-354 O ' ystem, 188 pt~mal solution. 308 OptlmlZatiOn(s), 294-2 and algOrithm selecti!6.3~ee also Tradeoff(s) combinational I ' . 6 criteria for, 295 OglC, 296-317 defi~ed, 294, 295 at higher vs. lOwer d . multilevel logic 31 eslgn levels. 355 power, 357-300 5-317
~n RTL deSign. 345-354 equenUallogic.3 17_333 two-level 10 ' . OR glc Size. 296-315 gates, 42-43 OR operator, 38--40 Orthogonal implementati OSCillation, 99-100 on features, 410-411 Oscillators: defined, 102 quartz, 102 in sequential I ' '. OTP ROM oglc d.escnpuon. 461-463 . see One-ume OutDelay, 213-2 14 programmable ROM Output(s), 31. 32 in combinational I . reading. 246 oglc description. 450 reg. 453. 454, 460 Output enCoding, 327-328 Output glitches. 136 OutPUt logic. 329 Overclocking (in Pes). 253 Overflow detection, 198-200
p Pacemakers, 13 7-1 ~ PAL (programable array logic). 407 Parnllelload Counters. 185-187 ~~I~elload registers, 151-152. 160-161 rdluUomng. _3 Pe (program COunter). 426 Pel'. see P:np . heral component interface p enuum ml roProcessors. _1 Perfect indu tion. 49 Perfonnance (in digirnl systems). _95 Pe~ormanre euensions (programmable Pe~od (clock signal). 103 proces rs). ~ I Penpheruls. ~3 Peripheral component interfoce (Pel). 1~. 141
SJS
536
Index
P·framcs. <;;ee Predicted frames
Physical design. 387 Physical implementation. 379-117 alternati ve technologies for. 401-409 comparing technologies for. 409--t 12
of giant video display. 412-1 16 and manufactured IC technologies. 379- 388 and programmable IC technologies. 388-40 I PIC microprocessor. 21. 422 Pictures. digiti zed. 8 Piezoelectric crystals. 210
Product term. 50 Program, 42 1, 425 Programable array logic (PAL). 407
Program counter (PC). 426 Programmable illlegraled circui t (lC) technology. see Field programmable gate arrays (FPGAs) Programmable inlerCOnneCIS. 394--396 Program mable logic arrays (PLAs). 407 Programmable logic device (PLD). 404-407 Prog ramm able processors. 42 1-442 control unit for. 424-428
Pipeline reg isters. 346
datapath for. 422-424
Pipelining. 345- 347 Pixels. 192. 361 Placement (in chip components). 387 PLAs (programmable logic arrays), 407 Platform SOCs. 408-109 PLD. see Programmable logic device PMOS transistors. 37. 42-44. 73 Pop (in queues). 272 Pones):
input/ou lput ex ten sions 10, 440 instructi on set eX lensions to. 439-440 performance ex tensions 10, 441 six-instruction. 434-439
in combinational logic description. -+47
read. 205 write. 205 Positive edge-triggered flip-Hops. 107
Positive numbers. subtractors for. 190- 194 Powe r:
in digital systems. 295 dynamic. 358 Power optimi zation. 357-360 Power PC programmable processor. 422 Precharging (RAM bit storage), 261 Predicted frames (P-frames). 363-364, 369 Preset (asynchronous set). 135 Prime (term ). 48 Prime implicant. 309 Printers. 192- 194 Priori ty encoders. 86 Proces declaration, 452-453 Processor(s): defi ned, 225 digital signal. 213 single-purpose, 421 superscalar. 44 1 Very Large In "ruction Word (VLlW), 44 1 Product. 48 Product-of-maxterms form, 64 Product profi les: cell phones. 279-284 dIgital video pl aye rlrecorde rs, 361 -370 giant VIdeO d"play, 412-4 16 pacemaker>. 137-139 ultr",ound machines. 209-2 16
th ree-i nstruction. 428-434 Programmable ROM , 267 Programmers (ROM ), 267 Programming languages, 254-258 PROM , see Progra mmable ROM Propagate (in carry- lookalJead adde rs), 338. 340-34 1 Propagation. 104
Propositional calculus. 504 Pulse width modulation (PWM), 415 Push (in queues). 272 PWM (pu lse width modulation). 4 15
Q Quantizati on (in video compression). 366-367, 369 Quartz, 102 Quartz oscillators, 102 Queues. 271-272 Queuing. 271-274 Quine-McCluskey method, 3 11-3 12 QWERTY keyboard, 7 1
R Race condition. 100 Radi x. 5 10 Random access memory (RAMs): bit storage in , 260-26 1 dynamic (DRAM), 262-263 example using, 264-265 in RTL design, 259-265, 271 static, 26 1- 262 readO fun ction. 455 Reading (data), 15 1 Read-Onl y Memory (ROM s): examples using, 269- 27 1 in RTL design , 265-27 1 types of. 266-269 Read-onl y memory programming, 265
Read pon, 205 Read time, 263 Real nu mbers, 505-507 Record ing, audio, 5-7 Reduce operation. 3 15 Register(s), 109- 111 , 15 1- 165 design process for, 163 examples using, 152-160, 164- 165 local (Dctr), 232- 233 multifunct ion, 160- 163 in multiple bit storage, 109- 111 N-bi t, 15 1 parallel load, 151-152 wi th parallel load and shi ft , 160- 163 pipeline, 346 rotate, 159- 160 in sequential logic descripti on, 459-46 1 shi ft , 158, 159 updati ng of, 245-246 Regislered data outputs, 246-247 Register fi les, 204-208 dual-poned, 208 mul ti-poned, 208 MxN, 204 single-poned, 208 Register-transfer level (RTL) components, 151 Registe r- transfer level (RTL) design, 225-285 abstraction in, 276 behavioral-level, 254-258 clock frequen cy, determination of. 25 1-254 component allocation in. 349-350 concurrency in, 348-349 connection of data path to controller, 236 controller's FSM , derivation of. 237. 238 data-dominated,247-248 data path, creation of, 234-236 examples of. 238-244, 248-250. 269-27 1. 279-284 hierarchy in. 275-278 high-level state machine. creation of. 229-233 managing complexilY in, 275 memory components in . 258-271 method, 226-238 operalor binding in. 350-351 operalor scheduling in, 35 1- 3 4 optimizalions and tradeolTs in, _45- 354 pipelining in. 345- 347 pitfalls in. 245- 246 queuing in, 27 1- 274 RAMs in, 259- _65, 27 1 and registered da ta outpulS, 2-16-_47 ROMs in, 265- 27 1 scope of. 225- 126 using hardware langung., Ill, -17_ 91
Index .. 537 using programmin g I reg output, 453, 45 7 ~nguages in, 254-258 Relays, 32 ' 60 Reset inputs, 134- 135 Resetting, 98 ReSistance, 31 Resource sharing, 351 Resplll (in IC fabrication), 380 Reverse engllleering 1?6 RGB color space, 192--194 RGB monitors, 192 Rising edge-triggered fl' Rolling over, 181 Ip-ftOps, 107 ROMs, see Read-Onl y Mem Rotate registers, 159-160 ory :Outin g (in chips), 387 5-6000 SP processor 157 RTL components, 151 ' RTL design, see Register-tra Run-length encoding. 367, 3~~fer level design
S SAD. see Sum-of-absolute-<1'!t Sampl ing, 6
I.
erences
Sscale, chompen ating weight (example) 173 Can c run. 399 . Scan convener, 213 SC_CfOR statement, 45 1--452 454 Scheduling. operator. 351-354' Schematic, 445 SChematic capture tool (use in circUits) 84 SC_1Il0 statement, 451 ' SC_METHOD. 454-455, 458 SC_module. 450-452 sc_outo statemenL 451 sc_signal statement. 451 SC_THREAD testbench process. 458. -162-463 Search(es): binary. 257 linear. 56 Seal belt warning lighl (example): .." ended. on an FPGA. 395-'96 implementing. with a lookup table. 390 usmg OR-b:L
&
538
Index
Sensitive processes. 453. 455 Sensitivity lists. 46 1-462 Scnsor(s). 9- 10 bunon. 10 light. 10 traffic light. 188 Sequence ge nerator (exa mple). 124- 125. 327-328 Sequencer. li gh t (example). 184 Sequenti al ci rcuits. 30. 85-86. 95. 126- 127. See also Fini te-state mac hines (FS Ms) con trollers. I I I. I 19- 130. 135- 140 convertin g to FS M (exa mple). 126- 127 Rip-Oo ps. 96- 111 . 130-135 Sequential logic descripti on: con trollers in. 463-466 osci llators in. 46 1-463 reg isters in. 459-46 1 using hardware languages in. 459-466 Sequent ial logic optimizati on. 317-333 and Moore vs. Mealy FS Ms. 328-333 state encodi ng as. 323-328 state reducti on as. 317-323 Sequen tial multi plie rs. 343-345 Seri al communicati on. 160 Seri al co mputati on. 354-355 Serializing (in computations). 352 Servant 0 latch. 105- 106 Set inputs. synchronous/asy nchronous. 135 Setting (in latches). 99 Setup ti me (i n flip-flop inputs). 13 1. 132 Shannon. Claude. 40 Shifters. 173- 176 barrel. 176 examples using. 175 simple. 174 Shift registers. 158. 159 Shockley. William. 33 SHRO function. 477 Signa l(s).448 cu rren tstate. 463-466 di gital. 4-7 nex tstate. 463-466 state. 476 Signal processor. 2 13 Sign bit. 196 Signed-magni tude. 194 Significand.510 Silicon (elemen t). 37 Silicon chips. 33-35. See also Integ rated ci rcuits (ICs) and economy of scale. 200 fabri cation of. 380 Silicon Valley (Californ ia). 37
Simple programmable logic dev ice (SPLO). 404-407 C PLOs vs .. 407-408 FPGAs vs .. 407-408 Simul ati on (in ci rcuits). 84 Simul ator. 84 Single- ported register fi le. 208 Single- purpose processor. 42 1 Si x- instru cti on programmable processors. 434-439 cont ro l unit in. 435-437 datapath in. 435-437 instru ctio n set in. 434-435 Size (in di gital sys tems). 295 Small -scale integrati on. see SS I SOc. see System-on-a-chip Soda machine dispense r (ex ample). 227-229. 515-525 contro ller. design of. 5 16-51 8 understanding be hav io r o f contro ller and datapath . 51 9-525 Soft ware. 18 Solid-s tate transistors. 33 Sound. 2 10-2 12 Sound ge neration circuits. 2 13-2 14 Sound wa ves. 2 10. 2 12 Source inpu t. 3 1. 32. 35 . 36 SPG bloc ks. 339 Spin (in IC fabri cati on). 380 SPLO. see S im ple programmable log ic devi ce Spurious va lues. 17 1 SRAM. see Static random access memory SR flip-flops. 108. 13 1 SR latches. 97- 10 I bas ic. 97- 99 level-se nsitive. 99- 10 I SSI (s mall-scale integrati on). 34, 401-402 Stages: pipeline registers. 346 programmable processors. 425-428 Standard architecture (for controllers). 11 9 Standard cells. 382- 383 Standard represe nt ati on. 62 State(s): of ci rcuits. 85- 86. 95 . III eq uivalency between. 3 18 State diagram. I 14 State encoding: alternative min im um-bitw idt h binary. 323- 324 one-hot. 324-326 output. 327-328 in sequential logic optimization. 323- 328 Statements. See also specific statements assert. 456. 458-459 display. 457
State minimi zation. 3 17-323 Sl3le reduction :
algorithm for. 3 19 example. for. us ing implica ti on table. 32 1- 322 Implication tables. 3 18-320 in sequen tial log ic optimi za tio n. 3 17- 323 steps in. 320-32 1 Stale signal. 476 Statetype. 463-466 Static random access memory (SRAM). 261-262. 271 Steenn g (of sound). 2 1 I. 2 12 Stereo speaker. 2 10 SLOre instruction . 429-43 1, 434 Store operations. 423-424 Structure (in combinatio nal logic descripti on). 447-452 Structured AS ICs. 383. 408 Subsening (i n program lang uage ). 258 subtract instruction. 435-437 Subtraction (using addition). 195- 196 Subtraction method. 13- 14. 505 SubtracLOr(s). 190-200 detecting overR olV in. 198-200 examples using. 191 - 194, 198 for positive numbers. 190-194 usi ng adder 10 build a. 197-200 Sum. 48 Summation circuits. 2 14--2 15 Sum-of-absolute-differences (SAD): wilh concu rrency (example). 348-349 design example. 241 - 244 examples using C code. 254-258 Sum-of-minterms form. 63-65 Sum-of-products. 50 Superscalar processor. 44 1 SlI'itch(es). 3 1-35 and discrete transistors. 33 Duallnline Package. 171 - 172 and integrated circuits. 33-34 relays in. 32 sliding (exa mple). 306-307 and vacuum tubes. 32-33 Switching algebra. 496. 497 Swilch matrices. 394-396. 398-399. See also Programmable inlerconn ec ts Synchronizer. bunon press (exam ple). 123- 124 Synchronous circuit. 102 Synchronous clear. 164 Synchronous clea ring. 184 Synchronous reset in puts. 134- 135 Synchronous se t. 164 Synchronous Sci inputs . 135
2
Index -4 539 Systems: d~tector. 17- 19. 21 digital. 17- 18 embedded. 4 SystemC. 450-45? 454-4 470-471 . 474-475 479-4~5. 458-463. 465-466 468 System-on-a-chip (SOC 0. 488-491 ' . T ). 408-409 Tables. implication. 318- 319 Tabular methOd. 311 - 312 ialking doll (example). 269-27\ ap (as mathematical te rm). 282 Technology rna ' Telephones. 8 PPlOg. 387 Temperat ure averager (e Temperature histo . Xample). 175 154-155 ry display (example). 109-111 Terms: . combining. to eliminate . prOduct. 50 a vanable. 297
Terminal count (counter OUI Testbenches. 455-459 put). 181 T flip-flops. 131 Three-cycles-high laser . ~mer (example): altern ative binary comroller for. 1 2c:.~~2 '"g for. 324 first deSign. poorly done. 111-112 FSM for. 115 using one-hot encOding. 326 3-D Images (ultrasound). 216 Three-mstruction prograrnmabl control unit for. 432-434 e processors. 428-434 datapath for. 431-433 first in truction set in. 428-431 Three-state driver. 206 Throu2hput (in Pipe . I'lOe regISters) . 347 Timer(s): . as coumer type. 187-188 Tthree-cYCles-high laser. 111-112. 115. 120-122 mllng analYSIs. 254 Timing diagrams. 20 Timing issues. with Mealy FSMs. 331-332 Tradeoff(s): See also Optimization(s) and algonthm selection. 356 among IC technologies. 409-110 datapath omponenL 333-345 defined. 29at higher vs. lo\\'er design 1e\-eL. 355 m RTL design. 34>-354 bet\\'":n serial and concurrent computation. 35+-355 Traffic Itght sensors. I Tmnsdu rs. 9. 210
540
Index
Transfonllation operations. 423-124
Transistors: CMOS. 35-37. ~ 1.42 discrete. 33 nMOS. 35. 36. ~2-44. 73 pMOS. 37. 42-44. 73 Transitions. 11 4 Transparent latch. sec Level-sensitive SR kl.l ch
Truth table(s). 42 and Boolean func tions. 56-58 as Boolean function standard representation. 62- 63
defined. 56 Tubes. vac uum. 32-33 Two-level logic adders. 334 Two-level log ic implementations. 67
Two-level logic size optimi zation. 296-3 15 automation of. 308-3 15 and don '( care input corn b i n ~lI i ons. 305-307 and K-maps. 298-306 usi ng algebraic methods. 296-298 Two's complement. 196- 197 building a subtractor using adders and, 197- 200
defined. 196 detecting overfl ow using. J 99-200 type declaration. 463 type statement. 463 Typewriters. 71
u Ultrasound (term). 210 Ultrasound imaging. 2 10
Ultrasound machines. 209-216 beamfonner in. 210-2 13 digital circuits in , 213-215
Vacuum lUbeS. 32-33 Variable(s). 49. ~97 combining temlS to elimintllc 3, 297
generic. 503 Veri log (hardware description language), 254, 258. 449-450.453-454.457.460.462.464-465,467. 469-470. 473-474,477-479.484-487 Very Large Instruction Word (V LlW) processor. 44 1 Very-large scale integration (V LSI), 34 VHDL (hardware description language). 254. 258, 447-449. 452-453. 456. 459-46 1. 463-464. 467-469. 47 1-473.475-477. 480-484 Video. digiti zed. 8,244 Video compression (examples): usi ng C code. 254-256 using sum-of-absolute differences (SAD) design. 24 1-244 Video display. giant. 412-416 Vinex II Pro platfo rm (Xilinx). 409 VLlW (Very Large Instruction Word) processor, 44 1 VLSI (very-large scale integration). 34 Volati Ie memory. 265 Voltage. 3 1
w wai l for statement. 46 J wai tO function. 458, 462 Wait state. 330 Wall (uni t). 357 Waves. cosine. 364-366 Wavefonn (of inputs), 84 Weight sampler (example). 153-154 Western Union. 8 While loop statements, 256
future challenges with . 216
Wireless commu nica tion. 16 J
moniLOr in. 2 J 3 scan converter in. 213
Wire signal, 457 wi res OUtput, 450. 453 Word (data item), 258 Wrapping around (co unters). 18 1 Wristwatch, beeping (example): using combined MooreiMealy machine, 333 using Mealy machine, 33 1 writeO function. 455 Write pan, 205
signal processor in. 2 13 transducer in, 2 10
Unique complement, 499 Uniting theorem. 297 Universal gates, 75, 384 Universal Serial Bus (US B), 161 Up·counters, 181-183, 471-475 Up/down counters. 184 US B (Uni versal Serial Bus), 161 use statement, 476
G
v
X XNOR gates, 74. 75 XOR gates. 74, 75
