Digital circuits.pdf

1

CHAPTER

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4 15

DIGITAL CIRCUITS NUMBER SYSTEM In general, in any number system there is an ordered set of symbols known as digits with rules defined for performing arithmetic operations like addition, subtraction, multiplication and division. A collection of these digits makes a number which in general has two parts-integer and fractional. The digits in a number are placed side by side and each position in the number is assigned a weight or index. Table 1 below gives the details of commonly used number systems. Table 1 Symbol used Weight assigned example (di or d –f) to position

Table 2 : 4-bit binary numbers and their corresponding decimal numbers. Decimal Number

Binary Number B3

B2

B1

B0

D1

D0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

2

0

0

1

1

0

3

0

1

0

0

0

4

0

1

0

1

0

5

0

1

1

0

0

6

Number System

Base or radix (b)

Binary

2

0,1

2 –i

2 –f

1011.11

0

1

1

1

0

7

Octal

8

0,1,2,3,4

8 –i

8 –f

3567.25

1

0

0

0

0

8

Decimal

10

0,1,2,3,4,5

10 –i 10 –f

3974.57

1

0

0

1

0

9

Hexadecimal

16

0,1,2,3,4,5,6,7,8 A,B,C,D,E,F

16 –i 16 –f

3FA9.56

1

0

1

0

1

0

1

0

1

1

1

1

1

1

0

0

1

2

1

1

0

1

1

3

1

1

1

0

1

4

1

1

1

1

1

5

Binary Number System The number system with base (or radix ) two is known as the binary number system. Only two symbols are used to represent numbers in this system and these are 0 and 1, these are known as bits. It is a positional system, that is every position is assigned a specific weight left - most bit is known as Most Significant Bit (MSB) and the right - most bit is known as the Least Significant Bit (LSB). Any number of 0s can be added to the left of the number without changing the value of the number. A group of four bits is known as nibble and a group of eight bits is known as a byte. Table 2 shows binary numbers and their equivalent decimal numbers.

Octal Number System It is one of the popular number system. There are 8(2 3) combinations of 3-bit binary numbers. Therefore, sets of 3-bit binary number can be conviently represented by octal numbers with base 8. Hexadecimal Number System Hexadecimal means 16. These are 16 combinations of 4-bit binary numbers and sets of 4-bit binary number can be entered in the microprocessor in the form of hexadecimal digits. Since 16 digits are used, the heights are in powers of 16. The decimal equivalent of a hexadecimal string equals sum of all hexadecimal digits multiplied by their weights.

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2 e.g., (F 8 E · 2 B)16 = F × 162 + 8 × 161 + E × 160 + 2 × 16–1 + B × 16–2 = 15 × 162 + 8 × 161 + 14 × 16 + 2 × 16–1 + 11 × 16–2 2 11 + = 3840 + 128 + 14 + = (3982.16796875)10. 16 256

NUMBER CONVERS IONS Binary-Decimal Conversion Any binary number can be converted into its equivalent decimal number using the weights assigned to each bit position. Since only two digits are used, the weights are powers of 2. these weights are 20 (Units), 21 (twos), 22 (fours) 23 (eights) and 24 (sixteen). If longer binary number involved, the weights continue in ascending powers of 2. The decimal equivalent of a binary number equals the sum of all binary number equal the sum of all binary digits multiplied by their weights. Example 1: Find the decimal equivalent of binary number 11111. Solution: The equivalent decimal number is, = 1 × 24 + 1 × 23 + 1 × 22 + 1 × 21 + 1 × 20 = 16 + 8 + 4 + 2 + 1 = ( 31 )10 Decimal-to Binary Conversion Any decimal number can be converted into its equivalent binary number. For integers, the conversion is obtained by continuous division by 2 and keeping track of the remainders, while for fractional parts, the conversion is effected by continuous multiplications by 2 and keeping track of the integers generated. Example 2: Express the 25.5 decimal number in the binary form. Solution: Integer Part: Thus, (25)10 = (11001)2 2 25 2 12 — 1 2 6 —0 2 3 —0 2 1 —1

Example 3 : Convert conversion (444.499)10. Solution : Division Generated Remainder 444 / 8 55/ 8 4 ® 6/8 7 ® 0/8 6 ® On reading the remainders from bottom to top, the decimal (444)10 ® (674)8. Now, fractional conversion Multiplication Generated Integer 0.499 ´ 8 = 3.992 3 0.992 ´ 8 = 7.936 7 7 0.936 ´ 8 = 7.488 0.488 ´ 8 = 3.904 3 The process gets terminated when significant digits are acquired. Thus, octal equivalent is (444.499)10 = (674.3773)8

Octal-Binary Conversion It can be explained through the following example: To convert (377)8 into binary, replace each significant digit by its 3-bit binary equivalent. (377)8 = 3 7 7 = 011 111 111 Thus, (377)8 = (011111111)2 Binary-Hexadecimal Conversion e.g., (10100110111110)2 = (0010 1001 1011 1110)2 = (2 9 B E)16 × 1 Hexadecimal-Binary Conversion It can be explained through an example. To convert (1D5)16 into binary, replace each significant digit by its 4-bit binary equivalent. (1D5)16 = 1 D 5 = 0001 1101 0101 Thus, (1D5)16 = (000111010101)2

BINARY ARITHMETIC Table 3 will illustrates the all four mathematical operations. Table 3 Addition

Subtraction Multiplication

Division

2 0 —1 Read down to up Fraction part 0 . 5

0+0=0

0–0 =0

0×0=0

0/1 = 0

0+1=1

1–0 =1

0× 0=0

1/1 = 1

1+0=1

1–1 =0

1× 0=0

0/0 = No

´

1 + 1 = 10

10 – 1 = 1

1× 1=1

1/0 = No

2

1 . 0 i.e., 0.510 = 0.12 Therefore 25.510 = 11001.12

Decimal-Octal Conversion This can be achieved by dividing the given decimal number repeatedly by 8, until a quotient of 0 is obtained.

SIGNED NUMBERS Representation for signed binary numbers: (i) Signed and Magnitude: In this representation, MSB is used to represent sign (0 for positive and 1 for negative) and remaining bits are used to represent magnitude of the number. e.g., binary 6-bit number 011010 represent a positive number and its value is 26, where as 111010 represents a negative number written as –26.


3 (ii)

One’s complement notation: In a binary number, if we replace each 0 by 1. and each 1 by 0, we obtain another binary number which is one’s complement of the first binary number. e.g., while (0111)2 represents (+7)10, (1000)2. In general, maximum positive and negative number that can be represented by (2n– 1 – 1) and – (2n–1 – 1) respectively. (iii) Two’s complement notation: By adding 1 to the one’s complement of a binary numbers we get two’s complement of that binary number. e.g., 0101 represents +5, where as its complement, 1011 (1s complement +1) represents –5.

CO D ES 1.

BCD code Þ Binary coded decimal Þ Weighted code Þ 4 bit code Þ 8421 code Þ Each decimal digit is represented with 4 bit. Decimal BCD Excess 3 code

2.

0 1

0000 0001

0011 0100

2 3

0010 0011

0101 0110

4 5

0100 0101

0111 1000

6 7 8

0110 0111 1000

1001 1010 1011

9

1001

1100

1010ü 1011ïï 1100ïï ý invalid BCD code or don ' t care. 1101ï 1110ï ï 1111ïþ Þ During Arithmetic operation if invalid BCD present the add 0110 to got correct result. Þ For write BCD code each digit (decimal) is write separately in BCD. e.g. (534)10 = (01010011 0100)BCD. Excess – 3code Excess – 3 code = BCD + 3 Unweighted code 4 bit code.

Decimal 0 1 2 3 4 5 6 7 8 9

Excess – 3 code 0011 0100 0101 0110 0111 self complement 1000 1001 1010 1011 1100 Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

4 Þ Þ Þ

It is self complement code. Only unweighted code which is self complement is Excess 3-code. The code which addition is 9 is self complement code.

eg. 2421ü 3321ïï ý weighted 4311ï 5211ïþ Q.

Write 2421 weighted code. Decimal 0 1 2 3 4 5 6 7 8 9

3. Þ Þ Þ Þ

ü ï ï ý self compemented ï ïþ

2421 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111

self complement

Binary to Gray code (A) Binary to Gray:Unweighted code. Successive no. is differ by 1 bit. Also called unit distance code. Also cyclic code, Reflective code and Minimum error code. B3 B 2 B1 B0 Binary 1 0 1 1 1 1 1 0

G3 G2 G1 G0

B3

G3

B2

G2

B1

G1

B0

G0

(B) Gray to Binary:-

G3 G2 G1 G0 1 1 1 0

B3 B2 B1 B0 1 0 1 1 Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

5 G3

B3

G2

B2

G1

B1

G0

B0

DIGITAL LOGICAL GATES OR Gate: Its symbol is given in the fig. 1(a) & its truth table is 4(a) Table 4(a)

Inputs

Output R= P+ Q

P Q 0 0 0 : 0 1 1 1 0 1 1 1 1 AND Gate: Its symbol is given in the fig. 1(b) & its truth table is 4(b) Table 4(b) Inputs P 0 0 1 1

Q 0 1 0 1

P Q

R=P+Q Fig.OR 1 (a)Gate : OR Gate

Output R=P.Q

P

R=PQ

Q

0 0 0 1

Fig. 1 (b) : AND Gate

NOT Gate (Inverter): Its symbol is given in the fig. 1(c) & its truth table is 4(c) Table 4(c) Inp ut P 0 1

P R=P Fig. 1 (c) : NOT Gate

Ou tp ut R 1 0

NAND Gate: Its symbol is given in in the fig. 1(d) & its truth table is 4(d) Table 4(d) Inputs P 0 0 1 1

Q 0 1 0 1

O utpu t R

P

R=P.Q

Q

1 1 1 0

Fig. 1 (d) : NAND Gate

NOR Gate: Its symbol is given in the fig. 1(e) & its truth table is 4(e) Table 4(e) Inputs P 0 0 1 1

Q 0 1 0 1

O utpu t R 1 0 0 0

P Q

R=P+Q Fig. NOR 1 (e) :gate NOR Gate


6

BOOLEAN ALG EBRA • •

It is used to simplify the design of logic circuits. Here we make use of boolean logic operations, properties of boolean algebra & binary addition & multiplication. Commutative Property: P+Q = Q+P Associative property: P + (Q + R) = (P + Q) + R Distributive property: P + QR =(P + Q)(P + R) Some more Boolean laws : (1) P + 0 = P

(2) P + 1 = 1

(3) P + P = P

(4) P + P = 1

(5) P.1 = P

(6) P.0 = 0

(7) P.P = P

(8) P.P = 0

(9) P = P

(10) P = P

Demorgan’s Theorems :

A B

Sum

•

PQ = P + Q

•

P + Q = P.Q

Half Adder In order to solve arithmetic operations, this type of devices are introduced. Half Adder is used for the addition of two bits. Half adder generates two outputs as SUM and CARRY. The logical diagram along with truth table 5 is depicted. Sum = A Å B Carry = A.B Truth Table Table 5

Cout

A

Fig. 2 : Half adder

B

SUM (S)

CARRY (C)

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

FULL ADDER

Q1

VDD Q2 Q3

A B

Q4 Schematic Fig. 3

C

A full adder is a device capable of adding three bits as shown in figure. Full Adder generates two outputs same as half adder. Sum = A Å B Å C Carry = AB + BC + CA Truth Table Table 6 A 0

B 0

Carry-in (C in ) 0

SUM (S) 0

CARRY (C) 0

0 0 0

0 1 1

1 0 1

1 1 0

0 0 1

1 1

0 0

0 1

1 0

0 1

1 1

1 1

0 1

0 1

1 1

CANONICAL NORMAL FORMS Sum of Products (SOP) Method It is an expression which denotes the logical sum of two or more logical product terms. It is basically an OR operation of AND operated variables such as Y = PQ + QR + PR, or Y = PQ + P R + QR Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

7 Product of Sums (POS) Method It is an expression which denotes the logical product of two or more logical sum terms. It is basically an AND operation of OR operated variables such as Y = (P + Q)(Q + R)(R + P ), or Y = (P + Q + R)(P + R )

Karnaugh Map (K-Map) Simplification It is a technique for simplifying & manipulating switching expressions. It is a modified form of a truth table where information contained either in truth table or in POS or in SOP form is represented on the K-map.

Basic Rules In an s-variable K-map, there are are 2s cells. Each cell represents one combination of s-variables. Each single cell that contains a ‘1’ represents a minterm in the function & each minterm can be thought of as a ‘product’ term with s variables. • Each single cell that contains a ‘0’ represents a maxterm in the function & each maxterm can be thought of as a ‘sum’ term with s variables. • To combine variables, use groups of 2, 4, 8 etc. • Thus, K-maps are tables of rows & columns with either 1’s or 0’s of SOP & POS representation The decimal codes are given inside each cell at the bottom right corner (which is basically a combination of corresponding variables). The K-map for 2, 3 & 4 variables can be drawn as shown in fig. 4 (a), 4 (b), 4 (c). • • •

For example R = PQ + PQ , thus its truth table in table 7 & graph in fig. 4 (d) will be drawn as shown :

Don’t Care Conditions • • •

Functions that have unspecified output for some input combinations are called incompletely specified functions. Unspecified minterms of a functions are called 'don't care' conditions. We simply don't care whether the value of 0 or 1 is assigned to F for a particular minterm. Don't care conditions are represented by X in the K-Map table. Don't care conditions play a central role in the specification and optimization of logic circuits as they represent the degrees of freedom of transforming a network into a functionally equivalent one.

B

A

AB 0 0 0

1 2

1 1

3

C

00 0

01 2

11 6

10 4

1 1

3

7

5

0

Fig. 4 (a) : Two variable

Fig. 4 (b) : Three Variable

AB 01

11

10

4

12

8

5

13

9

2

7

15

11

3

6

14

10

CD 00

00 0

01

1

11 10

Fig. 4 (c) : Four variable Table 7

P 0 0 1 1 P

Q 0 1 0 1 Q

0 0 1

R 1 0 1 0 1 0

0 1 1 1 2 0 3 Fig. 4 (d)


8

DIGITAL IC FAMILIES (a)

+ B Q1

A

C

Q2

Fig. 5 (a) : Schematic diagram A C B Fig. 5 (b) : Symbol

(b)

• •

130 W

1.6 K

4K

Resistor Transistor Logic • It is a digital circuit which has registers as input network & bipolar junction transistors as the switching device. • Here an RTL NOR gate in fig. 5 (a) with its symbol in fig. 5 (b) is shown, where we have taken two inputs. • When input A is on or gets high, Q1 will be conducting in nature, pulling the output pin C to the ground. Whereas when input B is on or gets high , Q2 will be conducting in nature, pulling the output pin C to the ground. • Characteristics of RTL family: - High power dissipation. - Poor noise immunity. - Low speed of operation. Transistor-Transistor -logic (TTL)

Q3 A B

Q2

Q1

C Q4

1K

C

B

(c)

Fig. 5 (d) : Symbol

OR D VCC

NOR C

Q1

Q5

Q6

D1

Q3 Q4

D2 2.43 K

Q2

(d)

A B -VCC Fig. 5 (e) : Schematic diagram

A B

C NOR

A B

D

Secondly, if any of A or B goes low, Q1 will conduct the emitter current, saturating it and pulling Q2 base to the ground. This will cause Q3 to conduct and Q4 to be cut-off. Logically, these families are developed to conduct only in the on and off conditions. This means that the output line always has low impedance, reducing the effect of noise. The fig. 5(c) shows the NAND gate TTL and 5 (d) schematic diagram of TTL circuit. Emitter-Coupled-Logic (ECL) • This is the fastest logical family and the only family that does not operate fully saturated or cut-off, preventing the adverse effects of diffusion capacitance.

•

300

315

If both the inputs, A and B are high, then Q1 has no emitter current, but its base collector junction is forward biased and constitutes the base current to the Q2. This will result in the transfer of base current to Q4, causing it to conduct. On the other side, Q2 collector will go low causing Q3 to be cut-off. Therefore, in this condition, Q4 is conducting and Q3 is cut-off.

•

Fig. 5 (c) : Schematic diagram

A

TTL is introduced to overcome the low speed problem of DTL.

When A goes high, causing Q2 Collector to be low, which lowers down the base and emitter (both) of Q1 generates a low NOR gate Output. At the same time, Q4 emitter goes high, tending to cut it off and Q5 base goes high as well as Q5 emitter and consequently the OR output. D1 and D2 provide the constant voltage supply to Q6 base and therefore a constant voltage to the Q4 base to operate it in Common base Amplifier mode. The fig. 5 (e) shows the Schematic diagram and 5 (f) symbol of ECL Complementary Metal Oxide Semiconductor (CMOS) • This logical family is mostly used in chip designing, as it 5 (g) is the most power consuming logical family and carries less space. Figure show the schematic diagram of CMOS. According to the figure, working can be explained as -

•

When A and B both inputs are high, then Q1 and Q2 get cut-off whereas Q3 and Q4 are ON, which takes C to ground.

•

When A goes ground, Q1 conducts and Q3 is in OFF mode, so that C goes HIGH.

•

When B goes ground, Q4 will be Cut-off and Q2 is turned ON, which leads C high. From above discussion, it is clear that just like TTL, in CMOS one transistor is

OR Fig. 5 (f) : Symbols Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

9 always conducting.

Q1

VDD Q2

A

C

Q3 A

Q4 Fig. 5 (g): Schematic diagram

C

B

B

Fig. 5 (h) : Symbol

Specification Table for Logical Family Devices Specification

RTL

TTL

CMOS

Power supply

3.8 Volts

+5 Volts

3-15 Volts

Propagation delay

12 nsec

15 nsec

25 nsec

Power Dissipation

30-100 mW

100 mW

10 nW

Noise Margin

0.2 Volts

0.4 Volts

45%of VD D

Fan Out

4

10

>50

MULTIPLEXER A Multiplexer is a Data selector, which gets several input signals to the single output. The method of selecting one of the several inputs is controlled by Control lines. We can define multiplexer as "a device consists of n-input line and having a single output line to process". Generally multiplexers are used in parallel - to serial conversion of data because it is used for routing several signals to the same destination, for example bus, synchronous transmission etc. In other words, we can say that a multiplexer is a digitally controlled multi-position switch. The fig. 6 (a) shows the block diagram of a multiplexer: Fig. 6 (b) shows the example of a 4 ´ 1 multiplexer along with two control lines: Table 8 Input Input Output S1 S2 Y 0 0 D0 0 1 D1 1 0 D2 1 1 D3 From table 8 output, Y = S1S2 D0 + S1S2 D1 + S1S2 D 2 + S1S2 D3 Application of MUX: • Data Routing • Logic Function generator • Control Sequencer • Conversion parallel to series

m select signals

n input signals

Multiplexer

1 output signal

Fig. 6 (a): Block diagram of multiplexer S1

S0

D0 D1 Y

D2 D3

Fig. 6 (b): 4-to-1 multiplexer m select signals

DEMULTIPLEXER The working of a demultiplexer is exactly opposite to that of a multiplexer. Demultiplexer receives information from a single line and transmits it to several lines. That is why demultiplexer is used in serial-to-parallel conversion and Data Distributors. The fig. 7 (a) shows the block diagram of a Demultiplexer with one input signal, m select signals and n output signals. Fig. 7 (b) shows the example of 1 ´ 4 demultiplexer along with two control lines.

1 input signal Demultiplexer

n output signals

Fig. 7 (a): Block diagram of demultiplexer


10 Table 9

Data input D

S0

S1

Data Control Control Output input input Input D S1 S2 Y3 Y2 Y1 Y0

Y0 Y1

0

0

0

0

1

0

0

D

0

1

0

0

D

0

0

Y3

D

1

1

D

0

0

0

FLIP FLOPS • •

Q A2 Fig. 8 (a) : Basic Memory Cell

It is an electronic circuit that has two stable states & can be used to store state information. It is basically a bistable multivibrator or latch or toggle. It can either be simple or clocked (synchronous or edge triggered). It can store information either in 1 or in 0 form.

•

It has two outputs; Q and Q shown in fig. 8 (a) which are always complement of each other.

•

In set state, Q is HIGH (logic 1) and Q is low (logic 0);

• (a)

In reset state, Q is HIGH (logic 1) and Q is low (logic 0); For a flip flop to act as a memory devices it should retain information stored in it. It is of 4 basic types: S-R, J-K, D & T. S-R (Set-Reset) Flip-flops •

It has two inputs: set & reset & two outputs: Q & Q .

•

The two outputs Q & Q are complement to each other.. It can be designed by using NOR gates or NAND gates. Here we have created an S-R flip flop using NOR gates with its symbol as shown in the fig. 8 (b) and 8 (c)

• • Table 10

R(Reset) Actions

S

R

Qn+1

Q n+ 1

0

0

Qn

Qn

No Change

0

1

0

1

Reset

1

0

1

0

Set

1

1

?

?

Forbidden

R S

• •

Q

CP (clock pulse) S

Q¢

Fig. 8 (d) : Clocked S-R Flip-flop

1

Q

2

Q

Q Q S(Set)

(b) R

D

D

Q

Outputs

0

D

•

Inputs

0

Y2 Fig. 7 (b) : 1-to-4 demultiplexer

A1

D

½ 7402 Fig. 8 (b) : Block diagramFig. 8 (c) : NOR based S-R flip-flop Feedback is developed as there is a cross-coupled connection from the output of one gate to the input of the other gate, thus classified as asynchronous sequential circuits. Its truth table can be made as shown in Table 10.

Clocked S-R Flip-flop The clocked SR flip-flop shown in fig. 8 (d) consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop. With both S = 1 and R = 1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flipflop is indeterminate, i.e., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse. Q n +1 = Sn + R n¢ Q n


11 Table 11: S-R Flip-flop Truth Table

Q 0 0 0 0 1 1 1 1

(c)

S 0 0 1 1 0 0 1 1

R 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 Indeterminate 1 0 1 Indeterminate

The disadvantage of S-R flip-flop is for S = 1, R = 1 output cannot be determined. This can be eliminated in J-K flip-flop. S-R flip flop can be converted to J-K flip-flop by using the two equation S = JQ’ and R = KQ. J-K Flip-flops : •

1

J CLK K

2

R=K.Q

S

Q

R

Q

Fig. 8 (e): J-K flip-flop using S-R flip-flop J

Q

K

Q

Fig. 8 (f): Graphic symbol of J-K flip flop

It has two inputs: J & K & two outputs: Q & Q .

• • •

The two outputs Q & Q are complement to each other.. It can be designed by using S-R flip flops. Here we have created a J-K flip flop using clocked S-R flip flop with its symbol as shown in fig. 8 (e) and 8 (f) respectively. • Its truth table can be made as shown in Table 12 The Master-Slave JK Flip-flop The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse.

(d)

S=J.Q

The outputs from Q and Q from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip-flop being connected to the two inputs of the “Slave” flip-flop. This feedback configuration from the slave’s output to the master's input gives the characteristic toggle of the JK flip-flop as shown in fig. 8 (g). The input signals J and K are connected to the gated “master” SR flip-flop which “locks” the input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip-flop is the inverse (complement) of the “master” clock input, the “slave” SR flip-flop does not toggle. The outputs from the “master”flip-flop are only “seen” by the gated “slave” flip-flop when the clock input goes “LOW” to logic level “0”. When the clock is “LOW”, the outputs from the “master” flip-flop are latched and any additional changes to its inputs are ignored. The gated “slave” flip-flop now responds to the state of its inputs passed over by the “master” section. Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flipflop are fed through to the gated inputs of the “slave” flip-flop and on the “Highto-Low” transition the same inputs are reflected on the output of the “slave” making this type of flip-flop edge or pulse-triggered. Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a “Synchronous” device as it only passes data with the timing of the clock signal. D Flip-flops :

Table 12

"Master Latch"

"Slave Latch"

J

Q

Clk Q

K Clk

Fig. 8 (g): The Master-Slave JK Flip-Flop

D

1

S(Set) 3

Q

4

Q

CLK 2

R

(Clear) Using NAND gates Fig. (a) 8 (h) : D-flip-flopUsing NAND gates

D

Q

•

It has only one input known as D (Delay) & two outputs Q & Q .

• • •

CLK Q It can be designed from NAND gates or through S-R flip flops. It is given in the fig. 8 (h) along with its symbol in fig. 8 (i). Fig. 8 (i) : Logic symbol Its truth table is shown in Table 13 Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

12

(e)

CLK 1 1 0

T Flip-flops • It is also known as trigger or toggle flip flop.

J

Q

•

CLK K

Q

• •

•

Fig. 8 (j) : T flip flop using a J-K-flip flop Q

T

Table 13 Input (D) Output (Qn +1) 0 0 1 1 X No change

It has only one data input denoted by T, a clock input & two outputs Q & Q . It can be designed by using J-K flip flop where J & K inputs are wired together. It is given in fig. 8 (j) with its symbol fig. 8 (k). Its truth table is shown here: Table 14

CLK 0 0 1 1

CLK Q

Fig. 8 (k) : Block diagram of T flip flop

Input (T) Output (Qn +1) 0 0 1 1 0 1 1 0

CO UN TERS

Q3

J3

Q3 K 3

Q2

J2

Q2 K2

J1

Q0 J0

Q 1 K1

Q1

Q0 K0

High

CLR

Fig. 9 (a) : Synchronous counter

A counter is a special kind of register, designed to count the number of clock pulses arriving at its input. It is one of the most useful subsystem in a digital systems. The input to this counter is a rectangular waveform called clock. Each time the clock signal changes state from low to high, the counter will add one (1) to the number stored in its flip flop. This means the counter will count the number of clock transitions from low to high. A clock having a small circle (bubble) in the input side would count clock transitions form high to low. Since clock pulses occur at known intervals, the counter can be used as an instrument for measuring time and therefore frequency. There are basically two different types of counters Synchronous and Asynchronous. (a) Synchronous counters: The ripple counter is the simplest of all kinds of counters. But the problem with it is its delay time. In a ripple counter each flip - flop has a delay time and these delay times are additive. Therefore the total "settling" time for the counter is equal to the delay time multiplied by total number of flip - flops. This problem can be overcome by the use of a synchronous or parallel counter. Here every flip-flop is triggered in synchronism with the clock. The fig. 9 (a) shows how to build a synchronous counter with positive - edge triggered flip - flop. Here the clock pulses drive all the flip -flop in parallel. The J and K inputs of Q0 flip-flop are tied to a high voltage. Therefore, it responds to each positive clock edge. But the remaining flip flops can responds to the +ve clock edge with certain conditions. The Q1 flip flop toggles on the positive clock edge only when Q0 is 1, the Q2 flip flop toggles only when Q1, Q0 are 1; the Q3 flip flop toggles only when Q2, Q1 and Q0 are 1. That is , a flip - flop toggles on the next +ve clock edge if all lower bits are 1. Here is the counting action. A low CLR reset the counter. Q = 0000. When the CLR goes high, the counter is ready to go. The first +ve clock edge sets Q, therefore Q = 0001. (i) Ring Counter: A ring counter is a shift-left register because the bits are shifted left one position per positive clock edge. But the final output is feedback to the D0 input. This kind of action is known as “rotate left” the bits are shifted left and fed back to the input. The following fig. 9 (b) is a ring counter built with D flip flops. When CLR goes low, the initial o/p word is Q = 0001. The first positive clock edge shifts MSB into LSB. The other bits shift left one position. Therefore the output word becomes Q = 0010.


13 The second positive clock edge causes another rotate left and o/p word becomes Q = 0100. After third positive clock edge, the output word is Q = 1000. The fourth positive clock edge starts the cycle and rotate left produces Q = 0001. The stored 1 bit follows a circular path. This is why the circuit is called a ring counter. By adding more flip-flops we can build a ring counter of any length. (ii) Decode counter ( Mode - 10 counter) : A counter with 10 distinct states is known as a decade counter. This counter counts 10 sequences and reset on 10th clock pulse. That is, the circuit count from 0000 to 1001 and on the tenth clock pulse, it generates its own clear signal and count jump back to 0000. The following shown in fig. 9 (c) is the mod –10 counter design. The counter can be reset, if the AND gate output is low. This can be happened with a low CLR or low Y. Initially low CLR produce Q = 0000. when CLR is high, the counter is ready and count sequence progress. The output of the NAND gate is, Y = Q3 Q1. This output is high for the first nine states ( 0000 to 1001). Nothing happens when the circuit is counting from 0 to 9 on the tenth clock pulse, the Q word becomes; Q = 1010, which means that Q3 and Q1 are high. Then immediately Y goes low, forcing the counter to reset to Q = 0000. Q3

J3

Q2

J2

Q1

J1

Q3

K3

Q2

K2

Q1

K1

Fig. 9 (b) : Ring counter

Q0PR J0 Q0

CLK

K0

CLR Y

(b)

Fig. 9 (c) : Decode counter Asynchronous counter (ripple counter): When the output of a flip-flop is used as the clock input for the next flip-flop we call the counter as a ripple counter or asynchronous counter. The triggers move through the flip-flops like ripple in water — because of this, the over all settling time is the sum of the individual delays. Fig. 9 (d) shows a 3 bit asynchronous counter with timing diagram. GET

GET

GET

CLR

CLR

CLR

8

Fig. 9 (d) : Asynchronous counter

ANALOG TO DIGITAL CONVERTER (A/D) • •

It is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity’s amplitude. It involves two basic steps: quantizing & encoding. Quantizing: Breaking down of analog values into finite states. Encoding: Assigning a digital number to each state & matching it to the input signal. Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

14 •

Clear Clock

Binary Counter

MSB Digital output

– + VS Analog input

LSB

D/A

•

A/D converter using a counter

Fig. 10 : A/D converter using a counter

DIGITAL TO ANALOG CONVERTER • •

a0 2R R

a1 2R

a2 2R

an–2 2R

2R

R R R Fig. 11: n-bit R-2R ladder

S

Vi

V0 C

(a) Schematic diagram

V0 C

Vi Control gate

C

V0 + LM 102

(b) Practical diagram Fig. 12 : Sample-and-hold circuit

+VCC R RC1 C 1 1 VC1 + Q1

R2

•

an–1

C2 Rc2 - + Vc2 Q2

Fig. 13(a) : Astable Multivibrator

Vout

There are two ways to improve its accuracy: Either by increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal. By increasing the sampling rate which increases the maximum frequency that can be measured. They are of six types: simultaneous or flash type, counter type, continuous type, successive approximation type, single slope type & dual slope type. Fig. 10 shows a A/D converter. It involves transforming the binary values 0’s & 1’s into an analog signal which represents the binary data. It involves two steps: sampling & quantizing. Sampling: Measurement at regular intervals of the amplitude of varying waveform. Quantizing: Breaking down of analog value into finite states. It is used for the generation of audio signals. There are two types of D/A converters: resistive divider & R-2R ladder type. Fig. 11 shows a n-bit R-2R ladder.

SAMPLE & HOLD CIRCUIT Sample & hold circuit is a device that is generally used to convert analog signal into its digitised form i.e. when an analog signal is applied at the input terminal of sample & hold circuit, it assigns a digital level to every pulse with the help of the switch. The output so generated by sample and hold circuit is used to convert data into digital signals by means of analog-to-digital convertor (A/D). The fig. 12 (a) shows the schematic circuit arrangement of the sample and hold circuit, in which a switch is connected in series with a capacitor. In practical experimentation, the switch can be a relay, BJT or MOSFET controlled gating signal. According to the fig. 12 (b), MOSFET is used as a switch because MOSFET is an excellent chopper due to its offset voltage, which is less than BJT’s. Working: When a negative pulse is applied to switch, p-channel MOSFET will turn it ON, which causes the capacitor to hold the charge with constant time w.r.t input voltage. Whereas in absence of negative pulse, the switch is OFF and capacitor is isolated from the circuit.

MULTIVIBRATOR • • •

It is basically a two-stage switching electronic circuit in which the output of the first stage is fed to the input of the second stage & vice versa. Here, output of two stages are complement to each other. It is of three types: astable, monostable & bistable. (a) Astable Multivibrator : • It is also known as free running multivibrator. • It generates square waves without any external triggering pulse. • This multivibrator does not have stable states i.e., have two quasi stable states where it switches back & forth from one state to each other. • The time period of switching of each stage depends upon the discharge of a capacitive circuit. • Its electronic circuit is shown in the fig. 13 (a) • It is used as a square wave generator, voltage to frequency converter, used in construction of digital voltmeters etc. (b) Monostable Multivibrator : • It is also known by the name of monoshot or one-shot multivibrator or univibrator. • This multivibrator has one stable state & one quasi-stable state. • The time duration for which this multivibrator resides in the stable state is obtained by time taken for discharging an RC circuit.


15 • • •

This multivibrator changes its state when the trigger pulse is applied. Its electronic circuit is shown in the fig. 13 (b). It is used for generating a uniform width pulse, to generate clean & sharp pulses from distorted pulses, as a time delay unit etc. (c) Bistable Multivibrator • It is also known as flip flops or Eccles-Jordan circuit. • This multivibrator has two stable states. • Switching from one state to the other takes place due to the applied trigger pulse. • Its electronic circuit is shown in the fig. 13 (c). • It act as memory element in shift registers, counters, can be utilize as frequency divider etc.

+VCC RC1 R IC1 C VC1 + Q1 C2

C1 R c2 R1IR1 Vc2 Q2 R2 IB2 - V Input + BB trigger pulse Fig. 13 (b) : Monostable Multivibrator +VCC

SCHMITT TRIGGER

I1 RC1

•

IC1 I3 R1 Q1

• • •

It acts as a wave shaping circuit where a square wave can be generated from a sine wave input. The electronic circuit is a bistable circuit where two transistor switches are connected regeneratively. The two transistors used here are identical to each other which get coupled through an emitter resistor. Its electronic circuit is shown in the fig. 14. It can be used as a voltage comparator, used for wave shaping circuits.

C1

• • •

I5 R3

I6 R4

Reset -VBB

Fig. 13 (c) : Bistable Multivibrator +VCC

RC1

It is basically a programmable integrated device which has the capacity of computing & decision making & functions as the CPU of a computer. It operates & communicates with the system attached to it in binary numbers 0 & 1 called bits. Every microprocessor has a fixed set of instruction in the form of binary patterns known as machine language. These binary instructions have been given the abbreviated names called mnenomics which forms the assembly language for a given microprocessor.

I2 R I4 c2 Ic2 R IB2 2 Q2 C2

Set

MICROPROCESSOR •

IR2

I1 R1 Q1

RB Vin IE

IC2=IE Rc2 Vout

IC1+I1 C1

RE

IB2

I2

Q2

R2

Fig. 14 : Schmitt trigger

Architecture of 8085 Microprocessor •

• •

•

Its hardware model has two major segments: One includes ALU (arithmetic/logic unit) & an 8-bit register (accumulator), instruction decoder & flags. The other one includes 8-bit & 16-bit registers. An internal bus connects both the segments with various internal connections. 8085 uses 3 buses: a 16-bit unidirectional address bus to send out memory addresses. an 8-bit bidirectional data bus to transfer data & a control bus for timing signals. 8085 hardware model is given in the fig. 15 (a) D7

D6

S

Z

D5

D4 AC

D3

D2 P

D1

Accumulator ALU Flags

Register Arrays Memory Pointer register

16-Bit Address Bus 8-Bit Data Bus

Instruction Decoder Timing and Control unit

Control Signals

Fig. 15 (a) : 8085 hardware model

Do CY

Fig. 15 (c) : Flag register


16 Accumulator A (8) B

(8)

C

(8)

D

(8)

E

(8)

(8)

L

F

Data Bus 8 Lines

Flag Register

(8)

Stack Pointer (SP)

(16)

Program Counter (PC)

(16) Address Bus 16 Lines Unidirectional

Fig. 15 (b) : Programming model

Registers : The 8085 programming model fig. 15 (b) includes six registers, one accumulator, and one flag register, as shown in Figure. The 8085 has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the fig. 15 (b). They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers. Flags : The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator is larger than eight bits, the flip-flop uses to indicate a carry — called the Carry flag (CY) - is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction. Program Counter (PC) : This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location. Stack Pointer (SP) : The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. Address bus is basically a group of 16 lines named from A0 to A15 , is unidirectional in nature and helps in identifying a peripheral or memory location. Its structure is given in the fig. 15 (d). A15 A0 8085 MPU

D7 D0

Address Bus Input

Output

Real World

Data Bus Control Bus

Fig. 15 (d) : 8085 Bus Structure The address lines are split into two segments: A15-A8 & AD7-AD0. Former are unidirectional & are used for higher order address & latter are bidirectional & are used for lower order address bus as well as data bus.

8085 Addressing Modes The various formats for specifying operands are called the ADDRESSING MODES. For 8085, they are of various types are : 1. Immediate addressing: Data is present in the instruction. Load the immediate data to the destination provided. Example: MVI R,data 2. Register addressing: Data is provided through the registers. Example: MOV Rd, Rs 3. Direct addressing: Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H. Example: IN 00H or OUT 01H Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

17 4.

Indirect Addressing: This means that the Effective Address is calculated by the processor. And the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register.

Instruction Word Size The 8085 instruction set is classified into the following three groups according to word size: 1. One-word or 1-byte instructions 2. Two-word or 2-byte instructions 3. Three-word or 3-byte instructions 1. One-Byte Instructions: 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are internal register and are coded into the instruction. For example: MOV

C,A

0100 1111

4FH

Add the contents of register B to the contents of the accumulator.

ADD

B

1000 0000

80H

Invert (compliment) each bit in the accumulator.

CMA

0010 1111

2FH

These instructions are 1-byte instructions performing three different tasks. In the first instruction, both operand registers are specified. In the second instruction, the operand B is specified and the accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the implicit operand. These instructions are stored in 8-bit binary format in memory; each requires one memory location. Two-Byte Instructions: In a two-byte instruction, the first byte specifies the operation code and the second byte specifies the operand. Source operand is a data byte immediately following the opcode. Three-Byte Instructions: In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order address.

8085 Pin Diagram • The 8085 pin diagram is shown in the fig. 15 (e). • 8085 has 40 pins, needs a +4V single power supply & is able to operate with a 3-MHz single phase clock. • All these pins are divided into 6 groups: (i) Address bus includes 16 pins. (A15 - A8 & AD7 - AD0) (ii) Data bus or multiplexed address includes AD7 - AD0. (iii) Control & Status signals includes: RD & WR are two control signals used for read & write operations respectively. Three status signals to identify the nature of operation : IO / M : used to differentiate between input/output & memory operation.

+5 V

SID SERIAL I/O ports

Copy the contents of the accumulator in the register C.

SOD

5

1

2

20

40

4

28 High-order Address Bus

TRAP RST 7.5 RST 6.5 RST 5.5 INTR

6

A8

21

7 8 9 AD7

10

19

8085A READY 35 HOLD

39

AD0 12

RESET IN 36

INTA HLDA

30

ALE

29

S0

11

33

S1

38

34

IO/M

3 RESET OUT

32

RD

31

WR

37 CLK OUT

Fig. 15 (e) : 8085 Pin diagram


Control and status signals

3.

Binary Code Hex Code

Externally initiated signals

2.

Op code Operand

External signal Acknowledgement

Task

18 S1 & S0: used for identifying various operations. ALE (Address latch enable): indicates the beginning of the operation. (iv) Externally initiated signals (INTR ( Input): interrupt request used as general purpose interrupt, RST 7.5, RST 6.5, RST 5.5, TRAP (Input) HOLD (Input), READY (Input), RESET IN (v) External signal acknowledgement : (HLDA, INTA ). (vi) Serial I/O ports (SID: serial input data & SOD: serial output data). Both are used to implement serial transmission.

Programming of 8085 Microprocessor Instruction Set Categories : 1. Data transfer: One of the most important functions of a microprocessor is copying data from register (I/O or memory) source to another register (I/O or memory) called destination through Data Transfer operators. Main Operations are8-Bit Instruction set for Data transfer MOV : Move Copy a data byte MVI : Move Immediate load a data byte directly OUT : Output to port Send a data byte to an output device IN : Input from port Read a data byte from an input device HLT : Halt Stop processing and wait NOP : No operation Do not perform any operation 16-bit Instruction set for Data transfer LXI : load register pair Immediate LDAX : Load Accumulator Indirect LDA : Load Accumulator Direct STAX : Store Accumulator Indirect STA : Store Accumulator Direct INX : Increment registers pair DCX : Decrement registers pair 2. Arithmetic Operation: (a) Addition ADD : Add Add the contents of the registers ADI : Add Immediate Add 8-bit data (b) Subtraction SUB : Subtract Subtract the contents of the registers SUI : Subtract Immediate Subtract 8-bit data (c) Increment and Decrement INR : Increment Increase the contents of register by 1 DCR : decrement Decrease the contents of a register by 1 3. Logical Operation: ANA : AND Logically AND the content of a register ANI : AND Immediate Logically AND 8-bit data ORA : OR Logically OR the content of a register ORI : OR Immediate Logically OR 8-bit data XRA : X-OR Exclusive-OR the content of a register XRI : X-OR Immediate Exclusive-OR 8-bit data 4. Branch Operation : (a) Jump Instruction JMP : Jump (b) Call and Return Instruction (c) Restart Instruction


19

Timing Diagram Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO / M , S1, and S0. The CLK required for the proper operation of different sections of the microprocessors. All actions in the microprocessor is controlled by either leading or trailing edge of the clock. The 3-status signals : IO / M, S1, and S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identify read or write operation and remain valid for the duration of the cycle. Table 15 shows details of the unique combination of these status signals to identify different machine cycles. Thus, time taken to execute one instruction is calculated in terms of the clock period. The execution of instruction always requires read and writes operations to transfer data to or from the memory or I/O devices. Each machine cycle consists of many clock periods/cycles, called T-states. The clock signal determines the time taken by the microprocessor to execute any instruction. The clock cycle shown in Fig. 15 (f) has two edges (leading and trailing or lagging). State is defined as the time interval between 2trailing or leading edges of the clock. Machine cycle is the time required to transfer data to or from memory or I/O devices. Table 15 : Machine cycle status and control signals Status Machine cycle Opcode Fetch (OF) Memory Read Memory Write I/O Read (I/OR) I/O Write (I/OW) Acknowledge of INTR (INTA) BUS Idle (BI) : DAD ACK of RST, TRAP HALF HOLD

IO/M 0 0 0 1 1 1 0 1 Z Z

Controls

S1

S0

1 1 0 1 0 1 1 1 0 X

1 0 1 0 1 1 0 1 0 X

RD 0 0 1 0 1 1 1 1 Z Z

WR 1 1 0 1 0 1 1 1 Z Z

INTA 1 1 1 1 1 0 1 1 1 1

X Þ Unspecified and Z Þ High impedance state

Fig. 15 (f) : Machine cycle showing clock periods

Processor Cycle The function of the microprocessor is divided into fetch and execute cycle of any instruction of a program. In the normal process of operation, the microprocessor fetches (receives or reads) and executes one instruction at a time in the sequence until it executes the halt (HLT) instruction. Thus, an instruction cycle is defined as the time required to fetch and execute an instruction. For executing any program, basically 2-steps are followed sequentially with the help of clocks • Fetch • Execute. The time taken by the microprocessor in performing the fetch and execute operations are called fetch and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as indicated in fig. 15 (g) Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

20

Fig. 15 (g) : Processor cycle Each read or writes operation constitutes a machine cycle. The 1st machine cycle of any instruction is always an OpCode fetch cycle in which the processor decides the nature of instruction. It is of at least 4-states. It may go up to 6-states. It is well known that an instruction cycle consists of many machine cycles. Each machine cycle consists of many clock periods or cycles, called T-states. The processor during (M1 cycle) puts the program counter contents on the address bus and reads the opcode of the instruction through read process. The T1, T2, and T3 clock cycles are used for the basic memory read operation and the T4 clock and beyond are used for its interpretation of the opcode. Based on these interpretations, the microprocessor comes to know the type of additional information/data needed for the execution of the instruction and accordingly proceeds further for 1 or 2-machine cycle of memory read and writes. One machine cycle is required each time the microprocessor access I/O port or memory. A fetch opcode cycle is always 1-machine cycle, whereas, execute cycle may be of one or more machine cycle depending upon the length of the instruction. Instruction Fetch (FC): An instruction of 1 or 2 or 3-bytes is extracted from the memory locations during the fetch and stored in the microprocessor’s instruction register. Instruction Execute (EC): The instruction is decoded and translated into specific activities during the execution phase. The fetch portion of an instruction cycle requires one machine cycle for each byte of instruction to be fetched. Since instruction is of 1 to 3 bytes long, the instruction fetch is one to 3-machine cycles in duration. The 1st machine cycle in an instruction cycle is always an opcode fetch. The 8-bits obtained during an opcode fetch are always interpreted as the Opcode of an instruction. The machine cycle including wait states is shown in fig. 15 (h).

Fig. 15 (h) : Machine cycle including wait states Opcode Fetch A microprocessor either reads or writes to the memory or I/O devices. The time taken to read or write for any instruction must be known in terms of the microprocessor clock. The 1st step in communicating between the microprocessor and memory is reading from the memory. This reading process is called opcode fetch. The process of opcode fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction. In order to differentiate between the data byte pertaining to an opcode or an address, the machine cycle takes help of the status signal IO/M, S1, and S0. The IO/M = 0 indicates memory operation and S1 = S0 = 1 indicates Opcode fetch operation. The opcode fetch machine cycle M1 consists of 4-states (T1, T2, T3, and T4). The 1st 3-states are used for fetching (transferring) the byte from the memory and the 4th-state is used to decode it. Thus, thorough understanding about the communication between memory and microprocessor can be achieved only after knowing the processes involved in reading or writing into the memory by the microprocessor and time taken w.r.t. its clock period. Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

21

Read Cycle The high order address (A15 - A8) and low order address (AD7 - AD0) are asserted on 1st low going transition of the clock pulse. The timing diagram for IO/M read are shown in Fig. 15 (i) and (j). The A15- A8 remains valid in T1, T2, and T3 i.e. duration of the bus cycle, but AD7 - AD0 remains valid only in T1. Since it has to remain valid for the whole bus cycle, it must be saved for its use in the T2 and T3.

Fig. 15 (i) : Memory read timing diagram ALE is asserted at the beginning of T1 and each bus cycle and is negated towards the end of T1. ALE is acting during T1 only and is used as the clock pulse to latch the address (AD7 Û AD0) during T1. The RD is asserted near the beginning of T1. It ends at the end of T3. As soon as the RD becomes active, it forces the memory or I/O port to assert data. RD becomes inactive towards the end of T3, causing the port of memory to terminate the data.

Fig. 15 (j) : I/O Read timing diagram Write Cycle Immediately after the termination of the low order address, at the beginning of the T 2, data is asserted on the addres/data bus by the processor. WR control is activated near the starts of T2 and becomes inactive at the end of T3. The processor maintains valid data until after WR is terminated. This ensures that the memory or port has valid data while WR is active It is clear from fig. 15 (k) and (l) that for READ bus cycle, the data appears on the bus as a result of activating RD and for the WR bus cycle, the time the valid data is on the bus overlaps the time that the WR is active. Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

22

Fig. 15 (k) : Memory write timing diagram

Fig. 15 (l) : I/O write timing diagram

DE CO D ER Þ Þ eq.

Decoder is combinational ckt which have many i/p and many o/p. It is used to convert binary data to other code (binary to ****) Binary to octal (3 × 8) BCD to Decimal (4 × 10) Binary to Hexadecimal BCD to seven segment Þ 2 to 4 decoder is minimum possible decoder. 2 × 4 Decoder:A (MSB)

2 ×4 Decoder

B

y0 y1 y2 y3

E

Truth table:EAB

y3

y2

y1

y0

0xx

0

0

0

0

10 0 101

0 0

0 0

0 1

1 0

11 0

0

1

0

0

111

1

0

0

0

logical expression:-


23 y0 = A B E y1 = A B E y2 = A B E y3 = AB E

A

B y0

E

y1

y2

y3 Q.

Þ Decoder and Demux internal ckt remains sam. Implement Halt adder using 2 × 4 decoder.

A (MSB) B

Þ A B

2 ×4 Decoder

AB AB AB AB

Sum = AB + AB CARRY = AB

E=1 We implement HA using 1 – 2 × 4 Decoder and 1 or gate and same for HS. AB BARROW = AB AB 2 ×4 AB AB + AB Decoder AB

E=1 Binary to octal Decoder:Þ Also called as 3 × 8 Decoder ABC

ABC A (MSB) B C

3×8 Decoder

y0

y1 ABC y 2 ABC y 3

ABC ABC ABC

y4 y5

y6 A B C y7 E=1 Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

24 Q. Implement using 3 × 8 Decoder. make FA. Sol. Sum = S m (1, 2, 4, 7) = A B C + A B C + A B C + ABC CARRY = Sm (3, 5, 6, 7) 0 1 A (MSB)

2

B

4

C

5

3

SUM

6

CARRY

7

THE SHIFT REGISTER The Shift Register is another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. The data bits may be fed in or out of the register serially, i.e. one after the other from either the left or the right direction, or in parallel, i.e. all together. The number of individual data latches required to make up a single Shift Register is determined by the number of bits to be stored with the most common being 8-bits (one byte) wide, i.e. eight individual data latches. Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being: • Serial-In To Parallel-Out (SIPO) - the register is loaded with serial data, one bit at a time, with the stored data being available in parallel form. • Serial-In To Serial-Out (SISO) - the data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control. • Parallel-In To Serial-Out (PISO) - the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. • Parallel-In To Parallel-Out (PIPO) - the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse. The effect of data movement from left to right through a shift register can be presented graphically as: Parallel Data Output Q3

Q2

Q1

Q0 LSB

MSB Serial D Data Input

1-bit

1-bit

1-bit

1-bit LSB

MSB D3

Q Serial Data Output

D2

D1

D0

Parallel Data Input


25 Also, the directional movement of the data through a shift register can be either to the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same register thereby making it bidirectional. In this tutorial it is assumed that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) 4-bit Serial-in to Parallel-out Shift Register 4-bit Parallel Data Output

QA

Serial Data in

D

Q

QB D

FFA

Q FFB

QC D

Q FFC

QD D

Q FFD

Clear Clock

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level "0" i.e, no parallel data output. If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0. The second clock pulse will change the output of FFA to logic "0" and the output of FFB and QB HIGH to logic "1" as its input D has the logic "1" level on it from QA. The logic "1" has now moved or been "shifted" one place along the register to the right as it is now at QA. When the third clock pulse arrives this logic "1" value moves to the output of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the outputs Q A to QD back again to logic level "0" because the input to FFA has remained constant at logic level "0". The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD. Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows. Basic Movement of Data through a Shift Register Clock Pulse No. 0

QA 0

QB 0

QC 0

QD 0

1

1

0

0

0

2

0

1

0

0

3

0

0

1

0

4

0

0

0

1

5

0

0

0

0


26

1

Data 0 Input

0 1

ClK

2

3

4

5

1 0

QA

0

0

0

0

0

0

0

0

0

1 QB

0

0

0

0

0

0

0

0

1 QC

1 QD

0

0

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register and will remain there provided clocking of the register has stopped. In practice the input data to the register may consist of various combinations of logic "1" and "0". Commonly available SIPO IC's include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) This shift register is very similar to the SIPO above, except were before the data was read directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow straight through the register and out of the other end. Since there is only one output, the DATA leavestheshift register onebit at atimein aserial pattern, hencethename SerialIn To Serial-Out Shift Register or SISO. The SISO shift register is one of the simplest of the four configurations as it has only three connections, the Serial Input (SI) which determines what enters the left hand flipflop, the Serial Output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register. 4-bit Serial-in to Serial-out Shift Register 0

1

0

Serial Data in

1

0

D

Q

FFA CLK

0

D

Q

FFB CLK

1

D

Q

FFC CLK

0

D

Q

FFD CLK

1

Q Serial Data Out

Clock

You may think what's the point of a SISO shift register if the output data is exactly the same as the input data. Well this type of Shift Register also acts as a temporary storage device or as a time delay device for the data, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC's include the 74HC595 8-bit Serial-in/Serialout Shift Register all with 3-state outputs.

Parallel-in to Serial-out (PISO) The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format i.e. all the data bits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read out sequentially in the normal shift-right mode from the Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

27 register at Q representing the data present at PA to PD. This data is outputted one bit at a time on each clock cycle in a serial format. It is important to note that with this system a clock pulse is not required to parallel load the register as it is already present, but four clock pulses are required to unload the data. 4-bit Parallel-in to Serial-out Shift Register 1

mux

D Q FFA

mux

D Q FFB

mux

D Q FFC

mux

D Q FFD

Q Serial Data out

Clock

PD

PC

PB

PA

4-bit Parallel Data Input

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

PARALLEL-IN TO PARALLEL- OUT (PIPO) The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. The data is presented in a parallel format to the parallel input pins PA to PD and then transferred together directly to their respective output pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is shown below. 4-bit Parallel-in to Parallel-out Shift Register 4-bit Parallel Data Output QD

D

Q

QC

D

Q

QB

D

Q

QA

D

Q

FFA

FFB

FFC

FFD

CLK

CLK

CLK

CLK

Clock PD

PC

PB

PA

4-bit Parallel Data Input The PIPO shift register is the simplest of the four configurations as it has only three connections, the Parallel Input (PI) which determines what enters the flip-flop, the Parallel Output (PO) and the sequencing clock signal (Clk). Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required.


28

1.

The point P in the following figiure is stuck-at-1. The output F will be [2006, 2 Marks] A

B

4.

F

P

C

(a) 2.

ABC

(b)

A

5.

(c) ABC (d) A Two D flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following Q1Q0 sequence 00 ® 01 ® 11 ® 10 ® 00 ® ... The inputs D0 and D1 respectively should be connected as [2006, 2 Marks]

(a)

Q1andQ0

(b)

Q0andQ1

(c) 3.

A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5 number 24 will be represented by its BCP code 010100. In this numbering system, the BCP code 100010011001 is corresponds to the following number in base-5 system [2006, 2 Marks] (a) 423 (b) 1324 (c) 2201 (d) 4231 An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used by the 8255 chip to decode internally its three ports and the control register. The address lines A3 to A7 as well as the IO/M signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is

(d) Q1 Q0andQ1Q0 Q1Q0andQ1Q0 A 4-bit D/A converter is connected to a free-running 3-bit UP counter, as shown in the following figure. Which of the following waveforms will be observed at Vo?

(a) F8H-FBH (c) F8H-FFH 6.

[2007, 2 Marks] (b) F8H-FCH (d) F0H-F7H

The following binary values were applied to the X and Y inputs off the NAND latch shown in the figure in the sequence indicated below. X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1 The corresponding stable P, Q outputs will be

In the figure shown above, the ground has been shown by the symbol Ñ [2006, 2 Marks]

(a)

(b)

(c)

(d)

[2007, 2 Marks] (a) P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1 (b) P = 1, Q = 0; P = 0, Q = 1 or P = 0, Q = 1; P = 0, Q = 1 (c) P = 1, Q = 0; P =1, Q = 1; P = 1, Q = 0 or P = 0, Q =1 (d) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1


29 7.

The circuit diagram of a standard TTL NOT gate is shown in the figure. When Vi = 2.5 V, the modes of operation of the transistors will be [2007, 2 Marks] 11.

8.

9.

(a) Q1 : reverse active; Q2 : normal active; Q3 : saturation; Q4 : cut-off (b) Q1 : reverse active; Q2 : saturation; Q3 : saturation; Q4 : cut-off (c) Q1 : normal active; Q2 : cut-off; Q3 : cut-off; Q4 : saturation (d) Q1 : saturation; Q2 : saturation; Q3 : saturation; Q4 : normal active The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of gates required is [2007, 1 Mark] (a) 2 (b) 3 (c) 4 (d) 5 For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is DT.

Which of the following waveforms correctly represents the output at Q1? [2008, 2 Marks] (a)

(a) M = (P OR Q) XOR R [2008, 2 Marks] (b) M1 = (P AND Q) XOR R (c) M = (P NOR Q) XOR R (d) M1 = (P XOR Q) XOR R The logic function implemented by the following circuit at the terminal OUT is [2008, 2 Marks]

(a) P NOR Q (b) P NAND Q (c) P OR Q (d) P AND Q 12. For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible. [2008, 2 Marks]

Which of the following statements is true? (a) Q goes to 1 at the CLK transition and stays at 1 (b) Q goes to 0 at the CLK transition and stays at 0 (c) Q goes to 1 at the CLK transition and goes to 0 when D goes to 1 (d) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1 13. For the circuit shown in the following figure l0 to l3 are inputs to the 4 : 1 multiplexer. R (MSB) and S are control bits [2008, 2 Marks]

(b)

(c)

(d) The output Z can be represented by 10.

Which of the following Boolean Expression correctly represents the relation between P, Q, R and M1

(a)

PQ + PQS + QRS

(b)

PQ + PQR + PQS

(c)

PQR + PQR + PQRS + QRS

(d)

PQR + PQRS + PQRS + QRS


30 14.

15.

16.

The two numbers represented in signed 2’s complement form are P = 11101101 and Q = 11100110. If Q is subtracted from P, the value obtained in signed 2’s complement form is [2008, 2 Marks] (a) 100000111 (b) 00000111 (c) 11111001 (d) 111111001 An 8085 executes the following instructions 2710 LXIH, 30A0 H 2713 DADH 2714 PCHL All addresses and constants are in hexadecimal. Let PC be the contents of the programme counter and HL be the contents of the HL register pair just after executing PCHL. Which of the following statements is correct? [2008, 2 Marks] (a) PC = 2715 H (b) PC = 30A0 H HL = 30A0 H HL = 2715 H (c) PC = 6140 H (d) PC = 6140 H HL = 6140 H HL = 2715 H What are the counting states (Q1, Q2) for the counter shown in the figure below? [2009, 2 Marks]

18.

{ (

19.

20.

22. (a) 11, 10, 00, 11, 10,... (b) 01, 10, 11, 00, 01,... (c) 00, 11, 01, 10, 00,... (d) 01, 10, 00,01, 10,... Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are [2009, 2 Marks]

23.

(a) NAND : first (0, 1) then (0, 1) NOR : first (1, 0) then (0, 0) (b) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (1, 0) (c) NAND : first (1, 0) then (1, 0) NOR : first (1, 0) then (0, 0) (d) NAND : first (1, 0) then (1, 1) NOR : first (0, 1) then (0,)

)} {

}

é X + Z Y + Z + XY ù X + Z(X + Y) = 1, than ë û [2009, 2 Marks]

21.

17.

If X = 1 in the logic equation

(a) Y = Z (b) Y = Z (c) Z = 1 (d) Z = 0 What are the minimum number of 2 to 1 multiplexers required to generate a 2 input AND gate and a 2 input ExOR gate? [2009, 2 Marks] (a) 1 and 2 (b) 1 and 3 (c) 1 and 1 (d) 2 and 2 The full forms of the abbreviations TTL and CMOS in reference to logic families are [2009, 1 Mark] (a) Triple Transistor Logic and Chip Metal Oxide Semiconductor (b) Tristate Transistor Logic and Chip Metal Oxide Semiconductor (c) Transistor Transistor Logic and Complementary Metal Oxide Semiconductor (d) Tristate Transistor Logic and Complementary Metal Oxide silicon In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set but the interrupt can be delayed or rejected. Such an interrupt is [2009, 1 Mark] (a) non-maskable and non-vectored (b) maskable and non-vectored (c) non-maskable and vectored (d) maskable and vectored Assuming that all flip-flops are in reset condition initially, the count sequence observed at QA in the circuit shown is [2010, 2 Marks]

(a) 0010111... (b) 0001011... (c) 0101111.... (d) 0110100... For the 8085 assembly language programme given below, the content of the accumulator after the execution of the programme is [2010, 2 Marks] 3000 MVI A, 45H 3002 MOV B, A 3003 STC 3004 CMC 3005 RAR 3006 XRA B (a) 00H (b) 45H (c) 67H (d) E7H


31 24.

25.

26.

27.

The Boolean function realized by the logic circuit shown is [2010, 2 Marks]

28. The output of a 3-stage Johnson (twisted-ring) counter is fed to a digital-to-analog (D/A) converter as shown in the figure below. Assume all states of the counter to be unset initially. The waveform which represents the D/A converter output V0 is [2011, 2 Marks]

(a) F = SM (1, 3, 5, 9, 10, 14) (b) F = SM (2, 3, 5, 7, 8, 12, 13) (c) F = SM (1, 2, 4, 5, 11, 14, 15) (d) F = SM (2, 3, 5, 7, 8, 9, 12) In the circuit shown, the device connected to Y5 can have address in the range [2010, 1 Mark]

(a) 2000 – 20 FF (b) 2D00 – 2DFF (c) 2E00 – 2EFF (d) FD00 – FDFF Match the logic gates in Column A with their equivalents in Column B. [2010, 1 Mark] Column A Column B

(a) P-2, Q-4, R-1, S-3 (b) P-4, Q-2, R-1, S-3 (c) P-2, Q-4, R-3, S-1 (d) P-4, Q-2, R-3, S-1 For the output F to be 1 in the logic circuit shown, the input combination should be [2010, 1 Mark]

(a)

(b)

(c)

(d)

29. Two D flip-flops are connected as a synchronous counter that goes through the following QBQA sequence 00 ® 11 ® 01 ® 10 ® 00 ® .... The connections to the inputs DA and DB are (a) DA = QB, DB = QA [2011, 2 Marks] (b) DA = QA,D B = Q B (c) DA = (Q A QB + Q A Q B ), DB = Q A ) (d) DA = (Q A Q B + Q A Q B ), D B = Q B 30. The logic function implemented by the circuit below is (ground implies a logic “0”). [2011, 1 Mark]

(a) F = AND (P, Q) (b) F = OR (P, Q) (c) F = XNOR (P, Q) (d) F = XOR (P, Q) 31. The output Y in the circuit below is always 1 when

[2011, 1 Mark] (a) two or more of the inputs P, Q, R are 0 (b) two or more of the inputs P, Q, R are 1 (a) A = 1, B = 1, C = 0 (b) A = 1, B = 0, C = 0 (c) any odd number of the inputs P, Q, R is 0 (c) A = 0, B = 1, C = 0 (d) A = 0, B = 0, C = 1 (d) any odd number of the inputs P, Q, R is 1 Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

32 32.

When the output Y in the circuit below is 1, it implies that data has [2011, 1 Mark]

36.

33.

(a) changed from 0 to 1 (b) changed from 1 to 0 (c) changed in either direction (d) not changed In the CMOS circuit shown, electron and hole mobilities are equal, and M1 and M2 are equally sized. The device M1 is in the linear region if [2012, 2 Marks]

34.

(b) Y = (A + B)C

(c) Y = ( A + B ) + C

(d) Y = AB + C

Consider the given circuit.

In this circuit, the race around [2012, 1 Mark] (a) does not occur (b) occurs when CLK = 0 (c) occurs when CLK = 1 and A = B = 1 (d) occurs when CLK = 1 and A = B = 0 37.

(a) Vin < 1.875 V (b) 1.875 V < Vin < 3.125 V (c) Vin > 3.125 V (d) 0 < Vin < 5V The state transition diagram for the logic circuit shown is [2012, 2 Marks]

(a) Y = AB + C

In the sum of products function f(X, Y, Z) = S (2, 3, 4, 5), the prime implicants are [2012, 1 Mark] (a)

XY,XY

(b)

(c)

XYZ, XYZ,XY

(d) XYZ, XYZ,XYZ, XYZ

XY, XYZ,XYZ

38.

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is [2012, 1 Mark] (a) 4 (b) 6 (c) 8 (d) 10 39. For 8085 microprocessor, the following program is executed. MVI A, 05H; MVI B, 05H; PTR: ADD B;

(a)

DCR B;

(b)

JNZ PTR; ADI 03H; (c) 35.

HLT;

(d)

In the circuit shown

At the end of program, accumulator contains [2013, 1 Mark] (a) 17H (b) 20H

[2012, 1 Mark]

(c) 23H 40.

(d) 05H

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles [2013, 1 Mark] (a) an AND gate (b) an OR gate (c) an XOR gate

(d) a NAND gate


33 41. There are four chips each of 1024 bytes connected to a 16-bit address bus as shown in the figure below. RAM’s 1, 2, 3 and 4 respectively are mapped to addresses. [2013, 2 Marks]

RAM #4 1024B E

8 bit data bus

RAM #3 1024B E RAM #2 1024B

A0-A9 E

A10 A11

RAM #1 1024B

A12

A14

Input

A13

A15

S1 S0

(a) 0C00H-0FFFH, 1C00H-1FFFH, 2C00H-2FFFH, 3C00H3FFFH (b) 1800H-1FFFH, 2800H-2FFFH, 3800H-3FFFH, 4800H-4FFFH (c) 0500H-08FFH, 1500H-18FFH, 3500H-38FFH, 5500H-58FFH

11 10 01 00

E

44. The output F in the digital logic circuit shown in the figure is [2014, Set-1, 2 Marks]

XOR X AND

Y

F

(d) 0800H-0BFFH, 1800H-1BFFH, 2800H-23FFH, 3800H3BFFH 42.

The Boolean expression (X + Y) (X + Y) + (X Y) + X

43.

simplifies to [2014, Set-1, 1 Mark] (a) X (b) Y (c) XY (d) X + Y Five JK flip–flops are cascaded to form the circuit shown in figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q3 is __________. [2014, Set-1, 1 Mark]

1 J4 Q4 Clk 1 K4

1 J3 Q3 Clk K3

1

1 J2 Q2 Clk 1 K2

1 J1 Q1 Clk 1 K1 clock

1 J0 Q0 Clk 1 K0

Z XNOR (a)

F = XYZ + X YZ

(b)

F = XY Z + X Y Z

(c)

F = X YZ + XYZ

(d) F = X Y Z + XYZ 45. Consider the Boolean function, F(w, x, y, z) = wy + xy + wxyz + wxy + xz + x yz . Which one of the following is the complete set of essential prime implicants? [2014, Set-1, 2 Marks] (a) w, y, xz, x z

(b) w, y, xz

(c) y, x yz

(d) y, xz, x z


34 46.

The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the XOR gate.

ClK

S=0

D1Q1 CLK

00

A D2Q2 S

Q1

Q2

S=1 10

X1

S=1 S=0 S=0

01

X2

S=1 11

W1

S=0

W2

S=1

Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram? [2014, Set-1, 2 Marks]

W4

(a) W1 (b) W2 (c) W3 (d) W4 The outputs of the two flip-flops Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at Q1 upon application of clock signal is [2014, Set-2, 2 Marks]

(a) Input A is connected to Q 2 (b) Input A is connected to Q2 (c) Input A is connected to Q1 and S is complemented

51.

(d) Input A is connected to Q1 47.

48. 49.

For an n-variable Boolean function, the maximum number of prime implicants is [2014, Set-2, 1 Mark] (a) 2(n-1) (b) n/2 (c) 2n (d) 2(n-1) The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is __________ . [2014, Set-2, 1 Mark] In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by [2014, Set-2, 1 Mark] (a) M = X Å Y , N = XY (b) M = XY , N = X Å Y (c)

50.

J1 Q1

Q

(a) 01110 ... (b) 01010... (c) 00110... (d) 01100... For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is [2014, Set-2, 2 Marks]

52.

A2

3 to 8 Decoder C

A1

B

A0

A

DS1

Q

D

Ds2

RD

Output (y)

x2

I/O Device DI0–DI7 DO0–DO7 Data Bus (D0 – D7)

FF1 Clk

K2 Q2

CLK

(d) M = X Y , N = X Å Y In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and W4. [2014, Set-2, 2 Marks]

D

J2 Q2

K1Q1

M = XY , N = X Å Y

x1

Q1

A3

Q FF2 Q

(a) (c)

MVI A, F8H OUT F8H

(b) IN F8H (d) LDA F8F8H


35 53. D

The circuit shown in the figure is a [2014, Set-3, 1 Mark]

En

D Latch

(d)

Q

Q

VDD

BL

D Latch En Q

Q

WL

BL

Clk

54.

(a) Toggle Flip Flop (b) JK Flip Flop (c) SR Latch (d) Master-Slave D Flip Flop Consider the multiplexer based logic circuit shown in the figure. W

56. In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by [2014, Set-3, 2 Marks]

0

4 : MUX

0

1

F

I0

1 S2 Which one of the following Boolean functions is realized by the circuit? [2014, Set-3, 1 Mark] (b) F = WS1 + WS2 + S1S2 (a) F = W S 1 S 2

55.

(a)

WL

VDD

BL

BL

WL

F =W X +W X +Y Z

(b)

F = W X + W X + YZ

(c)

F =W X Y +W XY

F

Y

Z

(d) F = (W + X ) + Y Z 57. If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor? [2014, Set-3, 2 Marks] Y

I0 I1

BL

Y

VDD

I0

I0 I1

BL

D

2:1 MUX

B

2:1 MUX

D

S S

Y X

2:1 MUX S S

X

(b) BL

X

(a)

I1

WL

Q

I3

W

Y

(c)

I2

I3

VDD

BL

I1

Q

I2

(a) (b)

I0

I1

S1

(c) F = W + S1 + S2 (d) F = W Å S1 Å S2 If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in [2014, Set-3, 2 Marks]

4 : MUX

I0 I1

2:1 MUX

B


36 (c)

I0

Y

I1

I0

Y

I1 I0

X

I1

60.

2:1 MUX

D

2:1 MUX

B

I0

X

I1

2:1 MUX

(a)

In the circuit shown in the figure, if C=0, the expression for Y is [2014, Set-4, 1 Mark]

61.

C A B Y

(a)

(d) Y = AB Y = A+ B The output (Y) of the circuit shown in the figure is [2014, Set-4, 1 Mark]

B

S2 S1 S0

A1 B1 C0

FA1

A14 B14 C1

FA14

A15 B15 C14

FA15

C15

(b) Y = A + B

Y = AB + AB

VDD

A

Y

(b) Y = ABC + ABD (d) Y = A BD + ABC (c) Y = ABC + ACD A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________. [2014, Set-4, 2 Marks]

FA0

(c)

59.

I0 I1 I2 I3 I4 I5 I6 I7

Y = ABC + ACD

A0 B0

A B

A + B.C + A.C

(c) A + B + C (d) A.B.C An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by [2014, Set-4, 2 Marks] 0 D 0 D 0 0 1 0

D

(b)

A+ B+C

S S

Y

58.

B

S S

X

(d)

(a)

2:1 MUX

C

S0

62.

S1

S14

S15

An 8085 microprocessor executes “STA 1234H” with starting address location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins A15 – A8 is [2014, Set-4, 2 Marks] (a) 1FH, 1FH, 20H, 12H (b) 1FH, FEH, 1FH, FFH, 12H (c) 1FH, 1FH, 12H, 12H (d) 1FH, 1FH, 12H, 20H, 12H

Output (Y) A

B

C


37

1.

2.

A signed integer has been stored in a byte using 2’s complement format. We wish to store the same integer in 16-bit word. We should copy the original byte to the less significant byte of the word and fill the more significant byte with (a) 0 (b) 1 (c) equal to the MSB of the original byte (d) complement of the MSB of the original byte. In the given combinational circuit, the output Z is

5.

(b) both switches are open (c) only one switch is closed (d) LED does not emit light irrespective of the switch positions A combinational circuit has input A, B and C and its K-map is as shown in figure. The output of the circuit is given by BC 00 01 10 11 A

B

Z

C

(a) 3.

4.

(b)

A+ B+C

ABC

(c) AB + BC + AC (d) Above all The truth table of a circuit is shown in figure A B C Z 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 The Boolean expression for Z is (a)

( A + B)( B + C)

(b)

(c)

( A + B) (B + C)

(d) Above all

( A + B )( B + C )

6.

( AB + AB) C

(b)

(c)

ABC

(d) A Å B Å C

x0

I0

x1

I1

x1

I2

3 to 8 Decoder

D0 D1 D2 D3 D4 D5 D6 D7

P (1, 2, 4,5, 7 )

f

(b)

å (1, 2, 4,5, 7 )

(d) None of these (c) å ( 0, 3, 6 ) The logic circuit shown in figure implements

VCC = 5 V 1 kW

( AB + AB ) C

f ( x 2 , x1, x 0 ) = ?

(a) 7.

1

(a)

In figure given below the LED emits light when

1 kW

1

01

A

1

1

00

x0

I0

x1

I1

x1

I2

3 to 8 Decoder

1 kW

EN

D0 D1 D2 D3 D4 D5 D6 D7

z

1 kW

D

1 kW

(a)

D (A C + A C)

(c)

D BÅ C + A B

(

)

(b)

(

D BÅ C + A C

)

(d) D (B C + A B)

(a) both switches are closed Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

38 8.

The network shown in figure implements 1 MUX

A

0

1 B

1 MUX

0

0

f

(a) AB + AQ (b) AB + BQ (c) Both A and B (d) None of these If the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR-gates is X, then the output Y is equal to

13.

S1

1

S0

Y X

C

9.

(a) NOR gate (b) NAND gate (c) XOR gate (d) XNOR gate The MUX shown in figure is 4 × 1 multiplexer. The output Z is

C

I3 I2 I1 I0

MUX

(a) 0 (b) 1 (c) X (d) X The counter shown in the figure is a

14.

Q

z

C Q

S1 S0

+5V A

10.

B (a) ABC (b) A Å B Å C (c) A B C (d) A + B + C The input signal Vi shown in figure is applied to a FF figure when initially in its 0-state. Assume all timing constraints are satisfied. The output Q is

Vi

J

K

1

A Q

K

Q1

J

Q2

J

Q3

J

J

Q4

K CLR

K CLR

16.

Counter

(d)

S Q

K CLR

(a) 24 (b) 48 (c) 25 (d) 36 The frequency of the pulse at z in the network shown in figure is 10 Bit Ring w 4-Bit Parallel x

A 4-bit ripple counter and a 4-bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then (a) R = 10 ns, S = 40 ns (b) R = 40 ns, S = 10 ns (c) R = 10 ns, S = 30 ns (d) R = 30 ns, S = 10 ns An AB flip-flop is constructed from an SR Flip-flop as shown in figure. The expression for next state Q+ is

K CLR

All J.K. Input are HIGH

(b)

A

Q0

K CLR

CLK

12.

Q

K

1

Q

D

Vi

11.

B

J

(a) MOD-8 up counter (b) MOD-8 down counter (c) MOD-6 up counter (d) MOD-6 down counter The mod-number of the asynchronous counter shown in figure is

15.

Q

(c)

Q

J

CLK

CLK

(a)

Q

J

17.

Counter

Mod - 25

y

Ripple Counter

4-Bit Johnson z Counter

(a) 10 Hz (b) 160 Hz (c) 40 Hz (d) 5 Hz The 8-bit shift-left shift register and D flip-flop shown in the figure is synchronized with the same clock. The D flip-flop is initially cleared. The circuit acts as

b7 b6 b5 b4 b3 b2 b1 b0 CLK

D Q Q

(a) Binary to 2’s complement converter (b) Binary to Gray code converter R B (c) Binary to 1’s complement converter (d) Binary to Excess - 3 Code converter Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

39 18.

Consider the TTL circuit of figure. If either or both V1 and V2 are logic LOW, Q1 is driven to saturation. The output V01 produces logic + VCC

R1

22. An 8-bit digital-ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with VT = 1 mV. The digital output for VA = 6.000 V is (a) 1 0 0 1 0 1 1 1 (b) 1 0 0 1 0 1 1 0 (c) 1 0 1 1 1 1 0 (d) 1 0 1 1 1 1 1 23. For the comparator circuit shown in figure the forward diode voltage drop is VT = 0.7 V and reverse Zener diode voltage is 5.6 V. If hysteresis width is 1 V, then the value of R2 is – 12 V

R2 V02 R3

V1 V2

Q1

+

Vi V01

1 kW

Q2

–

V0

+ 12 V R2

19.

(a) AND (b) OR (c) NAND (d) NOR Consider the RTL gate of figure. The transistor paratmeters are VCE(sat) = 0.2 V and b = 50. The logic HIGH voltage is VH = 3.5 V. If input drive the similar + 5 V type of gate, the fanout is

24.

25.

640 W

V0 450 W V1

450 W V2

26.

20.

(a) 5 (b) 10 (c) 15 (d) 20 Consider the CMOS circuit shown in figure. It acts as a VDD

V1

M3 V0

M4

V2

M2 M1

21.

(a) Negative NAND (b) Positive NAND (c) Negative NOR (d) Positive NOR A certain logic family has the following voltage parameters; VIH ( min ) = 3.5V , VIL( max ) = 1.0V , VOH( min ) = 4.9V

and VOL( max ) = 0.1V . The largest positive going and negative-going spike, that can be tolerated, is respectively (a) 1.4 V, 0.9 V (b) 0.9 V, 1.4 V (c) 3.9 V, 3.4 V (d) None of these

27.

(a) 1 kW (b) 12.6 kW (c) 2 kW (d) 6.3 kW The Boolean expression X (P, Q, R) = p (0, 5) is to be realized using only two 2-input gates. Which are these gates? (a) AND and OR (b) NAND and OR (c) AND and XOR (d) OR and XOR A master slave configuration consists of two identical flipflops connected in such a way that the output of the master is input to the slave. Which one of the following is correct? (a) Master is level triggered and slave is edge triggered. (b) Master is edge triggered and slave is level triggered. (c) Master is positive edge triggered and slave is negative edge triggered. (d) Master is negative edge triggered and slave is positive edge triggered. Match List - I (Type of N-bit ADC) with List-II (Characteristic) and select the correct answer using the codes given below the lists: List - I List - II A. Flash converter 1. Integrating type B. Successive 2. Fastest converter approximation C. Counter ramp 3. Maximum conversion time N = bits D. Dual slope 4. Uses a DAC in its feedback path Codes: A B C D A B C D (a) 1 4 3 2 (b) 1 3 4 2 (c) 2 4 3 1 (d) 2 3 4 1 Match List - I (Logic gates) with List-II (Operation) and select the correct answer using the codes given below the lists: List - I List - II A. TTL 1. More logical swing B. ECL 2. Low power dissipation C. HTL 3. Current hogging D. CMOS 4. NOR/OR output 5. Totem-pole output Codes: A B C D A B C D (a) 3 2 5 1 (b) 3 2 4 5 (c) 2 3 4 5 (d) 2 3 5 1


40 28.

The minimized expression for the given K map (X: don’t care) is

32.

AB 00

01

11

10

00

0

0

1

1

01

0

CD

29.

5V

1

11 10

1 1

0

1

S1

B

S0

0

1

0

I0

I1

I2 I3

IR

33.

Y

34.

A B C + ABC + ABC + ABC is

(a)

MUX F

(a) 0.65 mA (b) 0.70 mA (c) 0.75 mA (d) 1.00 mA Which one of the following statements is not correct? Conversion of EXCESS-3 code to BCD can be achieved by using (a) Discrete gates (b) 4 : 16 demultiplexer (c) A 4-bit full adder (d) A 4-bit half adder The minimised form of the logical expression

35.

SELECT

A C + BC + AB

(b)

AC + BC + AB

(c) AC + BC + AB (d) AC + BC + AB In the TTL circuit in figure, S2 to S0 are select lines and X2 and X0 are input lines. S0 and X0 are LSBs. The output Y is 1

B

0

A

31.

1K

1

(a) A (b) B (d) AB + AB (c) AB The output ‘F’ of the multiplexer circuit shown in the figure will be C C C C

V0

1

(a) A + B C (b) B + AC (c) C + AB (d) ABC The function ‘F’ implemented by the multiplexer chip shown in the figure is

A

I

1.4 K

F

30.

The transistors used in a portion of the TTL gate shown in the figure have a b = 100. The base-emitter voltage of is 0.7 V for a transistor in active region and 0.75 V for a transistor in saturation. If the sink current I = 1 mA and the output is at logic 0, then the current IR will be equal to

(a)

AB + BC + CA + B C

(b) (c)

A Å BÅ C AÅB

0 C

(d) A BC + ABC + ABC + ABC In the circuit shown below, the outputs Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be

J

Q

K

Q

(a) Y1 = 1, Y2 = 0 (c) Y1 = 0, Y2 = 1

Y2

Y1 J

Q

K

Q

(b) Y1 = 0, Y2 = 0 (d) Y1 = 1, Y2 = 1

X0 X1 X2 X3 X4 X5 X6 X7 B 8 : 1 MUX S B A

2

S1 S0 Y

36.

(a) Intermediate

(b)

(c)

(d) C. A Å B + C. ( A Å B)

AÅB

AÅB

(

)

Consider the following: Any combinational circuit can be built using 1. NAND gates 2. NOR gates 3. EX-OR gates 4. Multiplexers Which of these are correct? (a) 1, 2 and 3 (b) 1, 3 and 4 (c) 2, 3 and 4 (d) 1, 2 and 4


41 37.

Figure shows a mod-K counter, here K is equal to (a) J

Q

J

Q

fc 8

(b)

fc 6

fc fc (d) 3 2 A synchronous sequential circuit is designed to detect a bit sequence 0101 (overlapping sequence include). Everytime this sequence is detected, the circuit produces an output of ‘1’. What is the minimum number of states the circuit must have? (a) 4 (b) 5 (c) 6 (d) 7 It is required to construct a 2n to multiplexer by using 2- to -1 multiplexers only. How many of 2-to-1 multiplexers are needed? (a) n (b) 22n (c) 2n – 1 (d) 2n – 1

(c)

1

Q

K

1

Q

K

43.

CK

38.

(a) 1 (b) 2 (c) 3 (d) 4 Figure below shows a ripple counter using positive edge triggered flip flops. If the present state of the counter is Q2Q1Q0 = 011, then its next state (Q2Q1Q0) will be 1 CLK

39.

40.

41.

1

Q0

T0

44.

1 T1

Q0

Q2

T2

Q1

Q2

Q1

(a) 010 (b) 100 (c) 111 (d) 101 In the CMOS inverter, the power dissipation is (a) low only when VIN is low (b) low only when VIN is high (c) high during dynamic operation (d) low during dynamic operation The resolution of a 12-bit analog to digital converter in a percent is (a) 0.01220 (b) 0.02441 (c) 0.04882 (d) 0.09760 In the circuit assuming initially Q0 = Q1 = 0. Then the states of Q0 and Q1 immediately after the 33rd pulse are

45. The boolean expression Y Z + X Z + X Y is logically equivalent to (a) YZ + X (b) (c)

46.

Q0 J0

Q0

J1

Q1

K0

Q0

K1

Q1

CLK

42.

Q1

47. 48.

(a) 1 1 (b) 1 0 (c) 0 1 (d) 0 0 The three state Johnson-ring counter as shown above is clocked at constant frequency of fc from the starting state of Q0Q1Q2 = 101. The frequency of outputs Q0Q1Q2 will be

49.

50. J0

Q0

J1

Q1

J2

Q2

YZX + X Y Z

YZ + XZ + XY (d) X Y Z + X Y Z + XY Z + X YZ Which one of the following is not a characteristics of CMOS configuration? (a) CMOS devices dissipate much lower static power that bipolar device. (b) CMOS devices have low input impedances. (c) CMOS devices have higher noise-magins. (d) CMOS devices have much lower transconductance than bipolar devices. Race around condition always arise in a (a) Combination circuit (b) Asynchronous circuit (c) Synchronous circuit (d) Digital circuit For a mod-12 counter, the FF has a t pd = 60 ns. The NAND gate has a tpd of 25 ns. The frequency is (a) = 3.744 MHz (b) > 3.744 MHz (c) < 3.774 MHz (d) = 4.167 MHz The initial state of MOD-16 down counter 0110. After 37 clock pulses, the state of the counter will be (a) 1011 (b) 0110 (c) 0101 (d) 0001 The initial contents of the 4-bit serial-in parallel-out rightshift shift register shown in figure is 0110. After three clock pulses applied, the contents of the shift register will be Clock

K0

Q0 CLK

K1

Q1 CLK

K2

Q2 CLK

0 1 1 0 Serial in +

Clock

(a) 0000 (b) 0101 (c) 1010 (d) 1111 Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

42 51.

52.

Addition of all gray code to convert decimal (0 – 9) into gray code is (a) 129 (b) 108 (c) 69 (d) 53 Determine parity checker output from the below figure. If input is 11111 (D4D3D2D1D0) & 10000 (D4D3D2D1D0)

D4 D3 D2

54.

(a) error, error (b) error, no error (c) no error, error (d) no error, no error The counter start off in the ‘0000’ state, and then clock pulses are applied. Some time later the clock pulses are removed and the counter FFs read ‘0011’. How many clock pulses have occurred? (a) 3 (b) 35 (c) 51 (d) any of them For given MOD-16 counter with a 10 kHz clock input determine the frequency at Q3.

58.

59.

60.

CP1 10 kHz

CP0

MOD - 16 MR2 Q3 Q2 Q1 Q0

MR1

55.

56.

(a) 625 Hz (b) 10 kHz (c) 2.5 kHz (d) 0 Hz For a stable timer circuit, given RB = 750 W. Determine value for RA and C to provide a 1.0 MHz clock that has a duty cycle of 25%. (a) 15 kHz, 600 pF (b) 1.5 kHz, 480 pF (c) 1 kHz, 6 mF (d) 1.5 kHz, 600 pF Schmitt trigger is shown in figure. The upper & lower threshold voltages are respectively

61.

+2V

10 kW

62.

20 kW – 10 V

Vi

Vout

+ 5 kW + 10 V

(a) 2 V, – 4 V (c) 4 V, – 4 V

20kW

(b) 2 V, – 2 V (d) 4 V, – 2V

The open collector output of 2-input NAND gates are connected to a common pull-up resister. If the inputs of the gates are A, B and C, D respectively, the output is equal to (a)

E 1= error 0 = no error

D1 D0

53.

57.

A.B. C.D

(b)

A.B + C.D (c) A.B + C.D (d) A. B. C. D TTL circuits with active pull-up are preferred because of their suitability for (a) wired-AND operation (b) bus operated system (c) wired logic operation (d) reasonable dissipation and speed of operation The Zenith Computer can execute 1,000,000 instructions per second. A program running on this computer performs on average a one sector read and one sector write for every 200 instructions that it executes. The disk drive handling the I/ O transfers requires 0.00010 seconds each to perform the read and write operations. Assuming no overlap of these operations, the percent of CPU time spent in the wait state, is (a) 12% (b) 39% (c) 57% (d) 91% The following program is run on an 8085 microprocessor Memory Address in hex Instruction 2000 LXISP, 1000 2003 PUSH H 2004 PUSH D 2005 CALL 2050 2008 POP H 2008 HLT At the completion of execution of the program, the program Counter of the 8085 contains ___________ and the Stack Pointer contains __________ (a) 2050, 0FFC (b) 2020, 0CCF (c) 2000, CCF0 (d) 2020, 0FFC Four jobs to be executed on a single processor system arrive at time 0 in the order A, B, C and D. Their burst CPU time requirements are 4, 1, 8, 1 time units respectively. The completion time of a under round robin scheduling with time slice of one time unit is (a) 10 (b) 4 (c) 8 (d) 9 Consider the following set of instructions STC CMC MOV A, B RAL MOV B, A This set of instructions (a) doubles the number in Register by B (b) divides the number in Register by 2 (c) multiples B by A (d) adds A and B


43 63.

64.

65.

66.

67.

68.

DSPLY: MOV A, B Consider the following Assembly Language programme MVI A, 30H OUT PORT2 ACI, 30H HLT XRA, A This program will display POP, H (a) the bytes form 51 H to 82H at PORT 2 After the execution of the above program, the contents of (b) 00H AT PORT 1 the Accumulator will be (c) all byte at PORT 1 (a) 30 H (b) 60 H (d) the bytes from 52H to 81H at PORT 2 (c) 00 H (d) contents of stack 69. Consider the following 8085 instruction An Intel 8085 processor is executing the program given XRA A below MVI B, 4AH MVI A, 10H SUI 4FH MVI B, 10H ANA B BACK: NOP HLT ADD B The contents of register A and B are respectively RLC (a) 05, 4A (b) 4F, 00 JNC BACK (c) B1, 4A (d) None of the above HLT 70. Consider the following assembly language program The number of times that the operation NOP will be executed MVI B, 87H is equal to MOV A, B (a) 1 (b) 2 START: JMP NEXT (c) 3 (d) 4 MVI B, 00H A sample-and hold (S/H) circuit, having a holding capacitor XRA B of 0.1 nF, used at the input of an ADC (analog-to-digital OUT PORT 1 converter). The conversion time of the ADC is 1 msec, and HLT during this time, the capacitor should not lose more than NEXT: XRA B 0.5% of the charge put across it during the sampling time. JP START 1 The maximum value of the input signal to the S/H circuit is OUT PORT 2 5V. The leakage current of the S/H circuit is 5V. The leakage HLT current of the S/H circuit should be less than The execution of the above program in an 8085 will result in (a) 2.5 mA (b) 0.25 mA (a) an output of 87H at PORT1 (c) 25.0 mA (d) 2.5 mA (b) an output of 87H at PORT2 In an 8085 microprocessor, the instruction CMP B has been (c) infinite looping of the program execution with executed while the contents of accumulator is less than of accumulator data remaining at 00H register B. As result carry flag and zero flag will be (d) infinite looping of the program execution with respectively accumulator data alternating between 00H and 87H. (a) set, reset (b) reset, set 71. The instruction, that does not clear the accumulator of 8085, (c) reset, reset (d) set, set is Consider the following 8085 instruction (a) XRA, A (b) ANI 00H MVI A, A9H (c) MVI A, 00H (d) None of these MVI B, 57H ADD B 72. Consider the following loop ORA A XRA A The flag status (S, Z, CY) after the instruction ORA A is LXI B, 0007H executed, is LOOP: DCX B (a) (0, 1, 1) (b) (0, 1, 0) JNZ LOOP (c) (1, 0, 0) (d) (1, 0, 1) This loop will be executed Consider the following 8085 assembly program (a) 1 times (b) 8 times MVI A, DATA 1 (c) 7 times (d) infinite times MOV B, A 73. The contents of accumulator after the execution of following SUI 51H instructions will be JC DLT MVI A, B7H MOV A, B ORA A SUI 82H RAL JC DSPLY (a) 6EH (b) 6FH DLT: XRA A (c) EEH (d) EFH OUT PORT 1 HLT Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

44 74.

75.

76.

77.

78.

79.

80.

Consider the following set of instruction Of these statements MVI A, BYTE 1 (a) 2 and 4 are correct (b) 1, 2 and 4 are correct RLC (c) 2 and 3 are correct (d) 1, 3 and 4 are correct MOV B, A 81. Which of the following statements is true? RLC (a) ROM is a Read/Write memory ADD B (b) PC points to the last instruction that was executed If BYTE 1 = 07H, then content of A, after the execution of (c) Stack works on the principle of LIFO program will be (d) All instructions affect the flags (a) 46H (b) 70H 82. Cache memory is logically positioned (c) 38H (d) 68H (a) between CPU and main memory An 8085 mp based system drives a multiplexed 5-digits 7(b) between main memory and secondary memory segment display. The digits are refreshed at a rate of 500 Hz. (c) inside the CPU The ON time for each digit is (d) inside the I/O processor (a) 4 ms (b) 0.4 ms 83. When a CPU is interrupted, it (c) 10 ms (d) 25 ms The contents of Register (B) and Accumulation (A) of 8085 (a) stops execution of instructions microprocessor are 49H and 3AH respectively. The contents (b) acknowledges interrupt and branches to a subroutine of A and the status of carry flag (CY) and sign flag (S) after (c) acknowledges interrupt and continues executing SUB B instructions are (d) acknowledges interrupt and waits for the next (a) A = F1, CY = 1, S = 1 (b) A = 0F, CY = 1, S = 1 instruction from the interrupting device (c) A = F0, CY = 0, S = 0 (d) A = 1F, CY = 1, S = 1 84. In an 8085 mP system, the RST instruction will cause an An 8085 microprocessor based system uses a 4k × 8 bit interrupt RAM whose starting address is AA00H. The address of (a) only if an interrupt service routine is not being executed the last byte in this RAM is (b) only if a bit in the interrupt mask is made 0 (a) 0FFFH (b) 1000H (c) only if interrupts have been enabled by an EI instruction (c) B9FFH (d) BA00H (d) none of the above Match List - I (Instruction) with List-II (Application) and 85. The stack pointer in the 8085 microprocessor is a select the correct answer using the codes given below: (a) 16 bit register that point to stack memory locations List - I List - II (b) 16 bit accumulator A. SIM 1. 16-bit addition B. DAD 2. Initializing the stack (c) memory location in the stack pointer (d) flag register used for the stack C. DAA 3. Serial output data 86. If an original MIB microcomputer operates at 5 MHz with an D. SPHL 4. Checking the current 8 bit bus and a newer version operates at 20 MHz with a 32 interrupt mask setting bit bus, compute (approximately) the maximum speed-up 5. BCD addition possible. Codes: (a) 2 (b) 4 A B C D A B C D (c) 6 (d) 16 (a) 5 4 2 1 (b) 3 1 5 2 87. The larger the RAM of a computer, the faster is its speed, (c) 5 1 2 4 (d) 3 4 5 1 since it eliminates Memory chips of four different sizes as below are available: (a) need for ROM 1. 32 k × 4 (b) need for external memory 2. 32 k × 16 (c) frequent disk I/Os 3. 8 k × 8 (d) need for a data-wide path 4. 16 k × 4 All the memory chips as mentioned in the above list are 88. The TRAP is one of the interrupts available in INTEL 8085. Read/Write memory. What minimal combination of chips or Which one of the following statements is true of TRAP? chip alone can map full address space of 8085 (a) It is level triggered. microprocessor? (b) It is negative edge triggered (a) 1 and 2 (b) 1 only (c) It is positive edge triggered (c) 2 only (d) 4 only (d) It is both positive edge triggered and level triggered. Consider the following statements associated with 89. In a 16-bit microprocessor, words are stored in two microprocessors consecutive memory locations. The entire world can be read 1. Debug is synonymous with exponent in one operations provided the first 2. Direct-Memory Access Channel (DMA) facilitates to (a) word is even (b) word is odd move into and out of the system without program (c) memory location is odd (d) memory address is even interruption 3. Double precision employs double signal speed 4. Dump means copying data from internal storage to external storage. Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

45 90.

91.

92.

93.

94.

95.

96.

97.

98.

99.

In a multiprocessor configuration, two co-processors are connected to the host 8085 processor. The two co-processor instruction sets (a) must be the same (b) may overlap (c) must be disjoint (d) must be the same as that of the host In an assembler, which one of the following is required for variable names in symbol table? (a) Addresses (b) Values (c) Registers (d) Storage Direct Memory Access Channel (DMA) facilitates data to move into and out of the system (a) one first come first serve basis (b) with equal time delay (c) without subroutine (d) without program intervention In vectored interrupt (a) the branch address is assigned to a fixed location in memory (b) the interrupting source supplies the branch information to the processor through an interrupt vector (c) the branch address is obtained from a register in the processor (d) None of the above In an 8085 micro-processor, the instruction CMP B has been executed while the contents of the accumulator, is less than that of register B, As a result. (a) Carry flag will be set but Zero flag will be reset (b) Carry flag will be reset but Zero flag will be set (c) Both carry flag and Zero flag will be reset (d) Both carry flag and Zero flag will be set A single instruction to clear the lower four bits of the accumulator in 8085 assembly language is (a) XRI OHF (b) ANI FOH (c) XRI FOH (d) ANI OFH A binary tree T has n leaf nodes. The number of nodes of degree 2 in T is (a) log2 n (b) n – 1 (c) n (d) 2n The number of 1 s in the binary representation of {3*4096 + 15*256 + 5*16 + 3) are (a) 8 (b) 9 (c) 10 (d) 12 Choose the correct statement from the following (a) PROM contains a programmable AND array and a fixed OR array. (b) PLA contains a fixed AND array and a programmable OR array. (c) PROM contains a fixed AND array and programmable OR ARRAY. (d) None of these Figure shown below the circuit of a gate in the Resistor Transistor Logic (RTL) family. The Circuit represents a

VCC

V

Vi1

Vi2

(a) NAND (b) AND (c) NOR (d) OR 100. The initial contents of the 4-bit serial-in-parallel-out, rightshift, Shift Register shown in figure below, is 0110. After three clock pulses are applied, the contents of the Shift Register will be CLOCK SERIAL IN

0

1

1

0

+

101.

102.

103. 104.

105.

106.

(a) 0000 (b) 0101 (c) 1010 (d) 1111 Commercially available ECL gears use two ground lines add one negative supply in order to (a) Reduce power dissipation (b) Increase fan-out (c) Reduce loading effect (d) Eliminate the effect of power line glitches or the biasing circuit. The resolution of a 4-bit counting ADC is 0.5 Volts. For an analog input of 6.6 volts, the digital output of the ADC will be (a) 1011 (b) 1101 (c) 1100 (d) 1110 Maximum I/O space which can be addressed by 8088 CPU is (a) 1024 (b) 2048 (c) 65536 (d) 2000 Metastability in D-Flip Flop occurs when (a) Set up time of input data is not met (b) Clock period is too large (c) Set and reset are active simultaneously (d) D and Q pins are shortened. How many 1’s are present in the binary representation of 3 × 512 + 7 × 64 + 5 × 8 + 3? (a) 8 (b) 9 (c) 10 (d) 11 The basic memory cell of dynamic RAM consists of (a) a capacitance (b) a transistor (c) a flip-flop (d) a transistor acting as a capacitor.


46 107. PROMS are used to store (a) bulk information (b) sequential information (c) information to be accessed rarely (d) relatively permanent information 108. A 10 bit DAC has a step size of 10 mV. The percentage resolution is (a) 1% (b) 0.1% (c) 10% (d) 2% 109. The circuit shown below implements the function

113.

114.

115.

(

(a) ABC + A + B + C

(

)

)

(b) ABC + ABC

(c) ABC + A + B + C (d) None of these 110. The total number of memory accesses involved (inclusive of the op-code fetch) when an 8085 processor executes the instruction LDA 2003 is (a) 1 (b) 2 (c) 3 (d) 4 111. In the following question, match each of the items A, B and C on the left with an approximate item on the right. A. A shift register 1. for code conversion can be used B. A multiplexer can 2. to generate memory be used slip to select C. A decoder can be 3. for parallel-to-serial used conversion 4. as a many-to-one switch 5. for analog-to-digital conversion A B C (a) 1 2 3 (b) 3 4 1 (c) 5 4 2 (d) 1 3 5 112. The minimum Boolean expression for the following circuit is A

116.

117.

118.

B C

A

B

A C

119.

(a) AB + AC + BC (b) A + BC (c) A + B (d) A + B + C A carry look ahead adder is frequency used for addition because, it (a) is faster (b) is more accurate (c) used fewer gates (d) costs less Which one of the following can be used to change data from special code to temporal code? (a) Shift registers (b) Counters (c) A/D converters (d) Combinational circuits Match List-I (computer terms) with List-II (definitions) and select the correct answer using the codes given below this lists. List - I List - II A. Interface 1. A measure of rate of data transmission B. A bit 2. A binary digit C. Baud Speed 3. The common boundary between various sections and subsections 4. Analog to digital converter Codes: A B C (a) 3 2 1 (b) 3 1 2 (c) 2 4 1 (d) 4 2 3 If the memory chip size is 256 × 1 bits, then the number of chips required to make up 1 K (1024) bytes of memory is (a) 32 (b) 24 (c) 12 (d) 8 Match List - I with List - II and select the correct answer, using the codes given below the lists: List - I List - II (Logic gate) (Characteristic) A. HTL 1. High fan-out B. CMOS 2. speed of operation C. I2L 3. High noise immunity D. ECL 4. Lowest product of powder and delay Codes: A B C D (a) 4 3 2 1 (b) 4 1 2 3 (c) 3 1 4 2 (d) 3 4 1 2 A divide by 78 counter can be realized by using (a) 6 nos of mod-13 counters (b) 13 nos of mod-6 counters (c) one mod-13 counter followed by one mod-6 counter (d) 13 nos of mod-13 counters Hamming codes are used for error detection and correction. If the minimum Hamming distance is m, then the number of errors correctable is (a) equal to m (b) less than m/2 (c) equal to 2m (d) greater than m

B


47 120. The number of comparators is a 4-bit flash ADC is (a) 4 (b) 5 (c) 15 (d) 16 121. In a microcomputer, wait states are used to (a) make the processor wait during a DMA operation (b) make the processor wait during an interrupt processing (c) make the processor wait during a power shutdown. (d) interface slow peripherals to the processor 122. The problem of ‘current hogging’ is associated with (a) DCTL gates (b) DTL gates (c) ECL gates (d) CMOS gates 123. The most satisfactory LED driver circuit using a TTL gate is

470 W

(a)

(b) +5V

470 W

NUMERICAL TYPE QUESTIONS (d)

(c)

124. The minimal product-of sums function described by the Kmap given in Figure (a) A'C' (b) A' + C' (c) A + C (d) AC AB

00

01

11

10

0

1

1

f

0

1

0

0

f

0

C

(a) 16 address lines and 16 data lines (b) 4 address lines and 8 data lines (c) 8 address lines and 8 data lines (d) 4 address lines and 16 data lines 128. Consider the following statements regarding registers and latches: 1. Registers are made of edge-triggered FFS, whereas latches are made from level-triggered FFS. 2. Registers are temporary storage devices whereas latches are not. 3. A latch employs cross-coupled feedback connections. 4. A Register stores a binary word whereas a latch does not. Which of these statements given above are correct? (a) 1 and 2 (b) 1 and 3 (c) 2 and 3 (d) 3 and 4 129. A 1-bit full adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit. What is the maximum rate of addition per second when four 1-bit full adders are cascade? (a) 107 (b) 1.25 × 107 6 (c) 6.25 × 10 (d) 105

125. The circuit shown in the given figure is X Y

130. The number of comparators in a 4-bit flash ADC is 131. The ideal inverter in figure has a reference voltage of 2.5 V. The forward voltage of the diode is 0.75 V. The forward voltage of the diode is 0.75 V. The maximum number of diode logic circuit that may be cascaded ahead of the inverter without producing logic error, is +5V +5V+5V

+5V A

Z

B C

D n Stage of Diode Logic

132. A 12-bit (3-digit) DAC that uses the BCD input code has a full scale output of 9.99 V. The value of Vout for an input code of 0110 1001 0101 is 133. The step size of the DAC of figure is 0.5 V. The value of RF is MSB 1 kW D RRF

2 kW

(a) an adder circuit (b) a subtractor circuit (c) a comparator circuit (d) a parity generator circuit 126. Which of the following is a self-complementing code? (a) 8421 code (b) Excess 3 code (c) Pure binary code (d) Gray code 127. A ROM is to be used to implement a “squarer” which outputs the square of a 4-bit number. What must be the size of the ROM?

C Digital Inputs 0 V to 5 V B

4 kW

–– Vout +

8 kW A LSB


48 134. A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5 number 24 will be represented by its BCP code 010100. In this numbering system, the BCP code 100010011001 corresponds to the following number in base-5 system x1 = 10101010 ® ® XOR ® Gray Code ¾¾¾¾ 135. Input ¾¾¾¾¾¾ Output

x 2 = 11111111

COMMON DATA AND LINKED ANSWERS TYPE QUESTIONS

Statements for Linked Answer Questions 140 and 141 Two products are sold from a vending machine, which has two push buttons P1 and P2. When a button is pressed, the price of the corresponding product is displayed in a 7-segment display. If no buttons are pressed, 0 is displayed, signifying ‘RS 0’. If only P1 is pressed, 2 is displayed, signifying ‘RS 2’. If only P2 is pressed, 5 is displayed, signifying ‘RS 5’. If both P1 and P2 are pressed, E is displayed, signifying ‘Error’. The names of the segments in the 7-segment display, and the glow of the display for 0, 2, 5 and E, are shown below.

Consider (i) push button pressed/not pressed is equivalent to logic 1/ 0 respectively. (ii) a segment glowing/not glowing in the display is equivalent to logic 1/0 respectively. 140. If segments a to g are considered as functions of P1 and P2, then which of the following is correct?

g = P1 + P2 ,d = c + e

3

as per the relation VDAC =

å 2n -1 bn

r =0

(b) g = P1 + P2, d = c + e

(c) g = P1 + P2 ,e = b + c (d) g = P1 + P2, e = b + c 141. What are the minimum numbers of NOT gates and 2-input OR gates required to design the logic of the driver for this 7-segment display? (a) 3 NOT and 4 OR (b) 2 NOT and 4 OR (c) 1 NOT and 3 OR (d) 2 NOT and 3 OR

Volts, where b3(MSB), b2,

b1 and b0 (LSB) are the counter outputs. The counter starts from the clear state.

decimal

136. A certain 12-bit BCD digital-to-Analog converter has a full scale output of 9.99 V. The converter step size is 137. What is the largest value of output voltage from an eight bit DAC that produces 1.0 V for a digital input of 00110010? 138. The number of unused states in a 4-bit Johnson counter is 139. Consider the Memory System with the following parameters: Tc = Cache access time = 100 nsec Tm = Main memory access time = 1200 nsec If we would like to use the cache per paging and the hit ratio of finding the page table entry in the cache is 98%, the effective of average paged memory access time in seconds is equal to

(a)

Statement for Linked Answer (Q. 142-143) In the following circuit, the comparator output is logic “1” if V1 > V2 and is logic “0” otherwise. The D/A conversion is done

4bit D/A converter

CLR

Clock

142. The stable reading of the LED display is (a) 06 (b) 07 (c) 12 (d) 13 143. The magnitude of the error between VDAC and Vin at steady state in volts is (a) 0.2 (b) 0.3 (c) 0.5 (d) 1.0 Statements for Linked Answer Questions 144 and 145 In the Digital-to-Analog converter circuit shown in the figure below, VR = 10 V and R = 10 kW.

144. The current l is (a) 31.25 mA (b) 62.5 mA (c) 125 mA (d) 250 mA 145. The voltage V0 is (a) – 0.781 V (b)– 1.562 V(c) –3.125 V(d)– 6.250 V Statement for Linked Answer Questions 146 and 147 An 8085 assembly language program is given below Line 1 : MVI A, B5H 2 : MVI B, 0EH 3 : XRI 69H 4 : ADD B 5 : ANI 9BH 6 : CPI 9FH 7 : STA 3010 H 8 : HLT 146. The contents of the accumulator just after execution of the ADD instruction in line 4 will be (a) C3H (b) EAH (c) DCH (d) 69H 147. After execution of line 7 of the program, the status of the CY and Z flags will be (a) CY = 0, Z = 0 (b) CY = 0, Z = 1 (c) CY = 1, Z = 0 (d) CY = 1, Z = 1 Statement for Linked Answer Questions 148 and 149 Consider an 8085 microprocessor system. 148. The following programme starts at location 0100H. LXI SP, 00FF LXI H, 0701 MVI A, 20H SUB M


49 The content of accumulator when the programme counter reaches 0109H is (a) 20H (b) 02H (c) 00H (d) FFH 149. If in addition following code exists from 0109H onwards. ORI 40H ADD M What will be the result in the accumulator after the last instruction is executed? (a) 40H (b) 20H (c) 60H (d) 42H Statement for Linked Answer Questions 150 to 152: A PLA realization is shown below:

150. The output f1(x2,x1,x0) is (a) x2 x 0 + x1x0

(b) x2x0 + x1 x 2

(c) x2 Å x0 (d) x2 Ä x0 151. The output f2(x2,x1,x0) is (a) Sm(1,2,5,6) (b) Sm (1,2,6,7) (c) SM (2,3,4) (d) None of these 152. The output f3(x2,x1,x0) is (a) Pm (0,4,6,7) (b) Pm (2,4,5,7) (c) Pm(1,2,3,5) (d) Pm (2,3,4,7) Statement for Linked Answer Questions 153 and 154: Consider the square-wave generator shown below

153. The frequency is (a) 35 kHz (b) 577 kHz (c) 700 Hz (d) 28 kHz 154. The duty cycle of this circuit is (a) 75% (b) 50% (c) 60% (d) None of these Statement for Linked Answer Questions 155 and 156 Consider the following sequential circuit.

155. For the given sequential circuit the next state equations for flip-flop A and B are (a) A+ = A(B' + X) + A'(BX' + B'X) and B+ = AB'X + B(A' + X') (b) A+ = A(B'X) + A'(BX' + B'X) and B+ = A(B' + X) + B(A'X') (c) A+ = A(B'X) + A'(BX') and B+ = A(B'X) + B(A'X') (d) A+ = A(B' + X) + A'(BX' + B'X) and B+ = A'X + B'X'A' 156. Which of the following represents correct output sequence when input sequence is X = 01100? (a) 01100 (b) 00101 (c) 10100 (d) 00110


50

4.

PAST GATE QUESTIONS EXERCISE 1.

(d) In binary coded pentary (BCD) number system, 24 is represented as 0 1 0 1 0 0 E5555F E5555F

(d)

¯ 2

¯ 4

Thus,

2.

When P stuck at 1, x will be 1 whatever be other inputs B and C. Hence, the output F, as shown above is A. (a) The truth table D0 1 1 0 0

D1 Q1 Q0 0 0 0 1 0 1 1 1 1 0

1

D0 = Q1

¯ 4

D1 = Q0

D3 = Q 2

D2 = 0 D1 = Q1 D0 = Q0

¯ 1

5.

Corresponds to 4231. (c) Thus, address range is 11111000 (F8H) to 11111111 (FFH)

6.

(c)

7.

(a)

8.

(b) Y = AB + CD = AB + CD

X

Y P Q

0 0

1 0

1 1

0 1

1 1

1 0

1 0

0 1

= AB × CD

Q1 and Q0 respectively.. (b) The states of counter and D/A converter will be

Q 2Q1Q0

¯ 3

¯ 2

0

Hence, the inputs D0 and D1 should be connected to 3.

1 0 0 0 1 0 0 1 1 0 0 1 E5555F E5555555F E5555 F E5555F

V0

000

0

0

0

0

0

001

0

0

0

1

1

010

0

0

1

0

2

011

0

0

1

1

3

100

1

0

0

0

8

101 110

1 1

0 0

0 1

1 0

9 10

111

1

0

1

1

11

000

0

0

0

0

0

001

0

0

0

1

1

010

0

0

1

0

2

9.

The minimum number of 2-input NAND gates = 3. 1 (b) At Q, frequency will be th of clock frequency and 4 a time delay of 2DT due to two flip flops. Alternately Assume initially Q0 = 0 J K Qn +1 1

1

Qn

The V0 waveform will be

Q0 acts as clock for second JK flip-flop.


51 10.

14.

(d)

M1 = (PQ)(P + Q)R + R éPQ + P + Q ù ë û

15.

= (P + Q)(P + Q)R + R éë PQ + P.Q ùû = (PQ + PQ)R + R(PQ + P Q)

11.

12.

= (PQ + PQ)R + R(PQ + PQ) Output M1 = (P XOR Q) XOR R (d) The output Out is 1 only when the mode (S) is 0, since then the UPPER MOSFET is shorted and connected to Vdd. Node S is zero when P = Q = 1 as it shorts then lower MOSFET’s Hence Output logic Y = P ANS Q

16.

(b) In signed 2’s complement, the MSB represents the signal P = 11101101 = (– 19)10 Q = 11100110 = (– 26)10 P – Q = – 19 – (– 26) = (7)10 (7)10 = 00000111 (c) LXI H, 30 A0H Content of HL pair is 30A0 DADH Content of HL is 6140 PCHL Content of PC = 6140 (a) The counting sequence is shown here CLK 0 1 2 3 4 5

(a)

(Q2 ) J1

(Q2 ) K1

(Q1 ) J2

(Q1 ) Q1 K2 0 1 1 1 1 1 0 1 1 1 1 truth table

Q2

1 0 1 1 0

1 0 1 1 0

1 0 0 1 0

0 1 0 0 1 0

J

The truth table is 17.

CLK D Q Q0 1 0 0

13.

0 0 1

1 1 0

0 0 1

P1 = 0,

0 I0 (= P + Q) 1 I1 (= P)

1

0

I2 (= PQ)

1

1

I3 (= P)

0 1 1 0

0 1

1 1

Qn +1

Q1 = P1Q 2 = 1

P2 = 1, Q2 = P2Q1 = 0 Then after a few seconds output, Q1 = P1.Q 2 = 1

Z

0 0

Qn

The output sequence is 11, 10, 00, 11, 10....... (c) For NAND latches, assuming Q1 = Q2 = 0 initially

(c) The functional table R S

K Qn +1

0 0

and Q2 = P2 .Q1 = 0 For NOR latches Q1 = P1 + Q 2 and Q2 = P2 + Q1 Q1 = Q2 = 0 (Initially) P1 = 0, Q1 P2 = 1, Q2 and, after a few seconds P1 = 1, Q1 P2 = 1, Q2

Hence, Z can be expressed as Z = R S(P + Q) + RSP + RSPQ + RSP = PR S + Q R S + RSP + RSPQ + RSP = PR S(Q + Q) + (P + P)Q R S + P(Q + Q)SR + PQRS + PQRS + PQRS = PQRS + PQRS + PQRS + PQRS + PQRS + PQRS + PQRS + PQRS + PQRS = PQR S + PQ R S + P Q R S + PQRS +

18.

(d)

{ (

=1 =0 =0 =0

)} {

}

é X + Z Y + Z + XY ù X + Z(X + Y) = 1 ë û Þ

é XZ + XY + XZY ù = 1 ë û

For X = 1, Z + Y = 1, Z = 0 [since 1.1 = 1, and 0 + 1 = 1]

PQ RS + PQRS + PQRS + PQRS


52 19.

(a) For 2-input AND gate, 24.

(d)

That can be implemented. F = I0 S1S0 + I1S1S0 + I2S1S0 + I3S1S0 where, I0 = C I1 = D I2 = C

The Ex-OR gate output Y = AB + AB can be implemented as

I3 = C × D S1 = A S0 = B 20. 21.

22.

23.

(c) (d) The service routine for vectored interrupts starts from a fixed location of memory which can’t be externally set. There are four vector interrupts. Interrupt Memory location TRAP 0024H RST 7.5 003CH RST 6.5 0034H RST 5.5 002CH The interrupts which can be delayed and rejected are maskable interrupts. The maskable interrupts are RST 7.5, RST 6.5, RST 5.5, etc. (d)

CLK

DA (Q B Å QC )

DB(Q A ) DC(Q B ) Q A

= A B(D + D) + AB(C + C)D + ABC(D + D) + ABC D = A BCD + A BC D + ABCD + ABCD + ABCD + ABC D + ABC D = SM (2, 3, 5, 7, 8, 9, 12) 25.

(b)

Q B QC

0 1 2

1 1

0 1

0 0

0 1 1

0 0 1

0 0 0

3 4 5 6 7

0 1 0 0 0

1 0 1 0 0

1 1 0 1 0

0 1 0 0 0

1 0 1 0 0

1 1 0 1 0

(c) MVI A, 45 H ® A = 45 H MOV B, A ® B = 45 H STC ® set carry flag = 1 CMC ® complement carry = 0 RAR ® rotate A The content of A becomes 22H. XRA B ® XOR with B A Å B Þ (22)H Å (45)H Output = 01100111 Content of A will be 67 H.

F(A, B, C, D) = A BC + ABD + A BC + ABC D

Hence range of the address is 2DOO – 2DFF Alternately

= 2D00 Maximum address

= 2D00 Hence range of the address is 2D00 – 2DFF


53 26.

30.

(d)

(d) Truth-table for the given circuit is, S1 (P) S0 Q Y 0 0 I0 = 0 0 1 I1 = 1 1 0 I2 = 1 1 1 I3 = 0 k-map for the above

= (xy) × (yx) = (x + y) × + (y + x) = x y + xy + xx + yy = x y + xy º

From the k-map, Y = PQ + PQ = XOR(PQ)

= x Å y = x y + xy 31.

27.

(b)

28.

X = AÅB ; Y = A 5 ; Z=C Putting the different possibility, F will be 1 if A = 1, B = 0, C = 0 (a) For Johnson counter sequence D2

29.

D1 D0

V0

0

0

0

+1

1 1

0 1

0 0

+4 +6

1

1

1

+7

0 0

1 0

1 1

+3 +1

0 0 0 +0 (d) If DA = QB and DB = QA Then after 00 next state is also 00. Hence (a) is not correct. If we see the states of QAQB then QB QA 0 0 1 1 0 1 1 0 0 0 We saw that if QA and QB have same value then next value of QA = 1 and if have different values then next value of QA = 0 Hence, DA = Q A eQ B

= QAQB + QA QB and DB = Q B .

(b)

Hence, Y = (PQ × QR ) × PR

32.

33.

= (PQ × QR) + PR [using De-Morgans theorem] = PQ + QR + PR which shows that if at least two inputs of P, Q, R are 1, then output is 1. (a) Initially QA and QB = 0 Let data = 0 DA QA DB QB Y = QA.QB Next clock let 0 0 1 0 0 DA = 1 1 1 0=1 1 1.1 = 1 Hence, when the data is changed from 0 to 1 output Y becomes 1. (a) The inverter given is CMOS inverter and since both NMOS and PMOS inverter have equal values of Houshold voltage, it is also known as symmetric inverter.

Fig. CMOS inverter characteristics


54 The characteristic of this inverter is illustrated above, it can be seen here that for VIN slightly greater than VT. PMOS (M1) stays in Triode region (linear region) and NMOS (M2) stays in saturation. As VIN increases, the drain current increase, voltage drop across M1 increase, and the output voltage reduces. At some point later, PMOS (M1) will enter into saturation region. Hence right option for M1 to be in linear region is Vin < 1.875 volts. 34.

38.

(b) The truth table Input

A 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

(d) Y = AX 0 + AX1 D = Y = AX0 + AX1; Qn+1 = D Initially,

D = 0; Q n +1 = 1

If A = 0, Y = X0 = 1 If A = 1; Y = X1 = 0 D = Y = 1 Þ Qn+1 = 1; Q n +1 = 0; If A = 0; Y = X0 = 0 If A = 1; Y = X1= 1

35.

(a) Y = ( A + B ) C = (A + B) + C = A.B + C

36.

(a)

A 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Out put

B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

B 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Y 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0

Hence, number of combinations for which the output has logic 1, is 6. Qnext = A.CLK.Q = A.CLK + Q Q next = A.CLK + Q If CLK =1 and A and B = 1, then

Q next = 1üï ý Noracearound Q next = 1ïþ If CLK = 1 and A = B = 0, then

37.

Q next = Q üï ý No race around Q next = Q ïþ Thus race around does not occur in the circuit. (a) f(X, Y, Z) = S(2, 3, 4, 5) The Karnaugh map of the given function is shown below.

39.

(a)

MVI A, 05H Þ [ A] = 05H MVI B, 05H Þ [ B] = 05H PTR : ADDB Þ [ A] = [ A] + [ B ] = 05 + 05 = 0 AH DCR B Þ [ B ] = [ B ] - 1 = 05 - 1 = 04 H

[ A] = 0 AH JNZ PTR Þ Jump to location PTR if

[ B ] ¹ 0 as [ B ] ¹ 0 so it will jump to PTR . [ A] = 0 AH [ B ] = 04 H ADD B Þ [ A] = [ A] + [ B ] Þ 0 A + 04 = OE H

[ B ] = 04 H DCR B Þ [ B ] = [ B] - 1 = 04 - 1 = 03H

[ A] = OE H Thus, the prime implicants are XY (first row) and XY (second row).

JNZ PTRÞ as [ B ] ¹ 0 jump to PTR


55

JNZ PTR Þ As [ B ] ¹ 0 jump to PTR

[ A] = OE H [ B ] = 03 H

[ A] = 13H [ B ] = 01H

PTR : ADD B Þ [ A] = [ A] + [ B ] = OE + 03 = 11H

[ B ] = 03H

PTR : ADD B Þ [ A] = [ A] + [ B ] = 13 + 01 = 14 H

DCR B Þ [ B] = [ B ] - 1 = 03 - 1 = 02 H

[ B ] = 01H

[ A] = 11H

DCR B Þ [ B] = [ B] - 1 = 01 - 1 = 00 H

JNZ PTR Þ As [ B ] ¹ 0 jump to PTR

[ A] = 14 H JNZ PTR Þ as [ B ] = 0 so it will not jump to PTR

[ A] = 11H [ B ] = 02 H

and skip this command and go to next line. [A] = 14 H [B] = 00H and at the end of program the content of accumulator A is 17 H.

PTR : ADD B Þ [ A] = [ A] + [ B ] = 11 + 02 = 13H

[ B ] = 02 H DCR B Þ [ B ] = [ B ] - 1 = 02 - 1 = 01H

40.

(c)

[ A] = 13H 41.

(d)

A15 A14 A13 A12 A11 A10 A9 0 0 0 0 1 0 × 0 0 0 1 1 0 × 0 0 1 0 1 0 × 0 0 1 1 1 0 ×

RAM1 RAM2 RAM3 RAM4

42.

(a)

A8 × × × ×

- 0800H 0BFFH ü - 1800H 1BFFH ïï ý - 2800H 23FFH ï - 3800 3BFFH ïþ

A7 × × × ×

A6 A5 A4 A3 A2 A1 A0 × × × × × × × × × × × × × × × × × × × × × × × × × × × ×

RAM1 RAM2 RAM3 RAM4

XOR X

P

Y

AND F

( X + Y )( X + Y ) + ( X Y + X )

Þ X + X Y + XY + ( X + Y ). X Þ X + XY + XY + ( X + Y ). X Þ X + X Y + XY + XY = X Y + X + XY = X Y + X (1 + Y ) Þ X Y + X = X (Y + 1) ÞX 43.

62.5 The frequency (in kHz) of the waveform at Q3 is f 1´106 103 ´103 = = = 62.5kHz 16 16 16 (a) P = X Å Y

=

44.

Q= PÅ Z

Q Z

XNOR

P= XÅY Q= PÅ Z F = P.Q F = [X Å Y].[P Å Z] F = [XY + XY].[PZ + P Z] F = [XY + XY][(XY + XY)Z + (XY + XY)Z] F = XYZ + XYZ


56 45.

(d)

F ( w, x, y, z ) = wy + xy + wxyz + w xy + xz + x y z

54.

(d)

S1

W = I0 S1W W = I1 S1W

= w( x + x) y ( z + z ) + xy )( w + w)( z + z ) + wxyz + wxy( z + z ) + xz ( w + w)( y + y ) + ( w + w) x y z

F = S2 (S1 W + S1 W) + S2 (S1 W + S1 W)

wxyz + w xyz + w xyz + (wxz + wxz )( y + y )

F = S2 (S1W + S1W) + S2 éë( S1 + W ) .(S1 + W) ùû

+( wx y z + w x y z )

F = S2 S1W + S2S1W) + (S2S1 + S2 W)(S1 + W)

F = y + x.z + x.z

(d)

F = S2 (S1 Å W) + S2 (S1 Å W) yz

yz

1

yz 1

1

1

1

1

wx

1

1

1

1

Let X = S1 Å W

yz

wx

wx

46.

F = S2 S1 W + S2 S1 W + S2S1 W + (S1S2 W)

yz

wx

1

Qn S Qn+1 0 0 0 0 1 1 1 0 1 1 1 0

F = S2 X + S 2 X F = S2 Å X F = S2 Å S1 Å W

00

S=1

S=1 10 S=1

51. 52. 53.

(b)

56.

(c)

W

Qn Qn+1 S 0 0 0 0 1 1 1 1 0 1 0 1

Q

Y

Z

F

0 1 0

Q Q 0

1

0

0 0 1

0 1 0

0 1 1

0 0 1

1

1

0

1

F = Y Z (WX + WX ) + Y Z (WX + WX ) F = WX Y + WXY

57.

(a)

58.

(a)

01 S=1

S

D

S

B

0

Y

0

Y

1

Y

1

0

D = SY + SY

11

(d) 2n–1 4 byte 1856357 can be written in pack BCD as 1856357C 0001 1000 0101 0110 0011 0101

X

F = YZQ + YZQ

A B

0111

1100

1-byte 1-byte 1-byte 1-byte Hence, total byte = 4 byte (c) M = XY , N = X Å Y (c) Only option (c) W3 waveform is correct because flip flop will work for negative edge triggered clock pulse. (d) (d) (d) Master - Salve D Flip - Flop

B = SY

C

C

S=0

49. 50.

55.

1

S=0

47. 48.

Y = S1W + S1W

F = S 2Y + S 2Y

= ( wx + wx)( yz + yz ) + (wxy + wxy)( z + z )

wx

Y

AB + AB

Y AB + AB + C

A B

AB

Y = ( AB + AB + C + AB ).C Putting C = 0 & AB = AB + AB Y = AB + AB Y = AB. AB Y = ( A + B ).( A + B )

Y = AB + AB Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

AB + AB + C + AB

57 59.

(a)

5.

Y = A.B.C

(d)

Y= A+ B +C 60.

(c)

S2 A 0

S1 S0 B C 0 0

y I0 = 0

0 0

0 1

1 0

I1 = D I2 = 0

0 1 1

1 0 0

1 0 1

I3 = D I4 = 0 I5 = 0

1 1

1 1

0 1

I6 = 1 I7 = 0

f = å m ( 0,3, 6 ) = å m (1, 2, 4, 5, 7 )

7.

(d)

Z = D A B C + A BC + ABC + AB C + ABC

(

(

)

(

= D B A + B C + BC = D B e C + A B (b)

)

f1 = CB,S1 = F1

= C + B + A = ABC

00101010 000000000101010 11010110 1111111111010110

)

9.

11.

( A + B)( B + C) = ( A B)( BC) = A BC

(

)

A + B ( B + C ) = A + B + ( B + C)

= AB + B + C = A + B + C

)

(

)

= A ( B + C) + A = A + B + C

)

( A + B ) ( B + C ) = ( A + B) + ( B + C ) = A + B + C

Z = ABC + AB + AB + AB

(

10.

AB + BC + AC = A + B + B + C + A + C = A + B + C

(d)

= A BC + B + A B + B

ABC = A + B + C

4.

)

f = f 1 + f1 A = CB + CBA = CB + A

(

)

(

( ( ) ( ) ) = D ( AB + BC + ABC) = D( B + ( A + AC) + BC)

Z = A + AB + BC + C

(

)

(b)

8.

(c) 42 in a byte 42 in a word – 42 in a byte – 42 in a word

(b)

) (

6.

= A+ A+B+B+C +C = A+B+C

3.

(

= D A B C + C + BC A + A + AB C

Y = ACD + ABC 194.9 to 195.1 (a)

(d)

)

= A Å BÅ C

PRACTICE EXERCISE

2.

) (

= C AB + AB + C AB + AB

Y = ACD(B + B) + ABC

1.

(

= C AB + AB + C AB + AB

Y = ABCD + ABCD + ABC

61. 62.

A BC + ABC + A B C + ABC

12.

(a) At first edge of clock, D is HIGH. So Q will be high till 2nd rising edge of clock. At 2nd rising edge. D is low so Q will be LOW till 3rd rising edge of clock. At 3rd rising edge. At 4th rising edge D is HIGH so Q will be HIGH till 5th rising edge. At 5th rising edge, D is LOW, so Q will be LOW till 6th rising edge. (b) Propagation delay if 4-bit ripple counter R = 4 × tpd = 40 ns In synchronous counter, all F/Fs are given clock simultaneously. So S = 10 ns (c)

A B S R 0 0 1 0

Q Q+ 0 1

0

1

0 1

0

1

0 1 0 1 0 0 From truth table Z = A + B + C 0 1 0 1 1 0 Option (b) is correct. 1 0 0 0 0 0 (d) Output of NAND must be LOW for LED to emit light. 1 0 0 0 1 1 So both input to NAND must be HIGH. If any one or 1 1 1 1 0 x both switch are closed, output of AND will be LOW. If 1 1 1 1 1 x both switch are open, output of XOR will be LOW. So there can’t be both input HIGH and NAND. So LED Q+ = AB + AQ = AB + BQ doesn’t emit light. Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

58 13.

(b) Output of 1st XOR = X1 + X1 = X

19.

Output of 2nd XOR = X X + X X = 1 14.

So after 4, 6, 3 .........20 XOR output will be 1 (b) It is a down counter because 0 state of previous FFs change the state of next FF. You may trace the following sequence, let initial state be 0 0 0

16.

17.

111 110 111

101 100 011

001 001 000

000 110 001

110 111 110

010 001 000

(a) It is a 5 bit ripple counter. At 11000 the output of NAND gate is LOW. This will clear all FF. So it is a Mod-24 counter. Note that when 11000 occur, the CLR input is activated and all FF are immediately cleared. So it is a MOD 24 counter not MOD 25. (d) 10-bit counter is a MOD-10, so it divides the 160 kHz input by 10. Therefore, w = 16 kHz. The four bit parallel counter is a MOD-16. Thus, the frequency at x = 1 kHz. The MOD-245 ripple counter produces a frequency at y = 40 Hz. (1 kHz/25 = 40 Hz). The four-bit Johnson counter is a MOD-8. This, the frequency at z = 5 Hz. (b) The output of XOR gate is Z = bi +1 Å bi and this output shift the register to left, Initially Z = 0 After 1st clock Z = b7 Å 0 = b7

n£

20.

21.

1 0

0 0

0

0

0

VCC - 3.5 5 - 3.5 = = 15.6 Þ n £ 15 R C I B( sat ) 640 ( 0.15m )

(a) Let V1 = V2 = 0V, then M3 will be ON. M1 and M2 OFF and M4 ON, hence V0 = – VDD. Let V1 =0 V and V2 = – VDD then M3 will be ON, M1 OFF M4 OFF, M2 ON, Hence V0 = – VDD. Let V1 = – VDD and V2 = 0 V, then M3 OFF, M4 ON, M2 OFF hence V0 = – VDD. Finally if V1 = V2 = – VDD, M3 and M4 will be OFF and M1, M2 will be ON, hence V0 = 0 V. Thus the given CMOS gate satisfies the function of a negative NAND gate. (d) A positive noise spike can drive the voltage above 1.0 V level if the amplitude is greater than

VNH = VOH ( min ) - VIH ( min ) = 4.9 - 3.5 = 1.4V

22.

23.

(a) (Digital value) × resolution > VA + VT (Digital value) × 40 mV > 6.001 V = 6001 mV Digital value > 150.025, 15110 = 100101112 (b) VH = 5.6 + 0.7 = 6.3 V, VL = – 5.6 – 0.7 = – 6.3 V Let 1 kW = R1, æR ö æR ö VTH = - ç 1 ÷ VL , VTL = - ç 1 ÷ VH è R2 ø è R2 ø

(a) When Q1 is saturated, V01 is logic LOW otherwise V01 is logic HIGH. The following truth table shows AND logic.

0 1

5 - 0.2 = 0.15mA 50 ( 640 )

A negative noise spike can drive the voltage below 3.5 V if the amplitude is greater than

4th clock Z = b5 Å b4

V3 1

bR C

VNL = VIL( max ) - VOL( max ) = 1 - 0.1 = 0.9V

3rd clock Z = b6 Å b5

V1 V2 1 1

VCC - VCE( sat )

To assure no logic error V0 = VCC - I0 R C > VH = 3.5V

After 2nd clock Z = b7 Å b6

18.

=

For n attached gate I0 = nI B( sat )

JKC JKB JKA C B A 111 111 111 111 000 000 110 110 110 001 111

b

=

+ + +

000 000 111

IC( sat )

IB( sat ) =

FFC FFB FFA

15.

(c) For each successive gate, that has a transistor in saturation, the current required is

VTH - VTL = 1 =

Þ 1= 24.

25.

R1 ( VL - VH ) R2

1K ( 2 )( -6.3 ) Þ R2 = 12.6 kW R2

(d) The Boolean expression X(P, Q, R) = p(0.5) OR and XOR only two points gates. (c) 26. (c) 27. (d)


59 35. 28.

(a)

AB 00 CD

01

00

11

10

1

1

01

(d) S2 = C + 0 = C; S1 = B; S0 = A S2 = C S1 = B S0 = A Y

1

11

1

10

1

1

1

BC

(b)

0 0

0 1

C C

1 1

0 0

C C

36.

(

)

A 0 0 1 1

B 0 1 0 1

I C C C C

F= A B C + A B C + A B C + A B C

32.

0

0

1

0

0

0

1

1

1

1 1

0 0

0 1

0 1

1

1

0

1

1

1

1

0

(d) After 1st pulse Y1 = 0 Y2 = 1 After 2nd pulse Y1 = 0 Y2 = 0 After 3rd pulse Y1 = 1 Y2 = 0 After 4th pulse Y1 = 1 Y2 = 1 (c) I = IC = 1 mA (\ BJT is in saturation) VBEsat = 0.75 Þ 0.75 = IR. 1 K

33.

IR = 0.75 mA (d) Half-adder is a 1-bit adder circuit.

34.

(a)

A B C ABC + ABC + ABC

(

)

A C + B + B + ABC + ABC A C + ABC + ABC

(

)

(d) NAND & NOR are universal gates, so along with MUX they can be used to implement any combinational circuit. (c) J A = QB

K A = 1 J B = QA

X

When code is 0101 then the function is Y = B

31.

1

1

( ) ( Y = C ( A Å B) + C ( A Å B)

Y = AB + AB = A B + B = A

(d)

0

0

Y = C A B + AB + C AB + AB B A

37.

30.

0

0

Y = A B C + ABC + A BC + ABC

The expression is Y = A + BC 29.

0

X

X

1

1

1

1

0

1

K B = 1 QA

QB

X

X

0

0

1

1

0

1

1

0

0

0

1

0

0

ü ï ý MOD - 3 ï þ

38. 39.

(b) (d) MOS devices have low switching losses but high onstate losses.

40.

(b)

41.

(d)

% resolution =

J0 K 0 11 11

(

1 12

2

)

-1

´ 100

J1K1 Q0 Q1 0 1 0 0 1 0 1 0

Initially 1st pulse

0 1 11 11

0 1 0 1 1 0

0 1 0 0 1 0

2nd pulse 3rd pulse 4th pulse

0 1

0 1

0 1

5th pulse

After 4th pulse, output is same as after 1st one. So, sequence gets repeated. So output after 3rd pulse would be same as after 3rd pulse, i.e. (0, 0).

)

A C + BC + ABC = A C + B C + A B


60 42.

(b) These stage Johnson ring counter is a MOD-6 counter: Q0Q1Q2 will follow the normal sequence as expected i.e. 000 ® 001 ® 011 ® 111

55.

44.

(c) The circuit must consist of at least MOD -6 counter as it will from (0000) to (0101) i.e. 6 states (minimum). (d)

45.

(a)

(

)

(

)

(

YZ+ XZ+ XY = YZ X+ X + XZ Y+ Y + XY Z+ Z

)

and C = 56.

= X Y Z + X Y Z + X Z Y + X YZ 46. 48.

49.

50.

t pd

=

1 265 ´ 10-9

750 - 2 ´ 750 = 1.5 kHz 0.25

tp 0.693R B

=

0.25 ´ 10-6 = 480 pF 0.693 ´ 750

(c) Upper threshold point,

Þ VTH = 2V lower threshold point.

æ 5 ö æ 10 ö æ 20 ö çè ÷ ( -10) = çè ÷ 2 + çè ÷V 5 + 20 ø 10 + 20 ø 10 + 20 ø TL

= 3.774 MHz

VTL = – 4 V

(d) After 16 × 2 = 32 pulse ‘0000’ After 37 pulses 0110 – 0101 = 0001

57.

(a) Output = Y1.Y2 = AB. CD

58.

(c)

59.

(d) TTL circuit with active pull-up are preferred for reasonable dissipation and speed of operation. (d) The wait time can be calculated in the following manner: Time to read 1 sector 0.0010 Time to write 1 sector 0.0010 Time to execute 200 instructions 0.0002 Total program cycle time 0.0022 Wait time = 0.0020/0.0022 × 100% = 91% (a) After instruction: 2000 SP ® 1000 PC ® 2003 2003 SP ® OFF DE (SP decrement by 2) 2004 SP ® OFFC (SP decrement by 2) 2005 PC ® 2050 SP has OFFC, PC has 2050 (d) (a) STC CY 1 1 CMC CY CY CY 0 MOV A A B A¬B RAL Rotate all left MOV B, a B¬A (c) MVI A, 30 H A = 30 ACI 30 H A = 60 XRA A A= 0 POP H

Sin 1 0 1 0

51.

1

RB R A + 2R B

æ 5 ö æ 10 ö æ 20 ö ç ÷ (10 ) = ç ÷2+ç ÷ VTH è 5 + 20 ø è 10 + 20 ø è 10 + 20 ø

(b) 47. (b) (a) MOD-12, 4FFs = 4 × 60 = 240 ns tpd of NAND = 25 ns total tpd = 265 ns So, fc =

Duty cycle =

Þ RA =

¾¾ ®100 ¬ 110 ¬¾ ¾

43.

(b)

A B C D 0 1 1 0 1 0 1 1 0 1

(d) Decimal 0 1 2 3 4 5 6 7 8 9

1 0

0 1

1 0

60. 0 0 0 0 0 0 0 0 1 1

BCD 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0

0 1 0 1 0 1 0 1 0 1

Gray Code 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 4 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 0 1

0 1 3 2 6 7 5 4 12 13 + 53

52. 53.

(a) (d) May be 3, 3 + 16, 3 + 16 + 16 or 3 + 16 + 16 + 16

54.

(a)

fQ = 3

10kHz = 625Hz 16

61. 62.

63.


61 64.

(c) The sequence of instructions executed, MVI A, 10H MVI B, 10H NOP

0 CY

ADD

BA ® 20 H =

69.

(d)

RLC A ® 0 1 0 0 0 0 0 0 = 40 H 0 CY

70.

START:

ADD B A ® 0 1 0 1 0 0 0 0 = 50 H CY 0 RLC

A ® 1 0 1 0 0 0 0 0 = 40 H

JNC

CY 0 A ® 1 0 1 1 0 0 0 0 = 130 H

NEXT:

71.

(d)

72.

(a)

73.

(a)

74.

(a)

75.

(b)

RLC JNC 65. 66. 67.

68.

A ® 0 1 1 0 0 0 0 1 = 61 H

(d) (a) This instruction compare the contents of B with the contents of accumulator. (b) The ORA A instruction reset the CY flags S Z CY × × × MVI A, A 9H × × × × × × ADD B 0 1 1 ORA 0 1 0 (a) MVIA, MOV

DATA 1 B, A

; DATA1 ® A ; A® B

SUI JC MOV

51H DLT A, B

SUI JC

82H DSPLY

; A – 51H ® A ; IF CY= 1, Jump on DLT ;B®A ; A – 82H ® A

; DSPLY

XRA OUT

A PORT1

DSPLY:

MOV OUT HLT

A, B PORT2

B, 4AH 4FH B

; Clear A ; A ® PORT1 ;B®A

MVI MOV JMP XRA

B, 87H A, B NEXT B

JP

START

JMP XRA JP

NEXT B START

;B = 87 a = B = 87 ; Jump to next ; A ÅB ® A ; A = 00, B = 87 ; Since A = 00 is positive ; so jump to START ; Jump to NEXT ; A Å B ® A, A = 87,

; will not jump as D7, of A ; is 1 ; A = 87 ® PORT2 OUT PORT2 All instruction clear the accumulator XRA A ; A ÅA ANI 00H ; AND 00 ;00 ® A MVI A This instruction XRA will set the Z flag. LXI and DCX does not alter the flag. Hence this loop will be executed 1 times. RAL instruction rotate the accumulator left through carry. D7 ® CY, CY ® D0, ORA reset the carry. Accumulator CY Before RAL 10110111 0 After RAL 01101110 1 This program multiply BYTE1 by 10. Hence content of A will be 46H. 07H = 0710, 7 × 10 = 70, 7010 = 46H At a time 8085 can drive only a digit. In a second each digit is refreshed 500 times. Thus time given to each digit 1 = ( 5 ´ 500 ) = 0.4 ms

; If CY = 1, Jump on

DLT:

MVI SUI ANA HLT

;Clear A ;4A ® B ;A – 4FH ® A = B1H ;A AND B ® A = 00

(b)

NOP CY 0

ADDB

A

A = 00, B = 4A Thus d is correct option

0 0 1 0 0 0 0 0

JNC

XRA

76. 77. 78. 79.

; A ® PORT2

80.

(a) (b) 4k = (4096)10 = (1000)H (b) (c) 2 chips of 32k × 16 are required as 8085 microprocessor has 64 k address space and only lower 8 data bits can be used out of 16 data bits as 8085 mP has 8 bit data bus. (a) 81. (c)


62 82.

83. 84. 85. 86.

87. 88. 89. 90. 91. 92. 93. 94.

95. 96.

97.

98.

(a) Between CPU and main memory. Cache Memory is a small high-speed memory placed between the CPU and the RAM. It holds the currently active data and/or program segment. (b) When a CPU is interrupted. It acknowledges interrupt and branches to a subroutine. (c) The RST instruction will cause an interrupt only if interrupts have been enabled by an EI instruction. (a) The stack pointer in the 8085 microprocessor is a 16 bit register that point to stack memory locations. (d) Bus expansion increases data flow by a factor of 32/8 = 4. Likewise, operating at a higher clock-speed causes a speed-up of at most 20/5 = 4. Assuming that operating system and components support it, a speed up of 4 * 4 = 16. (c) Since if RAM is not enough, data has to be stored on disk and hence disk I/O is needed which is wastefull of time. (d) (d) The entire word can be read in one operation provided the first memory address is even. (d) The two co-processor instruction sets must be the same as that of the host. (c) Registers are used for variable names in symbol tables (d) (b) (a) CMP B will compare contents of reg. B with accumulator, upon finding that B reg. contents are more than accumulator CY = 1 and since data are not equal z = 0. (b) A single instruction to clear the lower four bits of the accumulator in 8085 assembly language is ANI FOH. (b) It can be proved by induction that a strictly binary tree with ‘n’ leaf nodes wil have a total number of 2n – 1 nodes. So number of non-leaf nodes is (2n – 1) – n = n – 1. (d) The given decimal number can be written as (1 + 2) × 212 + (1 + 2 + 4 + 8) × 28 + (1 + 4) × 24 + (1 + 2) = 213 + 212 + 211 + 210 + 29 + 28 + 26 + 24 + 21 + 20. This has 10 one’s. (c) PROM contains a fixed AND array and a programmable OR array is the correct statement. VCC

Vo

Q3 Vi1

Vi2

Q1

Q2

99.

(d) Q1 and Q2 form direct coupled transistor logic (DCTL) giving NOR output Vi1 Vi2 0 / PQ1 0 / PQ2 L ( 0 ) L ( 0 ) H (1) H (1) L ( 0 ) H (1) L ( 0 ) L ( 0) H (1) L ( 0 ) H (1) H (1)

L (0) L (0)

Logic 1 0

L ( 0) L ( 0)

0 0

Logic NOR Q3 is an inverter. \ V0 = OR

100. (c)

Clock Pulse 0

Remarks

State rd

th

0110

3 and 4 SR being 1, 0

After 1

0110

O/p of XOR is 1

After 2

0110

O/p of XOR is 1

After 3

0110

O/p of XOR is 0 for 1.1

101. (d) 102. (d) The output of ADC; VO = 6.6/0.5 = 13.20 » 14 . Hence, the binary equivalent will be 1110. 103. (c) Maximum I/O spare which can be addressed by 8088 CPU is 65536. 104. (a) Metastability in D-Flip flop occurs when set-up time of input data is not met. 105. (b) 12, 64, 8 and 0 are all power of 8. The proceeding number is translatable in second to an octal number 3 × 83 + 7 × 82 + 5 × 81 + 3 × 80 37536 = 011 111 101 0112 106. (d) The basic memory cell of dynamic RAM consists of a transistor acting as a capacitor. 107. (d) The ROM is a permanent type of memory; it contains memory cells that are permanently programmed by the manufacturer with a specific pattern of 1 s and Os. In some types, the ROM is programmed by the user, it is then programmable read only memory. 108. (b) % resolution =

1 n

(2 - 1)

´ 100 =

= 0.09775 » 0.1% Buy books : http://www.dishapublication.com/entrance-exams-books/gate-exams.html

100 10

2

-1

63 periods. To achieve this, the external control logic makes READY input t0 state T2 logic 0. When input to T2 is logic 0, the microprocessor enters state Tw (LWATT) instead of T3. When READY logic becomes 1, the machine cycle goes to state T3.

109. (a) If all inputs A, B and C are HIGH, then input to invertor is low and output Y is HIGH. If all inputs are LOW, then input to invertor is also LOW and output Y is HIGH. In all other case the input to inverter is HIGH and output Y is LOW.

(

Y = ABC + A B C = ABC + A + B + C

)

TR

110. (c) There will be three bytes, one for op-code LOA and two for 2003 111. (b) A - 3, B - 4, C - 1 112. (d) The Boolean expression is

(

)

(

T1

)

RESET

HALT

T3

A B + C + AB + A + B C

= AB + AC + AB + AC + BC

(

) (

T2

)

= AB + AB + AC + AC + BC = B + A + BC = A + B + C 113. (a) Carry look ahead adder is faster since the carry is generated in parallel at all stages of addition rather than sequentially as in ripple adders. 114. (a) It is a shift register. 115. (a) (i) Interface: The common boundary between various sections and sub-section (ii) Bit: A binary digit (iii) Baud Speed: A measure of rate of data transmission. 116. (b) For 1 Byte memory, the number of chips required 102 ´ 8 = 32 256 117. (c) A – 3, B – 1, C – 4, D – 2 118. (c) One mod-13 counters followed by the mode - 6 counter will result in mod-N counter where N is divisible by both 13 and 6 i.e. 78.

A0 A6

MOD 3

A0

MOD 6

COUNTER

A6

COUNTER

MOD 78

T3

Ready

OFF OFF

T3

T4

T5

So during the WAIT state all external signals from the microprocessor are held in the same state as they were at the end of state T2. By this method, the duration of the address is stretched and access times greater than that of microprocessor accommodated. 122. (a) DCTL gates. 123. (a) To reduce consumption, LEDs are loaded with resistors as in a & c. Between a & c, a is more satisfactory because the LED current is supplied by power supply instead of the gate in c. However, the logic of a is low level as it glows when input is HIGH. 124. (a)

y = C + A, y = A 'C '

125. (c)

X

Y

OUTPUT

119. (b) Less than m/2. Hamming code is an error detecting correcting code used in data transmission. When used with a 7-bit block, there would be information bits at 1, 2 and 4. This code detects all single and double errors in the block. 120. (c) 2n – 1 = 24 – 1 = 16 – 1 = 15. 121. (d) Here, it may be noted that to accommodated long access times, the microprocessor 8085 has a state called WAIT state. When the microprocessor generates an address in state T1 external control logic that monitors this state may ask the microprocessor to wait for a certain period of time, which are integrals of check

T6

F1

F2

F3 The circuit given above is a comparator circuit. When X < Y, F1 = 1; when X = Y, F2 = 1 and; When X > Y, F3 = 1


64 126. (b) Excess 3-code is self complementing code that means the 9’s complement of the decimal number is easily obtained by changing ones to zeros and zeros to ones. 127. (b) Therefore, the output Y is not determinable. 128. (b) SR latch is shown in figure

R

Q

Q

S

129. 130.

131.

132.

A latch employs cross – coupled feedback connections. (ii) Registers are made of edge triggered FFS, where as latches are made from level triggered FFS. (c) 15 No. of comparators in a flash ADC is equal to 2 n – 1 where n = no. of bits. 24 – 1 = 15. 3 Each diode causes a voltage level loss of 0.75 V. Therefore 0.75n < 2.5 V Þ n = 3. 6.95 Step size =

9.99 = 10 mV 999

0110 1001 0101 6 9 5 Þ 695 × 10 m = 6.95 V 133. 800 RF ´ 5 = 0.5, R F = 800 W Step size = 8k

134. 4231 100010011001 ® 4231 135. 127 01010101 xl Å x2 = = 0111111 = +127 Gray Code

136. 0.01 9.375 = – 2.3444 V 4 for 12 bit BCD, decimal no. is 000 to 999

Step size output is -

Step size

9.99V = 0.01 V 999

137. 5.10 (00110010)2 = 5010 1.0 V = K × 50 Þ K = 20 m the largest output for input (11111111)2 = 25510 Vout(Max) = 20 mV × 255 = 5.10 V 138. 8 Johnson counter is 2N – 1 counter where, N = Number of bits 2 × 4 = 8 states (used) Total States = 2N = 16 Remaining states 16 – 8 = 8 states 139. 340 We may consider the hit ratio of 98% as the probability of finding the page table entry if the associative memory (cache) Accordingly, with 98% probability the page memory access time will be: Cache access time for page number memory access time = 100 ns + 120 ns = 220 ns The other 2% of the time, the search in each will fail and the page number will be obtained through and additional normal memory access. Accordingly: Cache access time + memory access for page no. + memory access time: = 100 ns + 120 ns + 120 ns = 340 ns 140. (b) As per question, the truth table P1 P2 0 0 0 1 1 0

a 1 1 1

1

1 0 0 0 1 1 1

1

b 1 0 1

c 1 0 0

d 1 1 1

e 1 0 1

f 1 1 0

g 0 1 1

Hence, a = 1 b = P1 P 2 + P1 P 2 = P 2 (P1 + P1 ) = P 2 c = P1 P 2 + P1P2 = P1 (P 2 + P2 ) = P1 d=1 e = P1P2 = P1 + P 2 f = P1 P 2 = P1 + p 2 g = P1 P 2 = P1 + P2 141. (d) a = 1 b = P 2 Þ 1 NOT gate required c = P1 Þ 1 NOT gate required e = P1 + P 2 Þ 1 OR gate required f = P1 + P2 Þ 1 OR gatre required g = P1 + P2 Þ 1 OR gate required Hence, 2 NOT and 3 OR gates required.


65 From concept of virtual ground VA = 0 (Grounded) Hence, current from voltage source

3

142. (d) VDAC

n +1 = å 2 bn n =0

= 2–1 b0 + 20b1 + 21b2 + 22b3 Counter output will start from 0000 and will increase till Vin > VDAC. When VDAC = 6.5 V, the comparator output will be zero and the counter will be stable at that reading and the number displayed at LED will be 13. The counting sequence is shown below.

b3

b2

b1

b0

VD AC

0 1

0 0

0 0

0 0

0 1

0 0.5

2

0

0

1

0

1

3

0

0

1

1

1.5

4

0

1

0

0

2

5

0

1

0

1

2.5

6

0

1

1

0

3

7

0

1

1

1

3.5

8

1

0

0

0

4

9

1

0

0

1

4.5

10

1

0

1

0

5

11

1

0

1

1

5.5

12 13

1 1

1 1

0 0

0 1

6 6.5

14

1

1

1

0

7

15

1

1

1

1

7.5

143. (b) Error voltage = VDC – Vin = 6.5 – 6.2 = 0.3 volts 144. (b)

l=

VR 10 = = 1 mA R 10 ´103

Due to symmetry in the branches of circuit, the current division among various branches is

Hence, current =

l 1mA A= = 62.5mA 16 16

145. (c) The voltage Vo = – loR

æ 1 1ö = -ç + ÷ R è 16 4 ø æ 5l ö = -ç ÷ R è 16 ø =–

5 ´ 1mA ´ 10 kW = – 3.125 V 16

146. (b) After line (1) A contains B5 H After line (2) B contains OEH After line (3) A is XOR with 69H A 10 11 01 01 69 01 10 10 01 DC 11 01 11 00 After XOR A contain DC Now adding B to it 11 01 11 00 00 00 11 10 11 10 10 10 So after line 4, A = EAH 147. (c) Now line 5 ANI 9BH and immediate accumulator with 9BH (A) 11 10 10 10 9BH 10 01 10 11 10 00 10 10 Accumulator store 8AH in line 6 compare immediate with 9FH Since 9FH is greater than 8AH so carry flag will be generated, while zero flag remain unaffected.


66 148. (c) 0100H : LXI SP, 00FF ; Load SP with 00FFH 0103H : LXI H, 0701 ; Load HL with 0107H 0106H : MVI A, 20H; MOV 20H to accumulator 0108H : SUB M; subtract the contents of memory location whose address is stored in HL from A and result will be stored in A. 0109H : ORI 40; [A] – OR 40H ® [A] 010BH : ADD M ; [Memory location] + A ® [A] When program counter reaches 0107H; HL contains 0107H and content of 0107H is 20H. When PC reaches 0109H subtraction of 20H with 20H and result is stored in accumulator, i.e., content of accumulator in 00H. 149. (c) ORI 40H ® 00000000 01000000 OR [A] = 01000000 = 40 H ADDM ® [A] + [HL] = 40 H + 20 H = 60 H 150. (c) f = x0 x 2 + x0 x1 x2 + x 0 x2 = x0 x 2 (1 + x1 ) +

x0 x2

= x0 x 2 + x 0 x2 151. (b) f2 = x 0 x1 + x1x2 + x0 x1 x 2 = x 0 x1x2 + x 0 x1 x 2 + x1x2x0 + x1x2 x 0 + x0 x1 x 2 = x2x1 x 0 + x 2 x1 x 0 + x 2 x1 x0 + x2x1x0 f2(x2,x1,x0) = Sm(1, 2, 6, 7) 152. (c) f3 = x 0 x1 + x1x2 = x2 x1 x 0 + x 2 x1 x 0 + x2x1x0 + x2x1 x 0 f3(x2, x1, x0) = Sm(0, 4, 6, 7) f3(x2, x1, x0) = Pm(1, 2, 3, 5)

153. (b)

f=

1 , C = 0.5 mF 0.693(R A + 2R B )C

f=

1 = 577 Hz 0.693(1k + 4k)0.5m

154. (c) RA = 1 kW, RB = 2 kW RA + RB Duty cycle is D = R + 2R + 100 A B

1+ 2 ´ 100 = 60% 1+ 4 155. (a) A+ = AK'A + A'JA = A(B' + X) + A'(BX' + B'X) and B+ = B'JB + BK'B = B'(A' + X')' + B((A' + X')')' = B'AX + B(A' + X') = AB'X + B(A' + X') 156. (b) X = 0 1 1 0 0 AB = 00 00 10 11 01 11 Z = 0 0 1 0 1 Initially ® 101001111000 After 1st clock ® 010100111100 After 2nd clock ® 001010011110 After 3rd clock ® 000101001111 After 4th clock ® 000010100111 After 5th clock ® 100001010011 After 6th clock ® 110000101001 After 7th clock ® 111000010100 After 8th clock ® 111100001010 After 9th clock ® 011110000101 After 10th clock ® 001111000010

=


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