ASSIGNMENT 2:EE 705- VLSI DESIGN LAB
DESIGN OF 8-bit ALU INDRANIL CHAKRABOR CHAKRABORTY TY
ROLL - 143070072
ELECTRICAL ENGINEERING MICROELECTRONICS
DATE – 30th January, 2015
IIT BOMBAY
DESIGN OF A 8-BIT ALU FUNCTION: The ALU decodes a 2-bit op-code to decide the function to be performed on its two inputs X and Y to produce Z. BLOCK DIAGRAM:
x0-x7 8-bit ALU
z0-z7
y0-y7 Op_code0-Op_code7
DESCRIPTION:
The Alu8 computes Z as a function of X and Y. The following functions are to be supported: Op_code 00 01 10 11
Operation Z=(X+Y) Z=(X-Y) Z=(X>>Y) Z=(X<
Remark Addition Subtraction Logical Right Shift Logical Left Shift
DATA FILE GENERATION: We have written a C++ implementation of the ALU to generate a test file for our testbench. The organization of the test data file is as follows: Opcode
X
Y
Z
And for each opcode there are 65536 entries of X and Y because X and Y are 8-bit vectors. There are 4 combinations for opcode. So, total number of entries in the data file is 65536*4=262144. Note: Logical shifts more than 16-bit are not allowed in C++. So, a function has been defined to implement more than 16-bit shift.
SAMPLE C++ PROGRAM: #i ncl ude #i ncl ude #i ncl ude #i ncl ude usi ng namespace st d; i nt l s r ( i nt ar , i nt n) / / Logi cal Ri ght Shi f t f unc t i on { f or ( i nt i =0; i >1; } r et ur n ar ; } i nt l s l ( i nt ar , i nt n) / / Logi cal Lef t Shi f t f unct i on { f or ( i nt i =0; i
i nt mai n( ) { i nt x, y, z , op; s t r i ng xs , ys , z s , ops ; of s t r eam out put Fi l e; out put Fi l e. open( " dat a. t xt " ) ; / / Open Fi l e Command
f or ( op=0; op<4; op++) { f or ( x=0; x<256; x++) { f or ( y=0; y<256; y++) { xs = st d: : bi t set <8>( x) . t o_st r i ng( ) ; / / f unct i on conver t s an i nt eger t o a bi nar y st r i ng ys = st d: : bi t set < 8 >( y) . t o_st r i ng( ) ; ops = st d: : bi t set <2>( op) . t o_st r i ng( ) ;
i f ( ops==" 00" ) { z=x+y; zs=st d: : bi t set <8>( z) . t o_st r i ng( ) ; } el se i f ( ops==" 01") { z=x- y; zs=st d: : bi t set <8>( z) . t o_st r i ng( ) ; } el se i f ( ops==" 10") { z =l s r ( x, y) ; zs=st d: : bi t set <8>( z) . t o_st r i ng( ) ; } el se i f ( ops==" 11") { z =l s l ( x, y) ; zs=st d: : bi t set <8>( z) . t o_st r i ng( ) ; } out put Fi l e<
VHDL ORGANIZATION OF DUT Entity:
An entity is defined specifying the input and output ports.
ent i t y Al u8 i s por t ( X, Y: i n bi t _vect or ( 7 downt o 0) ; Z: out bi t _vect or ( 7 downt o 0) ; op_code: i n bi t _vect or ( 1 downt o 0) ) ; end ent i t y; Architecture and Process: The Architecture is designed using a Process statement which has a sensitivity list consisting of vectors X and Y. That is the process statement is processed whenever there is an event on X or Y.
For arithmetic operations, we convert bit_vector type X an d Y into unsigned using:
xu : = unsi gned( X) ; yu : = unsi gned( Y) ; The opcode decides which operation should be performed on X For example, when opcode is '00', addition is performed:
i f ( op_code = " 00" ) t hen zu : = xu+yu; … After arithmetic operations, unsigned 'zu' is converted to b it_vector and assigned to output signal 'Z'.
Z <= bi t _vect or ( zu) ; VHDL CODE: l i br a r y I EEE; use i eee. st d_l ogi c_1164. al l ; use i eee. numer i c_bi t . al l ; us e s t d. t ext i o. al l ; ent i t y Al u8 i s por t ( X, Y: i n bi t _vect or ( 7 downt o 0) ; Z: out bi t _vect or ( 7 downt o 0) ; op_code: i n bi t _vector( 1 downt o 0) ) ; - - Ent i t y def i ni t i on end ent i t y; Ar chi t ect ur e Al uBehave of Al u8 i s begi n Pr ocess( X, Y) var i abl e xu, yu, zu: unsi gned( 7 downt o 0) ; - - Unsi gned var i abl es def i ni t i on var i abl e yn: nat ur al ; begi n xu : = unsi gned( X) ; yu : = unsi gned( Y) ; i f ( op_code = "00") t hen - - Addi t i on zu : = xu+yu; el si f ( op_code = "01") t hen - - Subt r act i on zu : = xu- yu; el si f ( op_code = "10") t hen –Logi cal Ri ght Shi f t yn: =t o_i nt eger ( yu) ; zu: =SHI FT_RI GHT( xu, yn) ; el si f ( op_code = "11") t hen - - Logi cal Lef t Shi f t yn: =t o_i nt eger ( yu) ; zu: =SHI FT_LEFT( xu, yn) ; end i f ; Z <= bi t _vect or( zu) ; - - Unsi gned t o Bi t Vect or assi gnment end pr ocess; end Al uBehave;
VHDL ORGANIZATION OF TESTBENCH Entity and Architecture: An entity for the testbench is defined. The Architecture specifies the signals of the testbench and defines the DUT component.
ent i t y Test ALU i s end ent i t y; ar chi t ect ur e Behave of Test ALU i s si gnal x, y, z: bi t _vect or ( 7 downt o 0) : =" 00000000" ; si gnal op_code: bi t _vect or ( 1 downt o 0) : = " 00" ; component ALU8 por t ( X, Y: i n bi t _vect or ( 7 downt o 0) ; Z: out bi t _vect or ( 7 downt o 0) ; op_code: i n bi t _vect or ( 1 downt o 0) ) ; end component ; Process:We define the required variables in order to read from the data file and to display output. We used the text.stdio library to read from the data file:
f i l e_open( f i l e_poi nt er , "dat a. t xt ", READ_MODE) ; whi l e not endf i l e( f i l e_ poi nt er ) l oop
r eadl i ne ( f i l e_ poi nt er , l i ne_ num) ; READ ( l i ne_num, op_code_f i l e) ; READ ( l i ne_num, x_f i l e) ; READ ( l i ne_num, y_f i l e) ; READ ( l i ne_num, z_f i l e) ; Thus x_file,y_file,z_file and op_code_file now stores the values of x, y, z and op_code according to the data file generated earlier. We assert the original output z against the z_file obtained from test data file:
as s er t ( z =z _ f i l e) r epor t "Er r or i n out put " sever i t y er r or ; We also set counters to count the number of errors in each operation, and our testbench displays the number of success and failure for each operation, and also the total errors.
VHDL CODE FOR TESTBENCH: l i br a r y I EEE; use I EEE. numer i c_bi t . al l ; us e s t d. t ext i o. al l ; ent i t y Test ALU i s end ent i t y; ar chi t ect ur e Behave of Test ALU i s si gnal x, y, z: bi t _vect or ( 7 downt o 0) : ="00000000"; - - Si gnal def i ni t i on si gnal op_code: bi t _vect or ( 1 downt o 0) : = "00";
- - OpCode def i ni t i on
component ALU8 por t ( X, Y: i n bi t _vect or ( 7 downt o 0) ; Z: out bi t _vect or ( 7 downt o 0) ; op_code: i n bi t _vect or( 1 downt o 0) ) ; - - Component def i ni t i on end component ; begi n pr ocess f i l e f i l e_ poi nt er : t ext ; - - Fi l e Poi nt er var i abl e l _num: l i ne;
- - Li ne number
var i abl e count add, count sub, count sr , count sl : i nt eger : =0; - - Er r or Count er def i ni t i on var i abl e x_ f i l e, y_ f i l e, z _ f i l e: bi t _ vect or ( 7 downt o 0) ; s t or e i nput f r om f i l e
- - Var i abl es t o
var i abl e xs , ys , z s: s t r i ng( 1 t o 8) ; St r i ngs t o di spl ay out put
--
var i abl e op_code_f i l e: bi t _vect or ( 1 downt o 0) ; var i abl e ops: st r i ng( 1 t o 2) ; f unct i on I mage( I n_I mage: Bi t _vect or ) r et ur n St r i ng i s conver t bi t _vector t o st r i ng
- - f unt i on t o
var i abl e S: l i ne; var i abl e Y: st r i ng( 1 t o I n_i mage' l engt h) : = ( ot her s=> ' ' ) ; begi n st d. TextI O. WRI TE( S, i n_i mage) ; Y( S. al l ' r ange) : = S. al l ; Deal l ocat e( S) ;
r et ur n Y; end I mage; begi n f i l e_open( f i l e_poi nt er , "dat a. t xt ", READ_MODE) ; whi l e not endf i l e( f i l e_poi nt er ) l oop end of f i l e i s r eached
r eadl i ne ( f i l e_poi nt er , l i ne_num) ; READ ( l i ne_num, op_code_f i l e) ; st or ed i nt o var i abl es
- - Open f i l e command - - Loop r unni ng unt i l
- - Readi ng l i ne by l i ne - - I nput f r om f i l e i s
READ ( l i ne_num, x_f i l e) ; READ ( l i ne_num, y_f i l e) ; READ ( l i ne_num, z_f i l e) ; ops : = I mage( op_code_f i l e) ; f r om bi t _ vec t or s xs
- - St r i ngs ar e cr eat ed
: = I mage( x_f i l e) ;
ys : = I mage( y_f i l e) ; zs : = I mage( z_f i l e) ; op_code<=op_code_f i l e;
- - I nput s are assi gned
X<=x_f i l e; Y<=y_f i l e;
wai t f or 10 ns; asser t ( z=z_f i l e) condi t i on
- - Wai t i ng f or out put - - Asser t i on of out put
r epor t "Er r or i n out put " sever i t y er r or ; i f ( not ( z =z _ f i l e) ) t hen mi smat ches
- - Chec k i f out put
i f ( op_code_f i l e="00") t hen speci f i c er r or out put
- - Check opcode f or
r epor t "Oper at i on: Addi t i on. I nput : X: " & xs & " Y: " & ys & " Expect ed: " & zs & " Produced: " & I mage( z) ; - - Er r or out put count add: =count add+1;
- - I ncr ement Count er
end i f ; el si f ( op_code_f i l e="01") t hen
r epor t " Oper at i on: Subt r act i on. I nput : X: " & xs & " Y: " & ys & " Expect ed: " & zs & " Pr oduced: " & I mage( z) ; count sub: =count sub+1;
end i f ; el si f ( op_code_f i l e="10") t hen
r epor t "Oper at i on: Shi f t r i ght . I nput : X: " & xs & " Y: " & ys & " Expect ed: " & zs & " Pr oduced: " & I mage( z) ; count sr : =count sr +1;
end i f ; el si f ( op_code_f i l e="11") t hen
r epor t "Oper at i on: Shi f t Lef t . I nput : X: " & xs & " Y: " & ys & " Expect ed: " & zs & " Pr oduced: " & I mage( z) ; count sl : =count sl +1;
end i f ; end i f ; end l oop; f i l e_cl ose( f i l e_poi nt er ) ;
- - Fi l e cl ose command
i f ( count add>0 or count sub>0 or count sr >0 or count sl >0) t hen - - Tot al er r or s di spl ay r eport " Number of er r ors : " & i nt eger ' i mage( count add+count sub+count sr +count sl ) ; r epor t "Addi t i on: Success: " & i nt eger ' i mage( 65536- count add) & " Fai l ur e: " & i nt eger' i mage( count add) ;
r eport " Subt r act i on Success: " & i nt eger' i mage( 65536- count sub) & " Fai l ur e: " & i nt eger ' i mage( count sub) ; r eport " Shi f t Ri ght Success: 65536 " & i nt eger' i mage( 65536- count sr ) & " Fai l ur e: " & i nt eger ' i mage( count sr ) ; r eport " Shi f t Lef t Success: 65536 " & i nt eger ' i mage( 65536- count sl ) & " Fai l ur e: " &i nt eger ' i mage( count sl ) ; el se r epor t "Test passed successf ul l y f or al l " & i nt eger ' i mage( 65536*4) & " combi nat i ons. "; end i f ; wai t ; end pr ocess; dut : ALU8 por t map( x => X, y => Y, op_code => op_code, z => Z) ;
end Behave;
- - Por t Mappi ng
OUTPUT
Addition:
Subtraction:
Logical Right Shift
Logical Left Shift
Successful test output sample:
Unsuccessful test output sample: a) Manual change in data file:
b) Z6 stuck at 1:
c) Z4 stuck at 0:
d) Addition and Subtraction opcodes interchanged:
