dell-15-3000-series-fx3mc-hsw405070133021a00dell3446-haswellbak.pdf.pdf

5

4

3

2

1

CHARGER

HPA02224RGRR-1-GP INPUTS OUTPUTS

Cedar/Janus Block Diagram

Project code:4PD00I010001 PCB P/N: 13302-1 Revision: A00

$!. #%.

44

!"#$%&'%

SYSTEM DC/DC TPS51225RUKR-GP INPUTS OUTPUTS

45

(!()*$'+*,-)*$'+*,!"#$%&'% -)*,-

D

D

(!()*,-

Intel CPU CPU

GPU VRAM(DDR3L) *4 2GB

DDR3L

78,79

DIS only

DDR3L 1333/1600MHz Channel A

DDR3L SUS

WPT-LP 4 USB 3.0 ports

VGA

High Definition Audio

DP/VGA Converter Converter (Janus (Janus only) RTD2168 RTD21 68

DP

PCIE x 1

RealTek Cedar:(10/100)RTL8106E Janus:(10/100/1000)RT Janus:( 10/100/1000)RTL8111G L8111G

4 SATA ports

2!3-)*,2

CPU 1.05V 31

PCIE x 1 HDMI

USB2.0 x 1

54

14.0"/15"/17" LCD 52 (16:9)

WLAN

USB1(USB3.0)

USB2.0 x 1

MIC_IN/GND

Right side

HDA

Realtek ALC3234

HP_R/L

OUTPUTS

1D35V_S3

1D35V_S0 5V_S0

3D3V_S5

3D3V_S0

1D05V_S0

1D05V_VGA_S0

3D3V_S0

3D3V_VGA_S0

1D35V_S3

1D35V_VGA_S0

PCB LAYER

34,35

USB2.0 x 1

36 83

INPUTS

USB2(USB2.0)

52

HDA CODEC

B

29

34,35 Left side

USB2.0 x 1

Digital Digital MIC

58

51

1!-)*,2

Switches

5V_S 5

USB2.0 x 1

Camera

(!()*,-

Left side

USB3.0 x 1

Touch Panel

C

TLV70215DBVR-GP INPUTS OUTPUTS

802.11a/b/g/n BT V4.0 combo

USB2.0 x 1

eDP

48

!"#$%&'% 1!2-)*,2

ACPI 4.0a

HDMI V1.4a (Cedar only)

RT8237CZQW-2-GP INPUTS OUTPUTS

CPU 1D5V_S0

LPC I/F

C

49

!"#$%&'% 1!(-)*,(

RJ45 Conn. 30

8 PCIE ports

55

TPS51716RUKR-GP INPUTS OUTPUTS

LAN 10/100 & 10/100/1000 co-lay

8 USB 2.0/1.1 ports

VGA Conn. (Janus only)

!"#$%&'% )""*"&/0

12

28W (UMA) (UMA) 15W (DIS)

PCIE x 4

46,47 ISL95813HRZ-GP 33 INPUTS OUTPUTS

SODIMM A

Broadwell Broad well ULT ULT

NVIDIA NVIDIA N15V-GM-S-A2 N15V-G M-S-A2 GB2-64 (23x23) 73,74,75,76,77 25W

CPU Core Power

DDR3L 1333/1600

L1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Signal

IO Board Board

USB3(USB2.0)

B

27

Combo Jack 2CH SPEAKER (2CH 2W/4ohm)

USB2.0 x 1 29

CardReader

SD Card Slot

Realtek RTS5170

LPC BUS

LPC debug debug port 65

Thermal

SMBUS

NUVOTON NCT7718W NCT7718 W 26

KBC

SATA(Gen3) x 1

NUVOTON NUVO TON NPCE285P

Fan Control Control A

ANPEC APL5606AKI APL5606AKI

FAN 26

HDD 56

SPI 24

26

A

Int. KB

PS2

Flash ROM 8MB Quad Read 25

62

Touch PAD Image sensor

I2C

SATA(Gen1) x 1

ODD 56

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

5

4

3

2

1

D

D

(Blanking) C

C

B

B

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Si

D

N

(Reserved)

b

R

A

5

4

3

2

1

SSID = CPU 1D05S_VCCST RN401 XDP_TMS XDP_TDI

1 2 3 4

D

XDP_TDO

8 7 6 5

!"

D

SRN51J-1-GP XDP_TRST# R402 XDP_TCLK R406

1 1

!"

2 51R2J-2-GP 2 51R2J-2-GP

1D05S_VCCST HSW_ULT_DDR3L

CPU1B 1

R401 62R2J-GP C

Layout Note: Impedance control:50 ohm [24,42,44,46]

TP402 [24] 2

1 TP403 1

1

H_CATERR#

H_PECI

H_PROCHOT#

[36] H_THERMTRIP_EN

2 OF 19

Remove TP401 for TP604 spacing.

DY R411

2 H_PROCHOT#_R R403 156R2J-4-GP H_CPUPWRGD

2 2

0R2J-2-GP

Layout Note: Close to CPU

[12] DDR_PG_CTRL

R405

D61 PROC_DETECT# K61 CATERR# N62 PECI

K63

C61

PROCHOT#

MISC

JTAG THERMAL

PROCPWRGD

B

XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J60 H60 H61 H62 K59 H63 K60 J61

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

XDP_PRDY# XDP_PRDY # [96] XDP_PREQ# [96] XDP_TCLK [96] XDP_TMS [96] XDP_TRST# [96] XDP_TDI XDP_ TDI [96] XDP_TDO [96] XDP_BPM[7:0]

10KR2J-3-GP AU60 SM_RCOMP0 AV60 SM_RCOMP1 AU61 SM_RCOMP2 AV15 SM_DRAMRST# AV61 SM_PG_CNTL1

J62 K62 E60 E61 E59 F63 F62

PWR

1

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST# DDR_PG_CTRL

PRDY# PREQ# PROC_TCK PROC_TMS PROC_TRST# PROC_TDI PROC_TDO

DDR3L

C

XDP_BPM[7:0] XDP_BPM[7: 0] [96]

B

HASWELL-6-GP-U R407 1

2

200R2F-L-GP

SM_RCOMP_0

R408 1

2

121R2F-GP

SM_RCOMP_1

R409 1

2

100R2F-L1-GP-U SM_RCOMP_2

71.HASWE.G0U

1D35V_S3

Layout Note: Place close to DIMM

1

R410 470R2J-2-GP 2

SM_DRAMRST#

Layout Note: Design Guideline: SM_RCOMP keep routing length less than 500 mils.

1 R404

2

DDR3_DRAMRST# DDR3_DRAM RST# [12]

0R0402-PAD

Wistron Corporation

A


D

CPU (THERMAL/MISC/PM) N

b

R

A

5

4

3

2

1

SSID = CPU

D

D

19 OF 19

HSW_ULT_DDR3L

CPU1S

#514405

[96]

CFG[19:0]

CFG[19:0] CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

AC60 AC62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

CFG16 CFG18 CFG17 CFG19

AA62 CFG16 U63 CFG18 AA61 CFG17 U62 CFG19

C

1

2

CFG_RCOMP

R601 49D9R2F-GP

1

2

V63 A5

RSVD_TP#AV63 AV63 RSVD_TP#AU63 AU63

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RESERVED

TD_IREF

1 1

TP601 TP602

RSVD_TP#C63 RSVD_TP#C62 RSVD#B43

C63 C62 B43

RSVDC63 1 RSVDC62 1 EDP_SPARE 1

TP603 TP604 TP605

RSVD_TP#A51 RSVD_TP#B51

A51 B51

RSVDA51 RSVDB51

1 1

TP606 TP607

RSVD_TP#L60

L60

RSVDL60

1

TP608

RSVD#N60

N60

RSVD#W23 W23 RSVD#Y22 Y22 AY15 PROC_OPI_RCOMP RSVD#AV62 RSVD#D58

CFG_RCOMP

VSS VSS

RSVD#A5 RSVD#P20 RSVD#R20

E1 RSVD#E1 D1 RSVD#D1 J20 RSVD#J20 H18 RSVD#H18 B12 TD_IREF

RSVDAV63 RSVDAU63

Intel Recommend PROC_OPI_COMP3 PROC_OPI_COMP

R606 1 R602 1

DY

2 49D9R2F-GP 2 49D9R2F-GP

AV62 D58

C

Layout Note:

P22 N21 P20 HVM_CLK# R20 HVM_CLK

1 1

TP619 TP620

1.Referenced "continuous" VSS plane only. 2.Avoid routing next to clock pins or noisy signals. 3.Trace width: 12~15mil 4.Isolation Spacing: 12mil 5.Max length: 500mil

R603 8K2R2F-1-GP

#514405

PCH strap pin: CFG3 1

!"

R604 1KR2J-1-GP

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY) CFG[3]

2

0 : ENABLED SET DFX ENABLED BIT

IN DEBUG INTERFACE MSR

1 : DISABLED

B

B

CFG4 1 R605 1KR2J-1-GP

DISPLAY PORT PRESENCE STRAP CFG[4]

2

A

0 : ENABLED AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT 1 : DISABLED NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU (CFG)

5

4

SSID = CPU

3

2

1

www.vinaﬁx.vn

D

D

[55] PCH_DPB_N0 [55] PCH_DPB_P0 [55] PCH_DPB_N1 [55] PCH_DPB_P1

C !4 67 )8$ "79:;<6;<

C54 C55 B58 C58 B55 A55 A57 B57

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

C51 DDI2_TXN0 C50 DDI2_TXP0 C53 DDI2_TXN1 B54 DDI2_TXP1 C49 DDI2_TXN2 B50 DDI2_TXP2 A53 DDI2_TXN3 B53 DDI2_TXP3

1 OF 19

HSW_ULT_DDR3L

CPU1A

DDI

EDP

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

C45 B46 A47 B47

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

C47 C46 A49 B49

EDP_AUXN EDP_AUXP

A45 B45

EDP_RCOMP EDP_DISP_UTIL

D20 A43

EDP_TX0_DN EDP_TX0_DP EDP_TX1_DN EDP_TX1_DP

[52] [52] [52] [52] +VCCIOA_OUT R801 24D9R2F-L-GP

EDP_AUX_DN [52] EDP_AUX_DP [52] EDP_COMP EDP_BRIGHTNESS

1

1

Design Guideline: EDP_COMP keep routing length max 100 mils. Trace Width:20 mils.

C

2

TP801

HASWELL-6-GP-U

B

A

B

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

5

4

3

2

1

SSID = CPU CPU1P

D

C

B

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49 D5 D50 D51 D53 D54 D55 D57 D59 D62 D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22 G3 G5 G6 G8 H13

HSW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS HASWELL-6-GP-U

16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 VSS VSS AH46 VSS V23 VSS_SENSE E62 VSS AH16

D

C

VSS_SENSE U 1 P 1 G 0 1 9 L R F 2 R 2 0 0 1

B

VSS_SENSE [46]

Layout Note: 1. Place close to CPU 2. VCC_SENSE/ VSS_SENSE impedance=50 ohm 3. Length match<25mil

Wistron Corporation

A


D

N

b

CPU (VSS)

R

A

5

4

3

2

1

SSID = CPU

1D35V_S3 D

D

P P P P P P G 1 G 1 G 1 G 1 G 1 G 2 2 2 2 2 2 1 X 2 X 3 X 5 6 0 0 0 0 X DY 0 X DY 0 X DY 4 0 K 0 K 0 K 0 K 0 K 0 K 5 2 1 5 2 1 5 2 1 5 2 1 5 2 1 5 2 1 V C V C 0 C V C V C V C V 0 0 0 0 0 1 1 1 1 1 1 U U U U U U 0 0 0 0 0 0 1 1 1 1 1 1 C C C C C C S S S S S S

1

P 7 G

P 8 G

P 9 G

Layout Note: As close to CPU as possible

P 0 G

1 - 1 1 - 1 1 - 1 2 1 0 X 0 X 0 X 0 X

1 1 1 M 1 M C M C M C C 2 !" C C 2 2 2 V V !" V V 3 2 3 2 3 2 3 2 D D D D 6 6 6 6 U U U U 2 2 2 2 D D D D 2 2 2 2 C C C C S S S S

Layout Note: Direct tie to CPU VccIn/Vss balls

C

C

B

B

A

A


CPU (Power CAP1)

5

4

3

2

1

!"#$ &'()" &'*+*" D

1D05V_HSIO

,)-"

+V1.05DX_MODPHY_PCH

R1101

1

,&-" 1D05V_HSIO 1D05V_HSIO

1 0R0805-PAD-1-GP-U 2

C 1 1 P 1 0 G 2 1 X K 2 2 V 0 1 U 1 C S

L1101

C 1 P 1 0 G 1 1 X K 2 V 0 1 U 1 C S

2 0R3J-0-U-GP

1

+V1.05S_AUSB3PLL C 1 1 P 1 0 G 3 DY 1 X 2 K 2 V 0 1 U 1 C S

1 2

CAP need close to pin K9 L10

CAP need close to pin B18

./-"

0R0603-PAD-1-GP-U

1 2

2

X K 5 V 0 1 U 0 1 C S

+&-"

1

*+%,-,'!%'&B

1 2

C 1 1 P 1 1 G 3 DY 1 X 2 K 2 V 0 1 U 1 C S

4 P 1 1 G 1 2 C C X K 5 V 0 1 U 0 1 C S

CAP need close to pin A20

A

2

2

0R0603-PAD-1-GP-U

1D05V_S0

1 5 C 1 P1 P 1

1

1 G1 G 6 1 1 2 DY C C -

2

X K 5 V 0 1 U 0 1 C S

X 2 K 2 V 0 1 U 1 C S

CAP need close to pin AE9

C

1 5 P

2 1 G 1 2 DY C C X 2 K 5 V 0 1 U 0 1 C S

CAP need close to pin J18

&-" +V1.05S_CORE_PCH

R1105

1

+V1.05S_AXCK_DCB

C 1 1 P 2 P 1 1 1 G 1 G 1 1 1 2 - DY C X X 2 C K K 2 5 V V 0 0 1 1 U U 1 0 1 C C S S

&'0+)" +1.05M_ASW

1 R1104

1

0 1 G 1 2 DY C C X 2 K 5 V 0 1 U 0 1 C S

0.*-"

IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL L1104 2

+V1.05S_AXCK_DCB

2 IND-2D2UH-196-GP

*+%,-,'!%'&-

1 8 P

CAP need close to pin AC9

1D05V_S0 1D05V_S0

&*.-"

L1103 1

1 G 1 2 DY C C -

CAP need close to pin AA21

C 1 1 P 6 P 1 7 P 1 0 0 0 G 1 G 1 G 5 1 1 2 2 -DY 1 - DY C C X C X X 2 C K K 2 K 2 5 5 V V V 0 0 0 1 1 1 U U U 1 0 0 1 1 C C C S S S

CAP need close to pin B11

2

0R0603-PAD-1-GP-U

1 4 P 2

2

+V1.05S_ASATA3PLL

+V3.3A_PSUS

1 R1103

C 1 1 P 0 P 1 1 0 G 1 G 9 1 2 -DY 1 C X X 2 C K K 2 5 V V 0 0 1 1 U U 1 0 1 C C S S

0R3J-0-U-GP

1D05V_S0 3D3V_S5_PCH

+V1.05S_APLLOPI

2

2

+V1.05S_APLLOPI

1 R1102

1

1

4 P 1 3 P 0 2 1 G 1 G 1 2 1 2 - DY C C C X C X K 2 K 5 5 V V 0 0 1 1 U U 0 0 1 1 C C S S

0)-"

1D05V_S0

C

D

+V1.05S_ASATA3PLL

+V1.05S_AUSB3PLL L1102

2

RTC_AUX_S5

2

C 0R0805-PAD-1-GP-U C 1 1 1 1 1 1 P 8 P 1 1 G G 7 1 1 X 2 X 2 K K 2 2 V V 0 0 1 1 U U 1 1 C C S S

1 9 P 1

1 G 1 2 DY C C -

2

X K 5 V 0 1 U 0 1 C S

CAP need close to pin AE8 J11

C1120 S

C D 1 1 U DY 1 6 V 2 2 K X 3 G P

C1121 S C D 1 1 U 1 6 V 2 2 K X 3 G P

1 2

C 1 P 1 2 G 2 1 X K 2 V 0 1 U 1 C S

B

CAP need close to pin AG10

A


CPU (Power CAP2)

5

4

3

2

1

D

C

D

C

(Blanking)

B

A

B

A


(Reserved)DDR3-SODIMM2

5

4

3

2

1

D

C

D

(Blanking)

C

B

B

Wistron Corporation

A


(Reserved)_SODIMM _SODIMM4 D

N

b

R

A

5

4

3

2

1

SSID = CPU

PCH strap pin: Port B Detected

DDPB_CTRLDATA D

DDPC_CTRLDATA

* *

Low = Disable Port B (default) High = Enable Port B Low = Disable Port C (default) High = Enable Port C

D

The internal pull-down is disabled after PLTRST# deasserts 3D3V_S0

1 2

RN1501 SRN2K2J-1-GP

HSW_ULT_DDR3L

CPU1I

9 OF 19

4 3

B8 A9 C6

[52] L_BKLT_CTRL [24] L_BKLT_EN [52] EDP_VDD_EN

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA

eDP SIDEBAND

DDPB_CTRLCLK B9 C9 DDPB_CTRLDATA D9 D11 DDPC_CTRLDATA

RN1503

1 2

DGPU_HOLD_RST# DGPU_PW R_EN

4 3

OPS

[20]

PIRQA#

SRN10KJ-5-GP

C

R1509 1

UMA

2

DGPU_PWROK 100KR2J-1-GP

[20,24,62]

TP1501 R1512 1 0R2J-2-GP 2 INT_TP# [82,83] DGPU_PWR_EN [73] DGPU_HOLD_RST# [24,82,83] DGPU_PWROK

1

PIRQB# PIRQC# PIRQD# PCI_PME#

INT_TP#_GPIO55

1 EC1501 3D3V_S0

RN1505

1 2 3 4

8 7 6 5

PIRQC# PIRQD# PIRQB#

CLK_PCIE_WLAN_REQ3#

[18,58]

DY

P G 2 1 X K 2 V 0 5 P K 1 C S

1 EC1502

U6 PIRQA#/GPIO77 P4 PIRQB#/GPIO78 N4 PIRQC#/GPIO79 N2 PIRQD#/GPIO80 AD4 PME# U7 L1 L3 R5 L4

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

DISPLAY PCIE

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

C5 B6 B5 A6

DDPB_HPD DDPC_HPD EDP_HPD

C8 A8 D6

1

TP1502

EE Note: If layout is on constraint, please reserve TP for DDPC_CTRLCLK. PCH_DPB_AUXN [55] C

PCH_DPB_AUXP [55]

CRT_PCH_HPD

[55]

EDP_HPD [52]

DY

P G 2 1 X K 2 V 0 5 P K 1 C S

HASWELL-6-GP-U

SRN10KJ-6-GP

3D3V_S0 B

B

1 R1510 10KR2J-3-GP 2

Cedar CEDAR/JANUS_ID

CEDAR/JANUS_ID

[19]

1 R1511 10KR2J-3-GP 2

A

Janus

A


PCH ( EDP/GPIO/DDI )

5

4

3

2

1

SSID = PCH

D

D

CPU1Q

TP2201 TP2204

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 1TP_DC_TEST_AY60 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 1TP_DC_TEST_B2 DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63 DC_TEST_C1_C2

AY2 AY3 AY60 AY61 AY62 B2 B3 B61 B62 B63 C1 C2

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_AY60 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2

17 OF 19

A3 A4

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 A60 DAISY_CHAIN_NCTF_A61 A61 DAISY_CHAIN_NCTF_A62 A62 AV1 DAISY_CHAIN_NCTF_AV1 AW1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 AW2 DAISY_CHAIN_NCTF_AW3 AW3 DAISY_CHAIN_NCTF_AW61 AW61 AW62 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63 AW63

C

DC_TEST_A3_B3 TP_DC_TEST_A4 TP_DC_TEST_A60 DC_TEST_A61_B61 TP_DC_TEST_A62 TP_DC_TEST_AV1 TP_DC_TEST_AW1 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_AW63

1

TP2202

1

TP2203

1 1 1

TP2205 TP2206 TP2207

1

TP2208 C

HASWELL-6-GP-U

CPU1R

AT2 AU44 AV44 D15

B

F22 H22 J21

RSVD#AT2 RSVD#AU44 RSVD#AV44 RSVD#D15 RSVD#F22 RSVD#H22 RSVD#J21

HSW_ULT_DDR3L

18 OF 19

N23 R23 T23 U10

RSVD#N23 RSVD#R23 RSVD#T23 RSVD#U10 RSVD#AL1 RSVD#AM11 RSVD#AP7 RSVD#AU10 RSVD#AU15 RSVD#AW14 RSVD#AY14

AL1 AM11 AP7 AU10 AU15 AW14 AY14

B

HASWELL-6-GP-U

Wistron Corporation

A


D

N

CPU (RSVD)

b

R

A

5

4

3

2

1

SSID = Flash.ROM ,4B NA?OH /&PLQPM R7< 4"C

3D3V_S5

3D3V_S5

1 C2501 SC10U10V5KX-2GPDY

D

2

4 3

R2501 4K7R2J-2-GP

!" 1

RN2501 SRN4K7J-8-GP

C2502 SCD1U16V2KX-3GP

2

D

.QRSTM .B9 LEK7M8 JTKLE PNRRMPDQNR U.B9 FOK8 9HA VN8MW

1 2

3D3V_S5

SPI25

1 2 3 4

[18,24] SPI_CS0#_R [18,24] SPI_SO_R [18] SPI_WP# 1

EC2502 SC4D7P50V2CN-1GP

1

2

CS# DO/IO1 WP#/IO2 GND

VCC HOLD#/IO3 CLK DI/IO0

8 7 6 5

SPI_HOLD# [18] SPI_CLK_R [18,24] SPI_SI_R [18,24] 1

W25Q64FVSSIQ-GP

!"

#,%,:F*2%G&'

2

1

EC2501 SC4D7P50V2CN-1GP 2

EC2503 !" !" SC10P50V2JN-4GP 2

C

C

3D3V_S5

SKT25 SPI_CS0#_R SPI_SO_R SPI_WP#

1 2 3 4

DY

.NO7PM 8 7 6 5

SPI_HOLD# SPI_CLK_R SPI_SI_R

SKT-G6179HT0321-001-GP

F1>!H!1>I JKLD 7MK8

!1>I JKLD 7MK8

#,%,:F*2%G&'

A

A

#,%,:*2#%&&>

A

A

A

A

Refer to "NCPE985x/ NPCE995x board design reference guide"

*,%'&&+X%&'' &#,%,:0*2%&&&'

SSID = RBATT +RTC_VCC B

AFTP2502

3D3V_AUX_S5

RTC_AUX_S5 B

1 +RTC_VCC D2501

1 RTC1

PWR GND NP1 NP2

R2502 1KR2J-1-GP 2 1

1 2 NP1 NP2

BAT-060003HA002M213ZL-GP-U1

3 RTC_PWR

2

1 BAS40C-2-GP

75.00040.07D 1

DY

C2503 SCD47U6D3V2KX-GP

2

2nd = 75.00040.C7D

AFTP2501

3rd = 75.00040.A7D

*,%#&&'2%&&'

2nd = 62.70001.061 3rd = 20.F2316.002

Q2505

G

A

1 R2504 10MR2J-L-GP 2

D

RTC_DET# [20]

Wistron Corporation

S

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

2N7002K-2-GP

+2%,3#&,%4$' ,3! 6 +2%,3#&,%&$' $78 6 +2%&#&&,%9$'

A

Title

Flash/RTC

5

4

3

2

1

D

C

D

(Blanking)

C

B

B

Wistron Corporation

A


D

N

b

Reserved

R

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

Wistron Corporation

A


D

N

(Reserved)Card Reader b

R

A

5

4

3

2

1

D

D

(Blanking) C

C

B

B

Wistron Corporation

A


D

(Reserved) N

b

R

A

5

4

3

SSID = USB USB_PN1_R

USB_PP1_R

1

I/O1

2

GND

3

I/O2

DY

TR3401

D

2

1

U3401

[16]

USB_PN1

1

[16]

USB_PP1

4

2

USB_PN1_R

3

USB_PP1_R

N o t e : Z Z . 0 9 9 0 4 . 0 7 C 0 1

USB20_VCCA

I/O4

6

VDD

5

I/O3

4

',#=>2 47<6= 1 C3406

DY

2

USB20_VCCA USB2

SCD1U16V2KX-3GP

6 1

75.09904.07C AZC099-04S-1-GP

USB_PN1_R USB_PP1_R

8

2 3 4 5

FILTER-4P-6-GP

D

7

69.10103.041 USB20_VCCA

1

AFTP6205

SKT-USB8-14-GP

USB_PN1_R USB_PP1_R

1 1

AFTP6204 AFTP6209

22.10321.E91

C

C

U3402 USB3_PRX_CTX_N0_C USB3_PRX_CTX_P0_C

TR3404 [16]

USB_PN0

4

3

USB_PN0_C

[16]

USB_PP0

1

2

USB_PP0_C

USB3_PTX_CRX_N0_C USB3_PTX_CRX_P0_C

FILTER-4P-6-GP

1 2 3 4 5

IN1 IN2 GND IN3 IN4

U3403

NC#10 NC#9 GND NC#7 NC#6

DY

10 9 8 7 6

USB3_PRX_CTX_N0_C USB3_PRX_CTX_P0_C USB3_PTX_CRX_N0_C USB3_PTX_CRX_P0_C

USB_PN0_C

USB_PP0_C

1

I/O1

2

GND

3

I/O2

DY

N o t e : Z Z . 0 9 9 0 4 . 0 7 C 0 1

I/O4

6

VDD

5

I/O3

4

USB30_VCCC

1

DY

2


TVWDF1004AD0-1-GP AZC099-04S-1-GP

69.10103.041 75.01004.073

B

',#(>2 47<61

USB30_VCCC USB_PN0_C USB_PP0_C

75.09904.07C

1 1 1

USB1 USB3_PTX_CRX_P0_C USB30_VCCC USB3_PTX_CRX_N0_C USB_PN0_C C3404 [16] USB3_PTX_CRX_P0

1

R3408

2

USB3_PTX_CRX_P0_R

2

SCD1U16V2KX-3GP

USB_PP0_C USB3_PRX_CTX_P0_C

R3410

1

USB3_PTX_CRX_P0_C

[16] USB3_PRX_CTX_P0

2

0R0402-PAD

1

USB3_PRX_CTX_P0_C

USB3_PRX_CTX_N0_C

0R0402-PAD

10 9 1 8 2 7 3 6 4 5 11

AFTP6210 AFTP6211 AFTP6212

B

12

13

1

AFTP6217

SKT-USB13-151-GP

22.10341.Q21

2 1 0 0 4 4 3 3 C C

USB3_PTX_CRX_P0_C USB3_PTX_CRX_N0_C

1 1

!"

!"

2 2

A

C3403 [16] USB3_PTX_CRX_N0

1

R3409

2

USB3_PTX_CRX_N0_R

SCD1U16V2KX-3GP

2

R3411

1 0R0402-PAD

USB3_PTX_CRX_N0_C

[16] USB3_PRX_CTX_N0

2

1 0R0402-PAD

USB3_PRX_CTX_N0_C

P G 1 N C 2 V 0 5 P 7 D 4 C S

P G 1 N C 2 V 0 5 P 7 D 4 C S

A


USB 3.0

5

4

5V_S5

3

2

1

U3502 USB30_VCCC

1

1 2 3 4

[24] USB_PWR_EN#

C3502 SC1U10V2KX-1GP 2

GND IN EN1# EN2# DY

FLG1 OUT1 OUT2 FLG2

8 7 6 5

',#(>2 47<61

USB30_VCCC USB20_VCCA USB_OC#0_1 [16,18]

R P 1 3 G -

AP2182SG-13-GP

5 1 0 1 J 2 R K 0 0 1

1

DY

74.02182.071

2

D

2

USB20_VCCA 5V_S5 U3503

5 1

C3505 SC1U10V2KX-1GP

DY

IN

4

[24] USB_PWR_EN#

EN#

Active Low

2

OUT GND OC#

1 2 3

USB_OC#0_1 [16,18]

SY6288DAAC-GP

USB20_VCCA

074.06288.009B 1 USB30_VCCC

C3503 SCD1U16V2KX-3G P

5V_S5 U3504

5 1

IN

4

[24] USB_PWR_EN#

C3510 SC1U10V2KX-1GP 2

EN#

Active Low

OUT GND OC#

1 2 3

USB_OC#0_1 [16,18]

SY6288DAAC-GP

074.06288.009B

2

7 0 5 3 C P G 3 X K 2 V 6 1 U 1 D C S

,>

C 3

1 5 0

8 P G 1 X 2 K 2 V 0 1 U 1 C S

1 C3512

1 C3513

P G 2 2 X M 5 V 3 D 6 U 2 2 C S

1

DY

P G 2 2 X M 5 V 3 D 6 U 2 2 C S

2

TC3501 SC100U6D3V6MX-GP

78.10710.52L

D

',#=>2 47<6= ,>

C3506 S C 1 U 1 0 V 2 K X -1 G P

1

1 C3514

2

P G 2 2 X M 5 V 3 D 6 U 2 2 C S

1 C3509 P G 2 2 X M 5 V 3 D 6 U 2 2 C S

1

DY

2

TC3502 SC100U6D3V6MX-GP

78.10710.52L

C

C

Layout Note: Close CON1 5V_S5

Support 2A

USB20_VCCB

U3501

2 3 1 C3501 [24] USB_PWR_EN# 2

B

P G 3 X K 2 V 6 1 U 1 D

[16] USB_OC#2_3

IN#2 IN#3

OUT#6 OUT#7 OUT#8

4

EN/EN# DY

5

FLT#

GND GND

,>

6 7 8

R P 1 3 G 5 1 0 2 J 2 R K 0 0 2 1

DY

1 9

TPS2000CDGNR-GP

74.02000.B71

C S

C 3

1 5 1 7

2 S C D 1 U 1 6 V 2 K X 3 G P

C 3

P 1 5 1 G 8 1 X K 2 2 V 0 1 U 1 C S

1 C3515 P G 2 2 X M 5 V 3 D 6 U 2 2 C S

1

',#=>2 47<6( LB& #7?
C3516 P G 2 2 X M 5 V 3 D 6 U 2 2 C S

2nd = 74.02301.079

5V_S5

Support 2A

B

USB20_VCCB

U3505

5

1

[24] USB_PWR_EN# C3504

2

A

P G 3 X K 2 V 6 1 U 1 D C S

4

IN EN#

Active Low

OUT GND OC#

1 2 3

USB_OC#2_3 [16]

SY6288DAAC-GP

074.06288.009B

A


USB Power SW

5

4

3

2

1

SSID = Reset.Suspend

Power Good 3D3V_S0

ROSA Run Power

1

D

D

R3601 1KR2J-1-GP

3D3V_AUX_S5

1

!"

2

[49] 1D35V_VTT_PWRGD

1 R3610 2 0R0402-PAD

[7,48] 1D05V_VTT_PWRGD

1 R3611 2 0R0402-PAD

2 ALL_SYS_PWRGD

[24]

PS_S3CNTRL

R3607 100KR2J-1-GP

D G

S

6 5 4

5V_S5 5V_S5

Q3601 2N7002KDW-GP

84.2N702.A3F 1 2 3 2nd = 84.2N702.E3F S G D 3rd = 75.00601.07C 4th = 84.DMN66.03F [17,24,48,49,51] C

5V_S0 U3601

DY 4

R3609

1

PM_SLP_S3#

[17,24,26] PCH_PWROK

2 3V5V_S0_ON 0R0402-PAD 3D3V_S5

VBIAS

1 2 3

IN1#1 IN1#2 EN1

6 7 5

IN2#6 IN2#7 EN2

OUT1#13 OUT1#14 CT1

13 14 12

OUT2#8 OUT2#9 CT2

8 9 10

GND GND

5V_S0 3V5V_CT1

1

3D3V_S0

2 3V5V_CT2 C S 3 C

11 15

C S 3 C

6 4 1 6 0 4 7 1 0 7

1

2

2

G5016KD1U-GP

074.05016.0093

1 0 P 5 0 V 2 2 K X 3 G P

2 0 P 5 0 V 2 K X 3 G P

C S 3 C 6 1 0 0 5 U 1 0 V 5 K X -2 G P

C S 3 C 6 1 0 0 3 U 1 0 V 5 K X -2 G P

5V_S0 Comsumption Peak current 5A

3D3V_S0

C

3D3V_S0 Comsumption Peak current 2.5A

R3608

1

1D05V_S0

DY

2

H_THERMTRIP# [20]

1KR2J-1-GP B

B

E H_THERMTRIP_EN

[4] H_THERMTRIP_EN

PLT_RST#

1

84.02222.V11

B C

R3606 [17,24,30,52,58,65,73,96]

Q3602 MMBT2222A-3-GP

1

2 4K7R2J-2-GP


2

1 R3605 2K2R2J-2-GP

2ND = 83.00016.F11

2

D3602 BAS16-6-GP

2

3rd = 83.00016.P11

3

4th = 83.00016.G11 [45]

1

2

[24,26,76]

83.00016.K11

!" R3602 P A

PURE_HW_SHUTDOWN#

1

3V_5V_EN

G L F 2 R K 0 0 2

1

2

S5_ENABLE [24]

R3603 1KR2J-1-GP

Check R3603 is 1k or 2k.

A


Power Plane Enable

5

4

3

2

1

SSID = Reset.Suspend Layout Note: Place Close SO-DIMM1 D

D

DDR_VREF_S3 1D35V_S3 1

1

R3704 0R2J-2-GP

/4512335+6781!

/01233"

2

R3706 1K8R2F-GP

!" 2

2R2F-GP 1 R3708 2

M_VREF_CA_DIMMA

+V_SM_VREF_CNT [5] 1 2

1 R3703 1K8R2F-GP


+V_VREF_PATH3 1 R3707 24D9R2F-L-GP

2 2

C

C

Layout Note: Place Close SO-DIMM1

DDR_VREF_S3

1 R3710 0R2J-2-GP

1D35V_S3

1 R3701 1K8R2F-GP

!" 1

[5] DDR_WR_VREF01

2R2F-GP R3702 2

2

1 2

M_VREF_DQ_DIMMA 1


+V_VREF_PATH1 1 B

2

R3709 1K8R2F-GP 2 B

R3711 24D9R2F-L-GP 2

A

A


S3 Reduction Circuit

5

4

3

3D3V_S5

2

1

3D3V_S5_PCH

R3801 1

2

NON DS3

D

D

0R5J-5-GP

3D3V_S5

1

C3801

2

!.$ C

[17,24] PM_SLP_SUS#

1

Obs reason: For new project, pls help to use cost down version SY6288C10CAC for instead.

!.$

S C 1 U 1 0 V 2 K X -1 G P

3D3V_S5_PCH

U3801

2 DS3_PWRCTL R3802 0R2J-2-GP

1 2 3 4

!.$

GND OUT#8 IN#2 OUT#7 IN#3 OUT#6 EN/EN# OCB

8 7 6 5

C

1

C3802

SY6288CCAC-GP

#2%&*,++%&#X (OBS)

/YO&Z[ 122S 7HS

2

!.$

S C 1 U 1 0 V 2 K X -1 G P

DS3

B

B

Wistron Corporation

A


DSW D

N

b

R

A

5

4

3

2

1

D

D

(Blanking) C

C

B

B

Wistron Corporation

A


(Reserved) 1D05_M D

N

b

R

A

(Blanking)

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4

Document Number

Reserved

Rev

5

4

3

2

1

D

C

D

(Blanking)

C

B

B

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

A

Title Size

Document Number

Reserved

Rev

A

5

4

3

2

1

SSID = PWR.Support PBAT_PRES1# PBAT_SMBDAT1 PBAT_SMBCLK1 BT+ BT+ BT+

BT+ D

EC4304

1

DY

S C D 1 U 5 0 V 3 K X G P

2

K

1

EC4303 SCD1U25V2KX-GP

2

1 1 1 1 1 1

AFTP3902 AFTP3903 AFTP3904 AFTP3905 AFTP3907 AFTP3908

D

Batt Connecter

DY PD4302 SMF18AT1G-GP A

BAT1 RN4301 4 3 2 1

[24,44] BAT_SCL [24,44] BAT_SDA [24,42,44] BAT_IN#

10 1 5 6 7 8

2 3 4 5 6 7 8 9 11

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

AFTP3901 SRN100J-4-GP

1

BAT_ALERT

C

C

EC4301 S C 1 0 P 5 0 V 2 J N -4 G P

1

DY 2

EC4302 S C 1 0 P 5 0 V 2 J N -4 G P

1

DY 2

2

EC4305 S

ALP-CON9-6-GP-U AFTP3906 1 AFTP3909 1 AFTP3910 1

C

!" 0 1 P 1 5 0 V 2 J N -4 G P

20.81925.009 2nd = 20.81928.009

Placement: Close to Batt Connector

B A T _ I N #

B

B A T _ S C L

B A T _ S D A

3

3

3

D4302 LBAV99LT1G-1-GP


75.00099.O7D

1

A

2

B


75.00099.O7D

1

2

75.00099.O7D

1

2

2nd = 75.00099.K7D

2nd = 75.00099.K7D

2nd = 75.00099.K7D

3rd = 75.00099.Q7D

3rd = 75.00099.Q7D

3rd = 75.00099.Q7D

4th = 75.00099.D7D

4th = 75.00099.D7D

4th = 75.00099.D7D

3D3V_AUX_KBC

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Si

D

N

b

BATT CONN

R

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

(Blanking) C

C

B

B

A

A


(Reserved)

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


HDMI Level Shifter/Connector

5

4

3

2

1

SSID = ESATA

D

D

C

C

(Blanking)

B

A

B

A


ESATA

5

4

3

WLAN1

6 2

3D3V_S0

D

3D3V_S0

1

TP5801

C

TP5802 R5804 1

[24] E51_TXD [24] WIFI_RF_EN 2

WLAN_ACT BT_ACT

1

E51_RX 20R2J-2-GP E51_TX

DY

3D3V_S0

DY

R5805 1

[20] BLUETOOTH_EN 5V_S0

R5801

1

2 0R0402-PAD

DY

2+5V_MINI_DEBUG 0R2J-2-GP

TP5804 TP5803

1 1

R5807 0R2J-2-GP 1 DY 2

CARD_WLAN_OUT# CARD_WPAN_OUT#

DEBUG

REFCLK+ REFCLK-

13 11

CLK_PCIE_WLAN_P3 [18] CLK_PCIE_WLAN_N3 [18]

MS_TX+/PERN0 MS_TX-/PERP0

23 25

PCIE_PRX_WLANTX_N3 [16] PCIE_PRX_WLANTX_P3 [16]

MS_RX-/PETN0 MS_RX+/PETP0

31 33

PCIE_PTX_WLANRX_N3_C [16] PCIE_PTX_WLANRX_P3_C [16]

1.5V 3.3V/MS_V3

28 48

+1.5V +1.5V

52

+3.3V/MS_V3

24

+3.3VAUX/MS_V3

USB_DUSB_D+

36 38

RESERVED#3 SMB_CLK RESERVED#5 SMB_DATA RESERVED#8 RESERVED#10 RESERVED#12 WAKE# RESERVED#14 CLKREQ# RESERVED#16 PERST# RESERVED#17 RESERVED#19 RESERVED#20 GND RESERVED#37 GND RESERVED#39/MS_V3 GND RESERVED#41/MS_V3 GND RESERVED#43 GND RESERVED#45 GND RESERVED#47 GND RESERVED#49 GND RESERVED#51 GND GND GND 42 LED_WWAN# GND 44 LED_WLAN# GND 46 LED_WPAN# GND 1 2 P P MINI_PCI 52P N N SKT-MINI52P-81-GP-U1 1 2 P P N N

30 32

3 5 8 10 12 14 16 17 19 20 37 39 41 43 45 47 49 51

USB_PN5_R USB_PP5_R

1 7 22

CLK_PCIE_WLAN_REQ3# [15,18] PLT_RST# [17,24,30,36,52,65,73,96]

4 9 15 18 21 26 27 29 34 35 40 50 53 54

C

3D3V_S0

B

1

1

C5802 2

P G 3 X K 2 V 6 1 U 1 D C S

2

1

C5803 P G 2 2 X K 5 V 0 1 U 0 1 C S

C5804

P G 3 X K 2 V 6 1 U 1 D C S WLAN_ACT

USB_PN5_R USB_PP5_R

R5802 1

2 0R0402-PAD

USB_PN5

R5803 1

2 0R0402-PAD

USB_PP5 [16]

[16]

1

DY A

D

62.10043.C81

'%'> B

1

Mini Card Connector(802.11a/b/g)

SSID = Wireless

R5806 0R2J-2-GP BT_ACT 1

2

2

Wistron Corporation

C5807 P G 3 X K 2 V 6 1 U

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size

Mini Card (WLAN)

Document Number

Rev

A

A

B

C

D

E

4

4

(Blanking) 3

3

2

2

Wistron Corporation

1


D

N

b

Reserved

R

1

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

Wistron Corporation

A


(Reserved) D

N

b

R

A

5

4

3

2

1

SSID = User.Interface

Power button SW1

D

1

[24] KBC_PWRBTN#

KBC_PWRBTN#_C

2 100R2J-2-GP

AFTP6801

1

1

4 3 2 1

S DY EC6104 C

2

5

D 1 U 2 5 V 2 K X G P

ETY-CON4-34-GP

20.K0465.004

1

AFTP6802

2nd = 20.K0422.004 3RD = 20.K0382.004

Battery LED1 (AMBER_LED) Low actived from KBC GPIO

C

D

6

R6102

C

5V_S5 Q6104 2 R

[24] CHG_AMBER_LED#

1 R6104

2CHG_AMBER_LED_R#

E

B 1 R

C

0R0402-PAD

R6103 AMBER_LED_BAT

2

1

BAT_AMBER

499R2F-2-GP

DDTA144VCA-7-F-GP

AMBER

1

EC6105 DY 2 SC220P50V2KX-3GP

84.00144.N11 B

BAT_AMBER

[63]

BAT_WHITE

[63]

B

5V_S5 Q6103 2 R

[24] BATT_WHITE_LED#

1 R6105

2BATT_WHITE_LED_R# B 1 R

0R0402-PAD

E C

DDTA144VCA-7-F-GP

84.00144.N11

R6101 WHITE_LED_BAT

2

1

BAT_WHITE

WHITE

330R2J-3-GP 1

EC6103 DY 2 SC220P50V2KX-3GP

A

Battery LED2 (WHITE_LED) Low actived from KBC GPIO

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Si

D

N

b

LED Bard/Power Button

R

A

5

4

3

2

1

D

D

CON1 USB20_VCCB 17

TR6301

1

USB_PN2_IOBD1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

C

3

69.10103.041

3D3V_S0

USB_PP2_IOBD1

2

4

USB_PN2 [16]

1

USB_PP2 [16]

FILTER-4P-6-GP USB_PN2_IOBD1 USB_PP2_IOBD1

',#=>2 47<6(

USB_PN7_IOBD1 USB_PP7_IOBD1

"?
[61] [61]

C

K0!

18 PTWO-CON16-2-GP TR6302

20.K0382.016

USB_PN7_IOBD1

3

69.10103.041

USB_PP7_IOBD1

2

4

USB_PN7 [16]

1

USB_PP7 [16]

FILTER-4P-6-GP B

The maximum range of the PMOS output current in RTS5170 (Card Reader IC) is 400mA

B

USB20_VCCB

1 TC6301 SC100U6D3V6MX-GP 78.10710.52L 2

DY

Wistron Corporation

A


IO Board Connector D

N

b

R

A

5

4

3

2

1

SSID = User.Interface 3D3V_S5 D

D

2

R6401 100KR2J-1-GP

!" 1

LID_CLOSE#

[24] LID_CLOSE# 1

DY

2

C

C6401 SCD047U25V2KX-GP

3D3V_S5 P G 3 X K C6402 2 V 1 6 1 U 1 D 2 C S

LIDSW1 1 2 3

VSS VDD OUT C

S-5712ACDL1-M3T1U-GP

74.05712.0BB

B

B

Wistron Corporation

A


D

N

b

Hall Sensor

R

A

5

4

3

2

1

SSID = DEBUG PORT

D

D

!;@_G "799;I67<

Layout Note: Place near trace separated point 3D3V_S0 [18,24] LPC_AD[3..0]

LPC_AD[3..0] LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

[18,24] LPC_FRAME# [17,24,30,36,52,58,73,96] PLT_RST#

R6501 R6502

1 2 3 4

RN6501 SRN0J-7-GP-U 8 7 DEBUG6 5

1 DEBUG 1 DEBUG

2 2 0R2J-2-GP 0R2J-2-GP

DB1 11 1

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_FRAME#_DEBUG PLT_RST#_DEBUG

2 3 4 5 6 7 8 9 10 12

[18] CLK_PCI_LPC

C

C

PAD-10P-177042-GP

ZZ.00PAD.Y41 20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41 DB1 Optional: New one smaller LPC connector is 20.F1180.010.

B

B

Wistron Corporation

A


D

N

b

Dubu g connector

R

A

5

4

3

2

1

D

D

(Blanking) C

C

B

B

Wistron Corporation

A


D

N

b

Reserved

R

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


RESERVED

5

4

3

2

1

D

D

C

C

B

B

A

A


USB3.0 PORT

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

B

B

A

A


GPU-VRAM5,6 (3/4)

5

4

3

2

1

D

D

C

C

B

B

A

A


GPU-VRAM7,8 (4/4)

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

C

D

(Blanking)

C

B

B

Wistron Corporation

A


(Reserved)Finger Print D

N

b

R

A

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Free Fall Sensor

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

B

B

A

A


Ex press Card

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A


LVDS_Switch

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A


CRT_Switch

5

4

3

2

1

Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM D

D

DC Battery

BT+

3

SWITCH

PM_SLP_S4#

Page44

Page43

-7

-3 AC Adapter in Page42

+DC_IN

DCBATOUT DCBATOUT

SWITCH Page44

4a VIN

AD+ EN1

-5 Charger

DCBATOUT

BQ24715 ACOK

3a

S5_ENABLE

4

EN2

3D3V_S5

PM_SLP_S3#

TPS51225CRUKR

VIN

DC/DC

SW

TPS51367

PGOOD

EN

RUNPWROK

PGOOD

1D35V_S3

RUNPWROK

Page48

Page48

-2

(3.3V/5V)

Page44

SW

TPS51367 EN

VIN

1D05V_S0

4b 4b

5V_S5

1D35V_S3

Page41

3D3V_AUX_S5

-3

PSL_IN1#

GPIO34

VR_EN

KBC NPCE985

-1

PSL_IN2# GPIO8

PM_SLP_S3#

GPIO43 GPIO20

GPIO01

DPWROK

RSMRST#_KBC

VIDSOUT

Haswell ULT CPU with Lynx Point PCH

RSMRST#

PM_PWRBTN#

PWRBTN#

2

GPIO80

6

5

Page36

H_VR_ENABLE

Level Shifter

RUNPWROK

H_VCCST_PWRGD

Page7 H_CPU_SVIDDAT

3D3V_S5

12 APWROK

10

SWITCH

11

Page24

SLP_S3# de-assert, delay 20ms; PCH_PWROK assert.

3D3V_S0

RUNPWROK

7 DDR_PG_CTL

PM_SLP_S4#

C

4b

S5_ENABLE

1 KBC_PWRBTN#

Page36

Page46

3D3V_AUX_KBC AC_IN

SWITCH

0D675V_S0

TPS51206

Page24

-6

5V_S0

RUNPWROK

4 DDR_VTT_PG_CTRL

SWITCH

-4

C

PLTRST#

S0_PWR_GOOD PCH_PWROK

SLP_S3# de-assert, delay 200ms; S0_PWR_GOOD assert.

VCCST_PWRGD

SYS_PWROK

VR_READY

PCI_PLTRST#

4a VIN

4 PM_SLP_S3#

EN

VOUT

TPS51312

PGOOD

RUNPWROK

Page51

5 PCH_PWROK

1D5V_S0

4b

H_VCCST_PWRGD

B

B

SYS_PWROK be asserted after S0_PWR_GOOD assertion and CPU core VR power good assertion.

11 H_CPU_SVIDDAT

H_VR_ENABLE

7

S0_PWR_GOOD VDIO

TPS51622 VR_ON

9 IMVP_PWRGD

PGOOD

Page46

PWR_VCC_PWM1

DCBATOUT

8

CSD97374 VSW

VCC_CORE

Page47

A

A

1

2

3a

4

4a

4b

5

6

7

8

9

10

11

12


Power Se quence Diagram

5

4

3

2

1

DCBATOUT

Adapter

RT8237

TPS51216RUKR

ISL95813

AP3211

D

D

Charger 1D05V_S0

BQ24717

1D35V_S3

+PBATT

Battery

TPS22966

1D05V_VGA_S0

TLV70215

1D5V_S0

0D675V_S0

VCC_CORE

VGA_CORE

SIRA06DP

1D35V_VGA_S0

C

C

TPS51125ARGER

15V_S5

3D3V_AUX_S5

5V_AUX_S5

5V_S5

AP2182SG

USB30_VCCA USB30_VCCB

AP2301M8G

+5V_USB1

3D3V_S5

TPS22966

TPS22966

TLV70215 3D3V_S0

5V_S0

1D5V_S0

AO3403

3D3V_LAN_S5

B

B

SY6288

ODD_PWR_5V

RT9724

Power Shape LCDVDD

A

TPS22966

3D3V_VGA_S0

Regulator

LDO

Switch

A


Power Block Dia gram

A

B

C

PCH SMBus Block Diagram 3D3V_S5_PCH

D

E

KBC SMBus Block Diagram

3D3V_S0

TP_VDD ‧

‧

3D3V_S0

‧

SRN2K2J-1-GP

SRN10KJ-5-GP ‧

1

SMBCLK

SMB_CLK

SMBDATA

SMB_DATA

DIMM 1

PCH_SMBCLK

‧

‧

‧

SRN10KJ-5-GP

TouchPad Conn.

SCL

‧

PCH_SMBDATA

SDA

SMBus Address:0xA0/0xA1

PSDAT1

TPDATA

PSCLK1

TPCLK

‧

‧

TPDATA

TPDATA

TPCLK

TPCLK

1

2N7002SPT

3D3V_AUX_KBC

TPAD PCH_SMBCLK

‧

SCL

PCH_SMBDATA

3D3V_S5_PCH

SDA SRN4K7J-8-GP

SMBus Address:0x58/0x59 ‧

SRN33J-7-GP GPIO17/SCL1

PTN3355

SRN2K2J-1-GP PCH_SMBCLK

GPIO22/SDA1

VDDA33_DP

PCH_SMBDATA

TMS

SML0CLK SML0_CLK

BAT_SCL

PBAT_SMBCLK1

BAT_SDA

PBAT_SMBDAT1

‧ ‧

‧

‧

CLK_SMB DAT_SMB

SMBus address:16

(Janus Only)

HPA02224RGRR

SMBus Address:0xC0H/0x40H

SML0DATA SML0_DATA

Battery Conn.

KBC

SCL SDA

NPCE285P

SMBus address:12

2

2

GPIO73/SCL2 GPIO74/SDA2

PCH

3D3V_S0

SMBus Address: 0x94/0x95/0x96/0x97

3D3V_S5_PCH ‧

3D3V_S0

SRN2K2J-8-GP

SRN2K2J-8-GP

‧

SML1CLK SML1DATA

SML1_CLK

‧

‧

‧

‧

‧

SML1_DATA

THM_SML1_CLK

SCL

THM_SML1_DATA SDL

‧

SMBus Address:0x82/0x83

Thermal NCT7718W

SMBus Address:0x98/0x99 2N7002SPT

3D3V_VGA_S0

‧

SRN4K7J-8-GP

3D3V_VGA_S0

dGPU

‧

3

3

SMBC_Therm_NV SMBD_Therm_NV

‧

‧

I2CS_SCL I2CS_SDA

SMBus Address:0x9E/0x9F

3D3V_S0

5V_S0 0R2J-2-GP

‧

DY

‧

3D3V_S0 SRN2K2J-1-GP

SRN2K2J-1-GP ‧

GPIO47/SCL4A

PROCHOT_EC

GPIO53/SDA4A

LCD_TST_EN

‧

‧

LCD_TST_EN

H_PROCHOT_EC ‧

0R2J-2-GP DDPB_CTRLCLK DDPB_CTRLDATA

PCH_HDMI_CLK

DDC_CLK_HDMI

‧

‧

PCH_HDMI_DATA

‧‧

DDC_DATA_HDMI

‧

‧

HDMI CONN

LCD_TST

2N7002DW-1-GP

4

4


SMBUS Block Dia

5

4

3

2

1

CLK Block Diagram Intel CPU Haswell/Broadwell ULT

D M_A_DIMA_CLK_DDR0

CK0

DDR3L

DIMM1

CK0#

M_A_DIMA_CLK_DDR#0

M_A_DIMA_CLK_DDR1

CK1 CK1#

M_A_DIMA_CLK_DDR#1

D

SA_CLK0 SA_CLK#0

SA_CLK1 SA_CLK#1

CLK_PCIE_WLAN_P3

CLKOUT_PCIE_P2 CLKOUT_PCIE_N2

C

VRAM1

CK#

FBA_CLK0P

FBA_CLK0P

VRAM2

CK CK#

FBA_CLK0N

‧ ‧

FBA_CLK0

PEX_REFCLK#

PEX_REFCLK

REFCLK_N

CLK_PCIE_VGA

VRAM3

CK#

FBA_CLK1P XTAL_IN

FBA_CLK1N

X3001 25MHz

VRAM4

CK#

FBA_CLK1N ‧ ‧

CKXTAL2

27MHZ_IN

X7601 27MHz

FBA_CLK1P CK

CKXTAL1

CLKOUT_PCIE_P4 LANXOUT

CK

C

CLKOUT_PCIE_N4

FBA_CLK0#

‧ ‧

REFCLK_P

LANXIN CLK_PCIE_VGA#

WLAN NGFF

LAN RTL8106E/RTL8111G

CLK_PCIE_LAN_N4

CLKOUT_PCIE_N3

VGA N15V-GM-S-A2 GB2-64 (23x23)

FBA_CLK0N

REFCLKN0

CLK_PCIE_LAN_P4

CLKOUT_PCIE_P3 CK

REFCLKP0

CLK_PCIE_WLAN_N3

‧ ‧

FBA_CLK1 FBA_CLK1#

XTAL_OUT

27MHZ_OUT

HDA_BCLK/I2S0_SCLK

RN2102

HDA_BITCLK

HDA_CODEC_BITCLK

BITCLK

Audio Realtek ALC3223

SRN33J-5-GP-U

B

RTC_X1

B

RTCX1 R5815

X1901 32.768KHz

0R2J-2-GP

RTC_X2

NGFF

SUSCLK_NGFF SUS_CLK

RTCX2

KBC NPCE285P

XTAL24_IN XTAL24_IN SUSCLK/GPIO62

X1801 24MHz

CLKOUT_LPC_1 XTAL24_OUT XTAL24_OUT

CLKOUT_LPC_0

SUS_CLK_PCH R1710 SUS_CLK 0R2J-2-GP R1805

CLK_PCI_KBC_R

R2441 ‧ ‧

CLK_PCI_LPC_R

R1804

CLK_PCI_LPC

CLKOUT_ITPXDP#

GPIO0/EXTCLK/F_SDIO3 LCLK/GPIOF5

0R2J-2-GP

0R2J-2-GP

CLKOUT_ITPXDP_P

SUS_CLK_KBC

0R2J-2-GP

CLK_PCI_KBC

LPC

Test Point

A

A


A

B

C

D

Thermal Block Diagram

E

Audio Block Diagram

1

1

3D3V_S5_PCH

PCH

3D3V_S0

PAGE28

D+

NCT7718_DXP SC2200P50V2KX-2GP

SML1DATA/GPIO74 SML1CLK/GPIO75

SML1_DATA ‧

SML1_CLK

‧ ‧

‧ ‧

2N7002

‧

Thermal NCT7718

THM_SML1_DATA

SDA

THM_SML1_CLK

SCL

‧

‧

D-

SPKR_L+ SPKR_LSPKR_RSPKR_R+

MMBT3904-3-GP

Place near CPU PWM CORE

Codec ALC3223

MMBT3904-3-GP

PAGE20

K L C _ 1 L M S

T_CRIT#

GPIO4 GPIO56

1 _ C A D _ 1 N A F

1 H C A T _ N A F

3

PURE_HW_SHUTDOWN#

D

EN

3V/5V

COMBO

SLEEVE

PCH_PWROK

RING2

Put under CPU(T8 HW shutdown)

2

PAGE86

GPIO73

GPIO94

2N7002

G

GPIO74

KBC NPCE285P

THERM_SYS_SHDN#

S ‧

PAGE27

AUD_HP1_JACK_R

3D3V_S0

2

HP MIC

AUD_HP1_JACK_L

T8 A T A D _ 1 L M S

SPEAKER

NCT7718_DXN

VGA

SMBD_THERM_NV

I2CS_SCL

SMBC_THERM_NV

I2CS_SDA

2N7002

GPIO0/DMIC_DATA GPIO1/DMIC_CLK

DMIC_DATA_R

DMIC_CLK_R

R2714 0R2J-2-GP R2716

DMIC_DATA

Digital MIC

DMIC_CLK

0R2J-2-GP

N15V-GM-S-A2 GB2-64 (23x23)

3

TACH

FAN 1 C C V _ N A F

5V

VIN

VSET

VIN

VOUT

FAN CONTROL

APL5606AKI PAGE28

4

4


Thermal/Audio Block Dia

5

4

3

2

1

Change notes DATE

VERSON

DATE

Page

Modify List

OWNER

D

D

C

C

B

B

A

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Si

D

N

b

Chan ge History

R

dell-15-3000-series-fx3mc-hsw405070133021a00dell3446-haswellbak.pdf.pdf

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