Decade Counter

Sample design

--Counter VHDL

library IEEE;

--library definition

use IEEE.std_logic_1164.a IEEE.std_logic_1164.all; ll; use IEEE.std_logic_unsigned.al IEEE .std_logic_unsigned.all; l;

entity Counter is

--entity definition

port ( clk:in std_logic; reset: in std_logic; q: out std_logic_vector(3 downto 0) ); end Counter;

architecture Counter of Counter is

-- Architecture definition

begin process(clk,reset)

-- Process definition

variable qtemp: std_logic_vector(3 std_logic_vector(3 downto 0); -- temporary variable for output output q[3..0] begin if reset='1' then qtemp:="0000";

-- Reset asychroniously

else if clk'event and clk='1' then if qtemp<9 then

-- Counting state

qtemp:=qtemp+1;

-- Counter increase

else qtemp:="0000";

-- Return the zero state

end if; end if; q<=qtemp;

-- Output

end if; end process; end Counter;

-- End Process -- End Architecture