PROMESA is a model for undermining democracy and pushing austerity elsewhere in the U.S.
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Piano and vocals to Broken Vessels by Hillsong United
Piano and vocals to Broken Vessels by Hillsong United
A guide to using the dubug rom, if you downloaded the rom, I highly suggest downloading this to help you on your way.
Arquitectura y Tecnología de los Computadores. Departamento de Automática. Universidad de Alcalá. MANUAL BREVE DE “DEBUG” Se trata de una utilidad muy poco amigable, sin menús y -sólo en ve…Descripción completa
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Ancalia - The Broken TowersFull description
Ancalia - The Broken Towers
AGENDA A GENDA GUI interface Saved circuit states View test patterns Simulate and justify values SimVision Debugging design violations
Scan chains
Contention
Inactive logic
Enc ncou ount nte er Te Test Usi sing ng th the e Sch che ematic Vie iew w fo forr Debu bug g
Enc ncou ount nte er Te Test Usi sing ng th the e Sch che ematic Vie iew w fo forr Debu bug g
Debuggi bug ging ng scan chain chains s There is more than one method for scan chain debug
This is just one possible method
Encounter Test traces scan chains both forwards from scan-in and backwards from scan-out. A broken scan chain normally produces two error messages messages
WARNING (TSV-384): Controllable scan chain beginning at {objectName} is not a observable scan chain.
WARNING (TSV-385): Observable scan chain ending at {objectName} is not a controllable scan chain.
Normally Normally it is easier easier to debug scan scan chains working working backwards backwards,, so use the TSV-385 messages.
Debugging scan chains There is more than one possible cause of an error
Design error in the netlist.
Error in the pin definitions in the “assignfile”
Error in the initialisation sequence in the “seqdef” file
Error in the cell library models
This is a set up guidelines based on edge-triggered mux-scan, different approaches may be used for LSSD. You can do debug at the primitive level or at the library cell level. (explained on next slide)
This presentation shows the use of the library level.
Circuit Tracing GUI Tracing The way the blocks are displayed when tracing forward and backward in the Circuit Display can be customized In the Circuit Display -> Options > Circuit Tracing On the bottom, tracing at the primitive, cell, or macro level can be set.
“Apply” just changes for current session
“Apply and Save” changes for all future sessions
First steps Invoke Encounter Test in the gui mode
et –gui
Open the design
File > Open
Select the “Tasks” tab and select the “verify_test_structures” task Select the “messages” tab Click on the “View Messages” icon Select “TSV-385” Messages and click “View” Select the specific message and click “Analyze”
Verify Test Structures Message Summary
Verify Test Structures Specific Message List
Instance will be displayed The instance displayed is normally the last break in the scan chain.
correct
instance before the
If the instance is top-level pin then no flops were correctly traced
If it is a flop, then this is the last working flop.
You can “implode” the instance to move up the hierarchy to the library level
Left click to select the block
Right click to open “Block Actions” menu
Click “Implode”
This may need to be done more than once until the library level cell is found. The instance cell type and instance name are shown in the right hand “Information Window”
Typical values for a correct flop The picture on the next slide shows typical values for a correctly functioning scan flops
The clock pin will show a defined off-state
The asynchronous set or reset pin will show a valid off-state
1 in this case as the reset is active low, 0 or X would be an error
The scan-enable pin is active
(0 or 1 is acceptable, X is an error)
1 in this case
The data-in and scan-in pins are undefined
This is normal during scan chain trace and is not an error
Possible errors on the initial instance The first step is to check the instance displayed.
Is the scan-enable pin at the correct logic state?
Does the scan-in pin show an “X” state? (This is correct)
If it is “x” (lower case) then the input is undriven
If it is a “0”, “1”, “+” or “-” then the scan-in pin has been forced to a fixed logic value.
The next two slides show possible errors
scan-enable at incorrect state
Scan-in at “ x” state (lower case), unconnected
Finding the faulty instance As described earlier the analysis of the TSV message will show the last “correct” instance. You need to trace backwards from the scan-in pin to find the cause of the fault.
Left click to select the scan-in pin
Right click to open “Pin Actions” menu
Click “Trace Backward”
(alternatively use keyboard “b” as shortcut)
If it is not possible to trace backward if there is no connection
You may need to trace back through levels of buffering
The GUI can be setup to trace through multiple blocks at 1 time, this is explained on the next slide.
Circuit Tracing GUI Tracing The way the blocks are displayed when tracing forward and backward in the Circuit Display can be customized In the Circuit Display -> Options > Circuit Tracing The tools is setup to only trace 1 level of hierarchy and stop at latches/flip flops. These tracing options can be modified in this window. The upper portion of the window sets how many levels to trace through and when to stop tracing.
Default is to trace only 1 block and stop at any flop/latches
Analysis of the “ faulty instance” “Implode” to the library level Place the cursor over each of the input pins and check them:
Clock pins
Does it have a defined “off-state” 0 or 1, an “X” indicates a corrupt clock
Is the clock defined as “EC” (possibly SC as well)
Asynchronous
set/reset pin
EITHER - Is the pin tied to the correct inactive level?
“+” or “1” for active low
“-” or “0” for active high
OR
Is it defined as an “SC” type clock with the correct “off-state”
The following slides show “correct” values on pins.
Correct scan clock The clock has a defined off-state “0” (“1” is OK for a negative edge triggered clock) The clock is an “EC” type so will be pulsed during shift
Correct asynchronous reset The clock has a defined off-state “1” which is correct for an active low reset. The clock is an “SC” (not “EC”) type so it will not be pulsed during shift. Alternatively the clock may be set at a fixed logic value.
Correct scan-enable The scan-enable has a defined logic “1”.
Detailed Graphical Analysis of Broken Scan Chains
The following slides show some examples of possible errors and how they would appear in the GUI.
No scan clock
No reset clock
Invalid assign file flag
Wrong clock polarity
No shift clock on the flop The logic state of the CK pin is “X”, no clock is defined
Uncontrolled reset The reset pin is at a logic “X” state so the flop will be corrupted.
Incorrect clock type
The clock is of type “SC” (not “EC”) so will not be clocked during the shift sequence.
Wrong reset clock polarity The asynchronous reset clock has an “off-state” of “0” so the flop will be reset when the clocks are held “off” during shift.
Incorrect clock type on asynchronous reset The reset has an “EC” type clock so will be pulsed during shift. This will corrupt the scan chain operation. Resets and sets should be “SC”.
Checking the detailed shift operation If the previous checks have not identified a problem look at the simulation of the shift sequence. Follow menus
View > Test Data > Sequence Definition Data
Expand “click blue boxes” to find “Define Sequence Scan_Sequence”
View > Circuit Values
A “Simulating sequences” window will appear
The schematic will be updated to show the shift sequence
Viewing the shift sequences
Correct scan clock A clean pulse “p” is seen on the clock pin
Corrupt scan clock The clock shows a “*” state, this indicates an unknown pulse state.
