Dct 6000 09 Qpsk Manual

EDU-LABS DIDACTIC QPSK Modulator Experiment Module

Chapter 17 : DCT17

User Manual

Digital and Analog Communication Systems

17-1: Curriculum Objectives

1. To understand the operation theory of the bit splitter. 2. To understand the operation theory of the balanced modulator. 3. To design the balanced modulator by using MC1496. 4. To understand the methods of measuring and adjusting the balanced modulator circuit.

17-2: Curriculum Theory

In the communication systems, besides PSK modulation that we have mentioned before, there is another type of modulation, which we called quadrature phase shift keying (QPSK) modulation. Both PSK and QPSK modulations use the variation of phase of the carrier to modulate the data signal. However, the main difference between PSK and QPSK modulations is PSK modulation uses binary system, which means the phase difference of the carrier signal is 180° 180° that represents “1” or “0” for the data signal. If the data signal is not binary system, but M-ary level, then we can use QPSK,

17－2


17-1: Curriculum Objectives

1. To understand the operation theory of the bit splitter. 2. To understand the operation theory of the balanced modulator. 3. To design the balanced modulator by using MC1496. 4. To understand the methods of measuring and adjusting the balanced modulator circuit.

17-2: Curriculum Theory

In the communication systems, besides PSK modulation that we have mentioned before, there is another type of modulation, which we called quadrature phase shift keying (QPSK) modulation. Both PSK and QPSK modulations use the variation of phase of the carrier to modulate the data signal. However, the main difference between PSK and QPSK modulations is PSK modulation uses binary system, which means the phase difference of the carrier signal is 180° 180° that represents “1” or “0” for the data signal. If the data signal is not binary system, but M-ary level, then we can use QPSK,

17－2

Chapter 17

QPSK Modulator

8PSK and so on to transmit the data signal more effectively. These types of modulations just use the phase shift within 360 360°° to represent the M-ary levels. Therefore, N-bits of data signal can be transmitted at the same time. This will reduce the transmitted bandwidth and a high transmission rate can be achieved.

QPSK modulated signal is a system with M = 4 levels, which means 2 bits data will be transmitted at the same time. From the equation (15-1) in chapter 15, we know that the QPSK modulated signal can be expressed as

x QPSK ( t ) = A cos [ ωc t + ( 2m − 1)

π 4

] ; m = 1, 2, 3, 4

(17-1)

From the above equation, we know that the phase of carrier of the QPSK modulated signal is distributed to π / 4 , 3π / 4 , 5π / 4 and 7 π / 4 . Each phase represents 2 bits data signal as shown in table 17-1. The signal constellation diagram is shown in figure 17-1.

Expanding equation (17-1), we get

x QPSK ( t )

=

−

A cos [ ( 2 m

−

A sin [ ( 2 m

−

1) 1)

π

4 π

4

] cos ( ω c t ) ] sin( ω c t )

(17-2)

17－3


Table 17-1

The signal constellation characteristics characteristics of quadrature phase shift keying

Phases of QPSK

2 bits inputs

π/4

11

3π/4

10

5π/4

00

7π/4

01 Φ 2 (t )

Region 3

Signal Point (10)

Signal Point (11)

Region 4

Φ 1 (t )

Region 2

Signal Point (00)

Signal Point (01)

Region 1

Figure 17-1 The signal constellation diagram of QPSK modulation

From equation (17-2), it exits a group of orthogonal functions, which are Φ1 ( t ) = A cos (ωc t)

(17-3a)

Φ 2 ( t ) = A sin (ωc t )

(17-3b)

So, from equation (17-1), QPSK modulated signal can be simplified as

x QPSK ( t ) = cos [ (2m − 1)

17－4

π 4

] ⋅ Φ1 − sin [ ( 2m − 1)

π 4

]⋅ Φ2

(17-4)

Chapter 17

QPSK Modulator

From the above equation, QPSK modulated signal can be assumed as a combination of two BPSK modulation signal. Figure 17-2 is the basic block diagram of the QPSK modulator. From the block diagram, the input data signal has to be converted to parallel output by the multiplexer. I-data

Data Signal Input

Multiplexer

Q-data

Balanced Modulator

I-BPSK QPSK Modulated Signal Output

Φ 1 (t )

Balanced Modulator

Q-BPSK

Φ 2 (t )

Figure 17-2

The basic block diagram of QPSK modulator

The outputs of the multiplexer are the I-data and Q-data, which will match with the orthogonal functions and the balanced modulators to obtain the I-data of BPSK modulation signal (I-BPSK) and Q-data of BPSK modulation signal (Q-BPSK). These two groups of data will be summed to produce the QPSK modulated signal. Figure 17-3 shows the circuit circ uit block diagram of QPSK modulator. 2 bits data (2 bits in a group) is sent to the bit splitter at the same time. These two groups of data will be split to parallel data. One of them will lead to I

17－5


channel to become I-data and the other will lead to Q channel to become Q-data. The phase of I-data is similar to the carrier of the reference oscillator, which will be modulated to become I-BPSK. However, the phase difference between Q-data and the carrier of the reference oscillator is 90°, which will be modulated to become Q-BPSK. We know that the QPSK modulator is the combination of two BPSK modulators. Thus, at the output terminal of the I balanced modulator (I-BPSK), there are two types of phases will be produced, which are + cos ωc t and − cos ωc t . Similarly, at the output terminal of the Q balanced modulator (Q-BPSK), there are also two types of phases will be produced, which are + sin ωc t and − sin ωc t . I Channel

± cos ωc t Balanced Modulator 1 Logic 1 = +1V Logic 0 = −1V

f b

2 bits Data Signal Input

f b / 2

Reference Carrier Oscillator cos ωc t

I Buffer Q

f b / 2 Bit Splitter

Figure 17-3

Linear Adder

QPSK Output BPF

90o Phase Shift

1/2

Bit Clock

cos ωc t

Logic 1 = +1V Logic 0 = −1V

Q Channel f b / 2

sin ωc t Balanced Modulator 2 ± sin ωc t

The circuit block diagram of QPSK modulator

When the summer combines these two groups of orthogonal BPSK modulated signal, there will be four possible phases which are + sin ωc t + cos ωc t , − sin ωc t − cos ωc t .

17－6

+ sin ωc t − cos ωc t ,

− sin ωc t + cos ωc t

and

Chapter 17

QPSK Modulator

Figure 17-4(a) is the truth table of the phase output of QPSK modulation and figure 17-4(b) is the constellation diagram of QPSK modulation. From figure 17-4 (b), QPSK has four possible signal constellations with same amplitude and the phase difference is 90o . Therefore, although the QPSK signal has a

± 45o deviation during

transmission, the receiver still can demodulate the signal correctly. Figure 17-5 to figure 17-9 are the details circuit diagrams of each block of QPSK modulator in figure 17-3. Figure 17-5 shows the bit splitter, which is comprised by four D-flip flops and one JK flip flop. D-flip flop 1 (DFF1) and D-flip flop 2 (DFF2) comprise a shift register which its transmission rate is the same as the data rate. JK flip flop 1 (JKFF1) and XOR gate comprise an inverter. The objective is to invert the CLK signal, then it will pass through the capacitor to delay the signal so that the D-fli p flop 3 (DFF3) and D-flip flop 4 (DFF4) are able to convert the serial input to parallel output, which are I-data and Q-data. The duty cycle of I-data and Q-data are the double the original data signal, 2T b . Binary Input

Q

Phase Output of QPSK Modulation Signal

Q

I

0

0

− 135o

0

1

− 45o

1

0

+ 135o

1

1

+ 45o

(a) The truth table of phase output Figure 17-4

I

+ sin ωc t − cos ωct

1

cos

Q

c

t

1

t

cos

c

1

c

t

Q

I 0

I

+ sin ωc t + cos ω c t

0

− sin ωc t − cos ωc t

0

Q sin

I

− sin ωct + cos ωct sin

c

t

0

1

(b) The constellation diagram

The truth table and the constellation diagram of QPSK modulator

17－7


Data I / P

D CLR Q

DFF1

CLK I / P

CK PR Q

D CLR Q DFF2

D CLR Q DFF3

CK PR Q

CK PR Q

I-Data

+5V D CLR Q DFF4

CLR Q JKFF1 CK Q K PR J

CK PR Q

C1

Figure 17-5

Q-Data

100 nF

Bit splitter

Figure 17-6 shows the unipolar to bipolar converter, which is comprised by 74HCU04, 74HC126, 3904, 3906, D Z1, DZ2, DZ3 and R 1 to R 8. The objective of this circuit is to convert the unipolar I-data and unipolar Q-data to bipolar I-data and bipolar Q-data. After that these signals will be inputted to pin 1 of MC1496. The operation theory is to invert the digital signal by inverter (74HCU04) and then pass through two followers to split the signal into two. These two signals will pass through the switch, which is comprised by 3904, 3906, D Z1, DZ2, DZ3 and R 1 to R 8 to convert the unipolar signal to bipolar signal.

17－8

Chapter 17

QPSK Modulator

+5V

10k

R 1

U1

50

U2

R 2 Unipolar Data Input

R 7

R 5

1k R 3

Q1 3906

74126

7404 10k

1k D Z2

Bipolar Data Output

DZ3 U3

R 4

Q2 3904

74126 1k

D Z1

R 8

R 6

1.5k

50

−5V

Figure 17-6

The circuit diagram of unipolar to bipolar converter

R 12 +12V C4

1k R 13 1k

3

2 Carrier

Signal Input 100k R 1

C1

R 15 3.9k

100 R 10

100 R 9 R 3

8

R 16 3.9k C3

6

10 10nF 2.7k 10k

R 5 VR 1

Data

Signal Input

6.8k

+12V 10nF

12

10k R 7

10nF MC1496

R 17 5.6k

100k

R 2

0.01uF

µA741 C5

PSK Output

−12 V

1 10k R 4

10k R 6 VR 2

4 R 8

R 11

100

100

14

5

R 18

0.1uF C2

500k

R 19 10k

200 R 14 10k

−12 V

Figure 17-7

The circuit diagram of balanced modulator

17－9


Figure 17-7 shows the details circuit diagram of balanced modulator. The balanced modulator is comprised by MC1496. Both the carrier signal and data signal are single-ended inputs. The carrier signal is inputted at pin 10 and the data signal is inputted at pin 1. The R 13 and R 14 determine the gain and the bias current of the circuit, respectively. If we adjust VR 1 or the amplitude of digital signal, we may prevent the modulated signal from distortion. Then this signal will pass through the filter, which is comprised by µA741 , C3, C5, R 17, R 18 and R 19. The objective is to remove the high frequency signal in order to obtain the optimum PSK signal.

Figure 17-8 shows the phase shifter, which is used to shift the phase of carrier signal. This situation will produce a group of orthogonal carrier signal, which will supply to the balanced modulators of I-channel and Q-channel. The phase angle ( θ ) is related to R i , Ci and the frequency of carrier. The expression is θ tan ( ) 2 R i = 2π f Ci

(17-5)

Figure 17-9 shows the circuit diagram of linear summer. The objective of the linear summer is to combine the two groups of the orthogonal BPSK modulation signals to become a QPSK signal.

17－10

Chapter 17

QPSK Modulator

100k R 2

1nF

Ci

100k R 1 Carrier Input Terminal

uA741

20k R i

Carrier Output Terminal

C1

Phase Adjustment

10nF

Figure 17-8

The circuit diagram of phase shifter

1k R 4

1k R 1 I-BPSK

uA741

Q-BPSK

QPSK Output

1k R 2 R 3 330

Figure 17-9

The circuit diagram of linear summer

17－11


17-3: Experiment Items Experiment 1: Bit splitter 1. Refer to figure 17-5 or ETEK DA-2000-09 module. 2. At input terminal of data signal (Data I / P ), input 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V), 100 Hz frequency and square wave with 33% duty cycle, i.e. a serial input data streams signal with “100”. 3. At the input terminal of clock signal (CLK I / P ), input 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V), 300 Hz square wave frequency. 4. By using oscilloscope, observe on the I-Data output terminal and Q-Data output terminal of bit splitter, then record the measured results in table 17-1. 5. Change the frequency of data signal to 1 kHz and the frequency of clock signal to 3 kHz, the others remain the same. By using oscilloscope, observe on the I-Data output terminal and Q-Data output terminal of bit splitter, then record the measured results in table 17-1. 6. Change the duty cycle of data signal to 66 %, i.e. a serial input data streams signal with “110” and the others remain the same. Repeat steps 2 to 5, then record the measured results in table 17-2.

17－12

Chapter 17

QPSK Modulator

Experiment 2: QPSK modulator 1. Refer to the circuit block diagram of QPSK modulator in figure 17-3, then by using the detail circuit diagrams of the each circuit block diagram from figure 17-5 to figure 17-9, construct the QPSK modulator or ETEK DA-2000-09 module. 2. At the input terminal of data signal (Data I / P ), input 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V and low is 0 V), 100 Hz frequency, square wave with 33% duty cycle, i.e. a serial input data streams signal with “100”. 3. At the input terminal of clock signal (CLK I / P ), input 2.5 V amplitude and 2.5 V offset (i.e. high is 5 V and low is 0 V) and 300 Hz square wave frequency. 4. By using oscilloscope, observe on the I-Data output terminal and Q-Data output terminal of bit splitter, and also the output terminal T 1 and T 2 of unipolar to bipolar converter. Then records the measured results in table 17-3. Let f Data = 1 kHz , f CLK = 3 kHz , repeat the above steps and record the measured results in table 17-3. 5. At the carrier signal input terminal (Carrier I / P ), input a 500 mV amplitude and 20 kHz sine wave frequency. 6. By using oscilloscope, observe on the output terminals of I-Carrier and Q-Carrier of phase shifter, then adjust the variable resistor VR i (or the “Phase Adjust” of ETEK DA-2000-09 module), so that the phase difference between I-Carrier and Q-Carrier is 90°, then record the measured results in table 17-4.

17－13


7. By using oscilloscope, observe on the signal output terminal of balanced modulator 1 (T 3), adjust VR 1 (or BMR 1 of ETEK DA-2000-09 module), until the waveform without occurring distortion. Then slightly adjust VR 2 (or BMR 2 of ETEK DA-2000-09 module) to avoid the asymmetry of the waveform. Finally record the output signal waveform of the balanced modulator in table 17-4, which is the I-BPSK modulated signal. 8. By using oscilloscope, observe on the signal output terminal of balanced modulator 2 (T4), adjust VR 1 (or BMR 3 of ETEK DA-2000-09 module), until the waveform without occurring distortion. Then slightly adjust VR 2 (or BMR 4 of ETEK DA-2000-09 module) to avoid the asymmetry of the waveform. Finally record the output signal waveform of the balanced modulator in table 17-4, which is the Q-BPSK modulated signal. 9. By using oscilloscope, observe on the output terminal of linear summer, which is the combination of I-BPSK and Q-BPSK modulation signals. Then record the measured results in table 17-4, which is the QPSK modulated signal. 10. Let f Data = 1 kHz , f CLK = 3 kHz , repeat step 7 to step 9, then record the measured results in table 17-4. 11. Change the duty cycle of data signal to 66 %, i.e. a serial input data streams signal with “110” and the others remain the same. Repeat steps 1 to 10 and by using oscilloscope, observe on the waveform of each signal output terminal, then record the measured results in table 17-5 and table 17-6.

17－14

Chapter 17

QPSK Modulator

17-4: Measured Results Table 17-1

Observe on the output signal of bit splitter by changing the frequency of data signal (The duty cycle of data signal is 33 %).

Data Signal Frequencies

100 Hz

1 kHz

Clock Signal Frequencies

300 Hz

3 kHz

Data Signal Waveforms

I-Data Output Terminal of Bit Splitter

Q-Data Output Terminal of Bit Splitter

17－15


Table 17-2

Observe on the output signal of bit splitter by changing the frequency of data signal (The duty cycle of data signal is 66 %).


100 Hz

1 kHz


300 Hz

3 kHz




17－16

Chapter 17

Table 17-3

QPSK Modulator

Observe on the output signal of QPSK modulator by changing the frequency of data signal ( Vc = 500 mV , f c = 20 kHz , Duty cycle of data signal is 33 %).


100 Hz

1 kHz


300 Hz

3 kHz




17－17


Table 17-3

Observe on the output signal of QPSK modulator by changing the frequency of data signal (Continue) ( Vc = 500 mV , f c = 20 kHz , Duty cycle of data signal is 33 %).


100 Hz

1 kHz


300 Hz

3 kHz

I-Data Output Terminal T1 of Unipolar to Bipolar Converter

Q-Data Output Terminal T1 of Unipolar to Bipolar Converter

17－18

Chapter 17

Table 17-4

QPSK Modulator



100 Hz

1 kHz


300 Hz

3 kHz

I-Carrier Output Terminal of Phase Shifter

Q-Carrier Output Terminal of Phase Shifter

Output Terminal T3 of Balanced Modulator 1 (I-BPSK)

17－19


Table 17-4


Output Terminal T4 of Balanced Modulator 2 (Q-BPSK)

Output Terminal of Linear Summer (QPSK O / P )

17－20

Chapter 17

Table 17-5

QPSK Modulator



100 Hz

1 kHz


300 Hz

3 kHz




17－21


Table 17-5



100 Hz

1 kHz


300 Hz

3 kHz



17－22

Chapter 17

Table 17-6

QPSK Modulator


Data Signal Frequency

100 Hz

1 kHz

Clock Signal Frequency

300 Hz

3 kHz




17－23


Table 17-6



Output Terminal of Linear Summer (QPSK O / P )

17－24

Chapter 17

QPSK Modulator

17-5: Problems Discussion 1. What are the basic circuit structures of QPSK modulator and also explain its operation theory? 2. What is the operation theory of bit splitter? 3. If the data input of bit splitter is 50% duty cycle, what are the output signals of I-Data output terminal and Q-Data output terminal of bit splitter? 4. If we need the input phase and output phase to be 90° phase difference, then what are the values for R i and Ci as shown in figure 17-8? (assume the carrier frequency is 100 kHz)

17－25

Table 17-1 Observe on the output of bit splitter by changing the frequency of data signal (The duty cycle of data signal is 33 %) Data Signal Frequencies Clock Signal Frequencies

Data Signal Waveform



100Hz

1kHz

300Hz

3kHz

Table 17-2 Observe on the output signal of bit splitter by changing the frequency of the data signal (The duty cycle of data signal is 66%) Data Signal Frequencies Clock Signal Frequencies




100Hz

1kHz

300Hz

3kHz

Table 17-3 Observe on the output signal of QPSK modulator by changing the frequency of data Signal (Vc=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies Clock Signal Frequencies




100Hz

1kHz

300Hz

3kHz

Table 17-3 Observe on the output signal of QPSK modulator by changing the frequency of data signal (Vc=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies Clock Signal Frequencies



100Hz

1kHz

300Hz

3kHz





100Hz

1kHz

300Hz

3kHz



Output Terminal of Linear Summer (QPSK- O/P)

100Hz

1kHz

300Hz

3kHz

Table 17-5 Observe on the output signal of QPSK modulator by changing the frequency of data Signal (Vc=500mV, fc=20kHz, Duty cycle of data signal is 66%) Data Signal Frequencies Clock Signal Frequencies




100Hz

1kHz

300Hz

3kHz




100Hz

1kHz

300Hz

3kHz





100Hz

1kHz

300Hz

3kHz



Output Terminal of Linear Summer (QPSK- O/P)

100Hz

1kHz

300Hz

3kHz

EDU-LABS DIDACTIC QPSK Demodulator

Experiment Module Chapter 18 : DCT18

User Manual

Digital Communication Systems

18-1: Curriculum Objectives 1. To understand the operation theory of QPSK demodulation. 2. To design the signal squarer by using MC1496. 3. To understand the methods of measuring and adjusting the QPSK demodulation circuit.

18-2: Curriculum Theory Figure 18-1 shows the circuit block diagram of QPSK demodulator. From the diagram, we know that the operation of QPSK demodulator is similar to PSK demodulation in chapter 16. Both of them use the structure of the Squaring loop detector, the main difference is just the QPSK demodulator needs two groups of signal squarer. If let x QPSK ( t ) as the PSK modulated signal, then π

x QPSK ( t ) = A cos [ωc t + ( 2m − 1) ] ; m = 1, 2, 3, 4 4

(18-1)

Where the corner frequency ( ωc ) is constant. When we let this modulation signal input into the signal squarer 1, then the output signal of signal squarer 2 can be expressed as

18－2

Chapter 18

QPSK Signal Input Terminal

Signal Squarer 1

Signal Squarer 2

I O/P Analog Switch

LPF and Comparator

Q O/P

Figure 18-1

QPSK Demodulator

Frequency Divider

PLL

Phase Detector

(1/4)

I-Data

Parallel to Serial Converter

Q-Data

Data Signal Output Terminal

The circuit block diagram of QPSK demodulation

x out ( t ) = k { k [ x QPSK ( t ) x QPSK ( t ) ] }2 =

=

k 3 A 4 cos 4 [ ωc t + ( 2m − 1) 3 8 +

=

3 8 −

3

4

k A + k 3A 4 8 3

4

8

2

4

]

cos [ 2ωc t + ( 2m − 1)

π

2

]

cos [ 4ωc t + (2m − 1) π ]

k A + k 3A 4

k 3A 4

π

k 3A 4 2

cos [ 2ωc t + ( 2m − 1)

cos ( 4ωc t )

π

2

]

(18-2)

From the equation (18-2), k represents the gain of the signal squarer. The first term is the DC signal, the second term is the output of 2 nd harmonic of the carrier signal ( 2ωc ) and the third term is the output of 4 th harmonic of the carrier signal ( 4ωc ). From the third term above, we know that the two groups of signal squarers can remove all the four phases variation of QPSK and the output of the signal squarer 2 is the four times frequency of the carrier signal.

18－3


Let the output signal of signal squarer as equation (18-2). Then this signal will pass through a filter to block the DC signal and the 2 nd harmonic signal. After that by using the PLL, the 4 th harmonic sine wave signal will be converted to square wave and the square wave signal will pass through a frequency divider to reduce the frequency which equals to the frequency of carrier signal ( ωc ). Then, this signal will pass through the phase detector, which is used to adjust the phase shift of the QPSK signal. The objective of phase detector is to control the analog switch for the I O / P and Q O / P of parallel signal outputs. Then the parallel signals will pass through the rectifier and comparator, which the parallel I-Data and Q-Data outputs will be recovered. Finally by using the parallel to serial converter, the output signals will be recovered to the original data signal. Figure 18-2 to figure 18-7 are the details circuit diagram of each block in figure 18-1. Figure 18-2 is the signal squarer, which is designed by using MC1496. The input signal passes through R 1 and U1, which is the buffer amplifier. This signal will be inputted to pin 1 and pin 10 of MC1496. The magnitude of the input signal is controlled by VR 1, then adjusting VR 1 so that the output signal of pin 12 will double the frequency of the input signal. The U3, C4, R 15, R 16 and R 17 comprise a filter. The objective of the filter is to remove the DC signal and the harmonic signal of the signal squarer. The R 11 and R 12 determine the gain and the bias current of the circuit, respectively.

18－4

Chapter 18

QPSK Demodulator

Figure 18-3 shows the details circuit diagram of the PLL. The objective is to convert the output signal of signal squarer 2 to square wave. The phase of the square wave signal is similar to the phase of the carrier of QPSK. In figure 18-3, we know that the PLL circuit is comprised by 74HC4046, R 1, R 2, R 3, C1, C2 and VR 1. Then we can control the frequency of voltage controlled oscillator by adjusting VR 1. The free-running frequency is the output frequency of the square wave signal in figure 18-3.

Figure 18-4 is the frequency divider, which is implemented by using 74HC393. From the circuit, we know that this frequency divider has two divisors, which are 2 and 4. Pin 3 is used to divide the clock signal by 2. Pin 10 is used to divide the output signal of PLL signal by 4.

R 10 C2 100nF

C1

+12V

3

Signal Input Terminal

7

U1 6

2 R 1 10k

10nF

R 5 100

100 2

3

8

6

R 4

−12 V

VR 1 100k

R 15 10k

4 14

U3

2

6

R 18 1k

4

C6

Signal Output R 19 10nF Terminal 1k

−12 V R 17

5

C3

100nF

7

3 10nF

MC1496 1

R 6 10k

+12V

12

U2

R 8 R 9 100 100

R 14 3.9k C4

10

2.7k

R 5 10k

C5 100nF

R 13 3.9k

R 11 R 7 100

R 2 2k

4

+12V

1k

R 3 1k

R 12 10k

R 16 680

1k

−12 V

Figure 18-2

The circuit diagram of signal squarer

18－5


Square Wave Signal Output

+5V

74HC4046 1 2 3 4

R 1 3.3K

5 6

C2

7 8

1nF

16

Vcc 15 Zener

PCPout PC1out PCinB VCOout EN C1A C1B GND

Sine Wave Signal Input

14

PCinA 13 PC2out 12 R2 11 R1 10

SFout 9 VCOin

R 3 22k

VR 1 30k

R 2 680 C1 10n

Figure 18-3

The circuit diagram of PLL +5V

Clock Signal Input Terminal

U1:74HC393 1 2 3

(1/2) Signal Output Terminal

4 5 6 7

Figure 18-4

1A 1CLEAR

Vcc 2A

1QA

2CLEAR

1QB

2QA

1QC

2QB

1QD

2QC

GND

2QD

14 13 12

Signal Input Terminal

11 10 9

(1/4) Signal Output Terminal

8

The circuit diagram frequency divider

Figure 18-5 is the details circuit diagram of phase shifter. This circuit is used to adjust the phase shift the square wave from frequency divider. Then the phase shifted square wave is used to detect the phase variation of the QPSK signal, which will be used to control the analog switch for parallel I O / P and Q O / P signals. The phase shifter is comprised by using two 26S02 to adjust the phase of the square wave. Then the two

18－6

Chapter 18

QPSK Demodulator

output square waves will be outputted through port 2 and port 4 of U 2, which is used to detect the phase variation of the QPSK signal. After that this signal is used to control the analog switch, 74HC4053 for the two parallel signal outputs, i.e. I O / P and Q O / P .

Figure 18-6 shows the low-pass filter, which is comprised by RC circuit and the voltage comparator, which is comprised by using µA741 and diode. The objective of this circuit is to recover the parallel output signals I O / P and Q O / P to parallel output signals of I-Data and Q-Data.

Figure 18-7 is the circuit diagram of parallel to serial converter. This circuit is used to convert and recover the parallel I-Data and Q-Data signals to serial data signals. From figure 18-7, we know that this converter is comprised by using 74165. The parallel input signal I-Data and Q-Data are inputted through pin 5 and pin 6. The output serial data signal can be obtained at pin 9. The required clock signal of this converter is similar to the clock signal of QPSK modulator. Therefore, we just need to input the clock signal of the QPSK modulator to the input terminal (pin 2) of the converter. At this moment the clock signal will pass through a 1/2 frequency divider and convert to pulse signal which will be sent to pin 1 of 74165.

18－7


+5V +5V VR 1 500k C1 100pF

U1:26S02 1

R 1

2

4.7k

3

+5V

4

Signal I/P

5

+5V

Rx C/D I1

/IO 6 Q 7 /Q 8 GND

Port1

+5V

100pF C2 R 2

Vcc 16 15 Cx 14 Rx 13 C/D I1 12 /IO 11

Cx

100k

Q 10 /Q 9

Port3

+5V +5V R 3 100k

C3 100pF

U2:26S02 1 2 3 4 5

Port1 Port2

6 7 8

R 5 1k

+5V

Cx

Vcc

Rx

Cx

C/D

Rx C/D

I1

I1

/IO Q

/IO

/Q

Q

GND

/Q

100pF C4 R 4

16 15 14 13

100k

12 11 10 9

Port3 Port4

R 6 1k

+5V

+5V QPSK I/P

+5V

R 10 680

R 11 680

U3:74HC4053 1

R 8

2 3

680

4 5 6

R 7

7 8

3.3k

Yo Y2 Y Y3 Y1 Inhibit VEE GND

Vcc 16 X2 15 X1 14 X 13 X0 12 X3 11 A 10 B 9

Q O/P I O/P

R 12 680

C5 100nF

R 9 2.7k

−12 V

Figure 18-5

18－8

The circuit diagram of phase shifter

Port2 Port4

Chapter 18

QPSK Demodulator

+5V

Signal Input Port

3

C1 10nF

Figure 18-6

7

1N4004

U1

6

2 uA741

R 1 100k

R 2 1k

D1 C2 10n

4 −5 V

C2

R 2

74HC04

4.7k

1nF R 1

1/2

Parallel Signal Input Port

R 3 1k

The circuit diagram of low-pass filter and voltage comparator

U1 Clock Signal Input Port

Signal Output Port

10k

I-Data Q-Data

Figure 18-7

C1 1nF

1 2 3 4 5 6 7 8

Vcc Shift/Load CLK Inhibit CLK D E C F 2 U :74165 B G A H Serial/IP QH QH GND

+5V 16 15 14 13 12 11 10 9

Serial O/P

Serial Signal Output Port

The circuit diagram of parallel to serial converter

18－9




18-3: Experiment Items



Experiment 1: Signal squarer and PLL 1.

Refer to the circuit block diagram of QPSK demodulator in figure 18-1, then by using the circuit diagram of signal squarer and PLL in figures 18-2 and 18-3, construct the QPSK demodulator or

EDU-LABS DCT-6000-09

module. 2.

Adjust VR 1 of PLL or PLLR 1 of


module until the

free running frequency (f o) of the output terminal (T3) of 74HC4046 is 80 kHz. 3.

At the input terminal of QPSK demodulator (QPSK I / P ), input a carrier signal with 500 mV amplitude and 20 kHz frequency.

4.

Adjust VR 1 of signal squarer 1 or SSR 1 of


module

until the output signal frequency of the output terminal (T 1) of signal squarer 1 is double the carrier frequency, which is 40 kHz. Adjust VR 2 of signal squarer 2 or SSR 2 of


module until the

output signal frequency of output terminal (T 2) of the signal squarer 2 is four times of the carrier frequency, which is 80 kHz. 5.

By using oscilloscope, observe on the output signal waveforms T 1 of signal squarer 1, T2 of signal squarer 2 and T 3 of PLL. Then record the measured results in table 18-1.

18－10

Chapter 18

QPSK Demodulator

Experiment 2: QPSK demodulator 1.

Refer to the circuit block diagram of QPSK demodulator in figure 18-1, then by using the detail circuit diagrams of the each circuit block diagram from figure 18-2 to figure 18-7, construct the QPSK demodulator or EDU-LABS DCT-6000-09 module.

2.

Using the QPSK modulator in figure 17-3 of chapter 17 or DCT-6000-09

EDU-LABS

module, to produce the PSK modulation signal as the

signal source for this experiment. 3.

At the data signal input terminal of QPSK modulator (Data I / P ), input a signal with 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V), 100 Hz frequency and square wave with 33 % duty cycle, i.e. a serial input data streams signal with “100”.

4.

At the clock signal input terminal of QPSK modulator (CLK I / P ), input 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V ) and 300 Hz square wave frequency.

5.

At the carrier signal input terminal of QPSK modulator (Carrier I / P ), input 500 mV amplitude and 20 kHz square wave f requency.

6.

Adjust QPSK modulator to obtain the optimum output waveform of QPSK modulation signal.

7.

Adjust VR 1 of PLL of QPSK demodulator or PLLR 1 of

EDU-LABS

DCT-6000-09 module until the free-running frequency of output terminal (T3) of 74HC4046 is 80 kHz.

18－11


8.

Connect the output signal of QPSK modulator to the input terminal of QPSK demodulator (QPSK I / P ).

9.

Follow the steps in experiment 1 to adjust the signal squarer 1 and signal squarer 2, so that the output signal T 1 is the two times of the carrier frequency (40 kHz) and the output signal T 2 is the four times of the carrier frequency (80 kHz).

10. Adjust VR 1 in figure 18-5 or “Phase Adjust” in


module, until the I-Data and Q-Data can be obtained correctly. 11. By using oscilloscope, observe on the input signal of QPSK, output signal T1 of signal squarer 1, output signal T 2 signal squarer 2, output signal T3 of PLL 74HC4046, output signal T 4 of frequency divider 74HC393, output signal of I-Data, output signal of Q-Data and the output signal waveform of QPSK demodulator. Then record the measured results in table 18-2. 12. Change the frequency of data signal to 1 kHz and the frequency of clock signal to 3 kHz, the others remain the same. Then record the measured results in table 18-2. 13. Change the duty cycle of data signal to 66 %, i.e. a serial input data streams signal with “110”, and the others remain the same. By using oscilloscope, observe on the waveforms of each output terminal and record the measured results in table 18-3.

18－12

Chapter 18

QPSK Demodulator

 18-4: Measured Results  Table 18-1

The measured results of the output terminal of signal squarer and PLL ( Vm = 500 mV , f c = 20 kHz ).

Test Points

Output Signal Waveforms

QPSK Input Signals

Signal Squarer 1 Output Signal T 1


PLL Output Signal T 3

18－13


Table 18-2

Observe on the output signal of QPSK demodulator by changing the frequency of data signal ( Vm = 500 mV , f c = 20 kHz , Duty cycle of data signal is 33 %).

Data signal frequencies

100 Hz

1 kHz

Clock pulse frequencies

300 Hz

3 kHz

QPSK Input Signals




18－14

Chapter 18

Table 18-2

QPSK Demodulator

Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Continue) ( Vm = 500 mV , f c = 20 kHz , Duty cycle of data signal is 33 %).

Data signal frequencies Clock pulse frequencies

100 Hz

1 kHz

300 Hz

3 kHz

Frequency Divider Output Signal T 4

I-Data Output Signal Waveforms

Q-Data Output Signal Waveforms

QPSK Demodulated Signal Waveforms

18－15


Table 18-3

Observe on the output signal of QPSK demodulator by changing the frequency of data signal ( Vm = 500 mV , f c = 20 kHz , Duty cycle of data signal is 66 %).

Data signal frequencies

100 Hz

1 kHz

Clock pulse frequencies

300 Hz

3 kHz

QPSK Input Signals


Signal Squarer 2 Output Signal, T 2


18－16

Chapter 18

Table 18-3

QPSK Demodulator

Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Continue) ( Vm = 500 mV , f c = 20 kHz , Duty cycle of data signal is 66 %).

Data signal frequencies Clock pulse frequencies

100 Hz

1 kHz

300 Hz

3 kHz

Frequency Divider Output Signal T 4

I-Data Output Signal Waveforms

Q-Data Output Signal Waveform

QPSK Demodulated Signal Waveform

18－17




18-5 Problems Discussion



1.

What are the basic circuit structures of QPSK demodulator?

2.

What are the functions of the phase shifter in QPSK demodulator?

3.

Explain the circuit structure of parallel to serial converter and also the functions of the parallel to serial converter in QPSK demodulator?

18－18

Table 18-1 The measured results of the output terminal of signal squarer and PLL (Vm=500mV, fc=20kHz). Test Points

QPSK Input Signals

Signal Squarer 1 Output Signal T1


Output Signal Waveform

Table 18-1 The measured results of the output terminal of signal squarer and PLL (Vm=500mV, fc=20kHz). Test Points

PLL Output Signal T3

Output Signal Waveform

Table 18-2 Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Vm=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies Clock Signal Frequencies

QPSK Input Signals



100Hz

1kHz

300Hz

3kHz

Table 18-2 Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Vm=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies Clock Signal Frequencies

PLL Output Signal T3

Frequency Divider Output Signal T4

I- Data Output Signal Waveform

100Hz

1kHz

300Hz

3kHz

Dct 6000 09 Qpsk Manual

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