3.10 COMMON-COLLECTOR AMPLIFIER A typical common-collector amplifier using an npn transistor is shown in Figure 46. This circuit is also known as emitter-follower. Its small-signal analysis circuit is given in Figure 47. The corresponding dc and ac load lines are depicted in Figure 48. V CC
i 1
R 1
i C
R S
v s
+ v CE _
i in
+ _
i 2
R 2
i E
+
R E
R L
i o
v o _
Figure 46: A typical common-collector configuration
R S i in
i b
+ v s
+ _
r
π
i c
i a v in
i e
R B
R E
_
+ i o
R L
v o _
Figure 47: Small-signal analysis circuit
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iC (mA) iACM
AC Load Line
IDCM
Q-Point
ICQ
0
IBQ DC Load Line
0
VCEQ
vACM
VDCM
vCE (V)
Figure 48: DC and ac load lines The dc resistance in the collector-emitter loop is RE/α. For small-signal analysis, the effective resistance in the emitter branch is the parallel combination of RE and RL. Let us denote the parallel combination as REL. Then, REL = RE || RL. The forward diode resistance in the base branch is rπ . The effective resistance as seen from the base terminal is RibL such that RibL = rπ + (β + 1) REL = (β + 1)(re + REL) where
re = rπ / (β + 1)
is the equivalent forward diode resistance in the emitter branch. Note that we have included the subscript L to highlight the fact that the effective resistance as seen from the base terminal depends upon the load resistance RL. As long as REL >> re (which is usually the case), the resistance as seen from the base terminal is RibL ≈ (β + 1) REL This is a relatively high resistance. For instance, if REL is in kilo-ohms and β is high (say 100), then RibL is in hundreds of kilo-ohms. Thus, an emitter follower (common collector amplifier) usually offers high input resistance as seen from the base terminal.
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It is evident from Figure 47 that the input resistance depends upon the load resistance. As the load resistance changes so does the input resistance. Let us denote the input resistance including the effect of the load resistance as RinL. From the small-signal analysis circuit, it is clear that RinL is simply a parallel combination of RB and RibL. That is RinL = RB || RibL This equation states that the input resistance can be made very large by choosing a large value of RB. We can, therefore, say that a common-collector configuration can be used as an amplifier in such circuits where large input resistance is needed. In fact, we can use this configuration as a pre-amplifier when the input signal has unusually large resistance to minimize the loading effect. We can now compute all the small-signal currents as follows:
ib =
v in R ibL
ic = βib =
β v in R ibL
i e = (β + 1) i b =
(β + 1) v in v in = R ibL re + R EL
Thus, the output voltage is
v o = i e R EL =
R EL v in re + R EL
From this equation, it should be clear that the output voltage is nearly equal to the input voltage as long as REL >> re (This is usually true). Thus, the voltage gain is
AV =
vo R EL = v in re + R EL
When we neglect re in comparison with REL, we find that the voltage gain is unity.
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We can also express the output voltage and voltage gain in terms of vs as
and
vo =
R EL re + R EL
R inL vs R S + R inL
A VS =
vo R EL = vs re + R EL
R inL R S + R inL
From the voltage gain equation, it becomes evident that as long as re << REL and RS << RinL, the voltage gain approaches unity. Under these assumptions, we can label a common-emitter
configuration as unity gain amplifier. Since the voltage at the emitter is nearly equal to the applied signal, it is for this reason the common-collector configuration is called the emitter follower. The emitter voltage follows the base voltage. From Figure 47, we see that the output resistance is a parallel combination of RE and the total resistance in the base branch as seen from the emitter terminal. Note that the signal voltage vs must be replaced with a short circuit. The total resistance in the base circuit is rπ + (RS || RB).
Thus, the output resistance is RO = RE || [{rπ + (RS || RB)} / (β + 1)]
Let us assume that the input signal is ideal in the sense that its resistance is very small and can be neglected, then RS → 0. The output resistance is now simply a parallel combination of RE and re. Since re is very small in comparison with RE, the output resistance is nearly re. Thus, a
common-collector configuration has negligibly small output resistance. This fact enables us to use the common-collector configuration as the output stage of an amplifier where the load resistance is small (This is usually the case when the load is either a 4-Ω, an 8-Ω, or a 16-Ω speaker). We can summarize our findings for the common-collector or emitter follower circuit as follows: (a)
Its voltage gain is nearly unity.
(b)
Its input resistance is usually quite high.
(c)
Its output resistance is usually very low. We have already discussed another circuit that has all of the above traits. Can you name
it? Well, it is an operational amplifier circuit called the buffer amplifier. Now you know that a single transistor common-collector configuration behaves more like a buffer amplifier. However, it is not as good as the buffer amplifier. But, what more can you expect from a single transistor?
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Design Example: Common-Collector Configuration __________________________________ Select the needed circuit components for the common-emitter amplifier of Figure 46.The following information is known for the amplifier: RE = 5 kΩ, RL = 5 kΩ, β = 49, VBE = 0.7 V, VCE(sat) = 0.2 V, RS = 1 kΩ, VCC = 10 V, and vS = 2 sin(10,000t) V. The other components must be selected in such a way that the input resistance is within ± 5% of 10 kΩ. Design philosophy: Let us first examine if we can design this amplifier for the maximum peak-to-peak voltage swing exactly like the common-emitter design. To determine the collector current at the dc operating point, we need to know RDC and RAC. For the dc analysis, the only resistance in the collector-emitter loop is RE. Thus, the equivalent dc resistance as seen by the collector current is RDC = RE/α = 5 /0.98 = 5.102 kΩ α = β/(β + 1) = 49/50 = 0.98.
where
The ac resistance in the emitter branch is simply the parallel combination of RE and RL. Since RE = RL = 5 Ω, the equivalent ac load resistance is REL = 2.5 kΩ. Thus, the ac resistance in the collector-emitter loop is RAC = REL/α = 2.5/0.98 = 2.551 kΩ
We can now compute the collector current at the Q-point using (34) as
I CQ =
VCC 10 = = 1.307 mA R AC + R DC 2.551 + 5.102
The emitter current and the collector-to-emitter voltage at the Q-point are IEQ = ICQ/α = 1.334 mA VCEQ = VCC – IEQ RE = 10 – (1.334 mA)(5 kΩ) = 3.33 V
The power dissipated by the transistor at the operating point, neglecting the power loss in the base circuit, is PT = VCEQ ICQ = (3.33V)(1.307 mA) = 4.35 mW
The power supplied by the dc source at the operating point is PDC = VCC ICQ = (10 V)(1.307 mA) = 13.07 mW
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The maximum peak-to-peak swing for the collector-to-emitter voltage is 2 VCEQ because the collector-to-emitter voltage can theoretically be as low as 0 V and as high as 2 VCEQ. Stated differently, the maximum swing in either direction for the collector-to-emitter voltage is VCEQ. Therefore, the maximum value of the swing in either direction is 3.33 V. A quick glance at Figure 47 reveals that it is also the swing for the load voltage because vCE + vo = 0. It implies that the maximum output voltage can be as high as 3.33 V. We already know that the voltage gain of the common-collector circuit is nearly equal to unity and the maximum value of the input signal is 2 V. Thus, the expected maximum value of the output signal is nearly equal to 2 V. We can reduce the maximum undistorted swing to a lower value by moving the operating point to the right on the dc load line. As we move down the dc load line, the collector current decreases. The decrease in the collector current causes a decrease in the power supplied by the dc source. If the dc source is a battery, as the power supplied by the battery decreases, the battery life increases. Therefore, moving the operating point down the dc load line is good from the power supplied point of view. As the operating point moves to the right, collector-to-emitter voltage increases while the collector current decreases. The product of collector current and the collector-to-emitter voltage is the power dissipated by the transistor. Note that the power dissipated by the transistor is zero when the voltage drop across the transistor is zero. This is the point on the y-axis which we labeled as (0, IDCM). On the other hand, the collector current is zero when the voltage drop across the transistor is VDCM. This is the point on the x-axis and we labeled it as (VDCM, 0). At any other point of operation on the dc load line, the transistor dissipates power. As we move from one extreme point, say from (0, IDCM) on the dc load line toward the other point (VDCM,0), the power dissipation by the transistor increases. At some value of the collector current IC(max) the power dissipated by the transistor becomes maximum, and then begins to decrease until we reach the other point where it is zero again. Let us now determine the point at which the power dissipated by the transistor is at its maximum. We already know that the voltage drop from collector to emitter is VCE = VCC – IC RDC
Thus, the power dissipated by the transistor is
PT = VCC I C − I C2 R DC
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The power dissipated by the transistor is at its maximum when the rate of change of PT with respect to IC is zero. Thus, differentiating the above equation with respect to IC and setting it to zero, we obtain the collector current at which the transistor dissipates maximum power as
I C (max) =
VCC 2 R DC
In our case, RDC is 5.102 kΩ and VCC = 10 V. Thus, IC(max) = 0.98 mA. The corresponding collector-to-emitter voltage is VCE(max) = 10 – (0.98 mA)(5.102 kΩ) = 5 V
The maximum power dissipation occurs at a point where VCE is 5 V and IC is 0.98 mA. We can call it as the maximum power dissipation point and represent it as (5 V, 0.98 mA). This point is on the right side of the Q-point for the maximum undistorted peak-to-peak voltage swing (3.334 V, 1.3067 mA) computed earlier. As we said earlier, we need to decrease the collector current at the operating point in order to reduce the power supplied by the dc voltage source. As we move the operating point to the right, the power dissipation by the transistor is expected to increase. The question: Where should the operating point be so that power supplied by the dc source is lower than 13.07 mW? Since we expect the maximum value of the output voltage swing to be 2 V or so, we can select the operating point such that vACM - VCEQ is about 2.5 V (using a safety factor of 1.25 to avoid going into the cut-off region). This will give us a theoretical peak-to-peak output voltage swing of 5 V whereas the expected peak-to-peak output voltage is only 4 V. This will surely keep us well above the cut-off region. From Figure 48, it is clear that vACM – VCEQ must be equal to ICQ RAC. Since RAC is 2.551 kΩ, the new Q-point collector current must be ICQ = 2.5/2.551 = 0.98 mA.
It is merely a coincident that the new Q-point happens to be where the transistor dissipates maximum power. Don’t always expect this to be the case. In fact, it would be nice if this really were not the case so that the transistor does not have to operate at a point where it dissipates maximum power. The emitter and base currents at the new Q-point are IEQ = ICQ / α = 0.98 / 0.98 = 1.0 mA IBQ = ICQ / β = 0.98 / 49 = 0.02 mA
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Thus, the collector-to-emitter voltage at the new Q-point is VCEQ = 10 – (1 mA)(5 kΩ) = 5 V.
The dc operating point selection appears to be satisfactory at this stage. At the Q-point, ICQ = 0.98 mA, IBQ = 0.02 mA, IEQ = 1 mA, and VCEQ = 5 V At the dc operating point, the base terminal voltage is VBQ = VBE + IEQ RE = 0.7 + (1 mA)(5 kΩ) = 5.7 V
Selection of R1 and R2: Since we need an input resistance of 10 kΩ, we select R1 and R2 on this basis. In the presence of the load resistance RL, the input resistance is RinL = RB || (β + 1)(re + REL) ≈ RB || (β + 1) REL
where we have neglected the contribution due to re at this time. From the above equation, we get 1 1 1 1 1 ≈ − = − R B R inL (β + 1) R E 10 50 × 2.5 RB = 10.87 kΩ.
Thus,
Note that RB is the parallel combination of R1 and R2. We can compute base voltage as VBB = VBQ + IBQ RB = 5.7 + (0.02 mA)(10.87 kΩ) = 5.92 V
You may have realized by now that VBB is the Thevenin equivalent voltage and RB is the Thevenin equivalent resistance of the biasing circuit. Thus,
VBB = VCC RB =
R2 R1 + R 2
(46)
R1 R 2
(47)
R1 + R 2
From (46) and (47), we obtain
R B = R1
VBB VCC
Substituting RB = 10.87 kΩ, VCC = 10 V and VBB = 5.92 V in the above equation, we get R1 = 18.36 kΩ. Let us select a standard resistor of 18 kΩ for R1.
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To compute R2, we can use the following equation: 1 1 1 = + R B R1 R2
Substituting RB = 10.87 kΩ and R1 = 18 kΩ in the above equation, we obtain R2 = 27.44 kΩ. Let us select a standard resistance of 27 kΩ for R2. We should now verify the design by carrying out exact dc analysis and the small-signal analysis. DC Analysis Using Selected Components All the resistors in the amplifier circuit are: R1 = 18 kΩ, R2 = 27 kΩ, RE = 5 kΩ, and RL = 5 kΩ.
The dc and ac resistances in the collector-emitter loop are RDC = 5.102 kΩ RAC = 2.551 kΩ.
and
The Thevenin equivalent circuit of Figure 46 is given in Figure 49 where VBB = RB =
10 × 27 =6 V 45
18 × 27 = 10.8 kΩ 45
10 V
10.8 kΩ
IC
IB 6 V +_
IE
5 kΩ
Figure 49: Thevenin equivalent circuit for dc analysis
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The currents in the circuit are IB =
6 − 0 .7 = 0.0203 mA 10.8 + 50 × 5
IC = β IB = 49 × 0.0203 = 0.995 mA IE = (β + 1) IB = 50 × 0.0203 = 1.015 mA
The collector-to-emitter voltage: VCE = 10 – (1.015 mA)(5 kΩ) = 4.925 V Since VCE is greater that VCE(sat), the transistor operates in the active region. Thus, the currents and voltages at the dc operating point are as follows: ICQ ≈ 1 mA, IEQ = 1.02 mA, IBQ = 0.02 mA, and VCEQ = 4.93 V Small Signal Analysis The ac load line passes through the Q-point (4.93 V, 1 mA) and intersects the x-axis at vACM where vACM = VCEQ + ICQ RAC = 4.93 + (1 mA)(2.551 kΩ) = 7.48 V
Thus, the maximum positive swing in the collector-to-emitter voltage is 2.55 V. The maximum negative swing, of course, is VCEQ = 4.93 V. Thus, the symmetrical undistorted peak-to-peak swing is 5.1 V (2 × 2.55). The required peak-to-peak swing is about 4 V. Hence, the transistor is expected to operate well above the cut-off region. The forward resistance of the diode in the base branch, when n = 1, is rπ =
VT 25 mV = = 1250 Ω I BQ 0.02 mA
Its counterpart in the emitter circuit is
re =
rπ 1250 = = 25 Ω β+ 1 50
The input resistance, including the load resistance, is RinL = RB || (β + 1)(re + REL) = 10.8 || 50 (2.5 + 0.025) = 9.95 kΩ.
The input resistance is well within the ± 5% variations of the desired value of 10 kΩ. Thus, our design meets the input resistance requirements.
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We can now compute the small signal base current and emitter current as
ib =
v in v in v in = = mA (β + 1)(re + R EL ) 50(2.5 + 0.025) 126.25
i e = (β + 1) i b = 50 i b =
v in mA 2.525
Thus, the output voltage is v o = i e R EL =
v in 2.5 = 0.99 v in V 2.525
Thus, the voltage gain is AV = 0.99. The output voltage is in phase with the input voltage. We can also express vin in terms of vs as
v in =
R inL 9.95 vs vs = 10.95 R S + R inL
Thus, the output voltage in terms of vs is v o = 0.99
9.95 v s = 0 .9 v s 10.95
Thus, the overall voltage gain is AVS = 0.9. As vs varies as 2 sin(10,000t) V, the output voltage varies as 1.8 sin(10,000t) V. The peakto-peak maximum swing of the output voltage is 3.6 V. It is well within the maximum undistorted swing of 5.1 V. We can, in fact, modify the design by redesigning the amplifier for a maximum peak-topeak swing of say 4.5 V using a safety factor of 1.25 (i.e. 1.25 × 3.6 V). This will certainly lower the collector current at the new dc operating point and thereby further reduce the drain on the battery. The new design is left as an exercise for you. Carry it out in order to build the necessary confidence in designing the amplifiers. The input and the output currents are
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i in =
v in v = in mA R inL 9.95
io =
vo 0.99 v in = = 0.198 v in mA RL 5
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Chapter – 3/BJT
io = 1.97 i in
Thus, the current gain:
AI =
Therefore, the power gain:
A P = A V A I = 0.99 × 1.97 = 1.95
The output resistance is R O = R E //
rπ + R S // R B β +1
Substituting the values, we obtain R O = 5 //
1.25 + 1 // 10.8 = 0.043 kΩ or 43 Ω. 50
As stated earlier, the output resistance of an emitter follower is low. Thus, an emitter follower can be used to match a high source resistance to a low load resistance. Other quantities of interest such as the total collector current, total collector-to-emitter voltage drop, power dissipated by all resistors, etc. can now be computed. 3.11 COMMON-BASE CONFIGURATION A general single transistor common-base amplifier is given in Figure 50. In this case, the input is at the emitter and the output is at the collector. The small-signal model of the common-base amplifier is shown in Figure 51. The corresponding dc and ac load lines are depicted in Figure 52. V CC
R 1
R C + R S
R 2
R L + _
R E
v s
v o _
Figure 50: A common-base amplifier
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i R B
+
r b
π
i e
v in i _ RE
R E
+
i c R C
R S i in
+ v _ s
R L i o
v o _
Figure 51: Small signal model of a common base amplifier
iC IACM
AC Load line
IDCM
Q-Point
ICQ
0
IBQ DC Load Line
0
VCEQ
vACM
VDCM
vCE
Figure 52: The dc and ac load lines In order to draw the dc and ac load lines, we need the dc and ac resistances in the collector-emitter branch. The examination of Figure 50 reveals that the dc resistance is (48)
RDC = RC + RE/α
where
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α = β/(β + 1)
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Chapter – 3/BJT
From the small signal model given in Figure 51, we find that the ac load resistance is (49)
RCL = RC || RL
In terms of RCL, the ac resistance in the collector-emitter branch is (50)
RAC = RCL + RE/α
When the transistor has a high β (≥100), we can make the first-order approximation that α is nearly unity. Then, the approximate values of the dc and ac resistances are RDC ≈ RC + RE RAC ≈ RCL + RE
and
The approximate expressions are good during the design process. Once we have selected all the components, then we can use the exact expressions. Let us now analyze the small-signal model given in Figure 51. The base current can be expressed in terms of vin as
ib = −
v in rπ + R B
(51)
Note that ib is inversely proportional to RB. The base current can be increase by setting RB equal to zero for the small-signal analysis. This can, of course, be done by connecting a large
capacitor between the base terminal and the common terminal. The capacitor will then provide a path for the ac variations in the base current. The collector current is ic = β ib = −
β v in rπ + R B
(52)
The emitter current is i e = (β + 1) i b = −
(β + 1) v in rπ + R B
(53)
The current through RE is
i RE =
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v in RE
(54)
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Chapter – 3/BJT
Hence, the input current is i in = i RE − i e = v in = v in
The output voltage:
+
1 RE
(β + 1) R E + rπ + R B R E (rπ + R B )
v o = − i c R CL = AV =
Therefore, the voltage gain:
β +1 rπ + R B
β R CL v in rπ + R B
β R CL rπ + R B
(55)
(56) (57)
Once again, it is clear from this equation that the voltage gain can be increased by bypassing RB is with a capacitor. This circuit, therefore, can provide a high voltage gain.
vo RC β = v in R L rπ + R B R C + R L
The output current:
io =
The current gain:
AI =
io β RC = i in RC + RL
RE rπ + R B + (β + 1) R E
(58)
(59a)
When RB is bypassed by a capacitor and rπ is small in comparison with (β + 1) RE, then the current gain becomes
α RC RC + RL
AI ≈
(59b)
Note that the output resistance for the common-base amplifier from Figure 51 is RC. If RC is selected on the basis of maximum power transfer to the load, then RC = RL. In this case, the current gain is less than 0.5 because α is usually less than 1. The input resistance:
R in = R E ||
rπ + R B β +1
(60)
Once again, if RB is bypassed by a capacitor and RE is usually quite large in comparison with re, then the input resistance is
R in ≈
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rπ = re β +1
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(61)
Chapter – 3/BJT
From this equation, it is clear that the input resistance of a common-base configuration is usually very low (few ohms). For this reason, this configuration is often used in high frequency applications (above 10 MHz) where low impedances are very common. It is also widely used as a differential amplifier in the design of integrated circuits. In a nutshell, a common-base amplifier has the following characteristics: *
Low input resistance ( ≅ re)
*
High output resistance (RC)
*
Low current gain (usually less than 1)
*
High voltage gain Example: Analysis of a Common Base Amplifier ____________________________________
A common-base amplifier circuit is shown in Figure 53. The circuit elements and the parameters of the transistor are RE = 10 kΩ, RC = 2.2 kΩ, RL = 2.2 kΩ, RS = 10 Ω, VCC = 15 V, – VEE = – 15 V, VBE = 0.7 V, VCE(sat) = 0.2 V, and β = 49. Determine the voltage gain, the current gain, the input and output resistances. V CC
R C R S
v s
+ _
v o R E
R L
- VEE Figure 53: A common-base amplifier
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VCC RC +
RS
RL
+ vs _
RE
vo _
- VEE Figure 54: Circuit of Figure 53 redrawn The common-base amplifier is usually drawn as shown in Figure 53 in order to shown the input signal on the left side and the output signal on the right side of the circuit. We can redraw this circuit so that it appears familiar to us. Such a circuit is redrawn in Figure 54.
VCC
IC IB
RC +
VCE _
IE
RE
- VEE Figure 55: Circuit for dc analysis
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DC Analysis The amplifier circuit for the dc analysis is shown in Figure 55. The base voltage is zero because it is directly connected to the common terminal (ground). The dc voltage at the emitter is – 0.7 V because of VBE = 0.7 V. The voltage drop across RE is – 0.7 – (– VEE). Since, – VEE is – 15 V, the voltage drop across RE is 14.3 V. Since RE is 10 kΩ, the emitter current is IE =
14.3 V = 1.43 mA 10 kΩ
The corresponding base and collector currents, when β = 49, are
IB =
IE 1.43 mA = = 0.0286 mA β +1 50
I C = β I B = 1.4014 mA
The collector-to-emitter voltage is VCE = VCC – VEE – IC RC – IE RE = 30 – (1.4014 mA)(2.2 kΩ) – (1.43 mA)(10 kΩ) = 12.617 V
Since VCE is greater that VCE(sat), the transistor operates in the active region. Therefore, at the dc operating point, we have ICQ = 1.4014 mA, IBQ = 0.0286 mA, IEQ = 1.43 mA, and VCEQ = 12.617 V In order to sketch the dc load line, let us first determine the dc resistance in the collector-emitter loop. From Figure 55, it is clear that the dc resistance is RDC = RC + RE/α
where
α = β / (β + 1) = 49 / 50 = 0.98
Thus:
RDC = 2.2 + 10/0.98 = 12.404 kΩ
The dc load line equation can now be written as VCE = VCC – VEE – IC RDC = 30 – 12.404 IC
The two points on this line are (30 V, 0) and (0, 2.42 mA). The line joining the two points yields the dc load line as depicted in Figure 56. The intersection of the dc load line with the transistor characteristic for IB = 0.0286 mA yields the Q-point.
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iC (mA)
IDCM = 2.42
Q - Point I BQ = 0.0286 mA
ICQ = 1.40
dc Load line 12.62 VCEQ
0
vCE (V)
30 VDCM
Figure 56: The dc load line
Small signal analysis Let us now compute the voltage gain, the current gain, the input resistance and the output resistance. To do so, we have to sketch the small signal equivalent circuit as given in Figure 57.
i c
r i b
π
R S v s
+ _
i e i + in v in
i
+ R C i o
R E
v R o L _
RE
_
Figure 57: Small signal circuit for the common-base amplifier
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From the above figure it is clear that the small signal collector current flows through the emitter resistance RE and the parallel combination of RL and RC. Note that RC in parallel with RL is the ac load resistance. That is, RCL = RC || RL
For our circuit, RC = 2.2 kΩ, and RL = 2.2 kΩ. Substituting these values in the above equation, we obtain RCL = 1.1 kΩ. The forward resistance of the diode in the base branch, when n = 1, is rπ =
VT 25 mV = = 874 Ω = 0.874 kΩ I BQ 0.0286 mA
The equivalent resistance in the emitter branch is
re =
rπ 874 = = 17.48 Ω β + 1 50
We can now calculate the base, collector, and emitter currents in Figure 57 as
ib = −
v in v in =− = − 1.144 v in mA rπ 0.874 kΩ
i c = β i b = 49 (− 1.144 v in ) = − 56.06 v in i e = (β + 1) i b = − 57.20 v in
mA
mA
The current through RE is
i RE =
v in v in = = 0.1 v in mA R E 10 kΩ
The output and the input currents are
io = − ic
RC 2 .2 (− 56.06 v in ) = 28.03 v in mA =− RC + RL 2 .2 + 2 .2
i in = i RE − i e = 0.1 v in + 57.2 v in = 57.3 v in mA
(62)
The output voltage can now be computed as v o = i o R L = (28.03 v in )(2.2) = 61.67 v in V
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(63)
Chapter – 3/BJT
Hence, the voltage and current gains are
AV = AI =
vo = 61.67 v in
i o 28.03 v in = = 0.489 i in 57.3 v in
As expected, the voltage gain is high and the current gain is less than 0.5. The power gain is A P = A V A I = 61.67 × 0.489 = 30.16
Let us now represent the output voltage in terms of the voltage of the applied signal. The input voltage vin can be expressed in terms of vs as
v in =
R in vs R in + R s
Since Rin is simply the ratio of vin to iin, it can be computed from (62) as 17.45 Ω. We could have also computed it as the parallel combination of RE and re. Since RE >> re, the input resistance is almost equal to re (17.5 Ω). The signal resistance RS is given as 10 Ω. Substituting these values in the above equation, we obtain v in = 0.636 v s
We can now express the output voltage from (63) in terms of vs as vo = 61.67 (0.636 vs) = 39.22 vs V
The overall voltage gain can now be computed as
A VS =
vo = 39.22 V vs
The output resistance is simply R C , i.e. 2.2 kΩ.
BG/BJT2/C/ May 31, 2002
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Chapter – 3/BJT
