MOS Transistors Width W Drain
Gate
Length L
SiO2 (insulator)
Gate
Source Drain
Source
nMOS nMOS tran transi sist stor or
n channel n
Gate
p-type (doped) substrate Conductor (poly)
Drain
• Sili Silico con n subs substr trat atee dope doped d with with im impuri puriti ties es
Source
pMOS pMOS tran transis sisto torr
• Addi Adding ng or cutt cuttin ing g away away insu insula lati ting ng glas glasss (Si (SiO O2) • Addi Adding ng wire wiress mad madee of of pol polyc ycry rysta stall llin inee sil silic icon on ( polysilicon, polysilicon, poly) or metal, insulated from the substrate by SiO2 EE 261
James Morizio
1
Silicon Lattice • Tran Transis sistor torss are are built built on a silic silicon on subst substra rate te • Sili Siliccon is a Grou Group p IV IV ma materi terial al • Form Formss crys crysta tall latt lattic icee with with bonds bonds to four four neigh neighbo bors rs
EE 261
Si
Si
Si
Si
Si
Si
Si
Si
Si
James Morizio
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Silicon Lattice • Tran Transis sistor torss are are built built on a silic silicon on subst substra rate te • Sili Siliccon is a Grou Group p IV IV ma materi terial al • Form Formss crys crysta tall latt lattic icee with with bonds bonds to four four neigh neighbo bors rs
EE 261
Si
Si
Si
Si
Si
Si
Si
Si
Si
James Morizio
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Dopants • Silico icon is is a se semiconductor • Pure Pure sil silic icon on has has no fre freee carr carrie iers rs and and con condu duct ctss poor poorly ly • Addi Adding ng dopa dopant ntss incr increa ease sess the the cond conduc ucti tivi vity ty • Grou roup V: V: ex extra tra ele elecctro tron (n(n-ty typ pe) • Grou Group p III: III: mis missin sing g ele elect ctro ron, n, cal calle led d hol holee ((pp-ty type pe))
EE 261
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
James Morizio
+ -
Si Si Si
3
p-n Junctions • A jun junct ctio ion n betw betwee een n p-t p-typ ypee and and n-t n-typ ypee semiconductor forms a diode. • Curr Curren entt flo flows ws only only in one one dir direectio ction n
EE 261
p-type
n-type
anode
cathode
James Morizio
4
nMOS Transistor • Four Four ter term minal inals: s: ga gate, te, sour source ce,, drai drain, n, bod body y • Gate – oxid oxidee – bod body st stack lo looks oks li like a capac pacitor itor – Gate Gate and and body body ar aree ccon ondu duct ctor orss – SiO2 (oxide) is a very good insulator – Call Called ed meta metall – oxid oxidee – semi semico cond nduc ucto torr (MOS (MOS)) cap capac acit itor or Source
– Eve Even th though ugh ga gate is
Gate
Drain Polysilicon
no longer made of metal
SiO2
n+
n+ p
EE 261
James Morizio
bulk Si
5
nMOS Operation • Body is commonly tied to ground (0 V) • When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF Source
Gate
Drain Polysilicon SiO2 0
n+
n+ p
EE 261
S
D
bulk Si
James Morizio
6
nMOS Operation Cont. • When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source
Gate
Drain Polysilicon SiO2 1
n+
n+ p
EE 261
S
D
bulk Si
James Morizio
7
pMOS Transistor • Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior Source
Gate
Drain
Polysilicon SiO2
p+
p+ n
EE 261
James Morizio
bulk Si
8
Power Supply Voltage • GND = 0 V • In 1980’s, VDD = 5V • VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
EE 261
James Morizio
9
Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain g=0 d nMOS
pMOS
d OFF
g
ON
s
s
s
d
d
d
g
OFF
ON s
EE 261
d
g=1
s
James Morizio
s
10
MOS Transistor Switches a
N-switch
a
s
S=0 s
N S=1
b b
EE 261
0
0
1
1 (degraded) Good 0, Poor 1
James Morizio
11
MOS Transistor Switches a P-switch
a
S=1 s
s
1
0
0 (degraded)
P S=0
b
Good 1, Poor 0
b CMOS switch (Transmission gate) a
1
s
s s b
a
C
b
a
b s
s
EE 261
James Morizio
S=0 S=1
Good 0 Good 1
12
Signal Strength • Strength of signal – How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0 • nMOS pass strong 0 – But degraded or weak 1
• pMOS pass strong 1 – But degraded or weak 0
• Thus nMOS are best for pull-down network EE 261
James Morizio
13
CMOS Inverter A
VDD
Y
0 1
A A
Y
Y
GND EE 261
James Morizio
14
CMOS Logic Gates-1 VDD
Inverter
Pull-up path
Input a
Pull-down path
Output a
Gnd VDD Pull-up tree b
2-input NAND a
z a b
Pull-down tree
Pull-up truth table a b z
0 0 Z 0 1 Z
0 0 1 0 1 1
1 0 Z
1 0 1
1 1 0
1 1 Z NAND truth table a b z 0 0 1 0 1 1 1 0 1 1 1 0
Gnd EE 261
Pull-down truth table a b z
James Morizio
15
CMOS Inverter A
VDD
Y
0 1
OFF
0
A=1
Y=0
ON A
Y
GND EE 261
James Morizio
16
CMOS Inverter A
Y
0
1
1
0
VDD ON A=0
Y=1
OFF A
Y
GND EE 261
James Morizio
17
CMOS NAND Gate A
B
0
0
0
1
1
0
1
1
EE 261
Y
Y A B
James Morizio
18
CMOS NAND Gate A
B
Y
0
0
1
0
1
1
0
1
1
EE 261
ON A=0 B=0
James Morizio
ON Y=1 OFF OFF
19
CMOS NAND Gate A
B
Y
0
0
1
0
1
1
1
0
1
1
EE 261
OFF A=0 B=1
James Morizio
ON Y=1 OFF ON
20
CMOS NAND Gate A
B
Y
0
0
1
0
1
1
1
0
1
1
1
EE 261
ON A=1 B=0
James Morizio
OFF Y=1 ON OFF
21
CMOS NAND Gate A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
EE 261
OFF A=1 B=1
James Morizio
OFF Y=0 ON ON
22
CMOS NOR Gate A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
EE 261
A B Y
James Morizio
23
CMOS Logic Gates-2 VDD
2-input NOR
a Pull-up tree
b
z a
b Gnd
Pull-down truth table a b z
Pull-up truth table a b z
0 0 Z 0 1 0
0 0 1 0 1 Z
1 0 0 1 1 0
1 0 Z 1 1 Z
Pull-down tree
• There is always (for all input combinations) a path from either 1 or 0 to the output • No direct path from 1 to 0 (low power dissipation) • Fully restored logic • No ratio-ing is necessary (ratio-less logic) • Generalize to n-input NAND and n-input NOR? EE 261
James Morizio
NOR truth table a b z 0 0 1 0 1 0 1 0 0 1 1 0
24
3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0
EE 261
James Morizio
25
3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0
Y A B C
EE 261
James Morizio
26
CMOS Compound (Complex) Gates-1 V DD
a
c
b
d z
a
• What function is implemented by this circuit?
b c
d Gnd
EE 261
James Morizio
27
Compound Gates-2 VDD
How to implement F = ab + bc + ca? a
b
c
b
• F = ab + bc + ca
VDD
a
c F
a
c
a
b
b
c
F
Gnd
Gnd EE 261
James Morizio
28
And-Or-Invert (AOI) Gates a b c d e
Pull-up network F F
f g h
a
d
f
b
e
g
c
h Gnd
EE 261
James Morizio
29
Or-And-Invert (OAI) Gate Pull-up network
a b c d e
F F
c
b
a
f g h e
d
f
g
h
Gnd • Generally, complex CMOS gates can be derived directly from maxterms of the function (as in a Karnaugh map) EE 261
James Morizio
30
Transmission Gates • Pass transistors produce degraded outputs • Transmission gates pass both 0 and 1 well
EE 261
James Morizio
31
Transmission Gates • Pass transistors produce degraded outputs • Transmission gates pass both 0 and 1 well Input g a
b gb
a
b gb
EE 261
g = 0, gb = 1 a b
g = 1, gb = 0 0 strong 0
g = 1, gb = 0 a b
g = 1, gb = 0 strong 1 1
g
g a
g b
gb
Output
a
b gb
James Morizio
32
Tristates • Tristate buffer produces Z when not enabled EN
EN 0 0 1 1
A 0 1 0 1
Y Y
A
EN Y
A EN
EE 261
James Morizio
33
Tristates • Tristate buffer produces Z when not enabled EN
EN 0 0 1 1
A 0 1 0 1
Y Z Z 0 1
Y
A
EN Y
A EN
EE 261
James Morizio
34
Nonrestoring Tristate • Transmission gate acts as tristate buffer – Only two transistors – But nonrestoring • Noise on A is passed on to Y
EN A
Y EN
EE 261
James Morizio
35
Tristate Inverter • Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A EN Y EN
EE 261
James Morizio
36
Tristate Inverter • Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A
A
A EN Y
Y
Y
EN = 0 Y = 'Z'
EN = 1 Y=A
EN
EE 261
James Morizio
37
Multiplexers • 2:1 multiplexer chooses between two inputs S S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
X
EE 261
Y
D0
0 Y
D1
James Morizio
1
38
Multiplexers • 2:1 multiplexer chooses between two inputs S S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
EE 261
D0
0 Y
D1
James Morizio
1
39
Gate-Level Mux Design Y = SD1 + SD0 (too many transistors)
• How many transistors are needed?
EE 261
James Morizio
40
Gate-Level Mux Design Y = SD1 + SD0 (too many transistors)
• How many transistors are needed? 20 D1 S D0
D1 S D0 EE 261
Y
4
2 4
2
4
2
Y
2
James Morizio
41
Transmission Gate Mux • Nonrestoring mux uses two transmission gates
EE 261
James Morizio
42
Transmission Gate Mux • Nonrestoring mux uses two transmission gates
S
– Only 4 transistors
D0 Y
S D1 S EE 261
James Morizio
43
Inverting Mux • Inverting multiplexer – Use compound AOI22 – Or pair of tristate inverters – Essentially the same thing
• Noninverting multiplexer adds an inverter D0 S
S D1
D0
D1
S
S
Y S
S
S Y
S
D0
Y
S D1
EE 261
James Morizio
0 1
44
4:1 Multiplexer • 4:1 mux chooses one of 4 inputs using two selects
EE 261
James Morizio
45
4:1 Multiplexer • 4:1 mux chooses one of 4 inputs using two selects – Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
– Or four tristates D0 S0 D0
0
D1
1
S1 D1 0 Y
Y D2
0
D3
1
1 D2
D3
EE 261
James Morizio
46
CMOS Exclusive-Nor Gate TG1
a
• 8-transistor implementation F=a
b
b
TG2 a
b
0 0 0 1 1 0 1 1
TG1
TG2
F
nonconducting conducting B (1) nonconducting conducting B (0) conducting nonconducting B (0) conducting nonconducting B (1)
• Better, 6-transistor implementation is possible! EE 261
James Morizio
47
D Latch • When CLK = 1, latch is transparent – D flows through to Q like a buffer
• When CLK = 0, the latch is opaque – Q holds its old value independent of D
• a.k.a. transparent latch or level-sensitive latch CLK D
EE 261
h c t a L
CLK D
Q Q
James Morizio
48
D Latch Design • Multiplexer chooses D or old Q CLK D
1
CLK
Q Q
Q
D
Q
0 CLK
CLK
CLK
EE 261
James Morizio
49
D Latch Operation Q D
CLK = 1
Q
Q D
Q
CLK = 0
CLK D Q EE 261
James Morizio
50
D Flip-flop • When CLK rises, D is copied to Q • At all other times, Q holds its value • a.k.a. positive edge-triggered flip-flop, masterslave flip-flop CLK
CLK D
D
EE 261
p o l F
Q Q
James Morizio
51
D Flip-flop Design • Built from master and slave D latches CLK
CLK CLK CLK
D
h c t a L
EE 261
QM
D CLK
QM
h c t a L
CLK
Q CLK
CLK
Q CLK
James Morizio
CLK
52
D Flip-flop Operation D
QM
Q
CLK = 0
D
QM
Q
CLK = 1
CLK D Q
EE 261
James Morizio
53
Race Condition • Back-to-back flops can malfunction from clock skew – Second flip-flop fires late – Sees first flip-flop change and captures its result – Called hold-time failure or race condition CLK1 CLK1 D
EE 261
p o l F
CLK2 Q1
p o l F
CLK2 Q2
Q1 Q2
James Morizio
54
Nonoverlapping Clocks • Nonoverlapping clocks can prevent races – As long as nonoverlap exceeds clock skew
• We will use them in this class for safe design – Industry manages skew more carefully instead φ2
φ1
QM
D φ2
φ2
φ2
Q φ1
φ1
φ1
φ1 φ2
EE 261
James Morizio
55
Design Representation Levels • Design domains
Gajski and Kuhn’s Y-chart (layered like an onion)
– Behavioral – Structural – Physical
Structural
Behavioral
Algorithms Boolean equations Differential equations
Processor Gates Transistors Polygons Cells
• Hardware description languages commonly used at behavioral level, e.g. VHDL, Verilog
Chip Physical (geometric)
• Example: Consider the carry function co = ab + bc + cia EE 261
James Morizio
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Verilog Example (Behavioral) Boolean equation form:
Boolean truth table form:
module carry (co, a, b, c i); output co; input a, b, ci; assign co = (a & b) | (a & c i) | (b & ci); end module
Timing information: module carry (co, a, b, ci); output co; input a, b, ci; Wire #10 co = (a & b) | (a & ci) | (b & ci); end module
primitive carry (co, a, b, ci); output co; input a, b, ci; table // a b c co 1 1 ? : 1; 1 ? 1 : 1; ? 1 1 : 1; 0 0 ? : 0; 0 ? 0 : 0; ? 0 0 : 0; end table end module
co changes 10 time units after a, b, or c changes EE 261
James Morizio
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