Class D amp

Project Number: JKM-2A03

Class-D Audio Amplifier A Major Qualifying Report: submitted to the Faculty of the WORCESTER POLYTECHNIC INSTITUTE in partial fulfillment of the requirements for the Degree of Bachelor of Science

by ______________________________________________ Alex C. DiDonato ______________________________________________ Ryan T. Dupuis ______________________________________________ Tyler W. Folsom

Date: April 29, 2004 Approved:

__________________________________________ __________________________________________ Professor John McNeill Professor Demetrios Papageorgiou Project Advisor Project Advisor

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ABSTRACT This MQP involved the design, construction, and testing of an Ultra-Efficient, High-Powered, Class-D audio amplifier. The main goal was to achieve 95% efficiency using the 42 Volt PowerNet Standard. The signal processing stage was completed using a three-level Sigma-Delta Modulation scheme which powered a MOSFET H-Bridge configuration. Testing confirmed that the goal of 95% efficiency was met, and an RMS power of 400 Watts was produced using a 42 Volt supply.

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Acknowledgements We would first like to thank Analog Devices, Texas Instruments, and Allegro Microsystems for sponsoring the Analog MQP lab. Without their continued support, the resources needed to fund this project would not have been available. We would also like to thank all the companies that were willing to donate free samples for us to perform testing in lab.

These companies included Fairchild Semiconductor, Texas Instruments,

Intersil, and Analog Devices. A huge thank you goes out to Tom Angelotti for all his patience and willingness to help us when we needed anything from the shop. The most thanks goes out to our MQP advisors Professor McNeill and Professor Papageorgiou for all their guidance and support throughout the year. Without their willingness to always bestow their knowledge and help when in dire need, our MQP would not have been a success.

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TABLE OF CONTENTS ABSTRACT ............................................................................................................................................................................... 2 ACKNOWLEDGEMENTS ...................................................................................................................................................... 3 TABLE OF FIGURES .............................................................................................................................................................. 5 EXECUTIVE SUMMARY ....................................................................................................................................................... 7 1

INTRODUCTION............................................................................................................................................................ 9

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BACKGROUND ............................................................................................................................................................ 10 2.1 WHAT IS CLASS-D...................................................................................................................................................10 2.2 METHODS OF ACHIEVING CLASS-D.........................................................................................................................12 2.2.1 Pulse Width Modulation ....................................................................................................................................12 2.2.2 Sigma-Delta Modulation....................................................................................................................................15 2.2.3 Digital Signal Processing ..................................................................................................................................18 2.2.3.1

2.3 2.4 2.5 2.5.1 2.5.2 2.6 2.7 2.8 3

DESIGN .......................................................................................................................................................................... 43 3.1 3.2 3.3 3.4 3.5 3.6

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SIGMA DELTA MODULATION...................................................................................................................................43 POWER STAGE .........................................................................................................................................................48 SYSTEM STABILITY .................................................................................................................................................50 FILTER .....................................................................................................................................................................53 HEAT SINK ...............................................................................................................................................................57 PRINTED CIRCUIT BOARD ........................................................................................................................................59

PROJECT EVOLUTION.............................................................................................................................................. 62 4.1 4.2 4.3 4.4

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S/PDIF ....................................................................................................................................................................... 19

POWERNET 42V STANDARD ....................................................................................................................................22 POWER MOSFETS ..................................................................................................................................................25 POTENTIAL CONCERNS ............................................................................................................................................28 Filtering .............................................................................................................................................................28 Electromagnetic Interference (EMI) ..................................................................................................................32 EFFICIENCY .............................................................................................................................................................35 CONTROLS THEORY.................................................................................................................................................39 TEST MEASUREMENT METHODOLOGY ....................................................................................................................41

FIRST PCB...............................................................................................................................................................62 SECOND PCB...........................................................................................................................................................63 THIRD PCB..............................................................................................................................................................65 FOURTH PCB...........................................................................................................................................................67

TESTING AND RESULTS ........................................................................................................................................... 68 5.1 5.2 5.3 5.4 5.5 5.6

EFFICIENCY TESTING ...............................................................................................................................................68 “DEAD-ZONE”.........................................................................................................................................................71 ACOUSTIC CLARITY.................................................................................................................................................75 OUTPUT POWER.......................................................................................................................................................76 SIGNAL TO NOISE RATIO .........................................................................................................................................78 EFFICIENCY LOSS ....................................................................................................................................................80

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RECOMMENDATIONS............................................................................................................................................... 88

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CONCLUSIONS ............................................................................................................................................................ 90

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REFERENCES............................................................................................................................................................... 91

APPENDIX .............................................................................................................................................................................. 92

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Table of Figures Figure 1: Class-D explanation without modulation or brightness reduction ............................................ 10 Figure 2: Class-D explanation with resistor added to reduce brightness.................................................. 11 Figure 3: Switch Open .............................................................................................................................. 11 Figure 4: Switch Closed............................................................................................................................ 11 Figure 5: Input Sine Wave vs. PWM Output............................................................................................ 13 Figure 6: Two-Level vs. Three-Level PWM ............................................................................................ 14 Figure 7: PWM Comparator ..................................................................................................................... 15 Figure 8: Delta Modulation and Demodulation ........................................................................................ 16 Figure 9: Block Diagram of Sigma-Delta (Σ-∆) Modulation ................................................................... 17 Figure 10: DSP Block Diagram ................................................................................................................ 19 Figure 11: Biphase-Mark-Code Example ................................................................................................. 21 Figure 12: Maximum Over-voltage .......................................................................................................... 23 Figure 13: Maximum Dynamic Voltage ................................................................................................... 24 Figure 14: Starting Voltage....................................................................................................................... 25 Figure 15: H-Bridge.................................................................................................................................. 27 Figure 16: Typical Low-Pass Filter .......................................................................................................... 29 Figure 17: H-Bridge Output Low-Pass Filter ........................................................................................... 30 Figure 18: Bode Plot for 1 Ohm Load ...................................................................................................... 30 Figure 19: Bode Plot for 2 Ohm Load ...................................................................................................... 31 Figure 20: Bode Plot for 4 Ohm Load ...................................................................................................... 31 Figure 21: Bode Plot for 8 Ohm Load ...................................................................................................... 31 Figure 22: Braided Speaker Wire Example .............................................................................................. 33 Figure 23: EMI Interference ..................................................................................................................... 33 Figure 24: Basic level circuit model ......................................................................................................... 36 Figure 25: Current paths through the H-bridge......................................................................................... 37 Figure 26: MOSFET Switching Losses .................................................................................................... 38 Figure 27: Block Diagram ........................................................................................................................ 40 Figure 28: Duty Cycle............................................................................................................................... 41 Figure 29: Testing Diagram ...................................................................................................................... 41 Figure 30: Basic Sigma-Delta Modulation ............................................................................................... 43 Figure 31: Noise Spectrum ....................................................................................................................... 44 Figure 32: Three-Level Sigma-Delta Modulation .................................................................................... 44 Figure 33: Integrator ................................................................................................................................. 45 Figure 34: Quantizers................................................................................................................................ 47 Figure 35: Three-Level Switching ............................................................................................................ 47 Figure 36: Feedback Attenuation.............................................................................................................. 48 Figure 37: Three possible MOSFET configurations................................................................................. 49 Figure 38: Graphical Bode Plot Method................................................................................................... 52 Figure 39: Bode Plot ................................................................................................................................. 52 Figure 40: H-Bridge Filter Configuration................................................................................................. 54 Figure 41: H-Bridge Filter Half Representation ....................................................................................... 55 Figure 42: H-Bridge Filter Design Configuration .................................................................................... 56 Figure 43: H-Bridge Filter Configuration................................................................................................. 57 Figure 44: Heat sink used for testing ........................................................................................................ 58

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Figure 45: Heat sink shown with supports................................................................................................ 58 Figure 46: Placement of MOSFETs for Heat Sink ................................................................................... 60 Figure 47: Two Separate Sections of Board Layout................................................................................. 61 Figure 48: Original PCB ........................................................................................................................... 63 Figure 49: Second PCB Ground Plane (Top) ........................................................................................... 65 Figure 50: Second PCB 42V Power Plane (Bottom) ................................................................................ 65 Figure 51: Third PCB Ground Plane (Top) .............................................................................................. 66 Figure 52: Third PCB 42V Power Plane (Bottom)................................................................................... 66 Figure 53: Third PCB Fully Populated ..................................................................................................... 67 Figure 54: Oscilloscope Snapshot............................................................................................................. 69 Figure 55: Efficiency vs. Clock Speed ..................................................................................................... 70 Figure 56: Ideal Integrator Output ............................................................................................................ 72 Figure 57: Vdz = 7.5mV (Too Small), f = 1kHz .................................................................................. 73 Figure 58: Vdz = 150mV (Too Large), 1kHz ....................................................................................... 74 Figure 59: Vdz = 150mV (Too Large), 10kHz ...................................................................................... 74 Figure 60: Vdz = 50mV (Near-Ideal Value), f = 1kHz ........................................................................... 75 Figure 61: Vdz = 50mV (Near-Ideal Value), f = 10kHz ......................................................................... 75 Figure 62: Speaker Test ............................................................................................................................ 76 Figure 63: Input vs. Output....................................................................................................................... 77 Figure 64: FFT used to obtain SNR.......................................................................................................... 79 Figure 65: Power Loss .............................................................................................................................. 81 Figure 66: Actual vs. Ideal 0.01uF Capacitor Impedance ........................................................................ 83 Figure 67: Power Loss vs. Dissipation Factor .......................................................................................... 84 Figure 68: Power Loss vs. Switching Frequency...................................................................................... 84 Figure 69: Efficiency vs. Switching Speed............................................................................................... 85 Figure 70: Efficiency vs. Clock Speed ..................................................................................................... 86

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Executive Summary Completing a project in the Analog Lab at WPI involves an enormous amount of growth, maturity and perseverance. The time invested and the struggles that we overcame left us with a sense of self-satisfaction and a broader knowledge that can be used in future endeavors. It is because of projects like this, that WPI is such a highly touted academic institution. The MQP was a wonderful hands-on experience that one can only achieve by participating in a project of this nature. This project, sponsored by Analog Device, Texas Instruments, and Allegro was to design a Class-D Audio Amplifier with an efficiency of at least 90%. For us, this project meant more than just exceeding the goals of previous MQP groups that have tackled similar projects. It meant exploring a larger scope of what could and will be done with Class-D design in the near future. Many topics were researched, such as how to implement the signal processing of the amplifier, which covered Pulse-Width Modulation, Sigma-Delta Modulation, and Digital Signal Processing. After an immense amount of research, Sigma-Delta Modulation was decided upon to carry out the signal processing due to various advantages it brought to the design. Also researched were electrical systems that would be incorporated into future automobiles that would ultimately revolutionize the design of Class-D amplifiers. Future luxury cars are predicted to consume 5,000 Watts of power requiring the evolution of the 42 Volt PowerNet Standard. This project would therefore be designed around the new standard allowing for greater power potential. These new concepts ultimately changed the goal of the project to design a Class-D amplifier capable of 95% efficiency. With such a small window for power loss, more research was spent investigating the leading causes of power loss in Class-D amplifiers. After an extensive study, we decided to implement a three-level modulation scheme that would allow for better efficiency than a twolevel design. We also discovered that the MOSFET selection and the filter components would be a critical choice in our amplifier design. The current that passes through the load passes through the MOSFETs and the inductors of the filter as well. This makes it extremely important to find components with a minimal DC on resistance to minimize voltage drops across these elements. In order to achieve a three-level modulation scheme, it was necessary to alter the typical scheme of Sigma-Delta Modulation. Instead of having one signal to control the output, there would be four signals controlling the output. These signals are the cornerstone for the three-level modulation. The reason that three-level was chosen over two-level was to maximize efficiency. The reason that it is able to do so is because with a three-level signal, you have the ability to control the load with either a 7

positive state, a negative state, or a neutral state. During the positive state, current is drawn through the load in one direction, during the negative state, current is drawn through the load in the opposite direction, and during the neutral state, current is not required to flow from the supply. Instead, both terminals across the load are grounded, causing any residual current to exit through the ground plane. The configuration that we used for the MOSFETs was a standard H-Bridge.

This is the

configuration used in most Class-D amplifiers on the market. To add more safety into the design, we used a driver chip to drive the MOSFETs. We did this because it had built in logic protection preventing a short from the power plane to ground. The driver chip could also drive the MOSFET gates with up to 1 Amp of current. This would allow the MOSFETs to turn on and off faster than without the use of a driver chip. These faster switching speeds would result in greater efficiency. After the MOSFET stage of our amplifier, the signal had to pass through one more block before it could reach the load. This last block was the filter. In our filter design, we used an inductor and a capacitor to create a low-pass filter. The low-pass filter was necessary to reduce the amount of electromagnetic interference that would radiate out of the amplifier without it. It was also necessary to transform the digital logic stream back into an analog signal that more closely represents the input signal. The filter was created with two separate cut-off frequencies at both 14 kHz and 37 kHz. The reasoning behind separating the poles was to maintain stability throughout the amplifier. When the design of the amplifier had taken shape and was ready to be tested, we ordered a printed circuit board to limit the inductive and capacitive effects found in typical breadboards. The design of the printed circuit board was done in a program called Ultiboard 2001. This program gave us the freedom to design the board in any matter that we saw fit. The end result was a professional looking populated printed circuit board that avoided the side effects of a breadboard. In the end, we were happy to report that the amplifier we designed and built was a success. The output power of the final product met its goal of being high powered with a measured output of 400 Watts RMS. The efficiency goal of the amplifier was also met reaching 95% efficiency with a fully clipped input signal. The total footprint size of the amplifier measured to be only 29 square inches. This produced a power to size ratio greater than many other amplifiers found on the market today. With the completion of our project, we like to think that we are paving the way for future designs of Class-D amplifiers utilizing the 42 Volt PowerNet Standard.

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1 Introduction Currently there are many Class-D amplifiers on the market for car audio applications. The conventional Class-D amplifier has several drawbacks: most have only 85% efficiency, they typically are used as subwoofer amplifiers, and are generally lower quality than conventional Class-A or ClassAB amplifiers. Imagine now, an amplifier with both the advantages of the Class-AB and Class-D amplifiers combined. This combination would provide an amplifier that is smaller in size with higher efficiency, very low distortion, and lower cost. The goal of this project is to create a Class-D, car-audio amplifier with an efficiency of at least 95%. The overall scheme of the project will be to foresee the future of car audio amplifiers assuming the adoption of the new 42 Volt PowerNet standard. The footprint size of the amplifier will be reduced dramatically due to the fact that the power supply of the amplifier will be eliminated from the design. This allows the amplifier to produce the same amount of power as other Class-D amplifiers with twice the footprint size. Similar to all Class-AB amplifiers, this amplifier will have a goal of running full audible bandwidth (20 to 20 kHz). Unlike present amplifiers on the market, this Class-D amplifier will not use Pulse-Width Modulation (PWM). Instead, Sigma-Delta Modulation will be used to drive the MOSFET switching stage by means of discrete components. The method of creating a Sigma-Delta modulated signal ensures a high level of efficiency which utilizes feedback to create a clean output signal.

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2 Background This section is included to provide the necessary background information and design concepts to build a Class-D amplifier. The topics include a brief overview of what Class-D really is and methods of creating a Class-D amplifier. The subsequent topics include relevant information on the PowerNet 42 Volt Standard, Power MOSFETs, Filtering, Efficiency, and Controls Theory.

2.1 What is Class-D Before this report goes into detail on how to construct a Class-D amplifier, it is important to discuss the theory behind a Class-D amplifier. One way to explain and show the relevance of a Class-D amplifier is to start a discussion about the simple circuit shown in Figure 1. Here, we have a 12 Volt battery connected to nothing but a light bulb. Since this bulb has a resistance of 1Ω, using the formula V = I ∗ R , the current through this bulb equals 12 Amps. Also by using the power formula, P = V ∗ I ,

it can be found that the power dissipated by the light bulb is 144 Watts.

Figure 1: Class-D explanation without modulation or brightness reduction

Now if it was determined that this particular light bulb was running much brighter than intended, we would need to decrease the power that the light bulb dissipates. The simplest solution to fix this problem would be to implement a resistor in series with the light bulb. This would decrease the voltage across the light bulb, resulting in less current flow through it. For simplicity of explanation, we’ll add a resistor to the circuit of the same resistance, 1Ω. This can bee seen in Figure 2.

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Figure 2: Class-D explanation with resistor added to reduce brightness

Notice that now when we calculate the current, we see that the voltage across the light bulb has dropped from the full 12 Volts down to 6 Volts. What this means is that there is now only 6 Amps running through the bulb, which reduces the power the light bulb dissipates, and in effect, the brightness. Now this light bulb is emitting 36 Watts of power instead of the original 144 Watts which is what we wanted. The problem however is that the resistor is also consuming 36 Watts of power, which is being released in the form of heat, which is detrimental to achieving high efficiency. If only there was a way to decrease the power consumption of the light bulb to reduce the brightness while conserving energy at the same time. It turns out that adding a switch to the circuit instead of a resistor achieves this goal. Please take a look at Figure 3 & Figure 4 below.

Figure 3: Switch Open

Figure 4: Switch Closed

Notice that when the switch is in the open position, there is no current flowing through the light bulb, resulting in the light bulb being off. However, when the switch is in the closed position the current is back to the original 12 Amps resulting in the light bulb being on again. In order for the light bulb to be dimmer than it was originally, but still remain on for the entire duration, the controlling switch would have to be switched very rapidly between “off” and “on.” If this happens, the bulb appears to remain on for the entire duration, illuminated at approximately half of its full capable brightness. Energy is

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conserved in this situation in the respect that a resistor is not absorbing half the power. Assuming the switch is lossless, an efficiency of 100% would be reached. If we calculate the power of these three circuits, we can see that in the first circuit we have 144 watts of power being dissipated by the light bulb. This is running at 100% efficiency, but we want the light bulb to be much dimmer. In the circuit we have the resistor and the light bulb which both dissipate 36 Watts of power. The 36 Watts of power dissipated by the resistor, in the form of heat, is actually wasted since it does not become dissipated by the light bulb. In this circuit we have 50% efficiency since the light bulb gets only 50% of the total power in the circuit. In the last circuit the light bulb averaged 72 watts of power due to the fact that it received 6 Volts across it on average, but at the full 12 Amps of current. In this circuit there is no wasted energy as there was in the resistor circuit, therefore there is no power loss due to non-bulb elements. Again we see the potential for 100% efficiency in this circuit while the bulb is running at 50% brightness, which was our goal. This example briefly explains and shows the relevance behind a Class-D amplifier. Even though the example has nothing to do with music or sound, it is intuitive that by implementing switching into a circuit, there are endless possibilities to what one may control. This leads into a few possible techniques to control the switching of various devices, comparing both advantages and disadvantages of each scheme.

2.2 Methods of Achieving Class-D While there are many possible ways of designing a Class-D amplifier, we focused on three different methods that were studied and analyzed to determine which method we thought would be most appropriate for our project. Those three methods that we investigated were Pulse Width Modulation, Sigma-Delta Modulation, and Digital Signal Processing.

2.2.1 Pulse Width Modulation PWM is what makes a Class-D amplifier digital, or at least quasi-digital. Instead of an amplifier using a sine wave throughout its amplification process, it uses a series of square waves in which the duty

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cycles vary according to the input signal. As an input signal approaches its upper limits, the duration of the pulses increase. The average of all the varying width pulses is equivalent to the original input. The Class-D amplifier utilizes an H-bridge to convert the PWM square-wave to an acoustic wave that ultimately drives the speakers at the output stage. Figure 5 depicts a PWM signal.

Figure 5: Input Sine Wave vs. PWM Output

The red line in Figure 5 is the input sine wave that was needed to generate the PWM signal. Notice when the sinusoidal waveform reaches its peaks, the pulse width remains wider versus when the sinusoidal waveform approaches zero volts, the pulse widths get smaller. Class-D amplifiers typically use two-level rather than three-level PWM to control the switching of the H-bridge circuit. Two-level PWM contains two possible output levels, high and low. Three-level PWM contains three possible output levels, positive, negative, and zero. difference between the two PWM methods.

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Figure 6 illustrates the

Figure 6: Two-Level vs. Three-Level PWM

Three-level PWM is more beneficial because it increases the efficiency of the H-bridge circuit. To prove this, we must look at the input when it is zero volts. The two-level’s duty cycle will be 50% because the MOSFETs will be switching on and off equally. The three-level’s duty cycle will be zero because there is no need to draw current through the load. This conserves energy by minimizing MOSFET switching, increasing the efficiency. In today’s standard Class-D amplifier, the PWM signal is created by a comparator.

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comparator’s job is simply to compare the audio signal to a reference signal, typically a triangle wave. When the audio signal’s amplitude is larger than the reference signal’s amplitude the resulting PWM signal is high. The longer the audio signal’s amplitude remains larger than the reference signal’s amplitude, the longer the PWM will remain high. In the case when the audio signal changes polarity, the terminals on the comparator circuit become switched. The analog input goes to the inverting terminal and the reference signal goes to the non-inverting terminal.

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Figure 7: PWM Comparator

To achieve a proper PWM signal that will represent an analog input, the reference signal amplitude must be larger than the maximum input amplitude. Another important factor of the reference signal is the operating frequency or clock speed of that waveform. The operating frequency must be faster than the audio signal to assure an accurate sampling rate.1 The faster the clock speed of the reference signal, the closer the output will represent the input. A drawback is more Electromagnetic Interference (EMI) will be radiated from the circuit which will be talked about later. The advantage of an extremely high clock speed, 1MHz and up, is full audible bandwidth capabilities of the amplifier, 20 to 20 kHz. As of 2003, the Xtant 1.1i was the only Class D amplifier on the market with this capability.2 For the purposes of this project, a comparator will not be used to create a square wave signal in the manner just discussed. A Sigma-Delta modulated signal (SDM) will be used as opposed to a PWM signal. The SDM will be created using discrete components that accept an analog input. The analog input will be a standard 1.4 Volt peak.

2.2.2 Sigma-Delta Modulation To understand Sigma-Delta Modulation it is important to first understand how it originated. Before Sigma-Delta Modulation there was delta modulation. “Delta modulation is based on quantizing the change in the signal from sample to sample rather than the absolute value of the signal at each sample.”3 Figure 8 shows the block diagram of the delta modulator and demodulator.

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Figure 8: Delta Modulation and Demodulation3

Notice how the output of the integrator in the feedback loop of Figure 8(a) tries to predict the input x(t ) . This signifies that the integrator works as a predictor and the equation x(t ) − x(t ) is the prediction error term. The prediction error term in each current prediction is quantized and is used in the subsequent prediction. The quantized prediction error (delta modulation output) is integrated in the receiver just as it is in the feedback loop. Finally, the predicted signal is smoothed out with a low-pass filter and produces the channel output.3 It is important to mention that delta modulators exhibit slope-overload for rapidly rising input signals. Slope-overload happens because the output takes a long time to catch up and follow the input. Thus, delta modulators performance is dependent on the frequency of the input signal. On the reverse end, granular noise can also be a problem when implanting SDM. Granular noise occurs when the step size is too large and causes excessive quantization noise when the input changes slowly. The step size is explained in much greater detail later in the report. 16

Integration, a linear operation, allows the two integrators in delta modulation to be combined into one without altering the input/output characteristics. Figure 9 shows the Sigma-Delta (Σ-∆) Modulator.

Figure 9: Block Diagram of Sigma-Delta (Σ-∆) Modulation3

Sigma-Delta Modulation is a smoothed out version of delta modulation, which is why it was chosen for this project. Both delta modulation and Sigma-Delta Modulation use a simple quantizer (comparator) but only in Sigma-Delta Modulation does this comparator encode the integral of the signal itself. The performance of this system is insensitive to the rate of change of the signal. Later in this report, these noise-shaping properties will be discussed in more detail and will show why Sigma-Delta Modulation is “well suited to signal processing applications such as digital audio and communications.”3 Sigma-Delta Modulation and Pulse-Width Modulation are similar and are applicable in the same topologies. Both SDM and PWM quantize the signal of interest directly. The product of the encoded waveforms when filtered can be represented in both cases by the ratio of the time the signal spends in the high position to the time it spends in the low position over a given time. The only difference is the time the two use to modulate the signal. The PWM signals are averaged over one switching cycle where 17

SDM are averaged over several cycles.

Due to the modulation strategy for SDM, the switching

frequency is “hidden” and less harmonic energy is contained at lower frequencies.3 The frequency is “hidden” due to the MOSFETs not switching every cycle of the clock. With PWM, switching occurs at every instance of the reference signal. This results in a more spread out spectral density for SDM. When comparing these two methods, the fact that SDM has a more spread out spectral density really separates it apart from PWM. PWM uses only one switching cycle, which will have a tendency for its power spectrum to be concentrated about the switching frequency and its harmonics, which give rise to harmonic spikes. These spikes can produce many drawbacks for PWM with unwanted effects such as acoustic noise, torque ripple, and electromagnetic interference. One case where the drawbacks of SDM exceed those of PWM is at low modulation indices. With first order SDM, spectral spikes will degrade the performance unless a dither is added. Dither will help reduce the spikes and open the door for SDM.

2.2.3 Digital Signal Processing For this project we explored implementing a digital DSP chip as the brains of the operation. We found that an Analog Devices chip, the ADSP-21161 SHARC® would be an excellent choice for the signal processing. This chip is extremely versatile and meets all of our specifications. Some of these specifications include an S/PDIF (Sony Philips Digital Interface) input, the capability of controlling the level of accuracy needed to generate a Sigma-Delta Modulated signal, and an analog input for a controlled feedback loop. The arrangement below shows an example of what the block diagram for the DSP chip would look like.

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Figure 10: DSP Block Diagram

The main function of the DSP chip would be to process the audio input and create an equivalent square wave output to drive the H-bridge. The DSP chip would utilize the new S/PDIF input for signal processing and regulate both the output voltage level from fluctuating, due to the automobile’s power consumption and excessive charging voltage, and minimize the level of total harmonic distortion in the final audio signal with analog feedback. More information about the benefits of feedback can be found in the Controls Theory section of this report. In the subsequent paragraphs, a deeper understanding of the S/PDIF input will be explored.

2.2.3.1 S/PDIF Sony Philips Digital Interface (S\PSIF) format, also known as TOSlink, is a standard that is specified in the compact disc “red book”. “The ‘red book’ describes in detail the workings of digital audio transmission, storage and replay within a compact disc digital audio environment.”4 S/PDIF is sent over coaxial cable, and TOSLink (Toshiba) is sent over fiber optic cable, but they are otherwise identical. “Many audiophiles and industry professionals feel that the S/PDIF protocol allows for better sound quality than TOSlink.”4 S/PDIF is used on DAT, Minidisc, and CD hardware.

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The S/PDIF (IEC-958) is a 'consumer' version of the AES/EBU-professional interface. Below is table that shows the differences between S/PDIF and AES/EBU.

Table 1: AES/EBU vs. S/PDIF5

There are two distinct parts that make up an S/PDIF signal: data protocol and hardware interface. The data protocol is universal across all S/PDIF devices. Sampling rates and resolutions between 16 and 24 bits can be supported as well as up to 4 channels. The hardware interface is what has already been mentioned and that is how to send S/PDIF data. The next table illustrates other important details about the Standard IEC958 "Digital audio interface" from EBU (European Broadcasting Union).

Table 2: EBU Details Pertaining to Digital Audio Input5

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Some key points in this table are the sampling frequencies and control information about the inputs. These are necessary points that allow signal processing to be carried out. The signal on the digital output of any device looks like an almost perfect sine-wave, with amplitude of 500 mVolts and a frequency of almost 3 MHz. Each sample contains two 32-bit words that are transmitted which result in a bit-rate of 2.8224 Mbit/s at a 44.1 kHz sampling rate for CD and DAT.5 The S/PDIF signal is coded using the 'biphase-mark-code' (BMC), which is a kind of phasemodulation. What this means is that if two zero-crossings exist, the signal records a logical 1 and if there is one zero-crossing, a logical 0 will be recorded. Figure 11 shows an example of BMC.

Figure 11: Biphase-Mark-Code Example5

In the figure above, the clock frequency is twice the bit rate. It can be easily seen that each bit of the data signal is represented by two logical states for a cell. The length of a cell is knows as a “time slot” which is also equal to the length of a data bit. BMC uses two-level modulation where the logical level at the start of a bit is always inverted to the level at the end of the previous bit. This is as far as we got with S/PDIF as we chose to use an analog input to our Sigma-Delta Modulation .

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2.3 PowerNet 42V Standard In the very near future, we will see a change in the technology incorporated into all of our automobiles. For instance, many systems that have been operated by mechanical or hydraulic power such as brakes, valves, and steering will be replaced by electrically driven devices. As soon as 2005 some luxury cars are expected to implement these electronic devices. Other electronically driven devices are expected to replace complex transmissions, engine power management control system processors, infinitely variable cabin climate control systems, etc. It is clearly visible that the standard 12 Volt battery, which was adopted in the 1920s, will soon be obsolete due to its inability to support the expected 5,000 Watts of power for the future average-sized car. Today’s cars rarely consume greater than 1,500 Watts. The 42 Volt system called “PowerNet” was first conceptualized in 1996 and is currently seeking standardization. It was introduced in FAKRA (DIN Standards Committee for Road Vehicles) and VDA (Association of German Automotive Industry) in November 1996.6 In 1997 both associations agreed upon its standardization and are currently working out a draft acceptable by DIN and ISO. Currently the Working Group “Standardization“(WGS) has 19 members participating including:

• • • • • • • •

FAKRA DaimlerChrysler BMW VW Hella Varta TÜV Automotive Süddeutschland Infineon

• • • • • • • •

Siemens AT AMP Valeo Bosch Delphi Sican Renault PSA.

The transition to a 42 Volt standard from 12 Volt is something that will occur over time. Companies such as DaimlerChrysler and BMW are pioneering 14/42 Volt dual voltage systems. These

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cars will have the ability to power both 14 Volt and 42 Volt components using two separate circuits. Currently, components such as aftermarket car stereos and other mobile electronics are not ready for this jump. As the 42 Volt system becomes more prevalent, it can be assumed that companies producing devices such as car audio amplifiers will take advantage of this new system. One of the obvious reasons is the greater potential that the 42 Volt system allows over the 12 Volt system. A primary concern of the 42 Volt standard is limiting the maximum allowed voltage produced by the automobile. In the PowerNet, the generator must supply a voltage, UPN, of 42 Volt to the vehicle’s electrical system whereas the maximum static over-voltage is to be no more than 52 Volt including ripple due to load dump protection (LDP) ± 5%. This is shown in Figure 12.

Figure 12: Maximum Over-voltage6

The 48 Volt effective level was determined to be the power recharging voltage of the battery. Therefore, the peak static voltage is not to exceed 52 Volts given an 8 Volt (peak-to-peak) ripple riding on the effective voltage level. Perhaps the most important factors with regards to this project are the maximum and minimum dynamic voltages. The maximum dynamic voltage for the PowerNet is determined to be 58 Volts due to LDP. This is an important parameter when selecting semiconductors that see this unregulated power source. Each of the MOSFETs used in this project are able to withstand this voltage since their 23

breakdown limitation is at least 60 Volts. Figure 13 shows a test waveform of the maximum overshoot voltage.

Figure 13: Maximum Dynamic Voltage6

Another issue that must be considered is the minimum start voltage of the system. The minimum voltage in the PowerNet standard measured at the battery terminals is never to drop below 18 Volts at any point and 21 Volts at startup. This is to provide full functionality of all loads which are relevant for startup and safety, including brakes and engine power management. For an audio amplifier application, it is not necessary for all circuits to be immediately operable.

Often turn-on delay circuits are

implemented in order to minimize current draw to the amplifier at start-up. Figure 14 depicts what the voltage level may look like at the startup of the system; first dropping to its minimum value, then slowly increasing to a nominal 42/48 Volts.

24

Figure 14: Starting Voltage6

Many other factors such as slow decrease and increase of the power supply voltage have also been determined. This limitation is defined, “No undesired functions shall appear when decreasing the operating voltage from max 42 Volts to 0 Volts and increasing it from 0 Volts to max 42 Volts.”6

2.4 Power MOSFETs It was decided to use a completely discrete set of components for the output stage for this amplifier. The selection of the best MOSFET for this application is one of the most important steps in achieving peak efficiency. Each chip is built with a particular purpose in mind. The job was to determine the model that would meet or exceed the demands while remaining within the project’s budget of $1000. The first step in choosing output MOSFETS was figuring the appropriate breakdown voltage or Vss. This was not difficult to calculate since it was known that the rail voltages would be +/-42 Volts plus any additional charging voltage. Today, the automotive 12 Volt standard requires all electronics to be able to run between the operating voltages of 8 Volts to 18 Volts. In the future, the 48 Volt PowerNet standard will demand compliance within a 36 to 52 Volt range.6 However, since voltage

25

spikes are common with automotive alternators, a MOSFET was chosen with no less than 60 Volts for a breakdown voltage. This helped narrow the search significantly. The next step was to enter all other important specifications from each chip’s datasheet onto a spreadsheet for comparison. Specifications that were decided upon were peak drain current (Id), onresistance (Rds), gate charge (Qg), power dissipation (W), rise time (tr), and fall time (tf). From these values it was possible to calculate many important factors such as max switching speed, conduction loss, energy loss due to switching, and power loss. Table 3 below shows the equations that were used to calculate these factors. Derivations for each equation can be found in Appendix A. Appendix A also shows comparison tables and charts that were used in determining which MOSFET to choose for the Hbridge of this amplifier.

MaxSwitchingSpeed =

t rise

Conduction ( DC ) Loss = VRds * I d / 2 = [Watts ]

1 = [ Hz ] + t fall

⎡⎛ 2 Rds C.L. = ⎢⎜⎜ R ⎣⎝ Load + 2 Rds

⎤ ⎞ ⎤ ⎡ Vds ⎟⎟Vds ⎥ * ⎢ ⎥/2 R 2 R + ds ⎦ ⎠ ⎦ ⎣ Load

2

C.L. =

SwitchingP owerLoss (Gate − Source ) = Q g * V gs * f clk = [Watts ]

Vds * 2 Rds

2(RLoad + 2 Rds )

2

1 SwitchingPowerLoss ( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts] 2

Table 3: Table of Equations

Several values remain constant throughout the calculations. Switching will be at an absolute maximum frequency of 2 MHz however this is very unlikely.

Understanding how Sigma-Delta

Modulation works, the MOSFETs are not going to switch at every clock pulse. It would be difficult to compute the actual speed at which the MOSFETs are switching using SDM. This sampling rate is used in high-end processors and can produce THD at or below 0.001% and a signal-to-noise ratio >110dB.7 Switching speeds are not a limiting factor since all MOSFET values considered were into the 5-10 MHz range. Also, it has been decided that a Vgs of 12 Volts will be a sufficient value based on manufacturer’s

26

data in order to minimize DC on-resistance, Rds. All efficiency calculations have been considered at the predetermined load of 4Ω. Conduction loss is the largest factor in determining efficiency for the operating frequency of 2 MHz. Based on calculated results, the Fairchild FDP038AN06A0 seems to be the best MOSFET due to its low Rds and conduction loss. As seen in Appendix A, this MOSFET dissipated a loss of 16.3 Watts/chip with an Rload of 1Ω. Since the H-bridge configuration allows flow of current through two chips at a time we can find the total power loss in the MOSFETs by doubling this value.

Figure 15: H-Bridge

Therefore, the ideal efficiency limited by the output MOSFETs will be 98.14% given by the following equation. Efficiency =

PLoad PTotal

Efficiency =

1718.1W = 98.14% 1750.6W

Further details about efficiency calculations are given in the Efficiency section of this report.

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2.5 Potential Concerns Before this project even began, there were certain issues that we thought might give us trouble in later stages of the project. These items were filtering, and electromagnetic interference. To address these issues, we briefly describe the types of complications we thought each might contribute to the project.

2.5.1 Filtering In the audio industry, the audible bandwidth range is considered to be 20 – 20 kHz. Because of this fact, all frequencies above 20 kHz will be filtered out. Filtering benefits this project in that it reduces the signal range that the speaker would have to play. Energy is wasted in trying to play frequencies higher than the human ear can hear and will result in a loss of energy in the form of heat. Additionally, EMI caused from high frequencies will be kept to a minimum. Without filtering, the Sigma-Delta Modulated signal would remain digital instead of converting back to analog. To ensure the goal of 95% efficiency, it was decided to use a passive filter. A passive filter is able to achieve higher efficiency because it theoretically gives back all the energy that it absorbs. For this project an inductor and capacitor will be used to construct the filter. To determine the values for the two components, the following formulas were used:8

ω

0

= 2π *

f

0

2 ⎛ ⎞ 1 ⎜ ⎟ 2 ⎛ ⎞ 1 = ⎜ω 0 − ⎜ ⎟ ⎟ 2 RC ⎜ RC 2 ⎝ ⎠ ⎟⎠ ⎝

28

ω

0

=

1 LC

From these equations, the capacitor value was calculated to be 1.4 µF and the inductor value was calculated to be 45 µH. These were based on a 4Ω load in a typical low-pass filter configuration as seen below in Figure 16. A 4Ω load was chosen because it matches the typical speaker impedance. This means that if 2 speakers are connected in series yielding an 8Ω load, the amplifier will be capable of playing up to 40 kHz rather than the cut-off frequency of 20 kHz. Conversely, a 2Ω load will only be able to play up to 10 kHz, and a 1Ω load will only be able to play up to 5 kHz. We chose this configuration because when trying to achieve high quality sound, the lower impedances generally lose their quality. This means that a 2Ω or 1Ω load should be reserved for subwoofer applications where the cut-off frequency is not as much of an issue. A typical subwoofer is reserved for very low frequencies less than 500 Hz. L3 V3 1V 0.71V_rms 1000kHz 0Deg

45uH

C3 1.4uF

R2 4ohm

Figure 16: Typical Low-Pass Filter

Because a MOSFET H-bridge configuration will be used to drive the speaker in this project, our typical low-pass filter setup had to be altered slightly. A basic schematic of the layout and the values for the components can be seen below in Figure 17. This may look like the typical low-pass filter, but notice that based on the filter described above, the load output is half, the input voltage is half, the inductor value is half, and the capacitor value is doubled. This is due to the fact that there will be two of

29

these filters in place at the H-bridge, for simplicity and ease of explanation, the model was done in this manner. L1 V1 0.5V 0.35V_rms 1000kHz 0Deg

22.5uH

C1 2.8uF

R1 2ohm

Figure 17: H-Bridge Output Low-Pass Filter

To ensure that the design will perform in the manner that it was designed, simulations were in order.

Figure 18: Bode Plot for 1 Ohm Load

30




31

The simulations show where the cut-off frequency will be for each speaker load configuration. The calculations were very close to the simulated results with the margin of error increasing as the impedance decreased. Notice that the last figure of the 8Ω load shows a frequency of approximately 20 kHz. This is due to the fact that there is a slight rise in the filter response before the cut-off. The rise is approximately 3db, and that is what is shown. The actual -3dB point is in fact 40 kHz.

2.5.2 Electromagnetic Interference (EMI) Electromagnetic interference is caused by rapid changes in currents. When the power stage transitions, the switch’s output changes across the entire power supply voltage and the loudspeaker current is re-routed through the output stage. This is the main cause of electromagnetic interference in Class-D amplifiers. Contrary to popular belief, the voltage change is not a major issue as long as capacitively coupled currents can be returned directly to the source using electrostatic shielding. High changes in current value, on the other hand, will cause magnetic radiation, which is the main cause of electromagnetic interference. EMI becomes a problem when the speaker wires from the amplifier to the speaker act like an antennae and transmit the EMI throughout the car’s vehicle. Also, these same wires could receive EMI that the car might transmit, interfering with the signal that the speaker is trying to play. This is why it is important to keep the speaker wires as short as possible. The longer they become the better the chances are that they will either receive or transmit EMI. Another way to keep the EMI to a minimum is to use a braided speaker wire as shown in Figure 22. Theoretically, the EMI from one speaker wire is cancelled out by the other one.9

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Figure 22: Braided Speaker Wire Example9

Another major concern is due to the high-frequency noise caused by the fast switching speeds of the MOSFETs. In a mobile environment, the Class-D amplifier can be detrimental to the operation of the vehicle’s central computer. A typical Class-D amplifier should be at least 3 feet away preventing the occurrence of interference. However, in this project, one of the goals is to create an amplifier that remains high powered, small in size, and also EMI shielded.

Figure 23: EMI Interference

The high-frequency noise could also present a problem on the speaker lines. Even though it can not be heard in the speaker, there is always going to be residual high-frequency noise.10 Long speaker lines will act as an antenna to receive that high-frequency noise. This residual noise can also interfere with your radio reception. This interference is minor but it can also cause problems with the operation of the vehicle’s sensors. An example of this is in Toyota pickup trucks when the amplifier is mounted under the seat. The reason this is a problem is because the

33

vehicle’s central computer is also located there. This poses a problem because if the EMI affects the computer of the vehicle, it will affect the vehicles performance, and could create a safety concern. Also, the high-frequency noise carried through the line will be absorbed by the voice coil of the speaker. This noise is extra energy that the voice coil absorbs, causing it to not only heat up, but also waste energy in the process. To face these problems, EMI shielding must be implemented into the design of the amplifier. Currently, there is no shielding in Class-D amplifiers. The manufacturers warn consumers that the amplifier must be at least 3 feet from the car’s central computer.10 In this project, the amplifier will be designed so that the user may place it wherever it is convenient without worrying about where the central computer is located. To do this, three methods have been considered. The first is a braided material that can be purchased that shields EMI very effectively. The tradeoff is that if the braided material is wrapped around several of the components such as the MOSFETs, the heat transfer from the component to the heat-sink would be compromised due to the nylon casing that surrounds the sheilding. This could solve the EMI problem without adding excessive cost to the amplifier, but lacks the thermal capabilities of heat dissipation to the heat sink. The second possibility is to design both a base and heat sink for the amplifier that is naturally EMI shielded. One example would be lead, which is great at shielding, but not as great at dissipating the heat like aluminum.11 Also, implementing lead as a heat sink and an effective EMI shield would greatly increase the weight of the entire amp which would not be good in a mobile environment. Another material to look at is steel. Steel is a compromise between both shielding and heat transfer but adds weight and does not fully shield against all frequencies and still does not dissipate heat as well as aluminum.12

34

A third method is to use perforated metals. Aluminum can still be used as the heat sink, but if we used perforated aluminum we can serve the purpose of both shielding and heat-sink. Tests have proven that a shielding effectiveness of 40dB provides 99.000% attenuation of EMI, and that a shielding effectiveness of 92dB provides 99.997% effectiveness.13 Our amplifier will meet or exceed the FCC regulation of 100 µVolts/m at a distance of 3 meters; however the attenuation required for the amplifier in uncertain at this time. The perforated aluminum appears to be the most effective way to go, but the cost of implementing perforated aluminum has yet to be determined.

Shielding Possibilities Material Shielded Material

Braiding

Naturally Shielded Heat Sink Perforated Aluminum

Advantage

Dis-Advantage

1. In-expensive

1. Difficult to work with. 2. Lacks heat transfer properties 1. Very heavy 2. Most metals either good at shielding or heat sink, not both. 1. Thicker heat-sink 2. Slightly more expensive

1. Serves as both shielding and heat-sink

1. Serves as both shielding and heat-sink 2. Lightweight Table 4: Shield Possibilities

Active research continues on reducing interference by inspecting new arrangements for components to either reduce or completely eliminate the electromagnetic waves. This is certainly an area that must be fully explored but will be much easier once the design of the amplifier is complete.

2.6 Efficiency The most limiting factor in achieving high-efficiency is in the final stage of any amplifier. The theoretical efficiency of a Class-D amplifier is 100%, but unfortunately it is also limited by non-ideal components. In addition, the increasing switching speed necessary to produce a clean audio output also

35

reduces this factor by a great deal. This section will attempt to describe the effects of discrete MOSFET shortcomings. In our amplifier, we chose to use a standard MOSFET H-bridge power stage. This allows us to apply both a positive and negative voltage to the load somewhat easily. Another alternative commonly used in an amplifier output stage is the push-pull BJT pair found in Class-AB amplifiers where the output stage consists of an NPN and a PNP transistor. As the input sweeps from VEE to VCC, the output passes through a dead zone of 1.4 Volts in which both transistors are off. This dead zone causes crossover distortion which can be avoided when using MOSFETS and either a Sigma-Delta or PulseWidth modulated signal. Figure 24 below shows a basic model of our circuit.

Figure 24: Basic level circuit model

In Figure 24 there are four N-MOS devices. In an H-bridge configuration as the one depicted below, current may take one of two paths.

36

Figure 25: Current paths through the H-bridge

Sigma-Delta technology implies that the signal be switched from 0 Volts to either rail voltage rapidly enough to represent an analog signal. This means that for any given pulse, the output must change 42 Volts. The fact that MOSFETS are not ideal and contain capacitive and inductive properties limits the speed at which this switching occurs. In order to simulate the effects of such characteristics one would need to simulate the complex model of each MOSFET in a circuit. We have circumvented such testing due to time limitations and have found equations to give linear approximations of the output. These can be found further along in this section. There are in fact two sources of loss from switching a MOSFET. The first is due to changing the drain to source voltage limited by Cds and the second from changing the gate to source voltage by Cgs. For our purposes, a linear approximation of the power loss due to switching from both the drain to source and gate to source will suffice. Figure 26 gives an accurate representation of what we are trying to calculate.14

37

Figure 26: MOSFET Switching Losses

The new simplified equation uses common specifications given by manufacturers and therefore may be estimated before purchasing any of the MOSFETs. The equations used to find the power loss are listed in Table 5 and are explained in the Appendix. SwitchingP owerLoss (Gate − Source ) = Q g * V gs * f clk = [Watts ]

Conduction ( DC ) Loss = VRds * I d / 2 = [Watts ] ⎡⎛ 2 Rds C.L. = ⎢⎜⎜ ⎣⎝ RLoad + 2 Rds

⎞ ⎤ ⎡ ⎤ Vds ⎟⎟Vds ⎥ * ⎢ ⎥/2 ⎠ ⎦ ⎣ RLoad + 2 Rds ⎦

1 SwitchingPowerLoss ( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts ] 2

Efficiency = 100 − 100 * 2 Efficiency = 100 − 100 * 2

2

C.L. =

Vds * 2 Rds

2(RLoad + 2 Rds )

2

Ploss Ptotal ( Psw,d − s + Psw, g − s + PDC ) ⎛ Vrail ⎜⎜ R 2 * ds + Rload ⎝

2

⎞ ⎟⎟ * Rds ⎠

Table 5: Power Loss and Efficiency Equations

From the calculations in the Power MOSFET section of this report, one can see that the efficiency of the Fairchild FDP038AN06A0 is adequate enough for us to achieve our goal of 95% efficiency. While other MOSFETs met or exceeded 95% efficiency at our test frequency of 192 kHz, this model was the most efficient. This has been made possible by a small Rds value and reasonably small Qg value. These two specifications are the most significant in gaining efficiency. As Rds or Qg increase, efficiency decreases proportionally.

These specifications are also

inversely related which means that a When manufacturing a MOSFET a design consideration has to be made because it is not possible to decrease both Rds and Qg at the same time. Currently it is not

38

possible to decrease both factors at the same time. Perhaps a different fabrication process will some day minimize these limiting factors. However, since Rds is a much larger factor to consider, we chose the MOSFET with the least DC-on resistance. Semiconductor technology continues to advance every year. New ways of making faster, higherpower, and smaller devices are being discovered all the time.15 These minimize both the size and cost of the electronic devices. Next year there will be an even better selection of MOSFETs to implement and raise efficiency once again. The most important factors to look for when deciding on any switching device would be its DC-on resistance, unless switching speeds are in excess of 10 MHz. The advent of these new components shall push the limits of efficiency and give engineers the tools they need to make amplifiers switch faster and ultimately produce higher fidelity sound.

2.7 Controls Theory A certain level of control must be implemented in the system to protect against the frequent instability of an automobile environment.

Feedback is a common method for dealing with this

instability. If employed correctly, it may safeguard the overall output of the amplifier from variations in the rail voltages and unwanted energy produced by the signal processing. A simple block diagram of the system gives a better understanding of how the output can be used to correct these simple problems.

39

Analog Input

Sigma Delta Modulation

H-Bridge

Low Pass Filter

Feedback

Figure 27: Block Diagram

A main concern of this MQP is to maintain a certain level of total harmonic distortion (THD). Since the rail voltage of the H-bridge is entirely dependent on the automobile’s PowerNet voltage, a wide range of values must be tolerated without alteration to the speaker output. This means that if a lower voltage is present, then the output may need to remain “high” for a longer period of time to reach an equivalent analog value. Conversely, if a higher rail voltage is present, the output will remain high for a shorter period of time. If done properly, the output should not deviate from the input apart from the gain. Figure 28 shows that as the rail voltage changes, the duty cycle must be changed to achieve a steady output. By using the average output voltage as a midpoint, relative voltage swings can be calculated and used to modify the duty cycle of the Sigma-Delta modulated signal. For instance, if the average voltage of a PowerNet system is 48 Volts and voltage drops to 44 Volts, the duty cycle must increase by 8.33%. DutyCycle =

V f − Vi Vi

=

48 − 44 = 8.33% 48

decreased by 8.33% if rail voltage rises to 52 Volts.

40

Conversely, the duty cycle must be

Figure 28: Duty Cycle

This same technique serves a dual purpose. In addition to opposing the effects of rail voltage swings, some of the excess energy generated by the switching output can be negated. The control circuit must be fast enough, i.e. clock speed remains much higher than 20 kHz, in order for this theory to work. All other noise generated will be attenuated by the output low-pass filter. Theoretically, the output should be a clean representation of the input.

2.8 Test Measurement Methodology It is often times overlooked as to how the actual testing of a system will be done. For this reason, it will be show on the most basic level how the amplifier will be tested in terms of power and efficiency. Please note the following figure.

Figure 29: Testing Diagram

41

By measuring both the voltage and current at the power supply, the input power of the amplifier can be determined using the following formula: PIN = I ∗ V By finding the RMS voltage out of the amplifier, the output power of the amplifier can be determined using the following formula:

POUT =

V2 R

From the actual power of the amplifier, the efficiency can be calculated.

The theoretical

efficiency has already been determined in the MOSFET section of this paper. If the measured output is divided by the input power, this will yield the efficiency of the amplifier.

OutputPower = Efficiency InputPower If a 1Ω load was used for testing in lab, the testing equipment would have to be capable of handling 42 Amps of current. Such equipment is expensive, and might not be readily available. However, we will not be testing at such a low load impedance.

42

3 Design The design of a Class-D car audio amplifier is a complex and faceted undertaking. The design stage of any project requires the most time and effort, and is also the most crucial to success. The design considerations we took into account for this project were signal processing, power output and amplification, filtering, thermal relief, and printed circuit board layout.

3.1 Sigma Delta Modulation The signal processing scheme that we chose was Sigma-Delta Modulation (Σ-∆). It is an analogto-digital conversion (ADC) method that is an adapted version of delta-modulation. A brief description of this technique can be found in the Background information section on Sigma-Delta Modulation. Transforming Σ-∆ into a reality is not a difficult process and can be broken down into several designable stages fairly easily. This section will focus on the design of these sections and the workings of the whole system. Previous to designing the circuitry involved in transforming an analog input signal into several quasi-digital gate drive signals, one must understand the whole amplifier as a system. Using control theory, one is able to map the signal flow and its transformation from stage to stage. Figure 30 below shows a basic Sigma-Delta Modulation scheme with no additional components.

Figure 30: Basic Sigma-Delta Modulation

The open loop response of this system would look something like a pole at the integration constant and a -20dB/dec slope thereafter. This is due to its transfer function

H (s) =

1 sτ int

where τint

is the integrator time constant. Ideally, noise would be introduced mostly at the switching frequency of the system but would be minimal at audible listening levels due to the inherent noise-shaping characteristic of Sigma-Delta.16 Figure 31 shows the normal (average) distribution of energy in the

43

harmonics of this noise. One can see the decline in magnitude within the audible band. All higher frequency noise is filtered out using a low-pass filter as described in the Filter section of this report.

Figure 31: Noise Spectrum

In the design of our amplifier, we chose to modify the basic modulation scheme depicted in Figure 30. By adding a second 1-bit quantizer, or comparator, we were able to generate four separate gate signals to drive the four n-channel enhancement mode MOSFET devices in our H-bridge configuration separately. This control over all the MOSFETs simultaneously was crucial in creating a three-level output signal. The functionality of how the MOSFETs create these three states can be found in further detail in the Power Stage section of this report. This additional control would minimize power loss from drain to source switching, given the following equation:

17 1 PDS − = Vin I o (t ON + t OFF ) f s = [Watts ] . 2

Discussion of this topic can be found in the Efficiency section of the report. This more advanced SigmaDelta Modulation scheme is shown in Figure 32.

Figure 32: Three-Level Sigma-Delta Modulation

44

The signal path can be described using Figure 32 above as a visual aide. First, (1), the signal arrives at the amplifier from the audio source as an analog waveform of either music or a test tone. Since Sigma-Delta Modulation requires a feedback loop in order to take the difference from input versus output, signal 7 is best described as a scaled down version of the output. Signal 2 is therefore the difference between the input and output waveforms. This may also be called the “error.” In order to keep track of this error, continuous integration takes place resulting in a “sum of errors” waveform at signal 3. Using two 1-bit quantizers, four quasi-digital streams, signal 4, are generated to control the gates of the H-bridge. The power stage of the amplifier receives these streams and is able to interpret them in such a manner to switch the four MOSFET devices. At location 5, the signal is very much still digital but greatly amplified to the level of +/- the rail voltage. After the amplified signal is filtered using a 2-pole Butterworth filter, the result is signal 6, an amplified version of the original analog signal. This loop is continued indefinitely. Now that the system has been described, each module involved can be delineated separately. Starting with the integrator, the schematic in Figure 33 shows the basic configuration.

Figure 33: Integrator

The integrator portion of the signal processing loop shown above has three important tasks. The first is to take the difference between input and feedback. This is shown in the blue square marked Delta including a pair of resistors whose center is the output. Since the input and output are roughly the same but opposite in sign, one can expect this waveform to fluctuate closely around zero volts. While testing, we did not capture this waveform since the magnitude was essentially zero. The second task is to 45

compute the integral of the signal at its negative input terminal. The final duty required for the integrator to accomplish is the addition of a zero as illustrated in the next paragraph. As described in the Stability section of this report, it is necessary to implement both a pole and zero into the integration of the signal to achieve stability. The zero of the integrator was determined to be 20 kHz using a Miller integrator equation of f z =

1 . The pole of the integrator was determined 2πRz C

by using the same equation, however this time the resistor value used to determine the pole was taken from the negative feedback of the integrator.

fp =

This yielded a pole at 7 kHz using the equation

1 .18 2πR p C The next stage of Sigma-Delta Modulation was to implement comparators as high and low 1-bit

quantizers. This was actually performed by using two comparators whose negative inputs saw either a voltage slightly higher or lower than zero. This voltage margin was called the “dead-zone” voltage due to the fact that any output of the integrator between zero and this level resulted in zero switching of the output. We found that the calculation of such a value is a trivial matter since, in testing, it was best to finely tune this margin using a plug-and-check method. The resistor value that yielded the least crossover distortion and optimal switching efficiency was 620Ω. Using this ratio of resistors, the corresponding voltage for the dead-zone was computed to be VDZ = 15V *

620Ω = 90mV . The 100kΩ + 620Ω

need and application of a resistor divider network to accomplish this voltage margin can be read about in the Dead-Zone section of this report. As the sum of errors was compared to these near zero voltages, TTL logic level voltages are sent to a D-latch flip-flop which converts the two outputs to four quasidigital streams: Q1 , Q1 , Q 2 , and Q 2 . Figure 34 shows the resistive voltage divider, comparators, and

flip-flop.

46

Figure 34: Quantizers

If the Q1 and Q 2 waveforms are plotted on the same axis, this gives the illusion of three-level Sigma-Delta switching. While this waveform does not directly exist, the output of the H-bridge does follow the switching pattern seen in Figure 35. To further clarify, what appears to be switching either positive or negative is really a change in polarity at the load. However this three-level state is what the load thinks it is seeing, which is why we say that it does not directly exist.

Figure 35: Three-Level Switching

47

Since the H-Bridge is described in a different section of this report, we can jump to the final division of designing the signal processing segment of the amplifier. The feedback attenuation block is simply an instrumentation amplifier, or In-amp, that has been calibrated to the specific gain of our amplifier.

Figure 36: Feedback Attenuation

We were able to determine the values of these resistors by using the low frequency gain of the system, A = −

R1 19 . In our case, the amplification factor of the amplifier is about 30, so R2 must be 30 R2

times greater than R1. This completes the Sigma-Delta Modulation signal processing piece of our report and is now important to discuss the power output and final stage of the amplifier.

3.2 Power Stage After the input signal passes through our Sigma-Delta Modulation scheme, we then devised a way to control the MOSFETs of the H-Bridge. Because the signal is three-level, there are 3 possible output configurations that the MOSFETs must be in. Figure 37 shows the three possible MOSFET configurations.

48

Figure 37: Three possible MOSFET configurations

In order to achieve the three states shown above, we had to use all the resources available to us. This meant that we had to use all four outputs of the flip-flop to control the MOSFETs individually. To accomplish this goal, we used the output of the Q1 pin from the flip-flop to control the A-side High MOSFET, otherwise known as AH. This means that if the logic output sees a high, it triggers this MOSFET on. On the flip side, if the logic output sees a negative high, then we want the B-Side High MOSFET (BH) to be turned on. The way the flip-flop is configured, this corresponds to the Q 2 pin. These two states are what control the majority of the switching; however there are still two more connections to be made. When the AH MOSFET is on, the AL MOSFET must be off. In order to achieve this, the AL MOSFET was connected to the Q1 output pin of the flip-flop. This ensures that the AH MOSFET and the AL MOSFET will never be both on or off at the same time. The same type of configuration occurs on the B-Side. When the BH MOSFET is on, the BL MOSFET must be off to prevent a short to ground as well. This means the BL MOSFET must be connected to the Q 2 output pin of the flip-flop to ensure it is always opposite from the BH MOSFET. This leads us into a discussion of the final configuration of the MOSFETs, which we will call the zero state. For the time duration when neither the AH or the BH MOSFETs are on, we need a third state, zero. During this time, we turn both the AL and the BL MOSFETs on, grounding both sides of the speaker. Having this third state is what allows us to maximize efficiency because we are not wasting energy when not needed.

49

The output from our Sigma-Delta Modulation is what tells the MOSFETs when to turn off and on, but there is one other device that was not yet mentioned. Between the flip-flop and the MOSFETs is a driver chip. A driver chip was chosen for two reasons. The first reason is because it has built in logic protection to ensure that 42 Volts is never shorted to ground. The second reason is because the driver chip we chose can source up to 1 Amp of current per gate drive. What this means is that it will turn each of the MOSFETs off and on with more power, resulting in quicker turn-on and turn-off times. The actual schematic of the Power Stage can be found in the Appendix.

3.3 System Stability A major concern in designing our amplifier was how stable it would be under normal operating conditions. A circuit must be able to operate without unwanted resonance that may be damaging to its components. Each part of the amplifier was tackled by finding their individual transfer functions to avoid unwanted resonance. This section of the report discusses the different parts of the amplifier and how they each help or hurt the stability of the system. Transfer functions are equations that help relate both gain and phase shift to a circuit. A typical transfer function has the form H ( s ) =

Z (s) . The two polynomials, Z(s) and P(s), allow the zeros and P( s)

poles of the system to be found. Zeros are values for s that make Z(s) = 0 and the overall gain of the system zero. Poles are values that make P(s) = 0 and the overall gain infinite20. In addition, a zero produces a phase-shift of +90° while a pole produces a phase-shift of -90°. 21 The low pass filter used in the power output stage of the amplifier plays a large role in maintaining stability. This filter is 2nd order, which means it has two cutoff frequencies. These frequencies are calculated in the Filter section of this report to be at 14 kHz and 40 kHz. Together these two poles (low-pass cutoffs) add an additional -90° of phase shift to frequencies above each of their cutoffs. If the open-loop gain at these frequencies approaching -180° phase shift is not less than 1, or 0dB, resonance may become a problem. This could be detrimental to any system taking negative feedback from the output because the resonance could oscillate indefinitely, causing the system to crash. Now, instead of the negative feedback being able to correct for any imperfection in the output as described in the Sigma-Delta section of the report, the noise is reinforced. It is preferable to have a phase at which gain is 0dB of 145°or less.22 This is also called the phase margin, or difference between

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0dB phase and -180°. Later in this section it is shown that a phase margin of 35° is required for stability. The other source of poles and zeros comes from the Miller integrator used in Sigma-Delta processing. It was determined that our system could not tolerate any more poles without zeros, therefore an additional resistor was added in series with the capacitor of the integrator. Please reference the Sigma-Delta section of this report for this schematic and cutoff frequency calculation. The pole of the integrator was located at 7 kHz while the zero was introduced at 20 kHz. The location of the zero was chosen purposely close to the 14 kHz pole of the output low-pass filter. This zero would offset the phase shift and decrease the attenuation [in dB per decade] caused by the pole. The result of this action is such that neither pole nor zero have an overall effect on the system. The cancellation of pole and zero then allowed us to determine the frequency at which to make our integration pole while maintaining a phase margin greater than 35°. This calculation was not a simple one to make. Therefore a graphical method was used to determine this value. First, we had to determine the DC gain of our system. Using the equation below, it was computed to be the following: ⎛V A = 20 log⎜⎜ OUT ⎝ VIN

⎞ ⎟⎟ ⎠

⎛ 42V ⎞ A = 20 log⎜ ⎟ ⎝ 6V ⎠ A = 16dB

We then decided to draw a Bode Plot of our system. The DC gain of our amplifier is 16dB and therefore can be regarded at the starting point of our Bode Plot. Figure 38 helps illustrate the graphical method we used in obtaining the integrator pole. By reducing the frequency of this pole location, the magnitude curve is shifted down and phase margin decreased. Conversely, increasing the frequency of the integrator pole shifts the magnitude curve up and phase margin increased. The value at which the resulting phase margin is 35° is 7 kHz and can be seen in Figure 38.

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Figure 38: Graphical Bode Plot Method

The final bode plot of the system can then be plotted. This can be seen in Figure 39.

Figure 39: Bode Plot

From Figure 39 one can see that the system is stable. This is justified by the phase margin of about 35°. In this amplifier, the output filter relies on a 4Ω load for stability. If the gain of the amplifier was increased or load changed to different impedance, the system may become unstable.

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3.4 Filter One of the most critical stages of our amplifier was our filter. Without it, a sinusoidal input would remain in the form of a three-level Sigma-Delta Modulated output. This signal would contain a great deal of unwanted high frequency content. This energy at frequencies up to the fastest response frequency of the driver chip may be potentially damaging to a speaker and would use any speaker wire as an antenna for radiating EMI. In order to solve this problem, a low-pass filter was introduced to the circuit to cutoff any frequencies higher than approximately 20 kHz. This is because the human ear can only hear from 20-20 kHz, so any frequencies higher than this would result in wasted energy that the speaker would try to play. Originally, we thought we could create a second order Butterworth filter with a double pole at 20 kHz. However, the filter got slightly more complicated when we introduced our Sigma-Delta circuit. The problem that arose was that we then had to be concerned with the stability of our system. The details on the stability of our system can be found in the Stability section of this report. From a design standpoint the only thing we needed to know was that the poles had to be separated, meaning that there could not be a double pole at 20 kHz. Again, the reasoning for this can be found in the Stability section of this report. Separating the poles of the filter turned out to be a much more difficult task than anticipated. Early in the project, we knew that inductors would have to be ordered. Originally, we thought that we would be able to run a 1Ω load, resulting in nearly 50 Amps of current to be drawn through the inductors. Because of the high current rating of the inductors required for our specifications, the inductors had to be custom made. This resulted in a fairly costly investment for our amplifier, so once we had the inductors in our possession, we could not afford to send away for new ones. This posed a bit of a problem for our design. In order to determine the cut-off frequencies for our filter, the two equations below were used. 1

f1 =

2π L ∗ C R f2 = 2π ∗ L

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Notice that the inductor value is used to obtain both cut-off frequencies. This means that because we were stuck with our original inductor value of 22.5 µH, we were limited in the range of cutoff frequencies we could obtain. Also, thinking ahead to the testing of our amplifier, we decided to stick with a fixed load resistance of 4Ω. This meant that the cut-off frequency for f2 was predetermined.

f2 =

R 2Ω = = 14kHz 2π ∗ L 2π ∗ 22.5µH

Notice that the cut-off frequency is only 14 kHz. This is a design trade-off that we had to make in keeping our original inductor values. Although the first cut-off frequency is lower than 20 kHz, most people can only hear up to 16 kHz.23 By taking that into consideration, we decided as a group that it was one design decision we were willing to live with. The benefit of purchasing new inductors was not worth the small increase in cut-off frequency of the low-pass filter. Also notice that a resistance of 2Ω was used in the equation instead of 4Ω. This is because in an H-bridge configuration, there are two separate filters, one for each half of the bridge. This can be seen in Figure 40 below.

Figure 40: H-Bridge Filter Configuration

When trying to design a filter for an H-Bridge configuration, the easiest way to approach the situation is to look at only half the bridge at a time. What this means is that it is necessary to divide the bridge in half. If that is done, you will notice that the inductor value and capacitor values remain the same. The only variable that changes is the resistive load, because half would belong to each side of the filter. Please refer to Figure 41. 54

Figure 41: H-Bridge Filter Half Representation

The circuitry remains exactly the same, and you will notice that there is still a 4Ω load in place. However, when looking at the filter half representation, only 2Ω belongs to each filter, which is the reasoning behind the 2Ω being used in the f2 equation rather than the 4Ω. After we accepted the first cut-off frequency to be 14 kHz, it was then time to set the second cutoff frequency. Notice that the inductor value is also included in this equation, but we do have the flexibility to change the capacitor value.

Once again we already had purchased several 0.1 µF

capacitors, so we decided to use those as well. This was not as big of a concern because we had the ability to add as many 0.1 µF as we wanted, giving us a range of overall capacitance. Knowing that our first cut-off frequency was 14 kHz, we decided to make the second cut-off frequency approximately 40 kHz. This would be well past the audible range, but still low enough in frequency to reduce EMI. Using the formula for f1, we were able to compute what capacitor value was desirable to yield a cut-off frequency of 40 kHz.

f1 =

1 2π L ∗ C

→ 40kHz =

1 2π 22.5µH ∗ C

→ C = 0.7 µF

Based on this formula, the capacitance value that should be used is 0.7 µF. This would be easy to obtain from the 0.1 µF capacitors that we already had by configuring 7 of them in parallel. Figure 42 shows how the filter may look from a schematic perspective.

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Figure 42: H-Bridge Filter Design Configuration

One of the reasons that we decided to use multiple capacitors in parallel rather than one big capacitor was to reduce the equivalent series resistance, or ESR of the capacitors. The ESR is a calculated resistance at a particular frequency. As the frequency increases, the ESR decreases linearly. This was an important factor to take into consideration because at low frequencies, the ESR is relatively high, measuring at 1.6Ω for the capacitors we chose. However, AC current through this series resistance would be lower at low frequency since I = C

dv . A high ESR would be detrimental to our efficiency, dt

and will be talked about in further detail in the Efficiency Losses section of this report. Although the configuration shown in Figure 42 would have worked, this was not the layout that we chose for our filter. If you count the total number of capacitors in the circuit, you will find that 14 capacitors would be necessary in order to produce our filter. There is a way to reduce the total number of capacitors used that create the same filtering effects. The way to achieve that is to use some of the capacitors across the load instead. Please refer to Figure 43 for further clarification.

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Figure 43: H-Bridge Filter Configuration

By placing some of the capacitors across the load, they essentially become twice as effective. This is because they contribute to both sides of the H-Bridge filter, rather than one side at a time. Notice that if the 4 capacitors across the load count for each side, then that yields an overall capacitance of 0.8µF, not 0.7µF. Well this is true. We decided that we wanted a symmetrical looking board, and in order to achieve that, three rows of 4 capacitors would have to be used. We decided that this was also a design tradeoff we were willing to accept because the difference between 0.7 µF and 0.8 µF resulted in a cut-off frequency of 40 kHz and 37 kHz respectively. Also notice that the total capacitor count was reduced from 14 to 12, while still increasing the effective capacitance. Had we not added the capacitors across the load, and still wanted 0.8 µF of effective capacitance, then a capacitor count of 16 would have been necessary instead of the 12 we used in our filter design.

3.5 Heat sink For the testing of our project, we knew that the MOSFETs used for our H-Bridge would get hot due to the fast switching speeds. To increase the performance, a large heat sink was created to help maintain a reasonable temperature for the MOSFETs. Two different considerations were taken into account. The first consideration was to build a heat sink for testing purposes. The second consideration was to design a heat sink for marketing purposes. If this amplifier is to be marketable, the heat sink would have to be large enough to keep the MOSFETs cool for long durations of playtime. However, for 57

the testing of our amplifier in lab, we decided that 15 minutes of playing time would be more than sufficient to test the amplifier and obtain our results. It was decided to construct an adequate heat sink for our purposes of testing in lab, and to design another that would be used as both a housing and a heat sink if the amplifier was put into production. For testing purposes, two heat sinks were fabricated out of a solid piece of aluminum. The aluminum was donated to us by A & R Plastics Inc. as well as their machine shop for fabrication of our heat sinks. The design of the heat sinks presented some constraints. One constraint was how wide the heat sinks could be by the amount of space we had on our board between components. Our second constraint was the depth of the heat sink, which was limited by the depth of our board. We chose aluminum for the design of our heat sink because of its light weight and thermal properties. Secondly, in order to maximize the surface area of the heat sink to the ambient air, cooling fins were added to the design. Generally the more cooling fins that a heat sink has, the better job it will do at keeping the components cool. The heat sink was made larger than necessary, but in our situation it was best to over estimate the need for thermal protection. This yielded two identical heat sinks with overall dimensions of 2.25”x 2”x 1.375”. An actual picture of the heat sink used for testing can be seen in Figure 44 below.

Figure 44: Heat sink used for testing

Figure 45: Heat sink shown with supports

One of the problems that we encountered with such a large heat sink was the weight of the finished product. The heat sink could have been made smaller, but since the product was already finished, we thought it would be best to leave it alone. Because we had a machine shop at our disposal, we decided to drill and tap some supports into the fins of the heat sink. This would allow us to use 58

Teflon screws to support the weight of the excessively large heat sink. After it was mounted to the board, the idea worked out quite well. Figure 45 shows a heat sink mounted to the MOSFETs with supports in place to help reduce the load the MOSFETs would have to carry. Although it may not look as professional as it should, the idea worked, and so did the heat sinks. We were able to play music, which causes the most amount of switching, for approximately 15 minutes before the heat sinks started to get too hot. We were able to conduct all of our testing with the heat sinks shown. In the event that our amplifier is to be sold in today’s market, the amplifier would have to be contained in a solid casing of some sort. This means that the heat sinks can not be two large objects attached to the MOSFETs. Instead, the MOSFETs would be placed at the very edge of the board, and the casing surrounding the amplifier would double as a heat sink. Fins would be incorporated into the design for what would hopefully be fan cooled. In addition to this casing being used as both a heat sink and an outer housing unit, it would also serve as an EMI shield which was discussed in the Background section of this report. The actual fabrication of this type of device was not made, however it is important to point out the need for a housing in the event of a continuing MQP or for marketing purposes.

3.6 Printed Circuit Board The design and layout of any printed circuit board is a very cognitive task. One must first analyze the components that will ultimately populate the board and their needs. Secondly, the basic shape of the board can be determined. Thirdly, any components including input and output terminals requiring special locations can be placed. Lastly, the remainder of parts can be laid out using good engineering practices described in this section. Often times certain components require special locations and must be considered before all others. This was the case in the design of our PCB as well. In particular, high-power switching MOSFET devices were a major concern and had to be dealt with carefully. We knew that under the high current and fast switching they would be subjected to, heat was an issue. In order to deal with the thermal protection of the MOSFET devices, large heat sinks would be required. Through our experience with other audio amplifiers we were able to determine their best location. By aligning the TO-220 packages along the edges of the PCB and facing heat sink tabs outward, we would be able to effectively build as large of a heat sink as necessary. All other devices were not as much of a concern in this stage of PCB design. 59

Figure 46: Placement of MOSFETs for Heat Sink

Determining the fundamental shape of our board was one of the more elementary steps in laying out our design. While many forms and sizes may have worked, the most basic and industry standard shape is still the rectangle. Since our design followed a strict flow of information in one direction, an elongated rectangle certainly seemed the most reasonable model. This would allow for as much surface area as required by heat sinks as well as minimizing wasted space. The layout of the final board design was the next step to take place. As mentioned previously, the flow of our signal path was strictly unidirectional if feedback were ignored. Therefore we found it best to divide the PCB into sections, much like our circuit for both simplicity and practicality. One side of the board was clearly designated as the signal processing portion whereas the other was reserved for the power output section. These two divisions are distinct from one another in their requirements so were best left separate. On one hand, the signal-processing side is filled with mixed signals and hightransient voltage transmission lines. Adversely, the power output stage of the amplifier requires large ground planes, many wide current paths, and spacing between thermally dangerous components.

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Figure 47: Two Separate Sections of Board Layout

Good engineering practices should always be used when designing a printed circuit board. There are several rules of thumb that we used. The first and foremost was to allow high transient voltages their own paths and ground planes while keeping them short. What this means is to avoid running other traces either over or under these paths in a multilevel board. Failing to do so will certainly affect signal integrity as each trace acts as a transmitter and receiver. This is due to the fact that the traces are capacitively and inductively coupled. The second rule that we used was relative to any high current paths. These traces should be kept as wide as possible to minimize the trace resistance, and wherever possible, power planes should be used. Any high current path that is too narrow will not have negligible resistance. In our design using a 4Ω load, we measured currents in excess of 10 Amps. From a power loss perspective even a 0.1Ω trace would burn up to 10W of power, or 2.5% of the total. This loss could greatly set back our efficiency goal. Another method of keeping these traces short was to place power, ground, and speaker connections on the power output side of the board. By following these layout rules, we believe that efficiency and signal integrity can be maximized.

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4 Project Evolution In order for us to complete the project with a working amplifier, several board designs were used to achieve our goal. At first we started small, and eventually worked our way to a professional looking printed circuit board for the testing our amplifier. This section of the report will explain how the project evolved and how we ended at out final result.

4.1 First PCB Once the design was finalized in the respect that we were using a MOSFET H-Bridge configuration that was controlled by a driver chip, it was time to perform some testing. The simplest way would have been to use a breadboard to wire the circuit; however breadboards contain capacitance and inductance between the traces, so our results would not have been as accurate as we would have hoped. Also, we knew that we would be drawing approximately 2.5 Amps of current, and this reached the threshold of what we considered to be too much for a breadboard to handle. Pulling such a large amount of current through the breadboard could have caused it to melt, which would have been a safety concern in lab, and also could have damaged the components we were trying to test. Because of this, we decided to use a PC board that we would wire ourselves using a design layout that would minimize interference with transient currents as described in the PCB design section of our report. After much debate as to how the board would be laid out, we decided to wire the power stage of our amplifier using primarily 22ga wire for most of the connections; however 16ga wire was used to connect the power supply to the MOSFET bridge, the bridge to the load, and the bridge to ground. This is where the 2.5 Amps of current would be traveling, and we wanted to ensure that the wire would be able to handle the large current draw. Soldering the wires to all the components proved to be much more difficult than anticipated. In many cases, there were 3 wires attached to a single pin. This made it difficult because after one wire was soldered in place, one would then have to heat up the pin a second or a third time to add the additional wiring. In doing so, the previous wires that were already attached had the tendency to fall off because the solder was heating back into a liquid state. It took some time to complete, but you can see the end result depicted in Figure 48.

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Figure 48: Original PCB

As you can see, we tried our best to keep the board layout as neat as possible to simplify troubleshooting. The huge coils that you can see at the top of the picture are our inductors used for the low-pass filter. When we started the board layout, the custom wound inductors were just being ordered, so we had no idea they would be so large. Because of this, they are hanging off the edge of the board, but through the use of banana connectors, we were able to make it work regardless. Another thing to point out is the large black block attached to the MOSFETs. This was a chunk of aluminum we cut to use as a heat sink. The aluminum served the purposes we needed it for, and also gave us some practice for the heat sinks that were created later in the project.

4.2 Second PCB After our original PC Board was working properly and all the capacitor values, resistor values, diodes, etc. were finalized, we then decided to create a real PCB where we would get a more professional looking board that minimized transient currents, trace inductance and capacitance even further. We knew we still had the signal processing to work on, but for the time being, we thought that having a professional PCB would make things neater and a lot easier to work with for further testing. The program that was chosen to create the board layout was Ultiboard 2001, and at first it was difficult to use, but we got used to it and it worked out very nicely. We then sent out the board to be created using a company called Advanced Circuits.24 We looked into several vendors to create our board, however they were not only the cheapest, but also had a free quote by uploading some of our files that

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even told us where we had flaws in our design. Every flaw that the program found in our design was minor enough that the board could be produced immediately. Most flaws were clearance issue such as a hole being too close to the edge of the board, but since the board size was not etched in stone, they just expanded the board for us where it needed it. To our surprise, the turnaround time was only a few days. We were expecting a turnaround time of a week or two. Also, another observation that we made was that whether you bought 1 board or 4 boards, the price remained the same. This is because setting up the equipment to create your board takes the most time, and after that, the material cost for the board itself and the solder used to coat it is insignificant. When our board arrived, we were very happy with our product. It was very impressive looking, but more importantly it was a very neat design with a lot of thought put into the board layout, and the product was paying off. However, the first draft if you will of our project did have a few flaws. Fortunately however, nothing was catastrophic to the forward progress of our project. The flaws that we found in our first board were as follows: • • • • • • • • •

The ground pins of the BNC connectors were not connected to our ground plane The signal pin of the BNC connector was slightly too large for the hole that was drilled for it A keep out area on the power plane for the banana jacks used for speaker connections was forgotten Mounting holes to elevate the board of the ground were forgotten Many soldering pads were too small, making it very difficult to solder to A keep out area on the power plane was forgotten around the driver chip to make soldering easier The drill holes for the RJ45 jack were much too large, making the solder contact only on one side of each pin. A few of the diode and capacitor holes were slightly larger than necessary The power and ground pins for the voltage regulator were reversed, requiring surgery on our PCB Although most of the issues had to do with hole sizes, luckily in almost all cases, the holes were

larger than needed. Had the situation been reversed, we would have run into a much larger problem. Even where the BNC hole was too small, we were still able to make it fit after some TLC. Our first professional looking PCB can be seen in Figure 49 and Figure 50 below.

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Figure 49: Second PCB Ground Plane (Top)

Figure 50: Second PCB 42V Power Plane (Bottom)

For this board, the MOSFETs were separated by pairs on each half of the board. Because of this, a new heat sink had to be created. Unfortunately we do not have a picture of this board fully populated, but this did give us a chance to improve our fabrication skills. It was much easier to create this heat sink that it was for the first one because we now had some experience under our belt.

4.3 Third PCB After making all the necessary corrections to our second PCB and adding all the components for our sigma delta signal processing, we were ready to send out for another professional PCB. This would be our third board to work with. We once again sent the board out to Advanced Circuits because we were pleased with the results from the first board. This time however the board was about 3 times the cost of what it was the first time because of the considerable size difference. This ate up about half of our budget, but it was well worth it. The good news about this board was that because it was our second iteration of the power stage, there were no mistakes this time around. However, there were a couple in our new section for signal processing. Originally we thought that we could use two inputs for our driver chip, but after the board was already returned to us completed, we realized that we needed to control all four MOSFETs individually. This meant that we had to cut a couple of the traces off the board, and add 4 more. This was probably the most cosmetic damage that we had to put our board through. The only other mistakes on our part was a via that somehow connected one of our traces to the 42 Volt power plane by accident, and our feedback loops had to be switched. This was easily corrected by switching one of the leads for two resistors. To make it look slightly more appealing, we hid one of the resistors 65

under the board, so that as you looked at the top of the board, you only saw 1 resistor at a 45 degree angle rather than 2 crossing resistors. This was the board that we used for all of our testing on the amplifier. The board itself can bee seen in Figure 51 and Figure 52.

Figure 51: Third PCB Ground Plane (Top)

Figure 52: Third PCB 42V Power Plane (Bottom)

The populated board that was used for testing can be seen in Figure 53 below. As you can see, a massive heat sink was created. We put a lot more time into this design because we knew that audio applications play at a wide range of frequencies, causing the MOSFETs to switch much more often that if they were playing a sine wave. The more switching that takes place, the hotter the MOSFETs will get. This is why the heat sinks are so much larger than the previous ones, and also have fins on them to provide more surface area to the ambient air, which increases the thermal properties of the heat sink.

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Figure 53: Third PCB Fully Populated

4.4 Fourth PCB After correcting the mistakes that were found in our third PCB, we decided to create a fourth PCB with all the BNC connectors removed, and the board made as small as possible. We did this with the hopes that we might be able to send out one last board, but unfortunately, we ran out of both money and time. It is however a great place to pick up from if this project gets continued in the future. The PCB is ready to be sent out with all the mistakes already corrected in the program. Also added to the board were twice as many bypass capacitors for the 42 Volt power source. It also was important to see how small we could get the amplifier in size without the BNC connectors on there. They were necessary for troubleshooting, but now that the bugs are worked out of the amplifier, they just get in the way. The board layout for our final PCB as well as the previous ones can be found in the appendix.

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5 Testing and Results In this section of the report, we will guide you through the process of how we tested various aspects of our amplifier, and explain to you the results we obtained.

5.1 Efficiency Testing The goal of this project was to design and build a Class-D amplifier that achieves an efficiency of 95%. In order to determine that we met this specification it is first important to discuss the method of which data can be collected. Using the resources available we would need to determine input and output power. This section will illustrate the tools and techniques used to determine efficiency as well as an explanation of our final results. It was necessary to use three measurement devices in order to determine input and output power. There are several methods by which power can be calculated, but the resources that were available to us were slightly limited. However, by utilizing the simple equations below, we were able to determine both input and output power of our amplifier. Power = I * V

V2 Power = R Since the BK Precision regulated power supply we were using gave a current reading as well as a voltage reading, we chose to use the P = IV equation for input power. We were somewhat limited by the accuracy of this device since it was accurate only to one-tenth of an ampere. On the other hand, we would be able to easily monitor the input voltage directly on the board using an HP 34401A multimeter accurate to six significant figures. The output power was measured using only one device at a time. For this task, we chose to use a Tektronix TDS 210 digital real-time oscilloscope. With this device we were able to capture snap-shots of the output waveform as shown in Figure 54.

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Figure 54: Oscilloscope Snapshot

When connected to a computer, data could be uploaded into a spreadsheet to find the RMS, or root-mean squared, voltage. This was solved using the following equation.

2

Avg (VOUT ) =

∑V

2

OUTi

n

n 2

VRMS = Avg (VOUT )

The equation for output power was simply PO =

2 VRMS . R

The change in resistance due to

temperature was apparently negligible because the load resistance measured to be the same at both ambient room temperature and at 140°F. Finally, the ratio of input and output powers was solved for and recorded as the percentage efficiency of the amplifier.

Efficiency =

POUT [%] PIN

The efficiency in comparison to clock speed of the Sigma-Delta Modulation was our most critical measurement. This relation is essential in determining the sampling frequency at which yields 69

the highest efficiency. By using a HP33120A to generate an array of clock waveforms we were able to graph the results at several frequencies ranging from 250 kHz to 4 MHz. Figure 55 below shows the results of these tests.

Efficiency vs. Clock Speed 98.00% 96.00% 94.00%

Efficiency

92.00% 90.00% 88.00% 86.00% 84.00% 82.00% 80.00% 78.00% 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 Clock Speed [MHz] 0% Clipped, 1.4Vin

40% Clipped, 1.6Vin

100% Clipped, 3.0Vin

Figure 55: Efficiency vs. Clock Speed

Efficiency is shown here under three different input conditions in addition to clock speed. The first condition uses an un-clipped sinusoidal input. This produces the least efficient case since the output never reaches the rails of the supply. Therefore switching occurs at each clock pulse in order to represent a median value. The second case was taken with a 40% clipped input signal. At this condition, little or no switching takes place nearly 40% of the time. While no switching is taking place, no error can be apparent with the output at the rail, thus the Sigma-Delta Modulation does not send a correcting signal. The final case utilized for these results uses a fully clipped input signal. For this case, the output is either high or low during each half cycle of input, switching is at a minimum. Nearly all switching loss is therefore avoided and maximum efficiency is obtained. This proves that we do in fact meet our expected 95% efficiency.

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There are other factors that affect efficiency. Since the 42 Volt PowerNet standard states that all vehicles should run at a charging voltage of 48 Volt, we decided to test our amplifier in that state. Using a fully clipped input signal we were able to achieve a maximum of 97.4% efficiency. The larger efficiency is due to the increase in voltage and was noted to be due to the standard specifications. Lastly, using the correct value for the dead-zone resistor is important when optimizing efficiency and will be explained in the following section of this report.

5.2 “Dead-Zone” In order to achieve a clean output, the signal processing circuit must be properly calibrated. For a closer look at the components involved see the section on Sigma-Delta. One of the first items that must be taken into account is the dead-zone resistor, Rdz.

It determines the voltage that each

comparator sees on its negative input. Finding the ideal resistor value is a multilevel process beginning with the calculation of the integrator time constant, τint. The following equations are given knowing the transfer function of a Miller integrator discussed in the Sigma-Delta section of this report.

τ int = Rint Cint τ int = (24kΩ)(1000 pF ) τ int = 150u sec The corresponding dead-zone voltage would then be easily calculated as the voltage that the output of the integrator would swing during this time. Our first calculations to find an accurate deadzone resistor are seen below. Vripple = Vin (1 − e − t / τ )

Vripple = 5V (1 − e −6.7 kHz / 2 Mhz )

Vripple = 0.05V

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Figure 56: Ideal Integrator Output

Figure 56 shows the ideal integrator output and how given the correct VDZ there should be no overlap of MOSFET switching and minimal crossover distortion. Therefore the dead-zone voltage is half this total swing.

1 VDZ = Vripple = 0.025V 2 The dead-zone resistor is therefore the value that completes the ratio:

VDZ RDZ = Vrail RDZ − R100 k

RDZ = 167.5Ω It is also important to mention how to calculate VDZ given a Vrail of 15V, RDZ, and R100k.

VDZ = Vrail

RDZ RDZ − R100 k

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However when implemented in the circuit, this did not give us the results that we were looking to achieve. The output of the tri-level sigma-delta modulation scheme should be two waveforms that should nearly overlap at low voltages to avoid crossover distortion and not result in clipping at the output. With a dead-zone that is too small, outputs of the flip-flop will be too active. This decreases the efficiency of the scheme greatly since it leads to the greatest amount of switching. On the other hand, a value too great would result in cross-over distortion.

Figure 57: Vdz = 7.5mV (Too Small), f = 1kHz

Cross-over distortion is caused by too great a dead-zone voltage seen by the comparator negative input. This leads to a period when the outputs are both zero. The problem with crossover distortion is that this greatly affects performance at lower volume since the dead-zone is a large portion of a small input <100mV. This distortion can be seen in Figure 58 and Figure 59. When the input voltage is near zero, the filtered output looses its sinusoidal shape and flat-lines causing cross-over distortion for a small time duration.

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Figure 58: Vdz = 150mV (Too Large), 1kHz

Figure 59: Vdz = 150mV (Too Large), 10kHz

The theory behind the dead-zone voltage states that the noise in the output is regulated by the amount of crossover distortion. Since crossover distortion is clearly a result of an inaccurately tuned dead-zone, one can state that output noise is proportional to dead-zone voltage. Although we lacked the time to perform accurate signal-to-noise tests with several dead-zone voltages, listening tests were a second option. We can say that there was a distinct difference in noise level between each of the deadzones depicted above. Additionally, a signal processing scheme equipped with a larger dead-zone was susceptible to a greater percentage of noise at low input voltage levels. This is due to the fact that ⎛V ⎞ signal-to-noise ratio is calculated as 10 log⎜⎜ SIGNAL ⎟⎟ .25 This noise would emphasize the need for a ⎝ VNOISE ⎠

smaller dead-zone. The perfect dead-zone voltage was found by plugging and checking several resistor values in order to find where the crossover gap shrinks to zero and minimal overlap switching occurs. This voltage value was 50mV. Figure 60 and Figure 61 depict the ideal results given when using this value.

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Figure 60: Vdz = 50mV (Near-Ideal Value), f = 1kHz

Figure 61: Vdz = 50mV (Near-Ideal Value), f = 10kHz

The result of choosing the correct dead-zone voltage maximizes efficiency while providing satisfactory acoustic clarity. While minimizing crossover distortion is important, overlapping high and low switching signals could be detrimental to efficiency.

This would lead to overheating of the

MOSFETs and ultimately cause the amplifier to run too hot. The following section continues discussion of acoustic clarity.

5.3 Acoustic Clarity By our own definition, acoustic clarity is the ability of our amplifier to play music with adequate speech intelligibility.

Tests were conducted with a variety of input music and test signals.

We

performed several listening tests using the amplifier and attenuated load/speaker combination. The configuration we used for testing can be seen in Figure 62 as a resistive and loudspeaker load. The purpose of attenuating the output was to listen at a comfortable level while maintaining a 4Ω load.

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Figure 62: Speaker Test

Although listening tests were satisfactory, there was a slight “hiss” in the output. To view the noise, we displayed an FFT of the output. This noise had a constant magnitude regardless of input signal, so it was determined to be internally generated. In order to maximize the signal-to-noise ratio, it was best to leave any CD player or other device at full volume. At low volume speech intelligibility was greatly degraded. According to our system design, noise should have been stopped from reaching the load. In one respect, any high-frequency (EMI) would be filtered by a two-pole Butterworth filter. On the other hand, anything below our sampling rate should also be compensated by the time it reached the output with negative feedback. There are a few culprits that have been identifies as candidates for the hissing noise at our speaker. The first are improperly calibrated resistor networks used as voltage dividers using 5% resistors. In practice it is best to use special resistor network packages calibrated to less than a percent.

Secondly, Texas Instruments LF356 operational amplifiers were used in place of more

expensive types. In a final board design these components would be swapped with more precise and faster slewing chips.

5.4 Output Power Due to the fact that this MQP was about creating an audio amplifier, we thought it was necessary to show that the project we constructed actually had the ability to amplify a signal. After testing several

76

different areas of the amplifier, we were able to capture an oscilloscope output of one of our tests. This output can be seen in Figure 63 below.

Figure 63: Input vs. Output

What you can see from the picture is an input sine wave at 5 Volts per division on the scope and an output sine wave at 25 Volts per division. What you can’t see is that the test input signal was an 800 Hz sine wave with amplitude of 1.4 Volts. The output waveform was measured to have amplitude of 40 Volts. To determine the gain of our amplifier, you can simply divide the output power by the input power as shown. Gain =

Output 40 = = 28.57 Input 1.4

As you can see, the gain of our amplifier is approximately 30. This gain factor can be decreased at our discretion by adjusting the feedback discussed in the Sigma-Delta section of this report. This gain of 30 that we obtained was determined using the specifications of a CD player maximum output value of 1.4 Volts. Because this was a maximum value, we wanted a signal of equal magnitude to have the ability of playing through our amplifier without clipping. As you may recall, the voltage rails that we are using are 42 Volt. Based on Figure 63, the output is only 2 Volts from reaching the rails of our amplifier, which would result in a clipped output. Other adjustments could have been made to achieve a

77

greater gain if the input signal was attenuated, however we felt that the maximum value out of a portable CD player was adequate for our testing purposes. We also wanted to know how much power our amplifier was able to produce. To do this, we imported the data from the oscilloscope to our computer as mentioned in Efficiency section of this report. Using the same Microsoft Excel spreadsheet, we were able to compute the RMS power of our amplifier. To recap, the formula we used was: Power =

V2 R

Using the same input of an 800 Hz sine wave of amplitude 1.4 Volts, we were able to measure a power output of 400 Watts RMS when 42 Volt supply rails were used. We were very pleased with the results, and met our goal of creating a high powered amplifier. Perhaps 400 Watts was slightly more power than necessary, but it granted us great satisfaction in knowing that the amplifier we produced is capable of competing with other amplifiers on the market.26 Referring to Figure 63 once again, notice that the output remains in phase with the input. This is important because in car audio applications, often times an amplifier is used to only power the front speakers in the automobile. If the output was out of phase with the input, then the result would be rear speakers that were playing out of phase with the front speakers, resulting in poor sound quality and noise cancellation.

5.5 Signal to Noise Ratio When looking at industry standards, one specification given on almost every amplifier is a signal-to-noise ratio. This specification indicates how much noise is created in the amplifier relative to the signal you are trying to pass through it. The idea is that you want the output power to be much greater than that of the noise power in order to have a clean sounding amplifier. If the noise power is small enough compared to the output power, then it will not be audible to the human ear at the output. The SNR more simply is the ratio of signal power to noise power. This formula can be seen below. SNR =

PSignal PNoise

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In order to compute the SNR, an FFT of the output must first be examined. For our amplifier, we used an 800 Hz sinusoidal input with amplitude of 1.4 Volts. We then examined the output, as seen in Figure 64 below.

Figure 64: FFT used to obtain SNR The oscilloscope that we used for testing was a Tektronix TDS-210. One of the features that made this scope easy to work with that it has an output that allowed us to import data into the computer. The data was imported into Microsoft Excel, where we were able to use the data to compute the power of both the signal and noise. To do this, we had to first separate the signal power from the noise power. That was done by observing the large magnitudes that occurred around 800 Hz where the spike was apparent. Everything else was considered to be noise in our system. With the signal and noise magnitudes separated, the total power in each was found. This was done by converting all of the data from decibels into watts of power. The equations below show the correlation between decibels and watts of power.

PdB = 10 log10 PWatts = 10

79

−12

PWatts 10 −12

× 10

PdB 10

All of the signal and noise powers were then summed separately. Because the SNR is simply a ratio of the two powers, the SNR was easy to calculate at this point. With the information obtained from the FFT, we determined that our amplifier had a SNR of 43dB using the next equation.

SNRdB = 10 log

WSignal W Noise

.

Typically in the market, you will find amplifiers that range from 80dB – 120dB for a SNR. Our amplifier is much less, and as a result there is an apparent “hissing” noise at the output. If more time were permitted, there are several things that could be done to try and increase the SNR, or possibly locate the noise in our system. Some of these suggestions are listed in the Recommendation section of this report.

5.6 Efficiency Loss The primary goals of this MQP were the design of a high-power ultra-efficient Class-D amplifier and the analysis of why 100% efficiency is not possible. While the design of the amplifier was instrumental in completing a successful project, the first objective was not as much of a major concern as the second one. Hours were spent doing research and testing of why an amplifier is not capable of 100% efficiency. In theory, the Class-D design should be able to output as much power as it receives. Thanks to MOSFET switching devices, this technology is able to approach this echelon closer than any other previous design. Neither Class-A nor Class-AB boasts efficiencies above 50 or 80% respectively.27 The theory behind this is illustrated in the What is Class-D section of this report. The method by which efficiency would be maximized would be to first find the most ideal MOSFET switches. Since ideal switches do not exist, there are a few specifications that require special concern. A closer look into these specifications was done in the Background section of this report. Before one can name these categories, it is prudent to look at the equations that govern power loss in switches. These equations are found in Table 5.

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SwitchingPowerLoss (Gate − Source) = Qg * V gs * f clk = [Watts]

Conduction( DC ) Loss = VRds * I d / 2 = [Watts] ⎡⎛ 2 Rds C.L. = ⎢⎜⎜ R ⎣⎝ Load + 2 Rds

⎞ ⎤ ⎡ ⎤ Vds ⎟⎟Vds ⎥ * ⎢ ⎥/2 R + 2 R ds ⎦ ⎠ ⎦ ⎣ Load

1 SwitchingPowerLoss ( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts ] 2

Efficiency = 100 − 100 * 2 Efficiency = 100 − 100 * 2

2

C.L. =

Vds * 2 Rds

2(RLoad + 2 Rds )

2

Ploss Ptotal ( Psw,d − s + Psw, g − s + PDC ) ⎛ Vrail ⎜⎜ 2 * R ds + Rload ⎝

2

⎞ ⎟⎟ * Rds ⎠

Table 6: Power Loss and Efficiency Equations

These important specifications are therefore RDS and QG. This is discussed in the Background section on efficiency but is important to note that both RDS and QG should be minimized. These two factors greatly affect efficiency and follow the following power loss curve as shown in Figure 65.

Figure 65: Power Loss

Our decision to select the Fairchild FDP038AN06A0 PowerTrench MOSFET was based on finding the perfect match for our application. We needed a device with at least a 60 Volt break down voltage and a 50 Amp continuous current limit based on a 1Ω load. Since we found that with higher break down voltage, RDS increased, we chose a MOSFET with a break down voltage at our bare minimum of 60 Volts. Other decreases in efficiency are due to the filter components. Losses from either the capacitors or inductors can be calculated using several known equations given throughout this section. Methods by which these elements dissipate power are either conductively or in their AC characteristics. A primary concern in our filter design was the inductors. After calculating the appropriate values for these components, we needed to send our specifications to a custom winding company for 81

manufacture. Each inductor had to withstand the same amount of current as each MOSFET. Using a 1Ω resistive load, this current would peak to 50 Amps at 50 Volts. Therefore, above average gauge wire had to be used. The windings were made with 10 gauge wire and RDC of less than 20mΩ. Now that all the conduction loss resistances are known, the total conduction loss can be calculated from the MOSFET, inductor, and load values. Conduction( DC ) Loss = Vdrop * I d = [Watts] ⎡⎛ ⎤ ⎡ ⎤ ⎞ 2(RMOSFET + Rinductor ) Vrail ⎟⎟Vrail ⎥ * ⎢ C.L. = ⎢⎜⎜ ⎥ ⎣⎝ RLoad + 2(RMOSGET + Rinductor ) ⎠ ⎦ ⎣ RLoad + 2(RMOSGET + Rinductor ) ⎦ Vrail * 2(RMOSGET + Rinductor ) 2

C.L. =

=

(RLoad + 2(RMOSGET + Rinductor ))2

42 2 * 2(3.8mΩ + 20mΩ ) = 5.13W (4 + 2(3.8mΩ + 20mΩ ))2

Some additional power loss is due to the capacitors. A perfect capacitor would be lossless and return each bit of energy it had stored. However, the ESR (Equivalent Series Resistance) rating of a capacitor is a particular evaluation of quality given to each series of manufactured devices. Ideally this value would be zero and therefore would have no AC resistance. In order to calculate the ESR for a given capacitor, one must start by finding its dissipation factor. In our case, we used capacitors with a dissipation factor of < 1% @ 20°C at 1 kHz. Using a value of 1% and the following equations, we can solve for the ESR at a switching frequency of 192 kHz.

ESR =

δ=

ESR Xc

Xc =

1 2πCf

ESR =

δ 2πCf

.01 = 83mΩ 2π (0.1uF )(192kHz )

ESR is not constant and changes greatly with frequency. impedance of a 0.01 µF capacitor.

82

Figure 66 shows the ideal and actual

Figure 66: Actual vs. Ideal 0.01uF Capacitor Impedance28

Using the equations for current and ESR, the power dissipated in the capacitors can be found. I =C

dV dt

I = C * ∆V * f O I = (0.1uF ) * (84V ) * (192kHz ) I = 1 .6 A

P = ( I 2 R)*# ofcaps = (12.9 A2 * 83mΩ)16 = 3.4W

Figure 67 shows power loss versus dissipation factor. This is very helpful when determining how much loss is acceptable when selecting capacitors.

83

Figure 67: Power Loss vs. Dissipation Factor

Additionally, we have plotted the power loss versus switching frequency since we have a very dynamic range of switching frequencies that may be encountered during audio amplification. See Figure 69.

Power Loss vs. Switching Frequency 40

35

Power Loss [Watts]

30

25

20

15

10

5

0 0

200,000

400,000

600,000

800,000

1,000,000

1,200,000

1,400,000

1,600,000

Switching Frequency [Hz]

Figure 68: Power Loss vs. Switching Frequency

84

1,800,000

2,000,000

Theoretical calculations are extremely difficult for MOSFET switching, conduction, and filter losses in an amplifier that use Sigma-Delta Modulation. This is due to the fact that the actual number of switches per cycle of an input signal is not known. The amount of switching that occurs corresponds to the size of the “dead zone.” The “dead-zone” is described in its own section of this report. Also, input signal size has an affect on the efficiency. On one extreme, much too large an input will result in clipping and minimal switching. In this case, the MOSFET devices need only to switch twice per cycle. On the other hand, a small input signal creates the most uncertainty in the output and maximum amount of switching will occur. In this case or any in between, the number of switches per cycle is not known. In order to demonstrate this, we have plotted the “ideal” efficiency versus switching frequency in Figure 69 using the equations in Table 5.


Efficiency

70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 Clock Speed [MHz] Constant Switching

Clipped 800Hz Signal

Figure 69: Efficiency vs. Switching Speed

The results are as predicted. The efficiency of a constantly switched output is very poor and decreases linearly due to the frequency that the MOSFETs switch. Conversely, if the input signal is large and the output is clipped, the efficiency remains at 99.8%. We decided to plot our actual efficiency results using three different input conditions on the same axis as the predicted results. The first case was an unclipped 800 Hz sine wave. The second signal

85

was clipped 40% of the time. Finally, the last was a 100% clipped sine wave, or essentially a square wave. This is plotted in Figure 70.


Efficiency

70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 Clock Speed [MHz] 0% Clipped, 1.4Vin Constant Switching

40% Clipped, 1.6Vin Clipped 800Hz Signal

100% Clipped, 3.0Vin

Figure 70: Efficiency vs. Clock Speed

By analyzing the two simultaneously, we can see that the theoretical efficiency is lower than that obtained. Clearly something is happening that prevents the measured efficiency from dropping below the theoretical efficiency. The fact that the output MOSFET switches are not being toggled during each clock tick like in some configurations is not shown here. The only real data that we can abstract is a difference of nearly 5% difference in efficiency between an ideally clipped and actually clipped output. This would suggest that much more loss is due to conduction than expected. In fact, this would explain the warming of the MOSFET switches at high current. If this 5% were to be explained by a direct series resistance, that value would be 221mΩ solved for in the next few equations.

Efficiency =

Requiv Requiv + RLOAD

Requiv = 221mΩ

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Based on the fact that this amplifier was able to reproduce an unclipped sine wave at 92% efficiency, 32 Watts of power loss, would suggest a maximum number of 3.5 million switches per second or 1.75 MHz at theoretical conditions. These values can be found using Figure 68 The factors mentioned in this section have played a major part of determining the efficiency of our amplifier design. In summary, the lack of lossless capacitors, wires without resistance, and perfect MOSFET switches can not be avoided. Because we had a fairly large budget, we found the components that were most detrimental to our efficiency goals and purchased the best components we could find to reduce efficiency loss.

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6 Recommendations Now that the project is completed, we recognize that there are some things that could have been done differently. There are areas for improvement in all stages of the design. This section will focus on ideas that could be implemented into the amplifier to improve upon the existing design. The first recommendation if this project is continued is that a DSP chip should be used to control the signal processing. There are several reasons for this. DSP technology has been a fiercely growing application in audio. Many home entertainment units and even car audio amplifiers now use this technology. The benefits are numerous as the possibilities of signal processing with DSP are nearly limitless. First, is that the signal to noise ratio would be much higher, resulting in a cleaner sounding output. The cleaner sounding output is made by the much higher switching speed of the amplifier. Therefore if quantization noise can be pushed into the megahertz band, filtering becomes simpler and noise in the audible band is negligible. Second, DSP processors are often equipped with multiple analog and digital inputs that may perform other tasks besides Sigma-Delta Modulation. With the use of a DSP chip, external controls could be implemented into the amplifier. For example a digital keypad could be part of the design where the user could control the volume, crossover, bass boost, or other added features into the amplifier. If DSP is not the method of choice, then there are other options as well. First, a higher ordered Sigma-delta modulator could be used. This means that the feedback taken from the load would go through several integrators instead of just one. This creates a cleaner output, but as you might expect adds a great deal of complexity to the circuit. One thing to note is that every integrator added to the circuit creates another pole. To balance this, an equal number of zeros must be added to keep the system stable. Second, potentiometers could be used instead of resistors from the input signal to control the volume of the amplifier or to add a high or low-pass crossover. Typically, Class-D amplifiers are not used for full-range audio applications, but if the application requires a small frequency bandwidth, there is no reason to make the amplifier do more work than it has to. Our amplifier was designed to reproduce the full audible bandwidth of 20-20 kHz. If this was not such a stringent requirement, a lower switching speed could be used to further push the efficiency limitations. Lastly, all the components in the amplifier were designed for a 50 Amps maximum current draw. By reducing the impedance of the load, the amplifier may be tested at these more extreme levels. 88

While the components in our amplifier were designed to be able to run at a 1Ω load, the system will become unstable. The reason for this is because the inductors that were purchased for the project were very costly, and in order to push the poles further from each other, a different inductor value would have to have been chosen. By redesigning the filter, it is possible to achieve a phase margin of greater than 45° at a 1Ω load. It is imperative that these inductors be similarly rated for 50 Amps of current. At the very least, a future MQP group could improve our current signal processing circuit in a few ways. The first and most immediate impact would be to compare several different operational amplifiers. While the LF356 model chip used in our circuit is widely accepted for many applications, there are new technologies that deserve to be explored. Many of these technologies boast low-voltage offset, less jitter, and higher slew rates. These op-amps would be more able to accurately reproduce high frequency noise which would allow for more noise to be filtered out. If information is lost in translation through these devices, the risk of noise slipping through is greatly increased. Lastly, many basic components used in the signal processing portion of the amplifier could be replaced with more finely tuned values. These include both resistor and capacitor values and ratings. Many parts were used because of their accessibility through the WPI ECE Shop with short notice. Capacitors were all special ordered but their values were determined by manufactures’ data sheets only. Larger bypass capacitors may reduce the noise due to instant current demands and they may also increase stability. Resistor packages are available that deviate less than 1% of the measured value and they could be used as input to the instrumentation amplifier or differential feedback attenuator. Additionally, instrumentation amplifiers are available that would replace the need for these resistor packages and op-amp. While many of these upgrades would cost significantly more money, their nonmonetary value may make them worthwhile.

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7 Conclusions This project was deemed a success. An amplifier was designed, constructed, and tested that met all of the project goals. The first project goal to mention is the fact that amplifier is capable of reaching 95% efficiency. The goal was surpassed when the amplifier was tested under a 100% clipped input sine wave, at 800 Hz, using a 42 Volt supply. If you are skeptical about using a fully clipped input signal to achieve a maximum efficiency, we are pleased to announce that an efficiency of 92% was achieved using a purely sinusoidal input at 800 Hz once again with a 42 Volt supply. From the measurements taken of our amplifier, it was determined that a clock speed of 1.5 MHz would yield the highest efficiency. Another project goal was to design the amplifier around the 42 PowerNet Standard. With that said, the amplifier must also maintain a constant power throughout the fluctuations in voltage that will occur in a real-life car application. The amplifier was tested from 48 Volts all the way down to 30 Volts to observe the amplifier's response. The amplifier acted just as intended and the output power did not change more than 3 Watts over the swing in voltage. In the audio world, there is no point in making an amplifier unless the output is an amplified version of the input. Our amplifier was capable of driving a 4Ω speaker with a max power of 500 Watts and an RMS power of 400 Watts. At low volumes, the noise coming from the speaker was apparent but as the volume increased the noise became less and less noticeable. The noise is largely due to the tradeoff that is made with the "dead-zone" voltage. With a dead-zone voltage too high, acoustic clarity gets lost but efficiency goes up. For the opposite case, with a really small dead-zone voltage, acoustic clarity improves but the efficiency suffers. The dead-zone voltage that suited the amplifier's purposes the best was 50 mVolts. Lastly, it is believed that the amplifier that has been constructed could be marketable with a little more time. The amplifier currently has a footprint size of only 29 square inches, making the power to size ratio much higher than that of other amplifiers on the market. If more time was allowed to be spent on the design of an EMI shield that would double as a heat sink for the amplifier, the amplifier could be located anywhere in an automobile regardless of a vehicle’s central computer location. This would also make the amplifier very marketable.

90

8 References Beranek, Leo L. Acoustics. New York: Acoustical Society of America, 1996. Boylestad, L. Nashelsky. Electronic Devices and Circuit Theory. New Jersey: Prentice Hall, 1992 Haag, Michael. Understanding Pole/Zero Plots on the Z-Plane. July 2003, Incropera & DeWitt. Introduction to Heat Transfer 4th ed. New York: John Wiley & Sons, Inc. 2002 Mohan, Ned. Power Electronics and Drives. Minnesota: MNPERE, 2003. Pohlmann, K.C. Principles of Digital Audio, 3rd ed. New York: McGraw-Hill, 1995. Robichaud, Jon. Interview. Heat Transfer & Metal Properties. Leominster, 23 Sept. 2003 Sedra & Smith. Microelectronic Circuits 4th ed. New York: Oxford University Press, 1998.

1

http://www.cpemma.co.uk/pwm.html www.xtant.com/html/products/xtant1.1i.cfm 3 http://www.numerix-dsp.com/appsnotes/APR8-sigma-delta.pdf 4 http://skyvision.com/pages/information_center/hdtvfaq.html#t7 5 http://www.epanorama.net/documents/audio/spdif.html 6 http://www.sci-worx.com/internet/bordnetzforum/bnvill.pdf 7 http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=PCM1738 8 Class D Audio Amplifier, WPI MQP, 2003 9 http://www.web-ee.com/primers/files/DesignSem3.pdf 10 http://www.tripath.com/downloads/an11.pdf 11 Incropera & DeWitt , p53 12 Robichaud 13 http://www.diamondman.com/usesb3.htm 14 Mohan, p2-9 15 http://www.fairchildsemi.com/whats_new/30vauto_nph.html 16 Pohlmann, p154. 17 See Appendix on Efficiency Calculations 18 Sedra & Smith, p76. 19 Sedra & Smith, p89. 20 Haag, p1. 21 Haag, p2. 22 Ogata, Katsuhiko, Modern Control Engineering, Prentice Hall, 2002, p539. 23 Beranek, pg. 395. 24 www.4pcb.com 25 Beranek, pg 253. 26 Appendix Amplifier research 27 Boylestad, ch15. 28 http://newson-consulting.com/emi-capacitors.htm 2

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Appendix Manufacturer

Vbrdss Rds Id (break (mOhm, at Vin Gate Charge (Qg) Pmax (Watts) (25degC) down) Vgs=10V)

Part #

tON (nsec)

tOFF (nsec)

Max Switching Speed

Fairchild

FDP038AN06A0

60

80

3.8

10

95

310

163

75

4.20E+06

Fairchild Fairchild IRF Fairchild Fairchild Fairchild Fairchild IRF IRF Fairchild IRF

FDP050AN06A0 HUF76443P3 IRFP064V FDP10AN06A0 HUF76445P3 FDP13AN06A0 FDP14AN06LA0 IRFP064 IRFP054 FQP50N06L IRFZ44E

60 60 60 60 60 60 60 60 60 60 60

80 75 130 75 75 62 61 70 70 52 48

5 8 5.5 10.5 6.5 13.5 11 9 14 21 23

10 10 10 10 10 10 10 10 10 10 10

61 107 173.3 28 124 22 24 126.7 106.7 24.5 40

245 260 250 135 310 115 125 300 230 121 110

264 195 226 206 205 158 276 211 180 380 72

86 100 250 94 295 74 109 300 233 145 140

2.86E+06 3.39E+06 2.10E+06 3.33E+06 2.00E+06 4.31E+06 2.60E+06 1.96E+06 2.42E+06 1.90E+06 4.72E+06

MOSFET Specifications

Manufacturer

Part #

Fairchild

FDP038AN06A0

Fairchild Fairchild IRF Fairchild Fairchild Fairchild Fairchild IRF IRF Fairchild IRF

FDP050AN06A0 HUF76443P3 IRFP064V FDP10AN06A0 HUF76445P3 FDP13AN06A0 FDP14AN06LA0 IRFP064 IRFP054 FQP50N06L IRFZ44E

G-S Switching Loss (Watts, Vin=10V, fclk=192kHz)

1Ohm 2Ohm 4Ohm 8Ohm D-S Switching D-S Switching D-S Switching D-S Switching Conduction Loss (Watts, Conduction Loss (Watts, Conduction Loss (Watts, Conduction Loss (Watts, Efficiency Efficiency Efficiency Efficiency Loss Vin=10V,fclk=1 Loss Vin=10V,fclk=1 Loss Vin=10V,fclk=1 Loss Vin=10V,fclk=1 92kHz) 92kHz) 92kHz) 92kHz)

0.182

6.60

9.52

98.14%

1.66

4.78

98.49%

0.42

2.39

98.64%

0.10

1.20

98.65%

0.117 0.205 0.333 0.054 0.238 0.042 0.046 0.243 0.205 0.047 0.077

8.65 13.67 9.49 17.77 11.17 22.58 18.58 15.32 23.37 34.12 37.08

13.97 11.71 18.98 11.85 19.90 9.11 15.19 20.24 16.20 20.31 8.17

97.40% 97.05% 96.70% 96.57% 96.40% 96.31% 96.08% 95.87% 95.36% 93.56% 94.62%

2.18 3.47 2.40 4.53 2.83 5.80 4.75 3.90 6.00 8.88 9.69

7.02 5.90 9.54 5.99 10.01 4.61 7.68 10.21 8.21 10.37 4.18

97.88% 97.81% 97.20% 97.58% 97.01% 97.60% 97.14% 96.72% 96.68% 95.53% 96.76%

0.55 0.87 0.60 1.15 0.71 1.47 1.20 0.98 1.52 2.27 2.48

3.52 2.96 4.78 3.01 5.02 2.32 3.86 5.13 4.13 5.24 2.11

98.10% 98.16% 97.40% 98.08% 97.28% 98.25% 97.67% 97.11% 97.32% 96.54% 97.86%

0.14 0.22 0.15 0.29 0.18 0.37 0.30 0.25 0.38 0.57 0.63

1.76 1.48 2.40 1.51 2.52 1.17 1.94 2.57 2.07 2.63 1.06

98.17% 98.27% 97.38% 98.32% 97.34% 98.56% 97.92% 97.22% 97.58% 97.03% 98.39%

MOSFET Efficiency Calculations

92

93

MOSFET Efficiency Equations Conduction( DC ) Loss = VRds * I d / 2 = [Watts] MaxSwitchingSpeed =

1 = [ Hz ] t rise + t fall

⎡⎛ 2 Rds C.L. = ⎢⎜⎜ R ⎣⎝ Load + 2 Rds

⎞ ⎤ ⎡ ⎤ Vds ⎟⎟Vds ⎥ * ⎢ ⎥/2 R + 2 R ds ⎦ ⎠ ⎦ ⎣ Load

2

C.L. =

SwitchingPowerLoss(Gate − Source) = Qg * V gs * f clk = [Watts]

Vds * 2 Rds

2(RLoad + 2 Rds )

2

1 SwitchingPowerLoss( Drain − Source) = Vin I o (t ON + t OFF ) f s = [Watts] 2

a) Maximum Switching Speed [Hz] – the fastest a device can switch on and off based on its rise time and fall time. Since Hertz is simply the reciprocal of time in seconds, we can calculate the maximum switching speed by adding the rise and fall times and dividing 1 by this number. b) Conduction Loss (DC) [Watts] – power loss due to current flowing from the drain to source of a MOSFET device. This equation assumes DC current or current that is steady. In order to calculate DC loss, we can begin with the equation P=I*V where V is the rail voltage and current is the drain-source current. Since we are only concerned with one of the MOSFETS, we can divide by 2. The voltage across each MOSFET is given by the ratio of its resistance relative to 2 Rds the resistance of the load, . The drain-source current is then the ratio of the rail RLoad + 2 Rds Vds . The simplified voltage over the total resistance of the MOSFETs and the load, RLoad + 2 Rds conduction loss equation can be found in the table above. c) Switching Power Loss (Gate-Source) – power loss due to the charging of the gate-source capacitance of the system in order to reach the gate-source voltage. This can be found by multiplying the gate charge (Qg), gate-source voltage (Vgs), and switching speed (fclk). d) Switching Power Loss (Drain-Source) – power loss due to the charging of the drain-source capacitance of the system in order to reach the drain-source voltage. Equation was taken from Power Electronics and Drives, p2-9

94

Max Power [RMS Watts]

2500

2000

1500

1000

500

0 0

25

50

75

125

Competition

150

175

Competition Best Fit

Footprint Size [Sq. In]

100

Our Amplifier

200

225

250

Class - D Car Audio Amplifier Dimensions Max Total Power (RMS Watts) Alpine MRD-M100 700 Alpine MRD-M500 400 Alpine MRD-M300 200 ArcAudio 1500D-XXK 1000 ArcAudio 1500D-R 1000 Audiobahn A18001DT 1800 Audiobahn A12001DT 1200 Audiobahn A8001DT 800 Autotek MX2000 1200 Autotek MX5000 2200 Boss R1400D 800 Boss R2200D 1400 Boss R3000D 2200 Crossfire VR-300D 300 Crossfire VR-600D 600 Crossfire VR-1000D 1000 Crossfire VR-2000D 2000 Eclipse DA7122 1000 Eclipse DA7232 2000 Kenwood KAC-X810D 800 Kicker SX1250.1 1250 Kicker SX650.1 650 Kicker KX1200.1 1200 Kicker KX600.1 600 Kicker KX400.1 400 MA Audio HK-2000D 1500 MA Audio HK-4000D 3600 MA Audio SY7011DX 1500 MA Audio SY5011DX 1000 MA Audio H2KTP 2000 Memphis MC250D 250 Memphis MC500D 500 Memphis MC100D 1100 Memphis MC1500D 1500 Memphis MC2000D 2400 MTX Thunder251D 160 MTX Thunder311D 200 MTX Thunder421D 300 MTX Thunder801D 500 MTX Thunder1501D 1000 Orion 2500D 2500 Orion 1200D 1200 Orion 600D 600 Phoenix Gold R15.0:1 1000 Phoenix Gold R8.0:1 600 Phoenix Gold R30.0:1 2000 Rockford Fosgate Power 1001bd 1000 Rockford Fosgate Power 5001bd 500 Rockford Fosgate Power 1501bd 1500 Sony XM-D1000P5 900 Sony XM-D400PS 400 Soundstream EGA900D 900 Soundstream EGA1400D 1400 Soundstream EGA1700D 1700 U.S. Acoustics USX600D 375 U.S. Acoustics USX800D 600 U.S. Acoustics USX1000D 1250 Xtant X1001 1000 Xtant 1.1i 100 Zapco C2K-9.0XD 2200 Our Amp 400 Company

Model

Height (in) 2.6772 2.6772 2.6772 2.3500 2.3500 2.5000 2.5000 2.5000 2.6575 2.6575 2.2500 2.2500 2.2500 2.1000 2.1000 2.1000 2.1000 2.0500 2.0500 2.3125 2.5000 2.5000 2.5000 2.5000 2.5000 2.7100 2.7100 2.5600 2.5600 2.6800 2.0000 2.0000 2.0000 2.0000 2.2500 2.1000 2.1000 2.1000 2.1000 2.1000 2.3000 2.3000 2.3000 2.2500 2.2500 2.2500 2.3800 2.3800 2.3800 2.2500 2.2500 2.2000 2.2000 2.2000 2.3900 2.3900 2.3900 2.1875 1.6300 2.3750

Width (in) 21.6535 12.4016 8.2677 8.0000 8.0000 11.9375 11.9375 11.9375 8.5039 8.5039 11.7500 11.7500 11.7500 9.3000 9.3000 9.3000 9.3000 11.8500 11.8500 11.3333 10.0000 10.0000 10.0000 10.0000 10.0000 12.4000 12.4000 11.6000 11.6000 8.6000 6.5000 6.5000 6.5000 6.5000 9.1250 9.7500 9.7500 9.7500 9.7500 9.7500 10.5000 10.5000 10.5000 10.8750 10.8750 10.8750 9.8500 9.8500 9.8500 13.7500 11.5000 11.0000 11.0000 11.0000 9.5000 9.5000 9.5000 10.3125 5.8100 8.7500

Length (in) 9.7244 9.7244 9.7244 15.2500 15.2500 16.6875 14.5000 13.1250 13.4252 21.6535 11.4375 14.1875 15.3750 9.5000 11.5000 14.0000 22.0000 15.7500 21.0000 13.7500 17.0000 11.0000 17.5000 11.0000 7.7500 14.2900 25.8600 16.7300 15.9000 16.1000 8.2500 10.4000 13.4000 19.0000 22.5000 8.0000 8.0000 9.4000 11.5000 17.8000 27.2000 18.7000 16.4000 16.5000 14.7500 19.7500 13.0700 13.0700 17.0700 13.3750 11.6250 12.6000 15.0000 17.7000 5.7500 10.2500 15.7500 20.6875 6.5000 19.5000

Area (LxW) 210.5673 120.5981 80.3984 122.0000 122.0000 199.2070 173.0938 156.6797 114.1666 184.1392 134.3906 166.7031 180.6563 88.3500 106.9500 130.2000 204.6000 186.6375 248.8500 155.8329 170.0000 110.0000 175.0000 110.0000 77.5000 177.1960 320.6640 194.0680 184.4400 138.4600 53.6250 67.6000 87.1000 123.5000 205.3125 78.0000 78.0000 91.6500 112.1250 173.5500 285.6000 196.3500 172.2000 179.4375 160.4063 214.7813 128.7395 128.7395 168.1395 183.9063 133.6875 138.6000 165.0000 194.7000 54.6250 97.3750 149.6250 213.3398 37.7650 170.6250 29.0000

THD S/N Ratio (%) (dB) 1.000 90 1.000 90 1.000 90 0.055 98 0.055 98 0.050 100 0.050 100 0.050 100 90 90 100 100 100 0.080 90 0.080 90 0.080 90 0.080 90 0.007 120 0.007 120 0.200 100 1.500 98 1.500 98 1.500 95 1.500 95 1.500 95 1.000 96 0.500 96 1.000 96 1.000 96 0.200 98 0.500 80 0.500 80 0.750 80 0.750 80 0.500 90 1.000 100 1.000 100 1.000 100 1.000 100 2.000 100

1.000 1.000 1.000 0.050 0.050 0.050 0.600 0.600 0.300 0.300 0.300 0.015 0.300 0.500 2.000 1.000 0.050

90 90 90 100 100 100

80 80 80 80 80 80 90 100 85

LM111/LM211/LM311 Voltage Comparator 1.0 General Description The LM111, LM211 and LM311 are voltage comparators that have input currents nearly a thousand times lower than devices like the LM106 or LM710. They are also designed to operate over a wider range of supply voltages: from standard ± 15V op amp supplies down to the single 5V supply used for IC logic. Their output is compatible with RTL, DTL and TTL as well as MOS circuits. Further, they can drive lamps or relays, switching voltages up to 50V at currents as high as 50 mA. Both the inputs and the outputs of the LM111, LM211 or the LM311 can be isolated from system ground, and the output can drive loads referred to ground, the positive supply or the negative supply. Offset balancing and strobe capability are provided and outputs can be wire OR’ed. Although slower than the LM106 and LM710 (200 ns response time vs 40 ns)

3.0 Typical Applications

the devices are also much less prone to spurious oscillations. The LM111 has the same pin configuration as the LM106 and LM710. The LM211 is identical to the LM111, except that its performance is specified over a −25˚C to +85˚C temperature range instead of −55˚C to +125˚C. The LM311 has a temperature range of 0˚C to +70˚C.

2.0 Features n n n n n

Operates from single 5V supply Input current: 150 nA max. over temperature Offset current: 20 nA max. over temperature Differential input voltage range: ± 30V Power consumption: 135 mW at ± 15V

(Note 3)

Offset Balancing

Strobing

DS005704-36

DS005704-37

Note: Do Not Ground Strobe Pin. Output is turned off when current is pulled from Strobe Pin.

Increasing Input Stage Current (Note 1)

Detector for Magnetic Transducer

DS005704-38

Note 1: Increases typical common mode slew from 7.0V/µs to 18V/µs.

DS005704-39

© 2001 National Semiconductor Corporation

DS005704

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LM111/LM211/LM311 Voltage Comparator

January 2001

LM111/LM211/LM311


(Note 3) (Continued)

Digital Transmission Isolator

Relay Driver with Strobe

DS005704-40

DS005704-41

*Absorbs inductive kickback of relay and protects IC from severe voltage transients on V++ line. Note: Do Not Ground Strobe Pin.

Strobing off Both Input and Output Stages (Note 2)

DS005704-42

Note: Do Not Ground Strobe Pin. Note 2: Typical input current is 50 pA with inputs strobed off. Note 3: Pin connections shown on schematic diagram and typical applications are for H08 metal can package.

Positive Peak Detector

Zero Crossing Detector Driving MOS Logic

DS005704-24 DS005704-23

*Solid tantalum

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2

Operating Temperature Range LM111 −55˚C to 125˚C LM211 −25˚C to 85˚C Lead Temperature (Soldering, 10 sec) 260˚C Voltage at Strobe Pin V+−5V Soldering Information Dual-In-Line Package Soldering (10 seconds) 260˚C Small Outline Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. ESD Rating (Note 11) 300V

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Total Supply Voltage (V84) Output to Negative Supply Voltage (V74) Ground to Negative Supply Voltage (V14) Differential Input Voltage Input Voltage (Note 4) Output Short Circuit Duration

36V 50V 30V ± 30V ± 15V 10 sec

Electrical Characteristics (Note 6) for the LM111 and LM211 Parameter Input Offset Voltage (Note 7)

Typ

Max

Units

TA =25˚C, RS≤50k

Conditions

Min

0.7

3.0

mV nA

Input Offset Current

TA =25˚C

4.0

10

Input Bias Current

TA =25˚C

60

100

Voltage Gain

TA =25˚C

Response Time (Note 8)

nA

200

V/mV

TA =25˚C

200

ns

VIN≤−5 mV, IOUT =50 mA

0.75

1.5

V

TA =25˚C

2.0

5.0

mA

VIN≥5 mV, VOUT =35V

0.2

10

nA

4.0

mV

Input Offset Current (Note 7)

20

nA

Input Bias Current

150

nA

13.8,-14.7

13.0

V

0.23

0.4

V

VIN≥5 mV, VOUT =35V

0.1

0.5

µA

Positive Supply Current

TA =25˚C

5.1

6.0

mA

Negative Supply Current

TA =25˚C

4.1

5.0

mA

Saturation Voltage

40

TA =25˚C Strobe ON Current (Note 9) Output Leakage Current

TA =25˚C, ISTROBE =3 mA Input Offset Voltage (Note 7)

Input Voltage Range

RS≤50 k

V+ =15V, V− =−15V, Pin 7

−14.5

Pull-Up May Go To 5V Saturation Voltage

V+≥4.5V, V− =0 VIN≤−6 mV, IOUT≤8 mA

Output Leakage Current

Note 4: This rating applies for ± 15 supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is equal to the negative supply voltage or 30V below the positive supply, whichever is less. Note 5: The maximum junction temperature of the LM111 is 150˚C, while that of the LM211 is 110˚C. For operating at elevated temperatures, devices in the H08 package must be derated based on a thermal resistance of 165˚C/W, junction to ambient, or 20˚C/W, junction to case. The thermal resistance of the dual-in-line package is 110˚C/W, junction to ambient. Note 6: These specifications apply for VS = ± 15V and Ground pin at ground, and −55˚C≤TA≤+125˚C, unless otherwise stated. With the LM211, however, all temperature specifications are limited to −25˚C≤TA≤+85˚C. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5V supply up to ± 15V supplies. Note 7: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1 mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and RS. Note 8: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive. Note 9: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. Do not short the strobe pin to ground; it should be current driven at 3 to 5 mA. Note 10: Refer to RETS111X for the LM111H, LM111J and LM111J-8 military specifications. Note 11: Human body model, 1.5 kΩ in series with 100 pF.

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LM111/LM211/LM311

4.0 Absolute Maximum Ratings for the LM111/LM211(Note 10)

LM111/LM211/LM311

5.0 Absolute Maximum Ratings for the LM311(Note 12)

Operating Temperature Range 0˚ to 70˚C Storage Temperature Range −65˚C to 150˚C Lead Temperature (soldering, 10 sec) 260˚C Voltage at Strobe Pin V+−5V Soldering Information Dual-In-Line Package Soldering (10 seconds) 260˚C Small Outline Package Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Total Supply Voltage (V84) Output to Negative Supply Voltage (V74) Ground to Negative Supply Voltage (V14) Differential Input Voltage Input Voltage (Note 13) Power Dissipation (Note 14) ESD Rating (Note 19) Output Short Circuit Duration

36V 40V 30V ± 30V ± 15V 500 mW 300V 10 sec

Electrical Characteristics (Note 15) for the LM311 Typ

Max

Units

Input Offset Voltage (Note 16)

Parameter

TA =25˚C, RS≤50k

Conditions

Min

2.0

7.5

mV

Input Offset Current(Note 16)

TA =25˚C

6.0

50

nA

Input Bias Current

TA =25˚C

100

250

nA

Voltage Gain

TA =25˚C

Response Time (Note 17)

TA =25˚C

200

Saturation Voltage

VIN≤−10 mV, IOUT =50 mA

0.75

1.5

V

2.0

5.0

mA

0.2

50

nA

40

200

V/mV ns

TA =25˚C Strobe ON Current (Note 18)

TA =25˚C

Output Leakage Current

VIN≥10 mV, VOUT =35V TA =25˚C, ISTROBE =3 mA V− = Pin 1 = −5V

Input Offset Voltage (Note 16)

RS≤50K

Input Offset Current (Note 16) Input Bias Current Input Voltage Range Saturation Voltage

−14.5 V+≥4.5V, V− =0

10

mV

70

nA

300

nA

13.8,−14.7

13.0

V

0.23

0.4

V

VIN≤−10 mV, IOUT≤8 mA Positive Supply Current

TA =25˚C

5.1

7.5

mA

Negative Supply Current

TA =25˚C

4.1

5.0

mA

Note 12: “Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.” Note 13: This rating applies for ± 15V supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is equal to the negative supply voltage or 30V below the positive supply, whichever is less. Note 14: The maximum junction temperature of the LM311 is 110˚C. For operating at elevated temperature, devices in the H08 package must be derated based on a thermal resistance of 165˚C/W, junction to ambient, or 20˚C/W, junction to case. The thermal resistance of the dual-in-line package is 100˚C/W, junction to ambient. Note 15: These specifications apply for VS = ± 15V and Pin 1 at ground, and 0˚C < TA < +70˚C, unless otherwise specified. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5V supply up to ± 15V supplies. Note 16: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with 1 mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and RS. Note 17: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive. Note 18: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. Do not short the strobe pin to ground; it should be current driven at 3 to 5 mA. Note 19: Human body model, 1.5 kΩ in series with 100 pF.

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LM111/LM211/LM311

6.0 LM111/LM211 Typical Performance Characteristics Input Bias Current

Input Bias Current

DS005704-43

Input Bias Current

DS005704-44

Input Bias Current

DS005704-46 DS005704-45

Input Bias Current

Input Bias Current

DS005704-47

DS005704-48

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LM111/LM211/LM311

6.0 LM111/LM211 Typical Performance Characteristics Input Bias Current Input Overdrives

(Continued)

Input Bias Current Input Overdrives

DS005704-50

DS005704-49

Input Bias Current

Response Time for Various Input Overdrives

DS005704-51

DS005704-52


Output Limiting Characteristics

DS005704-54

DS005704-53

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Supply Current

LM111/LM211/LM311

6.0 LM111/LM211 Typical Performance Characteristics

(Continued)

Supply Current

DS005704-55

DS005704-56

Leakage Currents

DS005704-57

7.0 LM311 Typical Performance Characteristics Input Bias Current


DS005704-58

DS005704-59

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LM111/LM211/LM311

7.0 LM311 Typical Performance Characteristics Offset Error

(Continued)

Input Characteristics

DS005704-61

DS005704-60

Common Mode Limits

Transfer Function

DS005704-62


DS005704-63


DS005704-64

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DS005704-65

8

Output Saturation Voltage

LM111/LM211/LM311

7.0 LM311 Typical Performance Characteristics

(Continued)


DS005704-66

DS005704-67


Output Limiting Characteristics

DS005704-69

DS005704-68

Supply Current

Supply Current

DS005704-70

DS005704-71

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LM111/LM211/LM311

7.0 LM311 Typical Performance Characteristics

(Continued)

Leakage Currents

DS005704-72

8.0 Application Hints 8.1 CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS When a high-speed comparator such as the LM111 is used with fast input signals and low source impedances, the output response will normally be fast and stable, assuming that the power supplies have been bypassed (with 0.1 µF disc capacitors), and that the output signal is routed well away from the inputs (pins 2 and 3) and also away from pins 5 and 6. However, when the input signal is a voltage ramp or a slow sine wave, or if the signal source impedance is high (1 kΩ to 100 kΩ), the comparator may burst into oscillation near the crossing-point. This is due to the high gain and wide bandwidth of comparators like the LM111. To avoid oscillation or instability in such a usage, several precautions are recommended, as shown in Figure 1 below. 1. The trim pins (pins 5 and 6) act as unwanted auxiliary inputs. If these pins are not connected to a trim-pot, they should be shorted together. If they are connected to a trim-pot, a 0.01 µF capacitor C1 between pins 5 and 6 will minimize the susceptibility to AC coupling. A smaller capacitor is used if pin 5 is used for positive feedback as in Figure 1. 2. Certain sources will produce a cleaner comparator output waveform if a 100 pF to 1000 pF capacitor C2 is connected directly across the input pins. 3. When the signal source is applied through a resistive network, RS, it is usually advantageous to choose an RS' of substantially the same value, both for DC and for dynamic (AC) considerations. Carbon, tin-oxide, and metal-film resistors have all been used successfully in comparator input circuitry. Inductive wirewound resistors are not suitable. 4. When comparator circuits use input resistors (eg. summing resistors), their value and placement are particularly important. In all cases the body of the resistor should be close to the device or socket. In other words there should be very little lead length or printed-circuit foil run between comparator and resistor to radiate or pick up signals. The same applies to capacitors, pots, etc. For example, if RS =10 kΩ, as little as 5 inches of lead between the resistors and the input pins can result www.national.com

5.

6.

10

in oscillations that are very hard to damp. Twisting these input leads tightly is the only (second best) alternative to placing resistors close to the comparator. Since feedback to almost any pin of a comparator can result in oscillation, the printed-circuit layout should be engineered thoughtfully. Preferably there should be a groundplane under the LM111 circuitry, for example, one side of a double-layer circuit card. Ground foil (or, positive supply or negative supply foil) should extend between the output and the inputs, to act as a guard. The foil connections for the inputs should be as small and compact as possible, and should be essentially surrounded by ground foil on all sides, to guard against capacitive coupling from any high-level signals (such as the output). If pins 5 and 6 are not used, they should be shorted together. If they are connected to a trim-pot, the trim-pot should be located, at most, a few inches away from the LM111, and the 0.01 µF capacitor should be installed. If this capacitor cannot be used, a shielding printed-circuit foil may be advisable between pins 6 and 7. The power supply bypass capacitors should be located within a couple inches of the LM111. (Some other comparators require the power-supply bypass to be located immediately adjacent to the comparator.) It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and to avoid excessive noise on the output because the comparator is a good amplifier for its own noise. In the circuit of Figure 2, the feedback from the output to the positive input will cause about 3 mV of hysteresis. However, if RS is larger than 100Ω, such as 50 kΩ, it would not be reasonable to simply increase the value of the positive feedback resistor above 510 kΩ. The circuit of Figure 3 could be used, but it is rather awkward. See the notes in paragraph 7 below.

7.

tive supply. This signal is centered around the nominal voltage at pin 5, so this feedback does not add to the VOS of the comparator. As much as 8 mV of VOS can be trimmed out, using the 5 kΩ pot and 3 kΩ resistor as shown.

(Continued)

When both inputs of the LM111 are connected to active signals, or if a high-impedance signal is driving the positive input of the LM111 so that positive feedback would be disruptive, the circuit of Figure 1 is ideal. The positive feedback is to pin 5 (one of the offset adjustment pins). It is sufficient to cause 1 to 2 mV hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. The positive-feedback signal across the 82Ω resistor swings 240 mV below the posi-

8.

These application notes apply specifically to the LM111, LM211, LM311, and LF111 families of comparators, and are applicable to all high-speed comparators in general, (with the exception that not all comparators have trim pins).

DS005704-29

Pin connections shown are for LM111H in the H08 hermetic package

FIGURE 1. Improved Positive Feedback

DS005704-30

Pin connections shown are for LM111H in the H08 hermetic package

FIGURE 2. Conventional Positive Feedback

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LM111/LM211/LM311

8.0 Application Hints

LM111/LM211/LM311

8.0 Application Hints

(Continued)

DS005704-31

FIGURE 3. Positive Feedback with High Source Resistance


(Pin numbers refer to H08 package)

Zero Crossing Detector Driving MOS Switch

100 kHz Free Running Multivibrator

DS005704-13

DS005704-14

*TTL or DTL fanout of two

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LM111/LM211/LM311


(Pin numbers refer to H08 package) (Continued)

10 Hz to 10 kHz Voltage Controlled Oscillator

DS005704-15

*Adjust for symmetrical square wave time when VIN = 5 mV †Minimum capacitance 20 pF Maximum frequency 50 kHz

Driving Ground-Referred Load

Using Clamp Diodes to Improve Response

DS005704-17

DS005704-16

*Input polarity is reversed when using pin 1 as output.

TTL Interface with High Level Logic

DS005704-18

*Values shown are for a 0 to 30V logic swing and a 15V threshold. †May be added to control speed and reduce susceptibility to noise spikes.

13

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LM111/LM211/LM311


(Pin numbers refer to H08 package) (Continued)

Crystal Oscillator

Comparator and Solenoid Driver

DS005704-20

DS005704-19

Precision Squarer

DS005704-21

*Solid tantalum †Adjust to set clamp level

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LM111/LM211/LM311


(Pin numbers refer to H08 package) (Continued) Low Voltage Adjustable Reference Supply

DS005704-22

*Solid tantalum

Positive Peak Detector

Zero Crossing Detector Driving MOS Logic

DS005704-24 DS005704-23

*Solid tantalum

Negative Peak Detector

DS005704-25

*Solid tantalum

15

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LM111/LM211/LM311


(Pin numbers refer to H08 package) (Continued) Precision Photodiode Comparator

DS005704-26

*R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by an order of magnitude.

Switching Power Amplifier

DS005704-27

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LM111/LM211/LM311


(Pin numbers refer to H08 package) (Continued) Switching Power Amplifier

DS005704-28

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LM111/LM211/LM311

10.0 Schematic Diagram

(Note 20)

DS005704-5

Note 20: Pin connections shown on schematic diagram are for H08 package.

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18

LM111/LM211/LM311

11.0 Connection Diagrams Metal Can Package

DS005704-6

Note: Pin 4 connected to case

Top View Order Number LM111H, LM111H/883(Note 21) , LM211H or LM311H See NS Package Number H08C Dual-In-Line Package

Dual-In-Line Package

DS005704-34

Top View Order Number LM111J-8, LM111J-8/883(Note 21), LM311M, LM311MX or LM311N See NS Package Number J08A, M08A or N08E

DS005704-35

Top View Order Number LM111J/883(Note 21) See NS Package Number J14A or N14A

DS005704-33

Order Number LM111W/883(Note 21), LM111WG/883 See NS Package Number W10A, WG10A Note 21: Also available per JM38510/10304

19

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LM111/LM211/LM311

12.0 Physical Dimensions

inches (millimeters) unless otherwise noted

Metal Can Package (H) Order Number LM111H, LM111H/883, LM211H or LM311H NS Package Number H08C

Cavity Dual-In-Line Package (J) Order Number LM111J-8, LM111J-8/883 NS Package Number J08A

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20

LM111/LM211/LM311


inches (millimeters) unless otherwise noted (Continued)

Dual-In-Line Package (J) Order Number LM111J/883 NS Package Number J14A

Dual-In-Line Package (M) Order Number LM311M, LM311MX NS Package Number M08A

21

www.national.com

LM111/LM211/LM311



Dual-In-Line Package (N) Order Number LM311N NS Package Number N08E

Order Number LM111W/883, LM111WG/883 NS Package Number W10A, WG10A

www.national.com

22

LM111/LM211/LM311 Voltage Comparator

Notes

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com

National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected]

National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

FDP038AN06A0 / FDI038AN06A0 N-Channel PowerTrench® MOSFET 60V, 80A, 3.8mΩ Features

Applications

• r DS(ON) = 3.5mΩ (Typ.), V GS = 10V, ID = 80A

• Motor / Body Load Control

• Qg(tot) = 95nC (Typ.), VGS = 10V

• ABS Systems

• Low Miller Charge

• Powertrain Management

• Low QRR Body Diode

• Injection Systems

• UIS Capability (Single Pulse and Repetitive Pulse)

• DC-DC converters and Off-line UPS

• Qualified to AEC Q101

• Distributed Power Architectures and VRMs

Formerly developmental type 82584

• Primary Switch for 12V and 24V systems

SOURCE DRAIN

DRAIN (FLANGE)

D

SOURCE GATE

DRAIN

G

GATE

TO-220AB

DRAIN (FLANGE)

FDP SERIES

TO-262AB

S

FDI SERIES

MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol VDSS

Drain to Source Voltage

Parameter

Ratings 60

Units V

VGS

Gate to Source Voltage

±20

V

Drain Current ID

Continuous (TC < 151oC, VGS = 10V)

80

A

Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 62oC/W)

17

A

Pulsed E AS PD TJ, TSTG

Single Pulse Avalanche Energy (Note 1)

Figure 4

A

625

mJ

Power dissipation

310

W

Derate above 25oC

2.07

W/oC

Operating and Storage Temperature

o

-55 to 175

C

Thermal Characteristics RθJC

Thermal Resistance Junction to Case TO-220, TO-262

RθJA

Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2)

0.48

o

C/W

62

o

C/W

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

©2002 Fairchild Semiconductor Corporation

FDP038AN06A0 / FDI038AN06A0 Rev. A1

FDP038AN06A0 / FDI038AN06A0

August 2002

Device Marking FDP038AN06A0

Device FDP038AN06A0

Package TO-220AB

Reel Size Tube

Tape Width N/A

Quantity 50 units

FDI038AN06A0

FDI038AN06A0

TO-262AB

Tube

N/A

50 units

Electrical Characteristics TC = 25°C unless otherwise noted Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics B VDSS

Drain to Source Breakdown Voltage

IDSS

Zero Gate Voltage Drain Current

IGSS

Gate to Source Leakage Current

ID = 250µA, VGS = 0V

60

-

-

V

-

-

1

-

-

250

µA

VGS = ±20V

-

-

±100

nA

-

4

V

VDS = 50V VGS = 0V

TC = 150oC

On Characteristics VGS(TH)

rDS(ON)

Gate to Source Threshold Voltage

Drain to Source On Resistance

VGS = VDS, ID = 250µA

2

ID = 80A, VGS = 10V

-

0.0035 0.0038

ID = 40A, VGS = 6V

-

0.0049 0.0074

ID = 80A, VGS = 10V, TJ = 175oC

-

0.0071 0.0078

Ω

Dynamic Characteristics CISS

Input Capacitance

COSS

Output Capacitance

CRSS

Reverse Transfer Capacitance

VDS = 25V, VGS = 0V, f = 1MHz

Qg(TOT)

Total Gate Charge at 10V

VGS = 0V to 10V

Qg(TH)

Threshold Gate Charge

VGS = 0V to 2V

Qgs

Gate to Source Gate Charge

Qgs2

Gate Charge Threshold to Plateau

Qgd

Gate to Drain “Miller” Charge

VDD = 30V ID = 80A Ig = 1.0mA

-

6400

-

-

1123

-

pF pF

-

367

-

pF nC

95

124

-

12

15

nC

-

30

-

nC

-

18

-

nC

-

24

-

nC

ns

Switching Characteristics (VGS = 10V) tON

Turn-On Time

-

-

163

td(ON)

Turn-On Delay Time

-

15

-

ns

tr

Rise Time

-

93

-

ns

td(OFF)

Turn-Off Delay Time

-

38

-

ns

tf

Fall Time

-

13

-

ns

tOFF

Turn-Off Time

-

-

75

ns

V

VDD = 30V, ID = 80A VGS = 10V, RGS = 2.4Ω

Drain-Source Diode Characteristics ISD = 80A

-

-

1.25

ISD = 40A

-

-

1.0

V

Reverse Recovery Time

ISD = 75A, dISD/dt = 100A/µs

-

-

38

ns

Reverse Recovered Charge

ISD = 75A, dISD/dt = 100A/µs

-

-

39

nC

VSD

Source to Drain Diode Voltage

trr QRR

Notes: 1: Starting TJ = 25°C, L = 0.255mH, IAS = 70A. 2: Pulse Width = 100s




Package Marking and Ordering Information

1.2

250 CURRENT LIMITED BY PACKAGE

ID, DRAIN CURRENT (A)

POWER DISSIPATION MULTIPLIER

1.0

0.8

0.6

0.4

200

150

100

50

0.2

0 0

25

50

75

100

150

125

0 25

175

50

75

TC , CASE TEMPERATURE (o C)

100

125

TC, CASE TEMPERATURE

Figure 1. Normalized Power Dissipation vs Ambient Temperature

150

175

(o C)

Figure 2. Maximum Continuous Drain Current vs Case Temperature

2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01

ZθJC, NORMALIZED THERMAL IMPEDANCE

1

PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC

SINGLE PULSE 0.01 10-5

10-4

10-3

10-2

10-1

100

101

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance 3000

1000 IDM, PEAK CURRENT (A)

TC = 25oC

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC

I = I25

150

VGS = 10V 100

10 10-5

10-4

10-3

10-2

10-1

100

101

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability




Typical Characteristics TC = 25°C unless otherwise noted

2000

100

10µs

1000

100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)

10

10ms 1

DC

SINGLE PULSE TJ = MAX RATED TC = 25o C

0.1 1

10

STARTING TJ = 25oC

IAS, AVALANCHE CURRENT (A)


100µs

STARTING TJ = 150oC 10

If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01

100

0.1 1 10 tAV, TIME IN AVALANCHE (ms)

VDS, DRAIN TO SOURCE VOLTAGE (V)

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5. Forward Bias Safe Operating Area

Figure 6. Unclamped Inductive Switching Capability 160

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V

VGS = 20V


ID , DRAIN CURRENT (A)

160

120

80

TJ = 175 oC

TJ = 25o C

40

VGS = 10V

120 VGS = 6V VGS = 5V 80

40

o

TJ = -55 C

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

TC = 25o C

0

0 3.0

3.5

4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V)

6

0

Figure 7. Transfer Characteristics

0.5 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V)

1.5

Figure 8. Saturation Characteristics 2.5

6

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

NORMALIZED DRAIN TO SOURCE ON RESISTANCE

DRAIN TO SOURCE ON RESISTANCE(mΩ)

100

VGS = 6V 5

4

VGS = 10V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0

1.5

1.0

VGS = 10V, ID =80A

3 0

20

40

60

80


Figure 9. Drain to Source On Resistance vs Drain Current


0.5 -80

-40

0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

200

Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature




1.4

1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE

VGS = VDS, I D = 250µA

NORMALIZED GATE THRESHOLD VOLTAGE

1.2

1.0

0.8

0.6

0.4

0.2 -80

-40

0

40

80

120

160

1.1

1.0

0.9

200

-80

-40

TJ, JUNCTION TEMPERATURE (oC)

Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 10000

80

120

160

200

Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature

VGS , GATE TO SOURCE VOLTAGE (V)

CISS = CGS + CGD C, CAPACITANCE (pF)

40

10

COSS ≅ C DS + C GD

1000

0

TJ , JUNCTION TEMPERATURE (o C)

CRSS = CGD

VGS = 0V, f = 1MHz 1

10

VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Source Voltage


8

6

4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 40A

2

0

100 0.1

VDD = 30V

60

0

25

50 Qg , GATE CHARGE (nC)

75

100

Figure 14. Gate Charge Waveforms for Constant Gate Current




VDS BVDSS tP

L

VDS VARY tP TO OBTAIN

IAS

+

RG

REQUIRED PEAK IAS

VDD

VDD -

VGS DUT tP

IAS

0V

0

0.01Ω

tAV

Figure 15. Unclamped Energy Test Circuit

Figure 16. Unclamped Energy Waveforms

VDS VDD

Qg(TOT) VDS

L VGS

VGS

VGS = 10V

+

Qgs2

VDD DUT VGS = 2V

Ig(REF)

0 Qg(TH) Qgs

Qgd

Ig(REF) 0

Figure 17. Gate Charge Test Circuit

Figure 18. Gate Charge Waveforms

VDS

tON

tOFF

td(ON)

td(OFF)

RL

tr VDS

tf

90%

90%

+

VGS

VDD -

10%

0

10%

DUT

90%

RGS VGS

50%

50% PULSE WIDTH

VGS

0

Figure 19. Switching Time Test Circuit


10%

Figure 20. Switching Time Waveforms



Test Circuits and Waveforms

.SUBCKT FDP038AN06A0 2 1 3 ; rev July 04, 2002 Ca 12 8 1.5e-9 Cb 15 14 1.5e-9 Cin 6 8 6.1e-9

LDRAIN DPLCAP 10

Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD

RLDRAIN

RSLC1 51

5 51 EVTHRES + 19 8

+ LGATE GATE 1

ESLC

11 + 17 EBREAK 18 -

50 RDRAIN

6 8

ESG

DBREAK

+

RSLC2

Ebreak 11 7 17 18 69.3 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1

DRAIN 2

5

EVTEMP RGATE + 18 22 9 20

21

16

DBODY

MWEAK

6

MMED MSTRO

RLGATE

Lgate 1 9 4.81e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.63e-9

LSOURCE

CIN

8

7

SOURCE 3

RSOURCE RLSOURCE

RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

S1A 12

S2A

S1B CA

17

18 RVTEMP

S2B 13

CB 6 8

5 8

EDS

-

19 VBAT +

IT

14

+

+ EGS

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1e-4 Rgate 9 20 1.36 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.8e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD

15

14 13

13 8

RBREAK

-

8

22 RVTHRES

Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))} .MODEL DbodyMOD D (IS=2.4E-11 N=1.04 RS=1.65e-3 TRS1=2.7e-3 TRS2=2e-7 + CJO=4.35e-9 M=5.4e-1 TT=1e-9 XTI=3.9) .MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.7e-9 IS=1e-30 N=10 M=0.47) .MODEL MmedMOD NMOS (VTO=3.3 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.36 T_abs=25) .MODEL MstroMOD NMOS (VTO=4.00 KP=275 IS=1e-30 N=10 TOX=1 L=1u W=1u T_abs=25) .MODEL MweakMOD NMOS (VTO=2.72 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13.6 RS=0.1 T_abs=25) .MODEL RbreakMOD RES (TC1=9e-4 TC2=-9e-7) .MODEL RdrainMOD RES (TC1=4e-2 TC2=3e-4) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-6.7e-3 TC2=-1.5e-5) .MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.




PSPICE Electrical Model

rev July 4, 2002 template FDP038AN06A0 n2,n1,n3 = m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=2.4e-11,nl=1.04,rs=1.65e-3,trs1=2.7e-3,trs2=2e-7,cjo=4.35e-9,m=5.4e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.7e-9,isl=10e-30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.3,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.00,kp=275,is=1e-30, tox=1) LDRAIN m..model mweakmod = (type=_n,vto=2.72,kp=0.03,is=1e-30, tox=1,rs=0.1) DPLCAP 5 DRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1.5) 2 10 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-4) RLDRAIN sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5) RSLC1 51 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1) RSLC2 c.ca n12 n8 = 1.5e-9 ISCL c.cb n15 n14 = 1.5e-9 c.cin n6 n8 = 6.1e-9 DBREAK 50 -

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 69.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

RDRAIN

6 8

ESG

EVTHRES + 19 8

+ LGATE

GATE 1

EVTEMP RGATE + 18 22 9 20

21

EBREAK + 17 18 -

MMED MSTRO CIN

8

LSOURCE 7

SOURCE 3

RSOURCE RLSOURCE S2A

S1A

i.it n8 n17 = 1

12

13 8 S1B

CA

RBREAK

15

14 13

17

18 RVTEMP

S2B 13

CB

+

res.rlgate n1 n9 = 48.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 46.3

DBODY MWEAK

6

RLGATE

l.lgate n1 n9 = 4.81e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.63e-9

11

16

6 8

EGS

19

-

IT

14

+

VBAT

5 8

EDS -

+ 8

22 RVTHRES

m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-9e-7 res.rdrain n50 n16 = 1e-4, tc1=4e-2,tc2=3e-4 res.rgate n9 n20 = 1.36 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.8e-3, tc1=5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-6.7e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) }




SABER Electrical Model

th

REV 23 July 4, 2002

JUNCTION

FDP038AN06A0T CTHERM1 TH 6 6.45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 TL 1e-1 RTHERM1 TH 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.1e-1 RTHERM6 2 TL 1.4e-1

RTHERM1

CTHERM1

6

RTHERM2

CTHERM2

5

SABER Thermal Model SABER thermal model FDP035AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =6.45e-3 ctherm.ctherm2 6 5 =3e-2 ctherm.ctherm3 5 4 =1.4e-2 ctherm.ctherm4 4 3 =1.65e-2 ctherm.ctherm5 3 2 =4.85e-2 ctherm.ctherm6 2 tl =1e-1 rtherm.rtherm1 th 6 =3.24e-3 rtherm.rtherm2 6 5 =8.08e-3 rtherm.rtherm3 5 4 =2.28e-2 rtherm.rtherm4 4 3 =1e-1 rtherm.rtherm5 3 2 =1.1e-1 rtherm.rtherm6 2 tl=1.4e-1 }

RTHERM3

CTHERM3

4

RTHERM4

CTHERM4

3

RTHERM5

CTHERM5

2

RTHERM6

CTHERM6

tl


CASE



PSPICE Thermal Model

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DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification

Product Status

Definition

Advance Information

Formative or In Design

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

No Identification Needed

Full Production

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I1

HIP4081A

®

Data Sheet

February 2003

80V/2.5A Peak, High Frequency Full Bridge FET Driver

FN3659.6

Features

The HIP4081A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081A can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081A can switch at frequencies up to 1MHz and is well suited to driving Voice Coil Motors, high-frequency switching power amplifiers, and power supplies. For example, the HIP4081A can drive medium voltage brush motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching. The Application Note for the HIP4081A is the AN9405.

• Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations • Bootstrap Supply Max Voltage to 95VDC • Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns • User-Programmable Dead Time • On-Chip Charge-Pump and Bootstrap Upper Bias Supplies • DIS (Disable) Overrides Input Control • Input Logic Thresholds Compatible with 5V to 15V Logic Levels • Very Low Power Consumption • Undervoltage Protection

Applications • Medium/Large Voice Coil Motors • Full Bridge Power Supplies • Switching Power Amplifiers • High Performance Motor Controls

Ordering Information

• Noise Cancellation Systems

PART NUMBER

TEMP RANGE (oC)

HIP4081AIP

-40 to 85

20 Ld PDIP

E20.3

• Peripherals

HIP4081AIB

-40 to 85

20 Ld SOIC (W)

M20.3

• U.P.S.

PACKAGE

PKG. NO.

• Battery Powered Vehicles

Pinout HIP4081A (PDIP, SOIC) TOP VIEW

1

BHB

1

20

BHO

BHI

2

19

BHS

DIS

3

18

BLO

VSS

4

17

BLS

BLI

5

16

VDD

ALI

6

15

VCC

AHI

7

14

ALS

HDEL

8

13

ALO

LDEL

9

12

AHS

AHB 10

11

AHO

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

HIP4081A Application Block Diagram 80V

12V BHO BHS BHI

LOAD

BLO

BLI HIP4081A ALI

ALO AHS

AHI

AHO

GND

Functional Block Diagram

GND

(1/2 HIP4081A) HIGH VOLTAGE BUS ≤ 80VDC

AHB 10 UNDERVOLTAGE

CHARGE PUMP

LEVEL SHIFT AND LATCH

DRIVER

CBS AHS

VDD 16 AHI

AHO 11

12

7

TURN-ON DELAY DBS

DIS

3 15

DRIVER ALI

TURN-ON DELAY

6

VCC

ALO 13 ALS 14

HDEL

8

LDEL

9

VSS

4

2

TO VDD (PIN 16)

CBF

+12VDC BIAS SUPPLY

HIP4081A Typical Application

(PWM Mode Switching) 80V

2 BHI

DIS

3 DIS

BHO 20 HIP4081/HIP4081A

1 BHB 12V

4 VSS PWM INPUT

5 BLI 6 ALI 7 AHI 8 HDEL

BHS 19 LOAD

BLO 18 BLS 17 VDD 16 VCC 15

12V

ALS 14 ALO 13

9 LDEL

AHS 12

10 AHB

AHO 11

GND

-

TO OPTIONAL CURRENT CONTROLLER

+ 6V

GND

3

HIP4081A Absolute Maximum Ratings

Thermal Information

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . . .VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All Voltages relative to VSS, unless otherwise specified.

Thermal Resistance (Typical, Note 1)

θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Storage Temperature Range. . . . . . . . . . . . . . . . . . . -65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC Lead Temperature (Soldering 10s)) . . . . . . . . . . . . . . . . . . . . 300oC (For SOIC - Lead Tips Only

Operating Conditions Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500µA to -50µA Operating Ambient Temperature Range . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified TJS = -40oC TO 125oC

o

TJ = 25 C PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

All inputs = 0V

8.5

10.5

14.5

7.5

14.5

mA

Outputs switching f = 500kHz

SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current

IDD

VDD Operating Current

IDDO

VCC Quiescent Current

ICC

VCC Operating Current

ICCO

9.5

12.5

15.5

8.5

15.5

mA

All Inputs = 0V, IALO = IBLO = 0

-

0.1

10

-

20

µA

f = 500kHz, No Load

1

1.25

2.0

0.8

3

mA

All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V

-50

-30

-11

-60

-10

µA

IAHBO, IBHBO

f = 500kHz, No Load

0.6

1.2

1.5

0.5

1.9

mA

IHLK

VBHS = VAHS = 80V, VAHB = VBHB = 93V

-

0.02

1.0

-

10

µA

IAHB = IAHB = 0, No Load

11.5

12.6

14.0

10.5

14.5

V

IAHB, IBHB

AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage

VAHB-VAHS VBHB-VBHS

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage

VIL

Full Operating Conditions

-

-

1.0

-

0.8

V

High Level Input Voltage

VIH

Full Operating Conditions

2.5

-

-

2.7

-

V

-

35

-

-

-

mV

Low Level Input Current

IIL

VIN = 0V, Full Operating Conditions

-130

-100

-75

-135

-65

µA

High Level Input Current

IIH

VIN = 5V, Full Operating Conditions

-1

-

+1

-10

+10

µA

IHDEL = ILDEL = -100µA

4.9

5.1

5.3

4.8

5.4

V

Input Voltage Hysteresis

TURN-ON DELAY PINS: LDEL AND HDEL VHDEL, VLDEL

LDEL, HDEL Voltage

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage

VOL

IOUT = 100mA

0.7

0.85

1.0

0.5

1.1

V

High Level Output Voltage

VCC-VOH

IOUT = -100mA

0.8

0.95

1.1

0.5

1.2

V

VOUT = 0V

1.7

2.6

3.8

1.4

4.1

A

IO +

Peak Pullup Current

4

HIP4081A Electrical Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) TJS = -40oC TO 125oC

TJ = 25oC PARAMETER

SYMBOL

Peak Pulldown Current

IO -

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNITS

1.7

2.4

3.3

1.3

3.6

A

Undervoltage, Rising Threshold

UV+

8.1

8.8

9.4

8.0

9.5

V

Undervoltage, Falling Threshold

UV-

7.6

8.3

8.9

7.5

9.0

V

Undervoltage, Hysteresis

HYS

0.25

0.4

0.65

0.2

0.7

V

Switching Specifications

VO UT = 12V

TYP

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF. TJS = -40oC TO 125oC

TJ = 25oC PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO)

TLPHL

-

30

60

-

80

ns

Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO)

THPHL

-

35

70

-

90

ns

Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO)

TLPLH

RHDEL = RLDEL = 10K

-

45

70

-

90

ns

Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO)

THPLH

RHDEL = RLDEL = 10K

-

60

90

-

110

ns

Rise Time

TR

-

10

25

-

35

ns

Fall Time

TF

-

10

25

-

35

ns

TPWIN-ON

RHDEL = RLDEL = 10K

50

-

-

50

-

ns

Turn-off Input Pulse Width

TPWIN-OFF

RHDEL = RLDEL = 10K

40

-

-

40

-

ns

Turn-on Output Pulse Width

TPWOUT-ON

RHDEL = RLDEL = 10K

40

-

-

40

-

ns

Turn-off Output Pulse Width

TPWOUT-OFF

RHDEL = RLDEL = 10K

30

-

-

30

-

ns

Turn-on Input Pulse Width

Disable Turn-off Propagation Delay (DIS - Lower Outputs)

TDISLOW

-

45

75

-

95

ns

Disable Turn-off Propagation Delay (DIS - Upper Outputs)

TDISHIGH

-

55

85

-

105

ns

Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO)

TDLPLH

-

40

70

-

90

ns

Refresh Pulse Width (ALO and BLO)

TREF-PW

240

410

550

200

600

ns

TUEN

-

450

620

-

690

ns

Disable to Upper Enable (DIS - AHO and BHO)

TRUTH TABLE INPUT

NOTE:

OUTPUT

ALI, BLI

AHI, BHI

U/V

DIS

ALO, BLO

AHO, BHO

X

X

X

1

0

0

1

X

0

0

1

0

0

1

0

0

0

1

0

0

0

0

0

0

X

X

1

X

0

0

X signifies that input can be either a “1” or “0”.

5

HIP4081A Pin Descriptions PIN NUMBER

SYMBOL

DESCRIPTION

1

BHB

B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2

BHI

B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

3

DIS

DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

4

VSS

Chip negative supply, generally will be ground.

5

BLI

B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

6

ALI

A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

7

AHI

A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).

8

HDEL

High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.

9

LDEL

Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.

10

AHB

A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11

AHO

A High-side Output. Connect to gate of A High-side power MOSFET.

12

AHS

A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.

13

ALO

A Low-side Output. Connect to gate of A Low-side power MOSFET.

14

ALS

A Low-side Source connection. Connect to source of A Low-side power MOSFET.

15

VCC

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.

16

VDD

Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

17

BLS

B Low-side Source connection. Connect to source of B Low-side power MOSFET.

18

BLO

B Low-side Output. Connect to gate of B Low-side power MOSFET.

19

BHS

B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.

20

BHO

B High-side Output. Connect to gate of B High-side power MOSFET.

6

HIP4081A Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL

THPHL

U/V = DIS = 0

XLI

XHI

XLO

XHO

THPLH

TLPLH

TR (10% - 90%)

TF (10% - 90%)

(10% - 90%)

(10% - 90%)

FIGURE 1. INDEPENDENT MODE U/V = DIS = 0

XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

FIGURE 2. BISTATE MODE

TDLPLH

TDIS

U/V OR DIS TREF-PW

XLI

XHI

XLO

XHO TUEN

FIGURE 3. DISABLE FUNCTION

7

HIP4081A Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified 11.0

14.0 IDD SUPPLY CURRENT (mA)

IDD SUPPLY CURRENT (mA)

10.5 12.0 10.0 8.0 6.0 4.0

9.5

9.0

8.5

8.0

2.0 6

8

10 12 VDD SUPPLY VOLTAGE (V)

0

14

100

200

300

400

500

600

700

800

900 1000

SWITCHING FREQUENCY (kHz)

FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE

FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) 5.0

30.0

125oC 25.0 ICC SUPPLY CURRENT (mA)

FLOATING SUPPLY BIAS CURRENT (mA)

10.0

20.0

15.0

10.0

5.0

75oC

4.0

25oC 0 oC

3.0

-40oC 2.0

1.0

0.0 0

100

200 300

400

500

600

700

800

0.0

900 1000

0


100

200

300

400

500

600

700

800

900 1000


FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF)

FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE -90 LOW LEVEL INPUT CURRENT (µA)

FLOATING SUPPLY BIAS CURRENT (mA)

2.5

2

1.5

1

0.5

0

200 600 800 400 SWITCHING FREQUENCY (kHz)

1000

FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY

8

-100

-110

-120 -50

-25

0 25 50 75 JUNCTION TEMPERATURE (oC)

100

125

FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE


VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K

80

15.0

14.0

PROPAGATION DELAY (ns)

NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)

and TA = 25oC, Unless Otherwise Specified

13.0

12.0

11.0

10.0 -40

-20

0

20

40

60

80

100

70

60

50

40

30 -40

120

-20

0

o

JUNCTION TEMPERATURE ( C)

FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE

60

80

100

120

80



40

FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE

525

500

475

450

425 -50

20

JUNCTION TEMPERATURE (oC)

70

60

50

40

30 -25

0

25

50

75

JUNCTION TEMPERATURE

100

-40

125 150

-20

0

20

40

60

80

100

120


(oC)

FIGURE 12. DISABLE TO UPPER ENABLE, TUEN, PROPAGATION DELAY vs TEMPERATURE

FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE 80

450


REFRESH PULSE WIDTH (ns)

70 425

400

375

60

50

40

30 350 -50

-25

0

25

50

75

100 o


FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE

9

125 150

20 -40

-20

0

20

40

60

80

100


FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE

120


VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K

80

80

70

70 PROPAGATION DELAY (ns)


and TA = 25oC, Unless Otherwise Specified (Continued)

60

50

40

30

50

40

30

20 -40

-20

0

20

40

60

80

100

20 -40

120

o


-20

20

40

60

80

100

120

FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE 80

70

70 PROPAGATION DELAY (ns)

80

60

50

40

60

50

40

30

30

20

20 -40

-20

0

20

40

60

80

100

-40

120

-20

FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE

12.5

12.5

TURN-ON RISE TIME (ns)

13.5

11.5

10.5

9.5

-20

0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)

120

FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE

10

20

40

60

80

100

120

FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE

13.5

8.5 -40

0



GATE DRIVE FALL TIME (ns)

0


FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE


60

11.5

10.5

9.5

8.5 -40

-20

0

20

40

60

80

100

120


FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE


VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified 1500

1250 5.5 VCC - VOH (mV)

HDEL, LDEL INPUT VOLTAGE (V)

6.0

5.0

750 -40oC 0oC

500

4.5

25oC 250

4.0 -40

-20

0 20 40 60 80 100 JUNCTION TEMPERATURE (oC)

12 BIAS SUPPLY VOLTAGE (V)

14

3.5

GATE DRIVE SINK CURRENT (A)

1250

1000

750 -40oC 0 oC 25oC 250

125oC

FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA

1500

500

75oC

0 10

120

FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE

VOL (mV)

1000

75oC

3.0 2.5 2.0 1.5 1.0 0.5

125oC 0 10

0.0 12 BIAS SUPPLY VOLTAGE (V)

14

FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA

11

6

7

8

9 10 11 12 13 VDD , VCC, VAHB , VBHB (V)

14

15

16

FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE


VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 500 LOW VOLTAGE BIAS CURRENT (mA)

GATE DRIVE SINK CURRENT (A)

3.5 3.0 2.5 2.0 1.5 1.0 0.5

10,000pF

200 100

3,000pF

50

1,000pF

20

100pF

10 5 2 1 0.5 0.2

0.0 6

7

8

9

10

11

12

13

14

15

0.1

16

1

2

5

VDD, VCC, VAHB, VBHB (V)

10

20

50

100

200

500 1000


FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE

FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE

1000

LEVEL-SHIFT CURRENT (µA)

500

200 100 50

20 10 10

20

50

100

200

500

1000


FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE 150

9.0

120 8.8 DEAD-TIME (ns)

BIAS SUPPLY VOLTAGE, VDD (V)

UV+

8.6

UV-

90

60

8.4 30

8.2 50

25

0

25

50

75

100

125

150

o

TEMPERATURE ( C)

FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE

12

0 10

50

100 150 200 HDEL/LDEL RESISTANCE (kΩ)

250

FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE

IN2

IN1

POWER SECTION

+12V

B+ Q1

1

R29

JMPR1

2

13

U2

+ C6

JMPR5

CONTROL LOGIC SECTION

JMPR2

12

U2

IN+/ALI

CD4069UB 5

JMPR3 HEN/BHI

6

U2 CD4069UB

10

U2

CW CD4069UB

1

VCC 15 ALS 14

8 HDEL 9 LDEL

ALO 13 AHS 12

DD

3 L1 AO Q2

+12V

R23

2

CW

1

L2

C1

1

BO C2

3 Q4 R24

AHO 11

2

1 3

CR1

2

2

6 IN+/ALI 7 IN-/AHI

R22

3

3 IN-/AHI

BLS 17 16 V

2

1

C3

R30 CX

R31

CY

C5 ENABLE IN I R32

3

U2

4

COM

O ALS

BLS NOTES:

CD4069UB

1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V. 9

U2

8

CD4069UB

O

2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4.

FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC

HIP4081A

11

Q3

3

4 V SS 5 OUT/BLI

10 AHB

R34

R33 JMPR4

CR2

U1 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18

OUT/BLI

C8

1

HIP4080A/81A

CD4069UB 13

R21

DRIVER SECTION

2

R26

COM

C8 C6

R28

R27

B+

CR2

+

R32

+

JMPR5

R29

+12V

C7

14

GND

Q1 C4 BHO

U1

Q3

1

R22

1

O IN2

ALS ALO

Q2

R23

Q4

1

1

R21 AHO

O

CY

CX

FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN

R31

R34

R30

CR1 R33

BLS

C3 C5

ALS

HDEL

LDEL

L2

HIP4081A

JMPR1 JMPR2 JMPR3 JMPR4

I

BLO BLS

L1

IN1

HIP4080/81

R24 DIS

U2

HIP4081A Dual-In-Line Plastic Packages (PDIP) N

E20.3 (JEDEC MS-001-AD ISSUE D) 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1 INDEX AREA

1 2 3

N/2

INCHES -B-

SYMBOL

-AD A2

-C-

SEATING PLANE D1

e

B1

D1

A1

eC

B 0.010 (0.25) M

C A B S

MAX

NOTES

-

0.210

-

5.33

4

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

C L

B

0.014

0.022

0.356

0.558

-

eA

B1

0.045

0.070

1.55

1.77

8

C

0.008

0.014

0.204

0.355

-

D

0.980

1.060

24.89

26.9

5

D1

0.005

-

0.13

-

5

C

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

15

MIN

A

A L

MAX

A1

E

BASE PLANE

MILLIMETERS

MIN

E

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

e

0.100 BSC

2.54 BSC

-

eA

0.300 BSC

7.62 BSC

6

eB

-

0.430

-

10.92

7

L

0.115

0.150

2.93

3.81

4

N

20

20

9 Rev. 0 12/93

HIP4081A Small Outline Plastic Packages (SOIC) N INDEX AREA

H

0.25(0.010) M

M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

B M

E

INCHES

-B1

2

SYMBOL

3

L SEATING PLANE

-A-

h x 45o

A

D -C-

e

µα A1

B 0.25(0.010) M

0.10(0.004) C A M

B S

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

MIN

MAX

NOTES

A

0.0926

0.1043

2.35

2.65

-

0.0040

0.0118

0.10

0.30

-

B

0.013

0.0200

0.33

0.51

9

C

0.0091

0.0125

0.23

0.32

-

D

0.4961

0.5118

12.60

13.00

3

E

0.2914

0.2992

7.40

7.60

4

0.050 BSC

1.27 BSC

-

H

0.394

0.419

10.00

10.65

-

h

0.010

0.029

0.25

0.75

5

L

0.016

0.050

0.40

1.27

6

8o

0o

N

NOTES:

MILLIMETERS

MAX

A1

e C

MIN

α

20 0o

20

7 8o

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com 16

LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner.

Features Advantages n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance — very low 1/f corner n Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers n New output stage allows use of large capacitive loads (5,000 pF) without stability problems n Internal compensation and large differential input voltage capability

Common Features n Low input bias current: 30pA n Low Input Offset Current: 3pA n High input impedance: 1012Ω n Low input noise current: n High common-mode rejection ratio: n Large dc voltage gain: 106 dB

100 dB

Uncommon Features

j Extremely

LF155/ LF355

LF156/ LF256/ LF356

LF257/ LF357 (AV =5)

Units

4

1.5

1.5

µs

5

12

50

V/µs

2.5

5

20

MHz

20

12

12

fast settling time to 0.01% j Fast slew

rate j Wide gain

bandwidth

Applications n n n n

n Logarithmic amplifiers n Photocell amplifiers n Sample and Hold circuits

Precision high speed integrators Fast D/A and A/D converters High impedance buffers Wideband, low noise, low drift amplifiers

j Low input

noise voltage

Simplified Schematic

00564601

*3pF in LF357 series.

BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation.

© 2001 National Semiconductor Corporation

DS005646

www.national.com

LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers

December 2001

LF155/LF156/LF256/LF257/LF355/LF356/LF357

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for availability and specifications. LF155/6

LF256/7/LF356B

LF355/6/7

Input Voltage Range (Note 2)

± 22V ± 40V ± 20V

± 22V ± 40V ± 20V

± 18V ± 30V ± 16V

Output Short Circuit Duration

Continuous

Continuous

Continuous

Supply Voltage Differential Input Voltage

TJMAX H-Package

115˚C

115˚C

N-Package

150˚C

100˚C

100˚C

M-Package

100˚C

100˚C

Power Dissipation at TA = 25˚C (Notes 1, 8) H-Package (Still Air)

560 mW

400 mW

400 mW

H-Package (400 LF/Min Air Flow)

1200 mW

1000 mW

1000 mW

N-Package

670 mW

670 mW

M-Package

380 mW

380 mW

160˚C/W

160˚C/W

160˚C/W

65˚C/W

65˚C/W

65˚C/W

N-Package

130˚C/W

130˚C/W

M-Package

195˚C/W

195˚C/W

Thermal Resistance (Typical) θJA H-Package (Still Air) H-Package (400 LF/Min Air Flow)

(Typical) θJC H-Package Storage Temperature Range

23˚C/W

23˚C/W

23˚C/W

−65˚C to +150˚C

−65˚C to +150˚C

−65˚C to +150˚C

300˚C

300˚C

300˚C

260˚C

260˚C

260˚C

Soldering Information (Lead Temp.) Metal Can Package Soldering (10 sec.) Dual-In-Line Package Soldering (10 sec.) Small Outline Package Vapor Phase (60 sec.)

215˚C

215˚C

Infrared (15 sec.)

220˚C

220˚C

See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. ESD tolerance (100 pF discharged through 1.5kΩ)

1000V

1000V

1000V

DC Electrical Characteristics (Note 3) Symbol

Parameter

Min VOS

Input Offset Voltage

RS =50Ω, TA =25˚C

Typ 3

Over Temperature ∆VOS/∆T

Average TC of Input Offset Voltage

RS =50Ω

∆TC/∆VOS

Change in Average TC with VOS Adjust

RS =50Ω, (Note 4)

IOS


Max Min 5

Typ 3

7

TJ =25˚C, (Notes 3, 5)

Max Min 5

Units

Typ

Max

3

10

mV

13

mV

6.5 5

5

µV/˚C

0.5

0.5

0.5

µV/˚C per mV

20 20

2

LF355/6/7

5

3

TJ≤THIGH

www.national.com

LF256/7 LF356B

LF155/6

Conditions

3

20 1

3

50

pA

2

nA

(Continued)

(Note 3) Symbol

Parameter

Min IB

Input Bias Current

LF256/7 LF356B

LF155/6

Conditions

Typ

TJ =25˚C, (Notes 3, 5)

Max Min

30

100

TJ≤THIGH Input Resistance

TJ =25˚C

AVOL

Large Signal Voltage Gain

VS = ± 15V, TA =25˚C

Output Voltage Swing

10 50

Input Common-Mode Voltage Range

CMRR

Common-Mode Rejection Ratio

PSRR

Supply Voltage Rejection Ratio

30

100

Max

30

200

pA

8

nA

5

12

12

50

± 13 ± 12

± 12 ± 10

Ω

12

10

200

10

200

25

± 13 ± 12 ± 15.1

± 12 ± 10

Units

Typ

200

V/mV

VO = ± 10V, RL =2k Over Temperature

25

VS = ± 15V, RL =10k

± 12 ± 10

VS = ± 15V, RL =2k VCM

Max Min

50

RIN

VO

Typ

LF355/6/7

VS = ± 15V

± 11

(Note 6)

25

+15.1

± 11

−12

15

+10

−12

V/mV

± 13 ± 12

V

+15.1

V

−12

V

V

85

100

85

100

80

100

dB

85

100

85

100

80

100

dB

DC Electrical Characteristics TA = TJ = 25˚C, VS = ± 15V Parameter Supply Current

LF155

LF355

LF156/256/257/356B

LF356

LF357

Typ

Max

Typ

Max

Typ

Max

Typ

Max

Typ

Max

2

4

2

4

5

7

5

10

5

10

Units mA

AC Electrical Characteristics TA = TJ = 25˚C, VS = ± 15V Symbol

Parameter

LF155/355

LF156/256/ 356B

LF156/256/356/ LF356B

LF257/357

Typ

Min

Typ

Typ

5

7.5

12

Conditions

SR

Slew Rate

LF155/6: AV =1,

GBW

Gain Bandwidth Product

ts

Settling Time to 0.01%

(Note 7)

en

Equivalent Input Noise Voltage

RS =100Ω

LF357: AV =5

in

CIN

Equivalent Input Current Noise

Units V/µs 50

V/µs

2.5

5

20

MHz

4

1.5

1.5

µs

f=100 Hz

25

15

15

f=1000 Hz

20

12

12

f=100 Hz

0.01

0.01

0.01

f=1000 Hz

0.01

0.01

0.01

3

3

3

Input Capacitance

pF

Notes for Electrical Characteristics Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is PD =(TJMAX−TA)/θJA or the 25˚C PdMAX, whichever is less. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: Unless otherwise stated, these test conditions apply:

3

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LF155/LF156/LF256/LF257/LF355/LF356/LF357

DC Electrical Characteristics

LF155/LF156/LF256/LF257/LF355/LF356/LF357

Notes for Electrical Characteristics LF155/156

(Continued) LF256/257

± 15V ≤ VS ≤ ± 20V

LF356B

± 15V ≤ VS ± 20V

LF355/6/7

Supply Voltage, VS

± 15V ≤ VS ≤ ± 20V

TA

−55˚C ≤ TA ≤ +125˚C

−25˚C ≤ TA ≤ +85˚C

0˚C ≤ TA ≤ +70˚C

0˚C ≤ TA ≤ +70˚C

THIGH

+125˚C

+85˚C

+70˚C

+70˚C

VS = ± 15V

and VOS, IB and IOS are measured at VCM = 0. Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5µV/˚C typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 5: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + θJA Pd where θJA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kΩ resistors for the LF155/6. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, AV = −5, the feedback resistor from output to input is 2kΩ and the output step is 10V (See Settling Time Test Circuit). Note 8: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits.

Typical DC Performance Characteristics

Curves are for LF155 and LF156 unless otherwise

specified. Input Bias Current

Input Bias Current

00564638

00564637

Input Bias Current

Voltage Swing

00564640

00564639

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4


specified. (Continued) Supply Current

Supply Current

00564642

00564641

Negative Current Limit

Positive Current Limit

00564643

00564644

Positive Common-Mode Input Voltage Limit

Negative Common-Mode Input Voltage Limit

00564645 00564646

5

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LF155/LF156/LF256/LF257/LF355/LF356/LF357


LF155/LF156/LF256/LF257/LF355/LF356/LF357



specified. (Continued) Open Loop Voltage Gain

Output Voltage Swing

00564648

00564647

Typical AC Performance Characteristics Gain Bandwidth

Gain Bandwidth

00564650

00564649

Normalized Slew Rate

Output Impedance

00564651

www.national.com

00564652

6

Output Impedance

(Continued) LF155 Small Signal Pulse Response, AV = +1

00564605

00564653

LF156 Small Signal Pulse Response, AV = +1

LF155 Large Signal Pulse Response, AV = +1

00564608

00564606

LF156 Large Signal Puls Response, AV = +1

Inverter Settling Time

00564609

00564655

7

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LF155/LF156/LF256/LF257/LF355/LF356/LF357

Typical AC Performance Characteristics

LF155/LF156/LF256/LF257/LF355/LF356/LF357

Typical AC Performance Characteristics Inverter Settling Time

(Continued) Open Loop Frequency Response

00564656

00564657

Bode Plot

Bode Plot

00564658

00564659

Bode Plot

Common-Mode Rejection Ratio

00564660

www.national.com

00564661

8

Power Supply Rejection Ratio

(Continued) Power Supply Rejection Ratio

00564662

00564663

Undistorted Output Voltage Swing

Equivalent Input Noise Voltage

00564664 00564665

Equivalent Input Noise Voltage (Expanded Scale)

00564666

9

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LF155/LF156/LF256/LF257/LF355/LF356/LF357

Typical AC Performance Characteristics

LF155/LF156/LF256/LF257/LF355/LF356/LF357

Detailed Schematic

00564613

*C = 3pF in LF357 series.

Connection Diagrams

(Top Views) Dual-In-Line Package (M and N)

Metal Can Package (H)

00564614

Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H, or LF357H See NS Package Number H08C

00564629

Order Number LF356M, LF356MX, LF355N, or LF356N See NS Package Number M08A or N08E

*Available per JM38510/11401 or JM38510/11402

Application Hints These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a www.national.com

10

Typical Circuit Connections

(Continued)

reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pickup” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.

VOS Adjustment

00564667

• • •

VOS is adjusted with a 25k potentiometer

•

Typical overall drift: 5µV/˚C ± (0.5µV/˚C/mV of adj.)

The potentiometer wiper is connected to V+ For potentiometers with temperature coefficient of 100 ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/ ˚C/mV of adjustment Driving Capacitive Loads

00564668

* LF155/6 R = 5k

LF357 R = 1.25k Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) . 0.01µF. Overshoot ≤ 20% Settling time (ts) . 5µs LF357. A Large Power BW Amplifier

00564615

For distortion ≤ 1% and a 20 Vp-p VOUT swing, power bandwidth is: 500kHz.

11

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LF155/LF156/LF256/LF257/LF355/LF356/LF357

Application Hints

LF155/LF156/LF256/LF257/LF355/LF356/LF357

Typical Applications Settling Time Test Circuit

00564616

• • • •

Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5 FET used to isolate the probe capacitance Output = 10V step AV = −5 for LF357

Large Signal Inverter Output, VOUT (from Settling Time Circuit) LF355

LF357

00564619

00564617

LF356

00564618

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12

LF155/LF156/LF256/LF257/LF355/LF356/LF357

Typical Applications

(Continued) Low Drift Adjustable Voltage Reference

00564620

• • • • •

∆ VOUT/∆T = ± 0.002%/˚C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Use LF155 for j Low IB j Low drift j Low supply current

Fast Logarithmic Converter

00564621

• • • • •

Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades), |VO| = 1V/decade Transient response: 3µs for ∆Ii = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/˚C

13

www.national.com

LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) Precision Current Monitor

00564631

• • •

VO = 5 R1/R2 (V/mA of IS) R1, R2, R3: 0.1% resistors Use LF155 for j Common-mode range to supply range j Low IB j Low VOS j Low Supply Current

8-Bit D/A Converter with Symmetrical Offset Binary Operation

00564632

• •

R1, R2 should be matched within ± 0.05% Full-scale response time: 3µs EO +9.920

www.national.com

B1 B2 B3 B4 B5 B6 B7 B8 1

1

1

1

1

1

1

1

Comments Positive Full-Scale

+0.040

1

0

0

0

0

0

0

0

(+) Zero-Scale

−0.040

0

1

1

1

1

1

1

1

(−) Zero-Scale

−9.920

0

0

0

0

0

0

0

0

Negative Full-Scale

14

LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) Wide BW Low Noise, Low Drift Amplifier

00564670

•

Parasitic input capacitance C1 . (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1. Boosting the LF156 with a Current Amplifier

00564673

•

•

IOUT(MAX).150mA (will drive RL≥ 100Ω)

No additional phase shift added by the current amplifier

15

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LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) 3 Decades VCO

00564624

R1, R4 matched. Linearity 0.1% over 2 decades.

Isolating Large Capacitive Loads

00564622

• • •

Overshoot 6% ts 10µs When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX):

www.national.com

16

LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) Low Drift Peak Detector

00564623

• • • •

By adding D1 and Rf, VD1 =0 during hold mode. Leakage of D2 provided by feedback path through Rf. Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp. Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 1⁄2πRfCD2 where CD2 is the shunt capacitance of D2. Non-Inverting Unity Gain Operation for LF157

00564675

Inverting Unity Gain for LF157

00564625

17

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LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) High Impedance, Low Drift Instrumentation Amplifier

00564626

• •

System VOS adjusted via A2 VOS adjust Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift

www.national.com

18

LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) Fast Sample and Hold

00564633

• •

Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)

• • •

LF156 develops full Sr output capability for VIN ≥ 1V

Acquisition time TA, estimated by:

Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

19

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LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) High Accuracy Sample and Hold

00564627

•

By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. No VOS adjust required for A2.

•

TA can be estimated by same considerations as previously but, because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible.

• • •

Overall system slower than fast sample and hold R1, CC: additional compensation Use LF156 for j Fast settling time j Low VOS

High Q Band Pass Filter

00564628

• • •

By adding positive feedback (R2)

• •

Clean layout recommended

Q increases to 40 fBP = 100 kHz

Response to a 1Vp-p tone burst: 300µs

www.national.com

20

LF155/LF156/LF256/LF257/LF355/LF356/LF357


(Continued) High Q Notch Filter

00564634

•

2R1 = R = 10MΩ 2C = C1 = 300pF

• • •

Capacitors should be matched to obtain high Q fNOTCH = 120 Hz, notch = −55 dB, Q > 100 Use LF155 for j Low IB j Low supply current

21

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LF155/LF156/LF256/LF257/LF355/LF356/LF357

Physical Dimensions

inches (millimeters) unless otherwise noted

Metal Can Package (H) Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H or LF357H NS Package Number H08C

Small Outline Package (M) Order Number LF356M or LF356MX NS Package Number M08A

www.national.com

22


Molded Dual-In-Line Package (N) Order Number LF356N NS Package Number N08E

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected]

www.national.com

National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected]

National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers

Physical Dimensions

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094D – DECEMBER 1982 – REVISED JULY 2003

D D D D D D

Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-µA Max ICC Typical tpd = 15 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max

SN54HC74 . . . J OR W PACKAGE SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)

1CLR 1D 1CLK 1PRE 1Q 1Q GND

description/ordering information

14

2

13

3

12

4

11

5

10

6

9

7

8

VCC 2CLR 2D 2CLK 2PRE 2Q 2Q

1D 1CLR NC VCC 2CLR

SN54HC74 . . . FK PACKAGE (TOP VIEW)

1CLK NC 1PRE NC 1Q

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

2D NC 2CLK NC 2PRE

1Q GND NC 2Q 2Q

The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

1

NC – No internal connection

ORDERING INFORMATION PACKAGE†

TA PDIP – N

SN74HC74N

Tube of 50

SN74HC74D

Reel of 2500

SN74HC74DR

Reel of 250

SN74HC74DT

SOP – NS

Reel of 2000

SN74HC74NSR

HC74

SSOP – DB

Reel of 2000

SN74HC74DBR

HC74

Tube of 90

SN74HC74PW

Reel of 2000

SN74HC74PWR

Reel of 250

SN74HC74PWT

CDIP – J

Tube of 25

SNJ54HC74J

SNJ54HC74J

CFP – W

Tube of 150

SNJ54HC74W

SNJ54HC74W

LCCC – FK

Tube of 55

SNJ54HC74FK

TSSOP – PW

–55°C to 125°C

TOP-SIDE MARKING

Tube of 25

SOIC – D –40°C to 85°C

ORDERABLE PART NUMBER

SN74HC74N HC74

HC74

SNJ54HC74FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1


FUNCTION TABLE OUTPUTS

INPUTS PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

L

X

X

L H†

H H†

H

H

↑

H

H

L

H

H

↑

L

L

H

H H L X Q0 Q0 † This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.

logic diagram (positive logic) PRE CLK

C

C

Q TG

C C

C

C C

D

TG

TG

TG

Q C

C

C

CLR

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

2




recommended operating conditions (see Note 3) SN54HC74 VCC

Supply voltage

VIH

VCC = 2 V VCC = 4.5 V

High-level input voltage

VCC = 6 V VCC = 2 V VIL

Low-level input voltage

VI VO

MAX

2

5

6

NOM

MAX

2

5

6

1.5

3.15

3.15

4.2

4.2

0

UNIT V V

0.5

0.5

1.35

1.35

1.8

1.8

VCC VCC

VCC = 2 V VCC = 4.5 V

Input transition rise/fall time

MIN

1.5

0

Output voltage

∆t/∆v

NOM

VCC = 4.5 V VCC = 6 V

Input voltage

SN74HC74

MIN

0

VCC VCC

0

1000

1000

500

500

V V V ns

VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER

VOH

VOL

TEST CONDITIONS

Ci

TA = 25°C TYP MAX

SN54HC74

SN74HC74

MIN

MIN

MAX

MAX

UNIT

2V

1.9

1.998

1.9

1.9

4.5 V

4.4

4.499

4.4

4.4

6V

5.9

5.999

5.9

5.9

IOH = –4 mA IOH = –5.2 mA

4.5 V

3.98

4.3

3.7

3.84

6V

5.48

5.8

5.2

5.34

2V

0.002

0.1

0.1

0.1

IOL = 20 µA

4.5 V

0.001

0.1

0.1

0.1

6V

0.001

0.1

0.1

0.1

4.5 V

0.17

0.26

0.4

0.33

6V

0.15

0.26

0.4

0.33

6V

±0.1

±100

±1000

±1000

nA

4

80

40

µA

3

10

10

10

pF

VI = VIH or VIL

VI = VIH or VIL

VI = VCC or 0 VI = VCC or 0,

MIN

IOH = –20 µA

IOL = 4 mA IOL = 5.2 mA II ICC

VCC

IO = 0

6V 2 V to 6 V



V

V

3


timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC

fclock

Clock frequency

PRE or CLR low tw

Pulse duration CLK high or low

Data ↑ Setup time before CLK↑

tsu

PRE or CLR inactive

Hold time, data after CLK↑ ↑

th

TA = 25°C MIN MAX

SN54HC74

SN74HC74

MIN

MIN

MAX

MAX

2V

6

4.2

5

4.5 V

31

21

25

6V

0

36

0

25

0

2V

100

150

125

4.5 V

20

30

25

6V

17

25

21

2V

80

120

100

4.5 V

16

24

20

6V

14

20

17

2V

100

150

125

4.5 V

20

30

25

6V

17

25

21

2V

25

40

30

4.5 V

5

8

6

6V

4

7

5

2V

0

0

0

4.5 V

0

0

0

6V

0

0

0

UNIT

MHz

29

ns

ns

ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER

FROM (INPUT)

TO (OUTPUT)

fmax

PRE or CLR

Q or Q

tpd d CLK

tt

Q or Q

Q or Q

VCC

TA = 25°C MIN TYP MAX

SN54HC74

SN74HC74

MIN

MIN

MAX

2V

6

10

4.2

5

4.5 V

31

50

21

25

6V

36

60

25

29

MAX

UNIT

MHz

2V

70

230

345

290

4.5 V

20

46

69

58

6V

15

39

59

49

2V

70

175

250

220

4.5 V

20

35

50

44

6V

15

30

42

37

2V

28

75

110

95

4.5 V

8

15

22

19

6V

6

13

19

16

ns

ns

operating characteristics, TA = 25°C PARAMETER Cpd

4

TEST CONDITIONS

Power dissipation capacitance per flip-flop


No load


TYP 35

UNIT pF


PARAMETER MEASUREMENT INFORMATION From Output Under Test

Test Point

VCC

High-Level Pulse

50%

50% 0V

CL = 50 pF (see Note A)

tw VCC

Low-Level Pulse

LOAD CIRCUIT

50%

50% 0V

VOLTAGE WAVEFORMS PULSE DURATIONS

Reference Input

VCC

50%

Input

VCC 50%

50% 0V

0V tsu Data Input

50% 10%

90%

tr

th

tPLH 90%

VCC 50% 10% 0 V

In-Phase Output

90%

90%

tr

tf

VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

50% 10%

tPHL

tPHL Out-of-Phase Output

90%

VOH 50% 10% VOL tf

tPLH 50% 10% tf

50% 10%

90%

VOH VOL

tr

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms



5

MECHANICAL DATA MCFP002A – JANUARY 1995 – REVISED FEBRUARY 2002

W (R-GDFP-F14)

CERAMIC DUAL FLATPACK Base and Seating Plane

0.260 (6,60) 0.235 (5,97)

0.045 (1,14) 0.026 (0,66)

0.008 (0,20) 0.004 (0,10)

0.080 (2,03) 0.045 (1,14)

0.280 (7,11) MAX 1

0.019 (0,48) 0.015 (0,38)

14

0.050 (1,27)

0.390 (9,91) 0.335 (8,51) 0.005 (0,13) MIN 4 Places

7

8 0.360 (9,14) 0.250 (6,35)

0.360 (9,14) 0.250 (6,35)

4040180-2 / C 02/02 NOTES: A. B. C. D. E.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB



1

MECHANICAL DATA MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

18

17

16

15

14

13

NO. OF TERMINALS **

12

19

11

20

10

A

B

MIN

MAX

MIN

MAX

20

0.342 (8,69)

0.358 (9,09)

0.307 (7,80)

0.358 (9,09)

28

0.442 (11,23)

0.458 (11,63)

0.406 (10,31)

0.458 (11,63)

21

9

22

8

44

0.640 (16,26)

0.660 (16,76)

0.495 (12,58)

0.560 (14,22)

23

7

52

0.739 (18,78)

0.761 (19,32)

0.495 (12,58)

0.560 (14,22)

24

6 68

0.938 (23,83)

0.962 (24,43)

0.850 (21,6)

0.858 (21,8)

84

1.141 (28,99)

1.165 (29,59)

1.047 (26,6)

1.063 (27,0)

B SQ A SQ

25

5

26

27

28

1

2

3

4 0.080 (2,03) 0.064 (1,63)

0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

4040140 / D 10/96 NOTES: A. B. C. D. E.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004



1

MECHANICAL MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

16 PINS SHOWN PINS **

14

16

18

20

A MAX

0.775 (19,69)

0.775 (19,69)

0.920 (23,37)

1.060 (26,92)

A MIN

0.745 (18,92)

0.745 (18,92)

0.850 (21,59)

0.940 (23,88)

MS-100 VARIATION

AA

BB

AC

DIM A 16

9

0.260 (6,60) 0.240 (6,10)

1

C

AD

8 0.070 (1,78) 0.045 (1,14)

0.045 (1,14) 0.030 (0,76)

D

D

0.325 (8,26) 0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38) Gauge Plane

0.200 (5,08) MAX Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.430 (10,92) MAX

0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M

14/18 PIN ONLY 20 pin vendor option

D 4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.



1

MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN 0.020 (0,51) 0.014 (0,35)

0.050 (1,27) 8

0.010 (0,25)

5

0.008 (0,20) NOM

0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)

Gage Plane 1

4

0.010 (0,25) 0°– 8°

A

0.044 (1,12) 0.016 (0,40)

Seating Plane 0.010 (0,25) 0.004 (0,10)

0.069 (1,75) MAX

PINS **

0.004 (0,10)

8

14

16

A MAX

0.197 (5,00)

0.344 (8,75)

0.394 (10,00)

A MIN

0.189 (4,80)

0.337 (8,55)

0.386 (9,80)

DIM

4040047/E 09/01 NOTES: A. B. C. D.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012



1

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN 0,38 0,22

0,65 28

0,15 M

15

0,25 0,09 8,20 7,40

5,60 5,00

Gage Plane 1

14

0,25

A

0°–ā8°

0,95 0,55

Seating Plane 2,00 MAX

0,10

0,05 MIN

PINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01 NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150



1

MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30 0,19

0,65 14

0,10 M

8

0,15 NOM 4,50 4,30

6,60 6,20 Gage Plane 0,25

1

7 0°– 8° A

0,75 0,50

Seating Plane 0,15 0,05

1,20 MAX

PINS **

0,10

8

14

16

20

24

28

A MAX

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

DIM

4040064/F 01/97 NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153



1

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Class D amp

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