Lecture: Circuits & Layout
Outline
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
Outline
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
CMOS Gate Design
Activity: – Sketch a 4-input CMOS NOR NOR gate
A B C D Y
CMOS Circuit Styles
Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path
high noise margins - full rail to rail swing - VOH and VOL are at VDD and GND, respectively
low output impedance, high input impedance no steady state path between V DD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions)
Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes
simpler, faster gates increased sensitivity to noise
Complementary CMOS
Complementary CMOS logic gates – nMOS pull-down network
pMOS pull-up network
– pMOS pull-up network inputs
– a.k.a. static CMOS
Pull-up OFF
output
Pull-up ON
Pull-down OFF Z (float)
1
Pull-down ON
X (crowbar)
0
nMOS pull-down network
Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN) VDD PMOS transistors only In1 In2
PUN
InN In1 In2 InN
pull-up: make a connection from V DD to F when F(In1,In2,…InN) = 1 F(In1,In2,…InN)
PDN
pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0 NMOS transistors only
PUN and PDN are dual logic networks
Threshold Drops VDD
PUN
VDD VDD 0 CL
PDN VDD
VDD CL
0 CL
VDD CL
Threshold Drops VDD
PUN
VDD
S
D
VDD D
0 VDD
VGS
S
CL
PDN
VDD 0 D
VDD S
CL
0 VDD - VTn CL
VGS
VDD |VTp| S
D
CL
Construction of PDN
NMOS devices in series implement a NAND function A • B A B
NMOS devices in parallel implement a NOR function A + B A
B
Dual PUN and PDN
PUN and PDN are dual networks
DeMorgan’s theorems A + B = A • B
[!(A + B) = !A • !B or !(A | B) = !A & !B]
A • B = A + B
[!(A • B) = !A + !B or !(A & B) = !A | !B]
a parallel connection of transistors in the PUN corresponds to a series connection of the PDN
Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)
Number of transistors for an N-input logic gate is 2N
Series and Parallel
nMOS: 1 = ON Series: both must be ON
Parallel : either can be ON
g2
(a)
a g1
g2
(c)
a g1
g2 b
1 b
OFF
OFF
OFF
ON
a
a
0
a
1
1
1
0
1
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
b
0 b
0
(b)
1
b
a
b
1
1
0
g2
a
b
a g1
a
0
0 b
(d)
a
0
g1
pMOS: 0 = ON
a
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate – Series nMOS: Y=0 when both inputs are 1 – Thus Y=1 when either input is 0 – Requires parallel pMOS
Rule of Conduction Complements
Y A B
– Pull-up network is complement of pull-down – Parallel -> series, series -> parallel
Static CMOS Circuits N and P channel networks implement logic functions – Each network Connected between Output and VDD or VSS
CMOS NAND
A
A
B
F
0
0
1
0
1
1
1
0
1
1
1
0
B
A • B A B A B
CMOS NOR
B A A + B A
B
A B
A
B
F
0
0
1
0
1
0
1
0
0
1
1
0
Compound Gates
Compound gates can do any inverting function
Ex: A
C
A
C
B
D
B
D
(a)
A
(b)
B C
D
(c)
D
A
B
(d)
C
D
A
B
A
C
B
D
Y
(e)
C
A B C D (f)
Y
Layout of Complex Gate
Example: O3AI
A B C
D Y D
A
B
C
Practice 1
OUT = D + A • (B + C) B A C D A D B
C
Complex CMOS Gate
B A C D OUT = !(D + A • (B + C)) A D B
C
Practice 1 OUT = D + A • (B + C)
V DD
V DD
C F
SN1
SN4
F
A
SN3
D B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network hierarchically by identifying sub-nets
A D B
C
(c) complete gate
Standard Cell Layout Methodology
Routing channel VDD
signals
GND
What logic function is this?
Practice 2
Duality is not Necessary
Signal Strength
Strength of signal – How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0 – But degraded or weak 1
pMOS pass strong 1 – But degraded or weak 0
Thus nMOS are best for pull-down network
Gate Layout
Layout can be very time consuming – Design gates to fit together nicely – Build a library of standard cells
Standard cell design methodology – VDD and GND should abut (standard height) – Adjacent gates should satisfy design rules – nMOS at bottom and pMOS at top – All gates include well and substrate contacts
Example: Inverter
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
Stick Diagrams
Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers VDD
VDD
A
A
B
C
metal1 poly
c
ndiff pdiff
Y
GND
INV
Y
GND
NAND3
contact
Wiring Tracks
A wiring track is the space required for a wire – 4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
Well spacing
Wells must surround transistors by 6 l – Implies 12 l between opposite transistor flavors – Leaves room for one wire track
Area Estimation
Estimate area by counting wiring tracks – Multiply by 8 to express in l
40
32
Example: O3AI
Sketch a stick diagram for O3AI and estimate area –
Stick Diagrams
Stick Diagrams
Objectives: • To know what is meant by stick diagram. • To understand the capabilities and limitations of stick diagram. • To learn how to draw stick diagrams for a given MOS circuit.
Outcome: • At the end of this module the students will be able draw the stick diagram for simple MOS circuits.
Stick Diagrams
Stick Diagrams
N+
N+
Stick Diagrams
Stick Diagrams VDD
VDD X
x
x
Stick Diagram
x
X X
X Gnd
Gnd
x
Stick Diagrams
Stick Diagrams VDD
VDD X
x
x
x
X X
X Gnd
Gnd
x
Stick Diagrams
Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon.
stick diagrams are a means of capturing topography and layer information using simple diagrams.
Stick diagrams convey layer information through colour codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout.
Stick Diagrams
Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.
Stick Diagrams
Stick Diagrams
Does not show • Exact placement of components • Transistor sizes • Wire lengths, wire widths, tub boundaries. • Any other low level details such as parasitics..
Stick Diagrams
Stick Diagrams – Notations Metal 1 poly ndiff pdiff Can also draw in shades of gray/line style.
Similarly for contacts, via, tub etc..
Stick Diagrams
Stick Diagrams – Some rules Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.
Stick Diagrams
Stick Diagrams – Some rules Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).
Stick Diagrams
Stick Diagrams – Some rules Rule 3. When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.
Stick Diagrams
Stick Diagrams – Some rules Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.
Stick Diagrams
How to draw Stick Diagrams
Stick Diagrams
Stick Diagrams
Power
A
Out
C B
Ground
Stick Diagrams Contains no dimensions Represents relative positions of transistors V DD
V DD
Inverter
NAND2 Out
Out
In GND
GND
A
B
Stick Diagram Drawing : CMOS Steps 1)
Implement the expression in CMOS Logic
2)
Find all Euler paths that cover the graph
3)
Find n and p Euler paths that have same labeling
4)
Draw Stick diagram for optimization of diffusion areas
Stick Diagrams Logic Graph
A j
X
C
C
B X = C • (A + B) C A
i
i
X B
B
PUN
A B C
VDD
j GND
A PDN
PUN: Pull-up Network, PDN: Pull-down Network
Two Versions of C • (A + B) A
C
B
A
B
C
VDD
VDD
X
GND
Two Strips Line of Diffusions
X
GND
One Strip Line of Diffusions
Two Stick Layouts of !(C • (A + B)) crossover requiring vias A
C
B
A
B
C
VDD
VDD
X
X
GND
GND
uninterrupted diffusion strip
Consistent Euler Path An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C i
X B
VDD
j GND
A A B C
For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
OAI22 Logic Graph
A
C
B
D
X D
X = ((A+B)•(C+D)) C A
D B
C VDD
X B
A B C D
PUN
A
GND
PDN
OAI22 Layout A
B
D
C
VDD
X
GND
Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)
Example: x = AB + CD VDD Euler paths {A B C D } D
C
A
B X = AB + CD
C
B VDD
A
D
X GND
GND
A B C D Stick diagram for ordering { A B C D }
Example: x = ab+cd x c
b
V DD
x a
c
b
V D D
x a
d GND
d GND
(a) Logic graphs for (ab+cd )
(b) Euler Paths {a b c d } V D D
Euler Paths For both PUD and PDN
x
GND a
b
c
d
(c) stick diagram for ordering {a b c d }
Layout of Complex Gate
CMOS Gate1
OUT = (D+E).A+B C
Minimize area-Eulers path
Z
Euler graph APPROACH
Stick Diagram using Euler Graph Method
Stick Diagram Optimum Gate Ordering
Find a Euler path in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.
ALL IN ONE
Euler path: traverses each branch of the graph exactly once!
By reordering the input gates as E-D-A-B-C, we can obtain an optimum layout of the given CMOS gate with single actives for both NMOS and PMOS devices (below).
Stick diagram
Example: 1. Draw Logic Graph
Identify each transistor by a unique name of its gate signal (A, B, C, D, E in the example of Figure 1).
Identify each connection to the transistor by a unique name (1,2,3,4 in the example of Figure 1).
Example: 2. Define Euler Path
Euler paths are defined by a path the traverses each node in the path, such that each edge is visited only once. The path is defined by the order of each transistor name. If the path traverses transistor A then B then C. Then the path name is {A, B, C} The Euler path of the Pull up network must be the same as the path of the Pull down network. Euler paths are not necessarily unique. It may be necessary to redefine the function to find a Euler path. F = E + (CD) + (AB) = (AB) +E + (CD) 68
Example: 3. Connection label layout
Example: 4. VDD, VSS and Output Labels
Example: 5. Interconnected
