CHAPTER 4 4.1
Remainder 147 2 73 2 36 2 18 2 9 2 4 2 2 2 12 0
1 1 0 0 1 0 0 1
From the remainders, we get the 8-bit number as follows: N2 = 1 0 0 1 0 0 1 1 4.2
Remainder 145 2 72 2 36 2 18 2 9 2 4 2 2 2 1 2 0
1 0 0 0 1 0 0 1
From the remainders, we get the 8-bit number as follows: N2 = 1 0 0 1 0 0 0 1 4.3
Remainder 1149 2 574 2 287 2 143 2 71 2 35 2 17 2 8 2 4 2 2 2 12 0
1 0 1 1 1 1 1 0 0 0 1
From the remainders, we get the 12-bit number as follows: N2 = 0 1 0 0 0 1 1 1 1 1 0 1 Note that the MSB must be zero since we have only eleven remainders.
4.1
4.4
Remainder 872 2 436 2 218 2
0 0
109 2
0
54 2 13 2
1 0 1
6 2
1
3 2
0
1 2
1 1
27 2
0
From the remainders, we get the 12-bit number as follows: N2 = 0 0 1 1 0 1 1 0 1 0 0 0 Note that the MSB must be zero since we have only eleven remainders.
4.2
4.5 We first find the 8-bit number for +121: Remainder 121 2 60 2
1
30 2
0
15 2
0
7 2
1
3 2
1
12
1
0
1
The 8-bit number for +121 is 01111001. To find the 8-bit number for -121, we first invert the 8-bit number for +121: 10000110. Then we add 1 to obtain the 8-bit number for -121: 10000111. 4.6 We first find the 8-bit number for +101: Remainder 101 2 50 2 25 2 12 2 6 2 3 2 1 2 0
1 0 1 0 0 1 1
The 8-bit number for +121 is 01100101. To find the 8-bit number for -121, we first invert the 8-bit number for +121: 10011010. Then we add 1 to obtain the 8-bit number for -121: 10011011.
4.3
4.7
Remainder 891 2 445 2 222 2 111 2
1
55 2
1
27 2 13 2
1
6 2
1
3 2 12 0
1 1
1 0
1 0
The 2's complement binary equivalent is thus, 001101111011 4.8
Remainder 695 2 347 2 173 2 86 2 43 2 21 2 10 2 5 2 2 2 1 2 0
1 1 1 0 1 1 0 1 0 1
The 2's complement binary equivalent is thus, 001010110111
4.4
4.9 To find the decimal value for 10010001, we must first subtract 1 from the LSB thus giving: 10010000 Next, we invert the 1's and 0's as follows: 01101111 Finally, we evaluate the decimal: N10 0 27 1 26 1 25 0 2 4 1 23 1 22 1 21 1 20 111 N10 111
4.10 To find the decimal value for 10001001, we must first subtract 1 from the LSB thus giving: 10001000 Next, we invert the 1's and 0's as follows: 01110111 Finally, we evaluate the decimal: N10 0 27 1 26 1 25 1 2 4 0 23 1 2 2 1 21 1 20 119 N10 119
4.11 The following table presents the maximum decimal number versus the number of bits for simple binary: No. Bits
Max. Dec. No. Simple Binary
12 13 14 15 16
212 -1 = 4095 213 -1 = 8191 214 -1 = 16383 215 -1 = 32767 216 -1 = 65535
Consequently, 15 bits are needed to represent 27541 in simple binary. For a two's complement binary number, the MSB will be zero so 16 bits will be required.
4.5
4.12 The following table presents the maximum decimal number versus the number of bits for simple binary: No. Bits
Max. Dec. No. Simple Binary
12 13 14 15 16
212 -1 = 4095 213 -1 = 8191 214 -1 = 16383 215 -1 = 32767 216 -1 = 65535
Consequently, 14 bits are needed to represent 12034 in simple binary. For a two's complement binary number, the MSB will be zero so 16 bits will be required. 4.13 The following table presents the maximum decimal number versus the number of bits for simple binary: No. Bits 8 9 10 11 12
Max. Dec. No. for Simple Binary 28 -1 = 255 29 -1 = 511 210 -1 = 1023 211 -1 = 2047 212 -1 = 4095
Consequently, 10 bits are needed to represent 756 in simple binary. However, for -756, an additional bit is required to represent the sign. Hence, 11 bits will be required. The representation of -756 in 2's complement binary is 10100001100. 4.14 The following table presents the maximum decimal number versus the number of bits for simple binary: No. Bits 8 9 10 11 12
Max. Dec. No. for Simple Binary 28 -1 = 255 29 -1 = 511 210 -1 = 1023 211 -1 = 2047 212 -1 = 4095
Consequently, 10 bits are needed to represent 534 in simple binary. However, for -534, an additional bit is required to represent the sign. Hence, 11 bits will be required. The representation of -534 in 2's complement binary is 11011101010.
4.6
4.15
N = 12 Vru = 8V Vrl = -8V Vin = input voltage (a) By Eq. B in Fig. 4.7:
Vin Vrl N 2 Vru Vrl
D0 int
int
4.2 8 2 8 8
12
int 3123.2 3123
(b) By Eq. B in Fig. 4.7:
D0 int
5.7 8 2 8 8
12
int 588.8 589
(c) Since 10.9V falls outside the input range, D o will have the maximum output: D0 212 1 4095 (d) Since -8.5V falls outside the input range, D 0 will take the minimum value: D0 0
4.7
4.16
N = 12 Vru = 8V Vrl = -8V Vin = input voltage (a) By Eq. B in Fig. 4.7:
Vin Vrl N 2 Vru Vrl 2.4 8 12 int 2 8 8 int 2662.4
D0 int
2662 (b) By Eq. B in Fig. 4.7: 6.3 8 12 D0 int 2 8 8 int 3660.8 3660
(c) Since 11V falls outside the input range, Do will have the maximum output: D0 212 1 4095 (d) Since 9.2V falls outside the input range, D 0 will take the maximum value: D0 212 1 4095
4.8
4.17
N8 Vru 10V Vrl 0V Vin input voltage
a) By Eq. B in Fig. 4.7:
Vin Vrl N 2 Vru Vrl
D0 int
int
5.75 0 28 10 0
int 147.2
147
b) The input is below the input range. Hence the output will be 0, D0 = 0 c) Since 11.5V falls outside the input range, the output will be the maximum possible. The output will be: D0 28 1 255 d) By Eq. B in Fig. 4.7:
D0 int
0 0 28
10 0
0
4.9
4.18
N 8 V ru 15V V rl 0V Vin input voltage
a) By Eq. B in Fig. 4.7:
Vin V rl N 2 V ru V rl
D0 int
6.42 0 8 2 15 0
int
int 109.6 109
b) The input is below the input range. Hence the output will be 0, D0 = 0 c) By Eq. B in Fig. 4.7:
Vin Vrl N 2 Vru Vrl
D0 int
12 0 8 2 15 0
int
int 204.8 204
d) By Eq. B in Fig. 4.7:
0 0 8 2 15 0
D0 int 0
4.10
4.19 We need Equation A of Figure 4.7 to solve this problem. (a) When the 1.5V signal is amplified with a gain of 10, it becomes 15V which exceeds the input range of the A/D converter (it is saturated). According to Figure 4.7, the maximum output is 2N/2-1 = 112/2-1 = 2047 (b) With the gain of 10, the input becomes 8V. The output, in decimal, is then: V Vrl N 2 N 8 ( 10) 12 212 Do int in 2 int 2 1638 2 2 10 ( 10) Vru Vrl (c) When amplified, -1.5V results in an input to the A/D converter which is below the input range (it is saturated). The largest negative output is –2 N/2 = -2048 (d)With the amplifier, this voltage results in an input to the A/D of –8V. The output is then: V Vrl N 2 N 8 (10) 12 212 Do int in 2 int 2 1638 2 2 10 (10) Vru Vrl 4.20 We need Equation A of Figure 4.7 to solve this problem. (a) When the 5.2V signal is amplified with a gain of 10, it becomes 52V which exceeds the input range of the A/D converter (it is saturated). According to Figure 4.7, the maximum output is 2N/2-1 = 112/2-1 = 2047 (b) When the 1.5V signal is amplified with a gain of 10, it becomes 15V which exceeds the input range of the A/D converter (it is saturated). According to Figure 4.7, the maximum output is 2N/2-1 = 112/2-1 = 2047 (c) When amplified, -5.2V results in an input to the A/D converter which is below the input range (it is saturated). The largest negative output is –2 N/2 = -2048 (d) When amplified, -1.5V results in an input to the A/D converter which is below the input range (it is saturated). The largest negative output is –2 N/2 = -2048 4.21
N 16 Vru 5V Vrl 0V Vin 136 . V
From Eq. 4.1:
Vru Vrl Volts 2N
Input Resolution Error 0.5
5 0 Volts 216
0.5
3.815 10 5Volts
The quantization error (as a percent reading) for an input of 1.36V is: 3.815 10 5Volts 100 0.0028% 136 . Volts
4.22 4.11
N 12 Vru 5V Vrl 0V Vin 2.45V
From Eq. 4.1: Vru Vrl Input Resolution Error 0.5 2N
Volts
50 0.5 Volts 12 2 6.104 10 4 Volts
The quantization error (as a percent reading) for an input of 2.45V is: 6.104 10 4 Volts 2.45Volts
100 0.00025%
4.23 Quantization error is computed using equation 4.1.
Vru Vrl 2N For 8 bits this becomes 8 (8) input res error 0.5 0.0313V and this is 0.42% of the 7.5V input. 28 For 12 bits this becomes 8 (8) input res error 0.5 0.00195V and this is 0.026% of the 7.5V input. 212 For 16 bits this becomes 8 (8) input res error 0.5 0.000122 V and this is 0.0016% if the 7.5V 216 input. input res error 0.5
4.12
4.24 Quantization error is computed using equation 4.1.
Vru Vrl 2N For 8 bits this becomes 10 (10) input res error 0.5 0.0391V and this is 0.49% of the 8V input. 28 For 12 bits this becomes 10 (10) input res error 0.5 0.00244V and this is 0.031% of the 8V input. 212 For 16 bits this becomes 10 (10) input res error 0.5 0.000153V and this is 0.0019% if the 8V 216 input. input res error 0.5
4.25
N 12 Vru 8V Vrl 8V Vin 4.16V
From Eq. 4.1,
Vru Vrl Volts 2N
Input Resolution Error 0.5
8 8 Volts 212
0.5
1996 . 10 3Volts
The quantization error (as a percent reading) for an input of -4.16V is: 1996 . 10 3Volts 100 0.048% 4.16Volts
4.13
4.26
N 12 V ru 5V V rl 5V Vin 2.46V
From Eq. 4.1, Vru Vrl Volts Input Resolution Error 0.5 2N 5 5 Volts 0.5 212 1.221 10 3 Volts
The quantization error (as a percent reading) for an input of -2.46V is: 1.221 10 3 Volts 2.46Volts
100 0.050%
4.27 Since the signal from the transducer varies between 15mV (0.015V) and the A/D converter input range is 10V, we can select a gain of 100 which will yield an input of 1.5V. A gain of 100 is chosen such that the amplified signal is not saturated (i.e. greater than the input range). The quantization error from Eq. 4.1 is as follows: V V Quantization Error 0.5 ru N rl Volts 2 10 10
0.5
212
3
2.44 10 Volts
The transducer voltage is 3.75mV but after a gain of 100 it becomes 0.375V. Thus, the quantization error as a percent reading is as follows: 2.44 10 3Volts 100 0.651% 0.375Volts
If the transducer output were attenuated by a factor of 2/3 (to 10 mV) the gain could be set to 1000 without saturating the A/D converter. The 3.75 mv output would then become 3.7510-3(2/3)1000 = 2.5 V at the input to the A/D converter and the resolution error would be reduced to 0.098%.
4.14
4.28 The amplified input must not exceed 10V. When amplified, the maximum input will be 0.075V, 0.75V and 3.75V for gains of 10, 100 and 500 respectively. So we can use the maximum gain of 500. The input resolution error is: 10 (10) input res error 0.5 2.44m V 212 This is 0.033% of the maximum 7.5V input. 4.29 The amplified input must not exceed 10V. When amplified, the maximum input will be 0.1V, 1V and 5V for gains of 10, 100 and 2000 respectively. The gain of 2000 will saturate the amplified signal and become greater than the input limit of 10V. Thus the maximum gain that can be used is 100. The input resolution error is: 10 (10) input res error 0.5 2.44 m V 212 This is 0.024% of the maximum 10V input. 4.30
N8 Vru 5V Vrl 0V D in Digital input 32
The output range will be divided into increments of: incr.
5 0.0195 28
An input of 32 would then give an output of: Vout 32 0.0195 0.625V
4.15
4.31
N 12 Vru 10V Vrl 0V Din Digital input 45
The output range will be divided into increments of: 10 incr. 12 0.00244 2 An input of 45 would then give an output of:
Vout 45 0.00244 0.110V
4.32 The reference voltage increment is: input span 10 V 12 0.0024414 2 2N Trial digital output (D0) 100000000000 010000000000 011000000000 010100000000 010110000000 010101000000 010101100000 010101010000 010101001000 010101000100 010101000010 010101000011
(2048) (1024) (1536) (1280) (1408) (1344) (1376) (1360) (1352) (1348) (1346) (1347)
D0V
Pass/Fail
5.0 2.5 3.75 3.12 3.44 3.28 3.36 3.32 3.30 3.2901 3.286 3.289
F P F P F P F F F F P P
Actual digital output
010000000000 010000000000 010100000000 010100000000 010101000000 010101000000 010101000000 010101000000 010101000000 010101000010 010101000011
The output is 010101000011 or 1347 in decimal.
4.16
(1024) (1024) (1280) (1280) (1344) (1344) (1344) (1344) (1344) (1346) (1347)
4.33 The voltage increment is V = 16/212 = 0.00390625 V. Since this converter is offset binary, the expected input for a given digital output D o is 0.0039806Do 8.0. The expected input for the final output is 4.2 V. Trial Do
VDo - 8.
Pass/Fail
Actual Digital Output
100000000000 (2048) 110000000000 (3072) 111000000000 (3584) 110100000000 (3328) 110010000000 (3200) 110001000000 (3136) 110000100000 (3104) 110000110000 (3120) 110000111000 (3128) 110000110100 (3124) 110000110010 (3122) 110000110011 (3123)
0.0 4.0 6.0 5.0 4.5 4.25 4.125 4.1875 4.21875 4.203125 4.195313 4.199219
P P F F F F P P F F P P
100000000000 (2048) 110000000000 (3072) 110000000000 (3072) 110000000000 (3072) 110000000000 (3072) 110000000000 (3072) 110000100000 (3104) 110000110000 (3120) 110000110000 (3120) 110000110000 (3120) 110000110010 (3122) 110000110011 (3123)
The final output is 110000110011 in binary or 3123 in decimal. The same result is obtained from Eq. B in Figure 4.7. 4.34 non-linearity error ADC span error ADC zero amplifier gain MUX crosstalk quantization aperture drift
bias bias bias bias precision precision precision precision
4.35 How many channels available? How many bits does the ADC output? Is there programmable gain and what values of gain are possible? Maximum number of samples per second? Is there capability for automatic timing of data taking? Is there a simultaneous sample and hold capability? Is there a capability for digital input? Is there a capability for frequency input? (not discussed in chapter) Is there a capability for analog output? What range of input voltages will not permanently damage the system? What software is available for the system? If intended for a harsh environment, how durable is the package?
4.17
