Chapter 3 : Intel 8086

Chapter 3 : Intel 8086

Chapter 3 : Intel 8086 3.1 3.1

Feat Featur uree of 8086 8086 Micr Microp opro roce cess ssor or

3.2

Internal Ar Architecture of 8086 086

3.3

Internal Registers of 808 8086

3.4

Signal Desc escription of 8086

3.5

Genera eral Bu Bus Op Operation Cy Cycle

3.6

Minimum Mo Mode 80 8086 Sy System

3.7

Maximum Mode of 8086 System

3.8

Minimum Mode Interface

3.9

Maximum Mo Mode Interface

3.10

Addre dressing Modes des

3.11 3.11

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3.12

I/O Ad Addressing

3.13 3.13

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3.14 3.14

Ins Instruc tructi tion on Set Setss of of 808 8086 6

3.15 3.15

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3.16 3.16

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3.17 3.17

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3.18

Coprocessor 808 8087


Chapter 3 : Intel 8086 3.1 Feature of 8086 Microprocessor 

It is a 16-bit μp.

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8086 has a 20 bit address bus can access up to 220 memory locations (1 MB) .

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It can support up to 64K I/O ports.

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It provides 14, 16 -bit registers.

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It has multiplexed address and data bus AD0- AD15 and A16 – A19.

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It requires single phase clock with 33% duty cycle to provide internal timing.

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8086 is designed to operate in two modes, Minimum and Maximum.

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It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution.

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It requires +5V power supply.

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A 40 pin dual in line package

3.1.1 Minimum and Maximum Modes :

The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This This is

single single micro micropro proces cessor sor confi configur gurati ation. on.

The maxim maximum um mode is sele selecte cted d by

applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.

3.2 Internal Architecture of 8086

8086 has two blocks BIU and EU. The BIU performs all bus operations such as instr instruct uction ion fetchi fetching, ng, readin reading g and writin writing g operan operands ds for memory memory and calcul calculati ating ng the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate operate asynchronous asynchronously ly to give the 8086 an overlapping overlapping instruction instruction fetch and execution execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction


pointe pointer, r, Addres Addresss adder. adder. EU contain containss Contro Controll circui circuitry try,, Instru Instructi ction on decode decoder, r, ALU, ALU, Pointer , Index register and Flag register. 3.2.1 Bus Interfacr Unit:

It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Instru Instructi ction on fetch, fetch, Instru Instructi ction on queuing queuing,, Operan Operand d fetch fetch and storag storage, e, Addres Addresss relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. These intervals of no bus activity, which may occur betwee between n bus cycles cycles are known as Idle Idle state state. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. 3.2.2 Execution Unit

The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates


operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automa automatic ticall ally y resets resets the queue queue and then then begins begins to fetch fetch instru instructi ctions ons from from this this new location to refill the queue.

Figure 1 : Block Diagram of 8086 3.3 Internal Registers of 8086

The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers The 8086 has a total of fourteen 16-bit registers including a 16

bit register register called called the status status register, register, with 9 of bits implemen implemented ted for status and control control flags. Most of the registers registers contain contain data/instru data/instruction ction


offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of proc proces esso sorr memo memory ry thes these e 4 segm segmen ents ts are are loca locate ted d the the processor uses four segment registers:

3.3.1 Code segment (CS) is a 16-bit register containing address of 64 KB segm segmen entt with with

proc proces esso sorr inst instru ruct ctio ions ns.. The The proc proces esso sorr us uses es CS

segmen segmentt for all access accesses es to ins instru tructi ctions ons refer referenc enced ed by ins instru tructi ction on pointer (IP) register. CS register cannot be changed directly. The CS regi registe sterr is auto automa mati tica call lly y updat updated ed duri during ng far far jump jump,, far call call and and far return instructions.

3.3.2 Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.

3.3.3 Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.

3.3.4 Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.

3.3.5 Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.


3.3.6 Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low order byte of the word, and CH contai contains ns the high-o high-orde rderr byte. byte. Count Count regis register ter can be used used in Loop, Loop, shift/rotate instructions and as a counter in string manipulation,.

3.3.7 Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low order byte of the word, and DH cont contai ains ns the the high high-o -ord rder er byte byte.. Data Data regi regist ster er can can be us used ed as a port port numb number er in I/O I/O oper operat atio ions ns.. In inte intege gerr 32 32-b -bit it mult multip iply ly and and divi divide de instruction the DX register contains high-order word of the initial or resulting number.

The following registers are both general and index registers: 3.3.8 Stack Pointer Pointer (SP) (SP) is a 16 16-bi -bitt regis register ter pointing pointing to progra program m stack.

3.3.9 Base Pointer (BP) is a 16-bit register pointing to data in stack segm segmen ent. t. BP regi registe sterr is usual usually ly used used for for based based,, base based d inde indexe xed d or register indirect addressing.

3.3.10 Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions.

3.3.11 3.3.11 Destinat Destination ion Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.

Other registers: 3.3.12 Instruction Pointer (IP) is a 16-bit register. 3.3.13 Flags is a 16-bit register containing 9 one bit flags. 3.3.13.1 Overflow Flag (OF) - set if the result is too large positive numb number er,, or is too too smal smalll nega negati tive ve numb number er to fit fit into into dest destin inat atio ion n operand.


3.3.13 3.3.13.2 .2 Direct Direction ion Flag Flag (DF) (DF) - if set set then then stri string ng mani manipu pula lati tion on instructio instructions ns will auto-decrement auto-decrement index registers registers.. If cleared cleared then the index registers will be auto-incremented.

3.3.13 3.3.13.3 .3 Interr Interrupt upt-en -enabl able e Flag Flag (IF) (IF) - set setting ting this his bit bit enab enablles maskable interrupts.

3.3.13.4 Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.

3.3.13.5 Sign Flag (SF) - set if the most significant bit of the result is set.

3.3.13.6 Zero Flag (ZF) - set if the result is zero. 3.3.13.7 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.

3.3.13.8 Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.

3.3.13.9 Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation.

Figure 2 : Internal Registers of 8086


Figure 3 : Flag register of 8086 3.4 Signal Description of 8086

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ).The 8086 signals can be categorized in three group groups. s. Th Thee firs firstt are are the the sign signal al havin having g comm common on func functi tion onss in mini minimu mum m as well well as maximum mode. The second are the signals which have special functions for minimum mode mode and and thir third d are are the the sign signal alss havi having ng spec specia iall funct functio ions ns for for maxi maximu mum m mode mode.. Th Thee following signal descriptions are common for both modes. Thes esee are are the the time time mult multip iple lexed xed memo memory ry I/O I/O addre address ss and and data data lines lines.. AD15-AD0 : Th Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines.

During T1 these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. The S4 and S3 combined indicate which segment register is presently being used for memory accesses . These lines float to tri-


state off during the local bus hold acknowledge. The status line S6 is always low . The address bit are separated from the status bit using latches controlled by the ALE signal. S4 S3 Indication 0 0 Alternate Data 0 1 Stack 1 0 Code or none 1 1 Data BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher

order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle.

0 0 Whole word 0 1 Upper byte from or to even address 1 0 Lower byte from or to even address RD – Read : This signal on low indicates the peripheral that the processor is performing

memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY : This is the acknowledgement from the slow device or memory that they have

completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high. INTR-Interrupt INTR-Interrupt Request : This is a triggered input. This is sampled during the last

clock clock cycles cycles of each instruct instruction ion to determ determine ine the availab availabil ility ity of the reques request. t. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low,

execu executi tion on will will cont contin inue ue,, else else the the proce process ssor or rema remain inss in an idle idle stat state. e. Th Thee input input is synchronized internally during each clock cycle on leading edge of clock.

Chapter 3 : Intel 8086 CLK - Clock Input : The clock input provides the basic timing for processor operation

and bus control activity. Its an asymmetric square wave with 33% duty cycle. MN/MX : The logic level at this pin decides whether the processor is to operate in either

minimum minimum or maximum maximum mode. The following following pin functions functions are for the minimum mode operation of 8086. M / IO – Memory/IO : This is a status line logically equivalent to S2 in maximum mode.

When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge “. INTA – Interrupt Acknowledge : This signal is used as a read strobe for interrupt

acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt. ALE – Address Latch Enable : This output signal indicates the availability of the valid

address address on the address/dat address/dataa lines, lines, and is connected connected to latch enable input of latches. latches. This signal is active high and is never tristated. DT/R – Data Transmit/Receive : This output is used to decide the direction of data flow

through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. DEN – Data Enable : This signal indicates the availability of valid data over the

address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during ‘ hold acknowledge’ cycle. HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the

processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock clock cycle cycle after after comple completin ting g the current current bus cycle. cycle. At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided : 1. The request occurs on or before T2 state of the current cycle.


2. The current cycle is not operating op erating over the lower byte of a word. 3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A Lock Lock instru instructi ction on is not bein being g execut executed. ed. The following pin function are applicable for maximum mode operation of 8086 . S2, S1, S0 – Status Lines : These are the status lines which reflect the type of operation,

being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles. S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

Indication Interrupt Acknowledge Read I/O port Write I/O port Halt Code Access Read memory Write memory Passive

LOCK : This output pin indicates that other system bus master will be prevented from

gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the ‘LOCK’ ‘LOCK’ prefix prefix instruct instruction ion and remain remainss active active until until the comple completio tion n of the next next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction instruction ensures that other processors processors connected in the system will not gain the the control of the bus. The 8086, while executing the prefixed prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller. By prefet prefetchi ching ng the instru instructi ction, on, there there is a consid considera erable ble speedi speeding ng up in instru instructi ction on execution in 8086. This is known as instruction pipelining. At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even. The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte. The second byte is then decoded in continuation with the first byte to


decide decide the instruct instruction ion length length and the number of subseq subsequent uent bytes bytes to be treate treated d as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concur concurren rentl tly y execut executing ing the fetched fetched instru instructi ctions ons.. The next next byte byte after after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program. The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit. While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.

QS1 0 0 1 1

QS0 0 1 0 1

Indication No operation First byte of opcode from the Queue Empty queue Subs Subse equen quentt byte byte from from the the

queue RQ/GT0, RQ/GT1 – Request/Grant : These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected. Request/Grant

sequence is as follows: 1. A pulse of one one clock wide wide from another another bus bus master master requests requests the bus bus access to to 8086. 2. During During T4(current) T4(current) or T1(next T1(next)) clock cycle, cycle, a pulse pulse one clock wide wide from 8086 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the ‘hold ‘hold acknowledge’ acknowledge’ state at next cycle. The CPU bus interface interface unit is likely to be disconnected from the local bus of the system. 3. A one clock wide wide pulse from from the another another master master indica indicates tes to the 8086 8086 that the hold request request is about to end and the 8086 may regain control control of the local bus at the next clock cycle. Thus each master to master exchange of the the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange.


The request and grant pulses are active low. For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and a nd HLDA in minimum mode.

Figure 4 : Pin Diagram of 8086


Figure 5 : Signal Groups of 8086 3.5 General Bus Operation Cycle

The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus. The main reason behind multiplexing multiplexing address and data over the same pins is the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, when ever required. Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle. The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.


Figure 6 : General Bus Operation Cycle

3.6 Minimum Mode of 8086 System

In a mini minimu mum m mode mode 808 8086 6 syst system em,, the the micr microp opro roce cess ssor or 8086 8086 is opera operate ted d in minimum mode by strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required required for selecting selecting memory or I/O devices, devices, depending upon the address map of the system. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separa separate te the valid valid data data from from the time time multi multiplex plexed ed address address/da /data ta signal signals. s. They They are


control controlled led by two signals signals namely namely,, DEN and DT/R. DT/R. The DEN signal signal indica indicates tes the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices. The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus. The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2. The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers. A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.


Figure 7 : Minimum Mode 8086 Typical Configuration

Figure 8 : Write Cycle Timing Diagram for Minimum Mode


3.6.1 Hold Response sequence : The HOLD pin is checked at leading edge of each clock

pulse. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given to another requesting master. The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock.

Figure 9 : Bus Request and Bus Grant Timings in Minimum Mode System

3.7 Maximum Mode of 8086 System

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this mode, the processor derives the status signal S2, S1, S0. Another chip called called bus contro controlle llerr derive derivess the contro controll signal signal using using this this status status inform informati ation on .In the maximum mode, there may be more than one microprocessor in the system configuration. The components in the system are same as in the minimum mode system. The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines. The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU. It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. systems. AEN and IOB are generally generally grounded. CEN


pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin. If IOB is grounded, it acts as master cascade enable to control casc cascad adee 8259 8259A, A, else else it acts acts as peri periph pher eral al data data enab enable le used used in the the mult multip iple le bus bus configurations. INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC, IOWC are I/O read command and I/O write command signals respectively .These signals enable an IO interface to read or write the data from or to the address port. The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals. All these command signals instructs the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available. Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals. R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1. In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. If reader input is not activated before T3, wait state will be inserted between T3 and T4. 3.7.1 Timings for RQ/ GT Signals :

The reques request/g t/gran rantt respons responsee sequen sequence ce contai contains ns a series series of three three pulses pulses.. The request/grant pins are checked at each rising pulse of clock input. When a request is detected and if the condition for HOLD request are satisfied, the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state. When the requesting master receives this pulse, it accepts the control of the bus, it sends a release pulse to the processor using RQ/GT pin.


Figure 10 : Maximum Mode 8086 System.

Figure 11 : Memory Read Timing in Maximum Mode


Figure 12 : Memory Write Timing in Maximum mode.

Figure 13 : RQ/GT Timings in Maximum Mode.


3.8 Minimum Mode Interface

When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups : address/data bus, status, control, interrupt and DMA. 3.8.1 Address/Data Bus : these lines serve two functions. As an address bus is 20 bits

long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address space which is 64K bytes in length. The 16 data bus lines D0 through D15 are actually multiplexed with address ad dress lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller. 3.8.2 Status signal: The four most significant address lines A19 through A16 are also

multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines. Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle. Code S4S3 = 00 identifies a register known as extra segment register as register as the source of the segment address. Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level. S4 0 0 1 1

3.8.3 Control Signals :

S3 0 1 0 1

Segment Register Extra Stack Code / none Data


The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus. 3.8.4 ALE is a pulse to logic 1 that signals external circuitry when a valid address word

is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. Another control signal signal that is produced produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serves a second function, which is as the S7 status line. Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. The direction of data transfer over the bus is signaled by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. On the other hand, RD indicates that that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN ( data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal. 3.8.5 3.8.5 READ READY Y signal is used to insert wait states into the bus cycle such that it is

extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub-system to signal the 8086 when they are ready to permit the data transfer to be completed.

Chapter 3 : Intel 8086 3.8.6 Interrupt signals : The key interrupt interface signals are interrupt request (INTR)

and interrupt acknowledge ( INTA). 3.8.6.1 INTR is an input to the 8086 that can be used by an external device to signal that

it need to be serviced. Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output. The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input. If the logic 1 is found, the MPU suspend operation and goes into the idle state. state. The 8086 no longer executes executes instructi instructions, ons, instead it repeatedly repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0. As TEST switches to 0, execution resume with the next instruction in the program. This feature can be used to synchronize the operation of the 8086 to an event in external hardware. There are two more inputs in the interrupt interface: the non maskable interrupt NMI and the reset interrupt RESET. On the 0-to-1 transition of NMI control is passed to a non maskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 a nd initiates a reset service routine. 3.8.7 DMA Interface signals :The direct memory access DMA interface of the 8086

minimum mode consist of the HOLD and HLDA signals. When an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level. 3.9 Maximum Mode Interface

When the 8086 is set for the maximum-mode configuration, it provides signals for implementi implementing ng a multiproce multiprocessor ssor / coprocessor coprocessor system environment environment.. By multiprocess multiprocessor or environ environmen mentt we mean mean that that one microp microproc rocess essor or exists exists in the syste system m and that that each each processor processor is executing executing its own program. Usually Usually in this type of system environment environment,, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors.


These are known as local or private private resources. resources. Coprocessor also means that there is a second processor in the system. In this two processor does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum-mode 8086 system, facilities are provided for implementing allocat allocation ion of global global resour resources ces and passin passing g bus contro controll to other other microp microproc rocess essor or or coprocessor. 3.9.1 8288 Bus Controller – Bus Command and Control Signals :

8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces. Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow. S2 S1 S0 are input to the external bus controller device, the bus controller con troller generates the appropriately timed command and control signals. S2 0 0 0 0 1 1 1 1

S1 S0 CPU Cycles 8288 Command 0 0 Interrupt Acknowledge INTA 0 1 Read I/O Port IORC 1 0 Write I/O Port IOWC, IOWC 1 1 Halt None 0 0 Instruction Fetch MRDC 0 1 Read Memory MRDC 1 0 Write Memory MWTC, AMWC 1 1 Passive None The 8288 produces one or two of these eight command signals for each bus

cycles. For instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read cycle is to be performed. In the code 111 is output by the 8086, it is signaling that no bus activity is to take place. The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems.

3.9.2 The output of 8289 are bus arbitration signals :

Bus busy (BUSY), (BUSY), common bus request (CBRQ), bus priority priority out (BPRO), (BPRO), bus priority priority in (BPRN), bus request (BREQ) and bus clock (BCLK).


They correspond to the bus exchange signals of the Multi bus and are used to lock other processor off the system bus during the execution of an instruction by the 8086. In this this way the proces processor sor can be assure assured d of uninte uninterru rrupte pted d access access to common common syste system m resources such as global memory. 3.9.2.1 Queue Status Signals : Two new signals that are produced by the 8086 in the

maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2 bit queue status code, QS1, QS0. Following table shows the four different queue status. QS1

QS0 Queue Status

0 (low)

0

0

1

1 (high)

1

0 1

No Operation. During the last clock cycle, nothing was taken from the queue. First Byte. The byte taken from the queue was the first byte of the instruction. Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction.

3.9.2.2 Local Bus Control Signal – Request / Grant Signals : In a maximum mode

configuration, the minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus. 8086 Maximum mode

Block Diagram Maximum mode of 8086


3.10 Addressing Modes Of 8086

Addressing mode indicates a way of locating data or operands. Depending upon the data types used in the instruction and the memory addressing modes, any instruction may belong to one or more addressing modes, or some instruction may not belong to any of the addressing addressing modes. Thus the addressing addressing modes describe the types of operands and the way they are access accessed ed for executing executing an instru instructi ction. on. Here, Here, we will will presen presentt the addressing modes of the instructions instructions depending upon their types. types. According to the flow of instruction execution, the instructions may be categorized as (i) Sequential control flow instructions and (ii) Control transfer instructions. Sequential control flow instructions are the instructions which after execution, transfer control to the next instruction appearing immediately after it ( in the sequence ) in the program. For example, the arithmetic, arithmetic, logical, data transfer transfer and processor control instructions are sequential sequential control flow instructions.

The control control transfer instructions,

on the other hand, transfer control to some predefined address or the address somehow specified in the instruction, after their execution, For example, INT, CALL, RET and JUMP instructions fall fall under this category. category.


Thee addre Th address ssin ing g mode modess for for sequ sequen enti tial al and and cont contro roll tran transf sfer er inst instru ruct ctio ions ns are are explained as follows: 3.10.1 Immediate

In this type of addressing, immediate data is a part of instruction, and appears in the form of successive byte or bytes.

Example

MOV

AX, 0005H

In the above example, 000H is the immediate data. The immediate data may be 8 –bit or 16 –bit in size

3.10.2 Direct

In the direct addressing mode, a 16 – bit memory address (offset )is directly specified in the instruction as a part of it. Example

MOV

AX , [ 5000 H]

Here, data resides in a memory location in the data segment, whose effective address may be computed using 5000H as the offset address and content of DS as segment address. The effective address, here is 10H * Ds + 5000H.

3.10.3 Register

In the register addressing mode, the data is stored in a register register and it a register register and it is referred using the particular particular register. All the registers, except IP, may may be used in this mode. Example

MOV

BX, AX

3.10.4 Register Indirect


Sometimes, the address of the memory location which contains data or operand is determined n a indirect way, using using the offset registers. registers. This mode of addressing is known as register indirect mode. In this addressing mode, the offset address of data is in either BX or SI or DI register. The default segment is is either either DS or ES. The data is supposed to be available at the address pointed to by the content of any of the above registers in the default data segment.

Example

MOV AX, [BX] Here, data is present in a memory location in DS whose offset address is in BX. The effective address of the data given as 10H*DS +[BX].

3.10.5 Indexed

In this addressing mode, offset of the operand is stored in one of the index registers. DS is the default segment for index registers SI and DI. In case of string instruction DS and ES are default segment for SI and DI respectively. This mode is a special case of the above discussed register indirect addressing mode.

Example

MOV AX, [SI] Here, data is available available at an offset offset address stored stored in SI in DS. The effective effective address, address, in this case, is computed as 10H * DS + [SI].

3.10.6 Register Relative

In this addressing addressing mode, the data is available available at an effective effective address formed formed by adding an 8 –bit or 16 bit displacement with the content of any one of the registers BX, BP, SI and DI in the defaul defaultt (either (either DS or ES ) segmen segment. t. The example example given given below explains this mode.

Chapter 3 : Intel 8086 Example

MOV AX, 50H [BX] Here, the effective address is given as 10H*DS + 50H + [BX]

3.10.7 Based Indexed

The effective address of data is formed, in this addressing mode, by adding content of a base register (any one of BX or BP ) to the content of an index register (any one of SI or DI). The default segment register may be ES or DS.

Example

MOV AX, [BX ] Her, Her, BX is the base regis register ter and and SI is the index index registe register. r.

The effec effectiv tivee address address is

computed as 10H* DS + [BX] + [SI]

3.10.8 Relative Based Indexed

The effective address is formed by adding an 8 or 16 – bit displacement with the sum of contents of any one of the base registers (BX or BP) and any one of the index registers, in a default segment.

Example

MOV AX, 50H [ BX] [SI] Here, 50H is an immediate displacement, BX is base register and SI is an index register. The effective address of data is computed as 10H*DS+[BX]+[SI]+50H.

For the control transfer instructions, the addressing modes depend upon whether the destinatio destination n location is within within the same segment or in a different one. It also depends depends upon the method of passing passing the destination address address to the processor. processor. Basically, there are two addressing modes for the control transfer instructions, viz. intransigent addressing modes .


If the location to which the control is to be transferred lies in a different segment other other than the curren currentt one, one, the mode is called called incensem incensement ent mode. mode. If the desti destinati nation on location lies in the same segment, the mode is called intransigent mode. Figure shows the modes for control transfer instructions. Inter segment direct Inter segment Modes for control

Inter segment indirect

transfer instructions

Intra segment direct Intra segment Intra segment indirect

3.10.9 Intra segment Direct Mode

In this mode, the address to which the control is to be transferred lies in the same segm segmen entt in whic which h the the cont contro roll tran transf sfer er inst instru ruct ctio ion n lies lies and and appe appear arss dire direct ctly ly in the the instr instruct uction ion ‘n’ as an immed immediat iatee displa displacem cement ent value. value. In this this address addressing ing mode, mode, the displacement is computer relative to the control of o f the instruction pointer IP The effective address to which the control will be transferred is given by the sum of 8 or 16 bit displacement and current control of IP. In case of jump instruction, if the signed displacement (d) is of 8 bits ( i.e-128
LABEL lies with in -128to +127 form the current IP content. Thus SHORT LABLE is 8 –bit signed displacement. A 16 –bit target address of a label indicates that it lies within -32768 to+32767. But a problem arises when one requires a forward jump at a relative address greater than 32767or backward jump at relative address -32768; in the same segment. Suppose current contents of IP are 5000H then a forward jump may be allowed at all the displacement DISP so that IP+DISP=FFFFH or DISP=FFFF-5000=AFFFH. Thus forward jumps may be allowed for all 16-bit displacement values from 0000H to AFFFH. If displacement exceeds AFFFH i.e. form B000H to FFFFH , then all such jump and coded as below. JMP NEAR PTR LABLE

Chapter 3 : Intel 8086 3.10.10 Intra segment Indirect Mode

In this mode, the displacement to which the control is to be transferred, is in the same same segmen segmentt in which which the control control trans transfer fer instruct instruction ion lies, but it is passed passed to the instruction indirectly. Here, the branch address is found as the control of a register or a memory location. This addressing mode may be used in unconditional branch instruction. Example JMP [BX]; Jump to effective address stored in BX.

JMP [BX + 500H] 3.10.11 Inter segment Direct

In this mode, the address to which the control is to be transferred is in a different segment. segment. This addressin addressing g mode provides a means of branching branching from one code segment to another code segment. segment. Here, the CS and IP of the destination destination address are are specified specified directly in the instruction. Example

JPM 5000H : 2000H; JUMP to effective address 2000H in segment 5000H

3.10.12 Inter segment Indirect

In this mode, the address to which the control is to be transferred lies in a different segment and it is passed to the the instruction indirectly, indirectly, i.e. contents of a memory b blo lock ck cont contai aini ning ng four four byte bytes, s, i.e. i.e. IP(L IP(LSB SB)/ )/,I ,IP( P(MS MSB) B),, CS(L CS(LSB SB)) and and CS(M CS(MSB SB)) sequentially. The starting address of the memory block memory block may be referred using any of the addressing modes, except immediate mode.

Example

JMP [2000H] JUMP to an address in the other segment specified at effective address 2000H in DS, that points to the memory block as said above.

Chapter 3 : Intel 8086 Forming the Effective Addresses

The follow following ing exampl examples es explai explain n formin forming g of the effect effective ive addres addresses ses in the different modes.

Example

The contents contents of differ different ent register registerss are given given below. below.

From From effect effective ive addresse addressess for

different addressing modes. Offset (displacement) = 5000H [AX] – 1000H,[BX] – 2000H, [SI] – 3000H/ [DI] – 4000H,[BP[ - 5000H, [SP] – 6000H,[CS] –0000H,[DS]-1000H, [SS] –2000H,[IP] – 7000H. Shifting a number four times is equivalent to multiplying it by 16D or 10H (i) Direct addressing mode

MOV AX, [5000H] DS: OFFSET

↔

10H*DS

↔

offset

↔

1000H: 5000H 1000 + 5000 15000H – Effective address

(ii) Register indirect

MOV AX, [BX] DS: BX 10H*DS

↔

1000H:2000H 10000

↔

[BX]

+2000

↔

12000H – Effective address (iii) Register relative

MOV AX, 5000 [BX] DS : [5000 + BX] 10H*DS

↔

1000

Offset

↔

+5000

[BX]

↔

+2000 17000H – Effective address


(iv) Based indexed

MOV AX, [BX] [SI] DS:[BX +SI] 10H* DS

↔

1000

[BX]

↔

+2000

[SI]

↔

+3000 15000H – Effective address

(v)

Relative ba based in indexed

MOV AX, 5000 [BX] [SI] DS: [BX + SI + 5000] 10H* DS [BX] [SI]

↔ ↔

↔

Offset

10000 +2000

+3000 ↔

+5000 1A000 - effective address

Below, we present examples of address ad dress formation in control transfer instructions.

3.11 Memory Organization

The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to the rules of the following following table. All information information in one segment type share the same logical attributes (e.g. code or data). By structuring memory into re locatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured. Word (16-bit) operands can be located on even or odd address boundaries and are thus not constrained to even boundaries as is the case in many


16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location. The BIU automatically performs the proper number of memory accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the software. This performance penalty does not occur for instruction fetches, only word operands. Physically, the memory is organized as a high bank (D15±D8) and a low bank (D7±D0 (D7±D0)) of 512 512K K 8-bit 8-bit bytes bytes address addressed ed in parall parallel el by the proces processor sor's 's address address lines lines A19±A1. Byte data with even addresses is transferred on the D7±D0 bus lines while odd addressed byte data (A0 HIGH) is transferred on the D15±D8 bus lines. The processor provides two enable signals, BHE and A0, to selectively allow reading from or writing into either an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd address, respectively. Consequently, in referencing word operands performance can be optimized by locating data on even address boundaries. This is an especially useful technique for using the stack, stack, since since odd addres addresss refere reference ncess to the stack stack may advers adversely ely affect affect the context context switching time for interrupt processing or task multiplexing. Certain locations in memory are reserv reserved ed for specif specific ic CPU operati operations ons (see (see Figure Figure 14). 14). Locati Locations ons from from addres addresss FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will always begin execution at locati location on FFFF0H FFFF0H where where the jump must must be. Locati Locations ons 00000H 00000H through through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address. The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts. Program, data and stack memories occupy the same memory space. As the most of the processor instructions use 16-bit pointers the processor can effectively address only


64 KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memo memory ry 16-b 16-bit it poin pointe ters rs and and data data are are stor stored ed as: as: addre address ss:: lowlow-or orde derr byte byte address+1: high-order byte 3.11.1 Program Memory - program can be located anywhere in memory. Jump and call

instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 to - 127 bytes from current instruction. 3.11.2 Data Memory - the processor can access data in any one out of 4 available

segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. 3.11.3 Stack Memory can be placed anywhere in memory. The stack can be located at

odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above). Reserved Locations : 0000H - 03FFH are reserved for interrupt vectors. Each interrupt vector is a 32-bit

pointer in format segment: offset. FFFF0H - FFFFFH - after RESET the processor always starts program execution at the

FFFF0H address.


Figure 14: Reserved Memory Memory Locations 3.12 I/O Addressing


In the 8086, I/O operations can address up to a maximum of 64K I/O byte registers or 32K I/O word registers. The I/O address appears in the same format as the memory address on bus lines A15±A0. The address lines A19±A16 are zero in I/O operations. The variable I/O instructions which use register DX as a pointer have full address capability while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory locations. Even addressed bytes are transferred on the D7±D0 bus lines and odd addressed bytes on D15±D8. Care must be taken to assure that each register within an 8-bit peripheral located on the lower portion of the bus be addressed as even.

Figure 15 : I/O Space of the processor 3.13 Interrupts and Exceptions

Interr Interrupt uptss and except exception ionss alter alter the normal normal progra program m flow flow in order order to handle handle external events, report errors or exceptional conditions. The difference between interrupts and exceptions is that interrupts are used to handle asynchronous external events while excepti exceptions ons handle handle instru instructi ction on fault faults. s. Althou Although gh a progra program m can genera generate te a softwa software re interrupt via an INT N instruction, the processor treats software interrupts as exceptions. Hardware interrupts occur as the result of an external event and are classified into two types: types: maskabl maskablee or non non-ma -maska skable ble.. Interr Interrupt uptss are servic serviced ed after after the execut execution ion of the curren currentt instru instructi ction. on. After After the interr interrupt upt handle handlerr is finis finished hed servic servicing ing the interr interrupt upt,, execution proceeds with the instruction immediately after the interrupted instruction. Exceptions are classified as faults, traps, or aborts, depending on the way they are reported and whether or not restart of the instruction causing the exception is supported. Faults are exceptions that are detected and serviced before the execution of the faulting instruction. Traps are exceptions that are reported immediately after the execution of the


instruction which caused the problem. Aborts are exceptions which do not permit the precise location of the instruction causing the exception to be determined. Thus, when an interrupt service routine has been completed, execution proceeds from the instruction immediately following the interrupted instruction. On the other hand, the return address from an exception fault routine will always point to the instruction causing the exception and will include any leading instruction prefixes. 3.13.1 Interrupt Processing

When an interrupt occurs, the following actions happen. h appen. First, the current program address and Flags are saved on the stack to allow resumption of the interrupted program. Next, an 8-bit vector is supplied to the Microprocessor which identifies the appropriate entry in the interrupt table. The table contains the starting address of the interrupt service routine. Then, the user supplied interrupt service routine is executed. Finally, when an IRET instruction is executed the old processor state is restored and program execution resume resumess at the appropr appropriat iatee instru instructi ction. on. The 8-bit 8-bit interr interrupt upt vector vector is suppli supplied ed to the Microp Microproc rocess essor or in severa severall differ different ent ways: ways: except exception ionss supply supply the interr interrupt upt vector vector internally; software INT instructions contain or imply the vector; maskable hardware interrupts supply the 8-bit vector via the interrupt acknowledge bus sequence. NonMaskable hardware interrupts are assigned to interrupt vector 2. 3.13.1.1 INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled

using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 * . Interrupt processing routine should return with the IRET instruction. 3.13.1.2 NMI is a non-maskable interrupt. Interrupt is processed in the same way as the

INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority then the maskable interrupt. 3.13.1.3 Software Interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.


INT instruction - any one interrupt from available 25 6 interrupts. INTO instruction - interrupt on overflow Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. 3.13.2 Processor Exceptions Exceptions : Divide Error (Type 0), Unused Opcode (type 6) and

Escape opcode (type 7). Software interrupt processing is the same as for the hardware interrupts.

Figure 16 : Interrupt Service


Vector Table


Chapter 3 : Intel 8086 Hardware External Interrupt

Chapter 3 : Intel 8086 Example Program Flow For A Software Interrupt

Chapter 3 : Intel 8086 3.14 Instruction Sets of 8086 3.14 .1 DATA TRANSFER INSTRUCTIONS 

PU SH

-

Copy specified word to top of stack.



POP POP

-

Copy Copy wor word from from top top of stack tack to speci pecifi ficc loca locattion. ion.



PU SH A

-

(80186/80188 only) Copy all registers stack.



POPA POPA

-

(801 (80186 86/8 /80l 0l88 88 only only)) Copy Copy word wordss f stac stack k to all all regi regist ster ers. s.



XCHG

-

Exchange bytes or exchange words.



X LA T

-

Translate a byt byte in AL using a table in memory.

3.14 .2 INPUT AND OUTPUT PORT TRANSFER INSTRUCTION: 

IN

-

Copy a byte or word from specified port to accumulator



O UT

-

Copy a byte or word from accumulator specified port.

3.14 .3 SPECIAL ADDRESS TRANSFER INSTRUCTION 

L EA

-

Load effective address to register



LD S

-

Load pointer to DS



LES

-

Load pointer to ES

3.14 .4 FLAG TRANSFER INSTRUCTIONS: 

LA H F

-

Load \ah with flags



SAHF

-

store AH into flags



PUSHF

-

Push flags



POPF

-

POP flags

3.14 .5 ARITHMETIC INSTRUCTIONS 3.14 .5.1ADDITION INSTRUCTIONS: 

ADD ADD -

Add Add spec speciified fied byt byte to byt byte or speci peciffied wor word to word. ord.



ADC ADC -

Add Add byte byte + byt byte + carr carry y flag flag or word ord + wor word + carr carry y flag flag..



INC

Increment speci ecified byte or specified by 1.



AAA -

ASCII adjust after addition.



DAA -

Decimal (BCD) adjust after addition.

-

3.14 .5.2 SUBTRACTION INSTRUCTIONS: 

SU B

-

Sub Subtract byte from byte or word ord from word ord.

Chapter 3 : Intel 8086 

SBB SBB

-

Subt Subtra ract ct byte byte and and carr carry y flag flag from from byte byte word word and and carr carry y flag flag from from word.



DEC DEC



N EG -

-

Decr Decrem emen entt speci peciffied byt byte or spec speciified fied word word by l. Neg Negate – invert each bi bit of a sp specified by byte or word and ad add 1 (form 2’s complement).



CMP CMP -

Com Compare pare two spec speciified ied byte bytess or two spec speciified fied word ord



AAS

-

ASCII adjust after subtraction.



DAS

-

Deci ecimal (BCD) adjust ust aft after subtraction.

3.14 .5.3 MULTIPLICATION INSTRUCTIONS: 

MUL

-

Multiply unsigned byte by byte or unsigned word by word



IMUL

-

Integer Multiplication



AAM

-

ASCII Adjust after Multiplication

3.14 .5.4 DIVISION INSTRUCTIONS: 

DIV DIV

-

Divi Divide de unsi unsign gned ed word word by byt byte or uns unsigne igned d doub doublle wor word by word



IDIV

-

Integer Division



AAD

-

ASCII Adjust after Division



CBW

-

Convert Byte to word



CWD

-

Convert word to double word

3.14 .6 BIT MANIPULATION INSTRUCTIONS 3.14 .6.1 LOGICAL INSTRUCTIONS: 

NOT NOT -

Inve Invert rt each each bit bit in a byte byte or wor word



AND -

AND the conten contentt of of a byte byte or or a word word with with anot another her byte byte or or word word



OR

OR the the cont conten entt of a byte byte or a word word with with anot anothe herr byte byte or word word



XOR -

-

Exclusi Exclusive ve OR the conten contentt of of a byte byte or or a word word with with anot another her byte byte or or word



TEST TEST -

AND AND fun funct ctio ion n to to fla flags gs,, No No res resul ultt

3.14 .6.2 SHIFT INSTRUCTIONS: 

SHL/SAL -

Shift bits of word or byte left, put zero(s) in LSB(s)

Chapter 3 : Intel 8086 

SHR

-

Shift bits of word or byte right, put zero(s) in MSB(s)



SAR SAR

-

Shif Shiftt bit bits of wor word or byt byte righ rightt, copy copy old old MSB into nto new new MSB

3.14 .6.3 ROTATE INSTRUCTIONS: 

ROL ROL



R OR -

Rotate bi bits of of byte or word right, LS LSB to MSB and to CF



RCL RCL

-

Rot Rotate ate bit bits of byt byte or word word left eft, MSB to CF and and CF to LSB LSB



RCR

-

Rotate bi bits of of byte or word right, LS LSB to CF an and CF CF to MS MSB

-

Rot Rotate ate bit bits of byt byte or word word left eft, MSB to LSB LSB and and to CF

3.14 .7 STRING INSTRUCTIONS 

REP

-

Repeat until CX = 0



REPE / REPZ

-

Repeat equal / Repeat zero until CX = 0 Or

Zero flag ZF!=1 

REPN REPNE E / RE REPNZ PNZ -

Repe Repeat at not not equa equall / Repe Repeat at not not zer zero unt untiil CX = 0 or ZF = 1



MOVS / MOVSB / MOVSW -

Move byte byte / word / byte word



COMPS / COMPSB / COMPSW- compare byte / word / byte word



SCAS SCAS / SCASB SCASB / SCASW SCASW

-

scan scan byte byte / word word / byte byte word word



LODS LODS / LODSB LODSB / LODSW LODSW

-

Load Load byte byte / word word / byte byte word word to AL / AX



STOS / STOSB STOSB / STOSW STOSW

-

Store Store byte byte / word word / byte byte word word from from AL / AX

3.14 .8 PROGRAM EXECUTION TRANSFER INSTRUCTIONS 3.14 .8.1 UNCONDITIONAL TRANSFER INSTRUCTIONS: 

RET RET

-

Retu Return rn from from proc proced edur uree to call callin ing g prog progra ram m



JMP

-

Go to sp specified ad address to ge get next instruction



CALL CALL -

Call Call a proc proced edur uree (su (subp bpro rogr gram am), ), save save retu return rn addr addres esss on stac stack k

o

Direct within-segment (near or intrasegment)

o

Indirect within-segment (near or intrasegment)

o

Direct to another segment (far or intersegment)

o

Indirect to another segment (far or intersegment)

Chapter 3 : Intel 8086 3.14 .8.2 CONDITIONAL TRANSFER INSTRUCTIONS: 

JA/JN JA/JNBE BE - Jump Jump if above/J above/Jump ump if not not below below or equal equal



JAE/JN JAE/JNB B



JB/JNAE -Jump if below/Jump if not above or equal



JBE/JNA -Jump if below or equal/Jump if not above



JC

- Jump if carry flag CF 1



JE/ JE/JZ

- Jum Jump if equa equall/Jum /Jump p if zero zero flag ZF = 1



JG/JNLE JG/JNLE - Jump Jump if greater/Ju greater/Jump mp if not less less than or equal equal



JGE/JNL -Jump if greater than or equal Jump if not less than



JL/JNGE -Jump if less than/Jump than/Jump if not greater than or equal



JLE/JNG JLE/JNG

-Jump if less less than than or equal/Jump equal/Jump if if not greater greater than than



JNC

-Jump if no carry (CF = 0)



JNE/JN JNE/JNZ Z - Jump Jump if not equal/ equal/lum lump p if not ’ zero zero (ZF (ZF = 0)



JNO



JNP/JP JNP/JPO O -Jump -Jump if not not parit parity/J y/Jump ump if if parit parity y odd (PF (PF = 0)



JNS

- Jump if not sign (sign flag SF=0)



JO

- Jump if overflow flag OF=1



JP/J JP/JPE PE

- Jump Jump if if pari parity ty/J /Jum ump p if pari parity ty even even (PF (PF =1) =1)



JS

- Jump if sign (SF = 1)

-Jump -Jump if above above or equal equal/Ju /Jump mp if not belo below w

-Jump if no overflow (overflow flag OF = 0)

3.14 .9 ITERATION CONTROL INSTRUCTIONS: 

LO O P

-



LOOPE / LOOPZ -

Loop while equal / not zero



LOOP LOOPNE NE / LOOP LOOPNZ NZ--

Loop Lo op whi while le not not equ equal al / not not zero zero



JCX Z

Jump on CX zero

-

Loop CX times

3.14 .10 INTERRUPT INSTRUCTIONS: 

IN T

-

Interrupt type specified



I N TO

-

Interrupt on overflow



IR E T

-

Interrupt return

3.14 .11 PROCESS CONTROL INSTRUCTIONS


FLAG SET / CLEAR INSTRUCTIONS: 

STC - Set carry carry flag flag CF to 1



CLC - Clear Clear carry carry flag flag CF to to 0



CMC - Complement the state of the carry flag CF



STD

- Set direct direction ion flag flag DF DF to l (decr (decreme ement nt strin string g pointe pointers) rs)



CLD

-Clear direction flag DF to 0



STI

-Set interrupt enable flag to 1 (enable INTR input)



CLI

-Clear interrupt enable flag to 0 (disable INTR input)

3.14 .12 EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS: 

HLT



WAIT - Wait (do nothing) until signal on the test pin is low



ESC



LOCK - An instruction prefix. prefix. Prevents another another processor from taking the bus

- Halt (do nothing) until interrupt or reset

-Escape to external coprocessor such as 8087 or 8089

while the adjacent instruction executes 

NOP

- No action except fetch and decode

Example AAA Instruction Instruction - AAA converts the result of the addition of two valid unpacked BCD

digits to a valid 2-digit BCD number and takes the AL register as its implicit operand. Two operands of the addition must have its lower 4 bits contain a number in the ange from 0-9.The AAA instruction then adjust AL so that it contains a correct BCD digit. If the addition produce carry (AF=1), the AH register is incremented and the carry CF and auxiliary carry AF flags are set to 1. If the addition did not produce a decimal carry, CF and AF are cleared to 0 and AH is not altered. In both cases the higher 4 bits of AL are cleared to 0. AAA will adjust the result of the two ASCII characters that were in the range from 30h (“0”) to 39h(“9”).This is because the lower 4 bits of those character fall in the range of 0-9.The result of addition is not a ASCII character but it is a BCD digit. Example:

MOV MOV AH,0 AH,0

; Cl Clear ear AH for MSD

MOV AL,6

; BCD 6 in AL


ADD AL,5

; Add BCD 5 to digit in AL

AAA

; AH=1, AL=1 representing BCD 11.

AAD Instruction - ADD converts unpacked BCD digits in the AH and AL register into a

single binary number in the AX register in preparation for a division operation. Before executing AAD, place the Most significant BCD digit in the AH register and Last significant in the AL register. When AAD is executed, the two BCD digits are combined into a single binary number nu mber by setting AL=(AH*10)+AL and clearing AH to 0.

Example:

MOV AX,02 ,0205h

; The unpa npacked BCD number ber 25

AAD

; Af After AAD , AH=0 and;AL=19h (25)

After the division AL will then contain the unpacked BCD quotient and AH will contain the unpacked BCD remainder. Example:

;AX=0607 unpacked BCD for 67 decimal ;CH=09H AAD DIV CH

;Adjust to binary before division ;AX=0043 = 43H =67 decimal ;Divide AX by by unp unpacked BCD BCD in CH CH ;AL ;AL = quotient = 07 unpacked BCD ;AH = remainder = 04 unpacked BCD

AAM Instruction - AAM converts the result of the multiplication of two valid unpacked

BCD digits into a valid 2-digit unpacked BCD number and takes AX as an implicit operand. To give a valid result the digits that have been multiplied must be in the range of 0 – 9 and the result should have been placed in the AX register. Because both operands of multiply are required to be 9 or less, the result must be less than 81 and thus is completely contained in AL. AAM unpacks the result by dividing AX by 10, placing the quotient (MSD) in AH and the remainder (LSD) in AL. Example:

MOV AL, 5 MOV BL, 7


MUL BL

; Multiply AL by BL , result in AX

AAM

; After AAM, AX =0305h (BCD 35)

AAS Instruction Instruction - AAS converts the result of the subtraction of two valid unpacked

BCD digits to a single valid BCD number and takes the AL register as an implicit operand. The two operands of the subtraction must have its lower 4 bit contain number in the range from 0 to 9 .The AAS instruction then adjust AL so that it contain a correct BCD digit. MOV AX,0901H

; BCD 91

SUB AL, 9

; Minus 9

AAS

; Give AX =0802 h (BCD 82)

(a)

; AL =0011 1001 =ASCII =ASCII 9 ;BL=0011 0101 =ASCII 5 SUB AL, BL

; (9 - 5) Result AL = 00000100 = BCD 04,CF = 0

AAS

;Result AL=00000100 =BCD 04 CF = 0 NO Borrow required

(b)

;AL = 0011 0101 =ASCII 5 BL = 0011 1001 = ASCII 9 SUB AL, BL

;( 5 - 9 ) Result AL = 1111 1100 = - 4 in 2’s complement CF = 1

AAS

;Results AL = 0000 0100 =BCD 04 CF = 1 borrow needed .

ADD Instruction - These instructions add a number from source to a number from some

destination and put the result in the specified destination. The add with carry instruction ADC, also add the status of the carry flag into the result. The source and destination must be of same type , means they must be a byte location or a word location. If you want to add a byte to a word, you must copy the byte to a word location and fill the upper byte of the word with zeroes before adding. EXAMPLE:

ADD AL,74H

; Add immediate number 74H to content of AL

ADC ADC CL,BL

; Add contents nts of BL plus carry status to con contents nts of CL.


ADD DX, BX

; Add contents of BX to contents ;of DX

ADD DX, [SI]

; Add word from memory at offset [SI] in DS to contents of DX ; Addition of Un Signed numbers

ADD ADD CL CL, BL BL

; CL CL = 01 011100 10011 =1 =115 de decimal ;+ BL BL = 010 0100111 1111 = 79 de decimal ; Result in CL = 11000010 = 194 decimal Addition of Signed numbers

ADD CL, BL

; CL = 01110011 = + 115 decimal + BL = 01001111 = +79 Decimal Result in CL = 11000010 = - 62 decimal ; Incorrect because result is too large to fit in in 7 bits.

AND Instruction - This Performs a bitwise Logical AND of two operands. The result of

the operation is stored in the op1 and used to set the flags. AND op1, op2 To perform a bitwise AND of the two operands, each bit of the result is set to 1 if and only if the corresponding bit in both of the operands is 1, otherwise the bit in the result I cleared to 0

AND BH, CL

; AND byte in CL with byte in BH result in BH

AND AND BX, BX,00 00FF FFh h

; AND AND word word in BX with with imme immedi diat atee 00FF 00FFH. H. Mask Mask uppe upperr byt byte, e, leave lower unchanged

AND CX,[SI]

; AND word at offset [SI] in data segment with word in CX ; register . Result in CX register . BX = 10110011 01011110

AND BX,00FFh

; Mask out upper 8 bits of BX Result BX = 00000000 01011110 ; CF =0 , OF = 0, PF = 0, SF = 0 , ZF = 0

CALL Instruction Instruction - This Instruction is used to transfer execution to a subprogram or

procedure. There are two basic b asic types of CALL ’s : Near and Far. A Near CALL is a call to a procedure which is in the same code segment as the CALL instruction . When 8086 executes the near CALL instruction it decrements the stack pointer by two and copies the offset of the next instruction after the CALL on the stack. This offset saved on the stack is referred referred as the return address, address, because this is the address address that executi execution on will will return returnss to after after the procedure procedure execute executes. s. A near near CALL CALL instruction will also load the instruction pointer with the offset of the first instruction in the procedure.


A RET RET inst instru ruct ctio ion n at the the end end of the the proc proced edur uree will will retu return rn exec execut utio ion n to the the instruction after the CALL by coping the offset saved on the stack back to IP. A Far CALL is a call to a procedure which is in a different from that which contains the CALL instruction . When 8086 executes the Far CALL instruction it decrements the stack pointer by two again and copies the content of CS register to the stack. It then decrements the stack pointer by two again and copies the offset contents offset of the instruction after the CALL to the stack. Finally it loads CS with segment base of the segment which contains the procedure and IP with the offset of the first instruction of the procedure in segment. A RET instruction at end of procedure will return to the next instruction after the CALL by restoring the saved CS and IP from the stack. Direct within-segment ( near or intrasegment )

CALL MULTO

;MULTO is the name of the procedure. The assembler determines displacement of MULTO from the instruction instruction after the CALL and codes this displacement in as part of the instruction .

Indirect within-segment ( near or intrasegment )

CALL BX

; BX contains the offset of the first instruction of the procedure .Replaces contents of word of IP with contents o register BX.

CALL WORD PTR[BX] ;Offset of first instruction of procedure is in two memory addresses in DS .Replaces contents of IP with contents of word memory location in DS pointed to by BX. Direct to another segment- far or intersegment.

CALL SMART

;SMART is the name of the Procedure

SMART PROC FAR ; Procedure must be declare as an far CBW Instruction - CBW converts the signed value in the AL register into an equivalent

16 bit signed value in the AX register by duplicating the sign bit to the left. This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be the sign extension of AL. Example:

; AX = 00000000 10011011 = - 155 decimal CBW

; Convert signed byte in AL to signed word in AX. ; Result in in AX = 11111111 10011011 = - 155 decimal

Chapter 3 : Intel 8086 CLC Instruction - CLC clear the carry flag ( CF ) to 0 This instruction has no affect on

the processor, registers, or other flags. It is often used to clear the CF before returning from a procedure to indicate a successful termination. It is also use to clear the CF during rotate operation involving the CF such as ADC, RCL, RCR . Example: CLC CLC

;Cle ;Clear ar carr carry y flag flag..

CLD Instruction - This instruction reset the designation flag to zero. This instruction has

o effect on the registers or other flags. When the direction flag is cleared / reset SI and DI will automatically be incremented when one of the string instruction such as MOVS, CMPS, SCAS,MOVSB and STOSB executes. Example : CLD

;Clear ;Clear directio direction n flag so that that string string pointer pointerss auto increm increment ent

CLI Instruction - This instruction resets the interrupt flag to zero. No other flags are

affected. If the interrupt flag is reset , the 8086 will not respond to an interrupt signal on its INTR input. This CLI instruction has no effect on the non maskable interrupt i/p ,NMI CMC Instruction - If the carry flag CF is a zero before this instruction, it will be set to a

one after the instruction. If the carry flag is one before this instruction, it will be reset to a zero after the instruction executes. CMC has no effect on other flags. Example: CMC

; Invert the carry flag.

CWD Instruction - CWD converts the 16 bit signed value in the AX register into an

equivalent 32 bit signed value in DX: AX register pair by duplicating the sign bit to the left. The CWD instruction sets all the bits in the DX register to the same sign bit of the AX register. register. The effect effect is to create a 32- bit signed result that has same integer integer value as the original 16 bit operand. Example:

Assume AX contains C435h. If the CWD instruction is executed, DX will contain FFFFh since bit 15 (MSB) of AX was 1. Both the original value of AX (C435h) and resulting value of DX : AX (FFFFC435h) represents the same signed number. Example:


;DX = 00000000 00000000 AX = 11110000 11000111 = - 3897 decimal CWD

;Convert signed word in AX to signed double word in DX:AX Result DX = 11111111 11111111 AX = 11110000 11000111 = -3897 decimal . 

DAA Instruction - Decimal Adjust Accumulator



S ubtraction DAS Instruction - Decimal Adjust after Subtraction



DEC Instruction - Decrement destination register or memory DEC

destination. 

DIV Instruction - Unsigned divide-Div source



ESC Instruction

When a double word is divided by a word, the most significant word of the double word must be in DX and the least significant word of the double word must be in AX. After the division AX will contain the 16 –bit result (quotient ) and DX will contain a 16 bit remainder. Again , if an attempt is made to divide by zero or quotient is too large to fit in AX ( greater than FFFFH ) the 8086 will do a type of 0 interrupt . Example: DIV CX

; (Quotient) AX= (DX:AX)/CX (Reminder) X=(DX:AX)%CX

For DIV the dividend must always be in AX or DX and AX, but the source of the divisor can be a register or a memory location specified by one of the 24 addressing modes. If you want to divide a byte by a byte, you must first put the dividend byte in AL and fill AH with all 0’s . The SUB AH,AH instruction is a quick way to do. If you want to divide a word by a word, put the dividend word in AX and fill DX with all 0’s. The SUB DX,DX instruction does this quickly. Example:

; AX = 37D7H = 14, 295 decimal BH = 97H = 151 decimal DIV BH ;AX / BH

; AX = Quotient Quotient = 5EH = 94 decima decimall AH = Remainder Remainder = 65H = 101 decimal

3.15 Procedure and Macros of 8086 3.15.1 Procedure:

Named group of statement which is performed particular task is called procedure.


Procedure or subroutine may require input data or constants for their execution. Their data or constants may be passed to the subroutine by main program or some subroutine may access readily available data of constants available in memory. Generally , the following technique are used to pass input / parameter to procedures in ALP a)

Using Gl Global declared va variable

b)

Using re registers of of CP CPU ar architecture ure

c)

Using me memory location

d)

Using stack

e)

Using PUBLIC and EXTERN

3.15.1.1 Using Global declared variable

A variable or a parameter label may be declared global in the main program and the same variable or parameter label can be used by all the procedures of the application. Examples of passing parameters ASSUME CS : CODE,DS : DATA DATA SEGMENT NUMBER EQY 77H GLOBAL DATA ENDS CODE1 SEGMENT START :

MOV AX AX,DATA MOV DS,AX -

-

-

-

CODE1 ENDS ASSUME CS : CODE2 CODE2 SEGMENT START :

MOV AX AX,DATA MOV DS,AX

CODE2 ENDS

-

-

-

-


END START

3.15.1.2 Using registers of CPU architecture

Thee CPU Th CPU gene genera rall purpos purposee regi regist ster erss may may be used used to pass pass param paramet eter erss to the the procedures. The main program may store the parameters to be passed to the procedure in the variable CPU registers and the procedure may use the same register content for execution. The original content of the used CPU register may change during execution of the procedure. This may be avoided by pushing all the register content to be used to the stack sequentially at the start of the procedure and poping all the register contents at the end of the procedure in opposite sequence. ASSUME CS : CODE,DS : DATA CODE SEGMENT START :

MOV AX A X , 5555H MOV BX , 5456H -

-

-

-

PROCEDURE P1 NEAR -

-

-

-

ADD AX , BX -

-

-

-

RET P1 ENDP CODE ENDS END START 3.15.1.3 Using memory location

Memory location may also be used to pass parameter to a procedure in the same way as registers. A main program may store the parameter to be passed to a procedure at known known memory memory addres addresss locatio location n and the procedur proceduree may use the same same locatio location n for accessing the parameter.


Example: ASSUME CS : CODE,DS : DATA DATA SEGMENT NUM DB (55H) COUNT EQY 77H DATA ENDS CODE SEGMENT START :


-

-

-

CALL ROUTINE -

-

-

-

PROCEDURE ROUTINE NEAR MOV BX , NUM MOV CX , COUNT -

-

ROUTINE ENDP CODE ENDS END START 3.15.1.4 Using stack

Stack memory can also be used to pass parameters parameters to procedure. A main program may store the parameters to be passed to a procedure in its CPU registers . The registers will further further be pushed on to the stack. The procedure during during its execution execution pops back the appro appropr pria iate te para parame mete ters rs as and and when when requi require red. d. Th This is proc procedu edure re of pop popin ing g back back the the parameters must be implemented carefully because besides the parameters to be passed to the proced procedure ure the stack stack contai contains ns other other import important ant inform informati ation on like like content contentss of other other pushed registers, return addresses from the current procedure and other procedure or interrupt service routines. Example :


ASSUME CS : CODE,SS : STACK STACK SEGMENT STACKDATA DB 200H DUP ( ? ) STACK ENDS CODE SEGMENT START :

MOV AX A X , STACK MOV SS,AX MOV BX , 55H MOV CX , 10H -

-

PUSH AX PUSH CX CALL ROUTINE -

-

-

-

PROCEDURE ROUTINE NEAR -

-

MOV DX , SP ADD SP ,02H POP CX POP BX MOV SP , DX -

-

ROUTINE ENDP CODE ENDS END START 3.15.1.5 Using PUBLIC and EXTERN

For passing passing the paramet parameters ers to procedure proceduress using

the PUBLIC PUBLIC & EXTERN EXTERN

directives , must be declared PUBLIC (for all routine) routine) in the main routine and the same should be declared EXTERN in the procedure Thus the main program can pass the PUBLIC parameter to a procedure in which it is declared EXTERN(external)


Example: ASSUME CS : CODE,DS : DATA DATA SEGMENT PUBLIC NUMBER EQY 77H DATA ENDS CODE SEGMENT START :


-

-

-

CALL ROUTINE -

-

PROCEDURE ROUTINE NEAR EXTERN NUMBER MOV AX , NUMBER -

-

ROUTINE ENDP CODE ENDS END START 3.15.2 MACROS

The macro is also similar to subroutine. Suppose , a number of instructions are repeat repeating ing through through in the main program program , the listin listing g

become becomess length lengthy. y. So a macro macro

definition i. e. a label , is assigned with in the repeatedly appearing string of instructions. The process of assignin assigning g a label or macro name to the string string is called macro. macro. A macro within within the macro is called nested nested macro. The macro name or macro definiti definition on is then used throughout the main program to refer to the string of instructions. Thee diff Th differ erenc encee betwe between en a macr macro o and a subr subrout outin inee is that that in the the macr macro o the the complete code of the instructions string is inserted inserted at each place where the macro name appears. Hence the EXE file becomes lengthy. Macro does not utilize the service of stack. There is no question of transfer of control as the program using the macro inserts the complete code of the macro at every reference of the macro name.


On the other hand , subroutine is called whenever necessary, i.e. the control of execution is transferred to the subroutine , every time it is called . The executable code in case of the subroutines becomes smaller as the subroutine appears only once in the complete code. Thus , the EXE file is smaller as compared to the program using macro .The control is transferred to the subroutine whenever it is called , and this utilize the stack service .The program using subroutine requires less memory space for execution than the using the macro. Macro requires less time for execution , as it does not contain CALL and RET instructions as the subroutine do

3.15.2.1 Defining a MACRO

A MACRO can be defined anywhere in the program using the directives MACRO and ENDM. The label prior to MACRO is the macro name which should be used in the actual program. The ENDM directive mark the end of the instructions .The following macro DISP displays the message MSG on the CRT. The syntax is as given: DISP MACRO MOV AX , SEG MSG MSG MOV DS , AX MOV DX , OFFSET MSG MOVE AH , 09H INT 21H ENDM The above definition of macro assign the name DISP to the instruction sequence between the directives MACRO and ENDM. While assembling , the above sequence of the instructions will replace the label ‘DISP’, whenever it appear in the program. A macro may be called by quoting its name, along with any value to be passed to the macro. Calling a macro means inserting the statements and instructions represented by the macro directly at the place of the macro name in the program. 3.15.2.2 Passing Parameters to a MACRO

Using parameters in a definition , the programmer specifies the parameters of the macro those are likely to be changed each time the macro is called. For example the DISP


macro written above can be made to display two different messages MSG1 and MSG2 as shown DISP MACRO MOV AX , SEG MSG MSG MOV DS , AX MOV DX , OFFSET MSG MOVE AH , 09H INT 21H ENDM This parameter MSG can be replaced by MSG1 and MSG2 while calling the macro as shown. ASSUME CS : CODE,DS : DATA CODE SEGMENT START :

MOV AX AX,DATA -

-

DISP MSG1 -

-

DISP MSG2 -

-

CODE ENDS END START MSG1 DB OAH,ODH ,”PROGRAM TERMINATED NORMALLY” MSG1 DB OAH,ODH ,”Retry ,Abort , Fail”

3.16 Assembler Directives And Operators

The main main advant advantage age of machin machinee languag languagee progra programmi mming ng is that that the memory memory control is directly in the hands of the programmer enabling him to manage the memory of the system system more efficiently. However, there are more disadvantages. The programming, programming, coding and resource resource management management techniques techniques are tedious. tedious. As the programs programs one has to have a thorough technical knowledge of the processor architecture and instruction set.


The assembly language programming is simpler as compared to the machine programming. The instruction mnemonics mnemonics are directly written in the assembly language language progr program ams. s.

Thee prog Th progra rams ms are are now now more more read readabl ablee than than that that of mach machin inee lang langua uage ge

programs. The advantage that assembly assembly language has over machine language in that now the address address values and the constants constants can be identified identified by labels. If the labels are clear clear then then certa certain inly ly the the prog progra ram m will will beco become me more more und under erst stand andab able le,, and and each each time time the the programmer will not have to remember the different constants and the addresses at which they are stored, throughout throughout the programs. Due to this facility, the tedious tedious byte handling and manipulations are got rid of. Similarly, now different different logical segments and routines routines may be assigned with the labels rather rather than the different addresses. The memory control of machin machinee languag languagee progra programmi mming ng is left left unchang unchanged ed by provid providing ing storag storagee define define facilities in assembly language programming. programming. The documentation facility facility which was not possible with machine language programming is now available in assembly language. Readers will get a better glimpse of the different features of assembly language, when we discuss assembly programming in the next chapter. An assembler is a program used to convert an assembly language program into the equivalent machine code modules which may further be converted to executable codes. codes. It decides decides the address address of each label and substitu substitutes tes the vales for each of the constants constants and variables. variables. It then forms the machine machine code for the mnemonics mnemonics and data in the assembly assembly language language program. While While doing these things, things, the assembler assembler may find out syntax syntax errors. The logical logical errors or other programmi programming ng errors are not found out by the assembler. For completing all these tasks, an assembler needs some hints from the programmer programmer,, i.e. the required required storage for a particular particular constant constant or a variable, logical logical names of the segments, types of the different routines and modules, end of file, etc. These types of hints are given to the assembler using some predefined alphabetical strings called assembler directives, which help the assembler to correctly understand the assembly language programs to prepare the codes. Another type of hint which helps the assembler to assign a particular constant with with a label label or initia initializ lizee parti particula cularr memory memory location locationss or labels labels with constan constants ts is an operator. In fact, the operators perform perform the arithmetic and logical tasks unlike directives that just direct the assembler assembler to correctly correctly interpret interpret the program program to code it appropriately. appropriately.


The following directives are commonly used in the assembly language programming practice practice using Microsoft Microsoft Macro Assembler Assembler or Turbo Assembler. Assembler. The directives directives and operators are discussed here but their meanings and uses will be more clear in Chapter 3 on assembly language programming techniques. 3.16.1 DB: Define Byte

The DB directive is used to reserve byte or bytes of memory locations in the available available memory. While While preparing the EXE file, this directs the assembler assembler to allocate allocate the specified number of memory bytes to the said data type that may be a constant, variable, string, etc. Another option of this directive also initializes the reserved memory bytes bytes with the ASCII codes codes of the charact characters ers specifi specified ed as a string string..

The followi following ng

examples show how the DB directive is used for different purposes.

Example RANKS

DB 01H, 02H,

03H, 04 04H

This statement directs the assembler to reserve four memory locations for a list named RANKS and initialize them with the above specified four values. MESSAGE DB ‘GOOD MORNING’

This makes the assembler reserve the number of bytes of memory equal to the number of characters in the string named MESSAGE and initialize those locations by the ASCII equivalent of these characters. VALUE DB 50H

This statement direct the assembler to reserve 50H memory bytes and leave them un initialized for the variable named VALUE

3.16.2 DW: Define Word

The DW directive serves the same purposes as the DB directive, but it now makes the assembler reserve the number of memory words (16- bit) instead of bytes. Some examples are given to explain this directive. directive.

Example WORDS

DW 1234H, 4567H, 78BH, 045CH,


This makes the assembler reserve four words in memory (8 bytes), and initialize the words with the specified values in the statements. During initialization, initialization, the lower bytes are stored at the lower memory addresses, while the upper bytes are stored at the higher addresses. Another option of the DW directive is explained with the the DUP operator. WDATA

DW 5 DUP (6666H)

This statement reserves five words,i.e.10 – bytes of memory for a word lable WDATA and initializes all the word locations with 6666H.

3.16.3 DQ : Define Quad word

This directive is used to direct the assembler to reserve 4 words (8 bytes) of memory for the specified specified variable and may initialize initialize it with the specified specified values. 3.16.4 DT: Define Ten Bytes

This DT directive directs the assembler to define the specified variable requiring 10- bytes bytes for its storag storagee and initial initialize ize the 10 – bytes bytes with the specifie specified d values values.. The directive may be used in case of variables facing heavy numerical calculations, generally processed by numerical processors. 3.16.5 ASSUME: Assume logical Segment Name

The ASSUME directive is used to inform inform the assembler, the names of the logical segments segments to be assumed for differen differentt segments used used in the program. program. In the assembly assembly language language program, each segment segment is given a name. For example, example, the code segment may be given given the name CODE, CODE, data segme segment nt may be give given n the the name name DATA DATA etc. etc. statem statement ent ASSUME ASSUME

CS: CODE CODE

Thee Th

direct directss the assemb assembler ler that that the machin machinee codes are are

available in a segment named CODE, and hence the CS register is to be loaded with the address (segment) allotted by the operating system for the label CODE, while loading, Similarly, 3.16.6 ASSUME DS: DATA

It indica indicates tes to the assem assemble blerr that that the data data items items relate related d to the program, program, are available in a logical segment named DATA, and the DS register is to be initialized by the segment address value decided by the operating system for the data segment, while loadin loading. g.

It then then conside considers rs the the segment segment DATA DATA as a default default data data segment segment for each each


memory operation, related to the data and the segment CODE as a source segment for the machine codes of the program. The ASSUME statement statement is a must at the staring of each assemb assembly ly languag languagee progra program, m, withou withoutt which which a messag messagee ‘CODE/ ‘CODE/DAT DATA A EMITTE EMITTED D WITHOUT SEGMNT’ may be issued by an assembler. 3.16.7 END: END of Program

The END directive directive marks the the end of an assembly language language program. program. When the assembler comes across this END directive, it ignores the source lines available later on. Hence, it should be ensured that the END statement should be the last statement in the file and should not appear appear in between. Also, Also, no useful program statemen statementt should lie in the file, after the END statement. 3.16.8 ENDP: END of Procedure

In assembly assembly language programming, programming, the subroutines are called called procedures. They may be independent program modules which return particular results or values to the calling calling programs. programs. The ENDP ENDP directive directive is is used to to indicate indicate the end end of a procedure procedure.. A proced procedure ure is usual usually ly

assign assigned ed a name, i.e. i.e. label. label. To mark mark the end of a partic particula ular r

procedure, the name of the procedure, i.e. label may appear as a prefix prefix with the directive directive ENDP. The statements, appearing in in the same module but after the ENDP directive, directive, are neglected from that procedure. The structure given below explains the the use of ENDP. PROCEDURE STAR : STAR ENDP

3.16.9 ENDS : END of Segment

This This direct directive ive marks marks the end of a logica logicall segmen segment. t. The logical logical segment segmentss are assigned assigned with with the names using the ASSUME directive. directive.

The names names appear with the

ENDS directive as prefixes to mark the end of those those particular segments. Whatever are the contents contents of the segments, segments, they should should appear in the program program before ENDS. ENDS. Any statem statement ent appear appearing ing after after ENDS ENDS will will be neglec neglected ted from the segmen segment. t. The structu structure re shown below explains the fact more clearly. DATA

SEGMENT :

DATA

ENDS

ASSUME

CS: CODE, DS : DATA

CO DE

SEGMENT :

CO DE END

ENDS


The above structure represents a simple program containing two segments named DATA DATA and CODE. CODE.

Thee data Th data relat related ed to the the progr program am must lie betwe between en the DATA DATA

SEGMENT SEGMENT and DATA ENDS statement statements. s. Similarly Similarly,, all all the the executa executable ble instruction instructionss must lie between CODE SEGMENT and CODE ENDS statements. 3.16.10 EVEN : Align on EVEN Memory Address

Thee asse Th assemb mble ler, r, whil whilee star starti ting ng the the asse assemb mbli ling ng proce procedu dure re of any any prog progra ram, m, initializes initializes a location location counter and goes on updating updating it, as the assembly assembly proceeds. It goes on assigning the available addresses, i.e. the contents of the location counter, sequentially to the progra program m variab variables les,, constan constants ts and module moduless as per their their requir requireme ements nts,, in the sequence in which they appear in the program. The EVEN directive updates the location counter to the next even address, if the current location counter contents are not even, and assigns the following routine routine or variable or constant to that that address. The structure given below explains the directive. EVEN PROCEDURE ROOT The above structure shows a procedure ROOT that is :to be aligned at an even address. The assembl assembler er will start start assemb ass emblin ling g the main program prog ram callin calling g ROOT. ROOT. When When the ROOT ENDP assemb assembler ler comes comes across across the direct directive ive EVEN, EVEN, it checks checks the conten contents ts of the locati location on

counter. If it is odd, it is updated to the next even value and then the ROOT procedure is assigned to that that address, i.e. the updated contents of the location counter. If the content of the location counter is already even, then the ROOT procedure will be assigned with the same address. 3.16.11 EQU : Equate

The directive EQU is used to assign a label with a value or a symbol. symbol. The use of this directive is just to reduce the recurrence of the numerical values or constants in a program code. The recurring value is assigned assigned with a label, and that label is is used in place


of

that numeri numerical cal value, value, throughout throughout the program. program. While assembling assembling,, whenever whenever the

assembler assembler comes across across the label, it substitut substitutes es the numerical numerical value for that label and finds out the equivalent equivalent code. Using the EQU directive, directive, even an instructi instruction on mnemonic can be assigned assigned with a label, which which can then be used in the program program in place of that mnemonic. Suppose, a numerical constant which appears in a program ten times. If that constant is to be changed at a later time, one will have to make the correction 10 times. This may lead to human errors, because it is possible that a human programmer may miss one of those corrections. This will result in the generation of wrong codes. If the EQU directive is used to assign the value with a label that can be used in place of each recurrence of that constant, only one change in the EQU statement will give the correct and modified code. The examples given below show the syntax. syntax.

Example LABEL

EQU

0500H

ADDITION

EQU

ADD

The first statement assigns the constant 500H with the label LABEL, while the second statement assigns another label ADDITION with mnemonic ADD.

3.16.12 EXTRN: External and PUBLIC : Public

The directive directive EXTRN informs informs the assembler assembler that the names, names, procedures procedures and labels declared after this directive have already been defined in some other assembly language modules. While in in the other module, where the names, procedures and labels actually appear, they must be declared public, using the PUBLI directive. If one wants to call call a proc proced edur uree

FACT FACTOR ORIA IAL L appe appear arin ing g in MODULE MODULE 1 from from MODULE MODULE 2; in

MODULE 1, it must be declared PUBLIC using the statement PUBLIC FACTORIAL and and in modu module le 2, it must must be decl declar ared ed exte extern rnal al usin using g the the decl declar arat atio ion n EXTR EXTRN N FACTORI FACTORIAL. AL.

The stateme statement nt of declar declarati ation on EXTRN must be accomp accompani anied ed by the

SEGMENT and ENDS ENDS directives of the MODULE 1, before it it is called in MOBULE 2. Thus the MODULE 1 and MODULE 2 must have the following declarations. MODULE 1 PUBLIC MODULE 1

SEGMENT FACTORIAL FAR ENDS

MODULE 2 EXTRN MODULE 2



3.16.13 GROUP :Group the Related Segments

This directive is used to form logical groups of segments with similar purpose or type. type. This This directi directive ve is used used to inform inform the assemb assembler ler to form a logica logicall group group of the following segment names. The assembler passes an information information to the linker / loader loader to form the code such that the group declared segments or operands must lie within a 64kbyte memory segment. Thus all such segments and labels can be addressed using the same segment base. PROGRAM GROUP CODE, DATA, STACK The above statement directs the loader / linker to prepare an EXE file such that

CODE, DATA and STACK segment segment must lie within a 64kbyte memory segment that that is named named as PROGRA PROGRAM. M.

Now, Now, for the ASSU ASSUME ME state stateme ment nt,, one one can can use use the the labe labell

PROGRAM rather than CODE, DATA and STACK as shown. ASSUME CS : PROGRAM, PROGRAM, DS : PROGRAM, SS: PROGRAM PROGRAM

3.16.14 LABEL : Label

The Label directive is used to assign a name to the current of the location counter. When the assembly process starts, the assembler initializes a location counter to keep track of memory memory locations locations assigned assigned to the program. As the program assembly assembly proceeds, the contents of the location counter are updated. During the assembly process, whenever the assembler comes across the LABEL directive, it assigns the declared label with the current contents of the location location counter. The type of the label must be specified, specified, i.e. whether it is a NEAR or o r a FAR label, BYTE or WORD label, etc. A LABEL directiv directivee may be used to make a FAR jump jump as shown below. below. A FAR jump cannot be made at a normal normal label with a colon. The label CONTINUE can be used for a FAR jump, if the program contains the following following statement. CONTINUE LABEL FAR


The LABEL directive can be used to refer to the data segment along with the data type, byte or word as shown. DATA SEGMENT DATAS DB 50H DUP (?) DATA – LAST LABEL BYTE FAR DATA ENDS

After reserving 50H locations for DATAS, the next location will be assigned a label DATA – LAST and its type will be byte and far. 3.16.15 LENGTH : Byte Length of a Label

This directive is not available in MASM. This is used to refer refer to the length of a data array or a string. MOV CX, LENGTH ARRAY

This statement, when assembled, will substitute the length of the array ARRAY in bytes, in the instruction. 3.16.16 LOCAL

The labels, variables, constants or procedures declared LOCAL in a module are to be used only by that particular module. module. After some time, some other module may declare a particular data type LOCAL, which was previously declared LOCAL by an other module or modules. modules. Thus the same same label may serve differe different nt purposes purposes for different different modules of a program. With a single declaration statement, a number of variables variables can be declared local, as shown. LOCAL a, b, DATA, ARRAY, ROUTINE

3.16.17 NAME : Logical Name of a Module

The NAME directive is used to assign a name to an assembly language program module module.. The modul module, e, may now now be referre referred d to by its decla declared red name. name. The names names,, if selected to be suggestive, may point out the functions of the different modules and hence may help in the documentation. 3.16.18 OFFSET : Offset of a Label


When the assembler comes across the OFFSET operator along with a label, it first first computes the 16 – bit displacemen displacementt (also called as offset interchang interchangeably eably ) of the par parti ticu cula larr labe label, l, and and repl replac aces es the the stri string ng ‘ORR ‘ORRSE SET T LABE LABEL’ L’ by the the comp comput uted ed displacement. This operator is used with arrays, arrays, strings, strings, labels and procedures to to decide their offsets offsets in their their default default segments. segments. The segment segment may also be decided by another another operator operator of similar similar type, viz, SEG. Its most common common use is in the case of the indirect, indirect, indexed, or other addressing techniques of similar types, used to refer to the memory indirectly. The examples of thus operator are as follows.

Example CODE SEGMENT MOV SI, OFFSET LIST CODE ENDS DATA SEGMENT LIST DB 10H DATA ENDS

3.16.19 ORG: Origin

The ORG directive the assembler to start start the memory allotment allotment for the particular segment, segment, block or code from the declared address in the ORG statement. statement. While While stating the assembly assembly process process for a module, the assembler assembler initializes initializes a location counter counter to keep track of the allotted addresses for the module. module. If the ORG statement is not written written in the program, the location counter is initialized to 0000. If an ORG statement is present at the the starting of the code segment of that module, then the code will start from 200H address in code segment. segment. In other words, the location location counter will get in initialize initialized d to the address 0200H instead instead of 0000H. Thus, the the code for different different modules modules and segments segments can be located in the available memory memory as required required by the programmer. The ORG directive directive can even be used with data segments similarly. 3.16.20 PROC: Procedure

The PROC directive marks the start of a named procedure in the statement. Also, the types NEAR of FAR specify the the type of the procedure, i.e. i.e. whether it is to to be


called by the main program located located within 64K of physical memory memory or not. For example, the statement RESULT PROC NEAR marks the start of a routine RESULT, which is to be called by a program located located in the same segment of memory. memory. The FAR directive directive is used for the procedures to be called by the programs located in different segments of memory. The example statements statements are as follows:

Example RESULT

PROC

NEAR

ROUTINE

PROC

FAR

3.16.21 PTR : Pointer

The POINTER operator is used to declare the type of a label, variable or memory operand. The operator PTR is prefixed by either BYTE or WORD. If the prefix prefix is BYTE, then the particular label, variable or memory operand is treated as an 8 – bit quantity, while if WORD is the the prefix, then it is treated as a 16 – bit quantity. In other words, the PTR operator is used to specify specify the data type – byte or word. The examples of the PTR operator are as follows:

Example

MOV AL, BY BYTE PT PTR [SI]

-

Moves content of memory location

addressed by SI ( 8 –bit ) to AL INC BYTE PTR [BX]

-

Increments byte contents of memory location addressed by BX

MOV BX, WORD PTR [2000H] -

Move 16 –bit content of memory location 200H to BX, i.e. [2000H] to BL [2001H] to BH

INC WO WORD PTR [3 [300h]

-

Increments word contents of memory location 3000H considering contents of


of 3000H (lower byte) and 3001H (higher byte ) as a. 16 –bit number

In case of JMP instructions, the PTR operator is used to specify the type of the jump, i.e. near of far, as explained in the examples given below. JMP

NEAR PTR [BX] – NEAR jump

JMP

FAR

PTR [BX] – FAR jump

3.16.22 PUBLIC

As already discussed, the PUBLIC directive is used along with the EXTRN directive. This informs the the assembler that the the labels, variables, constants, constants, or procedures declared PUBLIC may be assessed assessed by other assembly modules to form their their codes, but while using the PUBLIC declared labels, variables m constants or procedures the user must declare them externals using the the EXTRN directive. On the other other hand, the data types types declare declared d EXTRN EXTRN in module module of the progra program, m, may be declared PUBLIC in at least any one of the other modules of the same program. (Refer to the explanation on EXTRN directive to get the clear idea of PUBLIC) 3.16.23 SEG: Segment of Label

The SEG operator is used to decide the segment address of the label, label, variable, or proced procedure ure and substitu substitutes tes the segment segment base address address in place of “SEG” “SEG” label. label.

The

example given below explains the use of SEG operator.

Example

MOV MOV

AX, AX, SEG SEG

ARRA ARRAY Y

; Th This is stat statem emen entt move movess the the segm segmen entt addr addres esss of ARRAY in

MOV

DS , A X

; Which it is appearing, to register AX and then to DS.

3.16.24 SEGMENT : Logical Segment

The SEGMENT directive marks the starting starting of a logical segment. The started is also assigned assigned a name, i.e. label, by this statement. The SEGMENT and ENDS directive


must bracket bracket each logical logical segment of a program. program. In some cases, cases, the segment segment may be assigned a type like PUBLIC (i.e. can be used by other modules of the program while linking) linking) or GLOBAL GLOBAL (can be accessed accessed by any other other modules). modules).

The program program structure structure

given below explains the use of the SEBMENT directive. EXE. CODE SEGMENT GLOBAL

; Start of segment named EXE. EXE. CODE that can be accessed by any other module.

MOV

; END of EXE. CODE logical segment

DS, AX

3.16.25 SHORT

The SHORT operator indicates to the assembler that only one byte byte is required to code the displacement for a jump (i.e. displacement is within – 128 to + 127 bytes from the address address of the byte next to the jump opcode). This method method of specifying specifying the jump address address saves the memory. memory. Otherwise, Otherwise, the assembler assembler may reserve reserve two bytes for the displacement. The syntax of the statement is is as given below. below. JMP SHORT LABEL 3.16.26 TYPE

The TYPE operator directs the assembler to decide the data type of the specified label and replaces the ‘TYPE’ label by the decided data type. type. For the word type variable, the data type type is 2, for double double word type, type, it is 4, 4, and for byte byte type, it is is 1. Suppose, Suppose, the STRING is a word array. The instruction instruction MOV AX, TYPE STRING moves the value 0002H in AX. 3.16.27 GLOBAL

The labels, variables constants or procedures declared GLOBAL may be used by other modules modules of the program. program. Once a variable variable is declared declared GLOBAL, it can be used by any module in the program. program. The following statement statement declares the procedure ROUTINE as a global label. ROUTINE

PROC GLOBAL

‘ + & -’ Operators Operators

These operators operators represent represent arithmeti arithmeticc addition addition and subtractio subtraction n

respectively and are typically used to add or subtract displacements (8 or 16 bit) to base or index registers or stack or base pointers p ointers as given in the example:

Chapter 3 : Intel 8086 Example MOV AL, [ SI + 2] MOV DX, [ BX - 5] MOV BX, [ OFFSET LABEL + 10H ] MOV AX, [ BX + 9I ]

3.16.28 FAR PTR

This directive directive indicates indicates the assembler assembler that the label followin following g FAR PTR is not available within the same segment and the address of the label is of 32 – bits i.e. 2 bytes offset followed by 2 bytes segment address.

Example JMP

FAR

PTR

CALL FAR PTR

LABEL ROUTINE

Both the above instructions indicate to the assembles that the target address is going to require four bytes; Lower byte of offset, higher byte of offset, lower byte of segment and higher byte byte of segment; indicating inter segment addressing addressing mode. 3.16.29 NEAR PTR

This This direct directive ive indica indicates tes that that the label follow following ing NEAR NEAR PTR is in the same same segment and needs only 16 bit i.e. 2 byte offset to address it.

Example

JMP NEAR PTR

LABEL

CALL NEAR PTR ROUTINE

If a label is not preceded by NEAR PTR or FAR PTR, then it is by default considered a NEAR PTR label and two bytes are reserved by the assembler for its address during the process of assembling.


3.18 Coprocessor 8087 3.18.1 Overview 

Each processor in the 80x86 family has a corresponding coprocessor with which it is compatible.



Math Coprocessor is known as NPX,NDP,FUP.



Numeric processor extension (NPX),



Numeric data processor (NDP),



Floating point unit (FUP).

3.18.2 Compatible Processor and Coprocessor Processors

1. 8086 & 8088 2. 80286 3. 80386DX 4. 80386SX 5. 80486DX 6. 80486SX Coprocessors

1. 8087 2. 80287,80287XL 3. 80287,80387DX 4. 80387SX 5. It is Inbuilt 6. 80487SX


Figure 17 : Pin Diagram of 8087 3.18.3 Architecture of 8087

1. Control Uni Unitt 2. Ex Exec ecut utio ion n Uni Unitt 3.18.3.1 Control Unit

Control unit: To synchronize the operation of the coprocessor and the processor. This unit has a Cont Contro roll word word and and Stat Status us word word and and Data Data Buff Buffer er If inst instru ruct ctio ion n is an ESC ape ape (coprocessor) instruction, the coprocessor executes it, if not the microprocessor executes. Status register reflects the over all operation of the coprocessor.


Figure 18 : Architecture of 8087

Chapter 3 : Intel 8086 3.18.3.2 Status Register

Figure 19 : status Register

C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit B-Busy bit indicates that coprocessor is busy executing a task. Busy can be tested by

exam examin inin ing g the the stat status us or by usin using g the the FWAI FWAIT T inst instru ruct ctio ion. n. Newe Newerr copr coproc oces esso sor r automatically synchronize with the microprocessor, so busy flag need not be tested before performing additional coprocessor tasks. C3-C0 Condition code bits indicates conditions about the coprocessor. TOP- Top of the stack (ST) bit indicates the current register address as the top of the

stack. ES-Error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is set.

In the 8087 the error summary is also caused a coprocessor interrupt. PE- Precision error indicates that the result or operand ex ecutes selected precision. UE-Under flow error indicates the result is too large to be represent with the current

precision selected by the control word. OE-Over flow error indicates a result that is too large to be represented. If this error is

masked, the coprocessor generates infinity for an overflow error.

Chapter 3 : Intel 8086 ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or

non-zero number. DE-Denormalized error indicates at least one of the operand is denormalized. IE-Invalid error indicates a stack overflow or underflow, indeterminate from (0/0,0,-0,

etc) or the use of a NAN as an operand. This flag indicates error such as those produced by taking the square root of a negative number. 3.18.3.3 Control Register

Control register selects precision, rounding control, infinity control. It also masks an unmasks the exception bits that correspond to the rightmost Six bits of status register. Instruction FLDCW is used to load the value v alue into the control register.

Figure 20: Control Register IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask

IC –Infinity control selects either affine or projective infinity. Affine allows positive and negative infinity, while projective assumes infinity is unsigned. INFINITY CONTROL

0 = Projective 1 = Affine

Chapter 3 : Intel 8086 RC –Rounding control determines the type of rounding. ROUNDING CONTROL

00=Round to nearest or even 01=Round down towards minus infinity 10=Round up towards plus infinity 11=Chop or truncate towards zero PC- Precision control sets the precision of he result as define in table PRECISION CONTROL

00=Single precision (short) 01=Reserved 10=Double precision (long) 11=Extended precision (temporary) 3.18.3.4 Exception Masks – It Determines whether the error indicated by the exception

affects the error bit in the status register. If a logic1 is placed in one of the exception control bits, corresponding status register bit is masked off. 3.18.3.5 Numeric Execution Unit

This Th is perf perfor orms ms all all oper operat atio ions ns that that acce access ss and and mani manipul pulat atee the the nume numeri ricc data data in the the coprocessor’s registers. Numeric registers in NUE are 80 bits wide. NUE is able to perfor perform m arithm arithmeti etic, c, logica logicall and transc transcend endent ental al operat operation ionss as well well as supply supply a small small number of mathematical constants from its on-chip ROM. Numeric data is routed into two parts ways a 64 bit mantissa bus and a 16 bit sign/exponent bus. Multiplexed address-data bus lines are connected directly from the 8086 to 8087. The status status lines lines and the queue status status lines connecte connected d direct directly ly from from 8086 to 8087. 8087. The Request/Grant signal RQ/GT0 of 8087 is connected to RQ/GT1 of 8086. BUSY signal 8087 is connected connected to TEST pin of 8086. Interrupt Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition. The main purpose of the circuitry between the INT output of 8087 and the NMI input is to make sure that an NMI signal is not present upon reset, to make it possible to mask NMI input and to make it possible for other devices to cause an NMI interrupt. BHE pin is connected to the system BHE line to Multiplexe Multiplexed d address-data address-data bus lines are connected connected directly directly from the 8086 to 8087. The status lines and the queue status lines connected con nected directly from 8086 to 8087.


The Request/Grant signal RQ/GT0 of 8087 is connected to RQ/GT1 of 8086. BUSY signal 8087 is connected connected to TEST pin of 8086. Interrupt Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition. The main purpose of the circuitry between the INT output of 8087 and the NMI input is to make sure that an NMI signal is not present upon reset, to make it possible to mask NMI input and to make it possible for other devices to cause an NMI interrupt. BHE pin is connected to the system BHE line to enable the upper bank of memory. The RQ/GT1 input is available so that another coprocessor such as 8089 I/O processor can be connected and function in parallel with the 8087. One type of Cooperati Cooperation on between the two processor processorss that you need to know about it is how the 8087 transfers data between memory and its internal registers. When 8086 reads an 8087 instruction that needs data from memory or wants to send data to memory, the 8086 sends out the memory address code in the instruction and sends out the appropriate memory read or memory write signal to transfer a word of data. In the case of memory read, the addressed word will be kept on the data bus by the memory. The 8087 then simply reads the word of data bus. The 8086 ignores this word .If the 8087 only needs this one word of data, it can then go on and executes its instruction. Some 8087 instructions need to read in or write out up to 80-bit word. For these cases 8086 outputs the address of the first data word on the address bus and outputs the appropriate control signal.


The 8087 reads the data word on the data bus by memory or writes a data word to memory on the data bus. The 8087 grabs the 20-bit physical address that was output by the 8086.To transfer additional words it needs to/from memory, the 8087 then takes over the buses from 8086. To take over the bus, the 8087 sends out a low-going pulse on RQ/GT0 pin. The 8086 responds to this by sending another low going pulse back to the RQ/GT0 pin of 8087 and by floating its buses. The 8087 then increments the address it grabbed during the first transfer and outputs the incremented address on the address bus. When the 8087 output a memory read or memory write signal, another data word will be transferred to or from the 8087. The 8087 continues the process until it has transferred all the data words required by the instruction to/from memory. When the 8087 is using the buses for its data transfer, it sends another low-going pulse out on its RQ/ GT0 pin to 8086 to know it can have the buses back again. The next type of the synchronization between the host processor and the coprocessor is that required to make sure the 8086 hast does not attempt to execute the next instruction before the 8087 has completed an instruction. Taking one situation, in the case where the 8086 needs the data produced by the execution of an 8087 instruction to carry out its next instruction.

In the instruction



sequence for example the 8087 must complete the FSTSW STATUS instruction before the 8086 will have the data it needs to execute the MOV AX , STATUS instruction. Without some mechanism to make the 8086 wait until the 8087 completes the FSTSW instruction, the 8086 will go on and execute the MOV AX , STATUS with erroneous data We solve this problem by connecting the 8087 BUSY output to the TEST pin of the 8086 and putt puttin ing g on the the WAIT WAIT inst instru ruct ctio ion n in the the prog progra ram. m. Whil Whilee 8087 8087 is exec execut utin ing g an instruction it asserts its BUSY pin high. When it is finished with an instruction, the 8087 will drop its BUSY pin low. Since the BUSY pin from 8087 is connected to the TEST pin 8086 the processor can check its pin of 8087 whether it finished it instruction or not. You place the 8086 WAIT instruction in your program after the 8087 FSTSW instruction .When 8086 executes the WAIT instruction it enters an internal loop where it repeatedly checks the logic level on the TEST input. The 8086 will stay in this loop until it finds the TEST input asserted low, indicating the 8087 has completed its instruction. The 8086 will then exit the internal loop, fetch and execute the next instruction.

Chapter 3 : Intel 8086 Example

FSTSW STATUS

;copy 8087 status word to memory

MOV AX, STATUS ;copy status word to AX to check ; bits bits (a) In this set of instructions we are not using WAIT instruction. Due to this the flow of execution of command will takes place continuously even though the previous instruction had not finished it’s completion of its work .so we may lost data . FSTSW STATUS ;copy 8087 status word to memory FWAIT

;wait for 8087 to finish before-; doing next 8086 instruction

MOV AX,STATUS ;copy status status word word to AX to to check ; bits (b) In this code we are adding up of FWAIT instruction so that it will stop the execution of the command until the above instruction is finishes it’s work .so that you are not loosing data and after that you will allow to continue the execution of instructions. Another case where you need synchronization of the processor and the coprocessor is the case where a program has several 8087 instructions in sequence. The 8087 are executed only one instruction at a time so you have to make sure that 8087 has completed one instruction before you allow the 8086 to fetch the next 8087 instruction from memory. Here again you use the BUSY-TEST connection and the FWAIT instruction to solve the problem. If you are hand coding, you can just put the 8086 WAIT(FWAIT) instruction after each instruction to make sure that instruction is completed before going on to next. If you are using the assembler which accepts 8087 mnemonics, the assembler will automatically insert the 8-bit code for the WAIT instruction ,10011011 binary (9BH), as the first byte of the code for 8087 instruction. 3.18.4 Interfacing

Multiplexed address-data bus lines are connected directly from the 8086 to 8087. The status lines and the queue status lines connected directly from 8086 to 8087. The Request/Grant signal RQ/GT0 of 8087 is connected to RQ/GT1 of 8086. BUSY signal 8087 is connected to TEST pin of 8086. Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition. A WAIT instruction is passed to keep looking at its TEST pin, until it finds pin Low to indicates that the 8087 has completed the


computation. computation. SYNCHRONIZATIO SYNCHRONIZATION N must be established established between the processor processor and coprocessor in two situations. a) The execution of an ESC instruction that require the participation of the NUE must not be initiated if the NUE has not no t completed the execution of the previous instruction. b) When a processor instruction accesses a memory location that is an operand of a previous coprocessor instruction .In this case CPU must synchronize with NPX to ensure that it has completed its instruction. Processor WAIT instruction is provided. 3.18.5 Exception Handling

The 8087 detects six different types of exception conditions that occur during instr instruct uction ion executi execution. on. These These will will cause cause an interr interrupt upt if unmask unmasked ed and interr interrupt uptss are enabled. 1) INVALID OPERATION 2) OVERFLOW 3) ZERO DIVISOR 4) UNDERFLOW 5) DENORMALIZED OPERAND 6) INEXACT RESULT 3.18.6 Data Types

Internally, all data operands are converted to the 80-bit temporary real format. We have 3 types. •Integer data type •Packed BCD data type •Real data type Coprocessor data types

Integer Data Type Packed BCD Real data type Example

Converting a decimal number into a Floating-point number. 1) Converting Converting the decimal decimal number into binary form. form. 2) Normal Normalize ize the binary binary number number


3) Calcul Calculate ate the biased biased exponen exponent. t. 4) Store the number number in the the floatin floating-point g-point format. format. Example

Step Result 1) 100.25 2) 11001 1100100 00.01 .01 = 1.10 1.1001 01000 0001 1 * 26 3) 110+0 110+011 11111 11111 11=10 =1000 00010 0101 1 4) Sign = 0 Exponent =10000101 Significant = 10010001000000000000000 •

In step tep 3 the the bias biased ed expo expone nent nt is the expo expone nent nt a 26 or 110, 110,pl plus us a bias bias of 01111111(7FH) ,single precision no use 7F and double precision no use 3FFFH.

•

IN step 4 the information found in prior step is combined to form the floating point no.

3.18.7 Instruction Set

Thee 8087 Th 8087 inst instru ruct ctio ion n mnem mnemon onic icss begin beginss with with the the lett letter er F whic which h stan stands ds for for Floating point and distinguishes from 8086. These are grouped into Four functional groups. The 8087 detects an error condition usually called an exception when it executing an instruction it will set the bit in its Status register. Types

I. DATA TRANSFER INSTRUCTIONS. II. ARITHMETIC INSTRUCTIONS. III. COMPARE INSTRUCTIONS. IV. TRANSCENDENTAL INSTRUCTIONS.(Trigonometric and Exponential) V. CONSTANT INSTRUCTIONS 3.18.7.1 Data Transfers Instructions 3.18.7.1.1 REAL TRANSFER FLD Load real FST Store real FSTP Store real and pop FXCH Exchange registers


3.18.7.1.2 3.18.7.1. 2 INTEGER TRANSFER FILD Load integer FIST Store integer FISTP Store integer and pop PACKED DECIMAL TRANSFER(BCD) FBLD Load BCD FBSTP Store BCD and pop Example FLD Source - Decrements the stack pointer by one and copies a real number from a stack

element or memory location to the new ST. FLD ST(3)

Copies ST(3) to ST.

FLD FLD LON LONG_ G_RE REAL AL[B [BX] X]

;Num ;Numbe berr fro from m mem memor ory y ;co ;copi pied ed to to ST. ST.

FLD Destination- Copies ST to a specified stack position or to a specified memory

location . FST ST(2)

;Copies ST to ST(2),and ;increment stack pointer.

FST SHOR SHORT_ T_RE REAL AL[B [BX] X]

;Cop ;Copy y ST to to a memo memory ry at at a ;SHO ;SHORT RT_R _REA EAL[ L[BX BX]]

FXCH Destination – Exchange the contents of ST with the contents of a specified stack

element. FXCH ST(5)

;Swap ST and ST(5)

FILD Source – Integer load. Convert integer number from memory to temporary-real

format and push on 8087 stack. FILD DWORD PTR[BX] ;Short integer from memory at [BX]. Intege gerr stor store. e. Conve Convert rt numb number er from from ST to inte integer ger and and copy copy to FIST DestinationDestination- Inte memory. FIST LONG_INT ;ST to memory locations named LONG_INT. FISTP Destination -Integer store and pop. Identical to FIST except that stack pointer is

incremented after copy. FBLD Source- Convert BCD number from memory to temporary- real format and push

on top of 8087 stack.

Chapter 3 : Intel 8086 3.18.7.2 Arithmetic Instructions .

Four basic arithmetic functions: Addition, Subtraction, Multiplication, and Division. 3.18.7.2.1 Addition FADD Add real FADDP Add real and pop FIADD Add integer 3.18.7.2.2 Subtraction FSUB Subtract real FSUBP Subtract real and pop FISUB Subtract integer FSUBR Subtract real reversed FSUBRP Subtract real and pop FISUBR Subtract integer reversed 3.18.7.2.3 Multiplication FMUL Multiply real FMULP Multiply real and pop FIMUL Multiply integer 3.18.7.2.4 Advanced FABS Absolute value FCHS Change sign FPREM Partial remainder FPRNDINT Round to integer FSCALE Scale FSQRT Square root FXTRACT Extract exponent and mantissa. Example FADD – Add real from specified source to specified destination Source can be a stack or

memory location. Destination must be a stack element. If no source or destination is specified, then ST is added to ST(1) and stack pointer is incremented so that the result of addition is at ST. FADD FADD ST( ST(3), 3), ST ST

;Add ;Add ST to ST( ST(3) 3),, res resul ultt in in ST( ST(3) 3)


FAD FADD ST ST,ST(4)

;Add ST ST(4) to to ST ST, re result in in ST ST.

FADD FADD ;ST ;ST + ST(1 ST(1

, pop pop stac stack k res resul ultt at at ST ST

FADDP ST(1)

;Add ST(1) to ST. Increment stack ;pointer so ST(1) become ST.

FIADD Car_Sold

;Integer number from memory + ST

FSUB - Subtract the real number at the specified source from the real number at the

specified destination and put the result in the specified destination. FSUB ST(2), ST

;ST(2)=ST(2) – ST.

FSUB Rate

;ST=ST – real no from memory.

FSUB

;ST=( ST(1) – ST)

FSUBP - Subtract ST from specified stack element and put result in specified stack

element .Then increment the pointer by one. FSUBP ST(1) ;ST(1)-ST. ST(1) becomes new ST FISUB – Integer from memory subtracted from ST, result in ST.

FISUB Cars_Sold

;ST becomes ST – integer from memory

3.18.7.3 Compare Instructions. FCOM Compare real FCOMP Compare real and pop FCOMPP Compare real and pop twice FICOM Compare integer FICOMP Compare integer and pop FTST Test ST against +0.0 FXAM Examine ST 3.18.7.4 Transcendental Instruction. FPTAN Partial tangent FPATAN Partial arctangent F2XM1 2x - 1 FYL2X Y log2X FYL2XP1 Y log2(X+1) Example FPTAN – Compute the values for a ratio of Y/X for an angle in ST. The angle must be in

radians, and the angle must be in the range of 0 < angle < π/4.

Chapter 3 : Intel 8086 F2XM1 – Compute Y=2x-1 for an X value in ST. The result Y replaces X in ST. X must

be in the range 0≤X≤0.5. FYL2X - Calculate Y(LOG2X).X must be in the range of 0 < X < ∞ any Y must be in

the range -∞
FYL2X except that it gives more accurate results when compute log of a number very close to one. 3.18.7.5 Constant Instructions. Load Constant Instruction FLDZ Load +0.0 FLDI Load+1.0 FLDPI Load π FLDL2T Load log210 FLDL2E Load log2e FLDLG2 Load log102 FLDLN2 Load loge2 ALGORITHM To calculate x to the power of y

Load base, power. Compute (y )*( log2 x) Separate integer(i) ,fraction(f) of a real number Divide fraction (f) by 2 Compute (2 f/2) * ( 2f/2) xy = (2x) * (2y ) Program: Program to calculate x to the power of y

.MODEL SMALL .DATA x

Dq 4.567

;Base

y

Dq 2.759

;Power

temp DD


temp1 DD temp2 DD

;final real result

tempint

DD

tempint1

DD

two

DW

diff

DD

trunc_cw

DW 0fffh

;final integer result

.STACK 100h .CODE star startt

: mov mov ax, ax, @DA @DATA TA ;ini ;initt dat dataa segm segmen entt mov ds, ax

• load:

fld y

;load the power

fld

x

;load the base

• comput: fyl2x

;compute (y * log2(x))

fst

;save the temp result

temp

trunc: fldcw trunc_cw

;set truncation command

frndint fld temp

;load real number of fyl2x

fist tempint

;save integer after truncation

fld temp

;load the real number

• getfrac: fi fisub tempint

;subtract the in integer

fst diff

;store the fraction

fracby2: fidiv two

;divide the fraction by 2

twopwrx: f2xm1

;calculate the 2 to the power fraction

fst temp1

;minus 1 and save the result

fld1

;load1

fadd

;add 1 to the previous result

fst temp1

;save the result


sqfr sqfrac ac:: fmul mul st(0 st(0)),st ,st(0) (0)

;squa square re the resu resullt as frac fracttion ion

fst temp1

;was halved and save the result

fild tempint

;save the integer portion

fxch

;interchange the integer ;and power of fraction.

scale: fscale

;scale the result in real and ;integer

fst temp2

;in st(1) and store fist tempint1 ;save the final result in real and integer

over: mov ax,4c00h

;exit to dos

int 21h end start

3.15 Procedure and Macros of 8086 3.15.1 Procedure:

Named group of statement which is performed particular task is called procedure. Procedure or subroutine may require input data or constants for their execution. Their data or constants may be passed to the subroutine by main program or some subroutine may access readily available data of constants available in memory. Generally , the following technique are used to pass input / parameter to procedures in ALP f)

Using Global declared variable

g)

Using re registers of of CP CPU ar architecture ure

h)

Using memory location

i)

Using stack

j)

Using PU PUBLIC and EXTERN

3.15.1.1 Using Global declared variable

A variable or a parameter label may be declared global in the main program and the same variable or parameter label can be used by all the procedures of the application. Examples of passing parameters ASSUME CS : CODE,DS : DATA DATA SEGMENT NUMBER EQY 77H GLOBAL


DATA ENDS CODE1 SEGMENT START :


-

-

-

CODE1 ENDS ASSUME CS : CODE2 CODE2 SEGMENT START :


-

-

-

CODE2 ENDS END START 3.15.1.2 Using registers of CPU architecture

Thee CPU Th CPU gene genera rall purpos purposee regi regist ster erss may may be used used to pass pass param paramet eter erss to the the procedures. The main program may store the parameters to be passed to the procedure in the variable CPU registers and the procedure may use the same register content for execution. The original content of the used CPU register may change during execution of the procedure. This may be avoided by pushing all the register content to be used to the stack sequentially at the start of the procedure and poping all the register contents at the end of the procedure in opposite sequence. ASSUME CS : CODE,DS : DATA CODE SEGMENT START :

MOV AX A X , 5555H MOV BX , 5456H -

-

-

-

PROCEDURE P1 NEAR -

-


-

-

ADD AX , BX -

-

-

-

RET P1 ENDP CODE ENDS END START 3.15.1.3 Using memory location

Memory location may also be used to pass parameter to a procedure in the same way as registers. A main program may store the parameter to be passed to a procedure at known known memory memory addres addresss locatio location n and the procedur proceduree may use the same same locatio location n for accessing the parameter. Example: ASSUME CS : CODE,DS : DATA DATA SEGMENT NUM DB (55H) COUNT EQY 77H DATA ENDS CODE SEGMENT START :


-

-

-

CALL ROUTINE -

-

-

-

PROCEDURE ROUTINE NEAR MOV BX , NUM MOV CX , COUNT -

-


ROUTINE ENDP CODE ENDS END START 3.15.1.4 Using stack

Stack memory can also be used to pass parameters parameters to procedure. A main program may store the parameters to be passed to a procedure in its CPU registers . The registers will further further be pushed on to the stack. The procedure during during its execution execution pops back the appro appropr pria iate te para parame mete ters rs as and and when when requi require red. d. Th This is proc procedu edure re of pop popin ing g back back the the parameters must be implemented carefully because besides the parameters to be passed to the proced procedure ure the stack stack contai contains ns other other import important ant inform informati ation on like like content contentss of other other pushed registers, return addresses from the current procedure and other procedure or interrupt service routines. Example : ASSUME CS : CODE,SS : STACK STACK SEGMENT STACKDATA DB 200H DUP ( ? ) STACK ENDS CODE SEGMENT START :

MOV AX A X , STACK MOV SS,AX MOV BX , 55H MOV CX , 10H -

-

PUSH AX PUSH CX CALL ROUTINE -

-

-

-

PROCEDURE ROUTINE NEAR -

-

MOV DX , SP


ADD SP ,02H POP CX POP BX MOV SP , DX -

-

ROUTINE ENDP CODE ENDS END START 3.15.1.5 Using PUBLIC and EXTERN

For passing passing the paramet parameters ers to procedure proceduress using

the PUBLIC PUBLIC & EXTERN EXTERN

directives , must be declared PUBLIC (for all routine) routine) in the main routine and the same should be declared EXTERN in the procedure Thus the main program can pass the PUBLIC parameter to a procedure in which it is declared EXTERN(external) Example: ASSUME CS : CODE,DS : DATA DATA SEGMENT PUBLIC NUMBER EQY 77H DATA ENDS CODE SEGMENT START :


-

-

-

CALL ROUTINE -

-

PROCEDURE ROUTINE NEAR EXTERN NUMBER MOV AX , NUMBER ROUTINE ENDP CODE ENDS

-


END START 3.15.2 MACROS

The macro is also similar to subroutine. Suppose , a number of instructions are repeat repeating ing through through in the main program program , the listin listing g

become becomess length lengthy. y. So a macro macro

definition i. e. a label , is assigned with in the repeatedly appearing string of instructions. The process of assignin assigning g a label or macro name to the string string is called macro. macro. A macro within within the macro is called nested nested macro. The macro name or macro definiti definition on is then used throughout the main program to refer to the string of instructions. Thee diff Th differ erenc encee betwe between en a macr macro o and a subr subrout outin inee is that that in the the macr macro o the the complete code of the instructions string is inserted inserted at each place where the macro name appears. Hence the EXE file becomes lengthy. Macro does not utilize the service of stack .There is no question of transfer of control as the program using the macro inserts the complete code of the macro at every reference of the macro name. On the other hand , subroutine is called whenever necessary, i.e. the control of execution is transferred to the subroutine , every time it is called . The executable code in case of the subroutines becomes smaller as the subroutine appears only once in the complete code. Thus , the EXE file is smaller as compared to the program using macro .The control is transferred to the subroutine whenever it is called , and this utilize the stack service .The program using subroutine requires less memory space for execution than the using the macro. Macro requires less time for execution , as it does not contain CALL and RET instructions as the subroutine do 3.15.2.1 Defining a MACRO

A MACRO can be defined anywhere in the program using the directives MACRO and ENDM. The label prior to MACRO is the macro name which should be used in the actual program. The ENDM directive mark the end of the instructions .The following macro DISP displays the message MSG on the CRT. The syntax is as given: DISP MACRO MOV AX , SEG MSG MSG MOV DS , AX MOV DX , OFFSET MSG MOVE AH , 09H


INT 21H ENDM The above definition of macro assign the name DISP to the instruction sequence between the directives MACRO and ENDM. While assembling , the above sequence of the instructions will replace the label ‘DISP’, whenever it appear in the program. A macro may be called by quoting its name, along with any value to be passed to the macro. Calling a macro means inserting the statements and instructions represented by the macro directly at the place of the macro name in the program. 3.15.2.2 Passing Parameters to a MACRO

Using parameters in a definition , the programmer specifies the parameters of the macro those are likely to be changed each time the macro is called. For example the DISP macro written above can be made to display two different message MSG1 and MSG2 as shown DISP MACRO MOV AX , SEG MSG MSG MOV DS , AX MOV DX , OFFSET MSG MOVE AH , 09H INT 21H ENDM This parameter MSG can be replaced by MSG1 and MSG2 while calling the macro as shown. ASSUME CS : CODE,DS : DATA CODE SEGMENT START :

MOV AX AX,DATA -

-

DISP MSG1 -

-

DISP MSG2 CODE ENDS

-


END START MSG1 DB OAH,ODH ,”PROGRAM TERMINATED NORMALLY” MSG1 DB OAH,ODH ,”Retry ,Abort , Fail” 3.16 Assembler Directives And Operators

The main main advant advantage age of machin machinee languag languagee progra programmi mming ng is that that the memory memory control is directly in the hands of the programmer enabling him to manage the memory of the system system more efficiently. However, there are more disadvantages. The programming, programming, coding and resource resource management management techniques techniques are tedious. tedious. As the programs programs one has to have a thorough technical knowledge of the processor architecture and instruction set. The assembly language programming is simpler as compared to the machine programming. The instruction mnemonics mnemonics are directly written in the assembly language language progr program ams. s.

Thee prog Th progra rams ms are are now now more more read readabl ablee than than that that of mach machin inee lang langua uage ge

programs. The advantage that assembly assembly language has over machine language in that now the address address values and the constants constants can be identified identified by labels. If the labels are clear clear then then certa certain inly ly the the prog progra ram m will will beco become me more more und under erst stand andab able le,, and and each each time time the the programmer will not have to remember the different constants and the addresses at which they are stored, throughout throughout the programs. Due to this facility, the tedious tedious byte handling and manipulations are got rid of. Similarly, now different different logical segments and routines routines may be assigned with the labels rather rather than the different addresses. The memory control of machin machinee languag languagee progra programmi mming ng is left left unchang unchanged ed by provid providing ing storag storagee define define facilities in assembly language programming. programming. The documentation facility facility which was not possible with machine language programming is now available in assembly language. Readers will get a better glimpse of the different features of assembly language, when we discuss assembly programming in the next chapter. An assembler is a program used to convert an assembly language program into the equivalent machine code modules which may further be converted to executable codes. codes. It decides decides the address address of each label and substitu substitutes tes the vales for each of the constants constants and variables. variables. It then forms the machine machine code for the mnemonics mnemonics and data in the assembly assembly language language program. While While doing these things, things, the assembler assembler may find out syntax syntax errors. The logical logical errors or other programmi programming ng errors are not found out by the assembler. For completing all these tasks, an assembler needs some hints from the


programmer programmer,, i.e. the required required storage for a particular particular constant constant or a variable, logical logical names of the segments, types of the different routines and modules, end of file, etc. These types of hints are given to the assembler using some predefined alphabetical strings called assembler directives, which help the assembler to correctly understand the assembly language programs to prepare the codes. Another type of hint which helps the assembler to assign a particular constant with with a label label or initia initializ lizee parti particula cularr memory memory location locationss or labels labels with constan constants ts is an operator. In fact, the operators perform perform the arithmetic and logical tasks unlike directives that just direct the assembler assembler to correctly correctly interpret interpret the program program to code it appropriately. appropriately. The following directives are commonly used in the assembly language programming practice practice using Microsoft Microsoft Macro Assembler Assembler or Turbo Assembler. Assembler. The directives directives and operators are discussed here but their meanings and uses will be more clear in Chapter 3 on assembly language programming techniques. 3.16.2 DB: Define Byte

The DB directive is used to reserve byte or bytes of memory locations in the available available memory. While While preparing the EXE file, this directs the assembler assembler to allocate allocate the specified number of memory bytes to the said data type that may be a constant, variable, string, etc. Another option of this directive also initializes the reserved memory bytes bytes with the ASCII codes codes of the charact characters ers specifi specified ed as a string string..

The followi following ng

examples show how the DB directive is used for different purposes.

Example RANKS

DB 01H, 02H,

03H, 04 04H

This statement directs the assembler to reserve four memory locations for a list named RANKS and initialize them with the above specified four values. MESSAGE DB ‘GOOD MORNING’

This makes the assembler reserve the number of bytes of memory equal to the number of characters in the string named MESSAGE and initialize those locations by the ASCII equivalent of these characters. VALUE DB 50H


This statement direct the assembler to reserve 50H memory bytes and leave them un initialized for the variable named VALUE

3.16.2 DW: Define Word

The DW directive serves the same purposes as the DB directive, but it now makes the assembler reserve the number of memory words (16- bit) instead of bytes. Some examples are given to explain this directive. directive.

Example WORDS

DW 1234H, 4567H, 78BH, 045CH,

This makes the assembler reserve four words in memory (8 bytes), and initialize the words with the specified values in the statements. During initialization, initialization, the lower bytes are stored at the lower memory addresses, while the upper bytes are stored at the higher addresses. Another option of the DW directive is explained with the the DUP operator. WDATA

DW 5 DUP (6666H)

This statement reserves five words,i.e.10 – bytes of memory for a word lable WDATA and initializes all the word locations with 6666H.

3.16.3 DQ : Define Quad word

This directive is used to direct the assembler to reserve 4 words (8 bytes) of memory for the specified specified variable and may initialize initialize it with the specified specified values. 3.16.4 DT: Define Ten Bytes

This DT directive directs the assembler to define the specified variable requiring 10- bytes bytes for its storag storagee and initial initialize ize the 10 – bytes bytes with the specifie specified d values values.. The directive may be used in case of variables facing heavy numerical calculations, generally processed by numerical processors. 3.16.5 ASSUME: Assume logical Segment Name

The ASSUME directive is used to inform inform the assembler, the names of the logical segments segments to be assumed for differen differentt segments used used in the program. program. In the assembly assembly language language program, each segment segment is given a name. For example, example, the code segment may be given given the name CODE, CODE, data segme segment nt may be give given n the the name name DATA DATA etc. etc.

Thee Th


statem statement ent ASSUME ASSUME

CS: CODE CODE

direct directss the assemb assembler ler that that the machin machinee codes are are

available in a segment named CODE, and hence the CS register is to be loaded with the address (segment) allotted by the operating system for the label CODE, while loading, Similarly, 3.16.6 ASSUME DS: DATA

It indica indicates tes to the assem assemble blerr that that the data data items items relate related d to the program, program, are available in a logical segment named DATA, and the DS register is to be initialized by the segment address value decided by the operating system for the data segment, while loadin loading. g.

It then then conside considers rs the the segment segment DATA DATA as a default default data data segment segment for each each

memory operation, related to the data and the segment CODE as a source segment for the machine codes of the program. The ASSUME statement statement is a must at the staring of each assemb assembly ly languag languagee progra program, m, withou withoutt which which a messag messagee ‘CODE/ ‘CODE/DAT DATA A EMITTE EMITTED D WITHOUT SEGMNT’ may be issued by an assembler. 3.16.7 END: END of Program

The END directive directive marks the the end of an assembly language language program. program. When the assembler comes across this END directive, it ignores the source lines available later on. Hence, it should be ensured that the END statement should be the last statement in the file and should not appear appear in between. Also, Also, no useful program statemen statementt should lie in the file, after the END statement. 3.16.8 ENDP: END of Procedure

In assembly assembly language programming, programming, the subroutines are called called procedures. They may be independent program modules which return particular results or values to the calling calling programs. programs. The ENDP ENDP directive directive is is used to to indicate indicate the end end of a procedure procedure.. A proced procedure ure is usual usually ly

assign assigned ed a name, i.e. i.e. label. label. To mark mark the end of a partic particula ular r

procedure, the name of the procedure, i.e. label may appear as a prefix prefix with the directive directive ENDP. The statements, appearing in in the same module but after the ENDP directive, directive, are neglected from that procedure. The structure given below explains the the use of ENDP. PROCEDURE STAR : STAR ENDP

3.16.9 ENDS : END of Segment


This This direct directive ive marks marks the end of a logica logicall segmen segment. t. The logical logical segment segmentss are assigned assigned with with the names using the ASSUME directive. directive.

The names names appear with the

ENDS directive as prefixes to mark the end of those those particular segments. Whatever are the contents contents of the segments, segments, they should should appear in the program program before ENDS. ENDS. Any statem statement ent appear appearing ing after after ENDS ENDS will will be neglec neglected ted from the segmen segment. t. The structu structure re shown below explains the fact more clearly. DATA

SEGMENT :

DATA

ENDS

ASSUME

CS: CODE, DS : DATA

CO DE

SEGMENT :

CO DE

ENDS

END

The above structure represents a simple program containing two segments named DATA DATA and CODE. CODE.

Thee data Th data relat related ed to the the progr program am must lie betwe between en the DATA DATA

SEGMENT SEGMENT and DATA ENDS statement statements. s. Similarly Similarly,, all all the the executa executable ble instruction instructionss must lie between CODE SEGMENT and CODE ENDS statements. 3.16.10 EVEN : Align on EVEN Memory Address

Thee asse Th assemb mble ler, r, whil whilee star starti ting ng the the asse assemb mbli ling ng proce procedu dure re of any any prog progra ram, m, initializes initializes a location location counter and goes on updating updating it, as the assembly assembly proceeds. It goes on assigning the available addresses, i.e. the contents of the location counter, sequentially to the progra program m variab variables les,, constan constants ts and module moduless as per their their requir requireme ements nts,, in the sequence in which they appear in the program. The EVEN directive updates the location counter to the next even address, if the current location counter contents are not even, and assigns the following routine routine or variable or constant to that that address. The structure given below explains the directive. EVEN PROCEDURE ROOT The above structure shows a procedure ROOT that is :to be aligned at an even address. The assembl assembler er will start start assemb ass emblin ling g the main program prog ram callin calling g ROOT. ROOT. When When the ROOT ENDP


assemb assembler ler comes comes across across the direct directive ive EVEN, EVEN, it checks checks the conten contents ts of the locati location on counter. If it is odd, it is updated to the next even value and then the ROOT procedure is assigned to that that address, i.e. the updated contents of the location counter. If the content of the location counter is already even, then the ROOT procedure will be assigned with the same address. 3.16.11 EQU : Equate

The directive EQU is used to assign a label with a value or a symbol. symbol. The use of this directive is just to reduce the recurrence of the numerical values or constants in a program code. The recurring value is assigned assigned with a label, and that label is is used in place of

that numeri numerical cal value, value, throughout throughout the program. program. While assembling assembling,, whenever whenever the

assembler assembler comes across across the label, it substitut substitutes es the numerical numerical value for that label and finds out the equivalent equivalent code. Using the EQU directive, directive, even an instructi instruction on mnemonic can be assigned assigned with a label, which which can then be used in the program program in place of that mnemonic. Suppose, a numerical constant which appears in a program ten times. If that constant is to be changed at a later time, one will have to make the correction 10 times. This may lead to human errors, because it is possible that a human programmer may miss one of those corrections. This will result in the generation of wrong codes. If the EQU directive is used to assign the value with a label that can be used in place of each recurrence of that constant, only one change in the EQU statement will give the correct and modified code. The examples given below show the syntax. syntax.

Example LABEL

EQU

0500H

ADDITION

EQU

ADD

The first statement assigns the constant 500H with the label LABEL, while the second statement assigns another label ADDITION with mnemonic ADD.

3.16.12 EXTRN: External and PUBLIC : Public


The directive directive EXTRN informs informs the assembler assembler that the names, names, procedures procedures and labels declared after this directive have already been defined in some other assembly language modules. While in in the other module, where the names, procedures and labels actually appear, they must be declared public, using the PUBLI directive. If one wants to call call a proc proced edur uree

FACT FACTOR ORIA IAL L appe appear arin ing g in MODULE MODULE 1 from from MODULE MODULE 2; in

MODULE 1, it must be declared PUBLIC using the statement PUBLIC FACTORIAL and and in modu module le 2, it must must be decl declar ared ed exte extern rnal al usin using g the the decl declar arat atio ion n EXTR EXTRN N FACTORI FACTORIAL. AL.

The stateme statement nt of declar declarati ation on EXTRN must be accomp accompani anied ed by the

SEGMENT and ENDS ENDS directives of the MODULE 1, before it it is called in MOBULE 2. Thus the MODULE 1 and MODULE 2 must have the following declarations. MODULE 1 PUBLIC MODULE 1


MODULE 2 EXTRN MODULE 2


3.16.13 GROUP :Group the Related Segments

This directive is used to form logical groups of segments with similar purpose or type. type. This This directi directive ve is used used to inform inform the assemb assembler ler to form a logica logicall group group of the following segment names. The assembler passes an information information to the linker / loader loader to form the code such that the group declared segments or operands must lie within a 64kbyte memory segment. Thus all such segments and labels can be addressed using the same segment base. PROGRAM GROUP CODE, DATA, STACK The above statement directs the loader / linker to prepare an EXE file such that

CODE, DATA and STACK segment segment must lie within a 64kbyte memory segment that that is named named as PROGRA PROGRAM. M.

Now, Now, for the ASSU ASSUME ME state stateme ment nt,, one one can can use use the the labe labell

PROGRAM rather than CODE, DATA and STACK as shown. ASSUME CS : PROGRAM, PROGRAM, DS : PROGRAM, SS: PROGRAM PROGRAM

3.16.14 LABEL : Label


The Label directive is used to assign a name to the current of the location counter. When the assembly process starts, the assembler initializes a location counter to keep track of memory memory locations locations assigned assigned to the program. As the program assembly assembly proceeds, the contents of the location counter are updated. During the assembly process, whenever the assembler comes across the LABEL directive, it assigns the declared label with the current contents of the location location counter. The type of the label must be specified, specified, i.e. whether it is a NEAR or o r a FAR label, BYTE or WORD label, etc. A LABEL directiv directivee may be used to make a FAR jump jump as shown below. below. A FAR jump cannot be made at a normal normal label with a colon. The label CONTINUE can be used for a FAR jump, if the program contains the following following statement. CONTINUE LABEL FAR

The LABEL directive can be used to refer to the data segment along with the data type, byte or word as shown. DATA SEGMENT DATAS DB 50H DUP (?) DATA – LAST LABEL BYTE FAR DATA ENDS

After reserving 50H locations for DATAS, the next location will be assigned a label DATA – LAST and its type will be byte and far. 3.16.15 LENGTH : Byte Length of a Label

This directive is not available in MASM. This is used to refer refer to the length of a data array or a string. MOV CX, LENGTH ARRAY

This statement, when assembled, will substitute the length of the array ARRAY in bytes, in the instruction. 3.16.16 LOCAL

The labels, variables, constants or procedures declared LOCAL in a module are to be used only by that particular module. module. After some time, some other module may declare a particular data type LOCAL, which was previously declared LOCAL by an other module or modules. modules. Thus the same same label may serve differe different nt purposes purposes for different different


modules of a program. With a single declaration statement, a number of variables variables can be declared local, as shown. LOCAL a, b, DATA, ARRAY, ROUTINE 3.16.17 NAME : Logical Name of a Module

The NAME directive is used to assign a name to an assembly language program module module.. The modul module, e, may now now be referre referred d to by its decla declared red name. name. The names names,, if selected to be suggestive, may point out the functions of the different modules and hence may help in the documentation. 3.16.19 OFFSET : Offset of a Label

When the assembler comes across the OFFSET operator along with a label, it first first computes the 16 – bit displacemen displacementt (also called as offset interchang interchangeably eably ) of the par parti ticu cula larr labe label, l, and and repl replac aces es the the stri string ng ‘ORR ‘ORRSE SET T LABE LABEL’ L’ by the the comp comput uted ed displacement. This operator is used with arrays, arrays, strings, strings, labels and procedures to to decide their offsets offsets in their their default default segments. segments. The segment segment may also be decided by another another operator operator of similar similar type, viz, SEG. Its most common common use is in the case of the indirect, indirect, indexed, or other addressing techniques of similar types, used to refer to the memory indirectly. The examples of thus operator are as follows.

Example CODE SEGMENT MOV SI, OFFSET LIST CODE ENDS DATA SEGMENT LIST DB 10H DATA ENDS

3.16.20 ORG: Origin

The ORG directive the assembler to start start the memory allotment allotment for the particular segment, segment, block or code from the declared address in the ORG statement. statement. While While stating the assembly assembly process process for a module, the assembler assembler initializes initializes a location counter counter to keep track of the allotted addresses for the module. module. If the ORG statement is not written written in the


program, the location counter is initialized to 0000. If an ORG statement is present at the the starting of the code segment of that module, then the code will start from 200H address in code segment. segment. In other words, words, the location location counter will get in initialise initialised d to the address address 0200H instead instead of 0000H. Thus, the the code for different different modules modules and segments segments can be located in the available memory memory as required required by the programmer. The ORG directive directive can even be used with data segments similarly. 3.16.21 PROC: Procedure

The PROC directive marks the start of a named procedure in the statement. Also, the types NEAR of FAR specify the the type of the procedure, i.e. i.e. whether it is to to be called by the main program located located within 64K of physical memory memory or not. For example, the statement RESULT PROC NEAR marks the start of a routine RESULT, which is to be called by a program located located in the same segment of memory. memory. The FAR directive directive is used for the procedures to be called by the programs located in different segments of memory. The example statements statements are as follows:

Example RESULT

PROC

NEAR

ROUTINE

PROC

FAR

3.16.22 PTR : Pointer

The POINTER operator is used to declare the type of a label, variable or memory operand. The operator PTR is prefixed by either BYTE or WORD. If the prefix prefix is BYTE, then the particular label, variable or memory operand is treated as an 8 – bit quantity, while if WORD is the the prefix, then it is treated as a 16 – bit quantity. In other words, the PTR operator is used to specify specify the data type – byte or word. The examples of the PTR operator are as follows: Example

MOV AL, BY BYTE PT PTR [SI]

-

Moves content of memory location

addressed by SI ( 8 –bit ) to AL INC BYTE PTR [BX]

-

Increments byte contents of memory location addressed by BX


MOV BX, WORD PTR [2000H] -

Move 16 –bit content of memory location 200H to BX, i.e. [2000H] to BL [2001H] to BH

INC WO WORD PTR [3 [300h]

-

Increments word contents of memory location 3000H considering contents of of 3000H (lower byte) and 3001H (higher byte ) as a. 16 –bit number

In case of JMP instructions, the PTR operator is used to specify the type of the jump, i.e. near of far, as explained in the examples given below. JMP

NEAR PTR [BX] – NEAR jump

JMP

FAR

PTR [BX] – FAR jump

3.16.23 PUBLIC

As already discussed, the PUBLIC directive is used along with the EXTRN directive. This informs the the assembler that the the labels, variables, constants, constants, or procedures declared PUBLIC may be assessed assessed by other assembly modules to form their their codes, but while using the PUBLIC declared labels, variables m constants or procedures the user must declare them externals using the the EXTRN directive. On the other other hand, the data types types declare declared d EXTRN EXTRN in module module of the progra program, m, may be declared PUBLIC in at least any one of the other modules of the same program. (Refer to the explanation on EXTRN directive to get the clear idea of PUBLIC) 3.16.24 SEG: Segment of Label

The SEG operator is used to decide the segment address of the label, label, variable, or proced procedure ure and substitu substitutes tes the segment segment base address address in place of “SEG” “SEG” label. label. example given below explains the use of SEG operator.

Example

MOV MOV

AX, AX, SEG SEG

ARRA ARRAY Y

; Th This is stat statem emen entt move movess the the segm segmen entt addr addres esss of ARRAY in

MOV

DS , A X

; Which it is appearing, to register AX and then to DS.

The


3.16.25 SEGMENT : Logical Segment

The SEGMENT directive marks the starting starting of a logical segment. The started is also assigned assigned a name, i.e. label, by this statement. The SEGMENT and ENDS directive must bracket bracket each logical logical segment of a program. program. In some cases, cases, the segment segment may be assigned a type like PUBLIC (i.e. can be used by other modules of the program while linking) linking) or GLOBAL GLOBAL (can be accessed accessed by any other other modules). modules).

The program program structure structure

given below explains the use of the SEBMENT directive. EXE. CODE SEGMENT GLOBAL

; Start of segment named EXE. EXE. CODE that can be accessed by any other module.

MOV

DS, AX

; END of EXE. CODE logical segment

3.16.26 SHORT

The SHORT operator indicates to the assembler that only one byte byte is required to code the displacement for a jump (i.e. displacement is within – 128 to + 127 bytes from the address address of the byte next to the jump opcode). This method method of specifying specifying the jump address address saves the memory. memory. Otherwise, Otherwise, the assembler assembler may reserve reserve two bytes for the displacement. The syntax of the statement is is as given below. below. JMP SHORT LABEL

3.16.27 TYPE

The TYPE operator directs the assembler to decide the data type of the specified label and replaces the ‘TYPE’ label by the decided data type. type. For the word type variable, the data type type is 2, for double double word type, type, it is 4, 4, and for byte byte type, it is is 1. Suppose, Suppose, the STRING is a word array. The instruction instruction MOV AX, TYPE STRING moves the value 0002H in AX.

3.16.28 GLOBAL


The labels, variables constants or procedures declared GLOBAL may be used by other modules modules of the program. program. Once a variable variable is declared declared GLOBAL, it can be used by any module in the program. program. The following statement statement declares the procedure ROUTINE as a global label. ROUTINE

PROC GLOBAL

‘ + & -’ Operators Operators

These operators operators represent represent arithmeti arithmeticc addition addition and subtractio subtraction n

respectively and are typically used to add or subtract displacements (8 or 16 bit) to base or index registers or stack or base pointers p ointers as given in the example:

Example MOV AL, [ SI + 2] MOV DX, [ BX - 5] MOV BX, [ OFFSET LABEL + 10H ] MOV AX, [ BX + 9I ]

3.16.29 FAR PTR

This directive directive indicates indicates the assembler assembler that the label followin following g FAR PTR is not available within the same segment and the address of the label is of 32 – bits i.e. 2 bytes offset followed by 2 bytes segment address.

Example JMP

FAR

PTR

CALL FAR PTR

LABEL ROUTINE

Both the above instructions indicate to the assembles that the target address is going to require four bytes; Lower byte of offset, higher byte of offset, lower byte of segment and higher byte byte of segment; indicating inter segment addressing addressing mode.

3.16.30 NEAR PTR


This This direct directive ive indica indicates tes that that the label follow following ing NEAR NEAR PTR is in the same same segment and needs only 16 bit i.e. 2 byte offset to address it.

Example

JMP NEAR PTR

LABEL

CALL NEAR PTR ROUTINE

If a label is not preceded by NEAR PTR or FAR PTR, then it is by default considered a NEAR PTR label and two bytes are reserved by the assembler for its address during the process of assembling.

Chapter 3 : Intel 8086 3.17 Assembly language programming of 8086 1.Writ a program for addition of two numbers.

ASSUME CS: CODE, DS : DATA DATA SEGMENT OPR 1 DW 1234 H

; 1 st operand

OPR 2 DW 0002 H

; 2nd operand

RESULT DW 01 DUP (?)

; A word of memory reserved for RESULT

DATA ENDS CODE SEGMENT START : MOV AX, DATA

; Initialization of data segment

MOV DS, AX MOV MOV AX, AX, OPR OPR 1

; tak takee 1st 1st oper operan and d in in AX AX

MOV B X, OPR 2

; take 2 n operand in BX

CLC

; Cleat carry

ADD AX, BX

; Add B X to AX

MOV DI, OFFSET RESULT; Take offset o ffset of Result in DI MOV [D [DI], AX AX

; St Store th the re result ult at at me memory ory ad adder ders in in DI DI

MOV AH, 4CH I NT 2 1 H

2.

; Return to Dos prompt

CODE ENDS

; CODE segment ends

END START

; program ends

Writ Wr itee a prog progra ram m for for the the add addit itio ion n of of a seri series es of 8 bit bit nu num mbers bers .

ASSUME CS: CODE, DS : DATA DATA SEGMENT NUMLIST DB 52 H, 23 H, 02H, 03H, 04H COUNT EQU 5 H

; counter

RESULT DW 01H DUP (?)

; one word is reserved for result

CODE SEGMENT ORG 200 H

; address 0200 h in code segment

START : MOV MOV AX, DATA MOV DS, A X

; Initialize data segment


MOV CX, COUNT

; set the counter value in C X

XOR AX, AX

; Clear AX and CF

XOR BX, BX

; Clear BH

MOV MOV SI SI , OFFSE OFFSET T NUML NUMLIS IST T

; poi point nt to the the fir first st number number

AGAIN : MOV BL,[SI]

; Take the I st number

ADD AX, BX

; Add Ax with BX

INC SI

; Increment pointer

DEC CX

; Decrement counter

JNZ AGAIN

; if all numbers are added point to result

MOV DI, OFFSET RESULT

; destination and store it

MOV [DI], A X MOV AH, 4C H

; return to dos

CODE ENDS END START

3. write a program program to find out the number number of even even and odd numbe number r from given given series of 16 bit numbers . Solution :

The simplest logic to decide whether a binary number iS even or odd, is to

check the least significant bit of the number. If the bit is zero, the number is even otherwise it is odd. Check the LSB by rotating the numbers through carry flag and increment even or odd number counter. ASSUME CS : CODE , DS : DATA DATA SEGMENT LIST DW 2357H, 0A57H ,0C32H , 0C91H , 0957H COUNT EQU 006H DATA ENDS CODE SEGMENT START

: XOR B X , BX XOR DX , DX MOV AX , DATA MOV DS, AX


MOV CL, COUNT MOV SI , OFFSET LIST AGAIN :

MOV AX , [SI] ROR AX , 01 JC ODD INC BX JMP NE X T

ODD :

INC X

NEXT :

ADD SI, 02 DEC

CL

JNZ AGAIN MOV AH, 4C H INT 21 H CODE ENDS END START

4. Write a program to find out the number of positive and negative numbers form a given series of signed numbers . Solution :

Take the it numbers is any of the registers. Rotate it left through carry. The

status of carry flag i.e the most significant bit of the number will give the information about the sign of the number, If F is 1 the number is negative ; otherwise it is positive ASSUME CS : CODE , DS : DATA DATA SEGMENT 457 DW 2579 H, 0A500 H, 0C009H, 0159H, 0B900 H COUNT EQU 05 H DATA ENDTS CODE SEGMENT START :

XOR B X , B X XOR AX , D X MOV AX , DATA MOV DS, AX


MOV CL, COUNT MOV SI, OFFSET LIST AGAIN : MOV AX, [SI] SHL AX , 01 JC NEG INC BX JMP NEXT NEG : INC DX NEXT : ADD SI, 02 DEC CL JNZ AGAIN MOV AH, 4CH INT 21 H CODE ENDS END START

5.

Write an assembly language program to arrange a given series of

hexadecimal bytes in ascending order Solution :

There exist a large number of sorting sorting algorithm. algorithm. The algorithm algorithm used here is bubble sorting. The method of sorting in explained as follows. To start with, the first number of the first series is compared with with the second one, if the first first number in greater than second one one , exchange exchange their positi positions ons in the the series series otherwise otherwise leave leave the positi position on unchanged. Then compare the second number in the recent form the series with third and repeat the exchange part that you have carried carried out for the first first and second numbers, and for all the remaining numbers of the series. Repeat this procedure for the complete series (n-1) times . After (n -1) iterations ,you will get the largest numbers at the end of the series. series. where ‘n’ ‘n’ is the the length length of the series. series. Again start start from from the first first address address of the series. Repeat the same procedure right from the first element to to the last element. After (n -2) iterati iterations ons you will will get the second second highest highest number number at the last last but one place in the


series .Continue this till till the complete series is arranges in ascending order let let the series be as given . 53 , 25 , 1 9, 02

n=4

25 , 53 , 1 9, 02

Ist operation

25 , 19 , 5 3, 02

2nd operation

25 , 19 , 0 2, 53

3rd operation

Largest no

4 -1 = 3 operations



19 , 25, 02, 53

Ist operation

19 , 02 , 2 5, 53

2 nd operation

2 nd largest number  4 -2 = 2 operations 02, 19, 25, 53 3rd largest number

Ist operation 

4 -3 = 1 operation

Instead of taking a variable count for the external loop in the program like (n-1), (n- 2) , (n- 3) etc It is better to take the count (n-1) all the time for simplicity.The resulting program in given as shown . ASSUME CS : CODE , DS : DATA DATA SEGMENT LIST DW 53 H, 25H, 19 H, 02 H COUNT EQU 04 H DATA ENDS CODE SEGMENT START : MOV AX , DATA MOV DS , AX MOV DX , COUNT – 1 AGAIN : MOV CX , D X MOV SI, OFFSET LIST AGAIN1 : MOV AX, [SI] JL PRI XCHG [SI +2] , AX XCHG [SI], AX PRI :

ADD SI, 02


LOOP AGAIN 1 DEC DX JNZ AGAIN MOV AH, 4CH INT 2, H CODE ENDS END START

6.

Writ Wr itee a prog progra ram m for for the the add addit itio ion n of of two two 3 x 3 mat matri rice cess :

Solution : In the addition of two matrices the corresponding elements are added to form

the corresponding elements of the result mea trine as shown

a1

a2

a3

a4

a5

a6

a7

a8

a9

+

Program (A)

b1

b2

b3

b4

b5

b6

b7

b8

b9

+

(B)

=

=

a1+b1 a2 a2 +b2

a3 +b3

4 + b4 a5+b5

a6 +a6

7+ b7

a9 + b9

a8 + b8

(A + B)

ASSUME CS : CODE , DS : DATA DATA SEGMENT DIM

EQ V

09 H

MAT 1 DB 01H, 02H, 03H, 04H, 05H, 06H, 07H, 08H, 09H MAT 2 DB 01H 02H, 03H, 04H, 05H, 06H, 07H, 08H, 09H RMAT3 DW 09H DUP (?) DATA ENDS CODE SEGMENT START : MOV AX, DATA MOV DS, AX MOV CX, DIM MOV SI, OFFSET, MAT 1 MOV DI, OFFSET, MAT 2 MOV BX OFFSET, RMAT 3


NEXT:

XOR AX , AX MOV AL, [SI] ADD AL, [DI] MOV WORD PTR [B X] , A X INC SI INC DI

ADD BX , 02 LOOP NEXT MOV AH, 4CH INT 21H CODE ENDS END START

7.

Writ Wr itee a progr program am to to move move a str strin ing g of data data wor words ds fro from m offs offset et 200 200H H to off offse sett

3000H the length of the string in OFH

ASSUME CS : CODE , DS : DATA DATA SEGMENT SOURCESTR EQU 2000 H DESTSTR

EQU 3000 H

DE STSTR EQU OFH DATA ENDS CODE SEGMENT START:

MOV AX, DATA MOV DS , A X MOV ES , A X MOV SI , SOURCESTR MOV DI , DESTSTR MOV C X , COUNT CLD

REP

MOVSW MOV AH, 4CH


INT 21 H CODE ENDS END START

8.

String Comparison :

The CMPS instruct instruction ion can be used to compare compare two strings strings of bytes bytes or words. The length of the string must must be stored in in the register CX. If the the both the byte or word strings are equal , zero flag is set , the flags are affected in the same way as CMP instruction. The DS:SI and ES:DI point to the two strings. The REP instruction prefix is used to repeat the operation till CX becomes zero.

ASSUME CS : CODE, DS : DATA DATA SEGMENT STR1 DB “ GOOD” , ‘$’ VAR1 DB “ NOT EQUAL” , ‘$’ VAR2 DB “ EQUAL” , ‘$’ COUNT EQU 03H DATA ENDS EXTRA SEGMENT STR 2 DB “ MORNING” , ‘$’ EXTRA ENDS CODE SEGMENT START : MOV A X, DATA MOV DS, A X MOV A X, EXTRA MOV ES, A X

MOV SI, OFFSET STR 1 MOV DI, OFFSET STR 2 MOV CX COUNT CLD


REPE VMPSW JZ L1 MOV DX,OFFSET VAR2 JMP L 1 L1:

MOV AH, 09 H INT 21 H MOV AH, 4C H INT 21 H

CODE ENDS END START

Chapter 3 : Intel 8086 2.17.1 2.17.1 DOS/ DOS/ BIOS BIOS Syste System m calls calls A.

Readin ding a charac racter fro from keyboa board

Reads a character character from the standard standard input device device and echoes it to the standard standard output device . If no character is ready , waits until one is available Calling Parameter AH = 01H ASSUME CS : CODE, DS : DATA CODE SEGMENT START : MOV MOV AL, 00H MOV AH, 01 H INT 21 H CODE ENDS END START B.

Display string :

Sends a string of characters characters to the standard output device. End of string is is indicated by character $ (24 H) Calling Parameter AH = 09H ASSUME CS : CODE, DS : DATA DATA SEGMENT STR 1 DB “ WELCOME” , ‘$’ DATA ENDS CODE SEGMENT START :

MOV A X, DATA MOV DS, D X MOV DX, OFFSET STR 1 MOV AL, 00H MOV AH, 09 H INT 21 H

CODE ENDS END START

Chapter 3 : Intel 8086 2.17 2.17..

2 Dis Disk k ope opera rati tion onss

a)

Create file :

Create a new file in the designated or default directory on the designated or default disk drive . If the specified file already exists, it is truncated to zero length.In either case, the file in opened and a handle is returned that can be used by the program for subsequent access to the file . Calling parameters : AH = 3CH DS : DX = segment : offset of ASCII path path name Source :

ASSUME CS : CODE , DS DS : DATA DATA STR 1 DB “ CREATED” CREATED” ,“$” STR 2 DB “ NOT CREATED” , “$” FNAME DB ‘H : \ IT 228 \ S. ASM ‘ 0 FHANDLE DW P( P( ? ) DATA SEGMENT START :

MOV AX, DATA MOV DS, A X MOV AH, 3CH XOR CX, CX MOV D X, SEG FNAME MOV DS, D X MOV DX, OFFSET FNAME INT 21 H JC ERROR MOV FHANDIE, AX MOV DX, OFFSET STR 1 MOV AH, 09H INT 21 H MOV AH, 4CH INT 21 H


ERROR : MOV DX, OFFSET STR 2 MOV AH, 09H IN 7 21 H MOV AH, 4CH IN 7 21 H CODE ENDS END START b) Delete file

Deletes a file from the specified or default and directory Calling parameters AH = 41 H DS : DX = Segment : offset of ASCII pathname Returns : if function successful carry flag = clear if function successful carry flag = set AX = error code Source :

ASSUME CS CODE , DS DATA DATA SEGMENT STR 1 DB “SUCCESSFUL” $” STR 2 DB “ UNSUCCESSFUL” $” FNAME DB ‘H : / IT 228/ A. ASM ‘, 0 DATA ENDS CODE SEGMENT START :

MOV A X, DATA MOV DS, A X MOV AH, 41 H MOV DX, SEG FNAME MOV DS, D X MOV DX, OFFSET FNAME


INT 21 H JC ERROR MOV DX, OFFSET STR1 MOV AH, 09 H INT 21H MOV AH, 4CH INT 21 H ERROR : MOV DX, OFFSET STR2 MOV AH, 09 H INT 21 H MOV AH, 4 CH INT 21 H CODE ENDS END START c)

Rename file :

renames renames a file and / OR moves its directory directory entry entry to a different different directory directory on the same disk. In Ms- Dos version 3. 0 and later this function can also be used rename directors . calling parameter AH = 56 DS : segment : offset of current path ES : D1 segment offset of new path Returns : if if function function successful successful carry flag = clear if function successful carry flag = set AX = error code Source :

ASSUME CS : CODE, DS : DATA, ES: EXTRA DATA SEGMENT STR 1 DB “ RENAMED ““$”


OLDNAME DB ‘H : / IT228/ S. ASM’, 0 NEWNAME DE’H’: /IT228/ A. ARM ‘, 0 DATA ENDS EXTRA SEGMENT STR 2 DB “ NOT RENAMED”, “$” EXTRA ENDS CODE SEGMENT START :

MOV AX, DATA MOV AH, 56 H MOV D X, SEG OLDNAME MOV DS, DX MOV DX, OFFSET OLDNAME MOV DI, SEG NEW NAME MOV ES, DI MOV DI, OFFSET NEWNME INT 21 H JC ERROR MOV DX, OFFSET STRI MOV AH, 09 H INT 21 H MOV AH, 4CH INT 21 H

ERROR : MOV DX, OFFSET STR2 MOV AH, 09 H INT 21 H MOV AH, 4 CH INT 21 H CODE ENDS END START

Chapter 3 : Intel 8086 Two Marks Questions And Answer 1. What are the modes in which 8086 can operate?

The 8086 can operate in two modes and they are minimum ( or uniprocessor) mode and maximum ( or multiprocessor) mode. 2 .What are the interrupts of 8086?

Thee inte Th interr rrup upts ts of 8085 8085 are are INTR INTR and NMI. NMI. Th Thee INTR INTR is gene genera rall mask maskab able le interruput and NMI is non-maskable interrupt.. 3. How clock signal is generate generated d in 8086? 8086? What is the maximum maximum internal internal clock frequency of 8086?

Thee 8086 Th 8086 does does not not have have on-c on-chi hip p cloc clock k gener generat atio ion n circ circui uit. t. Henc Hencee the the clock clock generator chip, 8284 is connected to the CLK pin of8086. The clock signal supplied by 8284 is divided by three for internal use. The maximum internal clock frequency of8086 is 5MHz. 4. What is pipelined architecture?

In pipelined architecture the processor will have number of functional units and the execut execution ion time time of functi functional onal units units are overla overlapped pped.. Each Each functi functional onal unit unit works works independently most of the time. 5. What are the functional units available in 8086 architecture?

The bus interface unit and execution unit are the two functional units available in 8086 architecture. 6. List the segment registers of 8086.

The segment registers of 8086 are Code segment, Data segment, Stack segment and Extra segment registers. 7. What is the difference between segment register and general purpose register?

The segment registers are used to store 16 bit segment base address of the four memory segments. The general purpose registers are used as the source or destination register during data transfer and computation, as pointers to memory and as counters. 8. What is queue? How queue is implemented in 8086?

A data structure which can be accessed on the basis of fIrst in fIrst out is called queue. The 8086 has six numbers of 8-bit FIFO registers, which is used for instruction queue.

Chapter 3 : Intel 8086 9. Write the special functions carried by the general purpose registers of 8086.

The special functions carried by the registers of 8086 are the following. Register Special function AX 16-bit Accumulator AL 8-bit Accumulator BX Base Register CX Count Register DX .Data Register 10. Write the flags of 8086.

The 8086 has nine flags and they are

11. What are control bits?

The flags TF, IF and DF of8086 are used to control the processor operation and so they are called control bits. 12. Describe the difference between the instructions MOV AX,2437H and MOV AX, [2437H].

Difference between the instructions MOV AX,2437H and MOV AX,[2437H] are former instruction takes 2437 as 16-bit data and latter instruction takes 2437 as 16-bit address.

Chapter 3 : Intel 8086 13. State the function of Direction flag in 8086.

Direction flag is used with string instructions. If DF= 0, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address. 14. In 8086 processor the code segment contains 4000H and instruction pointer contains 9F20H. Find the memory location addressed by the processor.

Segment address Shifted to left by four bits



4000 0 1 0 0 0 0 0 0 0 0 0 0

0000

0100 0000 0000 0000

0000 +

Offset address

1001

1111 0010 0000

---------------------------------------------------0100 1001

1111 0010 0000

-------------------------------------------------------Physical address

4

9

F

2

0

H

15. Mention the three operating modes of Intel 80386 processor.

i. Real Mode. ii. Protected Mode. iii. Virtual 8086 Mode. 16. Wh What at happen happenss in 8086 8086 proce processo ssor, r, when when a. overfl overflow ow of sum occur occurss du durin ring g additi addition on of signed signed nu numb mber ers. s. b. overf overflow low of qu quoti otient ent occu occurs rs du duri ring ng divisi division on operation.

a. When overflow of sum occurs during addition of signed numbers, overflow flag is set to one (OVF =1). b. When overflow of quotient occurs during division operation, type 0 (divide by zero ) interrupt is generated. 17. Discuss the functions of the following prefixes: LOCK, ESCAPE LOCK :

In a multiprocessor system each microprocessor has its own local buses and memory. The individual microprocessors are connected together by a system bus so that each can access system resources such as disk drives or memory. Each microprocessor only takes control of the system bus when it needs to access some system resources. The LOCK prefix allows a microprocessor to make sure that another processor does not take


control of the system bus while it is in the middle of a critical instruction which uses the system bus. ESCAPE:

This instruction is used to pass instructions to a coprocessor such as the 8087 math coprocessor which shares the address and data bus with an 8086. 18. What are the flag manipulation instructions of 8086.

1. LAHF : Load AH from low byte of flag register. 2. SAHF : Store AH to low byte of flag register 3. PUSHF : Push content of flag to the stack. 3. POPF : Pop content of stack and load it in the flag register. 19.Give the contents of the flag register after execution of following addition.

0110010111010001 + 0010001101011001 1000100100101010 SF = 1, ZF = 0, PF = 1, CF = 0, AF = 0, OF=1. 20. What are the three groups of signals in 8086 ?

The 8086 signals are categorized in three groups. They are : i. The signals having common function in minimum and maximum mode. ii. The signals having special functions for minimum mode , iii. The signals having special functions for maximum mode. 21. What are the uses of AD0 – AD15 lines ?

These These are the time time multip multiplex lexed ed memory memory 15 address address and data data lines. lines. Address Address remains on the line during T I state ,while data is available on the data bus during T2, T3, TW and T4. Here Ti' T2, T3, T4 and Tw are the clock states of a machine , cycle. Tw is a wait state. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. 22 What is the operation of RD signal ?

Read Read signa signall RD when when low, low, indi indica cate tess the the peri periph pher eral alss that that the the proc proces esso sorr is performing a memory (or) I/O read operation.

Chapter 3 : Intel 8086 23. What is the function of READY signal?

This is the acknowledgment from the slow devices (or) memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high. 24.What is the function of INTR signal ?

INTR- Interrupt Request: This is a level triggered input. This is sampled during the last clock cycle of each instruction to determine the availability of the request, If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internall internally y masked masked by resetting resetting he interrupt enable flag. This signal is active active high and 1ternally synchronized. 25. What is the operation performed when TEST .input in low ?

If the TEST input goes low, execution execution will continue, continue, else, the processor remains remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock. 26. What is the purpose of ALE signal in minimum mode?

ALE -Address Latch Enable: This output signal indicates the availability of the valid address on the address / data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. 27. What is the function of RESET pin ?

RESET input causes the processor to terminate the current activity and start execution from FFFFOH. This signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET return low. RESET is also internally synchronized. 28. What is the function of DEN signal in minimum mode ?

This signal indicates the availability of valid data over the address / data lines. It is used to enable the Transceivers to separate the data from the multiplexed address / data signal.It is active from the middle of T2 until the middle of T4 DEN is tristated during hold acknowledge cycle. 29. What are the differences between maximum mode and minimum mode Minimum mode

1 A processor is in minimum mode when MN /MX pin is strapped to +5v


2. All control signals are given out by microprocessor chip it self 3. There is a single micro processor Maximum mode

1. A processor is in maximum mode when MN /MX is is grounded 2. The processor derive the status signals S2, Sl and So. Another chip called bus controller derives control signals using this status information 2. There may be more than one microprocessor 30. What is the fabrication technology used for 8086?

The 8086 is fabricated using the HMOS (High density n-type metal oxide silicon field effect transistors) technology and contains approximately 29,000 transistors. The 8086 packed in a 40 pin DIP and requires a single 5V supply. 31. What is multimicro-processor architecture ?

The maximum clock frequency at which a system operate may be considered as one of the measure of the processor capability of the system. An appropriate system involving several microprocessors connected using a certain topology ma provide high proces processin sing g capacit capacity. y. The study study of such such a syste system m known known as multi multi micro micro proces processor sor architecture. 32. What are the functional parts of simple multi micro processor system ?

The simplest type of multimicr multimicroproces oprocessor sor system is one containing containing a CPU and a numeric data processor (NDP) and/or an Input / Output processor (IOP). 33. Give the interconnection topology classification oj multiprocessor system.

Some Some of the the inter nterco conn nnec ecttion topol opolog ogiies are: are: (Bas (Based ed on he mode mode of communication) i. Shared bus ii. Linked Input I Output iii. Multiport memory Based on the physical interconnections between the processors: i. Star configuration ii. Loop configuration iii. Complete interconnection iv. Regular topologies


v. Irregular topologies. 34. What is the fabrication technology used for 8087 (NDP) ?

Numeric processor packed in a 40 pin ceramic DIP package, it is available in 5MHZ, 8MHZ and 10MHZ versions compatible with 8086, 8088, 80186 and 80188 processors. 35. What is meant by numeric processor ?

The numeric processor 8087 is a coprocessor which has been designed to work under under the control control of the proces processor sor 8086 and offer offer it additi additional onal numeric numeric proces processin sing g capabilities. 36. What are the functional parts of coprocessor ?

The 8087 is divided into two sections internally. They are : i. Control Unit (CU) ii. Numeric Extension Unit (NEU) 37. What is the purpose of control unit ?

The control unit is mainly responsible for establishing communication between the CPU and memory and also for co-coordinating the internal coprocessor execution. 38. What is the function of INT pin in 8087 ?

The interrupt output is used by 8087 to indicate that an unmasked exception has been received during execution. This is usually handled by 8259A. 39. What is the function of busy signal in 8087 ?

This output signal, when high, indicates to the CPU that it is busy with the executi execution on of an allott allotted ed instru instructi ction. on. This This is usuall usually y connect connected ed to the TEST pin of 8086/8088. 40. Give the register classification of 8087.

In 8087 registers are divided into three fields. They are: (i) sign (1 bit) (ii) exponent ( 15 bits) (iii) significant (64 bit) 41. What is the use of instruction and data pointer (8087)?

The instruction and data pointers are used to enable the programmers to write their own exception handling subroutines.

Chapter 3 : Intel 8086 42. What is the. use of control word register (8087) ?

The control word register of 8087 allows the programmer to select the required processing options out of available ones. In other words, the 16-bit control word register is used to control the operation of the 8087. 43. Give the additional instructions supported by 8087.

Thee addit Th additio ional nal inst instru ruct ctio ions ns supp suppor orte ted d by 808 8087 7 can can be cate catego gori rize zed d into into the the following types. i. Data transfer instruction ii. Arithmetic instructions iii. Comparison instructions iv. Transcendental operations v. Constant operations vi. Coprocessor control operation. 44. Give the classification of multimicroprocessor system.

The multimicroprocessor systems are also classified as tightly (closely) coupled or loosely coupled systems, depending upon whether the microprocessor share a common memory and common system bus or not 45. Explain the tightly coupled (closely coupled) system.

In a tigh tightl tly y coup couple led d syst system em.. the the micr microp opro roce cess ssor or (eit (eithe herr copr coproc oces esso sorr or independent processors) may share a common clock and bus control logic The two processors in a closely coupled system may communicate using a common system bus or common memory The microprocessor in a closely coupled system either uses a status bit in memory (or) interrupt the host to inform it about the completion of the task allotted to it Expl Ex plai ain n the the loos loosel ely y coupl coupled ed mult multip ipro roces cesso sorr syst system em In a loos loosel ely y coup couple led d multiprocessor system. on the other hand. Each CPU may have its own bus control logic The bus arbitration is handled by an external circuit. Common to all the processor The loosely coupled system configurations like LAN and WAN can be spreaded over a large area

Chapter 3 : Intel 8086 46. Give the advantage of loosely coupled system over the tightly coupled system.

The loosely coupled system have the following advantage over the tightly coupled system, i. More number of CPUs can be added in a loosely coupled system to improve the system performance. ii. The system structure is modular and hence easy to maintain and troubleshoot. iii. A fault in a single module does not lead to a complete system breakdown. iv. Due to the independent processing modules used in the system, it is more fault -tolerant. v. More suitable to parallel applications due to its modular organization.

Chapter 3 : Intel 8086

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