Exercise 7–1
Ex: 7.1
Refer to Fig. 7.2(a) and 7.2(b).
Coordinates of point A: Vt and VDD ; thus 0.4 V and 1.8 V. To determine the coordinates of point B, we use Eqs. (7.7) and (7.8) as follows:
= −k V R −10 = −0.4 × 10 × V × 17.5 Av
n
OV
D
OV
Thus,
√ = 2k R kV R + 1 − 1 √ × 1.8 + 1 − 1 = 2 × 4 × 417.5 × 17.5 = 0.213 V
VOV
Thus,
=2× × × = R = 17.5 k V = V −R I = 1.8 − 17.5 × 0.04 = 1.1 V
VOV
VGS
and VDS
n
D
B
n
=V +V t
B
=V
OV B
B
DD
D
=k
If v DS
n
(v GS
= 0.4 + 0.213 = 0.613 V
= 0.213 V
C
Vt )v DS
is very small,
C
−
k (v V )v = 4(1.8 − 0.4)v iD
n
GS C
t
DS C
− C
1 2
2
v DS
C
DS C
=But iD
DD
C
DS C
D
n
2 OV
0.4
0.142
10
DS
DD
0.04 mA
D D
Ex: 7.3
= − I VR C
Av
C
T
× R ⇒ R = 8 k −320 = − 10.025 V = V −I R = 10 − 1 × 8 = 2 V C
C
C
CC
C
C
Since the collector voltage is allowed to decrease to 0.3 V, the largest negative swing allowed at the output is 2 0.3 1.7 V. The corresponding input signal amplitude can be found by dividing 1.7 V by the gain magnitude (320 V/V), resulting in 5.3 mV.
−
C
= V −R v
Thus, v DS
ID
OV
+
5.6v DS , mA
t
D
OV B
−
VGS
1
Thus, coordinates of B are 0.613 V and 0.213 V. At point C, the MOSFET is operating in the triode region, thus iD
= 0.14 V = V + V = 0.4 + 0.14 = 0.54 V = 12 k WL V
1.8 VR = 17.5 = 0.1 mA DD D
= 0.1 = 0.018 V = 18 mV, which 5.6
=
Ex: 7.4
5 V
is indeed very small, as assumed.
Ex: 7.2
Refer to Example 7.1 and Fig. 7.4(a).
RD
RG
Design 1:
= 0.2 V, V = 0.6 V = 0.8 mA
VOV ID
vo
GS
vi
Now, Av
k n VOV RD
=−
Thus,
Refer to the solution of Example 7.3. From
−10 = −0.4 × 10 × 0.2 × R ⇒ R = 12.5 k V = V −R I = 1.8 − 12.5 × 0.08 = 0.8 V
D
D
DS
DD
Design 2: RD
= 17.5 k
D D
Eq. (7.47), Av
≡ vv = −g
is absent).
o
m RD
(note that RL
i
Thus, gm RD
= 25
Substituting for gm k n VOV RD
= 25
=k V n
OV ,
we have
Exercise 7–2
where k n VOV RD
2
= 1 mA/V , thus
= 25
t
t
o
o
( 1) ∴
Next, consider the bias equation
= V = V −R
VGS
= vr + i = vr + g
it
DS
DD
Req
mv t
= vi = r g1 t
o
t
m
D ID
Thus,
Ex: 7.6
+V = V −R I Substituting V = 0.7 V, V = 5 V, and Vt
OV
DD
D D
t
1 ID
2 OV
n
VDD
DD
1
1
2 OV
2 OV
= 2k V = 2 × 1 × V = 2V
iD
we obtain 1
+V = 5− 2
0.7
OV
2 VOV RD
(2)
vDS
vgs
Equations (1) and (2) can be solved to obtain VOV
RD
= 0.319 V
vGS
and
VGS
= 78.5 k
RD
The dc current ID can be now found as ID
= 12 k V = 50.9 2 OV
n
µA
m
D
2
µ
n
G
D
G
ˆ
Finally, the maximum allowable input signal v i can be found as follows:
ˆ = |A V| + 1 = 250.7+V1 = 27 mV t
vi
VGS t
RG
= 1+g R R 0.5 M = 1 + 25 ⇒ R = 13 M Rin
=5V =2V V =1V λ=0 k = 20 A /V R = 10 k W = 20 L (a) V = 2 V ⇒ V = 1 V 1 W I = k V = 200 A 2 L V = V − I R = +3 V W (b) g = k V = 400 A/V = 0.4 mA/V L VDD
To determine the required value ofRG we use Eq. (7.48), again noting that RL is absent:
GS
D
v
n
DS
Ex: 7.5
OV
2 OV
DD
m
D
i
= v = −g R = −4 V/V (d) v = 0.2sin ωt V v = −0.8sin ωt V = V + v ⇒ 2.2 V ≤ v ≤ 3.8 V v
vt
i
DS
ds
DS
(e) Using Eq. (7.28), we obtain iD
= 12 k (V − V ) + k (V − V )v + 12 k v = 200 + 80sin ωt + 8sin ωt , A n
GS
n
S
D
ds
G 1 gm
m
gs
DS
ro
µ
OV
n
gs
0
D
v ds
(c) Av it
Req
D
µ
iD
GS
2
2
t
t
µ
gs
n
2 gs
Exercise 7–3
16 = 12 × 60 × 0.8 × (1.6 − 1) I = 216 A 2I 2 × 216 g = |V | = 1.6 − 1 = 720 A/V = 0.72 mA/V 1 1 = 0.04 = 25 V/ λ = 0.04 ⇒ V = λ V ×L r = = 25 × 0.8 = 92.6 k
= [200 + 80sin ωt + (4 − 4 cos2 ωt)] = 204 + 80sin ωt − 4cos2 ωt, A
2
µ
D
µ
m
Thus, 2HD
µ
D
ID shifts by 4 µA.
OV
ˆ = iˆ = 804 2ω
µA µA
iω
= 0.05 (5%)
µm
A
Ex: 7.7
A
o
0.216
ID
D
= V2 I
(a) gm
OV
ID ID gm ro
1
= 2 L V = 12 × 60 × 40 × (1.5 − 1) = 300 A = 0.3 mA, V = 0.5 V = 2 ×0.50.3 = 1.2 mA/V W
k
2
2 OV
n
µ
OV
15 = VI = 0.3 = 50 k
(b) ID
= 0.5 mA ⇒ g =
=
× 60 × 40 × 0.5 × 10
gm
2
2 µ n Cox
W
=
gm
A
A
D
OV
A
A
m o
Ex: 7.12
3
Given: gm
= ∂∂iv
C
BE iC
VA
15
ID
= 0.5 =
30 k
where IC ∂iC ∂v BE
Ex: 7.8
ID
D
OV
ID
L
= 1.55 mA/V
ro
= V2 I × VI = V2V V × L = V 2 × 12.5 × 0.8 L = 0.8 m ⇒ g r = 0.2 = 100 V/V gm ro
µ
A
D
m
Ex: 7.11
= 0.1 mA, g = 1 mA/V, k = 50 = V2 I ⇒ V = 2 ×10.1 = 0.2 V m
n
µA /V
2
= = I eV S
VBE /VT T
= IC
= VI
C T
Thus, gm
D
IS e
VBE /VT
= VI
C T
OV
OV
= 12 k WL V ⇒ WL = k 2VI = 502 × 0.1 = 100 × 0.2 1000 ID
2 OV
n
n
D 2 OV
Ex: 7.13
gm
mA = VI = 0.5 = 20 mA/V 25 mV C
T
2
Ex: 7.14 Ex: 7.9
gm
=µ C n
W ox
L
β
Same bias conditions, so same VOV and also same L and gm for both PMOS and NMOS. µn Cox Wn
=µ C p
ox Wp
⇒ µµ = 0.4 = WW
⇒ W = 2.5 n
=2
n
n
p
T
C
µ
Ex: 7.10
ID
p
C
m
B
Wp
1
= 0.5 mA ( constant) = 50 β = 200 g = I = 0.5 mA V 25 mV = 20 mA/V = 20 mA/V I 0.5 I = = 0.5 = 200 50 β = 10 A = 2.5 A 50 β = 20 = 200 r = g 20 = 2.5 k = 10 k IC
VOV
k
p
π
W L
m
(VSG
− |V |) t
2
µ
Exercise 7–4
Ex: 7.15
= 100 I = 1 mA 1 mA g = = 40 mA/V 25 mV β
ic
= βi = β vr
=
ie
= i + βi = (β + 1)i = (β + 1) vr
C
m
re
mV = VI = αVI 251 mA = 25 T
T
E
rπ
C
β
v be
rπ
π
=g
m v be
be
b
=r
= gβ = 100 = 2.5 k 40
be
b
b
b
v be
+ 1) =
π (β
π
v be
re
m
Ex: 7.18 Ex: 7.16
gm
C
= VI = 251 mA = 40 mA/V mV C
T
= vv = −g R = −40 × 10 = −400 V/V V = V −I R = 15 − 1 × 10 = 5 V v (t ) = V + v (t ) = (V − I R ) + A v (t ) = (15 − 10) − 400 × 0.005 sin ωt = 5 − 2sin ωt i (t ) = I + i (t ) ce
Av
m
C
gmvbe
be
C
CC
C
C
C
CC
B
re
C
vbe
E
C
B
be
v
ib
be
=v
be
=v
be
b
mA = Iβ = 1100 = 10 C
and ib (t )
= vr − g
=g
m v be
e
where IB
c
C
B
ib
µA
=v
be
1 re
−g 1
rπ/β +1 β
m v be (t )
m
− rβ
π
+1 − β = v r r r π
π
be π
β Ex: 7.19
ωt = × 0.005sin 100 = 2sin ωt, A
40
10
V
µ
Thus, iB (t )
= 10 + 2sin ωt ,
RE 10 k
µA
CC1
Ex: 7.17 vi
ib
ic
B
CC2
C
vo
vbe
bib
rp
RC 7.5 k
E
10 V
Exercise 7–5
IE IC
= 10 −100.7 = 0.93 mA = αI = 0.99 × 0.93
= −0.1 − 0.7 = −0.8 V I 0.99 (b) g = = 0.025 40 mA/V V VE
C
m
E
T
= 0.92 mA V = −10 + I R = −10 + 0.92 × 7.5 = −3.1 V v = αrR A = v C
C
o
= g = 100 2.5 k 40 β
rπ
C
m
=
ro
C
v
i
where re
m
= 0.93 mA = 26.9 × 7.5 × 10 = 276.2 V/V A = 26.9 For vˆ = 10 mV, vˆ = 276.2 × 10 = 2.76 V
= = 8 k R = 8 k V = VV × VV V
RC
3
v
i
π
B
40 mA/V
g
0.99
IC
(c) Rsig
e
25 mV
100 = 0.99 = 101 100 k = 2 k R = 10 k r = 2.5 k
VA
L
π
y
sig
π
y
sig
o
ro
= 100 k
RB rπ
= (R r ) + R × −g (R R r ) 2.5 × −40(8 8 100) = (1010 2.5 )+2 −0.5 × 40 × 3.846 = −77 V/V V If r is negelected, = −80, for an error V
Ex: 7.20
B
10V
8 k
m
C
L
o
sig
π
y
o
sig
of 3.9%.
Y X
Ex: 7.21
10 k
D
0.25 = 2 mA/V = V2I = 2 ×0.25 R =∞ A = −g R = −2 × 20 = −40 V/V R = R = 20 k R A =A = −40 × 20 20 R +R + 20 = −20 V/V G = A = −20 V/V vˆ = 0.1 × 2V = 0.2 × 2 × 0.25 = 0.05 V vˆ = 0.05 × 20 = 1 V
Z
gm
OV
I 1 mA
in
vo
IE IC
m
o
D
v
vo
D
L
= 1 mA = 100 × 1 = 0.99 mA 101
L
1 = 101 × 1 = 0.0099 mA (a) V = 10 − 8 × 0.99 = 2.08 2.1 V V = −10 × 0.0099 = −0.099 −0.1 V
v
IB
v
i
C
o
OV
o
B
This figure belongs to Exercise 7.20c. Rsig
X
Y
Vsig
Vy
Vp RB
rp
gmVp
Z
ro
RC
RL
Exercise 7–6
Ex: 7.22
IC gm
= 0.5 mA 0.5 mA = VI = 0.025 = 20 mA/V V C
rπ
ˆi ˆi /(b 1) b e
Rsig
T
= gβ = 100 = 5 k 20 = r = 5 k = −g R = −20 × 10 = −200 V/V m
Rin
π
Av o
m
Ro
ˆi vˆ r p e e
ˆp v
re
C
ˆ
vsig
E
C
k = R = 10 R = −200 × 5 +5 10 A =A R +R = −66.7 V/V 5 R × −66.7 G = A = 5+5 R +R = −33.3 V/V vˆ = 5 mV ⇒ vˆ = 2 × 5 = 10 mV vˆ = 10 × 33.3 = 0.33 V
Re
L
vo
v
L
o
in
v
v
in
sig
VT
sig
π
= 0.5 mA and β = 100, = αVI = 0.990.5× 25 50 r = I r = (β + 1)r 5 k For vˆ = 100 mV, R = 10 k and with vˆ For IC
E
o
e
sig
Refer to the solution to Exercise 7.21. If
ˆ = 0.2 V and we wish to keep vˆ = 50 mV, 3 then we need to connect a resistance R = in g gs
s
m
the source lead. Thus,
D
= 10 1 + R50 + 105 e
L
v
⇒ R = 350 R = (β + 1)(r + R ) = 101 × (50 + 350) = 40.4 k R R G = −β R + (β + 1)(r + R ) e
e
in
e
C
= 2 mA3 /V = 1.5 k R R G =A =− 1 +R g = − 0.520+201.5 = −5 V/V = 5 × 0.2 = 1 V (unchanged) vˆ = G vˆ Rs
v
sig
L
v
e
sig
10
o
sig
v
Ex: 7.25
1
= R = 100 sig
gm
⇒ g = 0.11k = 10 mA/V m
But
Ex: 7.24
From the following figure we see that
ˆ = ˆi R + vˆ + ˆi R = β i+ 1 R + vˆ + ˆi R = (β +vˆ 1)r R + vˆ + vrˆ R vˆ = vˆ 1 + Rr + Rr v sig
b
sig
π
e
sig
π
e
e
sig
sig
e
π
π
= 20.2I ⇒ I = 1 mA R ×g R G = R +R = 0.5 × 10 × 2 = 10 V/V D
in
e
e
D
OV
D
π
π
sig
e
= V2I
10
e
π
gm
Thus,
e
e
m
v
in
Q.E.D
e
= −100 10 + 101 × 0.4 = −19.8 V/V
s
m
π
limited to 10 mV, the value of Re required can be found from 100
v sig
C
π
Although a larger fraction of the input signal reaches the amplifier input, linearity considerations cause the output signal to be in fact smaller than in the srcinal design!
Ex: 7.23
T
e
sig
D
Exercise 7–7
1
Ex: 7.26
= 200 ⇒ g = 5 mA/V gm
= 1 mA V mV VI = 251 mA = 25 r = I R = r = 25 A = g R = 40 × 5 = 200 V/V R = R = 5 k IC
T
m
T
But
e
E
C
vo
m
o
C
RL
Av o
200
L
5
o
in
v
in
sig
Ex: 7.27
= r = 50 ⇒ I = Vr = 2550mV = 0.5 mA I I = 0.5 mA R R G = r +R R R 40 = Rin
e
T
e
ID
= 12 k WL V
L
2 OV
n
= 12 × 0.4 × 50 × 0.25 = 0.625 mA R = 1 k to 10 k
2
L
Correspondingly, Gv
= R R+ R = R R+ 0.2 L
L
E
C
VOV
⇒ WL = 50
E
C
L
= 0.4 × WL × 0.25
5 100 V/V
= RR + R = × 5 + 5 = = R +R ×A = 25 +255000 × 100 = 0.5 V/V Gv
W
n
Thus,
C
Av
= k
gm
e
in
L
o
L
will range from
v
e
sig
C
(50
50)
= +4 k
RC RL
Ex: 7.28 Refer
m
= V2I
D
= 10 ×20.25 = 1.25 mA L
ˆ = vˆ × R R+ R = 1 × 1 +10.1 = 0.91 V i
L
ˆ = vˆ
gm i
1 gm
Ex: 7.29
= 200
e
Gv o
+R
L
= 1 × 0.10.1+ 1 = 91 mV
Rout
L
= 1 V/V = r + βR+ 1 sig
e
= 5 + 10,000 = 104 101 R = R + r + βR+ 1 R + R 1 = 1 + 0.104 = 0.91 V/V Gv
Ro
L
o
1
v gs
T
C
in
Thus,
vo
T
E
sig
OV
ID
= 5 mA V mV VI = 255 mA =5 r = I R = 10 k R = 1 k R = (β + 1) (r + R ) = 101 × (0.005 + 1) = 101.5 k IC e
But gm
= 10 +100.2 = 0.98 V/V
Ex: 7.30
= 100 ⇒ g = 10 mA/V
gm
= 1 +10.2 = 0.83 V/V
to Fig. 7.41(c).
Thus, 1
to Gv
= 100
Ro
Gv
L
=
L
RL
L
sig
e
L
out
Exercise 7–8
re
=v
vπ
sig
VS
+ R + βR+ 1 vˆ = vˆ 1 + Rr + (β +R 1) r sig
re
L
sig
VD
RG should be selected in the range of 1 M to 10 M to have low current.
sig
L
π
e
e
10,000 ˆ = 5 1 + 1000 + 101 5 × 5 = 1.1 V/V
v sig
Correspondingly,
Ex: 7.33
= 0.5 mA = 12 k WL V
ID
ˆ = G × 1.1 = 0.91 × 1.1 = 1 V
vo
= −5 + 6.2 × 0.49 = −1.96 V = 5 − 6.2 × 0.49 = +1.96 V
v
n
2 OV
= 0.5 1× 2 = 1 = 1V ⇒V = 1+1=2V − 2 = 6 k ⇒ R = 5 0.5 = 6.2 k (standard value). For this R
2 OV
Ex: 7.31
= 12 k WL (V − V )
ID
GS
n
t
1
OV
2
D
2
= 2 × 1(V − 1) ⇒V =2V If V = 1.5 V, then 1 I = × 1 × (2 − 1.5) = 0.125 mA 2 I ⇒ = 0.125 − 0.5 = −0.75 = −75% 0.5
GS
⇒V ⇒V =V ⇒R
D
D
0.5
ID
D
= 12 × 1 × (V − 1)
ID
GS
t
2
D
we
have to recalculate ID :
GS
D
GS
2
= 12 (V − R I − 1) (V = V = V − R I ) 1 I = (4 − 6.2 I ) ⇒ I ∼ = 0.49 mA 2 V = 5 − 6.2 × 0.49 = 1.96 V DD
GS
2
D D
D
DD
D
D
D D
2
D
D
Ex: 7.32
RD
− 2 = 6 k = V I− V = 5 0.5 DD
D
Ex: 7.34 Refer
D
→ R = 6.2 k 1 W 1 I = k V ⇒ 0.5 = × 1 × V 2 L 2 ⇒V =1V ⇒V = V +V = 1+1=2V ⇒ V = −2 V V −V R = = −2 −0.5(−5) = 6 k I → R = 6.2 k If we choose R = R = 6.2 k , then I D
n
2 OV
IE
= =
OV GS
OV
IE
SS
D
D
will
change slightly:
= 12 × 1 × (V − 1) . Also V = −V = 5 − R I 2 I = (4 − 6.2 I ) ⇒ 38.44 I − 51.6 I + 16 = 0 ⇒ I = 0.49 mA, 0.86 mA I = 0.86 results in V > 0 or V > V , which is not acceptable. Therefore I = 0.49 mA and ID
2
GS
GS
S
D
S D
D
2 D
2
2 D
D
D
S
S
D
G
BE
1
2
= 100 and − 0.7 = 40 80 = 1.01 1 mA 3+ 4
= 50, 4 − 0.7 = 0.94 mA I = 40 80 3 + 51 For β = 150, 4 − 0.7 = 1.04 mA I = 40 80 3+ 151 For β
S
S
= 80 k, and
101
S
D
−V + Rβ + R1
VBB RE
=
For the nominal case, β
t
S
S
=
(a) For design 1, RE 3 k , R1 R2 40 k . Thus, VBB 4 V.
D
2 OV
to Example 7.12.
E
E
Thus, IE varies over a range approximately 10% of the nominal value of 1 mA.
=
=
(b) For design 2, RE 3.3 k , R1 8 k , and 4 k . Thus, VBB 4 V. For the nominal R2 case, β 100 and
=
=
=
Exercise 7–9
− 0.7 = 0.99 1 mA 4 8 3.3 + 101 For β = 50, 4 − 0.7 I = = 0.984 mA 4 8 3.3 + 51 For β = 150, 4 − 0.7 I = = 0.995 mA 4 8 3.3 + 151 IE
4
=
To maintain active-mode operation at all times, the collector voltage should not be allowed to fall below the value that causes the CBJ to become forward biased, namely, 0.4 V. Thus, the lowest possible dc voltage at the collector is 0.4 V 2V 1.6 V. Correspondingly,
−
−
E
+
=+
= 10 −I 1.6 101 −mA1.6 = 8.4 k
RC
C
E
Ex: 7.36
Thus, IE varies over a range of 1.1% of the nominal value of 1 mA. Note that lowering the resistances of the voltage divider considerably decreases the dependence on the value ofβ , a highly desirable result obtained at the expense of increased current and hence power dissipation.
E
to Fig. 7.54. For I = 1 mA and = 2.3 Refer V, V −V I = R 10 − 2.3 1= VC
CC
C
E
C
RC
⇒ R = 7.7 k C
Now, using Eq. (7.147), we obtain Refer to Fig. 7.53. Since the circuit is to be used as a common-base amplifier, we can dispense with RB altogether and ground the base; thus RB 0. The circuit takes the form shown in the figure below. Ex: 7.35
=
10 V
−V + β R+ 1 10 − 0.7 1= R 7.7 + 101 ⇒ R = 162 k IE
=
VCC
BE B
RC
B
B
Selecting standard 5% resistors (Appendix J), we use RC
= 160 k
RB vo
and
RC
= 7.5 k
The resulting value of IE is found as IE
=
10 7.5
− 0.7 = 1.02 mA + 160 101
and the collector voltage will be RE
vi
= V − I R = 2.3 V
VC
CC
IE
= 5 −R
= 1mA,
D
S
D
VDD
E
D
D
E
To obtain VOV , we use
E
vo vi
=g
m RC ,
where gm
= VI = C
T
40 mA/V. To maximize the voltage gain, we select RC as large as possible, consistent with obtaining a 2-V signal swing at the collector.
±
D
DD
RD
1 mA
The voltage gain
to Fig. 7.55(b).
= 3.5 and I = 0.5 mA; thus = VI = 3.5 = 7 k 0.5 = 15 V and V = 6 V; thus 15 − 6 = V I− V = 0.5 = 18 k mA
RS
VBE
= 5 −R 0.7 ⇒ R = 4.3 k
C
Ex: 7.37 Refer
5V
VS
To establish IE
E
ID
= 12 k V n
2 OV
= 12 × 4V ⇒ V = 0.5 V
2 OV
0.5
OV
Exercise 7–10
Thus, VGS
Ex: 7.40 Refer
= V + V = 1 + 0.5 = 1.5 V t
= V + V = 3.5 + 1.5 = 5 V S
5V
=2
µA
= 2.5 M
= 210 VA = 5 M
= V2I = 2 ×0.50.5 = 2 mA/V D
gm
OV
ro
= β I+ 1 0.5100mA = 5 E
IB
µA
The current through RB1 is
= I + I = 5 + 50 = 55 B
RB2
µA
Since the voltage drop across RB1 is VCC VB 10 V, the value of RB1 can be found from
− =
µ
This completes the bias design. To obtaingm and ro , we use
= 0.055 VmA = 100 k
The base current is
IRB1
The voltage drop across RG1 is 10 V, thus RG1
RB2
GS
Using a current of 2 µA in the voltage divider, we have RG2
= 5 V and
OV
We now can obtain the dc voltage required at the gate, VG
to Fig. 7.56(a). For VB 50-µA current through RB2 , we have
RB1
10 V = 0.055 = 182 k A µ
The value of RE can be found from
= V −R V ⇒ R = 5 − 0.7 = 8.6 k B
IE
BE
E
= VI = 100 = 200 k 0.5 A
E
D
0.5
The value of RC can be found from Refer to Fig. 7.55(a) and (c) and to the values found in the solution to Exercise 7.37 above. Ex: 7.38
Rin Ro Gv
5 2.5
RG1 RG2
1.67 M
==16.5 k == R r = 18= 200 = − R R+ R g (r R R ) D
o
m
o
D
L
sig
= − 1.671.67 + 0.1 × 2 × (200 18 20) = −17.1 V/V Ex: 7.39 To
reduce v gs to half its value, the unbypassed Rs is given by
= g1
From the solution to Exercise 7.37 above, gm 2 mA/V. Thus Rs
= = 12 = 0.5 k
gm
0.5 mA = VI 0.025 = 20 mA/V V
rπ
= gβ = 100 = 5 k 20
C
T
m
ro
=
VA IC
100 = 200 k 0.5
Refer to Fig. 7.56(b) and to the solution of Exercise 7.40 above. Ex: 7.41
= R R r = 182 100 5 = 4.64 k R = R r = 18 200 = 16.51 k R G =− g (R R r ) R +R o
B1
C
B2
π
o
in
D
in
C
C
m
in
sig
C
L
o
sig
= − 4.644.64 + 10 × 20 × (18 20 200) = −57.3 V/V Gv
= − R R+ R × − R1 R +R g 18 20 = − 1.671.67 + 0.1 × 0.5 + 0.5 = −8.9 V/V in
C
v
Neglecting ro , Gv is given by Gv
C
This completes the bias design. The values ofgm , rπ , and ro can be found as follows:
Rin
m
CC
6
in
in
Rs
= V −I R = 15 − 0.99 × 0.5 × R R 18 k VC
L
s
m
Refer to the solutions of Exercises 7.40 and 7.41 above. With Re included (i.e., left unbypassed), the input resistance becomes [refer to Fig. 7.57(b)] Ex: 7.42
Exercise 7–11
= 50 50+50 × 20(8 8) = 40 V/V = 40 × 10 mV = 0.4 V vˆ = 40 vˆ
= R R [(β + 1)(r + R )]
Rin
B1
B2
e
e
Thus,
= 182 100 [101(0.05 + R )] V where we have substituted r = = I 10
e
sig
o
T
e
E
25
Re
= 67.7
= −α R R+ R rR + RR 10 18 20 G = −0.99 × 10 + 10 0.05 + 0.0677 = −39.8 V/V in
Gv
in
C
e
sig
Ex: 7.43 Refer
= −1.7 I− (−5) = 13.3 = 3.3 k mA R = R [(β + 1)[r + (R r R )] V V = 100 = 100 k where r = I 1 mA R = 100 (100 + 1)[0.025 + (3.3 100 1)] = 44.3 k RE
to Fig. 7.58. e
E
E
in
e
T
= 5 V, we have
vo vi
−
Gv
= R R+ R in
in
gm (RC RL ) sig
0.469 V/V
= R + R = 44.3 + 50 = = r +R(R rrR R ) = 0.968 V/V in
sig
E
e
o
E
L
o
L
vo
sig
To obtain the required value of RE , we note that the voltage drop across it is(VEE VBE ) 4.3 V. Thus,
= 4.3 = 8.6 k 0.5
L
≡ v = 0.469 × 0.968 = 0.454 V/V R +R R = r R r + 100β +501 = 100 3.3 0.025 + 101 = 320 Gv
C
44.3
Rin
vi
v sig
C
RE
o
C
E
= = 5 − R × 0.5 ⇒ R = 8 k 1
E
in
E
−
e
o
E
=
B
A
e
VC VCC RC IC For VC 1 V and VCC
= 0.011 VmA = 100 k
The result is a base voltage of –1 V and an emitter voltage of –1.7 V. The required value of RE can now be determined as
= 50 = r R r V r = 50 = I ⇒ I = 0.5 mA I = α I I = 0.5 mA Rin
0.01 mA. For a dc voltage
drop across RB of 1 V, we obtain RB
e
1
IE
= β + 1 = 101
L
v
E
=
IB
The overall voltage gain can be found from
C
Refer to Fig. 7.59. Consider first the bias design of the circuit in Fig. 7.59(a). Since the required IE 1 mA, the base current Ex: 7.44
=
50 . The value of Re is found from the 0.5 equation above to be
=
B
out
o
E
e
sig
Chapter 7–1
7.1 Coordinates of point A: v GS and v DS VDD 5 V.
=
=
= V = 0.5 V t
To obtain the coordinates of point B, we first use Eq. (7.6) to determine VGS B as
√ + 2k R kV R + 1 − 1 √ = 0.5 + 2 × 10 ×1020× ×205 + 1 − 1 = 0.5 + 0.22 = 0.72 V VGS
=
n
Vt
B
D
= − = = = = = = ×× = − VGS
B
7.2 VDS
Vt
B
VOV
B
VOV
B
1
B
2
1
2
k n VDS
B
VDD
0.22 V
0.52
5
2
VDD
VDS
ID
|A
max
= 0.625 mA
OV B
B
Av
k n VOV
B
DS
= 12 k V
2 OV
56VOV
= 2 × 10 × 0.04 = 0.2 mA V −V R = = 5 − 1 = 20 k DS
IDQ
0.2
Coordinates of point B: Equation (7.6): n
D
D
OV Q
Q
= Q
12
56
= 0.214 V
− =− − − =− ⇒ =
To obtain the required VDS
VDD
Av
1
VDS
VOV
2
12
VDS
Q
Q
VDS
Q
0.214/2
Q
0.714 V
+1−1
n
VDD
D
iD RD v
Equations (7.7) and (7.8):
VDS
=√
2k n RD VDD
B
k n RD
+ 1 − 1 = 0.22 V
= −k R V = −10 × 20 × 0.2 = −40 V/V
Av
n
D
OV
, we use Eq. (7.17),
7.5 D VDD
t
B
Q
/2
=V + k R √2 × 10 × 20 × 5 + 1 − 1 = 0.5 + 10 × 20 = 0.5 + 0.22 = 0.72 V
VGS
RD
D
=− Thus, VOV
= 0.2 V and V = 1 V.
B
−14 = −k R × 0.25 ⇒ k R = 56 To obtain a gain of −12 V/V at point Q: −12 = −k R V
k
√ 2k R
B
n
twice the the value of n , then IDofBRwill be twice as large and required value D will be half that used before, that is, 3.6 k.
D
/2
0.25 V
n
If the transistor is replaced with another having
DD
B
Thus,
n
− 0.5 = 7.2 k = 0.625
n
OV B /2
Now, using Eq. (7.15) at point B, we have
5
IDQ
B
⇒ = =− VOV
B
7.3 Bias point Q: VOV
VOV
|= V− 2−V 14 = v
VOV
The value of RD required can now be found as
RD
=
7.4 From Eq. (7.18):
Thus,
ID
= −
v
0.5 V
B
−
v gs
D
The vertical coordinate of point B is VDS B ,
VDS
=
V 0.78 ˆ = 0.78 | A | = 40 = 19.5 mV
DD
n
The lowest instantaneous voltage allowed at the output is VDS B 0.22 V. Thus the maximum allowable negative signal swing at the output is VDSQ 0.22 1 0.22 0.78 V. The corresponding peak input signal is
vgs
VGS
DS
Chapter 7–2
W
= 5 V, = 24 k,
VDD RD
kn
= 1 mA V =1V
Vt
= 20 k = 200 A/V = 1.5 V = 0.7 V = −10 V/V = −k V R = I R = 12 k V
7.6 RD
2
L
kn
2
µ
VRD
(a) Endpoints of saturation transfer segment:
VGS Point A occurs at VGS Point A
= V = 1 V, i = 0 t
D
= (1 V,5 V ) ( V
GS , VDS
Av
Point B occurs at sat/triode boundary ( VGD
VGD
1V
V GS
VGS
= ⇒ − 5 + 12
2 12VGS
iD RD ]
[5
− −
(1)(24) [ VGS
Av
)
=V ) t
2
GS
D
DS
GS
t
GS
D
n
GS
t
= 12 × 1(1.5 − 1) ID
OV
iD
OV
OV
GS
OV
v
n
OV
D
2
2
n
∴
n
W
= 8.33
L
VGS
v GS
v gs
== +− ˆˆ ˆ = = − B
v DS
VDS
B
D
=
− = = 12 × 1 × (1.39 − 1) = 0.076 mA 2
v DS
vo
max downward amplitude , we get
vo
(c) From part (a) above, the maximum instantaneous input signal while the transistor remains in saturation is 1.61 V and the corresponding output volt age is 0.61 V. Thus, the maximum amplitude of input sine wave is (1.61 1.5) 0.11 V. That is,v GS ranges from 1.5 0.11 1.39 V, at which
−
2 OV RD
n
7.7 At sat/triode boundary
2
DS
n
D
2
= 0.125 mA V = +2.00 V Point Q = ( 1.50 V,2.00 V ) A = −k V R = −12 V/V v
D
= V−2 = −1.510 V = 0.30 V V = V −V = 0.40 V A k = = −0.3−10× 20 V R = 1.67 mA/V W = 1.67 mA/V k = k L t
= 1.605 V i = 0.183 mA V = 0.608 V Point B = ( +1.61 V,0.61 V ) (b) For V = V −V = 0.5 V, we have V = 1.5 V 1 I = k (V − V ) 2 VGS
OV
D
Av VRD
∴
− 23V + 6 = 0
OV
VRD
1
= − 1] − 1 = 0
n
v GS
B
B
= V + | vAˆ | − V o
Vt
GS
t
v
= V − vˆ vˆ V + | A | = V − vˆ V −V vˆ = 1+ | | For V = 5 V, V = 0.5 V, and W = 1 mA/V , we use k L −2(V − V ) A V = DS
o
o
OV
DS
o
v
DS
OV 1 Av
o
DD
OV
2
and
n
= 5 − 0.076 × 24 = 3.175 V and v = 1.5 + 0.11 = 1.61 V at which v = 0.61 V. v DS
GS
DS
Thus, the large-signal gain is
− 3.175 = −11.7 V/V 1.61 − 1.39
0.61
−
whose magnitude is slightly less ( 2.5%) than the incremental or small-signal gain ( 12 V/V). This is an indication that the transfer characteristic is not a straight line.
−
DD
DS
v
OV
and Eq. (1) to obtain
ˆ
ˆ
V DS
Av
vo
1V
−16 −14 −12 −10
471 mV
29.4 mV
933 mV
66.7 mV
1.5 V 2V 2.5 V
vi
1385 mV
115 mV
1818 mV
182 mV
( 1)
Chapter 7–3
= 1 V, A = −16 = −k V = 32 k = 4 V, I = 0.125 mA
For VDS ∴
RD
ID RD
=
OV RD
n
v
Substituting VDD 5 V, rearranging the equation to obtain a quadratic equation in k n RD , and solving the resulting quadratic equation results in
D
k n RD
7.8
= 213.7
which can be substituted into Eq. (2) to obtain
vDS
VDS
= =
0.212 V
B
The value of VDS at the bias point can now be found from Eq. (1) as
VDS
+ 0.5 = 0.712 V
0.212
Q
(b) The gain achieved can be found as
0.5 V
n
D
OV
gs
B
VDSB
= −k R V = −213.7 × 0.2 = −42.7 V/V 0.5 0.5 vˆ = | A | = 42.7 = 11.7 mV (c) I = 100 A V −V R = I 5 − 0.712 = = 42.88 k Av
Q
VDSQ
v
µ
D
VOV
DD
vGS
ˆ
vgs
Vt
D
D
0.1
VDSB
213.7 (d)
To obtain maximum gain while allowing for a 0.5-V signal swing at the output, we bias the MOSFET at point Q where
W
−
VDS
= + VDS
Q
0.5 V
B
DS Q
L
2
kn
= 42.88 = 4.98 mA/V 4.98 = 0.2 = 24.9
(1)
7.9
as indicated in the figure above. Now, VDS B is given by Eq. (7.8) [together with Eq. (7.7)],
VDS
= =
√ 2k R n
B
D VDD
k n RD
+1−1
VDD (2)
Q2
From the figure we see that
VDS
B
+ vˆ = 0.2 V (given) and
VOV
where VOV
gs
vO
ˆ = 0.5A V | | = k R0.5V = k R 0.5× 0.2 = k2.5R
Q1
vI
v gs
v
n
D
OV
n
D
n
D
Thus,
VDS
0.2
2.5
+k R n
n
D VDD
k n RD
2
D
Substituting for VDS
√ 2k R
=V =V 1 W For Q , i = k 2 L given Vt 1
= B
iD (3)
B
from Eq. (2), we obtain
+ 1 − 1 = 0.2 +
D
For Vt
t
n
n
I
O
[ VDD
2
= 12 k WL ≤ v ≤ v +V,
For Q1 , iD
2.5 k n RD
t2
t
1
[ vI
−v −V ] O
2
−V ] t
t
2
Chapter 7–4
+v = 5 − 4.5 = 0.5 V −v = 4.5 − 0.3 = 4.2 V Similarly →
equate iD 1 and iD 2
= W
−v +V ]
[ VDD
L
O
2
W L
[ VDD
t
−V ]
[ vI
t
1
t
VDD
vO
=
− vI
For
Vt
( W /L )2
O
max
O
( W /L)1 ( W/L )2
IC VCE (mA) (V)
·[v − V ] I
t
( W /L )1
Vt
( W /L )2
− +
( W /L )1
max
2
−v −V ]= O
2
= √ =
A (V/V)
v O
v O
POS (V)
v
Neg (V)
0.5
4.5
–20
0.5
4.2
1.0
4.0
–40
1.0
3.7
2.5
2.5
–100
2.5
2.2
4.0
1.0
–160
4.0
0.7
4.5
0.5
–180
4.5
0.2
50
( W/L )1 ( W/L )2
0.5 5
10,
7.12
0.5
Av
√ = − 10 = −3.16 V/V
7.10 Refer to Fig. 7.6.
= − V V− V = − 5 − 1 = −160 V/V CC
Av
CE
T
0.025
≤
The transistor enters saturation whenv CE 0.3 V, thus the maximum allowable output voltage swing is 1 0.3 0.7 V. The corresponding maximum input signal permitted v be is
−
=
0.7 V
ˆ
0.7
ˆ = | A | = 160 = 4.4 mV
v be
Av
v
= − I VR = − V V− V C
C
CC
T
CE
T
On the verge of satuation
7.11
VCE 5 V
IC
RC 1 k vO
− vˆ = 0.3 V ce
=A v − | A vˆ | = 0.3 ( 5 − I R ) − | A | × 5 × 10− = 0.3 For linear operation, v ce
vbe
VBE
VCE
C
be
v
be
v
C
3
v
But
| A | = I VR C
C
v
T
Thus,
IC RC
= | A |V v
T
and
= 0.5 mA, we have I R 0.5 A =− = − 0.025 = −20 V/V V V = V −I R = 5 − 0.5 = 4.5 V For IC
C
C
v
T
CE
CC
C
C
− | A |V − | A | × 5 × 10− = 0.3 | A |( 0.025 + 0.005 ) = 5 − 0.3 | A | = 156.67. Note A is negative. A = −156.67 V/V 5
v
T
3
v
v
V
v
∴
v
Chapter 7–5
Now we can find the dc collector voltage. Referring to the sketch of the output voltage, we see that
The resulting gain will be
Av
= − V V− V CC
CE
T
VCE
= 0.3 + | A | 0.005 = 1.08 V v
|
which results in VCC of
|
7.13 To determine Av max , we use Eq. (7.23),
| = V V− 0.3
v
max
T
V CC
Then, for VCE
VCC
|A | = v
VCCmin we obtain
T
=V
CE sat
+ P + | A |V v
T
can support a positive peak amplitude ofP , that is,
CC
| A |V ≥ P
VT
T
v
In the results obtained, tabulated below, VCEsat 0.3 V and VCC is the ne arest 0.5 V to VCC min .
T
Finally, if a negative-going output signal swing of 0.4 is required, the transistor must be biased at 0.4 0.3 0.7 V and the gain achieved VCE becomes
=
+
|A | =
V CC
v
=
Case A (V/V) P (V) v
a b
− 0.7 .
VT
c
The results are as follows:
d
VCC
1.0
− 0.3 |A |
VCC
v max
VCC /2
0.7 28 0.5
1.5 1.2 48 0.75
| A | 20 30 − 0.7 0.3 0.8 | A | 12 32 v
VCC
v
2.0 1.7 68
3 . 0 ( V)
f
2.7 (V) 108 (V/V)
1.0 40
g
1.5 (V) 60 (V/V)
1.3 52
e
=V
CEsat
−20 −50 −100 −100 −200 −500 −500
| A |V v
T
VCC m in VCC
0.2
0.5
1.0
0.5
1.25
2.05
2.5
0.5
2.5
3.3
3.5
1.0
2.5
3.8
4.0
1.0
5.0
6.3
6.5
1.0
12.5
13.8 14.0
2.0
12.5
14.8 15.0
Av
92 (V/V)
C
C
T
+P
7.16 (a) See figure on next page (b) See figure on next page Note that in part (b) the graph is shifted right by 5 V and up by 5 V.
+
+
5 V
2.5 V
10 k
Thévenin
5 k
vO
0.3 mA
1.0
× 5 = −60 V/V = − I VR = − 0.3 0.025
This figure belongs to Problem 7.15.
vI
=
7.15 See figure below
2.3 (V)
7.14 To obtain an output signal of peak amplitude P volts and maximum gain, we bias the transistor at
VCE
v
but we have to make sure that the amplifier
= 2 − V2
V CC
= 2V
CE
Thus the minimum required VCC will be
CC
|A
= V + | A |V
VCC
10 k
vO
vI
0.3 mA
Chapter 7–6
This figure belongs to Problem 7.16(a). vO
0.5 V vI
0
0.3 V
B
vI
vO
RC
5 V
5 V
A
This figure belongs to Problem 7.16(b). vO
5 V 5V
B
4.7 V
vI
vO
RC A
0 0
7.17 iC
IC
S
VBE /VT
S
CC
VCE
CE BE
−R
C IS
Av
VA
v BE
C IC
=VBE , v CE =VCE VA
1
eVBE /VT
dv CE dv BE
VBE /VT
RC
VT
1
= −I RI /RV 1+ V +V C
C
A
+− − (VCC
1
VCE )/VT V CC VCE
we obtain Q.E.D
V +V = 5 V, V = 3 V, and V = 100 V, 5−3 A (without the Early effect) = − 0.025 = −80 V/V −80 A (with the Early effect) = 2 1+ 100 3 + = −78.5 V/V
1 VA
IC V CE
+
1
VT
CE
CE
A
1
VA
Av
v
T
C
CE
CC
CE
C
VA
Q.E.D
= V R− V = 5 −1 2 = 3 mA = − V − V = − 3 = −120 V/V
7.18 IC
Av C
CE ,
CC
v
V CE
1
= V −V
A
C C
=−
For VCC
Thus,
Av
Substituting IC RC
VA
+ −
C IS e
= −R
v CE
C C
CC
= −R
1
V CE
=I e 1 = V −R i = V −R I = ddvv
v CE
Av
+ +
v BE /VT
=I e
vI
4.5V 5V
CC
CE
VT
0.025
Using the small-signal voltage gain with 5 mV, we have v BE
=+ v = A × v = −120 × 5 mV = −0.6 V O
v
BE
Chapter 7–7
Using the exponential characteristic yields
(e) Assuming linear operation around the bias point, we obtain
v BE /VT
=I e = 3 × e = 3.66 mA Thus, i = 0.66 mA and v = − i R = −0.66 × 1 = −0.66 V Repeating for v = −5 mV as iC
C
=A ×v = −60 × 5 sin ωt = −300 sin ωt , mV = −0.3 sin ωt, V − v = 0.1 sin ωt, mA (f) i = R v ce
5/25
C
O
C
be
v
ce
C
c
C
(g) IB
BE
follows.
= Iβ = 0.5100mA = 0.005 mA C
0.1 = iβ = 100 sin ωt = 0.001 sin ωt , mA c
Using the small-signal voltage gain:
ib
v = −120 × −5 = +0.6 V
(h) Small-signal input resistance
O
Using the exponential characteristic:
5 mV
C
be b
= 0.001 mA = 5 k
v BE /VT
=I e = 3 × e− = 2.46 mA Thus, i = 2.46 − 3 = −0.54 mA and v = 0.54 × 1 = 0.54 V iC
≡ vvˆˆ
5/25
(i)
C
O
vBE vbe
vO (exp)
vBE
vO (linear)
VBE
+5 mV −660 mV −600 mV −5 mV +540 mV +600 mV Thus, using the small-signal approximation underestimates v O for positive v BE by about 10% and overestimates v O for negative v BE by about 10%.
| |
| |
5 mV
0.673 V
0
t
vCE
1.8 V
vce
VCE
1.5 V 0.3 V
1.2 V
7.19 (a) Using Eq. (7.23) yields
|A
v
− 0.3 = 108 V/V | = V V− 0.3 = 30.025 CC
max
T
= −60 yields 3−V =−
(b) Using Eq. (7.22) with Av
−60 = −
VCC
−V
CE
VT
0
iC (mA) IC
t 0.6 mA
0.1 mA
0.5 mA 0.4 mA
CE
0.025
⇒ V = 1.5 V CE
(c) IC
IC RC RC
0
= 0.5 mA = V − V = 3 − 1.5 = 1.5 V CC
CE
1.5
IB
= 0.5 = 3 k S
3
BE
ib 1 A
6 A 5 A 4 A
VBE /VT
=I e 0.5 × 10− = 10− ⇒ V = 0.673 V (d) IC
t
iB (A)
15 VBE /0.025
e
0
t
Chapter 7–8
7.20 Av
=−
IC
VT
≡ vv = − vi O
C RC
BE
BE
= −g
m RC
=I
CE
A
CE
CC
CE
CE
C
∴
C /VT
For a transistor biased at IC 0.5
g m
C
C
Thus,
gm
C
CE
But
Av
⇒ i = I ( 1 + v /V ) = 5 ( 1 + v /100 ) = 5 + 0.05v V −v Load line ⇒ i = = 10 − v R Eq. of L1
RC
= 0.5 mA, we have
− v = 5 + 0.05v = v = 4.76 V
10
VCE
= 0.025 =
CE
CE
IC
20 mA/V
CE
iC
10
5.24 mA
v CE
= = − =
=
Now for a signal of 30-µA peak superimposed on IB 50 µA, the operating point moves along the load line between points N and M. To obtain the coordinates of point M, we solve the load line and line L2 to find the intersection M, and the load line and line L3 to find N:
7.21
For point M:
iC
= 8 + (8/100)v i = 8.15 mA,
CE
For point N:
iC
= 2 + 0.02v = 7.84 V,
CE
v CE
N
M
==
and iC
iC
==
and iC v CE
∴ C M
N
10
10
−v
CE
1.85 V
−v
CE
2.16 mA
=4−1=3V = 2.5 V, we obtain
Peak-to-peak v C swing For point Q at VCC /2
= 2.5 V, I = 2.5 mA = 25 A V − 0.7 = 25 A I = R ⇒ V = I R + 0.7 = 2.5 + 0.7 = 3.2 V VCE
C
IB
µ
BB
µ
B
B
BB
B
B
7.22 See the graphical construction that follows. For this circuit:
= 10 V, = 1 k,
VCC
β
RC
VA
= 100, = 100 V,
IB 50 µA (dc bias), At v CE 0, iC β iB
=
∴
IC
=
Thus the collector current varies as follows:
=
= 50 × 100
2.91 mA
= 5 mA (dc bias)
8.15 mA
Given the base bias current of 50 mA, the dc or bias point of the collector current IC , and voltage VCE can be found from the intersection of the load line and the transistor line L1 of iB 50 µA. Specifically:
=
5.24 mA
i 5.99 mA, peak to peak
2.16 mA 3.08 mA
Chapter 7–9
And the collector voltage varies as follows:
gm
= k V = 10 × 0.2 = 2 mA/V n
OV
which is an identical result.
3.08 V 7.84 V 4.76 V
5.99 V
v
7.25 (a) ID
DS
V sin ωt in Eq. (7.28),
7.23 Substituting v gs
1
= 2 k (V − V ) n
GS
+ 12 k V n
t
2 gs
2
gs
= + k (V − V )V n
GS
t
GS
+ 12 k V n
gs
sin ωt
sin2 ωt
= 12 k (V − V ) + k (V − V )V t
2
n
GS
t
gs
= 14 VV
gs
OV
For Vgs
2 1 gs (
− 12 cos 2 ω t ) 2
= 14 × 0.01 ×1 100 = 0.25 V 1
2 OV
GS
gs
gs
2 n OV
2
D
o
= −10 = −g
m RD
= −g × 20 m
while maintaining saturation-region operation, the minimum voltage at the drain must be at least equal to VOV . Thus
VDS
= 0.2 + V
OV
= −V 1 − V DD
2
DS
VOV
−10 = − 1.8 −0.50.2V − V ⇒ V = 0.27 V
OV
OV
OV
The value of ID can be found from D
D
0.27
I
OV
= −0.02 V, v = 0.2 − 0.02 = 0.18 V = 12 k v = 12 × 10 × 0.18 = 0.162 mA 2 n OV
2
Thus,
= 0.2 − 0.162 = 0.038 mA
Thus, an estimate of gm can be obtained as follows:
gm
m
v
OV
= 0.242 − 0.2 = 0.042 mA
v gs
id
A
D
gm
For
iD
A
10 = VI = 0.1 = 100 k A = − g (R r ) = −1(10 100) = −9.1 V/V
= V2I 2 ×I 0.5 =
Thus,
id
1 mA/V
D
1
2
v OV
iD
0.2
Since
= 2 k V = 2 × 10 × 0.2 = 0.2 mA = V + v , where v = 0.02 V = 0.2 + 0.02 = 0.22 V = 12 k v = 12 × 10 × 0.22 = 0.242 mA
v GS
m
v
Av n
5
= = × = (c) A = −g R = −1 × 10 = −10 V/V 1 (d) λ = 0.1 V− , V = = 10 V λ
= 0.5 mA/V To allow for a −0.2-V signal swing at the drain
=
7.24 ID
D
gm
10 mV, to keep the second-harmonic
1
D
k n VOV
7.26 Av
× − × 100 Q.E.D
distortion to less than 1%, the mini mum overdrive voltage required is
VOV
DD
(b) gm
ro sin ωt
Second-harmonic distortion 1 2 k n Vgs 4 100 Vt )Vgs k n (VGS
=
2 t
GS
2
2.91 V
n
n
= 12 × 5(0.6 − 0.4) = 0.1 mA V = V − I R = 1.8 − 0.1 × 10 = 0.8 V
1.85 V
iD
= 12 k (V − V )
+ 0.038 = 2 mA/V = 0.0420.04
Alternatively, using Eq. (7.33), we can write
0.067 mA
D
⇒ =
The required value of k n can be found from
ID
= 12 k V n
2 OV
= 12 k × 0.27 ⇒ k = 1.83 mA/V Since k = 0.2 mA/V , the W /L ratio must be W = kk = 1.83 = 9.14 L 0.2 0.067
n
2
2
n
2
n
n
n
Chapter 7–10
VOV
Finally,
= V + V = 0.4 + 0.27 = 0.67 V
VGS
t
7.27 Av
OV
= −g
VDS
m RD
= − 2VI R D
D
2(VDD v GS v DS
−
max
Q.E.D
min
i
DS
t
OV
max
=v
ID
+V
t
DS
DD
i
L
OV
i
DD
OV
2
n
2
= kk = 4.44 = 44.4 0.1 n
n
i
µp
OV
i
DD
i
i
OV
OV
For
2
= 500 cm /V·s, = 250 cm /V·s, and C = 0.4 fF/
7.28 Given µ n
OV
DS
VDD
n
i
OV
i
2 OV
= 2k V
DS
DS
DS
0.2
1
= 12 k × 0.3 ⇒ k = 4.44 mA/V W
v
OV
k
Q.E.D
n
kp
2
20 µA/V2
µn Cox
== 10
ox
=
µA /V
2
See table below.
= 2.5 V, vˆ = 20 mV and m = 15 i
0.2 mA,
The required W /L ratio can now be found as
i
v
200 µA
− 0.576= = 9.62 k=
n
+ vˆ = V − | A |vˆ Substituting for | A | from Eq. (1) yields 2 (V − V ) V + vˆ = V − vˆ V V [1 + 2(vˆ /V )] = V + vˆ + 2V (vˆ /V ) ⇒ V = V +1vˆ++2(2vˆV/V (vˆ)/V ) i
2.5
0.2
which results in
VOV
=
RD
i
v
DS min
i
v
i
To just maintain saturation-mode operation, v GS
OV
( 1)
= V + vˆ = V + V + vˆ = V − | A |vˆ GS
DS
v
To operate at ID
VDS )
VOV
= 0.576 V 2(V − V ) A =− = − 2(2.5 −0.30.576) V = −12.82 V/V vˆ = | A |vˆ = 12.82 × 20 mV = 0.256 V o
OV
=−
i
DD
Upon substituting for gm from Eq. (7.42), we can write
Av
= mvˆ = 15 × 20 = 0.3 V 2.5 × (0.02/0.3) = 0.3 + 0.021 ++ 22(×0.02 /0.3)
µm
2
,
Chapter 7–11
= 250
7.29 Given µ n Cox
= 0.5 V, L = 0.5 m For g = 2 mA/V
µA /V
2
= 1−R = 1−+ggRR +R g
vd
,
D
vi
Vt
m
D
m
S
S
m
µ
m
=
gm ∴
= 16
W
=
VGS
L
= 0.25 mA,
and ID
ID
W
⇒
7.31
= 32
L
VDD
µm
2 ID
VOV ∴
2µn Cox
W
2
0.25 V
gm VOV
I 500 µA
= = + V = 0.75 V
RG 10 M
t
vo
7.30
VDD
RL 10 k
vi
RD
vd
Vt
vi
VA vs
= 0.5 V = 50 V = V = 1 V. Also, I = 0.5 mA. = 0.5 V, g = V2I = 2 mA/V
Given VDS
RS
VOV
GS
D
D
m
OV
VA ro
VSS
= I = 100 k = −g ( R R r ) = −18.2 V/V v For I = 1 mA: √ 1 V increases by = 2 to 0.5 √ 2 × 0.5 = 0.707 V. V = V = 1.207 V g = 2.83 mA/V, r = 50 k and v = −23.6 V/V v D
vo
m
D
vd
G
L
o
i
D
RD
gmvgs
OV
G
vi
GS
1
vgs
gm
DS
m
o
o
S
i
vs
RS
7.32 For the NMOS device:
W
1
ID
vi vd vs ∴
= g v g1 + R = −g v R = +g v R v = 1 R = 1++gg RR v +R g m gs
m gs
D
m gs
S
s
S
m
S
i
m
S
m
m
S
S
= 100 = 2 µ C L V 1 10 = 2 × 400 × 0.5 ×V ⇒ V = 0.16 V 2I 0.1 mA = 2 ×0.16 = 1.25 mA/V g = V V = 5L = 5 × 0.5 = 2.5 V V r = = 2.5 = 25 k I 0.1 n
2 OV
ox
2 OV
OV
D
m
OV
A
A
o
D
Chapter 7–12
For the PMOS device:
ID
W
1
= 100 = 2 µ C p
1
ox
10
L
+
From the circuit
2 OV
= 2 × 100 × 0.5 × V ⇒ V = 0.316 V × 0.1 = 0.63 mA/V 2I g = = 20.316 V V = 6L = 6 × 0.5 = 3 V r = V = 3 = 30 k 0.1 I
=
−I
VD VDD assumed
OV
D
D RD
= 15 − 0.5 × 16 = +7 V, as
Finally,
m
OV
=
= 1.5 − V = 1.5 − 1
VGS 1.5 V, thus VOV 0.5 V
A
o
+
Since the drain voltage ( 7 V) is higher than the gate voltage ( 5 V), the transistor is operating in saturation.
2 VOV
=
A D
ID
t
= 12 k V = 12 × 4 × 0.5 = 0.5 mA 2 OV
n
2
which is equal to the given value. Thus the bias calculations are all consistent.
7.33 (a) Open-circuit the capacitors to obtain the bias circuit shown in Fig. 1, which indicates the given values.
= V2I = 2 ×0.50.5 = 2 mA/V D
(b) gm
OV
15 V
ro
= VI = 100 = 200 k 0.5 A
D
0.5 mA 10 M
(c) See Fig. 2 below.
v gs
7 V 1.5 V
v sig
5 M
= 10 M 5 M = 3.33 M = R R+ R = 3.333.33 + 0.2
(d) Rin
16 k
0.5 mA
in
in
sig
= 0.94 V/V v = −g (200 16 16) v = −2 × 7.69 = −15.38 V/V v = vv × vv = −0.94 × 15.38 v = −14.5 V/V o
7 k
m
gs
Figure 1 From the voltage divider, we have
VG
= 15 10 5+ 5 = 5 V
gs
o
sig
gs
7.34 (a) Using the exponential characteristic:
ic
From the circuit, we obtain
=I
Ce
giving
= V + 0.5 × 7 = 1.5 + 3.5 = 5 V
VG
o
sig
GS
v be /VT
ic IC
−I
=e
C
v be /VT
−1
(b) Using small-signal approximation:
which is consistent with the value provided by the voltage divider.
ic
=g
m v be
= VI · v C
be
T
This figure belongs to Problem 7.33, part (c).
Rsig 200 k v
o
vsig
vgs
10 M
5 M
gmvgs
200 k
Rin Figure 2
16 k
16 k
Chapter 7–13
ic
Thus,
= vV
be
IC
Voltage gain,Av
T
= −110 V/V
±
For signals at 5 mV, the error int roduced by the small-signal approximation is 10%. The error increases to above 20% for signals at 10 mV.
±
i c /I C Ex po ne nt ia l
(mV )
ce
be
See table below.
v be
V = vv = − 0.55 5 mV
i c /I C Error Sm al l si gn al (% )
Using small-signal approximation, we write
Av
= −g
m RC
where
gm
0.5 mA = VI = 0.025 = 20 mA/V V C
T
Av
20
5
100 V/V
+1
+0.041
+0.040
–2.4
–1
–0.039
–0.040
+2.4
+2
+0.083
+0.080
–3.6
= −the small-signal × = − approximation at this Thus, signal level (v = 5 mV) introduces an error of −9.1% in the gain magnitude.
–2
–0.077
–0.080
+3.9
7.36 At IC
+5
+0.221
+0.200
–9.7
–5
–0.181
–0.200
be
= 0.5 mA, 0.5 mA = 0.025 = 20 mA/V V
IC
gm
=V
rπ
= g = 20 100 = 5 k mA/V
T
+10.3
β
+8
+0.377
+0.320
–15.2
–8
–0.274
–0.320
+16.8
+10
+0.492
+0.400
–18.7
–10
–0.330
–0.400
+21.3
where
+12
+0.616
+0.480
–22.1
α
–12
–0.381
–0.480
m
7.35
= αIV
IE
T
C
= β +β 1 = 100100+ 1 = 0.99
25.9
+
=
re
VT
re
25 mV 50 = 0.990.5× mA At I = 50 A = 0.05 mA, I 0.05 = 0.025 = 2 mA/V g = V µ
C
C
m
5 V
T
rπ
0.5 mA
100 = g = 2 mA/V = 50 k = αV = 0.99 × 25 mV 500 β
m
5 k
VC
re
T
IC
0.5 mA
1 mA = VI = 0.025 = 40 mA/V V C
7.37 gm
T
vBE
re
= g = 400.99 25 mA/V α
m
With v BE
rπ
0.700 V
= V = V −R I = 5 − 5 × 0.5 = 2.5 V For v = 705 mV ⇒ v = 5 mV i =I e = 0.5 × e = 0.611 mA − R i = 5 − 5 × 0.611 = 1.95 V v = V v = v − V = 1.95 − 2.5 = −0.55 V C
CC
C C
BE
C
C
100
β
2.5 k
gm
= = 40 mA/V = A = −g R = −40 × 5 = −200 V/V vˆ = | A |vˆ = 200 × 5 mV = 1 V m
v
o
v
C
be
be
v be /VT
5/25
C
CC
ce
C
gm
IC
=V
T
C C
C
= 30 mA/V, ⇒ I = g V = 30 × 0.025 = 0.75 mA
7.38 For gm
rπ
C
m
β = gβ = 30 mA/V m
T
Chapter 7–14
≥ 3 k, we require ≥ 90 That is, β = 90. For rπ
then
β
VCC
min
be
IC RC
T
= 0.3
= V −ˆ0.3 V 1+ V CC
IC RC
( 1)
be
m
T
where
Since the voltage gain is given by
IC
=V
gm
ˆ − VV
C RC
which can be manipulated to yield
= gβ
7.39 rπ
−I
IC RC
T v
Nominally, gm 40 mA/V. However,IC varies by 20%, so gm ranges from 32 mA/V to 48 mA/V. Thus
=
±
rπ
50 48
= V − ˆ0.3 V +V ˆ = 5 mV, For V = 3 V and V 3 − 0.3 = 2.25 V I R = 5 1+ 25 CC
be
CC
= 1.04 k
= 4.7 k.
32
then
T
Thus, the extreme values of rπ are 150
VT
=−
Av
= 3250to to48150 mA/V
and
A
C
be
C
Thus,
= 3 V, 3 −1 = 2 = 1 mA
7.40 VCC
IC
VC
= 1 V,
RC
= 2 k
1 mA = VI = 0.025 = 40 mA/V V C
gm
T
= V −I R = 3 − 2.25 = 0.75 V Vˆ = V − 0.3 = 0.75 − 0.3 = 0.45 V 3 − 0.3 A =− = −90 V/V 0.025 0.005 + Check: I R 2.25 = − 0.025 = −90 V/V A = −g R = − V Vˆ = | A | × Vˆ = 90 × 5 = 450 mV = 0.45 V VCE
CC
o
C
C
CE
v
v be
0.005 sin ωt
= i = g v = 0.2 sin ωt , mA i (t ) = I + i = 1 + 0.2 sin ωt , mA −R i v (t ) = V = 3 − 2(1 + 0.2 sin ωt ) = 1 − 0.4 sin ωt, V i (t ) = i (t )/β = 0.01 + 0.002 sin ωt , mA v 0.4 = − 0.005 = −80 V/V A = v c
m be
C
C
C
c
CC
B
C C
C
C
m
v
T
o
7.42 Tr a n s i s t or
b
c
d
0.980
e 1
f
g
0.990 0.900 0.940
c
β
∞
1 00
IC(mA)
1.00
0.99
1.00 1.00 0.248
4.5
IE(mA)
1.00
1.00
1.02 1. 00 0. 25
5
ˆ
maximum gain magnitude. This in turn is achieved by biasing the transistor at the lowest VCE consistent with the transistor remaining in the active mode at the negative peak ofv o . Thus
− | A |Vˆ = 0.3 v
= V −I CC
C RC
= 0.3 V. Since
m RC
=V
T
RC
9
15.9 17.5 18.6
0
0.010
0.020
0
0.002
0.5
1.10
40
39.6
40
40
9.92
180
700
re () rπ ()
25
25 24.5 2 5 2.525 k 1.25 k
∞
= 1 mA,
7.43 IC
β
100 5 1.34 10.1 k 50 22.7
∞
= 100,
gm
1 mA = VI = 0.025 = 40 mA/V V
rπ
= g = 40 100 = 2.5 k mA/V
C
T
β
m
IC
100
IB(mA)
and
|A | = g
∞
50
gm(mA/V)
be
where we have assumed VCE sat
v
a
1.000 0.990
α
be
7.41 Since Vbe is the maximum value for acceptable linearity, the largest signal at the collector will be obtained by designing for
VCE
be
v
v
VCE
C
C
ro
=
VA IC
V = 100 = 100 k 1 mA
VA
= 100 V
Chapter 7–15
This figure belongs to Problem 7.43.
B
C
ib
C
B
rp
vp
ro
gmvp
E rp 2.5 k,
rp
E ro 100 k,
gm 40 mA/V
b 100
C
C
gmvp
B
ai
B
ro
vp
re
ro re
i
E
E
re 24.75 , gm 40 mA/V
ro 100 k, a 0.99 gm
α
= β β+ 1 = 100100+ 1 = 0.99
ib
re
25 mV = 24.75 = VI = αIV = 0.991×mA
= g v −α = g βv
T
=v
be
α
1
T
E
ro
bib
C
−g α
m
m be
m be
7.44
Rin
≡ vi = gβ = r be b
Q.E.D
π
m
7.45 Refer to Fig. 7.26. gmvbe B
ib
vbe
= αi = α vr = rα v be
e
e
=g
vbe
ic
re
be
e
Q.E.D
m v be
7.46 The large-signal model of Fig. 6.5(d) is shown in Fig. 1.
E
iB Rin
B vBE
ib
=
=v
v be
be
re
−g
1
re
m v be
−g
m
C DB
( ISB IS ) b
biB
E Figure 1
Since
re
= gα
m
For v BE undergoing an incremental changev be from its equilibrium value of VBE , the current iB
Chapter 7–16
C
changes from IB by an increment ib , which is related to v be by the incremental resistance of DB at the bias current IB . This resistance is given by VT /IB , which is rπ .
aiE
The collector current β iB changes from β IB to β( IB ib ). The incremental changes around the equilibrium or bias point are related to each other by the circuit shown in Fig. 2,
+
B
ie re
vbe
ib B
C
bib
rp
vbe
E Figure 2 which is the small-signal T model of Fig. 7.26(b). Q.E.D.
E
7.48 Refer to Fig. P7.48:
= 3 − 0.2 × 10 = 1 V 25 mV = VI = 0.2 = 125 mA
VC
Figure 2
T
re which is the hybrid-π model of Fig. 7.24(b). Q.E.D.
E
Replacing the BJT with the T model of Fig. 7.26(b), we obtain the equivalent circuit shown below.
7.47 The large-signal T model of Fig. 6.5(b) is shown below in Fig. 1.
C
aiE B
iE
vBE
(I
DE
SE
IS a
)
E Figure 1
If iE undergoes an incremental change ie from its equilibrium or bias value IE , the voltage v BE will correspondingly change by an incremental amount v be (from its equilibrium or bias value VBE ), which is related to ie by the incremental resistance of diode DE . The latter is equal to VT /IE , which is re . The incremental change ie in iE gives rise to an incremental change α ie in the current of the controlled source. The incremental quantities can be related by the equivalent circuit model shown in Fig. 2,
= −i × 10 k
vc
e
where
ie
= − vr = − 0.125v k i
e
Thus, vc vi
10 k = 0.125 k
= 80 V/V
i
Chapter 7–17
This figure belongs to Problem 7.50.
= | A |v | A | = g R = 50 × 2 = 100 V/V 7.49
v ce
be
v
m
v
7.51 Replacing the BJT with the T model of Fig. 7.26(b), we obtain the circuit shown below.
C
= 1100V = 0.01 V peak to peak
v be
ib
= vr
ix
C
For v ce being 1 V peak to peak,
aie
be π
B
vx
ie
where
re
= gβ = 100 = 2 k 50
rπ
m
E
Thus,
vx
0.01 V
ib
=
Since v x appears across re and ix
7.50
≡ vi = r
π
b
r
= r +r R = −g v R
vπ
π
v sig
π
sig
vo
m π
C
vo vπ
= −g
≡ vi = vi = r x
x
x
e
v
=v
= −g
7.52 Refer to Fig. P7.52. Replacing the BJT with the T model of Fig. 7.26(b) results in the following amplifier equivalent circuit:
= −g
m rπ
v
aie B
rπ rπ
+R
vi
RC
sig
re E
Re
sig
C
ib ie
sig
+R
rπ
= − r β+RR π
C
π o π v sig
m RC
, the
e
m RC
v o
x
e
e
The overall voltage gain can be obtained as follows: v sig
= i = vr
small-signal resistance r is given by
π
Rin
r ix
= 0.005 mA peak to peak
2 k
vo
Q.E.D.
Rin
Chapter 7–18
Rin
≡ vi = (1 −v α)i i
i
b
The input resistance Rin can be found by inspection to be
e
From the circuit we see that
ie
i
e
But 1
= r1 +− Rα e
α ie (RC
vo
i
RL )
− i × (12 12) = −0.99 × 6i = −=0.99 −v = −0.99 × 6 × 0.15 e
e
i
= (β + 1)(r + R ) e
e
Q.E.D.
Thus,
From the equivalent circuit, we see thatv o and v i are related by the ratio of the voltage divider formed by re and Re : vi
i
e
The output voltage v o is given by
1
Thus,
vo
i
sig
− = β +1
Rin
= − R v+ r = − 150v = − 0.15v k
ie
e
α
e
To determine the voltage gain( v o /v i ) we first find ie :
e
Thus,
Rin
= r = 75
Rin
= r +v R
= R R+ r e
e
vo
= 39.6 V/V
vi
Q.E.D.
7.54 Refer to Fig. P7.54.
e
= β β+ 1 = 200 = 0.995 201 I = α × I = 0.995 × 10 = 9.95 mA V = I R = 9.95 × 0.1 k = 0.995 V 1 V α
7.53 Refer to Fig. P7.53. The transistor is biased at IE 0.33 mA. Thus
=
re
=
VT IE
C
25 mV
= 0.33 mA = 75
E
C
C
C
Replacing the BJT with its hybrid-π model results in the circuit shown below.
Replacing the BJT with its T model results in the following amplifier equivalent circuit.
gm
10 mA = 400 mA/V = VI 0.025 V C
T
= g = 200 = 0.5 k 400 R = r = 0.5 k R = 10 k 0.5 k = 0.476 k 0.476 v = R R+ R = 0.476 + 1 = 0.322 V/V v β
rπ
m
ib
π
in
in
π
sig
vo
vπ vo v sig
in
= −g
m RC
sig
= −400 × 0.1 = −40 V/V
= −40 × 0.322 = −12.9 V/V
This figure belongs to Problem 7.54.
Rsig 1 k
vb vo
vsig
vp
10 k
Rin
Rib
rp
gmvp
RC
Chapter 7–19
This figure belongs to Problem 7.55. B
C
vsig
vp
gmvp
rp
ro
vo
RL very high
For
7.57
= ±0.4 V/V = v = ±−0.4 = ∓0.01 V = ∓10 mV 40 0.4 = −±12.9 = ∓31 mV
vo vb
5 V
π
v sig
RE
Rsig 50 7.55 The largest possible voltage gain is obtained when RL , in which case vo v sig
→∞ = −g r = − VI
C
VA
T
IC
m o
= − VV
vsig
Rin re 50
A
vo
T
For VA
= 25 V,
= −1000 V/V For V = 125 V, = −5000 V/V A
vo v sig
RC
25 = − 0.025
5 V vo v sig
125
= − 0.025 = 50 = VI ⇒ I = 0.5 mA
T
re
E
E
7.56 Refer to Fig. 7.30:
Rin
r
e
5
To obtain an input resistance of 75 ,
re
= 75 = VI
where
VE
= 2575mV = 0.33 mA
= 10 R− 0.7 = 0.33 mA ⇒ R = 28.2 k
IE
E
E
Note that the dc voltage at the collector remains unchanged. The voltage gain now becomes vi
× 14.1 = 186 V/V = αrR = 0.990.075 C
e
E
E
T
This current is obtained by raising RE to the value found from
vo
− V = 0.5 mA R
E
Thus,
IE
Thus,
0.7 V ⇒ R = 8.6 k E
To obtain maximum gain and the largest possible signal swing at the output for v eb of 10 mV, we select a value for RC that results in
VC
+ | A | × 0.01 V = +0.4 V v
which is the highest allowable voltage at the collector while the transistor remains in the active region. Since
VC
= −5 + I
C RC
−5 + 0.5R
C
then
−5 + 0.5R + g C
m RC
× 0.01 = 0.4
Chapter 7–20
Substituting gm
= 20 mA/V results in
1, 25 mV = I = 0.5 = 50 mA
For α
= 7.7 k
RC
VT
re
E
The overall voltage gain achieved is
= R R+ R × g R = 50 50 + 50 × 20 × 7.7 = 77 V/V vo
in
m
v sig
in
vi
C
sig
vi
If v o1 is connected to ground, RE will in effect be short-circuited at signal frequencies, andv o2 /v i will become v o2 α RC
=−
vi
= R R+ R in
Gv
and the dc voltage at the emitter will be
in
= V − 0.7 = 1.8 V = VR = 1.8 = 0.5 mA 3.6 E
L
= R v+ R sig
ii
I = 0.5 mA E
sig
Replacing the BJT with the T model of
io
Fig. 7.26(b) results in the following equivalent circuit model for the amplifier.
ii
= R v+ r = i R = v R R+ r v
=G
i
ie
E
E
i
v o2
= R R+ r E
E
e
Q.E.D.
vi
C
C
in
Rin
Rin
sig
in
e
in
C
E
+R
RL
+ R = 0.95 R = 0.95 R + 100 ⇒ R = 1.9 M
vi
E
v o2
Rsig
7.60 (a)
e
= −αi R = −α R + r R = − RαR+ r Q.E.D. e
Rin
+
RL
sig
= 79.4 × 20 +2 100 = 4762 A/A
E
e
=v
in
Rsig
vo
v
e
E
vi
o
2
o
and
v o1
+R
o
E
o1
RL RL
= 100 + 20 × 100 × 2 + 0.1 = 79.4 V/V v i = R
B
IC
Av o
sig
100
The dc emitter current can now be found as
IE
3.3 = − 0.05 = −66 V/V
re
7.59 See figure on next page.
= 5 100100 + 100 = 2.5 V
VE
= − 3.6 +3.30.05 = 0.904 V/V
v o2
7.58 Refer to Fig. P7.58. Since β is very large, the dc base current can be neglected. Thus the dc voltage at the base is determined by the voltage divider,
VB
= 3.6 +3.60.05 = 0.986 V/V
v o1
e
in
This figure belongs to Problem 7.58. vo2
aie
ie vi
RC
re vo1
100 k
100 k
RE
Chapter 7–21
This figure belongs to Problem 7.59.
Rsig 20 k
Ro 100
vsig
Rin 100 k
vi
RL 2 k
A
vi vo
vo
A o 100 v
This figure belongs to Problem 7.60.
Rsig
Ro
vsig
Rin
vi
A
v
RL
ovi
(b) With RL
=A
vo
v ov i
With RL
=A
vo
= 2 k,
7.61 The circuit in Fig. 1(b) (see figure on next page) is that in Fig. P7.61, with the output current source expressed as Gm v i . Thus, for equivalence, we write
2 2
+R
o
1 k ,
=
v ov i
Avo Gm
1 1
+R
=A
v ov i
2
− 1 +1 R 2+R o
o
io
To limit this change to 5% of the value with RL 2 k , we require
=
=
2 1 +R − 1+R ⇒ R = 19 k = 111 2
o
o
2
2
+R
0.05
o
(c) Gv
= 10 = R + R in
1.9
Av o sig
+R
o
2
= 1.9 + 0.1 × A × 2 + 0.111 ⇒ A = 11.1 V/V vo
vo
The values found about are limit values; that is, we require
Rin Ro
≥ 1.9 M ≤ 111 ≥ 11.1 V/V
Av o
=G
mv i
= vi
o
Gm
i RL
=0
and is known as the short-circuit transconductance. From Fig. 2 on next page,
= R R+ R = G v (R R ) in
v sig
RL RL
Ro
Thus Gm is defined as
vi
o
Rin
=
To determine Gm (at least conceptually), we short-circuit the output of the equivalent circuit in Fig. 1(b). The short-circuit current will be
o
Thus the change in v o is v o
vo
vo
in
sig
m i
o
L
Thus,
= R R+ R
vo
in
v sig
in
Gm (Ro RL )
sig
7.62
Gv o
= vv
o
sig RL
=∞
=∞
Now, setting RL in the equivalent circuit in Fig. 1(b), we can determine Gv o from
Chapter 7–22
This figure belongs to Problem 7.61.
Ro
io
io Norton
Rin
vi
A
vi vo
equivalent of output circuit
vo
A ovi Ro Gmvi v
Rin
vi
(a)
Ro
vo
(b)
Figure 1
Rsig
vsig
vi
Rin
Gmvi
Ro
RL
vo
Figure 2 This figure belongs to Problem 7.62.
Rsig
Rout
vsig
vi
Rin
G
v
RL
ovsig
vo
(a)
Rsig
Ro
vsig
vi
Rin
A
v
RL
ovi
vo
(b)
Figure 1
Gv o
= R R+ R in
in
sig RL
Gv o
Ri
= R +R i
Av o
vo
=∞
Denoting Rin with RL Gv o as
RL
=G
Gv
Av o
RL
Q.E.D.
+R
out
= ∞ as R , we can express i
Q.E.D.
sig
From the equivalent circuit in Fig. 1(a), the overall voltage Gv can be obtained as
7.63 Refer to Fig. P7.63. To determine Rin , we simplify the circuit as shown in Fig. 1, where
≡ vi = R R , where R ≡ vi = i R + (i − g v )(R R ) i
Rin
1
i
vi
f
f
f
in
m i
in
2
L
f
i
Chapter 7–23
This figure belongs to Problem 7.63.
Figure 1 controlled source gm v i . Thus, looking between the output terminals (behind RL ), we see R2 in parallel with Rf ,
Thus,
[1 + g ( R R ) ] = i [R + ( R R ) ] v R ≡ = 1R++g ((RR RR )) i vi
m
L
2
i
in
f
f
f
m
L
L
2
f
2
f
+ (R R ) 1 + g (R R ) Rf
L
2
m
L
2
m
L
2
Rin = R1 Rin 1
f
2
1
and
=R
= R R Q.E.D. For R = 100 k , R = 1 M, g = 100 mA/V R = 100 and R = 1 k 1000 + (0.1 1) = 100 99.1 R = 100 1 + 100(0.1 1) = 49.8 k Without R present (i.e., R = ∞), R = 100 k Ro
L
2
in
Q.E.D.
To determine Av o , we open-circuit RL and use the circuit in Fig. 2, where
f
f
in
and
Rf
if vo
R1
vi
= −100 × 0.1 1 − (1/1000.1× 1000) 1+ 1000 −10 V/V Without R , −A = 10 V/V and R = 0.1 1000 0.1 k = 100 Without R , R = 100 . Av o
R2
gmvi
R2
vo
f
vo
o
f
Figure 2
if vi
= g v + Rv
o
m i
2
+ + =
=i R +v = f
v i (1
−g
f
o
m Rf
)
vo
gm v i
R2
+v
o
Rf
1
vo
Rf
Gv
in
in
Av o sig
RL RL
+R
o
With Rf , 49.8
1
v
G
= 49.8 + 100 × −10 × 1 + 0.1 = −3 V/V
≡ vv = 1 − gRR 1+ R m
o
f
Without Rf ,
f
i
2
which can be manipulated to the form
Av o
= R R+ R
R2
Thus,
Av o
o
Thus the only parameter that is significantly affected by the presence of Rf is Rin , which is reduced by a factor of 2!
= −g
m R2
1 1
− 1/g R + (R /R ) m
2
f
Gv
1 = 100100 + 100 × −10 × 1 + 0.1 = −4.5 V/V
Q.E.D.
f
Finally, to obtain Ro we short-circuit v i in the circuit of Fig. P7.63. This will disable the
= 1 M, R = 10 k = 2 mA/V, R = 10 k
7.64 Rsig
gm
L
D
Chapter 7–24
= − g (R R ) = −2(10 10) = −10 V/V Gv
m
7.65 Rin
ID
D
= 2µ C n
320
gm
L
Gv
2 VOV
D2
gs2
o
gs1
gs2
= −g R × −g (R R ) = 3 × 10 × 3 × (10 10) m1
1
2 OV
= 2 × 400 × 10 × V
VOV
⇒
RD1 RL
W ox
D
m2
OV
=∞
1
= g = V2I = 2 ×0.20.3 = 3 mA/V = R = 10 k = 10 k = vv × vv
(b) gm1
L
0.4 V
=
D1
OV
Ro Gv
m
C
T
β = 20 100 = 5 k r = mA/V g R = r = 5 k R = R = 10 k A = −g R = −20 × 10 = −200 V/V R A =A = −200 × 10 10 R +R + 10 = −100 V/V R G = A R R + = 5 +5 10 × −100 = −33.3 V/V For vˆ = 5 mV, vˆ can be found from × R R+ R = vˆ × 5 +5 10 vˆ = vˆ
D
π
m
L
vo
o
10
= −16 × 10 + 10 = −8 V/V Peak value of v sig
in
π
o
C
vo
= 0.28 V = 25 mV.
m
C
L
vo
v
L
7.66 RD
= 2R = 30 k L
= 0.25 V G = − g (R R ) −10 = −g (30 15) ⇒ g = 1 mA/V 2I g = V 2 ×I 1= VOV
m
v
D
in
L
D
sig
π
m
OV
sig
in
sig
π
D
sig
in
0.25
⇒ I = 0.125 mA = 125 D
sig
⇒ vˆ = 15 mV sig
µA
ˆ
Correspondingly, v o will be
If RD is reduced to 15 k,
ˆ = G vˆ = 15 × 33.3 = 500 mV = 0.5 V vo
= − g (R R ) = −1 × (15 15) = −7.5 V/V D
v
in
m
m
o
v
m
Gv
L
0.5 mA = VI = 0.025 = 20 mA/V V
7.68 gm
D
L
D2
= 450 V/V
= V = 2 ×0.40.32 = 1.6 mA/V = −g R = −1.6 × 10 = −16 V/V = R = 10 k = A R R+ R 2 ID
Av o
m2
L
v
sig
7.67 (a) See figure below. This figure belongs to Problem 7.67.
Rsig 200 k
vsig
vgs1
gm1vgs1
RD1 vgs2
gm2vgs2
R D2
RL
vo
Chapter 7–25
| | = (R
7.69 Gv
RL
RL
sig /β)
That is,
+ (1/g
m)
8 10 + (1/g ) = 0.2 + (1/g ) ⇒ g1 = 0.3 or g = 3.33 mA/V
= 10 k, R = 10 k, g = VI
0.1
C
m
sig
T
1 = 0.025 = 40 mA/V Nominal β = 100 10 (a) Nominal | G | = (10/100) + 0.025
m
m
m
v
nominal
| G = 0.2 10 + 0.3 = 20 V/V (−20% of nominal ) v
= 80 V/V 10 (b) β = 50, | G | = (10/50) + 0.025 = 44.4 V/V 10 β = 150, | G | = (10/150) + 0.025 = 109.1 V/V Thus, | G | ranges from 44.4 V/V to 109.1 V/V. (c) For | G | to be within ±20% of nominal (i.e.,
min
We need to check the value obtained for β 150,
v
=
|G
v
v
which is less than the allowable value of 1.2 Gv nominal 30 V/V. Thus, the new bias current is
|
ranging between 64 V/V and 96 V/V), the corresponding allowable range of β can be found as follows:
m
v
+ 0.025
RL gm1
max
| |
rπ 1
= (10/10010 ) + (1/g
v sig vπ2 vπ1
C
m2
= r = g = 100 = 10 k 10 β
π2
rπ 1
= r + R = 10 10 + 10 = 0.5 V/V = −g (R r ) = −10(10 10) π1
m1
C1
π2
C2
L
π2
10
nominal
sig
o
m2
0.8 Gv
= 10 k
= −50 V/V v = −g (R R ) v = −10(10 10) = −50 V/V
m)
then
Rsig
m
vπ1
| | | |
±
|
C2
T
(d) By varying IC , we vary the term 1/gm in the denominator of the Gv expression. If β varies in the range 50 to 150 and we wish to keep Gv within 20% of a new nominal value of Gv given by nominal
= R = 10 k
= 10 k mA = g = VI = 0.25 = 10 mA/V 0.025 V
max
v
nominal
(b) RC 1
min
T
7.70 (a) See figure below.
10
⇒ β = 76.2 10 96 = (10/β ) + 0.025 ⇒ β = 126.3
|G
=
= g × V = 3.33 × 0.025 = 0.083 mA |G = 25 V/V
IC
v
min )
= 10/15010+ 0.3 = 27.3 V/V
max
v
= (10/β
= 0.1 10 + 0.3 = 25 V/V
|G
v
64
m
= (10/50) + (1/g
m)
This figure belongs to Problem 7.70.
Rsig 10 k
vsig
vp1
rp1
vp2
gm1vp1
rp2
vo
gm2vp2
RC1
RC2
RL
Chapter 7–26
vo
o
π2
π1
v sig
= vv × vv × vv = −50 × −50 × 0.5 = 1250 V/V π2
π1
sig
7.71 gm
+ 10 = 6.65 mV ˆ = 5 × 30.330.3 vˆ = vˆ × |G | = 6.65 × 15 100 mV v sig o
= 1 +gg
= 1 + 5R Rs
v
m
effective
= (β + 1)(r + R ) 15 = 75(r + R ) 15 k r +R = = 200 75 7.75 Rin
m Rs
5
2
sig
e
e
s
0.3 k
⇒ =
e
300
=
+
− − 2=1+g R ⇒ R = g1 = 12 = 0.5 k m
e
Rin
ˆ = vˆ
vπ
7.72 The gain magnitude is reduced by a factor of (1 gm Rs ). Thus, to reduce the gain from 10 V/V to 5 V/V, we write
sig
Rin
re
+R 15
= 150 × 15 + 30
5
m
+R
e
re
re
+R
e
⇒ r + R = 0.1 But r + R = 200 , thus r = 20 e
s
re
sig
re
s
e
e
e
e
e
e
7.73 Including Rs reduced the gain by a factor of 2, thus
+g R =2 1 ⇒ g = R1 = 0.5 = 2 mA/V The gain without R is −20 V/V. To obtain a gain of −16 V/V, we write 20 16 = = 1 +202R 1+g R ⇒ R = 125 1
m
s
m
s
s
m
s
s
s
0.5 = VI = 0.025 = 20 mA/V C
7.74 gm
T
1
g = 50 R = (β + 1)(r + R ) = 101(50 + 250) = 30.3 k αR = − 0.990.3× 12 −40 V/V A =− r +R R = R = 12 k re
m
e
in
C
o
e
C
RL
A
= A R +R = −40 × 12 12 + 12 = −20 V/V v
vo
L
π
C
E
e
in
v
in
sig
Total resistance in emitter
×6 = 15 + 30 × −0.99 0.2 −10 V/V vˆ = 0.15 × | G | = 1.5 V 15
0
v
in
sig
Rin
C
L
e
sig
C
L
e
sig
e
e
e
| G | = (10/β)10+ 0.025 v
sig
π
= −β R + (βR +1R)(r + R ) − (R /β)R + (Rr + R )
Gv
Without Re ,
v
sig
7.76 Using Eq. (7.113), we have
v
in
in
T
e
| G | = (10/β) +100.025 + R
o
= R R+ R × A = 30.330.3 + 10 × −20 = −15 V/V vˆ = 5 mV ⇒ vˆ = vˆ R + R
Gv
= Vr = 2520mV = 1.25 mA I I = 1.25 mA R = 180 G = R R +R × −α × Total resistance in collector
IE
e
vo
e
which requires a bias currentIE of
= 100, = 0.1 + 0.025 = 80 V/V
For the nominal case, β
Gv
10
nominal
For β
= 50,
Chapter 7–27
Gv
= == low
For β
Gv
10
0.2
150,
high
7.78 Adding a resistance of 100 in series with the 100- Rsig changes the input voltage divider ratio from
+ 0.025 = 44.4 V/V
| |
+ 0.025 = 109.1 V/V
Thus, Gv ranges from 44.4 V/V to 109.1 V/V with a nominal value of 80 V/V. This is a range of 44.5% to 36.4% of nominal.
−
1/gm
10 (1/15)
+
| | ±
1/gm
+ 100 to 1/g + 200
(1/gm )
m
Since this has changed the overall voltage gain from 12 to 10, then
= ((11//gg )) ++ 200 , where g 100
12
m
m
To limit the range of Gv to 20% of a new nominal value, we connect a resistance Re and
10
find its value as follows. With Re ,
A/V = 2.5 mA/V ⇒ g = 0.2 80 For I = 0.25 mA 2I 2.5 = = 2 ×V 0.25 V ⇒ V = 0.2 V
Gv
m
10
nominal
= (10/100) + 0.025 + R
= 0.12510+ R Now, β = 50, G = 0.22510+ R To limit this value to −20% of
D
e
D
OV
e
v
low
10
10 + R = 0.8 × 0.125 + R ⇒ R = 0.275 k = 275 0.225
e
Gv
7.79 For Rin nominal
,
e
e
With this value of Re ,
Gv
=
nominal
= 0.125 10 + 0.275 = 25 V/V 10
v
low
sig
1,
and, with α
VT
r = 2550mV = 0.5 mA g = I /V = 20 mA/V R G = g (R R ) R +R
IC
e
C
T
in
m
v
in
C
L
sig
= 50 50 + 50 × 20 × (10 10) = 50 V/V
Gv
high
7.77 Rin
Rin
and
in
m (RD
sig
0.5
R )
2( 5 5)
m
=
2k n ID , then to change gm by a factor
= 0.67, I must be changed by a factor of (0.67) = 0.45. 2
2
sig
ic
= αi i e
sig
Thus, vo
=iR =i c
sig RC
C
sig
m
1.33
i
L
== 20.5V/+V0.75 × For R = R = 0.75 k 1 = 0.75 ⇒ g = 1.33 mA/V g Since gm
ie
= R +R ×g
in
7.80 Refer to the circuit in Fig. P7.80. Since Rsig re , most of isig flows into the emitter of the BJT. Thus
= g1 = 2 mA1 /V = 0.5 k m
Gv
= R = 50 ,
= 50
re
m
= 0.225 + 0.275 20 V/V ( −20% of nominal) 10 G = (1/15) + 0.025 + 0.275 = 27.3 V/V (+9.1% of nominal)
Gv
OV
OV
e
we use
is in A/V
m
7.81 Rin
25 mV = r = VI = 0.2 = 125 mA T
e
E
gm
0.2 mA = VI 0.025 = 8 mA/V V C
T
D
Gv
= R R+ R in
in
gm (RC RL ) sig
Chapter 7–28
0.125 = 0.125 + 0.5 × 8(10 10) = 8 V/V
ˆ = vˆ
vπ
7.83
Rin
sig
Rin
+R
sig
0.125 = vˆ 0.125 + 0.5 ⇒ vˆ = 50 mV vˆ = G vˆ = 8 × 50 = 400 mV = 0.4 V 10
Rsig
sig
i
sig
o
i
sig
v
1
vsig
RL
= R +R = 2 +2 R
7.82 Av
L
Av Av Av
RL
o
nominal
= 1.5 + R
1
= 5+R
o
v
high
o
nominal
o
o
2
Av Av
nominal
= 2.357 = 0.85 V/V 5
high
v
L
m
m
D
n D
D
At the peak of the sine wave, V = 0.5 = 0.25 mA, thus 2 k i = I + 0.25 = 2.75 mA i = I − 0.25 = 2.25 mA = vˆ + vˆ = 0.05 + 0.5 = 0.55 V vˆ
id
= 5.357
= 0.93 (+10% above nominal) = 1.5 +1.50.357 A = 0.81 (−5% from nominal) 1 = R = 0.357 k g ⇒ g = 2.8 mA/V
= 0.1 × R = 0.1 × 2 = 0.2 k g = 5 mA/V g = 2k I 5= 2×5×I I = 2.5 mA gm
= 1.1 A 5 1.1 × 2 = 2+R 5+R ⇒ R = 0.357 k For Av
0.5 V (peak)
From the figure above, we have o
5
high
50 mV (peak)
o
1.5
low
gm
low
Dmax Dmin sig
D
D
gs
o
7.84
o
m
Rsig/( b + 1)
m
To find ID , we use
=
gm
⇒I
D
re
2 k n ID
=
vsig
gm2 /2k n
ID
RL
2 OV
= 2k V n
= 12 × 2.5 × V ⇒ V = 1.13 V
2 OV
1.6
OV
2
= 2 2.8 × 2.5 = 1.6 mA 1
vbe
ˆ = 0.5 V = 2 k vˆ = 5 mV vo
RL
be
vo
Chapter 7–29
From the figure above we see that
re
(b)
5 mV
= 500 mV
RL
R ⇒ r = 100 = 20 L
e
=
IE
VT
=
re
25 mV 20
Rsig
ai
B
= 1.25 mA
i
At the peak of the output sine wave, we have o
ˆi = Rvˆ = 0.52 = 0.25 mA e
re
vsig
L
RL
Thus,
iEmax
vbe
vo
Rin
= 1.25 + 0.25 = 1.5 mA
and
iEmin
= 1.25 − 0.25 = 1.0 mA
= vv =
=
+ r + βR+ 1 sig
RL
e
2 2
+ 0.02 + 200 101
be
e
RL
o
sig
L
o
From the figure, we have
Gv
ˆ = 10 mV R vˆ = × vˆ r v be
= 0.5 V/V
500 = 12.5 × 10 = 400 mV = 0.4 V 0.4 = Gvˆ = 0.82 = 0.488 V vˆ o
sig
v
(c) Gv o
Thus,
ˆ = Gvˆ = 0.50.5VV/V = 1 V o
v sig
Rout
v
=1 = r + βR+ 1 = 12.5 + 10,000 101 sig
e
= 111.5 Thus, 7.85 IC
re
=
VT IE
= 2 mA
VT IC
=
25 2
Gv
= 12.5
= (β + 1) ( r + R ) = 101 × (12.5 + 500) = 51.76 k (a) Rin
vb v sig
e
L
51.76 = R R+ R = 51.76 + 10
=G
sig
= 0.84 V/V v = vv × vv v o
b
sig
sig
o
+R
out
= 1 × 500 + 111.5 = 0.82 V/V which is the same value obtained in (a) above. For RL
Gv
= 250 ,
=G
RL vo
RL
+R
out
= 1 × 250 250 + 111.5 = 0.69 V/V
b
RL
= 0.84 × R + r
7.86 Rout
= 0.84 × 0.5 +0.50.0125
re
= 0.82 V/V
Rout
L
RL
500
in
in
RL vo
e
= r + βR+ 1 sig
e
25 mV = VI VI = 0.5 = 50 mA T
T
E
C
= 50 + 10,000 = 50 + 99 = 149 101
Chapter 7–30
RL
=
Gv
RL
= R +R R
= − ii
L
Rsig
L
+r + β+1 e
= 10001000 + 149 = 0.87 V Routmax
= 50 +
51
Routmin
= 50 +
10,000 151
= 50 + 196
= 10001000 + 116
L
L
outmin
e
b
B
E
e
e
RB β
(b)
re
RE
vc
ic RC ie
sig
5000
( 1)
( 2)
e
ie
= − r v+ R sig
e
Subtracting Eq. (1) from Eq. (2), we have
β
vsig
e
= + β+1 10,000 250 = r + β+1 5000
E
= −i R = −αi R = i (−r i+RR ) = α r R+ R v
ic
c
C
e
vc
= β +1
100
RE
Y
= r + βR+ 1
re
150
E
+1 + +
= 0.90 V/V 7.87 Rout
E
RE
=
= 50 + 66.2
= R +RR
Gv max
outmax
E
e
e
sig
= 10001000 + 246
L
L
+R )
(re
ib
C
= 116 = R +RR G = 0.80 V/V v min
ie
B
246
=
RB
+
= −β R + (β +R1)(r + R ) v = i R +−ii (Rr + R ) v
If β varies between 50 and 150, then we have 10,000
RC
c
b
out
c
e
sig
e
C
C
C
E
e
E
+ 1 = 50
Substituting in Eq. (1) yields 5000
= r + 50 ⇒ r = 50 150
7.89 With the Early effect neglected, we can write
e
Gv
e
Gv
Rsig RL
=
With the Early effect taken into account, the effective resistance in the collector is reduced
RL
=
+r + β+1 e
1000 1000
+ 50 +
= −100 V/V
10,000
= 0.8 V/V
50
from RC VA ro IC
=
(RC
= 10 k to (R r ), where V = 100 = 100 k 1 mA
vc v sig
=iR b
−i R + i (r + R ) c
B
e
C
o
e
E
k = −100 × 9.1 10 k = −91 V/V
Gv
o
r ) = 10 100 = 9.1 k
Thus, Gv becomes 7.88 (a) Refer to Fig. P7.88.
C
Chapter 7–31
Thus,
7.90
|G | = i Rsig
0
ro
0.1
where ro and
G
i 1
ro
o
=
IC
=v
sig
(RL ro )
= vv = vv =
Gv
o
o
sig
g
1
+g
(RL ro )
o
(1)
ro
m
L
o
v
o
m
From Eq. (1), we have
gm
= 49
0.2
0.125
125
41.2
0.5
0.050
50
55.6
1.0
0.025
25
57.1
1.25
0.020
20
55.6
(2)
the low value to minimize power dissipation. The required value of IC is found by substituting for ro and 1/gm from Eqs. (2) and (3), respecti vely, in Eq. (1) and equating Gv to 50. The result (after some manipulations) is the quadratic equation.
− 2.25I + 0.625 = 0 C
=
Substituting in Eq. (2) and solving for ro gives
ro
v
27.5
Observe that initially Gv increases as IC is increased. However, above about 1 mA this trend reverses because of the effect of ro . From the table we see that gain of 50 is obtained for IC between 0.2 and 0. 5 mA and also for IC above 1.25 mA. Practically speaking, one normally uses
IC2
ro
1
| G | ( V /V )
250
| |
m
r = 0.98 + g1 With R = 500 , (500 r ) = 0.49 G = 1 (500 r ) + g
=
r o ( k )
0.250
Q.E.D.
With RL removed,
Gv
(3)
IC mA
1 /g m ( k )
0.1
Noting that ro appears in effect in parallel with RL , v o is obtained as the ratio of the voltage divider formed by ( 1/gm ) and ( RL ro ),
(2)
0.025 V
=
I C ( m A)
vg
are in kilohms and are given by
C
VT
gm
v
RL
gm
m
A
1
vg vsig
1
(1)
V = VI = I25mA C
gm
+g
10 ro 1
v
The two roots of this equation are IC 0.325 mA and 1.925 mA; our preferred choice is IC 0.325 mA.
=
= 25,000 = 25 k 7.92
Thus 1
gm
=
25,000
49
VDD 9 V
⇒ g = 1.96 mA/V m
ID
7.91 Adapting Eq. (7.114) gives
G = −β R + (β + 1)r = − R R Rβ + r1 + r RC RL ro
v
L
β
= − RR R 1r +g β C
L
VD VG VS
o
sig
β
RD
e
sig
C
R
G1
o
sig
m
e
R G2
RS
Chapter 7–32
ID ID
= 1 mA = 12 k V
7.93
2 OV
n
5 V
= 12 × 2 × V ⇒V = 1V V = V +V = 1+1=2V V Now, selecting V = =3V 3 I R =3 3 R = = 3 k 1 2 OV
1
RD
OV
GS
t
ID
0
VG 0
OV
DD
S
D
RG 10 M
S
RS
S
5 V
Also,
ID RD
= V3 = 3 V DD
For ID
3
D
G
S
n
2 OV
= 12 × 1 × V ⇒V =1V V = V +V = 1+1=2V 2 OV
GS
OV
Thus the voltage drop across RG 2 (5 V) is larger than that across RG 1 (4 V). So we select
RG2
= 2k V
0.5
⇒ R = 1 = 3 k V = V +V =3+2=5V
= 0.5 mA
1
GS
VG
22 M
=
t
OV
Since
VS
0 V,
which leads to
RG1
RS
= 45 VV ⇒ R = 0.8R = 0.8 × 22 = 17.6 M G2
+
VD
= 18 M
=V
DD
− =−
= +2 V
and
RD
Note that this will cause VG to deviate slightly from the required value of 5 V. Specifically,
VG
S
VD is required to be halfway between cutoff ( 5 V) and saturation ( 0 Vt 1 V). Thus
Using only two significant figures, we have
RG1
− 2 = 6 k = 5 0.5
7.94
VDD 15 V
RG2
+R = 9 × 22 22 + 18 = 4.95 V RG2
G1
It can be shown (after simple but somewhat tedious analysis) that the resulting ID will be ID 0.986 mA, which is sufficiently close to the desired 1 mA. Since VD VDD ID RD 6V and VG 5 V, and the drain voltage can go down to VG Vt 4 V, the drain voltage is 2 V above the value that causes the MOSFET to leave the saturation region.
=
− =
2V
C
RG2
G1
VGS
= =− =− − − 5 = V I ( ) = − 20.5+ 5 = 6 k
and determine RG1 from
=
−
+
10 M
RG1
RD
5.1 M
RG2
RS
Chapter 7–33
VG
=V
RG2 DD
which is the maximum value. The minimum value can be obtained by using k n 0.2 mA/V2 and Vt 1.5 V in Eq. (1),
+R 5.1 = 15 × 10 + 5.1 = 5.07 V k = 0.2 to 0.3 mA/V V = 1.0 V to 1.5 V 1 I = k (V − V ) 2 With R = 0, I = 1 k (V − V ) 2 RG1
= = 1 I = × 0.2(3.57 − 0.62I ) 2 = 0.1(3.57 − 2 × 3.57 × 0.62I + 0.62 I 0.038 I − 1.442I + 1.274 = 0
G2
D
2
n
2
t
D
n
n
Here again, the physically meaningful answer is 0.91 mA, which is the minimum value of ID . ID Thus with a 0.62-k resistance connected in the source lead, the value of ID is limited to the range of 0.91 mA to 1.5 mA.
=
IDmax is obtained with Vtmin and k nmax : IDmax
D
= 37 mA or 0.91 mA
ID
2 t
G
2 2 D)
which results in
S
D
2
D
2 D
2 t
GS
D
= 12 × 0.3(5.07 − 1) = 2.48 mA 2
IDmin is obtained with Vtmax and k nmin :
= 12 × 0.2(5.07 − 1.5) = 1.27 mA With R installed and V = 1 V, k = 0.3 mA /V , we required I = 1.5 mA: 1 1.5 = × 0.3(V − 1) 2 ⇒ V = 4.16 V Since V = 5.07 V,
7.95
2
IDmin
S
VDD
t
2
n
D
2
GS
RD
RG1
ID
GS
VG 5 V
G
VS VG Thus,
=
RS
ID
− V = 5.07 − 4.16 = 0.91 V GS
RS
RG2
3 k
= VI = 0.91 = 607 1.5 S
D
From Appendix J, the closest 5% resistor is 620 . With RS 620 ,
=
VS
= I R = 0.62I = V − V = 5.07 − 0.62I = 12 k (V − V ) D
S
VGS
G
ID
n
D
S
GS
t
ID
2
D
t
n
n
GS
t
ID D
D
2
2
2 D
D
D
2
S
2 D
= 2 × 0.3(4.07 − 0.62I ) = 0.15(4.07 − 2 × 4.07 × 0.62I + 0.62 I 0.058I − 1.757I + 2.488 = 0 2 D
D
D
2
ID
S
= 2 × 2( 5 − 3I − 1) = 16 − 24I + 9I 9I − 25I + 16 = 0
t
1
D
1
2
2
= I R = 3I = 5 − V = 5 − 3I = 12 k (V − V )
VGS D
= 12 k (5.07 − 0.62I − V ) For k = 0.3 mA/V and V = 1, n
VS
2 2 D)
D
which results in
1.78 mA or 1 mA
= The first answer is physically meaningless, as it would result in V = 5.33 V, which is greater than V , implying that the transistor is cut off. Thus, I = 1 mA. If a transistor for which k = 3 mA/V is used, S
G
D
n
ID
= 28.8 mA, or 1.49 mA
The first value does not make physical sense. Thus,
ID
= 1.49 mA 1.5 mA
then
= 12 × 3(5 − 3I − 1) = 1.5(16 − 24I + 9I )
ID
D
2 D
2
2
Chapter 7–34
9ID2
5 V
− 24.67I + 16 = 0 D
whose physically meaningful solution is
ID
= 1.05 mA
RD
ID
7.96
RG
VD
VS
ID
VDD
RS
RD ID
5 V
VG 5 V VS 2 V ID
RS 2 k
Maximum gain is obtained by using the largest possible value of RD , that is, the lowest possible value of VD that is consistent with allowing negative voltage signal swing at the drain of 1 V. Thus
−1=v =V −V = 0−1 ⇒V =0V
VD ID
2V
= 2 k = 1 mA 1
V t )2
k n (VGS
VD
=2 − 1 1 = × 2( V − V − V ) 2 G
S
t
t
VDD
0
D
2
7.98
t
D
GS
S
S
D
ID VS
VDD 10 V
D
G
IG
D
D
4ID2
R1
2
D
R2
GS
G
S
0.5
VS
VD 3 V ID 1 mA
= 0.5 mA = 12 × 4(V − 1) ⇒ V = 1.5 V Since V = 0 V, V = −1.5 V, and −1.5 − (−5) = 7 k R = GS
RS ID
VG
− 15I + 12.25 = 0 = 1.2 mA = 2.4 V
7.97 ID
S
ID RD D
2
t
S
t
= = − 0 = 5 − 0.5 × R ⇒ R = 10 k
= (5 − 2 − V ) V =2V If V = 1.5 V, then we have V = I R = 2I V = V − V = 5 − 2I 1 I = × 2(5 − 2I − 1.5) 2 1
G
where we have assumed that the signal voltage at the gate is small. Now,
But
ID
Dmin
D
2
ID
= 1 mA and V = 3 V D
Thus,
RD
V = VI = 13mA = 3 k D
D
RD
Chapter 7–35
For the transistor to operate 1 V from the edge of saturation
VD
7.99
VDD
= V + |V | − 1 G
t
Thus,
= V + |V | − 1 V + |V | = 4 V (a) |V | = 1 V and k = 0.5 mA/V 3
G
G
t
t
VG R2
p
RS
µ
VSS
G
VD
=3V = 3 k = 12 k (V − |V |)
µ
G
p
SG
(a) VGS
ID
2
t
S
Vt
p
0 2
t
2V
R2
=
R1
= V I− V = 108 VA = 0.8 M
IG
= 10
DD
µA
= 0.2 M
G
µ
G
L
t
t
−V)
(VGS
t
2
ID K
+
ID K
+I
D RS
=V
SS
+ 2√I1 /K D
∂ ID K ∂ K ID
1 ∂ ID
RD
1
K
= 1 + 2√1KI
D
Vt
SG
S
S
G
∂K
=0
RS
D
S
2
µ
µ
D
D
=2 − | |) 1 1 = × 1.25(V − 2) 2 V = 3.265 V V = V + 3.265 = 2 + 3.265 = 5.265 V 10 − 5.265 = 4.7 k R = 1 SG
∂ ID
= 1/ 1 2 KI R ] Q.E.D K (b) K = 100 A/V , = ±0.1, and K V = 1 V. We require I = 100 A and I = ±0.01. Thus, I ID /ID
I SKD
2
p (VSG
S
D
k
ID
D
2
[ +
I SKD
− KI + R ∂K
t
=3V = 3 k
2
Differentiating relative to K , we have
1
| | = 2 V and k = 1.25 mA/V = 4 − |V | = 2 V
W
Thus,
D
VG
SS
GS
S
(b) Vt
n
⇒V =V +
G
DD
= 12 k GS
SG
S
=V
D RS
= K (V − V )
2
SG
+I
But
= 12 × 0.5(V − 1) ⇒V =3V V = V +3 = 3+3= 6V R = V −V I = 10 − 6 = 4 k 1
VD
ID
− V = 7 V = 0.7 M I 10 A
V DD
=
VG
VGS
RG
G
R1
ID
0V 2
=3V = VI = 103 VA = 0.3 M G
RD
RD ID
t
0.01
0.1 K /K 0.10 Substituting in the expression derived in (a),
=
=
=
2
= 1 + 2√0.11 × 0.1R ⇒ R = 45 k 0.1
S
To find VGS , 2
= K (V − V ) 100 = 100(V − 1)
ID
GS
t
GS
2
S
Chapter 7–36
=2V V +I R = V 2 + 0.1 × 45 = 6.5 V (c) For V = 5 V and V = 2 V, I R =3V 3 R = = 30 k 0.1 VGS GS
D
S
SS
SS
D
GS
S
Differentiating relative to Vt , we have 1
+ 2√21I /k D
∂ ID ∂ Vt ∂ ID ∂ Vt
√
1
=−
1
ID
1
= 1 + 2√0.1 × 0.1 × 30 = 7
ID
= 17 × KK = 17 × ±10% = ±1.4%
ID
n
∂ ID
GS
t
∂ Vt
Vt
t
D
n
1
t
t
t
t
t
V t )2
− = − V 2V− V = − V2V 2
t
For Vt
VOV
t
Q.E.D
OV
t
t
=S
ID
ID Vt
Vt
=−
Vt
= 12 k V ⇒ V = n
2 OV
OV
GS
⇒V =V + GS
t
t
OV
D
S
t
D
OV
D
require I
SVDt
=1
−1 = − 0.252 ×+ 0.5 2I R ⇒ I R = 0.375 V For I = 0.1 mA, 0.375 = 3.75 k R = 0.1 D
S
S
VDD 10 V
t
RG
2
10 M
Vt
+
kn
kn
+I
0
RD 10 k ID ID
2 ID
VGS 2 ID
kn
7.101
Thus
2 ID
D RS
= 12 k (V − V ) n
= − V +2V2I R Q.E.D V For V = 0.5 V, = ±5%, and V I V = 0.25 V, to limit to +5% we I
where VGS is obtained from
ID
D RS
But
(b) For fixed bias at the gate VG and a resistance RS in the source lead, we have GS
+I
S
Vt
= V +I
ID 2k n
D
× 0.5 × ±5% = − 2 0.25 = ∓20% VG
D
= 0.5 V, VV = ±5%, and
= 0.25 V, we have
ID
ID
Thus
t
GS
t
t
GS
D
GS
1
t
n
k n (VGS
√21k I + R
I
GS
D
S
∂ ID V t
= ∂V
SVDt
= − k (V I − V )V I = − k (V − V )V ≡ ∂∂ VI
I
SVDt
=0
∂ Vt
Thus 2
= − k (V − V ) n
∂ ID S
S
ID
SVt
7.100 (a) With a fixed VGS ,
= 12 k (V − V )
+R
n D
ID
ID
∂ Vt
+ R = −1
2 k n ID
S
SK
2 ∂ ID n kn
D RS
=V
G
VDS
Chapter 7–37
= V −I R = 10 − 10I (a) V = 1 V and k = 0.5 mA/V 1 I = k (V − V ) 2 VGS
DD
D
7.103
D
D
t
n
D
n
GS
t
= 2 × 0.5(10 − 10 I − 1) ⇒ I − 1.84I + 0.81 = 0 D
2 D
~ – 1 mA
2
1
ID
VDD 5 V
2
RD
2
R G1
ID 1.11 mA or 0.73 mA The first root results in VD 0.11 V, which is physically meaningless. Thus
=
VD IG
D
=−
= 0.73 mA V = V = 10 − 10 × 0.73 = 2.7 V (b) V = 2 V and k = 1.25 mA/V 1 I = × 1.25(10 − 10I − 2) 2 ⇒ I − 1.616I + 0.64 = 0 I = 0.92 mA or 0.695 mA
1 mA
R G2
ID
G
D
t
2
n
D
D
2 D
D
D
The first root can be shown to be physically meaningless, thus
ID VG
ID
= 12 k V n
2 OV
2
= 0.695 mA = V = 10 − 10 × 0.695 = 3.05 V D
= 12 × 8V ⇒ V = 0.5 V OV
Since the transistor leaves the saturation region of operation when v D < VOV , we select
VD
=V +2 OV
VD 2.5 V Since IG ID , we can write
=
RD
7.102
2 OV
1
= I− V = 5 −12.5 = 2.5 k = V + V = 0.8 + 0.5 = 1.3 V V DD
D
D
VGS
t
OV
Thus the voltage drop across RG2 is 1.3 V and that across RG 1 is ( 2.5 1.3) 1.2 V. Thus RG2 is the larger of the two resistances, and we select RG2 22 M and find RG1 from
5V
−
RG
0
RD ID
RG1
VD VG VGS
RG2
=
= = 1.2 ⇒ R = 20.3 M 1.3 G1
Specifying all resistors to two significant digits, we have RD 2.5 k , RG1 22 M, and RG1 20 M.
=
=
RB1 RB1 RB2
7.104
+
=
× 3 = 0.710
⇒ RR = 3.225 B2 B1
= 0.2 = 12 × 10(V − V ) ⇒ V = 1.2 V 5 − 1.2 R = = 19 k 0.2 ID
GS
GS
D
t
2
Given that RB1 and RB2 are 1% resistors, the maximum and minimum values of the ratio RB2 /RB1 will be 3.225 1.02 3.2895 and 3.225 0.98 3.1605. The resulting VBE will be 0.699 V and 0.721 V, respectively. Correspondingly, IC will be
×
=
×
=
Chapter 7–38
= 1×e
IC max
−
(0.710 0.699)/0.025
7.106
= 1.55 mA
VCC 9 V
and
IC min IC min
0.06mA
= 1×e − = 0.64 mA
(0.710 0.721)/0.025
0.6mA
RC
R1
VCE 3 V
VCE will range from VCEmin
3
1.55
2
0.1 V
=impossible, − × implying = − that the transistor which is will saturate at this value of dc bias!
VCEmax
RE
R2
RC
VB
VCC 3 V
R2
=∞ = R = 0.6 = 5 k 3V
E
9 + R = 0.06 = 150 k = V + V = 3 + 0.7 = 3.7 V 3.7 = 0.06 = 61.7 k 2
E
R
RC 2 k VCE
RB
1
BE
150
=
61.7
−
88.3 k
=
Using 5% resistors from Appendix J, and selecting R1 and R2 so as to obtain a VBB that is slightly higher than 3.7 V, we write
= 82 k and R = 62 k R = 5.1 k and R = 5.1 k R = 9 × 62 62 V =V + 82 = 3.875 R +R V −V I = R R + β+1
R1
IB
2
E
C
2
BB
CC
1
To obtain IC
IC β
=
BB
= 1 mA, we write
1 mA 100
−V
3
BE
where
− 0.7
230 k
IB 0.01 Since β ranges from 50 to 150 and IB is fixed at 0.01 mA, the collector current IC will range from 0.01 50 0.5 mA to 0.01 150 1.5 mA. Correspondingly, VCE will range from (3 0.5 2) 1 V to ( 3 1.5 2) 0 V. The latter value implies that the high-β transistor will leave the active region of operation and saturate. Obviously, this bias method is very intolerant of the inevitable variations inβ . Thus it is not a good method for biasing the BJT.
=
× = − × =
B
E
= 0.01 mA
= R R = 62 82 = 35.3 k 3.875 − 0.7 I 0.58 mA = 5.1 + 35.3 = 91 V = 0.58 × 5.1 = 3.18 V = 3.88 V 90 I = αI = × 0.58 = 0.57 mA 91 V = 6.1 V V I = = 3.88 = 0.063 mA R 62 RB
V CC
2
BE
E
Thus,
RB
Initial design: β
R1
7.105
=
3V
= 3 − 0.64 × 2 = 1.72 V
It should be clear that this biasing arrangement is useless, since even the small and inevitable tolerances in RB1 and RB2 caused such huge variations in IC that in one extreme the transistor left the active mode of operation altogether!
IB
3V
=
×
=
− × =
1
E
E
B
C
E
C
B
R2
2
2
Chapter 7–39
IB IR1
= β I+ 1 = 0.58 = 0.006 mA and 91 = 0.069 mA E
0.57
⇒ β = 75.7
VCC 9 V 0.3mA
0.6mA
R RC
1
VB
3V
7.108 Refer to Fig. 7.52.
3V
(a) IE
R2
RE
3V
=∞ = R = 0.6 mA = 5 k
Initial design: β
R1
R2 R1
IE
IE
IE
3V
E
9 + R = 0.3 = 30 k 2
VB
VE
VBE
= R = 5.1 k R = 18 k , R = 13 k 13 = 3.774 V V =9× 13 + 18 V −V I = = 3.77418− 0.713 = R R R + 5.1 + β +1 91 RE
2
BB
BB
E
BE
1
VE
= I R = 3.02 V
VB
= 3.72 V = αI = 90 × 0.593 = 0.586 mA 91 = V − I R = 9 − 0.586 × 5.1 = 6 V
E
E
C
C
IC falls to the value obtained in Problem 7.106, namely, 0.57 mA at the value of β obtained from IC
=α
−V + Rβ + R1
VBB RE
B
= V − VR R + 101 BB
BE
1
2
BE B
E
= V − VR R + 151 BB
high
BE B
E
= V − RV R + 51 BE
low
BE B
E
0.95 V RE
− VR + 101
BB
BE B
= −
=
V BB
/R + R101 R /R 1+ 51
1 0.95
+ R51
VBB
−V
E
B
E
nominal
×
VBE
RE
B
B
⇒ RR = 5.73 B
E
For this value,
IE
0.593 mA
CC
BE
Let’s constrain IE low to be equal to IE 0.95 and then check IE high :
2
E
E
−V + β R+ 1
nominal
C
1
VC
VBB RE
=
3.7 V
= + = = 3.7 = 12.3 k 0.3 = 30 − 12.3 = 17.7 k
If we select 5% resistors, we will have
IC
+ +
= 5.1(ββ +×13.074 ) + 7.548
7.107
RC
−
3.774 0.7 18 13 5.1 β 1
= β β+ 1
IE
IE
nominal
low
high
= 0.946
= 0.90
= 0.963
VBB
BE
RE
−V
BE
RE
VBE
−V
= =
BE
RE
0.95 IE
1.02 IE
Thus, the maximum allowable ratio is
RB RE
= 5.73
(b) IE
=
+− VBB
RE 1
VBE R B /RE β
+1
nominal
nominal
Chapter 7–40
V = V −5.73 1+ β+1 BB
IE RE
BE
7.109
V = V −5.73 1+ 101 ⇒ V = V + 0.352V (c) V = 5 V VCC
BB
5 V
BE
3
BB
BE
CC
CC
VBB
0.7
0.352
RC
IC
VC
IB
5
2.46 V
= + /3× = = V I /3 = 50.5 = 3.33 k CC
RE
E
RB
IE
= 5.73 × R = 19.08 k
RB
E
VBB
2.46
RE
R2
=V
CC
+R
R1
2
5 V
R2
= 5R + R 1
2.46R1
2
R1 R2
Required: IC
= 5 R + R = 5R
B
1
2
VB VE
1
R2
1
1
1
CE
RB
1
CC
C G
=0 = −0.7 V
IE
37.5 k
−R = (d) V = V − R I 1 = 5 − R × 0.99 × 0.5 ⇒ R = 8.1 k =
C
− (−5)
RE 8.6 k
E
⇒R = V = V + 2 = −0.7 + 2 = +1.3 V V −V = 5 −0.51.3 = 7.4 k R = I = 50 (b) β I = 51 = 0.5 0.01 mA I 51 I R = 0.5 × 8.6 = 4.3 V I R = 0.1I R = 0.43 V 0.43 = 0.01 = 43 k R E
E
CC
C
C
C
C
min
Check design:
E
=V
R2
CC
R1
37.5 + R = 5 × 37.5 + 38.8 2
= 2.46 V R = R R = 37.5 38.8 = 19.07 k 0.7 I = 2.46 −19.07 = 0.5 mA 3.33 + 101 0.7 = 2.46 −19.07 = 0.475 mA I 3.33 + 51 B
1
2
E nominal
E low
which is 5% lower than IE
IE
high
=
nominal
, and
which is 1.8% higher than IE
Bmax E
nominal
.
E
Bmax
Bmax
E
E
Bmax
(c) Standard 5% resistors:
= 43 k R = 8.2 k R = 7.5 k (d) β = ∞: V = 0, V = −0.7 V −0.7 − (−5) = 0.52 mA I = 8.2 I = 0.52 mA V = 5 − 0.52 × 7.5 = 1.1 V RB E
C
B
− 0.7 = 0.509 mA 19.07 3.33 + 151 2.46
E
4.3
=R
=
C
C
VE
0.5
=
= 0.5 mA and V = V + 2.
=∞
(a) β
= 5 × 19.08 ⇒ R = 38.8 k
VBB
VE
E
C
C
E
Chapter 7–41
= 50: 5 − 0.7 = 0.48 mA I = 43 8.2 + 51 V = −5 + 0.48 × 8.2 = −1.064 V V = −0.364 V 50 I = αI = × 0.48 = 0.47 mA 51
where β is the increased value of 150,
β
IC
E
= 150 × 0.435 mA 151
= 0.432 mA
E
Thus,
B
IC
C
E
VC
5
0.47
= −
7.5
×
= 0.432 − 0.39 = 0.042 mA
for a percentage increase of IC
1.475 V
× 100 = 0.042 × 100 = 10.8% 0.39
IC
=
7.111
7.110
3 V 3 V
IE RC IE/(b 1)
RC
VC
VC IC RB
0.7 V IE
RE
0.4 mA
3 V
RE
= V +1V = 1.3 V 3 − 1.3 = 0.5 mA I = R ⇒ R = 3.4 k I 0.5 = 101 0.005 mA I = β +1 V = V +I R 1.3 = 0.7 + 0.005 × R ⇒ R = 120 k
VC
− (−3) = −0.70.4
CE sat
E
C
= 5.75 k
C
±
To maximize gain while allowing for 1 V signal swing at the collector, design for the lowest possible VC consistent with
− 1 = −0.7 + V = −0.7 + 0.3 = −0.4 V V = 0.6 V V −V − 0.6 = 6.2 k = 3 0.39 R = I VC
C
BE
B
B
B
CEsat
B
Standard 5% resistors:
C
CC
E
B
RC
C
C
= 3.3 k
C
As temperature increases from 25◦ C to 125◦ C, (i.e., by 100◦ C), VBE decreases by 2 mV 100
− 200 mV. Thus I
E
0.2 V
× 0.2 V = increases by R
=
=
=
E
0.035 mA to become 0.435 mA. The 5.75 k collector current becomes
IC
= β +β 1 × 0.435
RB 120 k If the actual BJT has β
= 50, then − V I = = 3 − 0.7 = 0.41 mA R 120 R + 3.3 + β +1 51 V = 3 − I R = 3 − 0.41 × 3.3 = 1.65 V VCC
BE
E
B
C
C
E
C
Allowable negative signal swing at the collector is as follows:
VC
−V
CE sat
= 1.65 − 0.3 = 1.35 V
Chapter 7–42
3 V
An equal positive swing is just possible. For 150: β
IE
= =
VC
− 0.7 = 0.56 mA 120 3.3 + 151 = 3 − I R = 3 − 0.56 × 3.3 = 1.15 V 3
E
RC IC 2IB 2 IB
C
RB1
Allowable negative signal swing at the collector 1.15 0.3 0.85 V. An equal posit ive swing is possible.
=
−
=
IC 1 mA
0.7 V IB
I B2 I B
R B2
7.112 3 V
Figure 2
1.01 mA
RC
IB
0.01 mA
1.5 V 1 mA
1 = Iβ = 100 = 0.01 mA
RB2
C
0.7 = 0.7 = 0.01 I B2
RB
= 70 k 1.5 = 2I R + 0.7 0.8 = 2 × 0.01 × R R = 40 k 3 − 1.5 1.5 = 1.02 = 1.47 k R = 2I I + For β = ∞: 0.7 I = 0, I = = 0.7 = 0.01 mA R 70 I = I = 0.01 mA V = 0.01R + 0.7 = 0.01 × 40 + 0.7 = 1.1 V 3 − 1.1 − 1.1 = 1.29 = 3 1.47 I + 0.01 = R I = 1.28 mA B
B1
B1
Figure 1
B1
C
C
(a) From the circuit diagram of Fig. 1, we can write 3 − 1.5 = 1.01 1.5 k mA 1.5 = 0.01R + V = 0.01R + 0.7 ⇒ R = 80 k
RC
B
BE
B
B
(b) Selecting 5% resistors, we have
B
B
B2
B2
B1
B2
C
B1
C
= 1.5 k R = 82 k V −V I = R R + β +1 3 − 0.7 0.99 mA 82 = = 1.5 + 101 I = α I = 0.99 × 0.99 = 0.98 mA V = 3 − 1.5 × 0.99 = 1.52 V (c) β = ∞: V −V = 3 −1.50.7 = 1.53 mA I =I = R V = 0.7 V RC B
CC
BE
E
B
C
C
C
C
7.113
I
E
VC
C
CC
C
BE
E
C
C
(d) From the circuit diagram of Fig. 2, we can write
IB
RB
IC
Chapter 7–43
= 1 mA I = I +I = I + Iβ IC
C
7.115
B
VCC
C
C
R1
I IO
= + 1
1 1
I
β
0
= 1.01 mA
VC
Q1
IB R B
1.5 V
VB
VBE
I
= = + 1.5 = 0.01 × R + 0.7 R = 80 k B
Q2
IO
RE
B
R2 7.114 Refer to the circuit in Fig. P7.114. Replacing VCC together with the voltage divider (R1 , R2 ) by its Thévenin equivalent results in the circuit shown below.
= V −RV+ R− V +V V = IR + V V =V −V +V −V V = IR + V = (V − V − V ) R R R + V + +V − V V = Rα (V − V − V ) R R+ R I = R CC
I
BE 1
BE 2
1
IO aIE
B
2
E3
B
E3
2
BE 2
BE 1
BE 3
BE 2
2
BE 1
BE 3
2
IE /(b1)
CC
BE 1
BE 2
BE 1
1
BE 2
RB IE
VBB
BE 3
E
O
E
E
RE
=V
CC
R1
BE 2
IO
2
IO
and
RB
2
= β I+ 1 R + V + I R E
B
BE
E
E
−V R )/(β + 1)
VBB
BE
= R + (R I = αI = α VR [+R (/(RR +R R)/(β)] −+ V1) IE
E
C
1
2
E
CC E
2
1
1
=R
2
BE 2
= 2R
BE 3
2
2
BE
VB
BE
CC
BE
BE
Q.E.D
E
I
= V2
CC
= V2 + V CC
= (V − 2V B
BE
BE )/R2
=
VCC 2
−V
BE
But since I must be equal to IO , we have
VCC 2R E
=V
CC /2
−V
R2
2
and the currents in all junctions
BE 3
V CC
IO RE
Now,
VBB
1
Thus,
= (R R ) 1
BE 2
=V =V =V = R1 (V − 2V ) × 12 + V
VBE1
E
+R
BE 1
BE 1
where
VBB
2
CC
+V +V −V Now, for R1 equal,
R2
2
BE
R2
Chapter 7–44
Thus,
R1
=R =R
E
2
VCC
BE
VCC
7.117 Refer to the equivalent circuit in Fig. 7.55(b).
E
To obtain IO
V CC
G
G
E
10
m (RD
sig
R r ) L
o
E
7.118 (a) Refer to Fig. P7.118. The dc circuit can be obtained by opening all coupling and bypass capacitors, resulting in the circuit shown in Fig. 1.
E
1
gm (RD RL ro ) sig
= − 1010+ 1 × 3 × (10 20 100) = −17 V/V
= 0.5 mA,
= 2R = 2R ⇒ R = 10 k R = R = 8.6 k E
in
in
BE
2
0.5
= − R R+ R = − R R+ R g Gv
= 10 V and V = 0.7 V, = R = R 10 −101.4 = 0.86R
For VCC
R1
− 2V
2
7.116
5 V
IE
50.7 R
R
0.7 V
IO
Figure 1
= αI 0.5 mA = 0.5 mA ⇒ R = 5 −0.50.7 = 8.6 k = 0.7 − V = 0.7 − 0.3 v = +0.4 V
IO
E
See analysis on figure.
IE
C max
VGS VOV
= 2−1=1V = V − V = 1 − 0.7 = 0.3 V GS
t
Since VD at 2.5 V is 1.2 V higher than VS VOV 1 0.3 1.3 V, the transistor is
EC sat
+
= +
=
This figure belongs to Problem 7.118.
Rsig
vsig
R G1
RG2
vgs
gmvgs
Rin RG RG1 // RG2 Figure 2
ro
RD 5 k
RL 5 k
vo
Chapter 7–45
indeed operating in saturation. (Equivalent VD 2.5 V is higher than VG Vt 1.3 V by 1.2 V.)
=
− =
= 12 k V
ID
n
OV
G2
⇒ R = 0.3 = 5 k S
(b) Gv where
D
A
D
L
sig
G
gs
DS
v
D
D
v
sig
= −2.5 + I
VD
gs
= −2.5 + 0.3 × 5 = −1 V
D RD
To remain in saturation,
|A | = g v
m (r o
R R ) = 8.1 V/V D
ˆ ≤ vˆ + |V | −1 + 10 vˆ ≤ −vˆ + 0.7 vD
L
To remain in saturation, GS
t
gs
gs
ˆ = 0.154 V
and the corresponding output voltage
− 1.3 = 0.132 V ˆ = 2.59.1 sig
The corresponding amplitude at the output will be
| G |vˆ = 4.1 × 0.264 = 1.08 V (d) To be able to double vˆ without leaving saturation, we must reduce vˆ to half of what
sig
D
v
sig
sig
tp
where
= −2.5 + I
= −2.5 + 0.3R
D RD
D
and
|G | = g
sig
v
gs
ˆ
would be its new value; that is, we must keep v gs unchanged. This in turn can be achieved by connecting an unbypassed Rs equal to 1/gm , 1 = 3.33 mA = 300 /V Since vˆ does not change, the output voltage also will not change, thus vˆ = 1.08 V. o
sig
v
VD
sig
gs
ˆ = | G |vˆ = 1.54 V (d) If vˆ = 50 mV, then V + | G |vˆ = −vˆ + |V | vd
The corresponding value of vˆ is + 120 = 2 × 0.132 = 0.264 V = vˆ 120120 vˆ
Rs
sig
v sig
v gs
gs
tp
Satisfying this constraint with equality gives
This is satisfied with equality at
G
sig
ˆ ≥ vˆ − V 2.5 − 8.1vˆ ≥ 2 + vˆ − 0.7 v DS
v
sig
sig
where
where
sig
D
G
G min
D
GS
D
D
in
o
= V2I = 2 ×0.30.3 = 2 mA/V
−10 = −2R ⇒ R = 5 k (c) v = 0 V ( dc) + v = −vˆ v vˆ = V + | G |vˆ
= − R R+ R g (r R R ) = − 120120 + 120 × 3.33 × (100 5 5) = −4.1 V/V (c) V = 2 V, V = 2.5 V = 2 + vˆ , vˆ = 2.5 − | A |vˆ vˆ m
m RD
Thus,
D
in
gm
= −g OV
50 = VI = 0.5 = 100 k
Gv
SG
S
OV
ro
OV
1.5
= R R = 300 k 200 k = 120 k = V2I = 2 ×0.30.5 = 3.33 mA/V
gm
S
tp
D
2
(b) The amplifier small-signal equivalent-circuit model is shown in Fig. 2. G1
SG
G
3
n
n
Rin
(a) DC bias:
|V | = 0.3 V ⇒ V = |V | + |V | = 1 V Since V = 0 V, V = V = +1 V, and 2.5 − 1 = 0.3 mA I = R
2 OV
= 12 k × 0.3 ⇒ k = 11.1 mA/V 0.5
7.119 Refer to Fig. P7.119.
m RD
= 2R
D
Thus
−2.5 + 0.3R + 2R vˆ = −vˆ + |V | −2.5 + 0.3R + 2R × 0.05 = −0.05 + 0.7 0.4R = 3.15 ⇒ R = 7.875 k G = −g R = −2 × 7.875 = −15.75 V/V D
D sig
D
D
D
D
v
m
D
sig
tp
Chapter 7–46
= − 1010+ 1 × 2 × (100 12.5 10) = −9.6 V/V
7.120 Refer to Fig. P7.120.
= g1 = 50
Ri2
m2
(d) If terminal Y is grounded, the circuit becomes a CD or source-follower amplifier:
⇒ g = 501 A/V = 20 mA/V m2
r ) r ) + g1 = (9.5 100) 1 = 0.946 V/V (9.5 100) + 2 vz
If Q1 is biased at the same point as Q2 , then
gm1 id 1
= g = 20 mA/V = g × 5 (mV) m2
= 20 × 0.005 = 0.1 mA = i × 50 v = 0.1 × 50 = 5 mV v = i R = 1V 1V = 10 k R = 0.1 mA d1
o
o
Looking into terminal Z, we see Ro :
d1
o
(RS
(RS
m
m1
d1
=
vx
Ro
= R r g1 S
o
m
D
1
= 9.5 100 2 = 473
D
(e) If X is grounded, the circuit becomes a CG amplifier. 7.121 (a) DC bias: Refer to the circuit in Fig. P7.121 with all capacitors eliminated:
Rin at gate
=
= R = 10 M = −V , where V G
VG 0, thus VS obtained from
GS
RD
can be
GS
vy
= 12 k V
ID
n
2 OV
1 2
2 OV
vsg
= ×5×V ⇒ V = 0.4 V V = V + 0.4 = 0.8 + 0.4 = 1.2 V V = −1.2 V −1.2 − (−5) = 9.5 k R = 0.4 0.4
GS
t
Rsig 100 k
S
S
The figure shows the circuit prepared for signal calculations.
To remain in saturation, the minimum drain voltage must be limited to VG Vt 0 0.8 0.8 V. Now, to allow for 0 .8-V negative signal swing, we must have
−
VD
− =
=−
RD
= (b) gm
=
m
=V
12
100 9.5
(k )
= (=2 × 12.5) × 0.024 = 0.6 V
OV
40 = 0.4 = 100 k
7.122 (a) Refer to the circuit of Fig. P7.122(a):
Av o
(c) If terminal Z is connected to ground, the circuit becomes a CS amplifier,
Gv
g1
Rsig RS
(gm RD )v sg
vy
12.5 k
= = 2 ×0.40.4 = 2 mA/V
0.4 2 ID
ID
= 0.024 V
−0
VA
sig
= 50 × 10−3 (mA)
=0V 5
=i ×
v sg
and
ro
isig 50 A
RS
OV
RG
vy
= − v = R + R × −g sig
G
sig
m (ro
10
o1 i
10
+ g1
m
R R ) D
≡ vv =
L
Ro
1
=
10 10
+ 101
= g 10 k = 0.1 10 = 99 m
= 0.99 V/V
Chapter 7–47
VD
(b) Refer to Fig. P7.122(b):
Rin
1
= 10 k g = 10 0.1 = 99 = 5 2 = 10(5 2) = 14.3 V/V
ID
m
vo v i2
(c) v i2
= (A
v ovi
)
Rin
+R
Rin
GS
A
1
2
= 2 × 5 × 0.2
+ 4
1
60
The current in the voltage divider is
i
i2
VD
I
4
1.6 µA
0.0016 mA
= R + R = 2.5 = = Thus the current through R will be (0.107 + 0.0016) 0.109 mA and V −V R = = 10 − 4 = 55 k
i
1
2
D
i
o
DD
i
D
7.123 (a) DC bias:
D
0.109
(b) gm
2 ID
=V
OV
VDD 10 V
ro
=
VA
0.109
0.107 = ×0.2 = 1.07 mA/V 2
60 = 0.107 = 561 k
ID
(c) Upon replacing the MOSFET with its hybrid-π model, we obtain the small-signal equivalent circuit of the amplifier, shown in Fig. 2.
RD R2 2 M VD ID
Node equation at the output: vo
vo
R1 0.5 M vo
vo
v gs
+ r + −R
RD
VGS
DS
= 0.107 mA
o
= 0.99 × v × 99 99 + 99 0.5v v = 14.3 × v = 14.3 × 0.5v v = 7.15 V/V v o
2 OV
n
ID
1/gm
= 5V = 5 × 0.8 = 4 V = 12 k V 1 + VV
o
1
RD
2
+ r1 + R1 o
2
gm v gs
=+− =− 0
1
gm 1
gm R2
v gs
Thus, Figure 1
A
= V +V = 0.6 + 0.2 = 0.8 V
VGS
t
vo
OV
From the voltage divider (R1 , R2 : see Fig. 1), we can write
VGS
=V
D
R1 R1
+R =V
0.5 D
2
0.5
= −g
m (RD
r R ) 1 − g o
2
=v
R2 sig
R1
+R +v 2
R1
+R
2
(vo vgs)⁄R2
R2 R1
vgs
Figure 2
m R2
R1 o
This figure belongs to Problem 7.123(c).
vsig
1
v gs
(1)
Next, we express v gs in terms of v sig and v o using superposition: v gs
+2
gmvgs
vo
RD
ro
(2)
Chapter 7–48
= 0.2 V =V +V = 0.6 + 0.2 = 0.8 V
VOV
Substituting for v gs from Eq. (2) into Eq. (1) yields vo
= −Av
R2 sig
+ R − Av
R1
=g
A
m (RD
r R ) o
1
+ AR
1
= −A R R R + 1
+ −A R R+ R v = R v 1+A R +R = −1R+/RR /R 1+ A 2
o
1
2
VGS
2
2
v sig
1
+g
R2 /R1 1 R2 /R1
+
m (RD ro R2 )(1
m R2 )
4
D
+
−
µ
DD
D
IRD
(b) gm
0.102
= ×0.20.1 = 1 mA/V
2 ID
2
=V
OV
2/0.5
=−
= 1 VM = 11.6MV = 1.6 A = 0.1 + 0.0016 0.102 mA = V − V = 10 − 1.6 = 82.4 k
(c) Replacing the MOSFET with its T model results in the amplifier equivalent circuit shown in Fig. 2. At the output node ,
1 (2/0.5) 1.07(55 561 2000)(1 1/1.07
vo
× 2000)
vo
= i[R (R + R )] = iR D
1
2
( 1)
D
+ 1
D
2 OV
n
RD
− 1/g
=
−1 +
D
1.6 V
Idivider
1
Q.E.D
v sig
ID
= 0.50.5 + 0.5 V = 0.5V
2
Substituting numerical values yields vo
2VGS
= = = 12 k V
IRD
=−
VD
2
= 12 × 5 × 0.2 = 0.1 mA
2
Thus, vo
1
VD
1
2
= R R+ R
Thus v sig
1
1
OV
1
2
sig
t
From the voltage divider (R1 , R2 : see Fig. 1), we can write
gm R2
2
R2
+R
1
1
2
R1
R1
−
Thus, vo
R1 o
2
where
VGS
5
52.6
vo
= −3.65 V/V
−
R2
=
Note that the gain is nearly equal to R2 /R1 4, which is the gain of an op amp connected in the inverting configuration.
−
RD
i 0
bvo 1/gm
i
7.124 (a) DC bias:
R1
VDD 10 V
vsig
RD Figure 2
R2 0.5 M VD
R (R1 R ). The voltage at the where RD D 2 gate is a fraction β of v o with
=
β
R1 0.5 M
VGS
= R R+ R 1
1
2
Now, the current i can be found from
i Figure 1
+
= v 1/−gβ v = g v − β g v o
sig
m sig
m
m o
( 2)
Chapter 7–49
Substituting for i from Eq. (2) into Eq. (1) yie lds vo
= (g
− βg
m v sig
7.125 Refer to the circuit of Fig. P7.125.
m v o )RD
= α(V −RV ) R + β +1 BB
IC
Thus m
v sig
=
E
= 1 +gβRg
vo
1
D
where
m RD
+g
= V R R+ R = 15 × 15 15 + 27 = 5.357 V = R R = 15 27 = 9.643 k 0.99(5.357 − 0.7) 1.85 mA = 2.4 + 9.643 = 101
RB
mR
1
D
(R2 /R1 ) 2
IC Q.E.D
1
(3)
gm RD
The input resistance Rin can be obtained as follows:
rπ
= gβ = 100 = 1.35 k 74
C
Replacing the BJT with its hybrid-π model results in the equivalent circuit shown at the bottom of the page:
sig
o
RD v sig
= R
D
1
1
gm R
= g1
D
+g
1
m
+ 1 + (R /R ) 2
m RD
1
+ (0.5/0.5) = 1 + (0.5/0.5) v 1+ 1 × (82.4 1000) = 2 2 = 1.95 V/V 1+ 76.13 1
B
π
π
in
vo
in
= −g
vπ
Q.E.D
sig
m (RC
R ) L
= −74(3.9 2) = −97.83 v = −0.371 × 97.83 = −36.3 V/V v
(d) Substituting numerical values: vo
2
π
sig
R2
+
1
= 1.18 k 1.18 v = R R+ R = 1.18 + 2 = 0.371 V/V v
R1 R1
= R R r = R r = 9.643 1.35
Rin
by the inverse of the gain
vo
expression in Eq. (3) gives
Rin
mA = VI = 1.85 = 74 mA/V 0.025 V
m
and replacing
Rin
gm
i
= vv
1
2
T
v sig
Substituting for i from Eq. (1) yields
Rin
CC
2
= 1 ++1 + R /R =
2
VBB
1/β 1/β
1
Rin
BE
B
o
sig
sig
Note that the gain
7.126 Refer to the circuit of Fig. P7.125. DC design:
VB
2 1
For
1 + RR = 2, similar to that
of an op amp connected in the noninverting configuration!
Rin
1
=1
+× 1
1
= 5 V, = 4.3 V
VE
(82.4 1000)
0.5 0.5
+ 0.5
IE
IR2
= 39.1 k
IB
VBE
= 2 mA,
RE
= 0.7 V = VI = 4.32 = 2.15 k E
E
= 0.2 mA, IE
R2
5 = 0.2 = 25 k
2
0.02 mA
= β + 1 = 101
This figure belongs to Problem 7.125.
Rsig vo
vsig
R1
R2
vp
Rin
rp
gmvp
RC
RL
Chapter 7–50
= I + I = 0.2 + 0.02 = 0.22 mA − 5 = 45.5 k = V I − V = 150.22
IR1
R2
B
CC
R1
B
R1
Choosing 5% resistors:
= 2.2 k,
RE
R1
= 47 k,
R2
= 24 k
which is slightly higher than the required gain, and we will obtain
= 15 − 5.1 × 1.84 = 5.6 V
VC
which allows for only 1.2-V negative signal swing.
For these values,
=
IE
7.127 Refer to the circuit of Fig. P7.125:
−V + βR 1 +
VBB
BE B
RE
where
2
CC
1
B
1
2
2
E
B
E
C
E
BB
where
= V R R+ R = 15 × 47 47 + 82 = 5.465 V = R R = 47 82 = 29.88 k − 0.7) = 0.63 mA = 0.99(5.46529.88 7.2 + 101
m
T
100
RB
1
IC
m
Rin
R1 R2 rπ
47 24 1.36
1.25 k
= R = 1.25 = = = = 0.385 V/V v R +R 1.25 + 2 For an overall gain of −40 V/V, 40 v = − 0.385 = −104 V/V v vπ
in
sig
in
sig
o
π
C
vo
= − g (R R ) −104 = −73.4 (R 2) (R 2) = 1.416 R = 4.86 k m
C
L
C
C
C
We can select either 4.7 k or 5.1 k . With 4.7 k , the gain will be vo v sig
= −0.385 × 73.4 × (4.7 2) = −39.6 V/V
which is slightly lower than the required 40 V/V, and we will obtain
−
VC
= 15 − 4.7 × 1.84 = 6.4 V
allowing for about 2 V of negative signal swing at the collector. If we choose 5.1 k, the gain will be vo v sig
T
100 = gβ = 25.2 = 4 k R = R R r = R r = 29.88 4 = 3.5 k
rπ
m
1
B
π
2
π
v π
v sig vo
= 3.53.5+ 2 = 0.636 V/V
= − g (R R ) = −25.2(12 2) = −43.2 V/V v = −0.636 × 43.2 = −27.5 V/V v m
vπ
C
L
o
sig
But vπ
1
2
0.63 = VI = 0.025 = 25.2 mA/V
gm
in
= g = 73.4 = 1.36 k
rπ
CC
2
BE
C
2
VBB
E
β
BE
B
E
= V R R+ R = 15 × 24 24 + 47 = 5.07 V R = R R = 47 24 = 15.89 k 5.07 − 0.7 = 1.85 mA I = 15.89 2.2 + 101 V = I R + V = 1.85 × 2.2 + 0.7 = 4.8 V I = α I = 0.99 × 1.85 = 1.84 mA I 1.84 g = = 0.025 = 73.4 mA/V V VBB
= α(V −RV ) R + β+1
IC
= −0.385 × 73.4 × (5.1 2) = −40.6 V/V
Comparing the results above to those of Problem 7.125, we see that raising the resistance values has indeed resulted in increasing the transmission from source to transistor base, from 0.371 V/V to 0.636 V/V. However, because IC has decreased and gm has correspondingly decreased, the gain from base to collector has decreased by a larger factor (from 97.83 V/V to 43.2 V/V), with the result that the overall gain has in fact decreased (from 36.3 V/V to 27.5 V/V). Thus, this is not a successful strategy! 7.128 Refer to the circuit of Fig. P7.128. DC voltage drop across RB
= 0.2 V R = 0.2 V β+1 IR = 0.2 × 101
= 0.2 V, and
IB RB I
B
B
( 1)
Chapter 7–51
Rin RB
= R r = 10 k VI = 10 B
C
Selecting 5% resistors, we find
B
RB
RB
0.025 I /(β + 1) = 10
RB
RB
⇒ R = 21.2 k
π
T
and specifying I to one significant digit gives
× 101 = 10 I × 0.025 × 101 0.025
I
I
= 0.2 mA 0.2 = αVI 0.025 = 8 mA/V C
gm
T
10
Av o
+ 0.025I× 101 = 0.025 × 101R = 10 IR + 0.025 × 101 RB
= −g R = −8 × 22 = −176 V/V β r = = 100 = 12.5 k g 8 R = R r = 91 12.5 = 11 k 11 × 8(22 20) G =− 20 + 11 = −29.7 V/V m
C
π
B
(2)
B
m
B
in
Substituting for IRB from Eq. (1) yields
π
v
× 101R = 10 0.2 × 101 + 0.025 × 101 0.025R = 10 0.225 ⇒ R = 90 k 0.2 × 101 = 0.22 mA I= 90 0.025
= 91 k = 22 k
RC
B
B
7.129 Refer to the circuit of Fig. P7.129.
B
=
(a) IE 0.5 mA. Writing a loop equation for the base–emitter circuit results in
To maximize the open-circuit voltage gain between base and collector while ensuring that the instantaneous collector voltage does not fall below ( v B 0.4) when v be is as high as 5 mV, we impose the constraint
−
VC
IE
BE
B
CC
C
C
E
C
C
C
m
T
C
and
VB
rπ
= vv = − 5 +52.5 × 20 × (5 10) = −44.4 V/V Gv
o
sig
Thus, 0.22RC
−
= g = 100 = 5 k 20 β
m
= − 0.22 × 90 = −0.2 V 101
5
C
C
C
m
E
C
C
vo
E
× 2.5 + 0.7 + 0.5R = 3 ⇒ R = 4.6 k (b) I = α I 0.5 mA V = 0.5 = 3 − 0.5R ⇒ R = 5 k 0.5 mA I = 0.025 = 20 mA/V (c) g = V V C
= V −I R = 5 − 0.99 × 0.22R = 5 − 0.22R × 0.22 R = 8.7R | A | = g R = 0.990.025
E
+ 0.5
E
where
VC
E
BE
sig
β
E
101
− | A | × 0.005 = V + 0.005 − 0.4 vo
+V +I R = 3 R +V +I R = 3 1
IB Rsig
8.7RC
−
0.005
×
0.2
0.395
=− −
This figure belongs to Problem 7.129.
Rsig vo
vsig
rp
vp
gmvp
RC
RL
Chapter 7–52
This figure belongs to Problem 7.130.
7.130 Refer to the circuit of Fig. P7.130. (a) DC analysis of each of the two stages:
= V R R+ R = 15 10047+ 47 = 4.8 V R = R R = 100 47 = 32 k V −V I = R R + β+1 = 4.8 − 0.7 = 0.97 mA 1 mA 32 3.9 + 101 I = α I 1 mA V = V − I R = 15 − 1 × 6.8 = 8.2 V 2
VBB
CC
1
B
1
2
2
BB
BE
E
B
E
C
E
C
CC
C
C
= gβ = 2.5 k (c) R = R R r = R r = 32 2.5 = 2.32 k 2.32 v = R R+ R = 2.32 v + 5 = 0.32 V/V rπ
m
1
b1
B
π
2
C
T
Note that the emitter has a resistance Re 250 .
= = 200 k (β + 1)(r + R ) = 200 [101 × (0.25 + 0.25)] = 200 50.5 = 40.3 k v = R R+ R = 40.340.3 + 20 = 0.668 V/V v Rin
e
b
π
in
sig
Total resistance in collector
vo
= −α Total resistance in emitter − 0.2520+ 200.25 = −20 V/V vb
Gv
vo
0.668
20
in
sig
= R R r = R = 2.32 k = v = −g (R R ) v = −40(6.8 2.32) = −69.2 V/V v (e) = vv = −g (R R ) v = −40(6.8 2) = −61.8 V/V v = vv × vv × vv = −61.8 (f) v × − 69.2 × 0.32 = 1368.5 V/V (d) Rin2 v b2
1
2
For v be to be limite d to 5 mV, the signal between base and ground will be 10 mV (because of the 5 mV across Re ). The limit on v sig can be obtained by dividing the 10 mV by v b /v sig , mV ˆ = 100.668 = 15 mV
v sig
Correspondingly, at the output we have
b1
ˆ = | G |vˆ = 13.4 × 15 = 200 mV = 0.2 V
vo
v
sig
in1
π
v b2
m
C
7.132 (a)
in2
π1
o
0.5 mA
o
m
C
L
π
b2
2
o
o
b2
b1
sig
b2
b1
sig
VC 0.495 mA
200 k
0.005 mA
7.131 Refer to the circuit in Fig. P7.131:
re
13.4 V/V
× =−
in
sig
IE
e
in
sig
sig
=
in1
0.1 mA = VI 0.025 = 4 mA/V V
= v =−
(b) See figure above. IC gm 40 mA/V VT
=
gm
= 0.1 mA 25 mV = VI = 0.1 = 250 mA
200
T
E
0.5 mA
Figure 1
Chapter 7–53
vo
From Fig. 1 we see that
100 k
= 0.495 mA V = I × 200 k + I × 0.2 k + V = 0.005 × 200 + 0.5 × 0.2 + 0.7 = 1.18 V IC
C
B
E
ie
ie
re 50 Rsig 50
(b)
vo
vi 200
vo
i
200 k
Rin re 50
20 k
−v = −v = 100 0.1 k sig
re 50
i
vi
sig
At the output node,
= −αi (5 100) = α v0.1 (5 100) v = α 5 100 47.6 V/V vo
200
e
sig
o
From Fig. 2, we have
IC
0.1
v sig
Figure 2
7.134 (a) IE
0.495
=
= V = 0.025 20 mA/V
gm
T
=
re
= 50
IE
E
= r +v R = 50 +v 200 = 250v = 0.25v k = 4 v , mA i
i
e
i
e
i
E
i
i
vo
−v =0 + αi + v 200 o
i
vo
o
i
i
vo vi
×
1
1 + 200 = −v 20
i
4
0.99
1 − 200
= −71.9 V/V
= V 25 mV r = = 0.5 = 50 I mA R = r = 50 −v = −v i = 50 + 50 r +R T
e
E
e
sig
e
sig
E
B
E
E
e
in
The dc emitter current is equal to 0.5 mA, and IC α IE 0.5 mA; also,
e
E
100 (β
7.133 Refer to the circuit in Fig. P7.133.
in
E
E
E
v v + 0.99 × 4v + 200 − 200 =0 20 vo
E
B
Node equation at the output: 20
− 0.7 + β1001 +
3 1
= 50: 2.3 = 0.78 mA I = 100 1+ 51 V = I R = 0.78 V V = V + 0.7 = 1.48 V β = 200: 2.3 I = = 1.54 mA 100 1+ 201 V = I R = 1.54 V V = V + 0.7 = 2.24 V (b) R = 100 (β + 1)[r + (1 1)] β
VT
5 k
BE
sig
=β = 50: +
1)(re
0.5)
+
25 mV = VI = 0.78 = 32.1 mA R = 100 [51 × (0.0321 + 0.5)] = 21.3 k β = 200: V 25 mV r = = 1.54 = 16.2 I mA
re
T
E
in
T
e
E
vsig
Chapter 7–54
= 100 [201 × (0.0162 + 0.5)]
Rin
= 50.9 k v (c) = R R+ R v v = (1 (11) 1+) r = 500500+ r (r v β = 50: v = 21.321.3 10 = 0.68 V/V v + v 500 = = 0.94 V/V v 500 + 32.1 v = 0.68 × 0.94 = 0.64 V/V v b
in
sig
e
= vv × 130.4 = 0.964 × 65.2 2 o b
out
o
b
ii
= 62.9 A/A R = 3.3
in
sig
io
e
in )
e
b
re
+ β100 +1
= 3.3 0.0463 + 100 101 = 0.789 k = 789
sig
7.136 Refer to the circuit in Fig. P7.136.
o
b
o
sig
= 200: = 50.950.9 + 10 = 0.836 V/V v
β
vb
sig
vo vb vo
For dc analysis, open-circuit the two coupling capacitors. Then replace the 9-V source and the two 20-k resistors by their Thévenin equivalent, namely, a 4.5-V source and a 10-k series resistance. The latter can be added to the 10-k resistor that is connected to the base. The result is the circuit shown in Fig. 1, which can be used to calculate IE .
= 500500 + 16.2 = 0.969 V/V
9 V
= 0.836 × 0.969 = 0.81 V/V
v sig
4.5 V 20 k
7.135 Refer to the circuit in Fig. P7.135.
=
IE
2.3
=
IE 2 k
− 0.7 100 3.3 + β +1 3
3.3
+ 100 101
= 0.54 mA
25 mV = VI = 0.54 = 46.3 mA R = (β + 1)[r + (3.3 2)] = 101 × (0.0463 + 1.245) = 130.4 k 130.4 v = R R+ R = 130.4 + 100 v
Figure 1
T
re
E
b
in
sig
in
sig
0.566 V/V o
vb
=
e
in
=v
(a) IE
= (3.33.3 2) 2+ r = 1.2451.245 + 0.0463 e
= 0.964 V/V v = 0.566 × 0.964 = 0.55 V/V v o
sig
io
= 2 vk
ii
= Rv = 130.4v k
o
i
in
b
= IC
4.5 2
− 0.7
+ β 20+ 1
3.8 = 1.73 mA 20 + 101 = αI = 0.99 × 1.73 mA 2
E
= 1.71 mA I g = V = 68.4 mA/V m
re
C T
25 mV = VI = 1.73 = 14.5 mA T
E
= 0.0145 k = (β + 1)r = 101 × 0.0145 = 1.4645 k
rπ
e
(b) Replacing the BJT with its T model (without ro ) and replacing the capacitors with short circuits
Chapter 7–55
results in the equivalent-circuit model shown in Fig. 2.
Figure 3
Thus, Figure 2
= 20 k R = 20 k (β + 1)(R + 2) = 20 101 × 2.0145 = 18.21 k
Rin
ib
e
From Fig. 2 we see that
re
+
ve
=
vb
r = v + i r = i (10 2) 1 + 10 +i r
ii
ie
ie
e
10
(10 2)
e e
e
e
r = (1 − α)i + i 10 e
e
e e
e
r = β i+ 1 + i 10 e
e
e
We can now obtain Rin from
Rin
≡ vi = b
re 10 re
+ +
(10 2) 1
1
i
the amplifier input. The reduced Rin will result in a reduction in v b /v sig ,
re
+ 1 + 10 r + (β + 1)r (β + 1)(10 2) 1 + 10 = r 1 + (β + 1) 10
vb
β
e
e
+ 0.00145) + 101 × 0.0145 = 101 × (10 2) 1×+(1101 × 0.00145
+ 1.4645 = 148.3 k = 168.577 1 + 0.14645 vb
v
148.3 = R R+ R = 148.3 + 10 = 0.937 in
in
vb
e
=v = b
in
sig
= 0.646 V/V v 2 = 2 + 0.0145 = 0.993 v o
b
Gv
≡ vv = 0.646 × 0.993 o
sig
= 0.64 V/V which is much reduced relative to the value obtained with bootstrapping.
sig
ie 1
v o
= R R+ R = 18.21 28.21 in
v sig
e
v sig
which is greatly reduced because of the absence of bootstrapping. The latter causes the lower node of the 10-k base-biasing resistor to rise with the output voltage, thus causing a much reduced signal current in the 10-k resistor and a correspondingly larger effective resistance across
re
(10 2) re 10 (10 2) ie re 10
+ + +
ie 1
1.00145 × (10 2) = 1.00145 × (10 2) + 0.0145 = 0.991 V/V v = 0.937 × 0.991 = 0.93 V/V G ≡ v o
v
7.137 (a) Applying Thévenin’s theorem to the base-biasing circuit of Q1 results in the dc circuit shown below. From our partial analysis on the figure, we can write
IE 1 IE 2
sig
(c) When CB is open-circuited, the equivalent circuit becomes that shown in Fig. 3.
= 0.1 mA = 5 mA
VB1 can be obtained as VB1
= 2.5 − 2
µA
× 0.5 M = 1.5 V
Chapter 7–56
= 0.5 M [51 × (0.25 + 101.5)] k = 0.5 M 5.2 M = 456 k v = R R+ r = 101.5101.5 + 0.25 v = 0.9975 V/V v (d) = R R+ R = 456456 + 100 = 0.82 V/V v
Rin
0.5 M
100 51
2 A
100 A 0.1 mA
2.5 V
e1
ib
b1
0.05 mA 50 A 50 A
5 mA
ib
e1
b1
in
sig
in
sig
vo
(e)
7.138 We need to raise fH by a factor of
and VB2 can be found as
2 MHz
= V − 0.7 = 0.8 V
VB2
B1
500 kHz
(b) Refer to the circuit in Fig. P7.137. With a load resistance RL 1 k connected to the output terminal, the voltage gain v o /v b2 can be found as
=
RL
vo
L
e1
+g R ⇒ R = g3 1
m
m
1 mA = VI = 0.025 = 40 mA/V V C
T
mV = 255 mA = 5
Re
1000
vo
= 1000 5 = 0.995 V/V R = (β + + 1)(r + R ) = 101 × 1.005 = 101.5 k (c) R = 1 M 1 M (β + 1)(r + R
3
= 0.04 = 75
The new value of fL will be
v b2
ib2
2
e2
L
e1
in
where
re
e
e
gm
where
r e2
= 4. Thus =4
Since
= R +r
v b2
= 0.82 × 0.9975 × 0.995 = 0.814 V/V
v sig
VT
25 mV
= I = 0.1 mA = 250 = 0.25 k E1
ib2 )
100 Hz
fL
= 1+g
100
m Re
=
4
= 25 Hz
and the midband gain will become
| A | = 1 +100 = 100 = 25 V/V 4 g R M
m
e
