Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Chapter 9 Bistable Multivibrators
1. Design a fixed-bias bistable multivibrator using Ge transistors having h FE (min) (min) = 50, V CC CC = 10 V and V BB = 10 V, V CE(sat) CE(sat) = 0.1 V, V BE(sat) BE(sat) = 0.3 V, I C(sat) C(sat) = 5 mA and assume I assume I B(sat) B(sat) = 1.5 I B(min) B(min) . Solution:
RC
VCC
V CE (sat)
10 0.1 V
I C 2
1.98
R2
k Ω V
5 mA
9.9 V 5 mA
( V BB )
I 2
Choose I 2
1
10
I C 2
0.5 mA
R2
I B 2min
0.3 10 0 .5 I C 2
h FE min
10.3 V
=20.6 k Ω 0.5 mA 5 mA =0.1 mA 50
If Q 2 is in saturation I B 2
1.5 1. 5 I B 2 m in
= 0.15 mA I 1
I
I
2 B 2
= 0. 0.5 mA mA +0 +0 . 1 5 m A RC
R1
R1 ( RC
VCC
V
I 1
0 . 6 5 mA mA
10
0 .3
0 .6 5 m A
9 .7 V 0 .6 5 m A
14.92 k Ω
R1 ) RC
1 4 . 9 2 1 . 9 8 1 2 . 9 4
kΩ .
2. For a fixed-bias bistable multivibrator shown in Fig. 9p.2 using n–p–n Ge n–p–n Ge transistor V CC V, R C = 1 k Ω, R 1 = 10 k Ω, R 2 = 20 k Ω, h FE(min) = 40, V BB = 10 V. Calculate: CC = 10 V, R (a) Stable-state currents and voltages assuming Q 1 is OFF and Q 2 is ON and in saturation. Verify whether Q 1 is OFF and Q 2 is ON or not. (b) the maximum load current.
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 9p.2 The fixed-bias bistable multivibrator Solution: Assume V CE CE (sat) (sat) = 0.1 V, V BE (sat) (sat) = 0.3 V
Calculate V B1 B1 to verify whether Q 1 is OFF or not. R2 R1 0.1 20 (10)10 V B1 VCE (sat) ( V BB ) R1 R2 R1 R2 10 20 10 20 0.066 3.333 3.267 V Hence Q 1 is OFF VC1 V CC 10 V
To verify whether Q 2 is in saturation or not: Calculate I Calculate I B2 B2 , I C C2 To calculate I calculate I B2 B2 . Consider the cross-coupling circuit shown in Fig.2.1.
Fig. 2.1 Circuit to calculate the base current of Q 2
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Pulse and Digital Circuits
I 1
I 2
VCC V
10 0.3
RC R1
I B 2
V
V BB
1 10
0.3 10
R2
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
20
9.7 V 11 kΩ
10.3 20
=0.88 mA 0.515 mA
0.88 0.51
0.37 mA To calculate I C2 Consider the cross-coupling network shown in Fig. 2.2.
Fig. 2.2 Circuit to calculate the collector current of Q 2
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Pulse and Digital Circuits
I 3
I 4
VCC
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
V CE (sat)
RC 10 0.1
R1
9.9 mA
1 K VCE (sat)
V BB
R2
10.1
=0.336 mA 30 K I C 2 I 3 I 4
9.9 0.34 9.56 mA
I B 2min I B 2
I C 2 h FE min
9.56 mA 40
=0.24 mA
I B 2min
Hence Q 2 is verified to be in saturation. VC 2 0.1 V, V B 2 0.3 V . V C1 = V CC – I 1 R C = 10 – (0.88)1 = 9.12 V Hence the stable-state currents and voltages are as follows: V C1 = 9.12 V, V B1 = –3.267 V V C2 = 0.1 V I B2 = 0.37 mA, I C2 = 9.56 mA To find the maximum load current or minimum load resistance, consider Fig.2.3.
Fig. 2.3 Circuit to calculate maximum load current I L is maximum (I L(max) ) when I B2 is I B2(min)
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
I B2(min) = 0.2 mA I 2 = 0.51 mA I 1(min) = I 2 + I B2(min) =0.51+0.24 =0.75 mA V C1 (min) = I 1(min) R 1 +V 0.75 10 0.3
σ
7.8 V
I
VCC
V C 1(min)
12 7.8
RC
1
4.2 mA
I Lmax = I – I 1(min) = 4.2 mA – 0.75 mA =3.45 mA 7.8 V 2.26 kΩ. R L (min) = 3.45 mA 3. Design a self-bias bistable multivibrator shown in Fig.9p.2 with a supply voltage of – 12 V. A p-n-p silicon transistors with h FE (min) = 50, V CE (sat) = –0.3 V, V BE (sat) = –0.7 V and I C 2 = –4 mA are used.
Fig. 9p.2 Self-bias bistable multivibrator Solution:
1 Assume V EN = V CC 3 I C2 = –4 mA
1 3
12 4
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V
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Pulse and Digital Circuits
I B2(min) =
4
mA
50
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
0.08
mA
Choose I B2 = 1.5 I B2(min) = –0.12 mA ( I C 2 + I B2 ) = –4 – 0.12 = –6.12 mA R E
RC
V EN 2 I B 2
4.12
V
I C 2
VCC
VCE (sat) V EN 2
mA
0.97 k Ω
I C
12 0.3 4
Let V BN 2 R2
4
I 2
4
mA 1
7.7
V
4
mA 1
1.925
k
4 mA 0.4 mA I C 2 10 10 VEN 2 V 4 0.7 4.7 V
V BN 2
4.7
V
11.75 k Ω I 2 0.4 mA Choose R 2 = 12 k Find I 2 for this R 2 V 4.7 V 0.392 mA I 2 BN 2 R2 12.0 K
RC R1
VCC I 2
12
V BN 2
I B 2
4.7
7.3
0.392 0.12
0.512
V mA
14.26
k Ω
( RC R1 ) = 14.26 k Ω R 1 = ( RC
R1 ) RC
14.26 1.925 12.33 kΩ
Choose R 1 =12 k Note: Choose the nearest standard values. 4. A self-bias bistable multivibrator uses Si transistors having h FE (min) = 50. V CC = 18 V, R 1 = R 2 , I C( sat) = 5 mA. Fix the component values R E , R C , R 1 and R 2. Solution: 1 1 Assume V EN = V CC 18 6 V 3 3 and I C( sat) = 5 mA I B2(min) =
5 mA
0.1 mA 50 Choose I B2 = 1.5 I B2(min) =0.15 mA
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
( I C 2 + I B2 ) = 5 + 0.15 = 5.15 mA V EN 2 6V 1.16 k Ω R E I C 2 I B 2 5.15 mA RC
VCC
VC E (sat) V EN 2
I C
18 0.3 6
V BN 2
RC R1
RC R1
R1
R1
V CC V BN 2 I 2 I B 2
2.34 R1 0.15 R12
V CC V BN 2 VBN 2 I B 2 R2
R1 (V CC V BN 2 ) VBN 2 R1 I B 2
R1 (18 6.7)
4.25 R1 15.67
14
( 4.25) 2
11.3 R1
6.7 0.15 R1
4.25 R2
11.7 V
2.34 k Ω 5 mA V 6 0.7 6.7 V
5 mA VEN 2
6.7 0.15 R1 0
4 0.15 15.67
2 0.15 k Ω .
5. For a Schmitt trigger in Fig. 9p.4 using n–p–n silicon transistors having h FE (min) = 40, the following are the circuit parameters: V CC = 15 V, R S = 0, R C 1 = 4 k Ω, R C 2 = 1 k Ω, R 1 = 3 k Ω, R 2 = 10 k Ω and R E = 6 k Ω. Calculate V 1 and V 2 .
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 9p.4 The Schmitt trigger circuit Solution: From the given data, if Q 2 is in the active region, typically, V BE 2 = 0.6 V and let h FE = 40. To calculate V 1 : R E (1+h FE ) = 6(1+40) =246 k Ω R ' R2 / /( RC 1 R1 ) 10 k / /(4 k+3 k) 4.11 k
V'
V CC
V EN 2
(V '
V EN 2
R2 ( RC 1
R1
V BE 2 )
R
'
R1 R2
R t
8.82
V
h FE )
246
0.769
R 2 )
R1 R 2
4 (3 4
R E (1
3 10
R C 1 ( R1 R C 1
4 3 10
8.08 V 4.11 246 V 8.08 0.5 8.58 V 1
To calculate V 2 : R2 10
10
R E (1 h FE )
(8.82 0.6)
V 1 V EN 2
R t
R2 )
15
3
10)
10
3 . 0 5 k Ω
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Pulse and Digital Circuits
Rt
R E"
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
0.769 3.05 2.35 kΩ
(1
1 h FE
) RE
41 6
I C 1 V 2
(V '
V 2 )
Rt
( RC 1
" RE
6.15 kΩ
R2
'
Vt V V CC
40
R1
R2 )
(8.82 0.5)
2.35 6.15
15
10 4 3 10
8.82
V
0.978 mA
"
V BE 1 I C 1 RE
V 2
0.6 V (0.978 mA)(6.15 k Ω)
0.6 V 6.01 V 6.61 V Hence for the given Schmitt trigger V 1 = 8.58 V V 2 = 6.61 V
6. The self-bias transistor bistable multivibrator shown in Fig. 9p.3 uses n–p–n Si transistors. Given that V CC = 15 V, V CE(sat) = 0.2 V, V = 0.7 V, R C = 3 k ,R 1 = 20 k ,R 2 = 10 k , R E = 500 Ω. Find: σ
(i) Stable-state currents and voltages and the h FE needed to keep the ON device in saturation. (ii) f (max) , if C 1 = 100 pF. (iii) The maximum value of I CBO that will still ensure one device is OFF and the other is ON. (iv)The maximum temperature up to which the multivibrator can work normally if I CBO at 25°C = 20 µA.
Fig. 9p.3 The given self-bias bistable multivibrator
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Solution: (i) To calculate I B2 , consider the base circuit of Q 2, Fig. 6.1.
Fig.6.1. Circuit to calculate V thb and R thb of Q 2 . From Fig. 6.1, V thb
V CC
R2 RC R1 R2
=
15 10
150
3 20 10
33
= 4.54
V Rthb
R2
( RC R1 ) =
10 (3 20) 3 20 10
230 33
=6.96k
(ii) To calculate I C2 , consider the collector circuit of Q 2 , Fig. 6.2. .
Fig. 6.2. Circuit to calculate V thc and R thc of Q 2
V thc
V CC
Rthc
R1 R2 RC R1 R2 RC
© Dorling Kindersley India Pvt. Ltd 2010
=
(R1 R2 ) =
15 ( 20 10) 3 20 10
3 30 33
90 33
450 33
=13.6 V
=2.72 k
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Now let us draw the base and collector circuits of Q 2 , Fig. 6.3.
Fig. 6.3. Circuit to calculate I B2 and I C2 Writing the KVL equations of the input and output loops 4.54 – 0.7= (6.96+0.5) I B2 + 0.5 I C2 13.6 – 0.2 = 0.5 I B2 + (2.72+0.5) I C2 Eqs. (1) and (2) are simplified as 3.84 = 7.46 I B2 + 0.5 I C2 13.4 = 0.5 I B2 + 3.22 I C2 Solving Eqs. (3) and (4) for I B2 and I C2 we get I B2 = 0.263 mA I C2 = 3.75 mA 3.75 h FE = = 14.25 0.263 The h FE that keeps the ON device in saturation is 14.25.
(1) (2) (3) (4)
V EN 2 = ( I B2 + I C2 ) R E = (0.263+3.75)0.5 = 2 V V CN 2 = V EN 2 + V CE (sat) = 2 + 0.2 = 2.2 V V BN 2 = V EN 2 + V = 2 + 0.7 = 2.7 V. V BN 1 = V CN 2
R2
2.2 10
22
=0.733 V R1 R2 20 10 30 V BE 1 =V BN 1 – V EN 2 = 0.733 – 2 = –1.26 V
Hence Q 1 is OFF V CN 1 should be V CC . But actually it is less than V CC . I 1 =
V CC V BN 2 RC R1
=
15 2.7 3 20
0.534 mA.
V CN 1 = V CC – I 1 R C = 15 – (0.534)(3) =13.4 V. f max
R1
R2
2 R1 R2 C 1
(20 10)103 2 20 103 10 103 100 1012
750 kHz
(iii) V BE 1 was calculated as –1.26 V. This voltage exists at the base of Q 1 to keep Q 1 OFF. Till such time the voltage at B 1 of Q 1 is 0 V, let us assume that Q 1 is OFF, Fig. 6.4.To calculate R B and hence I CBO R B , short V EN (though I E1 = 0, there exists a
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
voltage V EN at the first emitter) and V CE(sat) sources. From Fig. 6.4, it is seen that R B is the parallel combination of R 2 and ( R 1 + R E ).
Fig. 6.4. Circuit to calculate I CBO R B R B
R2 ( R1 RE )
10 20.5
10 20.5
6.72 kΩ
Until I CBo(max) R B = V BE 1, Q 1 will be OFF. I CBo(max) =
1.26 V
6.72 k Ω
0.187 mA 187 A
(iv) I CBo at 25°C = 20 µA I CBo(max)
187
I CB 0
20
9.35
n
9.35 = 2 n=
log 9.35
log 2
0.3
T
10 T 2
25
10 T 2
0.97
3.23
n
3.23
25 32.3 57.3C
7. (a) Design a Schmitt trigger shown in Fig. 9p.4 with UTP of 8 V and LTP of 4 V. Si transistors with h FE = 40 and I C = 5 mA are used. The supply voltage is 18 V. The ON transistor is in the active region for which V BE = 0.6 V, V CE = 2.0 V. (b) Calculate R e1 for eliminating hysteresis.
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 9p.4 The Schmitt trigger circuit Solution: Till UTP is reached Q 1 is OFF and Q 2 is ON and in active region. Just at V 1 (UTP) Q 1 goes ON and Q 2 goes OFF. Just prior to this, Q 2 is ON and Q 1 is OFF, Fig. 7.1.
Fig. 7.1 Circuit when Q 1 is OFF and Q 2 is ON V 1 = UTP = V BN 2 = 8 V I E = I C2 = 5 mA V EN = V EN2 = V BN2 – V BE2 V EN2 = 8 – 0.6 = 7.4 V. V 7.4 R E EN 2 I E 5 mA
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
= 1.48 k Ω Choose R E = 1.5 k If Q 2 is in the active region and V CE = 2 V I C2 R C 2 = V CC – V CE – V EN 2 18 2.0 7.4
RC 2
5
8.6 V 5 mA
1.72
k Ω
Choose R C 2 = 1.75 k I 2
R2
1
I C 2 10 V BN 2
8V
I 2
I B 2min
0.5 mA
0.5 mA
I C 2
=16 k Ω
5 mA
h FE
40
0.125 mA
I B 2
1.5 I B 2 min 1.5 0.125
I B 2
I 2
0.1875 mA+0.5 mA 0.6875 mA
( RC 1 R1 ) R1
0.1875 mA
14.55
VCC
V BN 2
( I B 2
18 8
I 2 )
0.6875
10 0.6875
14.55
kΩ
k Ω RC 1
At LTP = 4 V, consider the Fig. 7.2.
Fig. 7.2 Circuit at LTP V BN 2 = V BN 1 = 4 V = LTP = V 2 Let I 1 be the current in R 2 I 1
I C1
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V BN 2
R2
I E 1
4V
16 k Ω
V2
V BE 1
R E
0.25 mA
4 0.6 1.5 k Ω
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
I C 1 = 2.27 mA Writing the KVL equation of the outer loop consisting of R C1 , R 2 and R 1 , V CC = ( I C 1 + I 1 ) R C 1 + I 1 ( R 1 + R 2 ) = ( I C1 + I 1 ) R C 1 + I 1 (14.55 k – R C 1 + R 2 ) V CC = I C 1 R C 1 + I 1 (14.55 k + R 2 ) V I (14.55 R2 ) RC 1 CC 1 I C 1 18 0.25(14.55 16)
10.36
4.56 k Ω 2.27 2.27 R C 1 = 4.56 k R 1 = ( R C1 – R 1 ) – R C 1 =14.55 – 4.56 = 9.99 k
Choose R 1 = 10 k and R C1 = 4.5 k . The designed Schmitt trigger circuit is shown in Fig. 7.3 with component values.
Fig. 7.3 Designed Schmitt trigger (b) To eliminate hysteresis R e1 is added in series with the emitter of Q 1, Fig. 7.4, such that V 1 – V 2 = V H = ( I C1 + I B1 ) R e1 4V 1.76 k R e1 = 2.27 mA
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 7.4 R e1 connected to eliminate hysteresis 8. (i) Design a Schmitt trigger in Fig.9p.5 with UTP of 8 V and LTP of 4 V. Si transistors with h FE = 40 and I C = 4 mA are used. The supply voltage is 12 V. The ON transistor is in saturation for which V BE = 0.7 V, V CE (sat) = 0.2 V. (ii) Calculate R e1 for eliminating hysteresis. (iii) Find R e2 to eliminate hysteresis.
Fig. 9p.5 The given Schmitt trigger circuit Solution: (i) Till UTP is reached, Q 1 is OFF and Q 2 is ON and in saturation region. Just at V 1 (UTP) Q 1 goes ON and Q 2 goes OFF. Just prior to this, Q 2 is ON and Q 1 is OFF, Fig. 8.1.
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 8.1 Circuit when Q 1 is OFF and Q 2 is ON V 1 = UTP = V BN 2 = 8 V I E = I C2 = 4 mA V EN = V EN 2 = V BN 2 – V BE 2 V EN 2 = 8 – 0.7 = 7.3 V. V 7.3 1.825 k Ω R E EN 2 I E 4 mA If Q 2 is in the saturation region and V CE = 0.2 V I C 2 R C 2 = V CC – V CE – V EN 2 12 0.2 7.3 4.5 V RC 2 1.125 k Ω 4 4 mA 1 I 2 I C 2 0.4 mA 10 V 8V R2 BN 2 =20 k Ω I 2 0.4 mA I B 2min I B 2 I B 2
I C 2
4 mA
h FE
40
0.1 mA
1.5 I B 2 min 1.5 0.1
I 2
R1 )
0.15 mA
0.15 mA 0.4 mA 0.55 mA
VCC
V BN 2
( RC 1
R1
7.27 k Ω RC 1
( I B 2
I 2 )
12 8 0.55
4 0.55
7.27
kΩ
At LTP = 4 V, consider Fig. 8.2.
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 8.2 Circuit at LTP V BN 2 = V BN 1 = 4V = LTP = V 2 Let I 1 be the current in R 2 I 1
V BN 2 R2
I C1
RC 1
I E 1
=
4V 20 k Ω V2
=0.2 mA
V BE 1
4 0.7
1.8 mA R E 1.825 k Ω Writing the KVL equation of the outer loop consisting of R C1 , R 2 and R 1 , V CC = ( I C1 + I 1 ) R C 1 + I 1 ( R 1 + R 2 ) V CC = ( I C1 + I 1 ) R C 1 + I 1 (7.27 – R C 1 + R 2 ) V CC = I C 1 R C 1 + I 1 (7.27+ R 2 ) V I 1 (7.27 R2 ) RC 1 CC I C 1
12 0.2(7.27 20)
10.36
3.6 k Ω 1.8 2.27 R 1 =( R C1 – R 1 ) – R C 1 R 1 = 7.27 – 3.6 = 3.67 k (ii) To eliminate hysteresis R e1 is added in series with the emitter of Q 1 , Fig. 8.3, such that V 1 – V 2 = V H = ( I C1 + I B1 ) R e1 4V =2.22 k Ω R e1 = 1.8 mA
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Fig. 8.3 R e1 connected to eliminate hysteresis (iii) To eliminate hysteresis R e2 is added in series with the emitter of Q 2, Fig. 8.4, such that
Fig. 8.4 R e2 connected to eliminate hysteresis V '
VCC R2
RC 1
R1
12 20
R2
'
3.6 3.67 20
R = R 2 //( R C1 + R 1 ) =
20 7.27
27.27
8.8
V
5.33 k Ω
We know, V 2
(V '
V BE 2 )
4 (8.8 0.7)
© Dorling Kindersley India Pvt. Ltd 2010
(1 h FE ) R E R '(1 h FE )( Re 2 R E ) 41 1.825
5.33 (41)( Re 2
1.825)
V
0.5
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Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
3.5
606 80.1 41 Re 2
143.5 R e2 =325.65 R e2 =2.26 k .
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20