BCM53128

DataShe Data Sheet et

BCM53128 Multiport Gigabit Ethernet Switches GENERAL DESCRIPTION The Broadcom® BCM53128 is a highly integrated, cost-effec cost-effective tive unmanaged-s unmanaged-smart mart gigabit gigabit switch. switch. The switch design is based on the field-proven, industryleading ROBO architecture. This device combines all the functions of a high-speed switch system including packet buffers, PHY transceivers, media access controllers (MACs), address management, port-based rate control, and a non-blocking switch fabric into a single 65-nm CMOS device. Designed to be fully compliant with the IEEE 802.3™ and IEEE 802.3x specifications, including the MACcontrol PAUSE frame, the BCM53128 provides compatibility with all industry-standard Ethernet, Fast Ethernet, and Gigabit Ethernet (GbE) devices. The BCM53128 has a rich feature set suitable for not only standard GbE connectivity for desktop and laptop PCs, but also for next-generation gaming consoles, set-top boxes, networked DVD players, and home theater receivers. It is also specifically designed for next generation SOHO/SMB routers and gateways. The BCM53128 contains eight full-duplex 10/100/ 1000BASE-TX Ethernet transceivers. The BCM53128 provides 70+ on-chip MIB counters to collect receive and transmit statistics for each port. The BCM53128 is available in commercial temperatur temperature e (C-Temp) (C-Temp) and industrial industrial temperatur temperature e (ITemp) rated packages. The BCM53128 is provided in a 256-pin eLQFP (28 mm x 28 mm) package.

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Nine 10/100/1000 10/100/1000 media access access contro controllers llers Eight port 10/100/1000 10/100/1000BASE-T BASE-T/Tx /Tx transceiver transceivers s One GMII/RGM GMII/RGMII/M II/MII/R II/RvMII vMII/TMI /TMII/Rv I/RvTMII TMII interface for an in-band management port (IMP) for connection to a CPU/management entity without PHY IEEE 802.1p, 802.1p, MAC, Port, TOS, and DiffSer DiffServ v QoS for four queues, plus two time sensitive queues

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Port Port-b -bas ased ed VLAN VLAN IEEE 802.1Q-bas 802.1Q-based ed VLAN with 4K entrie entries s MAC-based MAC-based trunking trunking with with automa automatic tic link link failover failover Port-b Port-base ased d rate rate contro controll Port Port mirr mirror orin ing g ® Broa BroadS dSyn ync c HD for IEEE 802.1AS support – Timestamp tagging at MAC interface i nterface – Time-aware egress scheduler DOS DOS attack attack preven preventio tion n – Support IPv6 IGMP snooping, snooping, MLD snooping snooping support support Green Green mode mode suppor supportt Spanning Spanning tree tree support support (multiple (multiple spannin spanning g trees– trees– up to eight) Loop detection detection for unmanaged unmanaged configurat configurations ions with Broadcom’s patented LoopDTech™ technology CableCheck CableChecker™ er™ with unmanaged unmanaged mode support support Double Double taggin tagging/Q g/QinQ inQ IEEE 802.az 802.az EEE (Energy (Energy Efficie Efficient nt Ethern Ethernet) et) support IEEE IEEE 802.3a 802.3as s suppor supportt IEEE 802.3x 802.3x programm programmable able per-po per-port rt flow flow contro controll and backpressure, with IEEE 802.1x support for secure user authentication EEPROM, EEPROM, MDC/MDIO MDC/MDIO,, and and SPI Interfaces Interfaces Serial Flash Interface Interface for accessing accessing embedded embedded 8051 processor 4K entry entry MAC address address table table with automatic automatic learning and aging 192 KB packet packet buffer buffer 256 multic multicast ast group group suppor supportt Jumbo Jumbo frame frame supp support ort up to 9720 9720 byte bytes s Serial Serial and and paral parallel lel LED LED inte interfa rface ce 1.2V 1.2V for for core core and and 3.3V 3.3V for I/O JTAG JTAG supp suppor ortt 256 256 eLQF eLQFP P

53128-DS07-R Corporate Headquarters: San Jose, CA

April 6, 2016

Figure Figure 1: Functional Functional Block Block Diagram

© 2016 by Broadcom. All rights reserved. Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, and Avago Technologies are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. Broadcom reserves the right to make changes without further notice to any products or data herein to to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume assume any liability liability arising out of the application application or use of this information, information, nor the application application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT.

BCM53128 Data Sheet

Revision History

Revision History Change Description

Customer Impact

Action Items

Revision: 53128-DS07-R Date: 04/06/16 Updated: • “Transmit Output Output Port Queues” on Corrected typo for entries page 90 number. • Table 291: 291: “EEE GLB Congst Congst TH Corrected typo for entries Register (Page 92h: Address C4h),” on number. page 293 • Tab Table le 293 293:: “EE “EEE E TXQ Con Cong g TH Reg Regist ister er Corrected typo for entries (Page 92h: Address C6h),” on page 293 number. Added: • Table 324: “BCM53128IQLE Package – with Heat Sink, 4-layer Board, P=3.1W,” on page 315 Revision: 53128-DS06-R

No action required. No action required.

No action required.

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Date: 06/02/14 Updated: • Table 324: “Ordering “Ordering Informatio Information,” n,” on page 318

Added ordering information for part number BCM53128IQLE(G)

No action required.

Updated the general description.

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Revision: 53128-DS05-R Date: 02/18/13 Updated: • Defau efaultbit ltbits s 13, 13, 12, 12, 8,and6 in Tabl Table e 128 128 on page 197. • Defaul Defaultt bits bits 11, 11, 10, 10, 8, 7, 6, 6, and and 5 in Table 132 on page 200. • Defaul Defaultt bits bits 12, 12, 11, 11, 10, 10, 9, and 8 in Table 137 on page 205. • Table 321: “Ordering “Ordering Informatio Information,” n,” on page 319. Revision: 53128-DS04-R Date: 07/21/11 Updated: • General Description

Broadcom ® April 6, 2016 • 53128-DS07-R

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BROADCOM CONFIDENTIAL CONFIDENTIAL

BCM53128 Data Sheet

Revision History

Change Description

Customer Impact

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Section Section 12: 12: “Ordering “Ordering Informatio Information,” n,” on Added ordering information for page 319 part number BCM53128VIQLE(G) Revision: 53128-DS03-R

Action Items No action required.

Date: 12/13/10 Updated: • “IGMP Snooping” on page 49 • “Loo “Loop p Dete Detect ctio ion” n” on page page 52 • “Addre “Address ss Reso Resolut lution ion and Frame Frame Forwarding” on page 59 • “Mul “Multi tica cast st Addr Addres esse ses” s” on page page 61

None. Upda Update ted d refe refere renc nced ed docu docume ment nt.. Edit Edited ed the forw orward ard fiel field. d.

No action required. No acti action on requ requir ired ed.. Corre orrect cted ed typo. ypo.

Remo Remove ved d refe refere renc nce e to IP_MULTICAST bit. Replaced IP_MULTICAST column with UNICAST/ MULTICAST column and updated the forwarding field. Replaced IPMCO with FWD_PRT_MAP. Updated Updated refere referenced nced document. document.

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Table Table 8: “Multi “Multicas castt Forw Forward ard Field Field Definitions,” on page 61

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Table Table 9: “Addre “Address ss Table Table Entry Entry for for Multicast Address,” on page 61 “Energy “Energy Efficient Efficient Ethernet Ethernet Mode” on page 66 “Ser “Seria iall Flas Flash h Int Interf erface” ace” on page page 95 Updat pdated ed SRAM SRAM valu value. e. Figure 44: “Write “Write Access Access to the Register Register Changed Read MII Register 27 Set Using the PseudoPHY PseudoPHY (PHYAD = to Write Register 27. 11110) MDC/MDIO Path,” on page 119 Table 29: “Signal “Signal Type Type Definitions Definitions,” ,” on Updated XTALO signal page 126 description and added GPIO pins. Sectio Section n 6: “Pin “Pin Assi Assignm gnment ent,” ,” on on page page Updated pin assignments to 139 include GPIO pins. “BCM53 “BCM53128 128KQL KQLE E Pin Pin List List by by Ball Ball Upda Update ted d pin pin list list to includ include e GP GPIO IO Name” on page 141 pins Table 31: “Control “Control Registers Registers (Page Added addresses B0h-B7h and 00h),” on page 145 B8h-BFh to table. “PHY “PHY Identi Identifie fierr Regist Register er (Page (Page 10h–17 10h–17h: h: Edited binary OUI. Address 04h)” on page 199 Table 170: “Expansion “Expansion Register Register 45h: Added addresses B8h-BBh and Transmit CRC,” on page 233 BCh-BFh Table Table 295: 295: “Absol “Absolute ute Maximu Maximum m Updated maximum value for Ratings,” on page 299 electrostatic discharge (VESD)

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Table 297: “Electrical “Electrical Character Characteristics istics,” ,” on page 300 • Figure Figure 64: 64: “SPI “SPI Timin Timings, gs, SS SS Assert Asserted ed During SCK High,” on page 313 • Table Table 316: 316: “SPI “SPI Timi Timing ngs, s,”” on page page 313 313 Added:

No action required.

No action required. No action required. required. No act action ion requ requir ired ed.. Corrected typo.

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New feature option available. New feature option available. No action required. Corrected typo. No action required. Corrected typo.

Updated XTALI minimum and maximum. Updated figure.

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Adde Added d time time inte interv rval al rows rows

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BCM53128 Data Sheet

Revision History

Change Description

Customer Impact

“GPIO ” on page 95 Revision: 53128-DS02-R

Action Items New feature option available.

Date: 09/08/10 Updated: • “Deep Green Mode” on page 66. • Figure 45: “LED Interface Interface Register Register Structure Diagram,” on page 121. • Table 29: “Signal “Signal Type Type Definitions Definitions,” ,” on page 125. •

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None. Corre orrect ct edit editin ing g err errors. ors.

Power interface description update to change core power from 1.1V to 1.2V. Table 82: “Aging Time Control Control Register Register Descriptions updated. (Page 02h: Address 06h–09h),” on page 169. “Absol “Absolute ute Maximu Maximum m Rati Ratings ngs”” on Updated core value absolute page 297. maximum rating value. “Recommen “Recommended ded Operating Operating Conditions” Conditions” Updated core voltage 1.2V on page 297. minimum and maximum value of recommended operating conditions. “Electrical “Electrical Characteris Characteristics” tics” on page page 298. 298. Updated Updated maximum maximum power consumption by core 1.2V and IO 3.3V. Sectio Section n 11: “Mecha “Mechanic nical al Inform Informati ation, on,”” on Corre orrect ct edit editin ing g err errors. ors. page 316.

Document Number

Date

53128-DS01-R

04/02/10

53128-DS00-R

12/17/09

No action required. No act action ion requ requir ired ed.. Suggest a review of the schematics. Typo correction.

Suggest a review of the schematics. Suggest a review of the schematics.

Suggest a review of the schematics. No act action ion requ requir ired ed..

Change Description

Updated: • Table Table 3: “Buc “Bucket ket Bit Bit Rate, Rate,”” on page page 44. 44. • Section Section 6: “Pin Assignment, Assignment,”” on page 137. • Section Section 7: “Register “Register Definitions Definitions,” ,” on on page page 141. • Section Section 8: “Electr “Electrical ical Charact Characterist eristics,” ics,” on page page 296. • Section Section 9: “Timing “Timing Charact Characterist eristics,” ics,” on page page 298. 298. • Section Section 10: “Thermal “Thermal Charact Characteristi eristics,” cs,” on page 313. Added: • “TMII “TMII (Turbo (Turbo MII) MII) and RvTMII RvTMII (Rever (Reverse se TMII) TMII) Interfac Interface” e” on page 91. • “Signal “Signal Description Descriptions” s” on page 124. • “LED Contr Control ol Register Register (Page (Page 00h: 00h: Address Address 1Ch)” 1Ch)” on page page 152. • “IMP RGMII RGMII Control Control Register Register (Page (Page 00h: 00h: Address Address 60h)” 60h)” on page 160. • “Page 03h: Interr Interrupt upt Contro Controll Register” Register” on page 175. • “Page 92h: EEE Contro Controll Register Register”” on page 287. Initial release.


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BCM53128 Data Sheet

Table of Contents

Table of Contents About This Document ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................30 ...........30 Purpose and Audience ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 30 Acronyms and Abbreviations........................ Abbreviations................................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........30 30 Document Conventions ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 30 References............ References ....................... ....................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................31 ...........31 Technical Support ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 31

Section 1: Introduction Introduction ............................ .......................................... ............................. ............................. ............................. ............................. ................ 32 Overview............ Overview........................ ....................... ....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................32 ..........32

Section 2: Features Features and Operation ............................ ........................................... ............................. ............................. ......................... .......... 33 Overview of Features and Operation........... Operation....................... ....................... ....................... ........................ ....................... ....................... ........................ .......................33 ...........33 Quality of Service ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........34 34 Egress Transmit Queues........................ Queues.................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 35 Port-Based QoS ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 35 IEEE 802.1p QoS ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 35 MACDA-Based QoS............................... QoS........................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 36 TOS/DSCP QoS............................... QoS........................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........36 36 TC Decision Tree ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 36 Non-BroadSync HD Frame ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 36 BroadSync HD Frame ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................37 ...........37 Queuing Class (COS) Determination ...................... .................................. ........................ ....................... ....................... ........................ ........................ ................... .......37 37 Port-Based VLAN............ VLAN....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........38 38 IEEE 802.1Q VLAN ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 39 IEEE 802.1Q VLAN Table Organization...................... Organization.................................. ........................ ....................... ....................... ........................ ....................... ............... .... 39 Programming the VLAN Table............ Table........................ ....................... ....................... ........................ ........................ ....................... ....................... ........................ .....................40 .........40 Double-Tagging ....................... ................................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................41 ..........41 ISP Port ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 42 Customer Port ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........42 42 Uplink Traffic (from Customer Port to ISP)................................ ISP)............................................ ....................... ....................... ........................ ....................... ............. .. 43 Downlink Traffic (from ISP to Customer Port) ....................... ................................... ....................... ....................... ........................ ....................... ................. ...... 43 Jumbo Frame Support ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................44 ...........44 Port Trunking/Aggregation........... Trunking/Aggregation....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 44 WAN Port........... Port ....................... ....................... ....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................45 ..........45 Rate Control ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 45 Ingress Rate Control ...................... .................................. ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................45 ..........45 Two-Bucket System ....................... ................................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................46 ..........46 Egress Rate Control ....................... ................................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................46 ..........46


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BCM53128 Data Sheet

Table of Contents

Bucket Bit Rate..................... Rate................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........47 47 IMP Port Egress Rate Control ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 47 Protected Ports........... Ports ...................... ....................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................47 ...........47 Port Mirroring............ Mirroring........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 48 Enabling Port Mirroring....................... Mirroring................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 48 Capture Port ....................... ................................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................48 ..........48 Mirror Filtering Rules ...................... .................................. ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................48 ..........48 Port Mask Filter ....................... ................................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................48 ..........48 Packet Address Filter ........................ .................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................49 ...........49 Packet Divider Filter ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 49 IGMP Snooping........... Snooping ...................... ....................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................49 ...........49 MLD Snooping ....................... ................................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................50 ...........50 IEEE 802.1x Port-Based Security ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 50 DoS Attack Prevention.......... Prevention ...................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................51 ...........51 MSTP Multiple Spanning Tree ........................ ................................... ....................... ........................ ........................ ....................... ....................... ........................ .....................52 .........52 Software Reset............ Reset....................... ....................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................52 ...........52 Loop Detection ...................... .................................. ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................52 ...........52 BroadSync HD ....................... ................................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................53 ...........53 Time Base and Slot Generation ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 53 Transmission Shaping and Scheduling ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............... .... 54 BroadSync HD Class 5 Media Traffic....................... Traffic................................... ........................ ....................... ....................... ........................ .......................54 ...........54 BroadSync HD Class 4 Media Traffic....................... Traffic................................... ........................ ....................... ....................... ........................ .......................55 ...........55 CableChecker™............ CableChecker™ ....................... ....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................56 ..........56 Egress PCP Remarking........... Remarking....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ........................ .....................57 .........57 Address Management ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................57 ...........57 Address Table Tabl e Organization................... Organization............................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 58 Address Learning ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 59 Address Resolution and Frame Forwarding.................. Forwarding.............................. ........................ ....................... ....................... ........................ ....................... ............. .. 59 Unicast Addresses ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 59 Multicast Addresses ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 61 Reserved Multicast Addresses....................... Addresses................................... ........................ ........................ ....................... ....................... ........................ .....................62 .........62 Static Address Entries ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........63 63 Accessing the ARL Table Entries................................ Entries............................................ ........................ ....................... ....................... ........................ ....................... ............... .... 63 Reading an ARL Entry ........................ ................................... ....................... ........................ ........................ ....................... ....................... ........................ .....................63 .........63 Writing an ARL Entry....................... Entry................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 63 Searching the ARL Table ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 64 Address Aging A ging ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........64 64 Fast Aging ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 65 Using the Multiport Addresses ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 65


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BCM53128 Data Sheet

Table of Contents

Power Savings Modes........... Modes....................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................65 ...........65 Auto Power Down Mode....................... Mode................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 66 Energy Efficient Ethernet Mode........................ Mode................................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 66 Short Cable Mode (Green Mode) ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 66 Deep Green Mode................................ Mode............................................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 67

Section 3: System Functional Functional Blocks........................... Blocks......................................... ............................ ............................. ....................... ........ 68 Overview of System Functional Blocks ....................... ................................... ........................ ....................... ....................... ........................ ....................... ................. ...... 68 Media Access Controller ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ........................ ................... .......68 68 Receive Function........................ Function.................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 68 Transmit Function....................... Function................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 69 Flow Control ....................... ................................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................69 ..........69 10/100 Mbps Half-Duplex...................... Half-Duplex................................. ....................... ........................ ....................... ....................... ........................ ........................ ................... .......69 69 10/100/1000 Mbps Full-Duplex ...................... .................................. ........................ ........................ ....................... ....................... ........................ .....................69 .........69 Integrated 10/100/1000 PHY.......... PHY ...................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 70 Encoder ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 70 Decoder............................ Decoder........................................ ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................71 ...........71 Link Monitor.............................. Monitor.......................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 71 Digital Adaptive Equalizer ........................ .................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................72 ...........72 Echo Canceler.............................. Canceler.......................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................72 ...........72 Cross Talk Canceler............................... Canceler........................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 72 Analog-to-Digital Converter ........................ ................................... ....................... ........................ ........................ ....................... ....................... ....................... .....................72 ..........72 Clock Recovery/Generator..................... Recovery/Generator................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 73 Baseline Wander Correction ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........73 73 Multimode TX Digital-to-Analog Converter............................ Converter........................................ ....................... ....................... ........................ ....................... ................. ...... 73 Stream Cipher ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........73 73 Wire Map and Pair Skew Correction ....................... ................................... ........................ ....................... ....................... ........................ ........................ ................... .......74 74 Automatic MDI Crossover .......................... ..................................... ....................... ........................ ........................ ....................... ....................... ....................... .....................74 ..........74 10/100BASE-TX Forced Mode Auto-MDIX ....................... ................................... ........................ ....................... ....................... ........................ .....................75 .........75 Resetting the PHY................................ PHY............................................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 75 PHY Address.............................. Address.......................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 76 Super Isolate Mode ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................76 ...........76 Standby Power-Down Mode....................... Mode.................................. ....................... ........................ ........................ ....................... ....................... ........................ .....................76 .........76 Auto Power-Down Mode ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 77 External Loopback Mode........................ Mode.................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 77 Full-Duplex Mode ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 78 Copper Mode ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 78 Master/Slave Configuration ........................ ................................... ....................... ........................ ........................ ....................... ....................... ....................... .....................79 ..........79 Next Page Exchange........................ Exchange.................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........79 79 Frame Management............ Management....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 79


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In-Band Management Port ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................79 ...........79 Broadcom Tag Format for Egress Packet Transfer................................. Transfer............................................ ....................... ........................ .......................81 ...........81 Broadcom Tag Format for Ingress Packet Transfer ........................ ................................... ....................... ........................ ........................ ................... .......82 82 MIB Engine ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 83 MIB Counters Per Port ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 83 Receive Only Counter (19) Description of Counter............................. Counter......................................... ........................ ........................ ................... .......83 83 Transmit Counters Only (19) Description of Counter ....................... .................................. ....................... ........................ .......................85 ...........85 Transmit or Receive Counters (10) Description of Counter ...................... .................................. ........................ ....................... ............. .. 86 Integrated High-Performance Memory ....................... ................................... ........................ ....................... ....................... ........................ ........................ ................... .......90 90 Switch Controller ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........90 90 Buffer Management................ Management............................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 90 Memory Arbitration ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................90 ...........90 Transmit Output Port Queues ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 90

Section 4: System Interfaces................... Interfaces................................. ............................. ............................. ............................. ............................. ................ 92 Overview of System Interfaces ........................ ................................... ....................... ........................ ....................... ....................... ........................ ........................ ................... .......92 92 Copper Interface ...................... .................................. ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................92 ..........92 Auto-Negotiation................... Auto-Negotiation........ ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........92 92 Line-side (Remote) Loopback Mode ....................... ................................... ........................ ....................... ....................... ........................ ........................ ................... .......93 93 Frame Management Port Interface........... Interface....................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 93 MII Interface ....................... ................................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................93 ..........93 TMII (Turbo MII) and RvTMII (Reverse TMII) Interface ....................... .................................. ....................... ........................ ....................... ............... .... 93 Reverse MII Port (RvMII).................. (RvMII).............................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........93 93 GMII Port ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 94 RGMII Port ....................... ................................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................94 ...........94 Configuration Pins ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 94 Programming Interfaces ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ........................ ................... .......95 95 Serial Flash Interface ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........95 95 GPIO ....................... .................................. ....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................95 ..........95 SPI-Compatible Programming Interface.................... Interface................................ ........................ ....................... ....................... ........................ ....................... ................. ...... 96 SS: Slave Select ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........96 96 SCK: Serial Clock........................ Clock.................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 96 MOSI: Master Output Slave Input ...................... .................................. ........................ ....................... ....................... ........................ ....................... ................. ...... 96 MISO: Master Input Slave Output ...................... .................................. ........................ ....................... ....................... ........................ ....................... ................. ...... 97 Without External PHY ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................98 ...........98 External PHY Registers ........................ ................................... ....................... ........................ ....................... ....................... ........................ ........................ ................... .......99 99 Reading and Writing BCM53128 Registers Using SPI ........................... ....................................... ........................ ....................... ............... .... 99 Normal Read Operation ........................ ................................... ....................... ........................ ....................... ....................... ........................ ........................ ................. ..... 100 Fast Read Operation................... Operation............................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 104 Normal Write Operation ........................ ................................... ....................... ........................ ....................... ....................... ........................ ........................ ................. ..... 107


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EEPROM Interface............................. Interface......................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 110 EEPROM Format ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 110 MDC/MDIO Interface ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 112 MDC/MDIO Interface Register Programming.................. Programming.............................. ........................ ....................... ....................... ........................ .....................112 .........112 PseudoPHY.............................. PseudoPHY................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 113 LED Interfaces ....................... ................................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .....................119 .........119 Dual Input Configuration/LED Output Function ....................... ................................... ....................... ....................... ........................ ....................... ............. .. 123

Section 5: Hardware Signal Definition Table ............................. ........................................... ............................. ..................... ...... 124 I/O Signal Types............ Types....................... ....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........124 124 Signal Descriptions ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 125

Section 6: Pin Assignment Assignment ............................. ............................................ ............................. ............................ ............................. ..................... ...... 138 BCM53128KQLE Pin List by Signal Name........... Name ...................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 138 BCM53128KQLE Pin List by Ball Number ........... Number ...................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 140

Section 7: Register Definitions Definitions ........................... ......................................... ............................. ............................. ............................. ................. 142 Register Definition............ Definition....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 142 Register Notations............ Notations....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 142 Global Page Register ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................142 ...........142 Page 00h: Control Registers ........................ .................................... ....................... ....................... ........................ ....................... ....................... ........................ .....................144 .........144 Port Traffic Control Register (Page 00h: Address 00h) ....................... .................................. ....................... ........................ ....................... ............. .. 146 IMP Port Control Register (Page 00h: Address 08h) ........................ ................................... ....................... ........................ ....................... ............... .... 147 Switch Mode Register (Page 00h: Address 0Bh) ...................... .................................. ....................... ....................... ........................ .......................148 ...........148 IMP Port State Override Register (Page 00h: Address 0Eh) ......................... ..................................... ........................ ....................... ............. .. 148 LED Control Register (Page 00h: Address 0Fh–1Bh)..................... 0Fh–1Bh)................................ ....................... ........................ ........................ ................. ..... 149 LED Refresh Register (Page 00h: Address 0Fh) ...................... .................................. ....................... ....................... ........................ .......................149 ...........149 LED Function 0 Control Register (Page 00h: Address 10h)....................... 10h)................................... ........................ ........................ ................. ..... 150 LED Function 1 Control Register (Page 00h: Address 12h)....................... 12h)................................... ........................ ........................ ................. ..... 151 LED Function Map Register (Page 00h: Address 14h–15h) ...................... .................................. ........................ ........................ ................. ..... 151 LED Enable Map Register (Page 00h: Address 16h–17h).................... 16h–17h)............................... ....................... ........................ .......................152 ...........152 LED Mode Map 0 Register (Page 00h: Address 18h–19h) ....................... .................................. ....................... ........................ ................... .......152 152 LED Mode Map 1 Register (Page 00h: Address 1Ah–1Bh) ....................... ................................... ........................ ........................ ................. ..... 152 LED Control Register (Page 00h: Address 1Ch)............................... 1Ch).......................................... ....................... ........................ ....................... ............... .... 153 PHY LED Control Register (Page 00h: Address 1Dh) ........................ ................................... ....................... ........................ ....................... ............. .. 153 Port Forward Control Register (Page 00h: Address 21h)................................. 21h)............................................. ........................ .......................154 ...........154 Protected Port Selection Register (Page 00h: Address 24h–25h) ....................... ................................... ........................ ................... .......155 155 WAN Port Select Register (Page 00h: Address 26h–27h) ........................ ................................... ....................... ........................ ................... .......155 155 Pause Capability Register (Page 00h: Address 28h–2Bh)........................ 28h–2Bh)................................... ....................... ........................ ................... .......155 155 Reserved Multicast Control Register (Page 00h: Address 2Fh)......................... 2Fh)..................................... ........................ .....................156 .........156 Unicast Lookup Failed Forward Map Register (Page 00h: A ddress 32h) ...................... .................................. .....................157 .........157


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Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h) ........................ .................................157 .........157 MLF IPMC Forward Map Register (Page 00h: Address 36h–37h)............ 36h–37h) ....................... ....................... ........................ ................... .......158 158 Pause Pass Through for RX Register (Page 00h: Address 38h–39h) ....................... ................................... ....................... ............. .. 158 Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh) ....................... ................................... ....................... ............. .. 158 Disable Learning Register (Page 00h: Address 3Ch–3Dh)............................ 3Ch–3Dh)........................................ ........................ ....................... ............. .. 159 Software Learning Register (Page 00h: Address 3Eh–3Fh) ...................... .................................. ........................ ........................ ................. ..... 159 Port State Override Register (Page 00h: Address 58h) ........................ ................................... ....................... ........................ .......................160 ...........160 IMP RGMII Control Register (Page 00h: Address 60h)........... 60h) ....................... ....................... ....................... ........................ ....................... ............. .. 161 MDIO IMP Port Address Register (Page 00h: Address 78h) ................................. ............................................. ........................ ................. ..... 161 Software Reset Control Register (Page 00h: Address 79h)................................. 79h)............................................. ........................ ................... .......161 161 Pause Frame Detection Control Register (Page 00h: Address 80h)........................ 80h).................................... ....................... ............... .... 162 Fast-Aging Control Register (Page 00h: Address 88h) ....................... .................................. ....................... ........................ ....................... ............. .. 162 Fast-Aging Port Control Register (Page 00h: Address 89h) ................................ ............................................ ........................ ................... .......162 162 Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh) ...................... .................................. ........................ .....................163 .........163 CPU Data 0 Share Register (Page 00h: Address B0h-B7h) ...................... .................................. ........................ ........................ ................. ..... 163 CPU Data 1 Share Register (Page 00h: Address B8h-BFh) ....................... ................................... ........................ ....................... ............... .... 163 Page 01h: Status Registers ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 164 Link Status Summary (Page 01h: Address 00h) ....................... ................................... ....................... ....................... ........................ .......................164 ...........164 Link Status Change (Page 01h: Address 02h) ...................... .................................. ....................... ....................... ........................ ....................... ............... .... 165 Port Speed Summary (Page 01h: Address 04h) ....................... ................................... ....................... ....................... ........................ .......................165 ...........165 Duplex Status S tatus Summary (Page 01h: Address 08h)........... 08h) ....................... ........................ ....................... ....................... ........................ ................... .......166 166 Pause Status Summary (Page 01h: Address 0Ah) ....................... ................................... ....................... ....................... ........................ ................... .......166 166 Source Address Change Register (Page 01h: Address 0Eh) ................................ ............................................ ........................ ................. ..... 167 Last Source Address Register (Page 01h: Address 10h)............................... 10h)........................................... ........................ ....................... ............. .. 167 Page 02h: Management/Mirroring Registers ....................... ................................... ........................ ....................... ....................... ........................ ................... .......168 168 Global Management Configuration Register (Page 02h: Address 00h) ....................... ................................... .......................169 ...........169 IMP Port ID Register (Page 02h: Address 01h) ...................... .................................. ....................... ....................... ........................ ....................... ............. .. 169 Broadcom Header Control Register (Page 02h: Address 03h) ...................... .................................. ........................ ....................... ............. .. 170 RMON MIB Steering Register (Page 02h: Address 04h) ........................ ................................... ....................... ........................ .....................170 .........170 Aging Time Control Register (Page 02h: Address 06h) ........................ ................................... ....................... ........................ .......................170 ...........170 Mirror Capture Control Register (Page 02h: Address 10h) ....................... .................................. ....................... ........................ ................... .......171 171 Ingress Mirror Control Register (Page 02h: Address 12h) ........................ ................................... ....................... ........................ ................... .......171 171 Ingress Mirror Divider Register (Page 02h: Address 14h)................................ 14h)............................................ ........................ .......................172 ...........172 Ingress Mirror MAC Address Register (Page 02h: Address 16h)......................... 16h)..................................... ........................ ................... .......172 172 Egress Mirror Control Register (Page 02h: Address 1Ch) ........................ ................................... ....................... ........................ ................... .......173 173 Egress Mirror Divider Register (Page 02h: Address 1Eh) ....................... .................................. ....................... ........................ .....................174 .........174 Egress Mirror MAC Address Register (Page 02h: Address 20h) ....................... ................................... ........................ .....................174 .........174 Device ID Register (Page 02h: Address 30h–33h) ............................. ........................................ ....................... ........................ ....................... ............. .. 174 Revision Number Register (Page 02h: Address 40h) ........................... ...................................... ....................... ........................ .......................174 ...........174


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High-Level Protocol Control Register (Page 02h: Address 50h–53h) ...................... .................................. ....................... ............... .... 175 Page 03h: Interrupt Control Register ....................... .................................. ....................... ........................ ....................... ....................... ........................ .....................177 .........177 Interrupt Status Register (Page 03h: Address 00h) ............................ ....................................... ....................... ........................ ....................... ............. .. 177 Interrupt Enable Register (Page 03h: Address 08h) ........................... ...................................... ....................... ........................ ....................... ............. .. 177 IMP Sleep Timer Register (Page 03h: Address 10h) ........................ ................................... ....................... ........................ ....................... ............... .... 178 Sleep Status Register (Page 03h: Address 18h)....................... 18h)................................... ....................... ....................... ........................ .......................178 ...........178 External CPU Interrupt Trigger Register (Page 03h: Address 20h) ............................. ......................................... .......................178 ...........178 Page 04h: ARL Control Register ............ Register ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 179 Global ARL Configuration Register (Page 04h: Address 00h) ....................... ................................... ........................ ....................... ............. .. 180 BPDU Multicast Address Register (Page 04h: Address 04h)............................... 04h)........................................... ........................ ................... .......180 180 Multiport Control Register (Page 04h: Address 0Eh–0Fh) ........................ ................................... ....................... ........................ ................... .......181 181 Multiport Address N (N=0–5) Register (Page 04h: Address 10h) ...................... .................................. ........................ .....................182 .........182 Multiport Vector N (N = 0–5) Register (Page 04h: Address 18h) ....................... ................................... ........................ .....................183 .........183 Page 05h: ARL/VTBL Access Registers............ Registers ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 184 ARL Table Tabl e Read/Write Control Register (Page 05h: Address 00h) ............................. ......................................... .......................185 ...........185 MAC Address Index Register (Page 05h: Address 02h) ....................... .................................. ....................... ........................ .......................185 ...........185 VLAN ID Index Register (Page 05h: Address 08h) ....................... ................................... ....................... ....................... ........................ ................... .......186 186 ARL Table Tabl e MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)............................. 10h)........................................ ............. .. 186 ARL Table Tabl e Data Entry N (N = 0–3) Register (Page 05h: Address 18h) ....................... ................................... .......................187 ...........187 ARL Table Tabl e Search Control Register (Page 05h: Address 50h) ...................... .................................. ........................ ....................... ............. .. 188 ARL Search S earch Address Register (Page 05h: Address 51h) ............................ ........................................ ........................ ....................... ............... .... 189 ARL Table Tabl e Search MAC/VID Result N (N=0-1) Register (Page 05h: Address 60h) ........................... ........................... 189 ARL Table Tabl e Search Data Result N (N = 0-1) Register (Page 05h: Address A ddress 68h) ........................ .................................190 .........190 VLAN Table Read/Write/Clear Control Register (Page 05h: Address 80h) ....................... ................................... ................. ..... 191 VLAN Table Address Index Register (Page 05h: Address 81h)............................. 81h)......................................... ........................ ................. ..... 192 VLAN Table Entry Register (Page 05h: Address 83h–86h) ....................... ................................... ........................ ........................ ................. ..... 192 Page 10h–17h: Internal GPHY MII Registers ...................... .................................. ........................ ....................... ....................... ........................ .....................194 .........194 MII Control Register (Page 10h–17h: Address 00h–01h) .......................... ...................................... ........................ ........................ ................. ..... 196 MII Status Register (Page 10h–17h: Address 02h)................................. 02h)............................................ ....................... ........................ .....................197 .........197 PHY Identifier Register (Page 10h–17h: Address 04h)................................ 04h)............................................ ........................ ....................... ............... .... 198 Auto-Negotiation Advertisement Register (Page 10h–17h: Address 08h) ....................... ................................... ................... .......199 199 Auto-Negotiation Link Partner Ability Abil ity Register (Page 10h–17h: Address A ddress 0Ah) ........................ ...................................200 ...........200 Next Page ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 201 Acknowledge............................... Acknowledge................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 201 Auto-Negotiation Expansion Register (Page 10h–17h: Address 0Ch)............................... 0Ch)........................................... ................. ..... 201 Next Page Transmit Register (Page 10h–17h: Address 0Eh) ...................... .................................. ........................ ....................... ............... .... 202 Link Partner Received Next Page Register (Page 10h–17h: Address 10h)................................. 10h)........................................ .......203 203 1000BASE-T Control Register (Page 10h–17h: Address 12h) ........................ .................................... ........................ .......................204 ...........204 Test Mode ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 204


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Master/Slave Configuration Enable.......................... Enable...................................... ........................ ....................... ....................... ........................ .....................205 .........205 1000BASE-T Status Register (Page 10h–17h: Address 14h)................................ 14h)............................................ ........................ ................. ..... 205 IEEE Extended Status Register (Page 10h–17h: Address 1Eh) ...................... .................................. ........................ .......................206 ...........206 PHY Extended Control Register (Page 10h–17h: Address 20h) ...................... .................................. ........................ .......................207 ...........207 PHY Extended Status Register (Page 10h–17h: Address 22h) ....................... ................................... ........................ .......................208 ...........208 Receive Error Counter Register (Page 10h–17h: Address 24h) ...................... .................................. ........................ .......................209 ...........209 Copper Receive Error Counter...................... Counter................................. ....................... ........................ ....................... ....................... ........................ .....................209 .........209 False Carrier Sense Counter Register (Page 10h–17h: Address 26h) ...................... .................................. ....................... ............. .. 209 Copper False Carrier Sense Counter..................... Counter................................. ........................ ....................... ....................... ........................ .......................209 ...........209 10BASE-T/100BASE-TX/1000BASE-T Packets Received with Transmit Error Codes Counter......... Counter......... 210 Packets Received with Transmit Error Codes Counter............................... Counter........................................... ........................ .....................210 .........210 Receiver NOT_OK Counter Register (Page 10h–17h: Address 28h) ...................... .................................. ....................... ............... .... 210 Copper Local Receiver NOT_OK Counter ....................... ................................... ....................... ....................... ........................ ....................... ............. .. 210 Copper Remote Receiver NOT_OK Counter ....................... ................................... ....................... ....................... ........................ .....................210 .........210 Receive CRC Counter Register (Page 10h–17h: Address 28h) .......................... ...................................... ........................ ................... .......211 211 Copper CRC Counter.............................. Counter......................................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 211 Expansion Register Access Register (Page 10h–17h: Address 2Eh)................................ 2Eh)............................................ ................. ..... 211 Expansion Register Select ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 211 Expansion Register Accessed ....................... ................................... ........................ ........................ ....................... ....................... ........................ ................... .......212 212 Auxiliary Control Shadow S hadow Value Val ue Access Register (Page 10h–17h: Address 30h) ....................... .............................. .......212 212 External Loopback ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 213 Receive Extended Packet Length ...................... .................................. ........................ ....................... ....................... ........................ ....................... ............... .... 214 Edge Rate Control (1000BASE-T) ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............. .. 214 Edge Rate Control (100BASE-TX)................... (100BASE-TX)............................... ........................ ....................... ....................... ........................ ........................ ................. ..... 214 Shadow Register Select................................ Select........................................... ....................... ........................ ....................... ....................... ........................ .....................214 .........214 10BASE-T Register ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ .....................214 .........214 Power/MII Control Register (Page 10h–17h: Address 30h) ....................... ................................... ........................ ........................ ................. ..... 215 Super Isolate (Copper Only) ....................... .................................. ....................... ........................ ....................... ....................... ........................ .......................215 ...........215 Shadow Register Select................................ Select........................................... ....................... ........................ ....................... ....................... ........................ .....................216 .........216 Miscellaneous Test Register (Page 10h–17h: Address 30h) ....................... ................................... ........................ ....................... ............... .... 216 Miscellaneous Control Register (Page 10h–17h: Address 30h)......................... 30h)..................................... ........................ .....................217 .........217 Auxiliary Status Summary Register (Page 10h–17h: Address A ddress 32h) ....................... ................................... ........................ ................. ..... 218 Interrupt Status Register (Page 10h–17h: Address 34h) ........................... ....................................... ........................ ........................ ................. ..... 219 Interrupt Mask Register (Page 10h–17h: Address 36h) ........................ ................................... ....................... ........................ .......................220 ...........220 Interrupt Mask Vector................................ Vector........................................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 220 10BASE-T/100BASE-TX/1000BASE-T Register 38h Access ...................... .................................. ........................ ....................... ............... .... 221 Spare Control 2 Register (Page 10h–17h: Address 38h) ........................ ................................... ....................... ........................ .....................221 .........221 Auto Power-Down Register (Page 10h–17h: Address 38h) ....................... ................................... ........................ ........................ ................. ..... 222 LED Selector 2 Register (Page 10h–17h: Address 38h) ....................... .................................. ....................... ........................ .......................223 ...........223


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Table of Contents

Mode Control Register (Page 10h–17h: Address 38h) ........................... ...................................... ....................... ........................ .....................225 .........225 Master/Slave Seed Register (Page 10h–17h: Address 3Ah) ....................... ................................... ........................ ....................... ............... .... 226 HCD Status Register (Page 10h–17h: Address 3Ah)........................ 3Ah)................................... ....................... ........................ ....................... ............... .... 227 Test Register 1 (Page 10h–17h: Address 3Ch) ...................... .................................. ....................... ....................... ........................ ....................... ............. .. 228 Expansion Registers............ Registers ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................229 ...........229 Expansion Register 00h: Receive/Transmit Packet Counter ................................. ............................................. ........................ ................. ..... 229 Packet Counter (Copper Only)............................... Only)........................................... ........................ ....................... ....................... ........................ .......................229 ...........229 Expansion Register 01h: Expansion Interrupt Status ........................ ................................... ....................... ........................ ....................... ............... .... 229 Transmit CRC Error ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 229 Expansion Register 45h: Transmit CRC Enable ....................... ................................... ....................... ....................... ........................ .......................230 ...........230 Transmit CRC Checker ....................... .................................. ....................... ........................ ........................ ....................... ....................... ........................ ................... .......230 230 Page 20h–28h: Port MIB Registers ........................ ................................... ....................... ........................ ....................... ....................... ........................ .......................230 ...........230 Page 30h: QoS Registers.......... Registers ...................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ........................ ................. ..... 235 QoS Global Control Register (Page 30h: Address 00h) ........................ ................................... ....................... ........................ .......................236 ...........236 QoS IEEE 802.1p Enable Register (Page 30h: Address 04h) ........................... ....................................... ........................ .....................236 .........236 QoS DiffServ Enable Register (Page 30h: Address 06h) ........................ ................................... ....................... ........................ .....................237 .........237 Port N (N = 0-7, 8) PCP_To_TC Register (Page 30h: Address 10h) ....................... ................................... ....................... ............... .... 237 DiffServ Priority Map 0 Register (Page 30h: Address 40h) ....................... .................................. ....................... ........................ ................... .......238 238 DiffServ Priority Map 1 Register (Page 30h: Address 46h) ....................... .................................. ....................... ........................ ................... .......239 239 DiffServ Priority Map 2 Register (Page 30h: Address 4Ch) ....................... ................................... ........................ ........................ ................. ..... 239 DiffServ Priority Map 3 Register (Page 30h: Address 52h) ....................... .................................. ....................... ........................ ................... .......240 240 TC_To_COS Mapping Register (Page 30h: Address 62h–63h) ........................ .................................... ........................ .....................241 .........241 CPU_To_COS Map Register (Page 30h: Address 64h–67h) .......................... ...................................... ........................ .......................242 ...........242 TX Queue Control Register (Page 30h: Address 80h) ........................ ................................... ....................... ........................ ....................... ............. .. 243 TX Queue Weight Register (Page 30h: Address 81h) ............................... ........................................... ........................ ........................ ................. ..... 243 COS4 Service Weight Register (Page 30h: Address 85h–86h) ....................... ................................... ........................ .......................244 ...........244 Page 31h: Port-Based VLAN Registers ...................... .................................. ........................ ....................... ....................... ........................ ........................ ................. ..... 245 Port-Based VLAN Control Register (Page 31h: Address 00h) ....................... ................................... ........................ ....................... ............. .. 245 Page 32h: Trunking Registers............ Registers........................ ....................... ....................... ........................ ........................ ....................... ....................... ........................ ................... .......246 246 MAC Trunking Control Register (Page 32h: Address 00h) ................................ ............................................ ........................ .....................246 .........246 Trunking Group 0 Register (Page 32h: Address 10h) ....................... .................................. ....................... ........................ ....................... ............... .... 247 Trunking Group 1 Register (Page 32h: Address 12h) ....................... .................................. ....................... ........................ ....................... ............... .... 247 Page 34h: IEEE 802.1Q VLAN Registers ...................... .................................. ........................ ....................... ....................... ........................ ....................... ............... .... 248 Global IEEE 802.1Q Register (Pages 34h: Address 00h) ....................... .................................. ....................... ........................ .....................248 .........248 Global IEEE 802.1Q VLAN Control 1 Register (Page 34h: Address 01h)........................ 01h).................................... ................... .......250 250 Global VLAN Control 2 Register (Page 34h: Address 02h)........................ 02h).................................... ........................ ........................ ................. ..... 251 Global VLAN Control 3 Register (Page 34h: Address 03h)........................ 03h).................................... ........................ ........................ ................. ..... 251 Global VLAN Control 4 Register (Page 34h: Address 05h)........................ 05h).................................... ........................ ........................ ................. ..... 252 Global VLAN Control 5 Register (Page 34h: Address 06h)........................ 06h).................................... ........................ ........................ ................. ..... 253


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Table of Contents

VLAN Multiport Address Control Register (Page 34h: Address 0Ah–0Bh) ........................ .................................... ................. ..... 254 Default IEEE 802.1Q Tag Register (Page 34h: Address 10h) ................................. ............................................. ....................... ............... .... 255 Double Tagging TPID Register (Page 34h: Address 30h–31h) ................................. ............................................. ....................... ............. .. 256 ISP Port Selection Portmap Register (Page 34h: Address 32h–33h) ...................... .................................. ....................... ............... .... 256 Page 36h: DOS Prevent Register ........... Register ....................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 257 DOS Control Register (Page 36h: Address 00h–03h) ....................... .................................. ....................... ........................ ....................... ............... .... 257 Minimum TCP Header Size Register (Page 36h: Address 04h) ............................ ........................................ ........................ ................. ..... 259 Maximum ICMPv4 Size Register (Page 36h: Address 08h–0Bh) ...................... .................................. ........................ .....................259 .........259 Maximum ICMPv6 Size Register (Page 36h: Address 0Ch–0Fh) ...................... .................................. ........................ .....................259 .........259 DOS Disable Learn Register (Page 36h: Address 10h) ........................ ................................... ....................... ........................ .......................259 ...........259 Page 40h: Jumbo Frame Control Register ....................... ................................... ........................ ....................... ....................... ........................ .......................260 ...........260 Jumbo Frame Port Mask Register (Page 40h: Address 01h)......................... 01h)..................................... ........................ ....................... ............. .. 260 Standard Max Frame Size Register (Page 40h: Address 05h) ...................... .................................. ........................ ....................... ............. .. 261 Page 41h: Broadcast Storm Suppression Register ........................ .................................... ....................... ....................... ........................ ................... .......262 262 Ingress Rate Control Configuration Register (Page 41h: Address 00h) ....................... ................................... .......................262 ...........262 Port Receive Rate Control Register (Page 41h: Address 10h) ...................... .................................. ........................ ....................... ............. .. 264 Port Egress Rate Control Configuration Register (Page 41h: Address 80h–91h)........................ 80h–91h)............................... .......266 266 IMP Port Egress Rate Control Configuration Register (Page 41h: Address C0h)........................... C0h)............................... .... 267 Page 42h: EAP Register ...................... .................................. ....................... ....................... ........................ ........................ ....................... ....................... ........................ ................... .......268 268 EAP Global Control Register (Page 42h: Address 00h) ........................ ................................... ....................... ........................ .......................269 ...........269 EAP Multiport Address Control Register (Page 42h: Address 01h) ....................... ................................... ........................ ................. ..... 269 EAP Destination IP Register 0 (Page 42h: Address 02h) ......................... .................................... ....................... ........................ ................... .......270 270 EAP Destination IP Register 1 (Page 42h: Address 0Ah) ....................... .................................. ....................... ........................ .....................270 .........270 Port EAP Configuration Register (Page 42h: Address 20h)............................... 20h)........................................... ........................ .....................271 .........271 Page 43h: MSPT Register ........... Register ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 272 MSPT Control Register (Page 43h: Address 00h) ........................ .................................... ....................... ....................... ........................ ................... .......272 272 MSPT Aging Control Register (Page 43h: Address 02h) ........................ ................................... ....................... ........................ .....................272 .........272 MSPT Table Register (Page 43h: Address 10h) ....................... ................................... ....................... ....................... ........................ .......................273 ...........273 SPT Multiport Address Bypass Control Register (Page 43h: Address 50h–51h)......................... 50h–51h)................................ .......274 274 Page 70h: MIB Snapshot Control Register ...................... .................................. ........................ ....................... ....................... ........................ .......................275 ...........275 MIB Snapshot Control Register (Page 70h: Address 00h) ........................ ................................... ....................... ........................ ................... .......275 275 Page 71h: Port Snapshot MIB Control Register .......... Register ...................... ........................ ....................... ....................... ........................ ....................... ............... .... 275 Page 72h: Loop Detection Register ....................... .................................. ....................... ........................ ....................... ....................... ........................ .......................276 ...........276 Loop Detection Control Register (Page 72h: Address 00h) ....................... ................................... ........................ ........................ ................. ..... 276 Discovery Frame Timer Control Register (Page 72h: Address 02h) ...................... .................................. ........................ ................. ..... 276 LED Warning Port Map Register (Page 72h: Address 03h) ....................... ................................... ........................ ........................ ................. ..... 277 Module ID 0 Register (Page 72h: Address 05h).......... 05h) ...................... ........................ ....................... ....................... ........................ ....................... ............. .. 277 Module ID 1 Register (Page 72h: Address 0Bh) ....................... ................................... ....................... ....................... ........................ .......................278 ...........278 Loop Detect Source Address Register (Page 72h: Address 11h) ...................... .................................. ........................ .....................278 .........278


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BCM53128 Data Sheet

Table of Contents

Page 88h: IMP Port External PHY MII Registers Page Summary ...................... .................................. ........................ .......................278 ...........278 Page 90h: BroadSync HD Register ............ Register ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................279 ...........279 BroadSync HD Enable Control Register (Page 90h: Address 00h–01h) ....................... ................................... .....................280 .........280 BroadSync HD Time Stamp Report Control Register (Page 90h: Address 02h) ......................... ................................ .......280 280 BroadSync HD PCP Value Control Register (Page 90h: Address 03h) ....................... ................................... .......................280 ...........280 BroadSync HD Max Packet Size Register (Page 90h: Address 04h) ............................ ........................................ .....................281 .........281 BroadSync HD Time Base Register (Page 90h: Address 10h–13h) ...................... .................................. ........................ ................. ..... 281 BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17) ....................... ..................................281 ...........281 BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh) ...................282 ...................282 BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh) ....................... ................................... ................... .......282 282 BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h)................................ 30h).................................. .. 283 BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h)................................ 60h).................................. .. 283 BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h)............................ 90h)........................................ ................. ..... 284 BroadSync HD Egress Time Stamp Status Register (Page 90h: Address D0h)............................... D0h)................................. .. 284 BroadSync HD Link Status Register (Page 90h: Address E0h–E1h)......................... E0h–E1h)..................................... ....................... ............. .. 285 Page 91h: Traffic Remarking Register ...................... .................................. ........................ ........................ ....................... ....................... ........................ ................... .......286 286 Traffic Remarking Control Register (Page 91h: Address 00h) ....................... ................................... ........................ ....................... ............. .. 286 Egress Egress Non-BroadSync Non-BroadSync HD Packet TC to PCP Mapping Register Register (Page 91h: Address 10h) ........ ............287 ....287 Page 92h: EEE Control Register ............ Register ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 288 EEE Enable Control Register (Page 92h: Address 00h) ....................... .................................. ....................... ........................ .......................288 ...........288 EEE LPI Assert Register (Page 92h: Address 02h) ........................ ................................... ....................... ........................ ........................ ................. ..... 289 EEE LPI Indicate Register (Page 92h: Address 04h) ........................ ................................... ....................... ........................ ....................... ............... .... 289 EEE RX Idle Symbol Register (Page 92h: Address 06h) ........................ ................................... ....................... ........................ .....................289 .........289 EEE Pipeline Timer Register (Page 92h: Address 0Ch) ....................... .................................. ....................... ........................ .......................290 ...........290 EEE Sleep Timer Gig Register (Page 92h: Address 10h) ....................... .................................. ....................... ........................ .....................290 .........290 EEE Sleep Timer FE Register (Page 92h: Address 34h) ........................ ................................... ....................... ........................ .....................291 .........291 EEE Min LP Timer Gig Register (Page 92h: Address 58h)................................ 58h)............................................ ........................ .....................291 .........291 EEE Min LP Timer FE Register (Page 92h: Address 7Ch) ....................... .................................. ....................... ........................ ................... .......292 292 EEE Wake Timer Gig Register (Page 92h: Address A0h) ......................... ..................................... ........................ ........................ ................. ..... 292 EEE Wake Timer FE Register (Page 92h: Address B2h) .......................... ...................................... ........................ ........................ ................. ..... 293 EEE GLB Congst TH Register (Page 92h: Address C4h) ....................... .................................. ....................... ........................ .....................293 .........293 EEE TXQ Cong TH Register (Page 92h: Address C6h) ......................... .................................... ....................... ........................ .....................293 .........293 Global Registers ...................... .................................. ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........295 295 SPI Data I/O Register (Global, Address F0h)........................ F0h).................................... ....................... ....................... ........................ ....................... ............... .... 295 SPI Status Register (Global, Address FEh) ................................ ............................................ ....................... ....................... ........................ .....................295 .........295 Page Register (Global, Address FFh) ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............... .... 296

Section 8: Electrical Electrical Characteristics Characteristics ............................ .......................................... ............................. ............................. .................... ...... 297 Absolute Maximum Ratings ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................297 ...........297 Recommended Operating Conditions........... Conditions ...................... ....................... ........................ ........................ ....................... ....................... ........................ ................... .......297 297


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Table of Contents

Electrical Characteristics. Characteristics........................ ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 298

Section 9: Timing Characteristics.............. Characteristics............................ ............................ ............................. ............................. ......................... ........... 299 Reset and Clock Timing.......... Timing ...................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ........................ ................... .......299 299 MII Interface Timing............ Timing ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 300 MII Input Timing........................ Timing.................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 300 MII Output Timing................................. Timing............................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 300 TMII Interface Timing............ Timing....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................301 ...........301 TMII Input Timing ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................301 ...........301 TMII Output Timing......................... Timing..................................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........302 302 Reverse MII/TMII Interface Timing............ Timing........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 302 Reverse MII/TMII Input Timing ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 302 Reverse MII Output Timing ........................ ................................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........303 303 RGMII Interface Timing ....................... ................................... ....................... ....................... ........................ ........................ ....................... ....................... ........................ ................... .......304 304 RGMII Output Timing (Normal Mode) ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............... .... 304 RGMII Output Timing (Delayed Mode).............................. Mode).......................................... ........................ ....................... ....................... ........................ ................... .......305 305 RGMII Input Timing (Normal Mode) ...................... .................................. ........................ ........................ ....................... ....................... ........................ ................... .......306 306 RGMII Input Timing (Delayed Mode)....................... Mode)................................... ........................ ....................... ....................... ........................ ........................ ................. ..... 307 GMII Interface Timing ...................... .................................. ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................308 ...........308 GMII Interface Output Timing ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 308 GMII Interface Input Timing.................................. Timing............................................. ....................... ........................ ....................... ....................... ........................ .....................308 .........308 MDC/MDIO Timing ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 309 Serial LED Interface Timing.......... Timing ...................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 310 SPI Timings ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 311 EEPROM Timing ...................... .................................. ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........312 312 Serial Flash Timing........... Timing...................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 313

Section 10: Thermal Characteristics Characteristics ............................ .......................................... ............................. ............................. .................... ...... 314 Section 11: Mechanical Mechanical Information Information ............................. ........................................... ............................ ............................. ..................... ...... 316 Section 12: Ordering Information Information ............................ .......................................... ............................. ............................. ......................... ........... 317


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BCM53128 Data Sheet

List of Figures

List of Figures Figure 1: Functional Functional Block Diagram Diagram............ ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... .....................2 ..........2 Figure 2: QoS Program Program Flow ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........34 34 Figure 3: VLAN Table Organizat Organization ion............ ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................... ........39 39 Figure 4: 4: ISP Tag Diagram Diagram ....................... ................................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... .....................41 ..........41 Figure 5: Trunking Trunking............ ....................... ....................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................44 ...........44 Figure 6: Bucket Flow ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 45 Figure 7: Mirror Mirror Filter Flow.......... Flow...................... ........................ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................48 ...........48 Figure 8: BroadSync BroadSync HD Shaping and Scheduling Scheduling.......... ...................... ........................ ........................ ....................... ....................... ........................ .....................54 .........54 Figure 9: Address Address Table Organization Organization............ ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 58 Figure 10: IMP Packet Encapsulation Encapsulation Format Format ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............... .... 80 Figure 11: TXQ and Buffer Tag Structur Structure e ....................... .................................. ....................... ........................ ....................... ....................... ........................ .......................91 ...........91 Figure 12: RvMII RvMII Port Connection Connection........... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................94 ...........94 Figure 13: Normal Normal SPI Command Command Byte........... Byte....................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 97 Figure 14: Fast SPI Command Command Byte ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ................... ........97 97 Figure 15: SPI Serial Interface Interface Write Operation Operation............ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 98 Figure 16: SPI Serial Interface Interface Read Operation Operation ...................... .................................. ........................ ....................... ....................... ........................ ....................... ............. .. 98 Figure 17: SPI Interface Interface Without External External PHY Device ....................... ................................... ....................... ....................... ........................ ....................... ............. .. 98 Figure 18: Accessing Accessing External PHY Registers Registers............ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 99 Figure 19: Normal Normal Read Operation Operation ....................... .................................. ....................... ........................ ........................ ....................... ....................... ....................... ................... ........101 101 Figure 20: Normal Normal Read Mode to Check the SPIF Bit of SPI Status Register Register ...................... .................................. ....................... ............. .. 102 Figure 21: Normal Normal Read Mode to Setup the Accessed Register Register Page Value........... Value....................... ........................ ....................... ............. .. 102 Figure 22: Normal Normal Read Mode to Setup the Accessed Register Register Address Value (Dummy Read) Read).................. ..................103 103 Figure 23: Normal Normal Read Mode to Check the SPI Status for Completion Completion of Read ........................ .................................... ................. ..... 103 Figure 24: Normal Normal Read Mode to Obtain the Register Content Content........... ....................... ....................... ....................... ........................ .......................104 ...........104 Figure 25: Fast Read Operatio Operation n ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ .......................105 ...........105 Figure 26: Normal Normal Read Mode to Check the SPIF Bit of SPI Status Register Register ...................... .................................. ....................... ............. .. 106 Figure 27: Fast Read Mode Mode to Setup New Page Value........... Value....................... ........................ ....................... ....................... ........................ .......................106 ...........106 Figure 28: Fast Read to Read the Register Register ....................... ................................... ........................ ....................... ....................... ........................ ....................... ................. ...... 107 Figure 29: Normal Normal Write Operation Operation ....................... .................................. ....................... ........................ ........................ ....................... ....................... ....................... ................... ........108 108 Figure 30: Normal Normal Read Mode to Check the SPIF Bit of SPI Status Register Register ...................... .................................. ....................... ............. .. 109 Figure 31: Normal Normal Write to Setup the Register Page Value ........................ ................................... ....................... ........................ ....................... ............... .... 109 Figure 32: Normal Normal Write to Write the Register Register Address Followed Followed by Written Written Data........... Data....................... ........................ ................. ..... 109 Figure 33: Serial EEPROM EEPROM Connection Connection............ ........................ ....................... ....................... ........................ ....................... ....................... ........................ .......................110 ...........110 Figure 34: EEPROM EEPROM Programming Programming Example............ Example....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 111 Figure 35: PseudoPHY PseudoPHY MII Register Definitions Definitions........... ...................... ....................... ........................ ....................... ....................... ........................ .......................113 ...........113

Broadcom® April 6, 2016 • 53128-DS07-R

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BCM53128 Data Sheet

List of Figures

Figure 36: PseudoPHY PseudoPHY MII Register 16: Register Set Access Control Bit Definition Definition............ ........................ ....................... ............. .. 114 Figure 37: PseudoPHY MII Register 17: Register Set Read/Write Read/Write Control Bit Definition ....................... .............................. .......114 114 Figure 38: PseudoPHY PseudoPHY MII Register 18: Register Access Status Bit Definition ....................... ................................... .....................115 .........115 Figure 39: PseudoPHY PseudoPHY MII Register 24: Access Register Bit Definition............ Definition....................... ....................... ........................ .....................115 .........115 Figure 40: PseudoPHY PseudoPHY MII Register 25: Access Register Bit Definition............ Definition....................... ....................... ........................ .....................115 .........115 Figure 41: PseudoPHY PseudoPHY MII Register 26: Access Register Bit Definition............ Definition....................... ....................... ........................ .....................116 .........116 Figure 42: PseudoPHY PseudoPHY MII Register 27: Access Register Bit Definition............ Definition....................... ....................... ........................ .....................116 .........116 Figure 43: Read Access to the Register Set Using the PseudoPHY (PHYAD = 11110) MDC/MDIO MDC/MDIO Path...117 Path ...117 Figure 44: Write Access Access to the Register Register Set Using the PseudoPHY PseudoPHY (PHYAD = 11110) MDC/MDI MDC/MDIO O Path ...118 Path ...118 Figure 45: LED Interface Register Structure Diagram ....................... ................................... ....................... ....................... ........................ ....................... ............. .. 121 Figure 46: LED Interface Interface Block Diagram Diagram ........................ ................................... ....................... ........................ ....................... ....................... ........................ .....................122 .........122 Figure 47: Dual LED Usage Usage Example........... Example ....................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 122 Figure 48: LED Circuit for Dual Input Configurat Configuration/LE ion/LED D Output Pins........... Pins ...................... ....................... ........................ ....................... ............. .. 123 Figure 49: Reset and Clock Clock Timing........... Timing....................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........299 299 Figure 50: 50: MII Input Input............ ....................... ....................... ........................ ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........300 300 Figure 51: MII Output Output Timing ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 300 Figure 52: 52: TMII Input Input............ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 301 Figure 53: TMII Output Output Timing.......... Timing ...................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 302 Figure 54: Reverse Reverse MII Input Timing Timing........... ....................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 302 Figure 55: Reverse Reverse MII Output Timing Timing ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 303 Figure 56: RGMII RGMII Output Timing (Normal (Normal Mode)............ Mode) ....................... ....................... ........................ ....................... ....................... ........................ .....................304 .........304 Figure 57: RGMII RGMII Output Timing (Delayed (Delayed Mode) ....................... ................................... ........................ ....................... ....................... ........................ ................... .......305 305 Figure 58: RGMII RGMII Input Timing (Normal (Normal Mode)........... Mode)...................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 306 Figure 59: RGMII RGMII Input Timing (Delayed Mode) Mode) ...................... .................................. ........................ ....................... ....................... ........................ .......................307 ...........307 Figure 60: GMII Output Output Timings Timings...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 308 Figure 61: GMII Input Input Timings ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 308 Figure 62: MDC/MDIO MDC/MDIO Timing Timing (Slave Mode) ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............... .... 309 Figure 63: Serial LED Interface Interface Timing Timing ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 310 Figure 64: 64: SPI Timings, Timings, SS SS Asserted During SCK High ...................... .................................. ....................... ....................... ........................ .......................311 ...........311 Figure 65: 65: EEPROM EEPROM Timing ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 312 Figure 66: 66: Serial Flash Flash Timing.......... Timing ...................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 313 Figure 67: BCM53128 Mechanical Specifications ....................... ................................... ........................ ....................... ....................... ........................ ................... .......316 316


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BCM53128 Data Sheet

List of Tables

List of Tables Table 1: TC Decision Tree Summary.......................... Summary..................................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 36 Table 2: Reasons to Forward a Packet to the CPU ....................... ................................... ....................... ....................... ........................ ........................ ................... ....... 38 Table 3: Bucket Bit Rate ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 47 Table 4: DoS Attacks Detected by BCM53128 ...................... .................................. ........................ ....................... ....................... ........................ ....................... ............... .... 51 Table 5: Cable Diagnostic Output ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 56 Table 6: Unicast Forward Field Definitions ...................... .................................. ........................ ........................ ....................... ....................... ....................... ..................... .......... 60 Table 7: Address Table Entry for Unicast Address ...................... .................................. ........................ ....................... ....................... ........................ ..................... ......... 60 Table 8: Multicast Forward Field Definitions ...................... .................................. ........................ ....................... ....................... ........................ ....................... ................... ........ 61 Table 9: Address Table Entry for Multicast Address ...................... .................................. ....................... ....................... ........................ ........................ ................... ....... 61 Table 10: Behavior for Reserved Multicast Addresses ...................... .................................. ....................... ....................... ........................ ....................... ............... .... 62 Table 11: Flow Control Modes ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 70 Table 12: 1000BASE-T External Loopback with External Loopback Plug ...................... .................................. ........................ ..................... ......... 77 Table 13: 1000BASE-T External Loopback Without External Loopback Plug ...................... .................................. ....................... ............... .... 77 Table 14: 100BASE-TX External Loopback with External Loopback Plug ........................... ....................................... ....................... ............... .... 78 Table 15: 100BASE-TX External Loopback Without External Loopback Plug.............................. Plug.......................................... ................... ....... 78 Table 16: 10BASE-T External Loopback with External Loopback Plug ...................... .................................. ........................ ....................... ............. .. 78 Table 17: 10BASE-T External Loopback Without External Loopback Plug ...................... .................................. ........................ ................... ....... 78 Table 18: Egress Broadcom Tag Format (IMP to CPU) ............................ ....................................... ....................... ........................ ........................ ................... ....... 81 Table 19: Ingress BRCM Tag (CPU to IMP) ...................... .................................. ........................ ....................... ....................... ........................ ........................ ................... ....... 82 Table 20: Receive Only Counter (19) Description of Counter............................... Counter........................................... ........................ ........................ ................... ....... 83 Table 21: Transmit Counters Only (19) Description of Counter........... Counter ....................... ....................... ....................... ........................ ....................... ............. .. 85 Table 22: Transmit or Receive Counters (10) Description of Counter ...................... .................................. ........................ ....................... ............... .... 86 Table 23: Directly Supported MIB Counters ................................ ............................................ ........................ ....................... ....................... ........................ ..................... ......... 86 Table 24: Indirectly Supported MIB Counters ...................... .................................. ........................ ....................... ....................... ........................ ....................... ................. ...... 88 Table 25: BCM53128 Supported MIB Extensions ................................. ............................................. ....................... ....................... ........................ ....................... ........... 89 Table 26: EEPROM_TYPE[1:0] Settings ........................ ................................... ....................... ........................ ....................... ....................... ........................ ..................... ......... 110 Table 27: EEPROM Header Format ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 111 Table 28: EEPROM Contents ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 111 Table 29: MII Management Frame Format ...................... .................................. ........................ ........................ ....................... ....................... ........................ ................... ....... 119 Table 30: LED Output Pins Per Port ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 120 Table 31: I/O Signal Type Definitions ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 124 Table 32: Signal Type Definitions ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ..................... ......... 125 Table 33: Global Page Register Map............ Map ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 142 Table 34: Control Registers (Page 00h) ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ........... 144 Table 35: Port Traffic Control Register Address Summary ........................ ................................... ....................... ........................ ........................ ................. ..... 146


Page 20


BCM53128 Data Sheet

List of Tables

Table 36: Port Control Register (Page 00h: Address 00h–07h) ................................. ............................................. ........................ ....................... ........... 146 Table 37: IMP Port Control Register (Page 00h: Address 08h) ....................... .................................. ....................... ........................ ....................... ........... 147 Table 38: Switch Mode Register (Page 00h: Address 0Bh)........... 0Bh) ....................... ....................... ....................... ........................ ........................ ................. ..... 148 Table 39: IMP Port State Override Register (Page 00h: Address 0Eh) ...................... .................................. ........................ ....................... ........... 148 Table 40: LED Control Register Address Summary .............................. .......................................... ....................... ....................... ........................ ..................... ......... 149 Table 41: LED Refresh Register (Page 00h: Address 0Fh) ....................... .................................. ....................... ........................ ........................ ................. ..... 149 Table 42: LED Function 0 Control Register (Page 00h: Address 10h–11h) ....................... ................................... ....................... ............... .... 150 Table 43: LED Function 1 Control Register (Page 00h: Address 12h–13h) ....................... ................................... ....................... ............... .... 151 Table 44: LED Function Map Register (Page 00h: Address 14h–15h) ....................... ................................... ........................ ....................... ........... 151 Table 45: LED Enable Map Register (Page 00h: Address 16h–17h) ......................... ..................................... ........................ ....................... ........... 152 Table 46: LED Mode Map 0 Register (Page 00h: Address 18h–19h)............................. 18h–19h)......................................... ........................ ................... ....... 152 Table 47: LED Function Map 1 Control Register (Page 00h: Address 1Ah–1Bh) .......................... ..................................... ............... .... 152 Table 48: LED Control Register (Page 00h: Address 1Ch) ................................. ............................................ ....................... ........................ ................... ....... 153 Table 49: PHY LED Control Register (Page 00h: Address 1Dh) ....................... .................................. ....................... ........................ ..................... ......... 153 Table 50: Port Forward Control Register (Page 00h: Address 21h) ....................... ................................... ........................ ....................... ............... .... 154 Table 51: Protected Port Selection Register (Page 00h: Address 24h–25h) ...................... .................................. ....................... ............... .... 155 Table 52: WAN Port Select Register (Page 00h: Address 26h–27h)............................ 26h–27h)........................................ ........................ ..................... ......... 155 Table 53: Pause Capability Register (Page 00h: Address 28h–2Bh) ....................... ................................... ........................ ....................... ............. .. 155 Table 54: Reserved Multicast Control Register (Page 00h: Address 2Fh) ....................... ................................... ........................ ................. ..... 156 Table 55: Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h–33h).............................. 32h–33h)..............................157 157 Table 56: Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h)........................ 34h–35h)............................ ....157 157 Table 57: MLF IMPC Forward Map Register (Page 00h: Address 36h–37h) ....................... ................................... ....................... ............. .. 158 Table 58: Pause Pass Through for RX Register (Page 00h: Address 38h–39h) ...................... .................................. ..................... ......... 158 Table 59: Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh) ............................. ........................................ ............. .. 158 Table 60: Disable Learning Register (Page 00h: Address 3Ch–3Dh) .............................. .......................................... ........................ ................. ..... 159 Table 61: Software Learning Control Register (Page 00h: Address 3Eh–3Fh) ...................... .................................. ....................... ........... 159 Table 62: Port State Override Register Address Summary ....................... .................................. ....................... ........................ ........................ ................. ..... 160 Table 63: Port State Override Register (Page 00h: Address 58h–5Fh) ...................... .................................. ........................ ....................... ........... 160 Table 64: IMP RGMII Control Register (Page 00h: Address 60h) ....................... .................................. ....................... ........................ ................... ....... 161 Table 65: MDIO IMP PORT Address Register (Page 00h: Address 78h) ....................... ................................... ........................ ................... ....... 161 Table 66: Software Reset Control Register (Page 00h: Address 79h) ............................. ......................................... ........................ ................. ..... 161 Table 67: Pause Frame Detection Control Register (Page 00h: Address 80h) ...................... .................................. ....................... ........... 162 Table 68: Fast-Aging Control Register (Page 00h: Address 88h) ........................ ................................... ....................... ........................ ................... ....... 162 Table 69: Fast-Aging Port Control Register (Page 00h: Address 89h) ....................... ................................... ........................ ....................... ........... 162 Table 70: Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh) ....................... ................................... ....................... ............... .... 163 Table 71: CPU Data 0 Share Register (Page 00h: Address B0h–B7h) ...................... .................................. ........................ ....................... ........... 163 Table 72: CPU Data 1 Share Register (Page 00h: Address B8h–BFh) ...................... .................................. ........................ ....................... ........... 163


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BCM53128 Data Sheet

List of Tables

Table 73: Status Registers (Page 01h) ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 164 Table 74: Link Status Summary Register (Page 01h: Address 00h–01h) ................................ ............................................ ..................... ......... 164 Table 75: Link Status Change Register (Page 01h: Address 02h–03h) ....................... ................................... ........................ ..................... ......... 165 Table 76: Port Speed Summary Register (Page 01h: Address 04h–07h) ...................... .................................. ........................ ................... ....... 165 Table 77: Duplex Status Summary Register (Page 01h: Address 08h–09h) ...................... .................................. ....................... ............... .... 166 Table 78: PAUSE Status Summary Register (Page 01h: Address 0Ah–0Dh) ...................... .................................. ....................... ............. .. 166 Table 79: Source Address Change Register (Page 01h: Address 0Eh–0Fh) ....................... ................................... ....................... ............. .. 167 Table 80: Last Source Address Register Address Summary........................... Summary...................................... ....................... ........................ ....................... ........... 167 Table 81: Last Source Address (Page 01h: Address 10h–45h) ....................... .................................. ....................... ........................ ....................... ........... 167 Table 82: Aging/Mirroring Registers (Page 02h)............................ 02h)........................................ ....................... ....................... ........................ ....................... ................. ...... 168 Table 83: Global Management Configuration Register (Page 02h: Address 00h).............................. 00h)......................................... ........... 169 Table 84: IMP Port ID Register (Page 02h: Address 01h) ....................... ................................... ....................... ....................... ........................ ................... ....... 169 Table 85: Broadcom Tag Control Register (Page 02h: Address 03h) ................................ ............................................ ....................... ............... .... 170 Table 86: RMON MIB Steering Register (Page 02h: Address 04h–05h) ...................... .................................. ........................ ..................... ......... 170 Table 87: Aging Time Control Register (Page 02h: Address 06h–09h) ...................... .................................. ........................ ....................... ........... 170 Table 88: Mirror Capture Control Register (Page 02h: Address 10h–11h) ....................... ................................... ........................ ................. ..... 171 Table 89: Ingress Mirror Control Register (Page 02h: Address 12h–13h) ...................... .................................. ........................ ................... ....... 171 Table 90: Ingress Mirror Divider Register (Page 02h: Address 14h–15h) ...................... .................................. ........................ ................... ....... 172 Table 91: Ingress Mirror MAC Address Register (Page 02h: Address 16h–1Bh) ....................... ................................... ................... ....... 172 Table 92: Egress Mirror Control Register (Page 02h: Address 1Ch–1Dh) 1Ch–1Dh) ....................... ................................... ........................ ................. ..... 173 Table 93: Egress Mirror Divider Register (Page 02h: Address 1Eh–1Fh) ...................... .................................. ........................ ................... ....... 174 Table 94: Egress Mirror MAC Address Register (Page 02h: Address 20h–25h) ...................... .................................. ..................... ......... 174 Table 95: Device ID Register (Page 02h: Address 30h–33h) ........................ ................................... ....................... ........................ ....................... ............. .. 174 Table 96: Egress Mirror MAC Address Register (Page 02h: Address 40h) ...................... .................................. ........................ ................. ..... 174 Table 97: High-Level Protocol Control Register (Page 02h: Address 50h–53h) ....................... ................................... ..................... ......... 175 Table 98: Page 03h: Interrupt Control Register ....................... ................................... ........................ ....................... ....................... ........................ ....................... ........... 177 Table 99: Interrupt Status Register (Page 03h: Address 00h) ....................... .................................. ....................... ........................ ....................... ............. .. 177 Table 100: Interrupt Enable Register (Page 03h: Address 08h) ........................ ................................... ....................... ........................ ..................... ......... 177 Table 101: IMP Sleep Timer Register (Page 03h: Address 10h) ....................... .................................. ....................... ........................ ..................... ......... 178 Table 102: Sleep Status Register (Page 03h: Address 18h) ....................... .................................. ....................... ........................ ....................... ............... .... 178 Table 103: External CPU Interrupt Trigger Register (Page 03h: Address 20h) ...................... .................................. ....................... ........... 178 Table 104: ARL Control Registers (Page 04h) ................................ ............................................ ....................... ....................... ........................ ....................... ............... .... 179 Table 105: Global ARL Configuration Register (Page 04h: Address 00h) ...................... .................................. ........................ ................... ....... 180 Table 106: BPDU Multicast Address Register (Page 04h: Address 04h–09h) ....................... ................................... ....................... ........... 180 Table 107: Multiport Control Register (Page 04h: Address 0Eh–0Fh)................................ 0Eh–0Fh)............................................ ....................... ............... .... 181 Table 108: Multiport Address Register Address Summary ........................ ................................... ....................... ........................ ........................ ................. ..... 182 Table 109: Multiport Address Register (Page 04h: Address 10h–17h, 20h–27h, 30h–37h, 30h–37h, 40h–47h, 50h–57h,


Page 22


BCM53128 Data Sheet

List of Tables

60h–67h)...................... 60h–67h).................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... .................... ........ 182 Table 110: Multiport Vector Register Address Summary........... Summary ....................... ........................ ....................... ....................... ........................ ..................... ......... 183 Table 111: Multiport Vector Register (Page 04h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h–4Bh, 58h–5Bh, 68h–6Bh) ....................... ................................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 183 Table 112: ARL/VTBL Access Registers (Page 05h) .............................. .......................................... ....................... ....................... ........................ ................... ....... 184 Table 113: ARL Table Read/Write Control Register (Page 05h: Address 00h) ...................... .................................. ....................... ........... 185 Table 114: MAC Address Index Register (Page 05h: Address 02h–07h)............ 02h–07h) ....................... ....................... ........................ ................... ....... 185 Table 115: VLAN ID Index Register (Page 05h: Address 08h–09h) ....................... ................................... ........................ ....................... ............... .... 186 Table 116: ARL Table MAC/VID Entry N (N=0-3) Register Address Summary ...................... .................................. ....................... ........... 186 Table 117: ARL Table MAC/VID Entry N (N=0-3) Register Register (Page 05h: Address 10h–17h, 20h–27h, 30h–37h, 40h–47h)...................... 40h–47h).................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... .................... ........ 186 Table 118: ARL Table Data Entry N (N=0-3) Register Address Summary ....................... ................................... ........................ ................. ..... 187 Table 119: ARL Table Data Entry N (N=0-3) (N=0-3) Register (Page 05h: Address Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h– 4Bh) ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 187 Table 120: ARL Table Search Control Register (Page 05h: Address 50h)............................. 50h)......................................... ....................... ........... 188 Table 121: ARL Search Address Register (Page 05h: Address 51h–52h) ....................... ................................... ........................ ................. ..... 189 Table 122: ARL Table Search MAC/VID Result N (N=0-1) Register Address Summary............................. Summary............................... .. 189 Table 123: ARL Table Search MAC/VID MAC/VID Result N (N=0-1) (N=0-1) Register (Page 05h: Address Address 60h–67h, 70h–77h)...................... 70h–77h).................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ....................... .................... ........ 189 Table 124: ARL Table Search Data Result N (N=0-1) Register Address Summary Summary ....................... .................................. ............... .... 190 Table 125: ARL Table Search Data Result N (N=0-1) Register Register (Page 05h: Address 68h–6Bh, 68h–6Bh, 78h–7Bh)...190 78h–7Bh)...190 Table 126: VLAN Table Read/Write/Clear Control Register (Page 05h: Address Address 80h) ........................ ................................. ......... 191 Table 127: VLAN Table Address Index Register (Page 05h: Address 81h–82h) ....................... ................................... ................... ....... 192 Table 128: VLAN Table Entry Register (Page 05h: Address 83h–86h) ...................... .................................. ........................ ....................... ........... 192 Table 129: 10/100/1000 PHY Page Summary..................... Summary................................. ........................ ....................... ....................... ........................ ....................... ............... .... 194 Table 130: Register Map (Page 10h–17h)............ 10h–17h) ....................... ....................... ........................ ........................ ....................... ....................... ........................ ................... ....... 194 Table 131: MII Control Register (Page 10h–17h: Address 00h–01h) ....................... ................................... ........................ ....................... ............. .. 196 Table 132: MII Status Register (Page 10h–17h: Address 02h–03h) ............................ ........................................ ........................ ..................... ......... 197 Table 133: PHY Identifier Register MSB (Page 10h–17h: Address 04–07h) ...................... .................................. ....................... ............... .... 198 Table 134: PHY Identifier Register LSB (Page 10h–17h: Address 06h–07h) ....................... ................................... ....................... ............. .. 198 Table 135: Auto-Negotiation Advertisement Register (Page 10h–17h: Address 08h–09h)........................... 08h–09h)...........................199 199 Table 136: Auto-Negotiation Link Partner Ability Register Register (Page 10h–17h: Address 0Ah–0Bh) ................... ...................200 200 Table 137: Auto-Negotiation Expansion Register (Page 10h–17h: Address 0Ch–0Dh)............................ 0Ch–0Dh)................................ .... 201 Table 138: Next Page Transmit Register (Page 10h–17h: Address 0Eh–0Fh) ...................... .................................. ....................... ........... 202 Table 139: Link Partner Received Next Page Register (Page 10h–17h: Address 10h–11h) ................. ........................ .......203 203 Table 140: 1000BASE-T Control Register (Page 10h–17h: Address 12h–13h) ....................... ................................... ..................... ......... 204 Table 141: 1000BASE-T Status Register (Page 10h–17h: Address 14h–15h) ................................ ........................................... ............. .. 205


Page 23


BCM53128 Data Sheet

List of Tables

Table 142: IEEE Extended Status Register (Page 10h–17h: Address 1Eh–1Fh) .................................. ......................................... ....... 206 Table 143: PHY Extended Control Register (Page 10h–17h: Address 20h–21h) ................................ ......................................... ......... 207 Table 144: PHY Extended Status Register (Page 10h–17h: Address 22h–23h)................................ 22h–23h)........................................... ........... 208 Table 145: Receive Error Counter Register (Page 10h–17h: Address 24h–25h) ....................... ................................... ................... ....... 209 Table 146: False Carrier Sense Counter Register (Page 10h–17h: Address 26h–27h).............................. 26h–27h)................................ .. 209 Table 147: 10BASE-T/100BASE-TX/1000BASE-T Transmit Error Code Counter Register (Address (Address 13h) ..210 ..210 Table 148: Receiver NOT_OK Counter Register (Page 10h–17h: Address Address 28h–29h) ....................... .................................. ........... 210 Table 149: CRC Counter Register (Page 10h–17h: Address 28h–29h) ....................... ................................... ........................ ..................... ......... 211 Table 150: Expansion Register Access Register (Page 10h–17h: Address 2Eh–2Fh) ........................ ................................. .........211 211 Table 151: Expansion Register Select Values V alues ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............. .. 212 Table 152: Auxiliary Control Shadow Values Access Register Register (Page 10h–17h: Address 30h)..................... 30h).....................212 212 Table 153: Reading Register 30h ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ..................... ......... 212 Table 154: Writing Register 30h ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 213 Table 155: Auxiliary Control Register (Page 10h–17h: 10h–17h: Address 30h, Shadow Value 000) ....................... ........................... ....213 213 Table 156: 10BASE-T Register (Page 10h–17h: Address 30h, Shadow Value 001) ........................... .................................... .........214 214 Table 157: Power/MII Control Register (Page (Page 10h–17h: Address 30h, Shadow Value 010)......................... 010).........................215 215 Table 158: Miscellaneous Test Register (Page 10h–17h: Address 30h, Shadow Value 100)....................... 100).......................216 216 Table 159: Miscellaneous Control Register (Page 10h–17h: Address 30h, Shadow Value 111) .................. ..................217 217 Table 160: Auxiliary Status Summary Register (Page 10h–17h: Address 32h–33h) ................................ .................................... .... 218 Table 161: Interrupt Status Register (Page 10h–17h: Address 34h–35h) ...................... .................................. ........................ ................... ....... 219 Table 162: Interrupt Mask Register (Page 10h–17h: Address 36h)................................ 36h)............................................ ........................ ................... ....... 220 Table 163: 10BASE-T/100BASE-TX/1000BASE-T Register 38h Shadow Values ....................... ................................... ................. .....221 221 Table 164: Spare Control 2 Register (Page 10h–17h: Address 38h, Shadow Value 00100) ...................... ........................ ..221 221 Table 165: Auto Power-Down Register (Page 10h–17h: Address 38h, Shadow Value 01010) ............... .................... .....222 222 Table 166: LED Selector 2 Register (Page (Page 10h–17h: Address 38h, Shadow Value 01110) ....................... ......................... ..223 223 Table 167: Mode Control Register (Page 10h–17h: Address 38h, Shadow Value 11111)............................ 11111)............................225 225 Table 168: Master/Slave Seed Register (Page (Page 10h–17h: Address 3Ah–3Bh) Bit 15 = 0 ....................... .............................. .......226 226 Table 169: HCD Status Register (Page 10h–17h: Address 3Ah–3Bh) Bit 15 = 1............................. 1........................................ ............. .. 227 Table 170: Test Register 1 (Page 10h–17h: Address 3C–3Dh) ............................. ......................................... ........................ ....................... ............... .... 228 Table 171: Expansion Register 00h: Receive/Transmit Packet Counter ...................... .................................. ........................ ..................... ......... 229 Table 172: Expansion Register 01h: Expansion Interrupt Status ........................ ................................... ....................... ........................ ................... ....... 229 Table 173: Expansion Register 45h: Transmit CRC ...................... .................................. ....................... ....................... ........................ ........................ ................. ..... 230 Table 174: Port MIB Registers Page Summary ....................... ................................... ........................ ....................... ....................... ........................ ....................... ........... 230 Table 175: Page 20h–28h Port MIB Registers ............................ ........................................ ........................ ....................... ....................... ........................ ................... ....... 230 Table 176: Page 30h QoS Registers ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 235 Table 177: QoS Global Control Register (Page 30h: Address 00h) ......................... ..................................... ........................ ....................... ............. .. 236 Table 178: QoS.1P Enable Register (Page 30h: Address 04h–05h) ...................... .................................. ........................ ....................... ............... .... 236


Page 24


BCM53128 Data Sheet

List of Tables

Table 179: QoS DiffServ Enable Register (Page 30h: Address 06h–07h) ......................... ..................................... ....................... ............... .... 237 Table 180: Port N (N=0-7,8) PCP_To_TC Register Address Summary ....................... ................................... ........................ ..................... ......... 237 Table 181: Port N (N=0-7,8) PCP_To_TC Register (Page 30h: Address 10h–33h) ....................... .................................. ............... .... 237 Table 182: DiffServ Priority Map 0 Register (Page 30h: Address 40h–45h) ....................... ................................... ....................... ............... .... 238 Table 183: DiffServ Priority Map 1 Register (Page 30h: Address 46h–4Bh) ...................... .................................. ....................... ............... .... 239 Table 184: DiffServ Priority Map 2 Register (Page 30h: Address 4Ch–51h) ...................... .................................. ....................... ............... .... 239 Table 185: DiffServ Priority Map 3 Register (Page 30h: Address 52h–57h) ....................... ................................... ....................... ............... .... 240 Table 186: TC_To_COS Mapping Register (Page 30h: Address 62h–63h) ....................... ................................... ....................... ............... .... 241 Table 187: CPU_To_COS Map Register (Page 30h: Address 64h–67h) ....................... ................................... ........................ ................... ....... 242 Table 188: TX Queue Control Register (Page 30h: Address 80h)............................ 80h)........................................ ........................ ....................... ............. .. 243 Table 189: TX Queue Weight Register Queue[0:3] Queue[0:3] (Page 30h: Address 81h–84h) ....................... .................................. ............... .... 243 Table 190: COS4 Service Weight Register (Page 30h: Address 85h–86h) ...................... .................................. ........................ ................. ..... 244 Table 191: Page 31h VLAN Registers ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 245 Table 192: Port-Based VLAN Control Register Address Summary ...................... .................................. ........................ ........................ ................. ..... 245 Table 193: Port VLAN Control Register (Page 31h: Address 00h–11h) ....................... ................................... ........................ ..................... ......... 245 Table 194: Page 32h Trunking Registers .............................. .......................................... ........................ ....................... ....................... ........................ ....................... ............. .. 246 Table 195: MAC Trunk Control Register (Page 32h: Address 00h) ...................... .................................. ........................ ........................ ................. ..... 246 Table 196: Trunk Group 0 Register (Page 32h: Address 10h–11h) ......................... ..................................... ........................ ....................... ............. .. 247 Table 197: Trunk Group 1 Register (Page 32h: Address 12h–13h) ......................... ..................................... ........................ ....................... ............. .. 247 Table 198: Page 34h IEEE 802.1Q VLAN V LAN Registers ....................... ................................... ....................... ....................... ........................ ....................... ............... .... 248 Table 199: Global IEEE 802.1Q Register (Pages 34h: Address 00h) .......................... ...................................... ........................ ..................... ......... 248 Table 200: Global VLAN Control 1 Register (Page 34h: Address 01h) ...................... .................................. ........................ ....................... ........... 250 Table 201: Global VLAN Control 2 Register (Page 34h: Address 02h) ...................... .................................. ........................ ....................... ........... 251 Table 202: Global VLAN Control 3 Register (Page 34h: Address 03h–04h) ...................... .................................. ....................... ............... .... 251 Table 203: Global VLAN Control 4 Register (Page 34h: Address 05h) ...................... .................................. ........................ ....................... ........... 252 Table 204: Global VLAN Control 5 Register (Page 34h: Address 06h) ...................... .................................. ........................ ....................... ........... 253 Table 205: VLAN Multiport Address Control Register (Page 34h: Address 0Ah–0Bh).............................. 0Ah–0Bh).................................. .... 254 Table 206: Default IEEE 802.1Q Tag Register Address Summary .............................. .......................................... ........................ ..................... ......... 255 Table 207: Default IEEE 802.1Q Tag Register (Page 34h: Address 10h–21h) ...................... .................................. ....................... ........... 255 Table 208: Double Tagging TPID Register (Page 34h: Address 30h–31h) ...................... .................................. ........................ ................. ..... 256 Table 209: ISP Port Selection Portmap Register (Page 34h: Address 32h–33h)................................. 32h–33h).......................................... ......... 256 Table 210: DOS Prevent Register ........................ ................................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........ 257 Table 211: DOS Control Register (Page 36h: Address 00h–03h) ....................... .................................. ....................... ........................ ................... ....... 257 Table 212: Minimum TCP Header Size Register (Page 36h: Address 04h) ....................... ................................... ....................... ............... .... 259 Table 213: Maximum ICMPv4 Size Register (Page 36h: Address 08h-0Bh) ...................... .................................. ....................... ............... .... 259 Table 214: Maximum ICMPv6 Size Register (Page 36h: Address 0Ch-0Fh) ....................... ................................... ....................... ............. .. 259 Table 215: DOS Disable Learn Register (Page 36h: Address 08h-0Bh) ...................... .................................. ........................ ..................... ......... 259


Page 25


BCM53128 Data Sheet

List of Tables

Table 216: Page 40h Jumbo Frame Control Register ................................. ............................................ ....................... ........................ ....................... ............... .... 260 Table 217: Jumbo Frame Port Mask Registers (Page 40h: Address 01h–04h) ................................. ............................................ ........... 260 Table 218: Standard Max Frame Size Registers (Page 40h: Address 05h–06h) ....................... ................................... ................... ....... 261 Table 219: Broadcast Storm Suppression Register (Page 41h) ........................ ................................... ....................... ........................ ..................... ......... 262 Table 220: Ingress Rate Control Control Configuration Register (Page 41h: Address 00h–03h) ....................... .............................. ....... 262 Table 221: Port Rate Control Register Address Summary ........................ ................................... ....................... ........................ ........................ ................. ..... 264 Table 222: Port Rate Control Register (Page 41h: Address 10h–33h) ....................... ................................... ........................ ....................... ........... 264 Table 223: Port Egress Rate Control Configuration Register Address Summary............................... Summary.......................................... ........... 266 Table 224: Port Egress Rate Control Configuration Registers Registers (Page 41h: Address 80h–91h) ..................... .....................266 266 Table 225: IMP Port Egress Rate Control Configuration Register Register Address Summary ....................... .................................. ........... 267 Table 226: IMP Port Egress Rate Control Configuration Registers Registers (Page 41h: Address C0h) ..................... .....................267 267 Table 227: Using Rate_Index to Configure Different Egress Rates for IMP in pps ................................ ....................................... ....... 268 Table 228: Broadcast Storm Suppression Register (Page 42h) ........................ ................................... ....................... ........................ ..................... ......... 268 Table 229: EAP Global Control Registers (Page 42h: Address 00h)............................ 00h)........................................ ........................ ..................... ......... 269 Table 230: EAP Multiport Address Control Register (Page 42h: Address 01h) ...................... .................................. ....................... ........... 269 Table 231: EAP Destination IP Registers 0 (Page 42h: Address 02h–09h) ....................... ................................... ....................... ............... .... 270 Table 232: EAP Destination IP Registers 1 (Page 42h: Address 0Ah–12h) ....................... ................................... ....................... ............... .... 270 Table 233: Port EAP Configuration Register Address Summary ....................... .................................. ....................... ........................ ..................... ......... 271 Table 234: Port EAP Configuration Registers (Page 42h: Address 20h–47h) ...................... .................................. ....................... ............. .. 271 Table 235: Broadcast Storm Suppression Register (Page 43h) ........................ ................................... ....................... ........................ ..................... ......... 272 Table 236: MSPT Control Registers (Page 43h: Address 00h–01h) ...................... .................................. ........................ ....................... ............... .... 272 Table 237: MSPT Aging Control Registers (Page 43h: Address 02h–05h) ...................... .................................. ........................ ................. ..... 272 Table 238: MSPT Table Register Address Summary ...................... .................................. ....................... ....................... ........................ ....................... ............... .... 273 Table 239: MSPT Table Registers (Page 43h: Address 10h–2Fh)............ 10h–2Fh) ....................... ....................... ........................ ........................ ................. ..... 273 Table 240: SPT Multiport Address Bypass Control Control Register (Page 43h: Address 50h–51h) ...................... ........................ ..274 274 Table 241: MIB Snapshot Control Register ................................. ............................................. ........................ ....................... ....................... ........................ ................... ....... 275 Table 242: MIB Snapshot Control Register (Page 70h: Address 00h) ................................. ............................................. ....................... ............. .. 275 Table 243: Port Snapshot MIB Control Register........... Register ...................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 275 Table 244: Loop Detection Control Register (Page 72h) ....................... ................................... ....................... ....................... ........................ ..................... ......... 276 Table 245: Loop Detection Control Registers (Page 72h: Address 00h–01h) ...................... .................................. ....................... ............. .. 276 Table 246: Discovery Frame Timer Control Registers (Page 72h: Address 02h) ....................... ................................... ................... ....... 276 Table 247: LED Warning Port Map Registers (Page 72h: Address 03h–04h) ...................... .................................. ....................... ............. .. 277 Table 248: Module ID 0 Registers (Page 72h: Address 05h–0Ah) ....................... ................................... ........................ ........................ ................. ..... 277 Table 249: Module ID 1 Registers (Page 72h: Address 0Bh–10h) ....................... ................................... ........................ ........................ ................. ..... 278 Table 250: Loop Detect Source Address Registers (Page 72h: Address 11h–16h)............................... 11h–16h)...................................... ....... 278 Table 251: IMP Port External PHY MII Registers Page Summary ............................... ........................................... ........................ ..................... ......... 278 Table 252: BroadSync HD Register...................... Register................................. ....................... ........................ ........................ ....................... ....................... ....................... ................... ........ 279


Page 26


BCM53128 Data Sheet

List of Tables

Table 253: BroadSync HD Enable Control Register (Page 90h: Address 00h–01h) ........................ ................................... ............. .. 280 Table 254: BroadSync HD Time Stamp Report Control Register (Page (Page 90h: Address 02h) ....................... ......................... .. 280 Table 255: BroadSync HD PCP Value Control Register (Page 90h: A ddress 03h).............................. 03h)....................................... ......... 280 Table 256: BroadSync HD Max Packet Size Register (Page 90h: Address 04h) ....................... ................................... ................... ....... 281 Table 257: BroadSync HD Time Base Register (Page 90h: Address 10h–13h)............................. 10h–13h)........................................ ............... .... 281 Table 258: BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17h)....................... 14h–17h)......................... ..281 281 Table 259: BroadSync BroadSync HD Slot Number and Tick Counter Counter Register (Page 90h: Address 18h–1Bh) ........ ............ ....282 282 Table 260: BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh).............................. 1Ch–1Fh)................................... ..... 282 Table 261: BroadSync HD Class 5 Bandwidth Control Register Address Summary Summary ........................ ................................... ............. .. 283 Table 262: BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h–31h, 32h–33h, 34h– 35h, 36h–37h, 38h–39h)..................... 38h–39h)................................. ........................ ....................... ....................... ........................ ....................... ....................... .................... ........ 283 Table 263: BroadSync HD Class 4 Bandwidth Control Register Address Summary Summary ........................ ................................... ............. .. 283 Table 264: BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h–61h, 62h–63h, 64h– 65h, 66h–67h, 68h–69h)..................... 68h–69h)................................. ........................ ....................... ....................... ........................ ....................... ....................... .................... ........ 284 Table 265: BroadSync HD Egress Time Stamp Register Address Summary ....................... ................................... ....................... ............. .. 284 Table 266: BroadSync HD Egress Time Stamp Stamp Register (Page 90h: Address Address 90h–93h, 94h–97h, 98h–9Bh, 9Ch–9Fh, A0h–A3h, A4h–A7h) ...................... .................................. ........................ ........................ ....................... ....................... ........................ ................... ....... 284 Table 267: BroadSync HD Egress Time Stamp Status Register (Page 90h: Address D0h) .............. ......................... ...........284 284 Table 268: BroadSync HD Link Status Register (Page 90h: Address E0h–E1h) ........................ .................................... ................. ..... 285 Table 269: Traffic Remarking Register ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 286 Table 270: Traffic Remarking Control Register (Page 91h: Address 00h) ...................... .................................. ........................ ................... ....... 286 Table 271: Egress Non-BroadSync HD Packet TC to PCP Mapping Register Address Summary Summary ............... ...............287 287 Table 272: Egress Non-Broa Non-BroadSync dSync HD Packet TC to PCP Mapping Register Register (Page 91h: Address Address 10h–17h, 18h–1Fh, 20h–27h, 28h–2Fh, 30h–37h, 38h–3Fh, 50h-57h)....................................................... 287 Table 273: Page 92h: EEE Control Register ....................... ................................... ........................ ....................... ....................... ........................ ....................... ............... .... 288 Table 274: EEE Enable Control Register (Page 92h: A ddress 00h)............................... 00h)........................................... ........................ ................... ....... 288 Table 275: EEE LPI Assert Register (Page 92h: Address 02h) ....................... .................................. ....................... ........................ ....................... ........... 289 Table 276: EEE LPI Indicate Register (Page 92h: Address 04h) ......................... ..................................... ........................ ........................ ................. ..... 289 Table 277: EEE RX Idle Symbol Register (Page 92h: Address 06h)................................ 06h)............................................ ........................ ................. ..... 289 Table 278: EEE Pipeline Timer Register (Page 92h: Address 0Ch) ....................... ................................... ........................ ....................... ............... .... 290 Table 279: EEE Sleep Timer Gig Register (Page 92h: Address 10h) ................................ ............................................ ....................... ............... .... 290 Table 280: EEE Sleep Timer Gig Register (Page 92h: Address 10h) ................................ ............................................ ....................... ............... .... 290 Table 281: EEE Sleep Timer FE Register (Page 92h: Address 34h) ................................. ............................................. ....................... ............... .... 290 Table 282: EEE Sleep Timer FE Register (Page 92h: Address 34h) ................................. ............................................. ....................... ............... .... 291 Table 283: EEE Min LP Timer Gig Register (Page 92h: Address 58h) .............................. .......................................... ....................... ............... .... 291 Table 284: EEE Min LP Timer Gig Register (Page 92h: Address 58h) .............................. .......................................... ....................... ............... .... 291 Table 285: EEE Min LP Timer FE Register (Page 92h: Address 7Ch) ....................... ................................... ........................ ....................... ........... 291


Page 27


BCM53128 Data Sheet

List of Tables

Table 286: EEE Min LP Timer FE Register (Page 92h: Address 7Ch) ....................... ................................... ........................ ....................... ........... 292 Table 287: EEE Wake Timer Gig Register (Page 92h: Address A0h) ...................... .................................. ........................ ....................... ............. .. 292 Table 288: EEE Wake Timer Gig Register (Page 92h: Address A0h) ...................... .................................. ........................ ....................... ............. .. 292 Table 289: EEE Wake Timer FE Register (Page 92h: Address B2h) ....................... ................................... ........................ ....................... ............. .. 292 Table 290: EEE Wake Timer FE Register (Page 92h: Address B2h) ....................... ................................... ........................ ....................... ............. .. 293 Table 291: EEE GLB Congst TH Register (Page 92h: Address C4h) ............................ ........................................ ........................ ................... ....... 293 Table 292: EEE TXQ CONG TH Register (Page 92h: Address C6h) ....................... ................................... ........................ ....................... ............. .. 293 Table 293: EEE TXQ Cong TH Register (Page 92h: Address C6h) ....................... ................................... ........................ ....................... ............... .... 293 Table 294: Global Registers (Maps to All Pages) ....................... ................................... ........................ ....................... ....................... ........................ ................... ....... 295 Table 295: SPI Data I/O Register (Maps to All Registers, Address F0h–F7h) ................................. ............................................ ............. .. 295 Table 296: SPI Status Register (Maps to All Registers, Address FEh) .......................... ...................................... ........................ ................... ....... 295 Table 297: Page Register (Maps to All Registers, Address FFh) ........................ ................................... ....................... ........................ ................... ....... 296 Table 298: Absolute Maximum Ratings ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 297 Table 299: Recommended Operating Conditions ...................... .................................. ........................ ....................... ....................... ........................ ..................... ......... 297 Table 300: Electrical Characteristics............. Characteristics......................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 298 Table 301: Reset and Clock Timing ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 299 Table 302: MII Input Timing ...................... .................................. ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........ 300 Table 303: MII Output Timing ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 301 Table 304: TMII Input Timing ...................... .................................. ....................... ....................... ........................ ....................... ....................... ........................ ....................... ................. ...... 301 Table 305: TMII Output Timing ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 302 Table 306: Reverse MII Input Timing ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 302 Table 307: Reverse TMII Input Timing............................. Timing......................................... ........................ ........................ ....................... ....................... ....................... ................... ........ 303 Table 308: Reverse MII Output Timing ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 303 Table 309: Reverse TMII Output Timing Ti ming ....................... .................................. ....................... ........................ ....................... ....................... ........................ ....................... ........... 303 Table 310: RGMII Output Timing (Normal Mode) ...................... .................................. ........................ ....................... ....................... ........................ ..................... ......... 304 Table 311: RGMII Output Timing (Delayed Mode) .............................. .......................................... ....................... ....................... ........................ ....................... ........... 305 Table 312: RGMII Input Timing (Normal Mode)............ Mode) ....................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 306 Table 313: RGMII Input Timing (Delayed Mode) ....................... ................................... ........................ ....................... ....................... ........................ ..................... ......... 307 Table 314: GMII Output Timing............................. Timing........................................ ....................... ........................ ........................ ....................... ....................... ....................... ................... ........ 308 Table 315: GMII Input Timing ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............... .... 309 Table 316: MDC/MDIO Timing (Slave Mode) ...................... .................................. ........................ ....................... ....................... ........................ ....................... ............... .... 309 Table 317: MDC/MDIO Timing (Master Mode) ...................... .................................. ........................ ....................... ....................... ........................ ....................... ............. .. 309 Table 318: Serial LED Interface Timing ........................ ................................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 310 Table 319: SPI Timings............................. Timings......................................... ....................... ....................... ........................ ........................ ....................... ....................... ....................... ................... ........ 311 Table 320: EEPROM Timing............................. Timing......................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 312 Table 321: Serial Flash Timing ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ............. .. 313 Table 322: BCM53128KQLE Package without Heat Sink, 4-Layer Board, P = 3.1W........................... 3.1W.................................... ......... 314


Page 28


BCM53128 Data Sheet

List of Tables

Table 323: BCM53128KQLE Package with Heat Sink, 2-Layer Board, P = 3.1W................................ 3.1W......................................... ......... 314 Table 324: BCM53128IQLE Package with Heat Sink, 4-layer Board, P=3.1W ............................ ........................................ ................. ..... 315 Table 325: Ordering Information ....................... ................................... ....................... ....................... ........................ ....................... ....................... ........................ ....................... ........... 317


Page 29


BCM53128 Data Sheet

About This Document

About This Document Purpose and Audience This This docume document nt is for designe designers rs intere intereste sted d in integr integrati ating ng the BCM531 BCM53128 28 switch switches es into into their their hardwa hardware re design designs s and for others who need specific data about the physical characteristics and operation of the BCM53128 switches.

Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php.. http://www.broadcom.com/press/glossary.php

Document Conventions The following notational conventions are used in this document: •

Signal names names are are shown shown in uppercase uppercase letters letters (such (such as DATA). DATA).

•

A bar over over a signal signal name indicate indicates s that itit is active active low (such (such as CE). CE).

•

In register register and signal signal descriptions, descriptions, [n:m] [n:m] indicates indicates a range range from bit n to bit m (such as [7:0] [7:0] indicates indicates bits bits 7 through 0, inclusive).

•

The use of R or Reserved Reserved indicates indicates that that a bit or a field is reserved reserved by Broadcom Broadcom for for future future use. Typically, Typically, R is used for individual bits and Reserved is used for fields.

•

Numerical Numerical modifiers modifiers such such as K or M follow traditional traditional usage usage (for example, example, 1 KB means means 1,024 bytes, bytes, 100 Mbps [referring to fast Ethernet speed] means 100,000,000 bps, and 133 MHz means 133,000,000 Hz).


Page 30


BCM53128 Data Sheet

Technical Support

References The references references in this section may be used in conjunction conjunction with this document. Note: Broadcom Note: Broadcom provides customer access to technical documentation and software through its Customer Support Portal (CSP) and Downloads and Support site (see Technical (see Technical Support). Support). For Broadcom documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name

Number

Source

Broadcom Items [1]

Layout Layout and Design Design Guide Guide

53128-AN1xx-R

CSP

[2]

BCM53128 BCM53128 Programmer Programmer's 's Reference Reference Guide

53128-PG1xx-R

CSP

Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its custom customer er suppor supportt portal portal (https://support.broadcom.com https://support.broadcom.com). ). For For a CSP CSP acco accoun unt, t, cont contac actt your your Sales Sales or Engi Engine neer erin ing g support representative. In addition, Broadcom provides other product support through its Downloads and Support site (http://www.broadcom.com/support/ http://www.broadcom.com/support/). ).


Page 31


BCM53128 Data Sheet

Introduction

Section 1: Introduction Overview The BCM53128 is a single-chip, 9-port Gigabit Ethernet (GbE) switch device. It provides: •

A 9-port 9-port nonblockin nonblocking g 10/100/100 10/100/1000-Mb 0-Mbps ps switch switch control controller ler

•

Eight ports ports with with 10/100/10 10/100/1000BASE 00BASE-TX-c -TX-compat ompatible ible transcei transceivers vers

•

Nine integrated integrated Gigabit Gigabit MACs MACs (GMACs) (GMACs)

•

One GMII/RGMII/MII GMII/RGMII/MII/RvMII/TMII/ /RvMII/TMII/RvTMII RvTMII port for PHY-less connection to the management agent

•

An integrat integrated ed Motorol Motorola a SPI-comp SPI-compatible atible interface interface

•

High perfor performance mance,, integrate integrated d packet packet buffer buffer memory memory

•

An addr address ess resolu resolutio tion n engin engine e

•

A set of managem management ent informat information ion base base (MIB) (MIB) statistics statistics registers registers

The GMACs support full-duplex and half-duplex modes for 10 Mbps and 100 Mbps and full-duplex for 1000 Mbps. Flow control is supported in the half-duplex mode with backpressure. In full-duplex mode, IEEE 802.3x frame-based flow control is supported. The GMACs are IEEE 802.3-compliant and support maximum frame sizes of 9720 bytes. An integrated address management engine provides address learning and recognition functions at maximum fram frame e rate rates. s. The The addr addres ess s tabl table e prov provid ides es capa capaci city ty for for lear learni ning ng up to 4K unic unicas astt addr addres esse ses. s. Addr Addres esse ses s are are adde added d to the table after receiving an error-free packet. The MIB statistics registers collect receive and transmit statistics for each port and provide direct hardware support for the Ether-like MIB, MIB II (interfaces), and the first four groups of the RMON MIB. All nine groups of RMON can be supported by using additional capabilities, such as port mirroring/snooping, together with an external microcontroller to process some MIB attributes. The MIB registers can be accessed through the Serial Peripheral Interface Port by an external microcontroller.


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BCM53128 Data Sheet

Features and Operation

S e c ti t i o n 2 : F e a t ur u r e s a n d O p e r at at i o n Overview of Features and Operation The BCM53128 switches include the following features: •

“Quality “Quali ty of Service Service”” on page 34

•

“Port-Based VLAN” on page 38

•

“IEEE 802.1Q 802.1Q VLAN” VLAN” on on page 39

•

“Programmin “Progr amming g the VLAN Table” Table” on page page 40

•

“Double-Tagging” on page 41

•

“Jumbo Frame Support” on page 44

•

“Port Trunking/Aggregation” Trunking/Aggregation” on page 44

•

“WAN Port” on page page 45

•

“Rate Control” on page 45

•

“Protected Ports” on page 47

•

“Port Mirroring” Mirroring” on page 48

•

“IGMP “IGM P Snooping” Snooping” on on page 49

•

“MLD Snoopi Snooping” ng” on page 50 50

•

“IEEE 802.1x Port-Based Security” on page 50

•

“DoS Attack Attack Preventi Prevention” on” on page 51 51

•

“MSTP Multiple Multiple Spanning Spanning Tree” Tree” on page page 52

•

“Software Reset” on page 52

•

“Loop Detec Detection” tion” on page page 52

•

“BroadSync “Broad Sync HD” HD” on page 53 53

•

“CableChecker™” on page 56

•

“Egress PCP Remarking” on page 57

•

“Address Management” Management” on page 57

•

“Powerr Savings “Powe Savings Modes” Modes” on page page 65

The following sections discuss each feature in more detail.


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BCM53128 Data Sheet

Quality of Service

Quality of Service The Quality of Service Service (QoS) feature provides up to six internal queues per port to support six different traffic traffic classes (TC). The traffic classes can be programmed so that higher-priority TC in the switch experiences less delay than lower-priority TC under congested conditions. This can be important in minimizing latency for delaysensitive traffic. The BCM53128 switches can assign the packet to one of the six egress transmit queues according to information in: •

“Port-Based QoS” on page 35 (ingress 35 (ingress port ID)

•

“IEEE 802.1p QoS” on on page 35

•

“MACDA-Based QoS” on page 36

•

“TOS/DSCP “TOS/ DSCP QoS” on on page 36

The “T “TC C De Decis cision ion Tr Tree ee”” on pa page ge 36 decide decides s which which priori priority ty system system is used used based based on three three progra programma mmable ble regist register er bits detailed in Table in Table 1: “TC Decision Tree Summary,” on page 36. 36. The corresponding traffic class is then assigned to one of the six queues on a port-by-port basis. Figure Figure 2: QoS Program Program Flow Flow

Port-Based Traffic Class Mapping

IEEE 802.1p Traffic Class Mapping

Incoming Packet

TC Decision Tree

MACDA-Based Traffic C lass Mapping

TOS/DSCP Based Traffic Class Mapping

COS 5 Traffic Class

BroadSync HD

traffic only COS 4 BroadSync HD

Outgoing Packet

PCP/DSCP Remarking

m h t i r o g l A R R W / P S

traffic only

COS 3 COS 2

COS Queue ID

COS Mapping

COS 1 COS 0


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BCM53128 Data Sheet

Quality of Service

Egress Transmit Queues Each Ethernet egress port has six transmit queues (COS0–COS5). The COS4 and COS5 are dedicated to BroadSync® HD traffic only and can not be shared with other traffic. Each COS queue has its own dedicated counter to measure the buffer occupancy of the queue for congestion management purpose. Every Ethernet (ingress) (ingress) port has its own set of counters to measure the buffer buffer occupancy and the arrival arrival rate related related to the traffic received from the port. The IMP (egress) port serves four queues (COS0–COS3) and the traffic generated by the Local Management Packet Generator which generate management report messages back to CPU, e.g., the Time Sync TX time stamp packets. Each COS queue has its own dedicated counter to measure the buffer occupancy of the queue for congestion management purpose. The IMP (ingress) port also has its own set of counters to measure the buffer occupancy and the arrival rated to the traffic traffic received from the port, but should be used only if it is configured configured as a regular regular Ethernet port. All incoming frames are assigned to an egress transmit queue depending on their assigned TC. Each egress transmit queue is a list specifying an order for packet transmission. The corresponding egress port transmits pack packet ets s from from each each of the the queu queues es acco accord rding ing to a prog progra ramm mmab able le algo algori rith thm, m, with with the the high higher er TC queu queues es bein being g give given n greater greater access than the lower TC queues. Queue 0 is the lowest-TC lowest-TC queue. The The COS0 COS0–C –COS OS3 3 queu queues es are are dedic dedicat ated ed to nonnon-Br Broa oadS dSyn ync c HD traf traffi fic c only only and and as prog progra ramm mmed ed in the the TX Queu Queue e Control register. The BCM53128 uses strict priority (SP) and weighted round robin (WRR) algorithm for COS0– COS3 queues scheduling. scheduling. The scheduling scheduling is configurable configurable using the TX Queue Control Control register as one of following combinations of SP and WRR; 4SP, 4WRR, 1SP and 3WRR, 2SP and 2WRR The WRR algorithm weights for each queue can be programmed using the TX Queue Weight register.

Port-Based QoS The TC of a packet received from an Ethernet (or IMP) port is assigned with the TC configured for the corresponding port. The mapping mechanism is globally enabled/disabled by programming the QoS Global Control register; the mapping entry is also per-port configured using the Default IEEE 802.1Q Tag register. When disabled, disabled, the TC that results from this mapping mapping is 000.

IEEE 802.1p QoS The The TC of a pack packet et rece receiv ived ed from from an Ethe Ethern rnet et (or (or IMP) IMP) port port is assi assign gned ed with with TC-c TC-con onfi figu gure red d for for the the corr corres espo pond nding ing IEEE 802.1p priority code point (PCP). The mapping mechanism is per port enabled/disabled using QoS IEEE 802. 802.1p 1p Enab Enable le regi regist ster er,, the the mapp mappin ing g entr entrie ies s are are perper-po port rt conf config igur ured ed by Port Port N (N = 0–7, 0–7, 8) PCP_ PCP_To To_T _TC C regi regist ster er.. When disabled or if the incoming packet is not tagged, the TC that results from this mapping is 000.


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BCM53128 Data Sheet

Quality of Service

MACDA-Based QoS MACDA-Based QoS is enabled when the IEEE 802.1p QoS is disabled using the 802_1P_EN bit in the QoS IEEE 802.1p Enable register. When using MACDA-based QoS, the destination address and VLAN ID is used to index the ARL table as described in “Address in “Address Management” on page 57. 57. The matching ARL entry contains a 3-bit TC field as shown in Table in Table 7 on page 60. 60. These bits set the MACDA-based TC for the frame. The MACDAbased TC is assigned to the TC bits depending upon the result shown in Table in Table 1. 1. The TC for the frame is mapp mapped ed to one one of the the egre egress ss tran transm smit it queu queues es base base on the the ingr ingres ess s port port usin using g the the TC_T TC_To_ o_CO COS S Mapp Mappin ing g regi regist ster er.. The TC bits for a learned ARL entry default to 0. To change the default, an ARL entry is written to the ARL table as described in the “Writing the “Writing an ARL Entry” on page 63. 63 . For more information about the egress transmit queues, see “Egress see “Egress Transmit Queues” on page 35. 35.

TOS/DSCP QoS The The TC of a pack packet et rece receiv ived ed from from an Ethe Ethern rnet et (or (or IMP) IMP) port port is assi assign gned ed with with TC conf config igur ured ed for for the the corr corres espo pond ndin ing g IP TOS/DSCP. The mapping mechanism is per port enabled/disabled using QoS DiffServ Enable register, the mapping entries are globally configured by DiffServ Priority Map 0 register through DiffServ Priority Map 3 register. When disabled or the incoming packet is not of IPv4/v6 type, the TC resulted from this mapping is 000.

TC Decision Tree Non-BroadSync HD Frame The TC decision tree determines which priority system is assigned to TC-mapping bits for the given frame. As summarized above, the TC bits for the frame can be determined according to the ingress port-based TC, IEEE 802.1p TC, MACDA-based TC, DiffServ TC or MACSA-based TC information. The decision on which TC mapping to use is based on the Port_QoS_En bit and the QoS_Layer_Sel bits of the QoS Global Control register. Table 1 summar summarize izes s how these these progra programm mmable able bits bits affect affect the derive derived d TC. The DiffSe DiffServ rv and IEEE IEEE 802.1p 802.1p QoS TC are only available if the respective QoS is enabled, and the received packet has the appropriate tagging. Table 1: TC Decision Decision Tree Summar Summary y Port_QoS _En

QoS_Layer _Sel

Value of TC Bits

0

00

IEEE 802.1p TC mapping if available; otherwise, MACDA-based TC mapping.

0

01

DiffServ TC mapping if available; otherwise, TC = 000.

0

10

DiffServ TC mapping for IP frame; otherwise, IEEE 802.1p TC mapping if available; otherwise, MACDA-based TC mapping.

0

11

The highest available TC of the following: IEEE 802.1p TC mapping, DiffServ TC mapping, MACDA-based TC mapping or MACSA-based TC mapping.

1

00

MACSA-based TC mapping if available; otherwise, Port-based TC mapping.

1

01


1

10



Page 36


BCM53128 Data Sheet

Quality of Service

Table 1: TC Decision Decision Tree Summary Summary (Cont.) Port_QoS _En

QoS_Layer _Sel

1

11

Value of TC Bits The highest available TC of the following: Port-based TC mapping, MACSAbased TC mapping, IEEE 802.1p TC mapping, DiffServ TC mapping or MACDA-based TC mapping.

BroadSync HD Frame For the BroadSync HD packet from an Ethernet port, the TC is determined directly from the explicit IEEE 802. 802.1Q 1Q/P /P tag tag carr carried ied in the the Broa BroadS dSyn ync c HD pack packet ets s (Bro (Broad adSy Sync nc HD pack packet ets s are are expe expect cted ed to alwa always ys be tagg tagged ed), ), which is independent of Table Table 1 on page 36 TC 36 TC mapping. The conditions deciding whether an incoming packet is BroadSync HD are: 1. The port from which the packet is received is configured as BroadSync HD-enabled. 2. The packet received received is either VLAN tagged or priority priority tagged, with PCP = 4 or 5. 3. The MACDA is of multicast type and can be found through ARL table search. search. Note: BroadSync Note: BroadSync HD cannot be received from the IMP port.

Queuing Class (COS) Determination The BCM53128 supports the COS mapping through the mapping mechanisms listed below. •

TC to COS mapping: mapping: The queuing queuing class to forwar forward d a packet to an Ethernet Ethernet port is mapped mapped from the the TC determined for the packet. The mapping entries are globally configured using TC_To_COS Mapping register.

•

BroadSync BroadSync HD to COS mapping: mapping: The The queuing class class to forward forward a BroadSync BroadSync HD packet packet to a BroadSync BroadSync HD-enabled Ethernet port is mapped from the PCP carried by the packet. PCP5 is mapped to COS5 and PCP4 is mapped to COS4.

•

CPU to COS mapping: mapping: The The queuing class class to forward forward a packet to the external external CPU throug through h the IMP port is determined based on the reasons to forward (copy or trap) the packet to CPU. The mapping entries are globally configured using CPU_To_COS Map register. Note: When Note: When the BCM53128 BCM53128 is configured configured in the aggregation aggregation mode where where the IMP operates as the uplink port to the upstream network processor, the COS is decided from the TC based on the normal packet classification flow. Otherwise, the IMP operates as the interface to the management CPU, and the COS is decided based on the reasons for forwarding the packet to the CPU.

Table 2 shows 2 shows the reasons for forwarding a packet to the CPU. The ToCPU COS values listed are the default setting and are configurable. In order to prevent out of order delivery of the same packet flow to the CPU, the COS for the mirroring and SA learning reasons must be programmed with a value that is lower than or equal to the value of the other reasons.


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BCM53128 Data Sheet

Port-Based VLAN

Table 2: Reasons Reasons to Forward a Packet Packet to the CPU ToCPU Reason

Description

ToCPU COS

Mirr Mirror orin ing g

The The pack packet et is forw forwar arde ded d (cop (copie ied) d) thro throug ugh h the the IMP IMP port port beca becaus use e it needs to be mirrored to the CPU as the capturing device.

0

SA Lear Learni ning ng

The The pack packetis etis for forwarde arded d (copi copied ed)) throu hroughth ghthe e IMP portbe portbeca caus use e its its SA 0 needs to be learned by the CPU.

Swit Switch chin ing g /Floo /Floodi ding ng

The The pack packet et is forw forwar arde ded d thro throug ugh h the the IMP IMP port port eith either er beca becaus use e the the CPU CPU 0 is one of the intended destination hosts of the packet or because the switch makes the flooding decision to reach all potential destinations.

Protocol Protocol Termination Termination

The packet packet is forwarded forwarded (trapped) (trapped) through through the IMP IMP port because because it implies an IEEE 802.1 defined L2 protocol that needs to be terminated by the CPU.

Protocol Protocol Snooping Snooping

The packet packet is forwarded forwarded (copied) (copied) through through the IMP port because because it 0 implies an L3 or application level protocol that needs to be monitored by the CPU for network security or operation efficiency.

Exception Exception Processing Processing The packet is forwarded forwarded (trapped) (trapped) through through the IMP port for some special special processing processing even though the CPU is not the intended intended destination.

0

0

A packet could be forwarded to the CPU for more than one reason, therefore the COS selection is based on the highest highest COS values among all the reasons reasons for the packet.

Port-Based VLAN The port-based virtual LAN (VLAN) feature partitions the switching ports into virtual private domains designated on a per port basis. Data switching outside of the port’s private domain is not allowed. The BCM53128 provide flexible VLAN configuration for each ingress (receiving) port. The port-based VLAN feature works as a filter, filtering out traffic destined to nonprivate domain ports. The private domain ports are selected for each ingress port using Port-Based VLAN Control register. For each received received packet, the ARL resolves resolves the DA and obtains obtains a forwarding forwarding vector (list of ports to which the frame will be forwarded). The ARL then applies the VLAN filter to the forwarding vector, effectively masking out the nonprivate domain ports. The frame is only forwarded to those ports that meet the ARL table criteria, as well as the port-based VLAN criteria.


Page 38


BCM53128 Data Sheet

IEEE 802.1Q VLAN

IEEE 802.1Q VLAN The The BCM5 BCM531 3128 28 supp suppor ortt IEEE IEEE 802. 802.1Q 1Q VLAN VLAN and and up to appr approx oxim imat ately ely 4000 4000 VLAN VLAN tabl table e entr entries ies that that resi reside de in the the internal embedded memory. Once the VLAN table is programmed and maintained by the microcontroller, the BCM53128 autonomously handle all operations of the protocol. These actions include the stripping or adding of the IEEE 802.1Q tag, depending on the requirements of the individual transmitting port. It also performs all the necessary necessary VLAN lookups in addition addition to MAC L2 lookups. lookups.

IEEE 802.1Q VLAN Table Organ Organizatio ization n Each VLAN table entry, also referred to as a VLAN ID, an Untag map, and a Forward map. •

The Untag Untag map controls controls whether whether the the egress egress packet is is tagged or untagg untagged. ed.

•

The Forward Forward map map defines defines the membership membership within within a VLAN VLAN domain. domain.

•

If the Ingress Ingress port is an ISP port port in double-tag double-tag mode, the FWD_MO FWD_MODE DE indicates indicates whether whether the packet packet forwarding forwarding should be based on VLAN membership membership or based on ARL flow.

The Untag map and Forward map include bit-wise representation of all the ports. Figure Figure 3: VLAN Table Table Organizatio Organization n

Entry 0

FWD_MODE MSTP_Index

UN T AG_M AP[ 8: 0]

F OR W AR D_ M AP[8 :0]

Entry 1 Entry 2

Entry 4095

Note: When Note: When the IEEE 802.1Q feature is enabled, frames sent using the CPU must be tagged. If the MII port is configured as a management port, then the tag is not stripped even if the untag bit is set.


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BCM53128 Data Sheet

Programming the VLAN Table

Programming the VLAN Table The IEEE 802.1Q VLAN feature can be enabled by writing to the Enable IEEE 802.1Q bit in the Global IEEE 802.1Q register. The default priority and VID can be assigned to each port in the Default IEEE 802.1Q Tag register. These are necessary when tagging a previously untagged frame. The Hashing algorithm uses either [VID, MAC] or [MAC] for the ARL index key, depending on the VLAN Learning Mode bits in the Global IEEE 802.1Q register. If both the VID and MAC address are used, a single MAC address is able to be a member of multiple VLANs simultaneously. The VLAN table can be written written using the following steps: steps: 1. Use the VLAN Table Entry register register to define the ports that are part of the VLAN group and the ports that that should be untagged. 2. Use the VLAN Table Address Index Index register to define the VLAN ID of the VLAN group. Note: VLAN Note: VLAN ID 0xFFF is reserved. reserved. However However VID = 0xFFF can be forwarded forwarded if the VID_FFF_Fw VID_FFF_Fwding ding bit is set in the Global VLAN Control 5 register. 3. Set bit [1:0] = 00 of the VLAN Table Read/Write/Clear Control register to indicate a write operation. 4. Set bit 7 of the VLAN Table Read/Write/Clear Control register to 1, starting the write write operation. This bit returns to 0 when the write is complete. The VLAN table can be read using the following steps: 1. Use the VLAN Table Address Index Index register to define from which which VLAN group to read the data. 2. Set bit [1:0] = 01 of the VLAN Table Read/Write/Clear Control register to indicate a read operation. 3. Set bit bit 7 of the the VLAN VLAN Tabl Table e Read Read/W /Wri rite te/C /Cle lear ar Cont Contro roll regi regist ster er to 1 to star startt the the read read oper operat atio ion. n. This This bit bit retu return rns s to 0 when the read is complete. 4. Read the VLAN Table Entry register to obtain the VLAN table entry information.


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BCM53128 Data Sheet

Double-Tagging

Double-Tagging The BCM53128 provide provide the double tagging feature, feature, which is useful useful for ISP applications applications.. When the ISP aggregates incoming traffic from each individual customer, the extra tag (double tag) can provide an additional layer of tagging to the existing IEEE 802.1Q VLAN. The ISP tag (extra tag) is a way of separating individual customers from other customers. Using the IEEE 802.1Q VLAN tag, the individual customer’s traffic can be separated. When the double-tagging double-tagging feature is enabled using the Global VLAN Control 4 register register and the Enable IEEE 802.1Q (bit7) of the Global IEEE 802.1Q register, users can expect two VLAN tags in a frame: the tag close to MAC_SA is the ISP tag, and the one following is the customer tag as shown in Figure in Figure 4. 4. Figure Figure 4: ISP Tag Tag Diagram Diagram

MAC_DA

MAC_SA ISP_TA TAG G C us t om er_ t ag T y /Len

T PI D

Pay load

VI D

The switch uses the ISP tag for ARL and VLAN table accesses and the customer tag as an IEEE 802.1Q tag. There is a per chip programmable register Double Tagging TPID register for ISP tag (default = 9100'h). All ISP tags will be qualified by this Tag Protocol ID (TPID) value. When the double-tagging feature is enabled, all switch ports are separated into two groups, ISP ports and custom customer er ports. ports. The BCM531 BCM53128 28 perfor performs ms the normal normalizat ization ion proces process s for all ingres ingress s frames frames,, whethe whetherr from from the ISP port or customer port. The normalization normalization process is to insert an ISP tag, customer tag, or ISP + customer customer tag (depending whether the ingress frame is without tags or with one tag) to allow all ingress frames with a double tag. But if the ingress frames are with a double tag (ISP + customer tag), and the ISP tag TPID matches the TPID TPID specif specified ied in the Double Double Tagging Tagging TPID TPID regist register, er, it does does not perfor perform m the normal normalizat ization ion proces process. s. The ISP ports ports are defined in the ISP Port Selection Portmap register. When the port (s) corresponding bit(s) are set, that port (s) should should be connec connected ted ISP, ISP, and otherw otherwise ise connec connected ted to custom customers ers.. Each Each switch switch device device can have have multip multiple le ports ports assigned as ISP ports, and each ISP is uniquely identified using different VLAN forward maps or the port-based VLAN feature. If the ingress frame is an untagged frame, the IEEE 802.1Q tag which can be configured by the Default IEEE 802.1Q Tag Register (Page 34h: Address 10h) will add to an incoming untagged frame. If the ingress frame is tagged with the 802.1p tag, the default VID which can be configured by the Default IEEE 802.1Q Tag Register (Page 34h: Address 10h) will be tagged the incoming 802.1p frame.


Page 41


BCM53128 Data Sheet

Double-Tagging

ISP Port It is possible for ISP port to receive three different types of frames: untagged, ISP-tagged, and ISP+Customertagged frames. When the double-tagging feature is enabled and the received frame is untagged (or the TPID does not match with ISP TPID specified in Double Tagging TPID register, the default ISP tag and customer tag are added, and VLAN VLAN ID of ISP ISP tag tag rece receive ives s it from from the the port port defa defaul ultt VID. VID. The The fram frames es are are forw forwar arde ded d acco accord rdin ing g to the the VLAN VLAN table table.. Howeve However, r, if the Port-B Port-Base ased d VLAN VLAN Contro Controll regist register er is enabled enabled,, the egress egress ports ports specif specified ied in the port-V port-VLAN LAN contro controll register override the VLAN table settings. If the received frame is ISP tagged (TPID matches with the ISP tag VLAN VLAN ID specif specified ied in the double double-ta -taggin gging g TPID TPID regist register) er),, the default default custom customer er tag (8100 (8100 + default default PVID) PVID) is added, added, the ISP VID is used to access the ARL table, and the ISP tag can be stripped on the way out according to the untagged untagged bit setting setting in the VLAN table. In addition, addition, ISP port frame can forward to the destination destination port directly based on forward port map of VLAN table by setting FWD_MODE bit to 1 of VLAN Table Entry register. The VLAN ID is generated from the ISP tag, and TC is generated from the ingress frame outer tag.

Customer Port It is also possible for Customer port to receive two different types of frames: untagged and Customer-tagged frames. When the double-tagging feature is enabled, all the ingress frames preform the normalization process to insert a ISP tag or ISP + Customer tag (depending whether the ingress frame is without tags or with one tag) to allow all ingress frames with a double tag. The VLAN ID of ISP tag receives it from the port default VID. The VLAN ID is generated from the ISP tag, and the TC is generated from the ingress frame outer tag. Note: It is illegal to strip out the ISP tag on the ISP egress port by using the untagged bit setting in the VLAN table. Only the VLAN tagged or untagged packets are expected for the ingress of the customer ports. The customer do not add the ISP tags. There are two possible traffic scenarios; one from a customer port to an ISP port, and one from an ISP port to a customer port.


Page 42


BCM53128 Data Sheet

Double-Tagging

Uplink Traffic (from Customer Port to ISP) Data traffic is traffic received from the customer port without tags or a customer tag, and the frame is destined for for an ISP ISP port port.. The The cust custom omer er ingre ingress ss port port perf perfor orms ms a norm normal aliz izat atio ion n proc proces ess s to allow allow ingr ingres ess s fram frames es with with doub double le tags (ISP + Customer tag), and the ISP tag VID is based on the port default VID tag. However, if the ingress frame is with an 802.1p tag, the VID of 802.1p tag is changed by the VID of port default VID tag after the customer port normalization process. The TC do not change. Control traffic frames can be forwarded to the CPU first and then the CPU forwards to the ISP port if the switch management mode is enabled and if the RESV_MCAST_FLOOD bit=0 in the Global VLAN Control 4 register. In this case, the control frame adds an ISP tag by ingress port and forward to the CPU. The CPU can then forward it to the ISP port with or without the ISP tag by using the egress-direct feature.

Downlink Traffic (from ISP to Customer Port) Data traffic frame received from ISP port may or may not have ISP tag attached. When the received frame does not have an ISP tag and customer tag, the ISP ingress port does a normalization process to insert double tags (ISP + Customer tag), and the ISP tag VID is based on the port default VID tag. All ARL and VID table access should be based on the new tag. The traffic is then forwarded to the customer port through proper VLAN configuration. Usually, the software configures so the customer Egress port continuously removes the ISP tag. However, it is based on how the untagged map is configured. Moreover, if the ingress frame is with an 802.1p tag, the VID of 802.1p tag is changed by the VID of port default VID tag after the ISP port normalization normalization process. The TC will not change. change. The Control traffic is forwarded to the CPU when the switch management mode is enable and if the RESV_MCAST_FLOOD bit=0 in the Global VLAN Control 4 register. The BCM53128 can also support multiple ISP port configurations by enabled the FWD_MODE bit of VLAN Table Entry register. There are also two ways to separate traffic that belongs to two different ISP customers: 1. Each group (ISP, and customer) is assigned to the same VLAN group, so that traffic does not leak to other ISP. 2. Use the Port-based VLAN to separate traffic that belongs to a different ISP.


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BCM53128 Data Sheet

Jumbo Frame Support

Jumbo Frame Support The BCM53128 can receive and transmit frames of extended length on ports linked at gigabit speed. Referred to as jumbo frames, these packets are longer than standard maximum size which is defined using the Standard Max Frame Size register, register, but shorter than 9720 bytes. bytes. Jumbo packets packets can only be received received or forwarded forwarded to 1000BASE-T linked ports that are jumbo-frame enabled. Up to 38 buffer memory pages are required for storing the longest allowed jumbo frame. While there is no physical limitation to the number of ports that can be jumbo enabled, it is recommended that no more than two be enabled simultaneously to ensure system performance. There is no performance penalty for enabling additional jumbo ports beyond the potential strain on memory resources that can occur due to accumulated jumbo packets at multiple ports.

Port Trunking/Aggregation The BCM53128 support MAC-based trunking. The trunking feature allows up to four ports to be grouped togeth together er as a single single-li -link nk connec connectio tion n betwee between n two two switch switch devices devices.. This This increa increases ses the effect effective ive bandwi bandwidth dth throug through h a link and provides redundancy. redundancy. The BCM53128 allow up to two trunk groups. groups. Trunks are composed composed of predetermined ports and can be enabled using Trunking Group 0 register. Ports within a trunk group must be of the same linked speed. By performing a dynamic hashing algorithm on the MAC address, each packet destined for the trunk is forwarded to one of the valid ports within the trunk group. This method has several key advantages. By dynamically performing this function, the traffic patterns can be more balanced across the ports within a trunk. In addition, the MAC-based algorithm provides dynamic failover. If a port within a trunking group fails, the other port within the trunk automatically assumes all traffic designated for the trunk. It allows for a seamless, automatic redundancy scheme. This hashing function can be performed on either the DA, SA, or DA/ SA, depending on the Trunk Hash Selector bit of MAC Trunking Control register. Figure Figure 5: Trunking Trunking S witch 1

Frame Z

Frame Y

Frame X

S wi tch 2

Port X Port Y

Port 0 One Pipe

Port Z

Port 1 Port 2


Page 44


BCM53128 Data Sheet

WAN Port

WAN Port The BCM53128 offers a programmable WAN port feature: it has a WAN Port Select register. Select a port as a WAN port, then all of that port’s traffic is forwarded to the CPU port only. The non-WAN port traffic from all other local ports does not flood to the WAN port.

Rate Control Ingress Rate Control Forwarding broadcast traffic consumes switch resources, which can negatively impact the forwarding of other traffic. The rate-based broadcast storm suppression mechanism is used to protect regular traffic from an overabundance of broadcast or multicast traffic. This feature monitors the rate of ingressed traffic of programmable packet types. If the rates of these packet types exceed the programmable maximum rate, the packets are dropped. To enable the Broadcast Storm Suppression, pull the BC_SUPP_EN high during poweron/reset. Alternatively, the feature can be activated in the Port Receive Rate Control register. The broadcast storm suppression mechanism works on a credit-based rate system that figuratively uses a bucket to track the bandwidth of each port (see the figure below). Credit is continually added to the bucket at a programmable bucket bit rate. Credit is decremented from the bucket whenever one of the programmable packet types is ingressed at the port. If no packets are ingressed for a considerable length of time, the bucket credit continues to increase up to a programmable-maximum bucket size. If a heavy burst of traffic is suddenly ingressed at the port, the bucket credit becomes drained. When the bucket is emptied, incoming traffic is constrained to the bucket bit rate (the rate at which credit is added to the bucket). At this point, excess packets are either dropped or deterred using flow control, depending upon the Suppression Drop mode in the Ingress Rate Control Configuration register. Figure 6: Bucket Bucket Flow Ingress Packet Rate assigned to Bucket 1 assigned

Bucket 1 Bit Rate

Ingress Packet Rate assigned to Bucket 2

Bucket 2 Bit Rate

Accumul Acc umulated ated Credit Credit Accumul Acc umulated ated Credit Credit

BUCKET 1

BUCKET 2

If there is no accumulated credit available, the switch does not accept input packets.


Page 45


BCM53128 Data Sheet

Rate Control

Two-Bucket System For added flexibility, the BCM53128 employ two buckets to track the rate of ingressed packets. Each of the two buckets (Bucket 0 and Bucket 1) can be programmed to monitor different packet types. For example, Bucket 0 could monitor broadcast packets, while Bucket 1 monitors multicast packets. Multiple packet types can be monitored by each bucket, and a packet type can be monitored by both buckets. The rates of each bucket can be individually programmed (see “Bucket (see “Bucket Bit Rate”). Rate”). For example, the broadcast packets of Bucket 0 could have a maximum rate of 3 Mbps, whereas the multicast packets of Bucket 1 could be allowed up to 80 Mbps. The size of each bucket can be programmed using the Suppressed Packet Type Mask of the Ingress Rate Control Configuration register. This determines the maximum credit than can accumulate in each bucket. The Rate Count and Bucket Size can be individually programmed for each port, providing another level of flexibility. Suppression control can be enabled or disabled on a per-port basis Ingress Rate Control Configuration register. This system allows the user to control dual packet-type rates on a per-port basis.

Egress Rate Contr Control ol The The BCM5 BCM531 3128 28 monit monitor or the the rate rate of egre egress ss traf traffi fic c per per port port.. Unlik Unlike e the the Ingr Ingres ess s traf traffi fic c rate rate cont contro rol, l, the the Egre Egress ss Rate Rate Control Control provides only the per port rate control control regardless of traffic types. This feature only uses one bucket to track the rate of egressed egressed packets. The Egress Rate Control Control feature can be enabled in the Port Egress Rate Control Configuration register and the output rate per port can be controlled by setting the bucket size and Refresh Count in the same register. The Egress Rate Control feature only support absolute bit rate mode (Bit Rate Mode = 0) and the bucket bit rate calculation is shown in Table 3. 3.


Page 46


BCM53128 Data Sheet

Protected Ports

Bucket Bit Rate The relative ingress rates of each bucket can be programmed Port Receive Rate Control register on a per port basis. Each port has a programmable Rate Count value for Bucket 0 and Bucket 1. Additionally, the bit rate mode is programmed Ingress Rate Control Configuration register on a chip basis. If this bit is 1, the packet rate is automatically automatically scaled according according to the port link speed. Ports Ports operating at 1000 Mbps would be allotted allotted a 100 times higher ingress rate than ports linked at 10 Mbps. Together, the Rate Count value and the bit rate mode determine the bucket bit rate, which is a reflection of how quickly data can be ingressed (Kbps) at the given port for a given bucket. The Rate Count values are specified in the following table. Values outside these ranges are not valid entries. Table 3: Bucket Bucket Bit Rate Rate Bit Rate Bucket Bit Rate Rate Count (RC) Mode Link Speed Equation

Approximate Computed Bucket Bit Rate Values Values (As a function function of RC)

1–28

0

Any

= (RC x 8 x 1M) / 125

64 KB, 128 KB, 192 KB,..., 1.792 MB

29–127

0

Any

= (RC – 27) x 1M

2 MB, 3 MB, 4 MB,..., 100 MB

128–240

0

Any

= (RC – 115) x 1M x 8

104 MB, 112 MB, 120 MB,..., 1000 MB

1–125

1

10 Mbps

= (RC x 8 x 1M) / 100

0.08 MB, 0.16 MB, 0.24 MB,... 10 MB

1–125

1

100 Mbps

= (RC x 8 x 1M) / 10

0.8 MB, 1.6 MB, 2.4 MB,..., 100 MB

1–125

1

200 Mbps

= (RC x 8 x 1M) / 5

1.6 MB, 3.2 MB, 4.8 MB,..., 200 MB

1–125

1

1000 Mbps = RC x 8 x 1M

8 MB, 16 MB, 24 MB,... 1000 MB

Note: 1M Note: 1M represents 1 x 106.

IMP Port Egress Rate Control The IMP port egress is configurable of rate limiting at packet-per-second (PPS) granularity, in addition to bitsper-second (BPS) granularity. It can be configured using the IMP Port Egress Rate Control Configuration register.

Protected Ports The Protec Protected ted Ports Ports featur feature e allows allows certai certain n ports ports to be design designate ated d as protec protected ted Protec Protected ted Port Port Selecti Selection on regist register. er. All other ports are unprotected. Traffic between protected port group members is blocked. However, protected ports are able to send traffic to unprotected ports. Unprotected ports can send traffic to any port. Several applications that can benefit from protected ports: •

Aggregator: Aggregator: For For example, example, all the available available ports are are designated designated as protected protected ports ports except except a single aggregator port. No traffic incoming to the protected ports is sent within the protected ports group. Any flooded traffic is forwarded only to the aggregator port.

•

To prevent nonsecur nonsecured ed ports from monitori monitoring ng important important information information on a server port, port, the server server port and nonsecured ports are designated as protected. The nonsecured ports will not be able to receive traffic from the server port.


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BCM53128 Data Sheet

Port Mirroring

Port Mirroring The BCM53128 support Port Mirroring, allowing ingress and/or egress traffic to be monitored by a single port designated as the mirror capture port. The BCM53128 can be configured to mirror the ingress traffic and/or egress traffic of any other port (s). Mirroring multiple ports is possible, but can create congestion at the mirror capture port. Several filters are used to decrease congestion.

Enabling Port Mirroring Port Mirroring is enabled by setting the Mirror Enable bit in the Mirror Capture Control register. Figure 7: Mirror Mirror Filter Filter Flow Port mask filter

Ingress mirror mask

Port address filter

Ingress mirror filter

Port divider filter

Ingress mirror divider

Capture port

All packets

Egress mirror mask

Egress mirror filter

Egress mirror divider

Destination port(s)

Capture Port The capture port is capable of monitoring other specified ports. Frames transmitted and received at the other ports are forwarded to the Capture port according to the mirror filtering rules discussed below. The Capture port is specified by the Capture Port bits of the Mirror Capture Control register.

Mirror Filtering Rules Mirror filtering rules consist of a set of three filter operations (Port Mask, Packet Address, and Packet Divider) that are applied to traffic ingressed and/or egressed at a switch port.

Port Mask Filter The IN_MIRROR_MASK bits in the Ingress Mirror Control register define the receive ports that are monitored. The OUT_MIRROR_MASK bits in the Egress Mirror Control register define the transmit ports that are monitored.


Page 48


BCM53128 Data Sheet

IGMP Snooping

Any number of ingress/egress ports can be programmed to be mirrored, but bandwidth restrictions on the onemirror mirror capture port should be taken into account to avoid congestion congestion or packet loss.

Packet Address Filter The Ingress Mirror Control register is used to set the type of filtering that is applied to frames received on the mirrored ports. The IN_MIRROR_FILTER bits select among the following: •

Mirror Mirror all receiv received ed frames frames

•

Mirror Mirror receiv received ed fram frames es with with DA = x

•

Mirror Mirror receiv received ed fram frames es with with SA = x

where x is the 48-bit MAC address programmed into the Ingress Mirror MAC Address register. Likewise, the Egress Egress Mirror Mirror Control register is used to set the type of filtering filtering that is applied to frames transmitted transmitted on the egressed mirrored ports. The filtering MAC address is specified in the Egress Mirror MAC Address register.

Packet Divider Filter The IN_DIV_EN bit in the Ingress Mirror Control register allows further statistical sampling. When IN_DIV_EN = 1, the the rece receiv ive e fram frames es pass passin ing g the the init initia iall filt filter er are are divid divided ed by the the value value IN_M IN_MIR IRRO ROR_ R_DI DIV, V, whic which h is a 10-b 10-bit it value value stored stored in the Ingress Mirror Divider Divider register. Only one out of every n frames frames is forwarded forwarded to the mirror mirror capture port, where n = IN_MIRROR_DIV +1. This allows the following additional capabilities: •

Mirr Mirror or ever every y nth received frame

•

Mirr Mirror or ever every y nth received frame with DA = x

•

Mirr Mirror or ever every y nth received frame with SA = x

Similarly, the Egress Mirror Divide function is controlled by the Egress Mirror Control register and the Egress Mirror Divider register. Note: When When multip multiple le ingres ingress s ports ports have have been been enable enabled d in the IN_MI IN_MIRRO RROR_M R_MASK ASK,, the cumulat cumulative ive total total packet count received from all ingress ports is divided by the value of IN_MIRROR_DIV to deliver the nth receive frame to the mirror capture port. Egressed frames are governed by the OUT_MIRROR_MASK bit and the OUT_MIRROR_DIV bit.

IGMP Snooping The BCM53128 supports IP layer IGMP Snooping which includes IGMP unknown, query, report, and leave messages using the High-Level Protocol Control register. A frame with a value of 2 in the IP header protocol field and IGMP frames are forwarded to the CPU port. The management CPU can then determine, from the IGMP control packets which port should participate in the multigroup session. The management CPU proactively programs the multicast address in the ARL table or the multiport address entries. If the IGMP_FWD_EN in the High-Level Protocol Control register is enabled, IGMP frames will be trapped to the CPU port only.


Page 49


BCM53128 Data Sheet

MLD Snooping

MLD Snooping The BCM53128 supports IP layer MLD Snooping including MLD query, report, and done messages using the High-Level Protocol Control register.

IEEE 802.1x Port-Based Security IEEE 802.1x is a port-based authentication protocol. By receiving and extracting special frames, the CPU can control control whether the ingress and egress ports should forward forward packets or not. If a user port wants service from another port (authenticator), it must get approved by the authenticator. EAPOL is the protocol used by the authen authentic ticati ation on proces process. s. The BCM531 BCM53128 28 detect detect EAP EAPOL OL frames frames by checki checking ng the destin destinati ation on addres address s of the frame. frame. The Destination addresses should be either a multicast address as defined in IEEE 802.1x (01-80-C2-00-0003) 03) or a user user-p -pre rede defi fine ned d MAC MAC (unic (unicas astt or mult multic icas ast) t) addr addres ess. s. Once Once EA EAPO POL L fram frames es are are dete detect cted ed,, the the fram frames es are are forwarded to the CPU so it can send the frames to the authenticator server. Eventually, the CPU determines whether the requestor is qualified or not based on its MAC_Source addresses, and frames are either accepted or dropped. The per-port EAP can be programmed in the register. BCM53128 provides three modes for implementing the IEEE 802.1x feature. Each mode can be selected by setting the appropriate bits in the register. The Basic Mode (when EAP Mode = 00'b) is the standard mode, the EAP_BLK_MODE bit would be set before authentication to block all of the incoming packets, upon authentication, the EAP_BLK_MODE bit would be cleared to allow all the incoming packets. In this mode, the Source Address of incoming packets is not checked. The second mode is Extended Mode (when EAP Mode = 10'b), where an extra filtering mechanism is implem implement ented ed after after the port port is authen authentic ticate ated. d. If the Source Source MAC addres address s is unknow unknown, n, the incomi incoming ng packet packets s would would be dropped and the unknown SA would not be learned. However if the incoming packet is IEEE 802.1x packet, or spec special ial fram frames es,, the the inco incomi ming ng pack packet ets s will will be forw forwar arde ded. d. The The defi definit nitio ion n of the the Unkn Unknow own n SA in this this case case is when when the switch cannot match the incoming Source MAC address to any of the addresses in ARL table, or the inco incomi ming ng Sour Source ce MAC MAC addr addres ess s matc matche hes s the the addr addres ess s in ARL ARL table table,, but but the the port port numb number er is mism mismat atch ched ed.. The The thir third d mode is Simplified Mode (when EAP Mode = 11'b). In this mode, the unknown Source MAC address packets would be forwarded to CPU rather than dropped. Otherwise, it is same as the Extended Mode operation. Note: The Note: The BCM53128 checks only the destination addresses to qualify EAPOL frames. Ethernet type fields, packet type fields, or non-IEEE 802.1Q frames are not checked.


Page 50


BCM53128 Data Sheet

DoS Attack Prevention

DoS Attack Prevention The BCM53128 supports the detection of the following DoS (Denial of Service) attack types based on a register setting, setting, which can be programmed programmed to drop or not to drop each type of DoS packet, respectively respectively.. Table 4: DoS Attacks Attacks Detected Detected by BCM53128 DoS DoS Atta Attack ck Type Type

Desc Descri ript ptio ion n

IP_LAND

IPDA = IPSA in an IPv4/IPv6 datagram

TCP_ TCP_BLA BLAT T

DPor DPortt = SP SPor ortt in a TCP TCP head header er carr carrie ied d in an unfr unfrag agme ment nted ed IP data datagr gram am or in the the firs firstt fragment of a fragmented IP datagram

UDP_ UDP_BL BLAT AT

DPor DPortt = SP SPor ortt in a UDP UDP head header er carr carrie ied d in an unfr unfrag agme ment nted ed IP data datagr gram am or in the the firs firstt fragment of a fragmented IP datagram

TCP_NU TCP_NULLS LLScan can

Seq_Nu Seq_Num m = 0 and and all all TCP_ TCP_FLA FLAGs Gs = 0 in a TCP header header carrie carried d in an unfrag unfragmen mented ted IP datagram or in the first fragment of a fragmented IP datagram

TCP_XM TCP_XMASS ASScan can

Seq_Nu Seq_Num m = 0, FIN = 1, URG URG = 1, and PSH = 1 in a TCP header header carrie carried d in an unfragmented IP datagram or in the first fragment of a fragmented IP datagram

TCP_SYNFIN TCP_SYNFINScan Scan

SYN = 1 and FIN FIN = 1 in a TCP TCP header header carrie carried d in an unfragment unfragmented ed IP datagram datagram or in the first fragment of a fragmented IP datagram

TCP_SY TCP_SYNEr NError ror

SYN = 1, ACK = 0, and SRC_Po SRC_Port rt < 1024 1024 in a TCP header header carrie carried d in an unfrag unfragmen mented ted IP datagram or in the first fragment of a fragmented IP datagram

TCP_Sh TCP_Short ortHD HDR R

The length length of a TCP TCP header header carrie carried d in in an an unfr unfragm agment ented ed IP datagr datagram am or the first first fragment of a fragmented IP datagram is less than MIN_TCP_Header_Size

TCP_Fr TCP_FragE agErro rrorr

The Fragme Fragment_ nt_Off Offset set = 1 in any fragme fragment nt of a frag fragmen mented ted IP datagr datagram am carryi carrying ng part part of TCP data

ICMPv4_Fra ICMPv4_Fragment gment

The ICMPv4 ICMPv4 protoco protocoll data data unit unit carried carried in a fragmented fragmented IPv4 datagram datagram

ICMPv6_Fra ICMPv6_Fragment gment

The ICMPv6 ICMPv6 protoco protocoll data data unit unit carried carried in a fragmented fragmented IPv6 datagram datagram

ICMPv4_Lon ICMPv4_LongPing gPing

The ICMPv ICMPv4 4 ping (echo request) request) protoc protocol ol data data unit carried carried in an unfragme unfragmented nted IPv4 data datagr gram am with with its its Tota Totall Leng Length th indic indicat ating ing a valu value e grea greate terr than than the the MAX_ MAX_IC ICMP MPv4 v4_S _Siz ize e+ size of IPv4 header

ICMPv6_Lon ICMPv6_LongPing gPing

The ICMPv ICMPv6 6 ping (echo request) request) protoc protocol ol data data unit carried carried in an unfragme unfragmented nted IPv6 datagr datagram am with with its payloa payload d length length indicat indicating ing a value value greate greaterr than than the MAX_IC MAX_ICMPv MPv6_S 6_Size ize

•

MIN_TCP_H MIN_TCP_Header_ eader_Size Size is programma programmable ble between between 0 and 255 bytes, bytes, inclusive. inclusive. The default default value is set to 20 bytes (TCP header without options).

•

MAX_ICMPv4_ MAX_ICMPv4_Size Size is programma programmable ble between between 0 and 9.6 KB, inclusive. inclusive. The default default value value is set to 512 bytes.

•

MIN_TCP_H MIN_TCP_Header_ eader_Size Size is programmab programmable le between between 0 and 9.6 KB, inclusive. inclusive. The default value value is set to 512 bytes.

•

The default default control control setting setting for all types of DoS DoS attacks is not to to drop the DoS attack attack packet. packet.

•

It is globally configur configurable able whether whether to perform perform the SA learning learning operation operation with with the received received packets packets of the DoS attack type defined in the registers, regardless of the individual DoS attack types.

•

Once a packet packet is detected detected as a DoS attack type type that must be dropped, dropped, the the packet is dropped dropped regardless regardless of ARL forwarding decisions, but its forwarding based on mirroring function is not affected.


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BCM53128 Data Sheet

MSTP Multiple Spanning Tree

MSTP Multiple Spanning Tree The BCM53128 supports up to eight multiple spanning trees. When the EN_RX_BPDU bit = 1, the BCM53128 forwards BPDU packets to the management port only.

Software Reset The BCM53128 provide Software Resets. Software Resets can be triggered by programming the Software Reset Control register.

Loop Detection The BCM53128 provide the Loop Detection feature for unmanaged environments (that is, those without a manage managemen mentt CPU). CPU). When When the Loop Loop Detect Detection ion featur feature e is enable enabled d and activa activated ted,, the switch switch genera generates tes Broadc Broadcom om proprietary tag frames (Loop Discovery Frames) at a programmed interval, and when it detects a loop, it gives a loop loop dete detect cted ed warn warning ing with with a blin blinkin king g LED LED or with with a soun sound d prod produc uced ed by a spea speake ker. r. This This feat featur ure e does does not not repa repair ir the loop, but only issues a warning. The Discovery Frame is a broadcast frame, and the switch ensures the forwarding of the frame by providing special priority for the frame by giving it a higher priority over other broadcast frames, assigning highest queue automatically and overwriting the pause condition. The control/options over this feature are provided beginning with the Loop Detection Control register. The Loop Discovery frame uses a default multicast address (01-80-C2-00-00-01) in the Loop Detect Source Address register as a source address. Using a multicast address as a source address is i s illegal in the IEEE standard; however, since this is only intended to be used in the ROBO environment only, it should be allowed. This address scheme is used to avoid a possible possible disruption in forwarding forwarding decision decision by using a regular regular random Source Address. The Loop Discovery frame also uses the Module ID 0 register along with the Module ID 1 register to identify the origin of the Discovery frame. These registers are used to define a Source Chip ID and Source Port ID to distinguish the Discovery Frames from other ROBO chips. The implementation example for the Loop Detect feature is described in the Layout the Layout and Design Guide (document number 53128-AN1xx-R).


Page 52


BCM53128 Data Sheet

BroadSync HD

BroadSync HD BroadSync HD is the enhancement to IEEE 802.3 MAC and IEEE 802.1D bridges to support the kind of lowlatency isochronous services and guaranteed quality of service (QoS) that is required for many consumer electronics applications. The BCM53128 provides the BroadSync HD feature through the BroadSync HD Enable Control register. The BCM531 BCM53128 28 always always forwar forwards ds BPDU, BPDU, MRP packet packets s to CPU for BroadS BroadSync ync HD applic applicati ations ons,, and handles handles the IEEE IEEE 802.1 Time Sync Protocol. The BCM53128 can identify a packet as a BroadSync HD packet if the MAC DA matches a MAC address in the ARL table. The PCP equals four or five and the ingress port is BroadSync HD-enabled. There are two dedicated queues for BroadSync BroadSync HD Class 5 and Class 4 traffic traffic per egress egress port. BCM53128 enhances shaping shaping and scheduling for BroadSync HD operation.

Time Base and Slot Generation For BroadSync HD applications, the BCM53128 maintains a time base (32-bit counter) running at a granularity of 1 ns, which can be adjusted by CPU for synchronization with the BroadSync HD time master unit (Switch or Host) through the IEEE 802.1 Time Synchronized (TS) protocol (to be standardized). The TS protocol is implemented by the CPU which requires the BCM53128 to perform the following operations. •

A received TS protocol protocol packet packet is time stamped stamped at the the ingress port port when the first first byte (of (of MACDA) MACDA) arrives, arrives, and is transferred along with the receiving time stamp to the CPU.

•

A TS protocol packet packet initiated initiated by the CPU CPU (to be transmitte transmitted d at an egress port) port) is time stamped stamped at the egress port when the first byte (of MACDA) is transmitted, and the transmit time stamp recorded at the egress port is reported reported back to CPU.

It is required that the time synchronization point peers over an Ethernet link is chosen such that the link delay is perceived as constant, and the protocol exchange occurs at least every 10 ms over every link. The CPU may be required required to speed up or slow down the time base maintained in BCM53128 based on the TS protocol execution. The BCM53128 provides the time base adjustment mechanism for graceful time changes based on CPU instructions. In addition, the BCM53128 maintains counter mechanism to generate time Slot for BroadSync HD traffic scheduling. •

A Slot Slot is defi define ned d as as 125 125  s, it is used to pace the BroadSync HD Class 5 traffic which has tight jitter requirements;

•

A MacroSlot MacroSlot is configurable configurable as 1 ms, 2 ms, or 4 ms (binary (binary number number of Slots) using using the BroadSync BroadSync HD Slot Slot Adjustment register. It is used to pace the BroadSync HD Class 4 traffic which has relaxed jitter requirements.

The CPU may be required to make the Slot wider or narrower based on the TS protocol execution. The BCM53128 provides the Slot adjustment mechanism for graceful Slot width changes based on CPU instructions.


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BCM53128 Data Sheet

BroadSync HD

Transmission Shaping and Scheduling Packets Packets queued at each Ethernet Ethernet (egress) port is subject subject to the scheduling scheduling behavior as shown in Figure in Figure 8. 8. Figure 8: BroadSync BroadSync HD Shaping Shaping and Scheduling Scheduling

COS5 CO S5

Shaper A

COS4 CO S4

Shaper B

SP/ WRR

COS3 CO S3 COS2 CO S2

SP/WRR A

Shaper C

COS1 CO S1 COS0 CO S0

BroadSync HD Class 5 Media Traffic The COS5 queue is dedicated for BroadSync HD Class 5 traffic only, and a COS5 packet is always the highest priority to be scheduled for transmission, if it is allowed by the Shaper A that operates as follows. •

The Shaper A is an emulation emulation of fixed fixed bandwidth bandwidth pipe for Class Class 5 BroadSync BroadSync HD traffic traffic with with tight jitter jitter adaptively to handle interference from non-BroadSync HD or Class 4 BroadSync HD traffic. Note that the preamble and IPG transmission are not taken into account for the pipe operation.

•

Tunable parameters parameters for the the Shaper Shaper A are are listed listed as follows: follows: – MaxAVPacketSize indicates the maximum packet size allowed on a BroadSync HD-enabled port. It is a global setting using the BroadSync HD Max Packet Size register. – Class5_BW indi cates the reserved bandwidth for Class 5 BroadSync HD traffic at granularity of Byte (per Slot, 125  s). It is a per-port setting using BroadSync HD Class 5 Bandwidth Control register. – Class5_Window indicates the jitter control for Class 5 BroadSync HD transmission. It is a per-port setting using BroadSync HD Class 5 Bandwidth Control register.

•

At the start start of each each Slot Slot,, – Reset the credit in i n the shaping bucket to Class5_BW, if the queue is empty. – Reset the credit in i n the shaping bucket to Class5_BW, if the queue is not empty and Class5_Window is set to 0. – Reset the credit in i n the shaping bucket to Class5_BW, if the queue is not empty, Class5_Window is set to 1, and the credit remained in the shaping bucket is greater than MaxAVPacketSize. – Add Class5_BW to the credit in the shaping bucket, if the queue is not empty, Class5_Window is set to 1, and the credit remained in the shaping bucket is less than or equal to MaxAVPacketSize.


Page 54


BCM53128 Data Sheet

•

BroadSync HD

The credit in the the shaping bucket bucket decrement decrements s for every byte byte transmitt transmitted ed for the Class Class 5 BroadSync BroadSync HD traffic through the port. – If the credit reaches 0 before the end of the current Slot Sl ot while transmitting a Class 5 BroadSync HD packet, the ongoing packet transmission is not interrupted, and the credit stays at 0 until being reset at the start of next Slot. – The credit decrements resumes at the next Slot if the ongoing transmission continues.

As long as the credits in the shaping bucket is greater than 0, a Class 5 BroadSync HD packet is allowed to be scheduled for transmission.

BroadSync HD Class 4 Media Traffic The COS4 queue is dedicated for BroadSync HD Class 4 traffic only, and a COS4 packet always yield to COS5 traf traffi fic c (if (if allow allowed ed to be sche schedu dule led) d),, but but take takes s prec preced eden ence ce over over the the traf traffi fic c from from COS0 COS0~C ~COS OS3 3 queu queues es or follo follow w the the weight ratio between COS4 and COS0~COS3 for transmission scheduling, if it is allowed by the Shaper B that operates as follows. •

The Shaper B is an emulation emulation of fixed fixed bandwidth bandwidth pipe for Class Class 4 BroadSync BroadSync HD traffic traffic with with relaxed jitter jitter adaptively to handle interference from non-BroadSync HD or Class 5 BroadSync HD traffic. It also statistically levels the Class 4 BroadSync HD transmission bursts towards the next hop switch to reduce the buffering requirements, by using Slot (instead of MacroSlot) as the pacing mechanism. The preamble and IPG transmission are not accounted for in the pipe operation.

•

Tunable parameters parameters for the the Shaper Shaper B are are listed listed as follows: follows: – MacroSlot_Period indicates the periodic cycle time to shape the Class 4 traffic. It is a global setting using BroadSync HD Slot Adjustment register to indicate 1 ms, 2 ms, or 4 ms. – MaxAVPacketSize indicates the maximum packet size allowed on a BroadSync HD-enabled port. It is a global setting. (same as for BroadSync HD Class 5 setting) – Class4_BW indi cates the evenly divided bandwidth share per Slot, which is derived from dividing di viding the reserved bandwidth for Class 4 BroadSync HD traffic at granularity of Byte (per MacroSlot) by the number number of Slots within a MacroSlot. MacroSlot. It is a per-port per-port setting using BroadSync BroadSync HD Class 4 Bandwidth Bandwidth Control register.

•

At the start start of each each Slot Slot,, – If the Slot is the first one for the current MacroSlot, reset the credit bucket to Class4_BW+MaxAVPacketSize; (MaxAVPacketSize is used as the deficit base) – Otherwise, add Class4_BW to the credit in the shaping bucket.

•

The shaping credit credit bucket decreme decrements nts for every byte byte transmitted transmitted for the Class Class 4 BroadSync HD traffic. traffic.

As long as the credits in the shaping bucket is greater than or equal to MaxAVPacketSize, a Class 4 BroadSync HD packet is allowed to be scheduled for transmission.


Page 55


BCM53128 Data Sheet

CableChecker™

CableChecker™ The BCM53128 provide the cable diagnostic capabilities for unmanaged environments. The actual cable diagnostic feature lies in the PHY functional block. The BCM53128 devices let the user monitor the cable diagnostic results through LED display by setting the appropriate bits in the LED refresh registers. The BCM53128 uses the existing LED display (which (which is already assigned to various various functions) to indicate the cable diagnostic results. The table below shows the cable diagnostic result output for each LED function where 1 and 0 represent the LED indication indication pin status; status; 1 indicates indicates active and 0 indicates nonactive. nonactive. Note: •

The best way for for a user to visualize visualize the cable diagnost diagnostic ic test result result through through LEDs is to bring bring out the LINK status bit to the LED display along with other functions to be displayed per port. In this way, the user can observe the cable diagnostic result from the flashing (or lit) LED of other functions while LINK LED is off. The switch will turn off the LINK status LED during the cable diagnostic mode.

•

The cable diagnosti diagnostic c is expected expected to be most effective effective when when the user cannot cannot establish establish the the link with the partner.

Table 5: Cable Cable Diagnostic Diagnostic Output LED Function Function in in LED Function Function Regist Register er

Cable Cable Diagnostic Diagnostic Output Output

Reserved

–

LNK

No output during the cable diagnostic mode

DPX

1: Passed 0: Failed

ACT

1: Passed 0: Failed

COL

1: Passed 0: Failed

LNK/ACT

No output during the cable diagnostic mode

DPX/COL

1: Passed 0: Failed

SPD10M

1: Failed 0: Passed

SPD100M

In LED function0 map 1: Cable diagnostic passed 0: Failed In LED function1 map 1: Cable diagnostic failed 0: Passed

SPD1G

1: Passed 0: Failed


Page 56


BCM53128 Data Sheet

Egress PCP Remarking

Table 5: 5: Cable Diagnostic Diagnostic Output Output (Cont.) (Cont.) LED Function Function in in LED Function Function Regist Register er

Cable Cable Diagnostic Diagnostic Output Output

10M/ACT

1: Failed 0: Passed

100M/ACT

In LED function0 map 1: Cable diagnostic passed 0: Failed In LED function1 map 1: Cable diagnostic failed 0: Passed

10–100M/ACT

1: Failed 0: Passed

1G/ACT

1: Passed 0: Failed

Reserved

–

Egress PCP Remarking The BCM53128 provides an egress PCP remarking feature of the outer tag at each egress port which includes the PCP field modification based on the internal generated TC. The Egress PCP remarking process applies to Ethernet ports only and can be enabled by Traffic Remarking Control register. Each Ethernet port can provide a 8-entry mapping table indexed by TC to map to the {New PCP} field for the outgoing packet using Egress NonBroadSync HD Packet TC to PCP Mapping register. Note: For Note: For the BroadSync HD-enabled egress port, the egress PCP for the non-BroadSync HD class of traffic must never be programmed with values of 100 and 101.

Address Managem Management ent The BCM53128 Address Resolution Logic contains the following features: •

Four bins per per bucket bucket address address table table configu configuratio ration. n.

•

Hashing Hashing of the MAC/VID MAC/VID address address to to generate generate the address address table table point. point.

The address management unit of the BCM53128 provides wire speed learning and recognition functions. The address table supports 4K unicast/multicast addresses using on-chip memory.


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Address Table Organization The MAC addresses are stored in embedded SRAM. Each bucket contains four entries or bins. The address table has 1K buckets buckets with four entries entries in each bucket. This allows up to four different MAC addresses addresses with the same same hash hashed ed index index bits bits to be simu simult ltan aneo eous usly ly mapp mapped ed into into the the addr addres ess s tabl table. e. In the the ARL ARL DA/S DA/SA A look lookup up proc proces ess, s, it hashes a 10-bit search index and read out bin0 and bin1 in the first cycle, and read out bin2 and bin3 in the second second cycle. These four entries are used for ARL routing routing and learning. learning. Figure Figure 9: Address Address Table Organizatio Organization n

MAC Address [47:0]

HASH Function

VID [11:0]

Hash Index [9:0] 4K ARL Table 000000

bi n0

bi n1

bin2

bin3

Four bins per index

Unicast Address V

S

A

TC

CON

R svd

Port ID

VID[11:0]

MAC AD DR

VID[11:0]

MAC AD DR

Multicast Address

0003FF

V

S

A

TC

CON

MC AST MAP

The index to the address table is computed using a hash algorithm based on the MAC address and the VLAN ID (VID) if enabled. Note: In Note: In the Enable IEEE 802.1Q and VLAN Learning Mode both the MAC address and the VLAN ID (VID) are used to compute the hashed index. See “IEEE See “IEEE 802.1Q VLAN” on page 39 for 39 for more information. The hash algorithm uses the CRC-CCITT polynomial. The input to the hash is reduced to a 16-bit CRC hash value. Bits[9:0] of the hash are used as an index to the approximately 4K locations of the address table. The CRC-CCITT polynomial is: x16+x12+x5+1


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Address Management

Address Learning Inform Informati ation on is gather gathered ed from from receiv received ed unicas unicastt packet packets s and learne learned d or stored stored for the future future purpos purpose e of forwar forwardin ding g frames addressed to the receiving port. During the receive process, the frame information (such as the Source Address [SA] and VID) is saved until completion of the packet. An entry is created in the ARL table memory if the following conditions are met: •

The packet packet has been received received without without error. error.

•

The packet packet is of legal legal leng length. th.

•

The packet packet has a unic unicast ast SA.

•

If using IEEE IEEE 802.1Q 802.1Q VLAN, the the packet packet is from an SA SA that belongs belongs to the the indicated indicated VLAN domain. domain.

•

The packet does does not have a reserved reserved multicast multicast destinatio destination n address. address. The Multicast Multicast Learning Learning bit of the Reserved Multicast Control register can disable this condition.

•

There is free space space available available in in memory memory to which which the hashed hashed index index points. points.

When unicast packets are dynamically learned, the VALID bit is set, the AGE bit is set, and the STATIC bit is cleared in the entry. See Table See Table 7 on page 60 for 60 for a description of a unicast ARL entry. Multicast addresses are not learned into the ARL table, but must be written using one of the “Programming the “Programming Interfaces” on page 95. 95. See “Writing See “Writing an ARL Entry” on page 63 and 63 and Table Table 9 on page 61 for 61 for more information.

Address Addre ss Resolu Resolution tion and Frame Forwarding Received packets are forwarded based on the information learned or written into the ARL table. Address resolution is the process of locating this information and assigning a forwarding destination to the packet. The destination address (DA) and VID of the received packet are used to calculate a hashed index to the ARL table. The hashed index key is used by the address address resolution function function to locate locate a matching matching ARL entry. The frame is assi assign gned ed a dest destin inat ation ion base based d on the the forw forwar ard d fiel field d (POR (PORTI TID D or FWD_ FWD_PR PRT_ T_MA MAP) P) of the the ARL ARL entr entry. y. If the the addr addres ess s resolution function fails to return a matching ARL entry, the packet is flooded to all appropriate ports. The follow following ing two sectio sections ns descri describe be the specif specifics ics of addres address s resolu resolutio tion n and frame frame forwar forwardin ding g for “Unicast “Unicast Addres Addresses” ses” on page 59 and 59 and “Multicast “Multicast Addresses” on page 61. 61.

Unicast Addresses Frames containing a unicast destination address are assigned a forwarding field corresponding to a single port. Listed below is the unicast address-resolution algorithm: •

If the multiport multiport addressi addressing ng feature feature is enabled and the DA matches matches one one of the programmed programmed multiport multiport addresses, then it is forwarded accordingly. See “Using See “Using the Multiport Addresses” on page 65. 65.

•

The lower lower 10 bits of the the hashed index index key are are used as a pointer pointer into into the address address table table memory, memory, and the entry is retrieved.

•

If the valid indicator indicator is set set and the address address stored stored at one of the locations locations matches matches the index index key of the packet received, the forwarding field port ID is assigned to the destination port of the packet. – If the destination port matches the source port, the packet is i s not forwarded.

•

If the address address resolution resolution function function fails to return return a matching matching valid ARL entry entry and the unicast unicast DLF forward forward bit is set, the frame is forwarded according to the port map in the Unicast Lookup Failed Forward Map register.

•

Otherwise, Otherwise, the packet packet is flooded flooded to to all appropriat appropriate e ports. ports.


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BCM53128 Data Sheet

Address Management

See Table See Table 6 for 6 for definitions of the unicast index key and the assigned forwarding field. The forwarding field for a unic unicas astt pack packet et is the the port port ID cont contai aine ned d in the the matc matchi hing ng ARL ARL entr entry. y. See See Table 7 for for a desc descri ript ption ion of a unic unicas astt ARL ARL entry. Table 6: Unicast Unicast Forward Field Definiti Definitions ons EN_1QVLAN

Index Key

Forwarding Field

1

DA and VID

Port ID

0

DA

Port ID

Table 7: Address Address Table Entry for Unicast Unicast Address Address Field

Description

VID

VLAN ID associated with the MAC address.

VALID

1 = Entry is valid. 0 = Entry is empty.

STAT ST ATIC IC

1 = Entr Entry y is stat static ic—S —Sho houl uld d not not be aged aged out out and and is writ writte ten n and and upda update ted d by soft softwa ware re.. 0 = Entry is dynamically learned and aged.

AGE

1 = Entry has been accessed or learned since last aging process. 0 = Entry has not been accessed since last aging process.

TC

MACDA-based TC (only valid for static entries). See “Quality of Service” on page 34 for 34 for more information.

Reserved

–

Reserved

Only 00 is valid.

PORT PO RTID ID

Port Port iden identi tifi fier er.. The The port port asso associ ciat ated ed with with the the MAC MAC addr addres ess. s.

MAC MAC ADDR ADDRES ESS S

48-b 48-bit it MAC MAC addr addres ess. s.

Note: The Note: The fields described described in Table in Table 7 can 7 can be written using the ARL Table MAC/VID Entry N (N=0-3) register and the ARL Table Data Entry N (N = 0–3) register. Multicast ARL table entries are described in Table in Table 9 on page 61. 61.


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BCM53128 Data Sheet

Address Management

Multicast Addresses Frames containing a multicast destination address are assigned a forwarding field corresponding to multiple ports specified in a port map. Multicast frames are assigned a forwarding field corresponding to a multicast port map from the matching ARL entry (see “Address (see “Address Management” on page 57). 57). If no matching ARL entry is found, the packet is flooded to all appropriate ports. Listed below is the multicast address resolution algorithm: •

If the DA matches matches one of the globally globally assigned assigned reserved reserved addresses addresses between between 01-80-C 01-80-C2-002-00-00-00 00-00 and 0180-C2-00-00-2F, the packet is handled as described in Table in Table 10 on page 62. 62.

•

If the multiport multiport addressi addressing ng feature feature is enabled and the DA matches matches one one of the programmed programmed Multiport Multiport Addresses, then it i t is forwarded accordingly. See “Using See “Using the Multiport Addresses” on page 65. 65.

•

Otherwise, Otherwise, the the lower 10 bits bits of the hashed hashed index key key are used as a pointer pointer into into the ARL table table memory, memory, and the entry is retrieved.

•

If the valid indicator indicator is set, set, and the address address stored stored at the entry entry locations locations matches matches the index key of the the packet received, the forwarding field port map is assigned to the destination port of the packet.

•

If the address address resolution resolution function function fails fails to return return a matching valid valid ARL entry entry and the multicast multicast DLF forwar forward d bit is set (see “Address (see “Address Management” on page 57), 57), the frame is forwarded according to the port map in the Multicast Lookup Failed Forward Map register.

•

Otherwise, Otherwise, all all other multicast multicast and broadcas broadcastt packets are are flooded to all appropri appropriate ate ports. ports.

See Table See Table 8 for 8 for definitions of the multicast index key and the assigned forwarding field. The forwarding field for a multicast packet is the port map contained in the matching ARL entry. See Table See Table 9 for 9 for a description of a multicast ARL entry. See “Accessing See “Accessing the ARL Table Entries” on page 63 for 63 for more information. Table 8: Multicast Forward Forward Field Definitions Definitions EN_1QVLAN

Unicast/Multicast

Index Key

Forwarding Field

1

Unicast

DA and VID

Port ID

0

Unicast

DA

Port ID

1

Multicast

DA and VID

FWD_PRT_MAP

0

Multicast

DA

FWD_PRT_MAP

Table 9: Address Address Table Entry for Multicast Multicast Address Address Field

Description

VID

VLAN ID associated with the MAC address.

VALID

1 = Entry is valid. 0 = Entry is empty.

STAT STATIC IC

1 = Entr Entry y is stat static ic—T —Thi his s entr entry y is not not aged aged out out and and is writ writte ten n and and upda update ted d by soft softwa ware re.. 0 = Not defined.

AGE

The AGE bit is ignored for static ARL table entries.

TC

MACDA-based TC (only valid for static entries). See “Q “Qua uali lity ty of Se Serv rvice ice”” on pa page ge 34 for more more information.

Reserved

–


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BCM53128 Data Sheet

Address Management

Table 9: Address Address Table Entry for Multicast Multicast Address (Cont.) (Cont.) Field

Description

FWD_PRT_MAP Multicast forwarding mask. [8:0] 1 = Forwarding Forwarding enable. 0 = Forwarding disable. MAC ADDRESS ADDRESS 48-bit MAC address. address.

Note: The Note: The fields described in Table in Table 9 on page 61 can 61 can be written using the ARL Table MAC/VID Entry N (N = 0-3) register and the ARL Table Data Entry N (N = 0–3) register. Unicast ARL table entries are described in Table in Table 7 on page 60. 60.

Reserved Multicast Addresses Table 10 summarizes 10 summarizes the actions taken for specific reserved multicast addresses. Packets identified with these destination addresses are handled uniquely since they are designed for special functions. Bits[4:0] of the Reserved Multicast Control register program groups of these addresses to be dropped or forwarded. Writing to these bits can change the default action of Unmanaged mode summarized in the following table. Table 10: Behavior Behavior for Reserved Multicast Multicast Addresses Addresses IEEE 802.1 Unmanaged Specified Action Mode Mode Acti Action on

Mana Manage ged d Mode Mode Acti Action on

Bridge group address

Drop frame

Flood frame

Forward frame to IMP only

01-80-C2-00 01-80-C2-00-00-0 -00-01 1

IEEE 802.3x MAC control frame

Drop frame

Receive MAC Receive MAC determines determines if it is a if valid pause frame and valid pause frame acts accordingly. and then acts accordingly

01-80-C2-00-00-02

Reserved

Drop frame

Drop frame

Forward to frame management port only

01-80-C2-00 01-80-C2-00-00-0 -00-03 3

IEEE 802.1x portbased network access control

Drop frame

Drop frame

Forward frame to management port only

01-80-C2-00-00-04– Reserved 01-80-C2-00-00-0F

Drop frame

Drop frame

Forward frame to management port only

01-80-C2-00 01-80-C2-00-00-1 -00-10 0

For Forward ward fra frame

Floo Flood d fram rame

For Forward ard fram frame e to all all port ports s including management port

01-80-C2-00-00-11– Reserved 01-80-C2-00-00-1F

Forward frame

Flood frame

Forward frame to all ports excluding management port

01-8 01-800-C C2-00 2-00--00-2 00-20 0



For Forward ard fram frame e to all all port ports s excluding management port

MAC Address

Function

01-80-C2-00 01-80-C2-00-00-0 -00-00 0

All LANs bridge management group address

GMRP MRP addre ddress ss


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BCM53128 Data Sheet

Address Management

Table 10: Behavior for Reserved Multicast Addresses (Cont.) MAC Address

Function

IEEE 802.1 Unmanaged Specified Action Mode Mode Acti Action on

01-8 01-800-C C2-00 2-00--00-2 00-21 1

GVRP VRP addr addres ess s



For Forward ard fram frame e to all all port ports s excluding management port

Forward frame

Flood framea

Forward frame to all ports excluding management port

01-80-C2-00-00-22– Reserved 01-80-C2-00-00-2F a.

Mana Manage ged d Mode Mode Acti Action on

Frames Frames flood to all ports. ports. Certain Certain exclusions exclusions apply, apply, such as VLAN VLAN restrictio restrictions. ns.

Static Stati c Addres Address s Entri Entries es The BCM53128 supports static ARL table entries that are created and updated using one of the “Programming the “Programming Interfaces” on page 95. 95. These entries can contain either unicast or multicast destinations. The entries are created created by writing writing the entry location location using the Page 05h: ARL/VTBL ARL/VTBL Access registers and setting the STATIC bit. The AGE bit is ignored. Static entries do not automatically learn MAC addresses or port associations and are not aged out by the automatic automatic internal aging process. See “Writing See “Writing an ARL Entry” on page 63 for 63 for details.

Accessing the ARL Table Entries ARL table entries are accessed by one of two mechanisms. The first mechanism uses the ARL A RL read/write control, control, which allows an address-ent address-entry ry location to be read, modified, or written based on the value of a known MAC address. The second mechanism searches the ARL table sequentially, returning all valid entries.

Reading Read ing an ARL Entry To read an ARL entry: 1. Set the MAC address in the MAC Address Index register. register. 2. Set the VLAN ID in the VLAN ID Index register. register. This This is necessary only if the VID is used in the index key. 3. Set the ARL_R/W bit to 1 in the ARL Table Read/Write Control register. 4. Set the the STAR START/ T/DO DONE NE bit to 1 in the the ARL ARL Tabl Table e Read Read/W /Wri rite te Cont Contro roll regis registe ter. r. This This init initiat iates es the the read read oper operat ation ion.. The MAC address and VID are used to calculate the hashed index to the ARL table. The matching ARL entry is read. The contents of entry are stored in the ARL Table MAC/VID Entry N (N = 0-3) register and the ARL Table Data Entry N (N = 0–3) register. Entries that do not have the VALID bit set should be ignored. The contents of the MAC/VID registers must be compared against the known MAC address and VID. Entries that do not match may be a valid entry, but are not a valid match for the index key. All other read entries are considered valid ARL entries.

Writing an ARL Entry To write an ARL entry:


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BCM53128 Data Sheet

Address Management

1. Follow the the steps steps in “Reading in “Reading an ARL Entry” on page 63 to 63 to read the ARL entry matching the MAC address and VID that are written to the table. 2. Keep the values that remain from the previous read operation. • MAC Address Address Index register register • VLAN VLAN ID ID Inde Index x regi registe ster r • ARL Table Table MAC/VI MAC/VID D Entry Entry N (N (N = 0-3) 0-3) register register • ARL Table Table Data Data Entry Entry N (N = 0–3) regist register er 3. Modify the correct correct entry as necessary. necessary. Set the STATIC bit so that the entry is not aged out. 4. Set the ARL_R/W bit to 0 in the ARL Table Read/Write Control register. 5. Set the the START START/D /DON ONE E bit bit to 1 in the the ARL ARL Tabl Table e Read Read/W /Wri rite te Cont Contro roll regi regist ster er.. This This initi initiat ates es the the writ write e oper operat ation ion.. The MAC address and VID are used to calculate the hashed index to the ARL table.

Searching the ARL Table The The seco second nd meth method od to acce access ss the the ARL ARL table table is thro throug ugh h the the ARL ARL sear search ch cont contro rol. l. The The enti entire re ARL ARL tabl table e is sear search ched ed sequ sequen enti tiall ally, y, reve reveali aling ng each each valid valid ARL ARL entr entry. y. Sett Settin ing g the the Star Start/ t/Do Done ne bit in the the ARL ARL Table Table Sear Search ch Cont Contro roll regis registe ter r begi begins ns the the sear search ch from from the the top top of the the ARL ARL tabl table. e. This This bit bit is clea cleare red d when when the the sear search ch is comp comple lete te.. Duri During ng the the ARL ARL search, search, the Search Valid bit indicates when a found valid entry is available available in the ARL Table Search MAC/VID MAC/VID Result N (N = 0–1) register and the ARL Table Search Data Result N (N = 0–1) register. When the host reads the the cont conten ents ts of the the ARL ARL Tabl Table e Sear Search ch Data Data Resu Result lt 1 regi regist ster er whic which h locat located ed in Page Page 05h: 05h: Addr Addres ess s 78h, 78h, the the sear search ch process automatically continues to seek the next valid entry in the address table. Invalid address entries are skipped, providing the host with an efficient way of searching the entire address table. The ARL search and ARL read/write operations execute in parallel with other register accesses. This allows the host host proces processor sor to start start a read, read, write, write, or search search proces process s and then then read/w read/writ rite e other other regist registers ers,, return returning ing period periodica ically lly to see if the operation operation has completed. completed.

Address Aging The aging aging proces process s periodi periodical cally ly remove removes s dynami dynamicall cally y learne learned d addres addresses ses from from the ARL table. table. When When an ARL entry entry is learned or referenced, the AGE bit is set to 1. The aging process scans the ARL table at regular intervals, aging out entries not accessed accessed during the previous previous one to two aging intervals. intervals. The aging interval interval is programma programmable ble using the Aging Enable and AGE TIME bit in the Aging Time Control Control register. Entries that are written and updated using one of the “Programming the “Programming Interfaces” on page 95, 95, should have the STATIC bit set. Thus, they are not affected affected by the aging process. For each entry in the ARL table, the aging process performs performs the following: following: •

If the VALID VALID bit bit is not set, no further further action action is required required..

•

If the VALID VALID bit is set set and the STATIC STATIC is set, set, no further further action action is required. required.

•

If the VALID bit bit is set, the STATIC STATIC bit is not set, set, and the AGE bit is set, then then clear the AGE AGE bit. This keeps keeps the entry in the table, but marks it so that it is removed if it is not accessed before the subsequent aging scan.


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BCM53128 Data Sheet

•

Power Savings Modes

If the VALID bit bit is set, the STATIC STATIC bit is not set, set, and the AGE bit is reset, reset, then reset reset the VALID VALID bit. This effectively effectively deletes deletes the entry from the ARL table. The entry has been aged out.

Fast Aging The fast aging function can be enabled per port or VLAN ID: The port fast aging can be enabled by setting the Start/Done of the Fast-Aging Control register, the Fast Age All Ports bit of the Fast-Aging Port Control register, and the appropriate port bits in the Fast-Aging Port Control register. The VLAN ID fast aging can be enabled by setting the Start/Done of the Fast-Aging Control register, the Fast Age All VID bit of the Fast-Aging VID Control register, and the appropriate VLAN ID bits of the Fast-Aging VID Control register.

Using the Multiport Addresses The Multiport Address N (N = 0–5) register can be used to forward a given MAC address and Ether Type to multiple ports. Packets with a corresponding DA are forwarded to the port map contained in the Multiport Vector N (N = 0–5) register. These registers must be controlled using Multiport Control register. Note: The Note: The Multiport Address N (N = 0–5) register is the only mechanism for TS Protocol qualification for the BroadSync HD application. It can be enabled by Multiport Control register.

Power Savings Modes The BCM531 BCM53128 28 offers offers differ different ent power power savings savings modes modes for differ different ent operat operating ing states states.. All the power power saving saving scheme scheme are implemented without any external CPU requirement. The various power savings modes are: •

Auto Power Down Mode: Mode: This is a stand alone PHY feature which is enabled by a register register bit setting. The PHY shuts off the analog portion of the circuitry when cable is not connected or the link partner power is down.

•

Energy Efficient Efficient Ethernet (EEE) Mode: Mode: Energy Efficient Ethernet is IEEE802.1az, an extension of the IEEE802.3 IEEE802.3 standard. standard. IEEE defines defines support support for the PHY to operate in Low Power Idle (LPI) mode. When enabled, enabled, this mode supports supports QUIET QUIET times during low link utilization, utilization, allowing allowing the both sides of link to disable portions of each PHY's operating circuitry and save power.

•

Short Cable Cable Mode (Green Mode): Mode): This mode requires the CPU to run the cable diagnostics, and the CPU enables power savings mode based on the cable length measurement result.

•

Deep Green Mode: Mode: This mode also requires the CPU to recognize the long period power down time and shut off the PHY power and the PLL to the PHY core. The BCM53128 enters normal operation and establishes a link when a signal is detected at the PHY input.


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BCM53128 Data Sheet

Power Savings Modes

Auto Power Down Mode Auto Power Down mode saves PHY power consumption while the link is down. When the user enables the Auto Power Down mode through a PHY register bit setting, the PHY goes into the power savings mode automatically whenever it is in linkdown state. During the Power Down state, the PHY wakes up every 2.7 or 5.4 seconds, depending on the register settings, and checks for a link signal. If no link signal is detected, then the PHY goes back to Power Down state, or the PHY wakes up and resumes the link process. Automatic Power Down mode applies to the following conditions: 1. Cable is plugged plugged in, but the link partner is shut down (for (for example, example, when a PC is off), so the port is in link down state. 2. Cable is unplugged, unplugged, so the port is in link down state.

Energy Efficient Ethernet Mode Energy Efficient Ethernet power savings mode saves PHY consumption while the link is up but when extended idle periods may exist between packet traffic. In EEE power savings mode PHY power consumption is scalable to the actual bandwidth utilization. The PHY can go in to “Quiet” mode (low-power idle mode) when there is no data data to be tran transm smit itte ted. d. This This feat featur ure e is base based d on the the late latest st IEEE IEEE 802. 802.3a 3az z stan standa dard rd.. The The EE EEE E supp suppor orti ting ng capa capabil bilit ity y of the link partner is a must for this feature to work, and the discovery of the capability is during auto-negotiation through Link Layer Discovery Protocol (LLDP). This EEE feature is an embedded PHY feature and no external CPU is required. In this this mode mode,, the the MAC MAC dete determ rmin ines es when when to ente enterr low powe powerr mode mode by exam examin ining ing the the stat state e of the the tran transm smit it queu queues es associated with each MAC. Four simple adjustments (settings) are used to trigger (optimize) the behavior of EEE control policy. These adjustments are: •

Global Buffer Buffer occupancy occupancy threshold threshold

•

Two-pa Two-part rt sleep sleep delay delay time timer r

•

Minimum Minimum low-power low-power idle duration duration timer

•

Wake Wake transit transition ion timer timer

The two-way communication between the PHY and its link partner is required for the PHY to achieve the power savings on both sides. The transmit PHY sends a sleep symbol to the link partner, and the link partner enters low power state. When the transmit PHY sends a wake symbol, the regular packet transfer mode resumes. For details on how the mode works and how to set up the conditions, please refer to the Layout the Layout and Design Guide (document number 53128-AN1xx-R).

Short Cable Mode (Green Mode) The Short Cable Power Savings mode (called (called Green mode) requires requires a CPU. In the BCM53128, BCM53128, a dedicated dedicated embedded 8051 processor is used to implement this feature. Software running in the 8051 triggers the cable diagnostic routine on a schedule programmed by the user (for example, upon every power up or every new linkup). The diagnostic routine routine obtains obtains the length length of the cable connected connected to the port. Then, the CPU reduces the PHY PHY rece receiv iver er powe powerr base based d on the the meas measur ured ed cabl cable e lengt length. h. It is for for the the Giga Giga link link only only and and the the maxi maximu mum m supp suppor orte ted d cable length is 30m.


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BCM53128 Data Sheet

Power Savings Modes

Deep Green Mode The Deep Green Power Savings mode is a step deeper than the Auto Power Down Power Savings mode. The Deep Green Power Savings mode can be enabled through the internal 8051 microcontroller by setting the En_Green strap pin high. The Auto Power Down Power Savings mode is per port, but the Deep Green Power Savings mode is per PHY core base with a common PLL. When the ports that are sharing a PLL are linked down, the Auto Power Down mode is enabled (Register (Register Page 10h – 17h, Address 38h, Shadow 01010b), 01010b), and the DLL Auto Power-Down mode is enabled (Register Page 10h – 17h, Address 38h, Shadow 00101b), then the PHYs enter the Deep Green Power Savings mode. In this mode, all the PHY circuits are powered down except the energy detection circuit, and the energy detection circuit constantly monitors the energy on the line. Upon signal energy detection, detection, the BCM53128 BCM53128 enters normal operation operation and establishes establishes a link if energy is detected. The Deep Green Power Savings mode is most effective when the user expects no activities on the line for a long period of time.


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BCM53128 Data Sheet

System Functional Blocks

S e c ti t i o n 3 : S y s te t e m F u n c ti ti o n a l B l o c k s Overview of System Functional Blocks The BCM53128 include the following blocks: •

“Media Access Controller”

•

“Integrated 10/100/1000 PHY” on page 70

•

“Frame Management” on page 79

•

“MIB Engine Engine”” on page 83 83

•

“Integrated High-Performance High-Performance Memory” Memory” on page 90

•

“Switch Controller” Controller” on page 90

Each of these is discussed in more detail in the following sections.

Media Access Controller The BCM53128 contains six 10/100/1000 GMACs, and one MAC. The MAC automatically selects the appropriate speed (CSMA/CD or full-duplex) based on the PHY autonegotiation result. In full-duplex mode, IEEE 802.3x PAUSE frame-based flow control is also determined through auto-negotiation. The MAC is IEEE 802.3-, IEEE 802.3u-, and IEEE 802.3x-compliant.

Receive Function The MAC initiat initiates es frame frame recept reception ion follow following ing the assert assertion ion of receiv receive e data data valid valid indicat indication ion from from the physic physical al layer. layer. The MAC monitors the frame for the following error conditions: •

Receive Receive error error indication indication from the PHY

•

Runt frame frame error if frame frame is fewer than 64 64 bytes bytes

•

CRC CRC erro error r

•

Long frame frame error if frame frame is greater greater than the standard standard maximum maximum frame frame size or 9,720 9,720 bytes for jumbojumboenabled ports. Note: Fram Frames es long longer er than than stan standa dard rd max max fram frame e size size whic which h conf config igur ured ed using using Stan Standa dard rd Max Max Fram Frame e Size Size regist register er are consid considere ered d oversi oversized zed frames frames.. When When jumbojumbo-fra frame me mode mode is enable enabled, d, only only the frames frames longer longer than 9,720 bytes are bad frames and dropped.

If no errors are detected, the frame is processed by the switch controller. Frames with errors are discarded. Receive functions can be disabled by writing to Port Traffic Control register.


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BCM53128 Data Sheet

Media Access Controller

Transmit Function Frame transmission begins with the switch controller queuing a frame to the MAC transmitter. The frame data is transmitted as received from the switch controller. The transmit controller is responsible for preamble insertion, carrier deferral, collision backoff, and inter-packet gap enforcement. In 10/100 Mbps half-duplex mode, when a frame is queued for transmission, the transmit controller behaves as specified by the IEEE 802.3 requirements for frame deferral. Following deferral, the transmitter adds 8 bytes of preamb preamble le and SFD to the frame frame data data receive received d from from the switch switch contro controlle ller. r. If, during during frame frame transm transmiss ission ion,, a collis collision ion is observ observed ed and the collisi collision on window window timer timer has not expire expired, d, the transm transmit it contro controller ller assert asserts s jam and then then execut executes es the backoff algorithm. The frame is retransmitted when appropriate. On the 16th consecutive collision, the backoff algorithm starts over at the initial state, the collision counter is reset and attempts to transmit the current frame continue. Following a late collision, the frame is aborted, and the switch controller is allowed to queue the next frame for transmission. While in full-duplex mode, the transmit controller ignores carrier activity and collision indication. Transmission begins after the switch controller queues the frame, and the 96-bit times of IPG have been observed. Transmit functions can be disabled by writing to Port Traffic Control register.

Flow Control The BCM53128 implement an intelligent flow-control algorithm to minimize the system impact resulting from traffic congestion. Buffer memory allocation is adaptive to the status of each port’s speed and duplex mode, providing an optimal balance between flow management and per-port memory depth. The BCM53128 initiate flow control in response to buffer memory conditions on a per-port basis. The MACs are capable capable of flow control in both full-and full-and half-duplex half-duplex modes.

10/100 Mbps Half-Duplex In 10/100 half-duplex mode, the MAC back-pressures a receiving port by transmitting a 96-bit time jam packet to the port. A single jam packet is asserted for each received packet for the duration of the time the port is in the flow-control state.

10/100/1000 Mbps Full-Duplex Flow control in full-duplex mode functions as specified by the IEEE 802.3x requirements. In the receiver, MAC flowflow-con contro troll frames frames are recogn recognize ized d and, and, when when proper properly ly receive received, d, set the flow-c flow-cont ontrol rol pause pause time time for the transm transmit it cont contro roll ller er.. The The paus pause e time time is assi assign gned ed from from the the 2-by 2-byte te paus pause e time time fiel field d foll follow owin ing g the the paus pause e opco opcode de.. MAC MAC cont contro roll PAUSE frames are not forwarded from the receiver to the switch controller. When the switch controller requests flow control, the transmit controller transmits a MAC control PAUSE frame with the pause time set to maximum. When the condition that caused the flow control state is no longer present, a second MAC control PAUSE frame is sent with the pause time field set to 0. The The flow flow cont contro roll capa capabi bilit lities ies of the the BCM5 BCM531 3128 28 are are enab enable led d base based d on the the resu result lts s of auto auto-n -neg egot otiat iatio ion n and and the the stat state e of the ENFDXFLOW and ENHDXFLOW control signals loaded during reset. Flow control in half-duplex mode is independent of the state of the link partner flow control (IEEE 802.3x) capability. See Table 11 for 11 for detailed information.


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BCM53128 Data Sheet

Integrated 10/100/1000 PHY

Table 11: Flow Control Control Modes Modes Link Partner Flow Control (IEEE Control Input 802.3x) ENFDXFLOW

Control Input ENHDXFLOW

Auto-negotiated Link Speed

Flow Control Mode

X

X

0

Half-duplex

Disabled

X

X

1

Half-duplex

Jam pattern

0

0

X

Full-duplex

Disabled

0

1

X

Full-duplex

Disabled

1

0

X

Full-duplex

Disabled

1

1

X

Full-duplex

IEEE 802.3x flow control

Integrated 10/100/1000 PHY There are eight integrated PHY blocks in the BCM53128. BCM53128. For more information information see “Copper see “Copper Interface” on page 92. 92. The following sections describe the operations of the internal PHY block.

Encoder Ther There e are are eigh eightt inte integr grat ated ed PHY PHY block blocks s in the the BCM5 BCM531 3128 28.. The The PHY PHY is the the Ethe Ethern rnet et tran transc scei eive verr that that appr approp opri riat atel ely y processes data presented by the MAC into an analog data stream to be transmitted at the MDI interface, which performs performs the reverse process on data received received at the MDI interface. interface. The registers of the PHY are read using the “Programming the “Programming Interfaces” on page 95. 95 . The following sections describe the operations of the internal PHY block. For more information, see “Copper see “Copper Interface” on page 92. 92 . In 10BASE-T mode, Manchester encoding is performed on the data stream that is transmitted on the twistedpair cable. The multimode transmit digital-to-analog converter (DAC) performs preequalization for 100m of Category 3 cabling. In 100BASE-TX mode, the BCM53128 transmits a continuous data stream over the twisted-pair cable. The transmit packet is encapsulated by replacing the first two nibbles of preamble with a start-of-stream delimiter (/ J/K codes) and appending an end-of-stream delimiter (/T/R codes) to the end of the packet. The transmitter repeatedly sends the idle code group between packets. The encoded data stream is serialized and then scrambled by the stream cipher block, as described in “Stream in “Stream Cipher” on page 73. 73 . The scrambled data is then encoded into MLT3 signal levels.


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BCM53128 Data Sheet


In 1000BASE-T mode, the BCM53128 simultaneously transmits and receives a continuous data stream on all 4 pairs of the Category Category 5 cable. Byte-wide Byte-wide data from the transmit transmit data pins is scrambled when the transmit transmit enable is asserted, and the trellis (a PAM5 symbol on each of the four twisted-pairs) is encoded into a fourdimensional code group and then inserted into the transmit data stream. The transmit packet is encapsulated by replacing the first 2 bytes of the preamble with a start-of-stream delimiter, and appending an end-of-stream delimiter to the end of the packet. When the transmit error input is asserted during a packet transmission, a tran transm smit it erro errorr code code grou group p is sent sent in plac place e of the the corr corres espo pond nding ing data data code code grou group. p. The The tran transm smit itte terr send sends s idle idle code code groups or carrier extend code groups between packets. Carrier extension is used by the MAC to separate packets within a multiple-packet burst and is indicated by asserting the transmit error signal and placing 0Fh on the transmit transmit data pins while the transmit transmit enable is low. A carrier carrier extend error is indicated indicated by replacing replacing the transmit data input with 1Fh during carrier extension. The encoding complies with IEEE standard IEEE 802.3ab and is fully compatible with previous versions of the Broadcom 1000BASE-T PHYs.

Decoder In 10BASE-T mode, Manchester decoding is performed on the data stream. In 100BASE-TX mode, following equalization and clock recovery, the receive data stream is converted from MLT3 to serial nonreturn-to-zero (NRZ) data. The NRZ data is descrambled by the stream cipher block, as described later in this document. The descrambled data is then deserialized and aligned into 5-bit code groups. The 5-bit code groups are decoded into 4-bit data nibbles. The start-of-stream delimiter is replaced with preamble preamble nibbles, and the end-of-str end-of-stream eam delimiter and idle codes are replaced with 0h. The decoded data is driv driven en onto onto the the MII MII rece receiv ive e data data pins. pins. When When an inva invali lid d code code grou group p is dete detect cted ed in the the data data stre stream am,, the the BCM5 BCM531 3128 28 asserts the MII receive error (RX_ER) signal. RX_ER is also asserted when the link fails, or when the descrambler loses lock during packet reception. In 1000BASE-T mode, the receive data stream is: •

Passed Passed thro through ugh the Viterb Viterbii decod decoder er

•

Desc Descra ramb mbled led

•

Translated Translated back into byte-wide byte-wide data

The start-of-stream delimiter is replaced with preamble bytes, and the end-of-stream delimiter and idle codes are replaced with 00h. Carrier extend codes are replaced with 0Fh or 1Fh. Decoding complies with IEEE standard IEEE 802.3ab and is fully compatible with previous versions of Broadcom 1000BASE-T PHYs.

Link Monitor In 10BASE-T mode, a link-pulse detection circuit constantly monitors the TRD pins for the presence of valid link pulses. In 100BASE-TX mode, receive receive signal energy is detected by monitoring monitoring the receive pair for transitions transitions in the signal level. Signal levels are qualified using squelch detect circuits. When no signal is detected on the receive pair, the link monitor monitor enters the Link Fail state and the transmissi transmission on and reception reception of data packets is disabled. When a valid signal is detected on the receive pair for a minimum of 1 ms, the link monitor enters the Link Pass state, and the transmit and receive functions are enabled.


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BCM53128 Data Sheet


Following auto-negotiation in 1000BASE-T mode, the master transceiver begins sending data on the media. The slave transceiver also begins transmitting when it has recovered the master transceiver’s timing. Each end of the link continuously continuously monitors monitors its local receiver status. When the local receiver receiver status has been good for at least 1 microsecond microsecond,, the link monitor enters the Link Pass state, and the transmissio transmission n and reception reception of data packets are enabled. When the local receiver status is bad for more than 750 ms, the link monitor enters the Link Fail state and the transmission and reception of data packets are disabled.

Digital Adaptive Equalizer The digital adaptive equalizer removes intersymbol interference (ISI) created by the transmission channel media. The equalizer accepts sampled unequalized data from the analog-to-digital converter (ADC) on each channel and produces equalized data. The BCM53128 achieves an optimum signal-to-noise ratio by using a combination of feed forward equalization (FFE) and decision feedback equalization (DFE) techniques. Under harsh noise environments, environments, these powerful powerful techniques achieve a bit error rate (BER) of less than 1 x 10 –12 for transmissions up to 100m on Category 5 twisted-pair cabling (100m on Category 3 UTP cable for 10BASE-T mode). The all-digital nature of the design makes the performance very tolerant to noise. The filter coefficients are self-adapting to accommodate varying conditions of cable quality and cable length.

Echo Canceler Beca Becaus use e of the the bidir bidirec ecti tion onal al natu nature re of the the chan channe nell in 1000 1000BA BASE SE-T -T mode mode,, an echo echo impa impair irme ment nt is caus caused ed by each each transmitter. The output of the echo filter is added to the FFE output to remove the transmitted signal impairment from the incoming receive signal. The echo canceler coefficients are self-adapting to manage the varying echo impulse responses caused by different channels, transmitters, and environmental conditions.

Cross Talk Canceler The BCM53128 transmits transmits and receives a continuous continuous data stream on four channels. channels. For a given channel, channel, the sign signal als s sent sent by the the othe otherr thre three e loca locall tran transm smit itte ters rs caus cause e impa impair irme ment nts s on the the rece receiv ived ed sign signal al beca becaus use e of near near-e -end nd crosstalk (NEXT) between the pairs. It is possible to cancel the effect because each receiver has access to the data for the other three pairs that cause this interference. The output of the adaptive NEXT canceling filters is added to the FFE output to cancel the NEXT impairment.

Analog-to-Digital Converter Each receive channel has its own 125-MHz analog-to-digital converter (ADC) that samples the incoming data on the receiv receive e channe channell and feeds feeds the output output to the digita digitall adapti adaptive ve equali equalizer zer.. Advanc Advanced ed analog analog circui circuitt techni technique ques s achieve the following results: •

Low Low offs offset et

•

High power-supp power-supply ly noise rejection rejection

•

Fast Fast settli settling ng time time

•

Low Low bit bit erro errorr rate rate


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BCM53128 Data Sheet


Clock Recovery/Generator The clock clock recove recovery ry and genera generator tor block block create creates s the transm transmit it and receiv receive e clocks clocks for 1000BA 1000BASESE-T, T, 100BASE 100BASE-TX -TX,, and 10BASE-T operation. In 10BASE-T or 100BASE-TX 100BASE-TX mode, the transmit transmit clock is locked to the 25-MHz 25-MHz crystal crystal input, and the receive clock is locked to the incoming incoming data stream. stream. In 1000BASE-T mode, the two ends of the link perform loop timing. One end of the link is configured as the master, and the other is configured as the slave. The master transmit and receive clocks are locked to the 25MHz crystal input. The slave transmit and receive clocks are locked to the incoming receive data stream. Loop timing allows for the cancellation of echo and NEXT impairments by ensuring that the transmitter and receiver at each end of the link are operating at the same frequency.

Baseline Wander Correction 1000BASE-T and 100BASE-TX data streams are not always DC-balanced. Because the receive signal must pass through a transformer, the DC offset of the differential receive input can vary with data content. This effect, which is known as baseline wander, can greatly reduce the noise immunity of the receiver. The BCM53128 automatically compensates for baseline wander by removing the DC offset from the input signal, thereby significantly reducing the probability of a receive symbol error. In 10BASE-T mode, baseline wander correction is not performed because the Manchester coding provides a perfect DC balance.

Multimode TX Digital-to-Analog Converter The multimode transmit digital-to-analog converter (DAC) transmits PAM5, MLT3, and Manchester coded symbols. The transmit DAC performs signal wave shaping that decreases the unwanted high frequency signal components, reducing electromagnetic interference (EMI). The transmit DAC uses a voltage driven output with internal terminations and hence, does not require external components or magnetic supply for operation thus reducing system complexity for routing and bill of materials.

Stream Cipher In 1000BASE-T and 100BASE-TX modes, the transmit data stream is scrambled to reduce radiated emissions and to ensure that there are adequate transitions within the data stream. The 1000BASE-T scrambler also ensures ensures that there is no correlation correlation among symbols on the four different different wire pairs and in the transmit transmit and receiv receive e data data stream streams. s. The scramb scrambler ler reduce reduces s peak peak emissi emissions ons by random randomly ly spread spreading ing the signal signal energy energy over over the transmit frequency range and eliminating peaks at certain frequencies. The randomization of the data stream also also assist assists s the digital digital adapti adaptive ve equali equalizer zers s and echo/c echo/cros rossta stalk lk cancel cancelers ers.. The algori algorithm thms s in these these circui circuits ts requir require e there to be no sequential or cross-channel correlation among symbols in the various data streams. In 100BASE-TX mode, the transmit data stream is scrambled by exclusive ORing the encoded serial data stream. stream. This is done with the output of an 11-bit wide linear feedback feedback shift register (LFSR), (LFSR), producing a 2047bit nonrepeating sequence.


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BCM53128 Data Sheet


In 1000BASE-T mode, the transmit data stream is scrambled by exclusive ORing the input data byte with an 8bit wide cipher text word. The cipher text word generates each symbol period from eight uncorrelated maximal length data sequences that are produced by linear remapping of the output of a 33-bit wide LFSR. After the scrambled scrambled data bytes are encoded, the sign of each transmitte transmitted d symbol is again randomized randomized by a 4-bit wide cipher text word that is generated in the same manner as the 8-bit word. The master and slave transmitters use different scrambler sequences to generate the cipher text words. For repeater or switch applications, where all ports can transmit the same data simultaneously, signal energy is randomized further by using a unique seed to initialize the scrambler sequence for each PHY. The receiver descrambles the incoming data stream by exclusive ORing it with the same sequence generated at the transmitter. The descrambler detects the state of the transmit LFSR by looking for a sequence representing consecutive idle code groups. The descrambler locks to the scrambler state after detecting a suffic sufficien ientt number number of consec consecuti utive ve idle idle codes. codes. The BCM531 BCM53128 28 enable enables s transm transmiss ission ion and recept reception ion of packet packet data data only when the descrambler descrambler is locked. The receiver receiver continually monitors monitors the input data stream to ensure ensure that it has not lost synchronization by checking that inter-packet gaps containing idles or frame extensions are received at expected intervals. When the BCM53128 detects loss of synchronization, it notifies the remote PHY of the inability to receive packets (1000BASE-T mode only) and attempts to resynchronize to the received data stream. stream. If the descrambler descrambler is unable to resynchronize resynchronize for a period of 750 ms, the BCM53128 is forced forced into the Link Fail state. In 10BASE-T mode, scrambling is not required to reduce radiated emissions.

Wire Map and Pair Skew Correction During 1000BASE-T operation, the BCM53128 has the ability to automatically detect and correct some UTP cable wiring errors. The symbol decoder detects and compensates for (internal to the BCM53128) the following errors: •

Wiring error errors s caused caused by the swappi swapping ng of pairs pairs within within the UTP UTP cable. cable.

•

Polarity Polarity errors errors caused caused by the swappi swapping ng of wires wires within within a pair. pair.

The BCM53128 also automatically compensates for differences in the arrival times of symbols on the four pairs of the UTP cable. The varying arrival times are caused by differing propagation delays (commonly referred to as delay skew) between the wire pairs. The BCM53128 can tolerate delay skews of up to 64 ns long. Autonegotiation must be enabled to take advantage of the wire map correction. During 10/100 Mbps operation, pair swaps are corrected. Delay skew is not an issue though, because only one pair of wires is used in each direction.

Automatic Auto matic MDI Crosso Crossover ver During During copper auto-negotiation auto-negotiation,, one end of the link needs to perform an MDI crossover crossover so that each transceiver’s transmitter is connected to the other receiver. The BCM53128 can perform an automatic mediadependent interface (MDI) crossover, eliminating the need for crossover cables or cross-wired (MDIX) ports. During auto-negotiation, the BCM53128 normally transmits and receives on the TRD pins. When When connec connectin ting g to anothe anotherr device device that that does does not perfor perform m MDI crosso crossover ver,, the BCM531 BCM53128 28 automa automatic tically ally switch switches es its TRD in pairs when necessary to communicate with the remote device. When connecting to another device that does have MDI crossover capability, an algorithm determines which end performs the crossover function.


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BCM53128 Data Sheet


During 1000BASE-T operation, the BCM53128 swaps the transmit symbols on pairs 0 and 1 and pairs 2 and 3 if auto-negotiation completes in the MDI crossover state. The 1000BASE-T receiver automatically detects pair swaps on the receive inputs and aligns the symbols properly within the decoder. The automatic MDI crossover function cannot be disabled when in 1000BASE-T mode. During 10BASE-TX and 100BASE-T operation, pair swaps automatically occur within the device and do not require user intervention. The automatic MDI crossover function by default only works when auto-negotiation is enabled. This function can be disabled during autonegotiation negotiation by writing 1 to bit 14 of the PHY Extended Control register. register. Note: This Note: This function only operates when the copper auto-negotiation is enabled.

10/100BASE-TX Forced Mode Auto-MDIX The automatic MDI crossover function can also be enabled when in forced 10BASE-T or forced 100BASE-TX mode. This feature allows the user to disable the copper auto-negotiation in either 10BASE-T or 100BASE-TX and still take advantage of the automatic MDI crossover function. Whenever the forced link is down for at least 4 seconds, then auto-negotiation is internally enabled with its automatic MDI crossover function until link pulses or 100Tx idles are detected. Once detected, the PHY returns to forced mode operation. The user should set the same speed in register 0 and the auto-negotiation advertisement register 4. Note: This Note: This function only operates when the copper auto-negotiation is disabled.

Resetting the PHY The BCM53128 provides provides a hardware hardware reset pin, RESET, which resets resets all internal nodes to a known state. state. Hardware reset is accomplished by holding the RESET pin low for at least 1 ms. Once RESET is brought high, the PHY will complete its reset sequence within 5 ms. All outputs will be inactive until the PHY has completed its reset sequence. The PHY will keep the inputs inactive for 5 ms after the deassertion of hardware reset. The hardware hardware configuration configuration pins and the PHY address address pins will be read on the deassertion deassertion of hardware hardware reset. The BCM53128 also has a software reset capability. To enable the software reset, a 1 must be written to the bit. This bit is self-clearing, meaning that a second write operation is not necessary to end the reset. There is no effect if 0 is written to this bit. Mode pins that are labelled sample on reset (SOR) are latched during hardware reset. Similarly, software resets also latch new values for the SOR mode pins.


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BCM53128 Data Sheet


PHY Address The BCM53128 has eight unique PHY addresses for MII management of the internal PHYs. The PHY addresses for each port are as follows, •

PHY addres address s for for Port Port 0 is 0

•


•


•


•


•


•


•


Super Isolate Mode When in Super Isolate mode, the transmit and receive functions on the Copper Media Dependent Interface are disabled (No link will be established with the PHY’s copper link partner). Any data received from the switch will be ignored by the BCM53128 and no data will be sent from the BCM53128.

Standby Power-Down Mode The The BCM5 BCM531 3128 28 can can be place placed d into into stan standb dby y powe powerr-do down wn mode mode using using soft softwa ware re comm comman ands ds.. In this this mode mode,, all all PHY PHY functions except for the serial management interface are disabled. To enter standby power-down mode, set MII Control register (Page 10h–17h: Address 00h), bit 11 = 1. There are three ways to exit standby power-down mode: •

Clear MII Contro Controll register register (addre (address ss 00h), 00h), bit 11 = 0.

•

Set the softwa software re RESET bit bit 15, MII Contro Controll register register (Page 10h–17h 10h–17h:: Address Address 00h).

•

Assert Assert the hardwa hardware re RESE RESET T pin. pin.

Read or write operations to any MII register, register, other than MII Control Control register, register, while the device is in the standby power-down mode returns unpredictable results. Upon exiting standby power-down mode, the BCM53128 remains remains in an internal reset state for 40 µs and then resumes normal operation. operation.


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BCM53128 Data Sheet


Auto Power-Down Mode The BCM53128 can be placed into auto power-down mode. Auto power-down mode reduces device power when the signal from the copper link partner is not present. The auto power-down mode works whether the device is in Auto-negoti Auto-negotiation ation Enabled or Forced mode. This mode is enabled enabled by setting setting bit 5 =1 of Auto PowerDown register. When auto power-down mode is enabled, the BCM53128 automatically enters the low-power mode when energy on the line is lost, and it resumes normal operation when energy is detected. When the BCM5 BCM531 3128 28 is in auto auto powe powerr-do down wn mode mode,, it wake wakes s up afte afterr 2.7s 2.7s or 5.4s 5.4s,, whic which h dete determ rmin ined ed by bit 4 of Auto Auto Powe PowerrDown register, and sends link pulses while monitoring for energy from the link partner. The BCM53128 enters normal operation and establishes a link if energy is detected, otherwise the wake-up mode continues for a duration of 84 ms to 1260 ms. This is determined by the timer bits [3:0] of Auto Power-Down register. before going back to low-power mode.

External Loopback Mode The External Loopback mode allows in-circuit testing of the BCM53128 as well as the transmit path through the magnetics and the RJ-45 connector. External loopback can be performed with and without a jumper block. External loopback with a jumper block tests the path through the magnetics and RJ-45 connector. External loopback without the jumper block only tests the BCM53128’s transmit and receive circuitry. In 1000BASE-T, 100BASE-TX, 100BASE-TX, and 10BASE-T modes, a jumper jumper block must be inserted into the RJ-45 connector connector to support support external loopback. The jumper block should have the following RJ-45 pins connected together: 1------------3 2------------6 4------------7 5------------8 Table 12 to Ta Tabl ble e 17 on pa page ge 78 descri describe be how the extern external al loopba loopback ck is enabled enabled for 1000BAS 1000BASE-T E-T,, 100BASE 100BASE-TX -TX,, and 10BASE-T modes with and without without a jumper jumper block. Table 12: 1000BASE-T External External Loopback with External Loopback Plug Register Writes

Comments

Write Write 1800h 1800h to 1000BA 1000BASESE-T T Contro Controll regist register er

Enable Enable 1000BA 1000BASESE-T T Master Master Mode Mode

Write ite 0040h to MII Control regist ister

Enable Force 1000BASE-T E-T

Writ Write e 8400 8400h h to Auxi Auxilia liary ry Cont Contro roll regis registe terr

Enab Enable le Exte Extern rnal al Loop Loopba back ck Mode Mode with with exte extern rnal al loop loopba back ck plug

Table 13: 1000BASE-T External External Loopback Without External External Loopback Plug Register Writes

Comments

Write Write 1800h 1800h to 1000BA 1000BASESE-T T Contro Controll regist register er

Enable Enable 1000BA 1000BASESE-T T Master Master Mode Mode

Write ite 0040h to MII Control regist ister

Enable Force 1000BASE-T


Enab Enable le Exte Extern rnal al Loop Loopba back ck Mode Mode


Enab Enable le Exte Extern rnal al Loop Loopba back ck Mode Mode with withou outt exte extern rnal al loop loopba back ck plug


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BCM53128 Data Sheet


Table 14: 100BASE-TX External External Loopback with External External Loopback Plug Register Writes

Comments

Writ Write e 2100 2100h h to MII Cont ontrol rol regis egiste terr

Enab Enable le For Force 100B 100BAS ASEE-TX TX full full-d -dup uple lex x mode ode

Table 15: 100BASE-TX External Loopback Without External External Loopback Plug Register Writes

Comment


Enab Enable le Forc Force e 100B 100BAS ASEE-TX TX fullull-du dupl plex ex mode ode


Enab Enable le exte extern rnal al loop loopba back ck mode mode with withou outt exte extern rnal al loop loopba back ck plug

Table 16: 10BASE-T External External Loopback with External Loopback Plug Register Writes

Comments


Enab Enable le For Force 10BA 10BASE SE-T -T full full-d -dup uple lex x mode mode

Table 17: 10BASE-T External External Loopback Without External Loopback Plug Register Writes

Comments


Enab Enable le Forc Force e 10BA 10BASE SE-T -T full full--dupl duplex ex mode ode


Enab Enable le exte extern rnal al loop loopba back ck mode mode with withou outt exte extern rnal al loopb loopbac ack k plug

Note: To Note: To exit the External Loopback mode, a software or hardware reset is recommended.

Full-Duplex Mode The BCM53128 supports full-duplex operation. While in full-duplex mode, a transceiver can simultaneously transmit and receive packets on the cable.

Copper Mode When auto-negotiation is disabled, full-duplex operation can be enabled by setting bit 8 of MII Control register. When auto-negotiation is enabled, the full-duplex capability is advertised for: •

10BASE-T 10BASE-T when bit 6 of of Auto-Negotia Auto-Negotiation tion Advertis Advertisement ement regist register er is set.

•

100BASE-T 100BASE-T when bit bit 8 Auto-Negotia Auto-Negotiation tion Advertis Advertisement ement regist register er is set.

•

1000BASE-T 1000BASE-T when when bit 9 of of 1000BASE-T 1000BASE-T Contro Controll register register is set. set.


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BCM53128 Data Sheet

Frame Management

Master/Slave Configuration In 1000BASE-T mode, the BCM53128 and its link partner perform loop timing. One end of the link must be configured as the timing master, and the other end as the slave. Master/slave configuration is performed by the auto-n auto-nego egotia tiatio tion n functi function. on. The auto-n auto-nego egotia tiatio tion n functi function on first first looks looks at the manual manual master master/sl /slave ave config configura uratio tion n bits bits advertised by the local PHY and the link partner. If neither PHY requests manual configuration, then the autonegotiation function looks at the advertised repeater/DTE settings. If one PHY is advertised as a repeater port and the other is advertised advertised as a DTE port, then the repeater port is configured as the master and the DTE port as the slave. Each end generates an 11-bit random seed if the two settings are equal, and the end with the higher seed is configured as the master. If the local PHY and the link partner generate the same random seed, then auto-negotiation is restarted. If both both ends ends of the the link link atte attemp mptt to forc force e the the same same manu manual al conf configu igura rati tion on (bot (both h mast master er or both both slav slave) e),, or the the rand random om seeds match seven consecutive times, then the BCM53128 sets the Master/Slave Configuration Fault bit in the 1000BASE-T Status register, and auto-negotiation is restarted. This is used to set the BCM53128 to manual master/slave configuration or to set the advertised repeater/DTE configuration.

Next Page Exchange The 1000BASE-T configuration requires the exchange of three auto-negotiation next pages between the BCM53128 and its link partner. Exchange of 1000BASE-T Next Page information takes place automatically when the BCM53128 is configured to advertise 1000BASE-T capability. The BCM53128 also supports software controlled Next Page exchanges. This includes the three 1000BASE-T Next Next Pages, Pages, which which are always always sent sent first. first. The BCM531 BCM53128 28 automa automatic tically ally genera generates tes the approp appropria riate te messag message e code code field for the 1000BASE-T pages. When the BCM53128 is not configured to advertise 1000BASE-T capability, the 1000BASE-T Next Pages are not sent. When the BCM53128 is not configured to advertise 1000BASE-T capability and bit 15 of the Auto-Negotiation Advertisement register is set, the BCM53128 does not advertise Next Page ability.

Frame Managem Management ent The BCM53128 provides a Frame Management block that works in conjunction with one of the GMII ports operate in IMP mode as the full duplex packet streaming interface to the external CPU, with in-band messaging mechanism for management purpose.

In-Band Management Port The GMII port can be configured as the management port, using the Frame Management Port bits in the Global Manage Managemen mentt Config Configura uratio tion n regist register. er. When When the GMII GMII port port is define defined d as the Frame Frame Manage Managemen mentt Port, Port, it is referr referred ed to as the in-band management port (IMP). The IMP can be used as a full-duplex 10/100/100010/100/1000-Mbps Mbps port, which can be used to forward management management information to the external management agent, such as BPDUs, mirrored frames, or frames addressed to other static address entries that have been identified as a special interest to the management system.


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BCM53128 Data Sheet

Frame Management

As IMP is defined as the frame management port, normal frame data is forwarded to the port based on the state of the RX_UCST_EN, RX_MCST_EN and RX_BCST_EN bits in the IMP Port Control register. If these bits are clea cleare red, d, no fram frame e data data will will be forw forwar arde ded d to the the Fram Frame e Mana Manage geme ment nt Port Port,, with with the the exce except ption ion that that fram frames es meet meetin ing g the mirror ingress/egress rules criteria, will always be forwarded to the designated frame management port. Packets transferred over the IMP port are tagged with the Broadcom proprietary header to carry the necessary information which is of interest to the management entity running on the CPU, as shown below, except for the PAUSE frame. The IMP port must support normal Ethernet pause based flow control mechanism. Figure Figure 10: IMP Packet Encapsulat Encapsulation ion Format

The BRCM tag is designed for asymmetric operation across the IMP port. The information carried from the switching device to the CPU is different from the information carried from the CPU to the switching device. Similarly, the host system must insert the BRCM tag fields into frames it wished to send into the management port, to be routed routed to specific specific egress ports. The OPCODE OPCODE within the tag field determines determines how the frame is handled, and allows frames to be forwarded using the normal address lookup using a port ID designation within the tag. The BRCM tag are transmitted with the convention of highest significant octet first, followed by the next lowest significant octet, and so on, with the least significant bit of each octet transmitted out from the MAC first. So, for the the BRCMtag BRCMtag fiel field d in Ta Tabl ble e 18 on pa page ge 81 the most most signif significa icant nt octet octet would would be transm transmitt itted ed first first (bits (bits [24:31 [24:31]), ]), with with bit 24 being the first bit transmitted.


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BCM53128 Data Sheet

Frame Management

Broadcom Tag Format for Egress Packet Transfer When a packet is forwarded by the switching device to the external CPU for processing, the BRCM tag is formatted as shown in Table in Table 18. 18.

Table 18: Egress Egress Broadcom Tag Format Format (IMP to CPU) 31–29

28–24

23–16

15–8

7–5

OPCODE = 000

Reserved

Reserved

REASON_CODE[7: 0]

TC[2 TC[2:0 :0]]

4–0 SRC_ SRC_PI PID[ D[4: 4:0 0 ]

63–61

60–38

37

36–32

OPCODE = 001

Reserved

T/R

T/R_PID[4:0]

31–0 TIME_STAMP[31:0] •

OPCO OP CODE DE 000 000 This indicates the packet transfer with explicit reasons to help the external CPU to direct the packet for the appropriate packet processing entities.

•

REASON REASON_CO _CODE DE [7:0] [7:0] This indicates the reasons why the packet is forwarded to the external CPU so that the CPU can identify the appropriate software routines for packet processing. – Bit [0] indicates mirroring – Bit [1] indicates SA learning – Bit [2] indicates switching – Bit [3] indicates protocol termination – Bit [4] indicates protocol snoopi ng – Bit [5] indicates flooding/exception processing – Bit [6] and Bit[7] are reserved

•

TC [2: [2:0] This indicates the traffic class classified by the switching device when forwarding the packet to the CPU.

•

SRC_ SRC_PI PID D [4:0 [4:0]] This indicates the ingress port of the switching switching device where where the packet is received. received.

•

OPCO OP CODE DE 001 001 This indicates a packet transfer with explicit time stamp recorded at the port where it was transmitted or received (indicated by the T/R_PID) for IEEE 802.1as protocol implementation.

•

T/R This indicates the type of time stamp. 0 indicates indicates the time stamp recorded recorded when the packet was received through the port (indicated by the T/R_PID); 1 indicates the time stamp recorded when the packet was transmitted through the port (indicated by the T/R_PID).


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BCM53128 Data Sheet

•

Frame Management

T/R_ T/R_PI PID D [4:0 [4:0]] This indicates the port through which the packet was transmitted transmitted when T/R = 1, or the port through which the packet was received when T/R = 0.

•

TIME_ST TIME_STAMP AMP [31:0] [31:0] This carries the time stamp value recorded recorded at the ingress port for a received received TS protocol protocol packet.

Broadcom Tag Format for Ingress Packet Transfer For packet transfer from the external CPU to the switching device, the BRCM tag is formatted as shown below. Table 19: Ingress Ingress BRCM Tag (CPU (CPU to IMP)

•

31–29

28–26

25–24

23–0

OPCODE = 000

TC[2:0]

TE[1:0]

Reserved

31–29

28–26

25–24

23

OPCODE = 001

TC[2:0]

TE[1:0]

TS

22–0 DST_MAP[22:0]

OPCO OP CODE DE 000 000 It indicates that the external CPU is not dictating how the packet is forwarded, and the packet is forwarded by the switching device based on the original Ethernet packet information.

•

OPCO OP CODE DE 001 001 This indicates the packet is forwarded to multiple (or single) egress ports by the switching device based on the explicit direction of the external CPU.

•

DST_ DST_MA MAP P [22: [22:0] 0] This indicates the egress port bit map to which the external CPU intends to forward forward the packet. packet.

•

TC [2: [2:0] This indicates the traffic class with which the external CPU intends to forward the packet.

•

TS (time (time stamp stamp reques request) t) This indicates whether the transmit time stamped at the egress port should be reported back to the external CPU.

•

TE (tag (tag enforc enforceme ement) nt) This indicates the 802.1Q/P tagging/untagging encapsulation enforcement for the packet transmission. 00: No enforcement (follow VLAN untag mask rules) 01: Untag enforcement 10: Tag enforcement 11: Reserved


Page 82


BCM53128 Data Sheet

MIB Engine

MIB Engine The MIB Engine is responsible for processing status words received from each port. Based on whether it is a receiv receive e status status or transm transmit it status status,, approp appropria riate te MIB counte counters rs are update updated. d. The BCM531 BCM53128 28 implem implement ent 70-plus 70-plus MIB counters on a per-port basis. MIB counters can be categorized into three groups: receive-only counters, transmit-only counters, and receive or transmit counters. This latter group can, as a group, be selectively steered to the receive or transmit process on a per-port basis. The section below describes each individual counter. The BCM53128 offers the MIB snapshot feature per port enabled. A snapshot of a selected port MIB registers can be captured captured and available available to the users while MIB counters counters are continuing continuing to count. count.

MIB Counters Per Port Receive Only Counter (19) Description of Counter Table 20: Receive Receive Only Counter (19) Description Description of Counter Field

Description

RxDr RxDrop opPk Pkts ts (32 (32 bit) bit)

The The numb number er of good good pack packet ets s rece receiv ived ed by a port port that that were were drop droppe ped d due due to a lack of resources (e.g., lack of input buffers) or were dropped due to a lack of resources before a determination of the validity of the packet was able to be made (e.g., receive FIFO overflow). The counter is only incremented if the receive error was not counted by the RxExcessSizeDisc, the RxAlignmentErrors, or the RxFCSErrors counters.

RxOc RxOcte tets ts (64 (64 bit) bit)

The The numb number er of data data byte bytes s rece receiv ived ed by a port port (exc (exclu ludi ding ng prea preamb mble le,, but but including FCS), including bad packets.

RxBroa RxBroadca dcastP stPkts kts (32 bit) bit)

The number number of good good pack packets ets receiv received ed by a port port that that are direct directed ed to the broadcast address. This counter does not include errored broadcast packets or valid multicast packets. The maximum packet size can be programmed.

RxMu RxMult ltic icas astP tPkt kts s (32 (32 bit) bit)

The The numb number er of good good pack packet ets s rece receiv ived ed by a port port that that are are dire direct cted ed to a mult multic icas astt address. This counter does not include errored multicast packets or valid broadcast packets. The maximum packet size can be programmed.

RxSA RxSACh Chan ange ges s (32 (32 bit) bit)

The The numb number er of time times s the the SA of good good rece receive ive pack packet ets s has has chan change ged d from from the the previous previous value. A count greater greater than 1 generally generally indicates the port is connected to a repeater-based network. The maximum packet size can be programmed.

RxUnde RxUndersi rsizeP zePkts kts (32 bit) bit)

The number number of good good pack packets ets receiv received ed by a port port that that are less less than than 64 bytes bytes long (excluding framing bits, but including the FCS).

RxOv RxOver ersi size zePk Pkts ts (32 (32 bit) bit)

The The numb number er of good good pack packet ets s rece receiv ived ed by a port port that that are are grea greate terr than than stan standa dard rd max frame size. The maximum packet size can be programmed.

RxFr RxFrag agme ment nts s (32 (32 bit) bit)

The The numb number er of pack packet ets s rece receive ived d by a port port that that are are less less than than 64 byte bytes s (excluding (excluding framing bits) and have either either an FCS error or an alignment error.

RxJabbers (32 bit)

The number of packets received by a port that are longer than 1522 bytes and have either an FCS error or an alignment error.

RxUn RxUnica icast stPk Pkts ts (32 (32 bit) bit)

The The numb number er of good good pack packet ets s rece receiv ived ed by a port port that that are are addr addres esse sed d to a unicast address. The maximum packet size can be programmed.


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BCM53128 Data Sheet

MIB Engine

Table 20: Receive Only Counter (19) Description of Counter (Cont.) Field

Description

RxAlign RxAlignmen mentEr tError rors s (32 (32 bit) bit)

The number number of pack packets ets receive received d by a port port that that have have a length length (exclu (excludin ding g framing bits, but including FCS) between 64 and standard max frame size, inclusive, and have a bad FCS with a nonintegral number of bytes.

RxFC RxFCSEr SErro rors rs (32 (32 bit) bit)

The The numb number er of pack packet ets s rece receive ived d by a port port that that have have a lengt length h (exc (exclu ludi ding ng framing bits, but including FCS) between 64 and standard max frame size, inclusive, and have a bad FCS with an integral number of bytes.

RxGo RxGood odOc Octe tets ts (64 (64 bit) bit)

The The tota totall numb number er of byte bytes s in all all good good pack packet ets s rece receiv ived ed by a port port (exc (exclud luding ing framing bits, but including FCS). The maximum packet size can be programmed.

JumboP JumboPktC ktCoun ountt (32 bit) bit)

The number number of good good packet packets s receiv received ed by a port port that that are greate greaterr than than the standard maximum size and less than or equal to the jumbo packet size, regardless of CRC or alignment errors.

RxPa RxPaus useP ePkt kts s (32 (32 bit) bit)

The The numb number er of PA PAUS USE E fram frames es rece receiv ived ed by a port port.. The The PA PAUS USE E fram frame e must must have have a vali valid d MAC MAC Cont Contro roll Fram Frame e Ethe EtherT rTyp ype e fiel field d (88– (88–08 08h) h),, have have a dest destin inat atio ion n MAC address of either the MAC Control frame reserved multicast address (01-80-C2-00-00-01) or the unique MAC address associated with the specific port, a valid PAUSE opcode (00–01), be a minimum of 64 bytes in length (excluding preamble but including FCS), and have a valid CRC. Although an IEEE IEEE 802.3802.3-com complia pliant nt MAC is only only permit permitted ted to transm transmit it PAUSE PAUSE frames frames when when in full-duplex mode with flow control enabled and with the transfer of PAUSE frames determined by the result of auto-negotiation, an IEEE 802.3 MAC receiver is required to count all received PAUSE frames, regardless of its half/ full-duplex full-duplex status. status. An indication indication that a MAC is in half-duplex half-duplex with the RxPausePkts incrementing indicates a noncompliant transmitting device on the network.

RxSym xSymbo bolE lErr rror ors s (32 bit bit

The The totalnum otalnumbe berr oftimesa oftimesa vali validd-le leng ngthpac thpacke kett was was rece receiv ivedat edat a por port and and at least one invalid data symbol was detected. The counter only increments once per carrier event and does not increment on detection of a collision during the carrier event.

RxDi RxDisc scar ard d (32 (32 bit) bit)

The The numb number er of good good pack packet ets s rece receiv ived ed by a port port that that were were disc discar arde ded d by the the Forwarding Process.

InRang InRangeEr eError rors s (32 bit) bit)

The number number of packet packets s receiv received ed with with good good CRC CRC and one of the follow following ing:: (1) The value of length/type field is between 46 and 1500 inclusive, and does not match the number of (MAC client data + PAD) data octets received, OR (2) The value of length/type field is less than 46, and the number of data octets received is greater than 46 (which does not require padding).

OutOfRang OutOfRangeErro eErrors rs (32 bit)

The number number of packets packets received received with good CRC and the value of length/typ length/type e field is greater than 1500 and less than 1536.


Page 84


BCM53128 Data Sheet

MIB Engine

Transmit Counters Only (19) Description of Counter Table 21: Transmit Transmit Counters Counters Only (19) Description Description of Counter Counter Field

Description

TxDr TxDrop opPk Pkts ts (32 (32 bit) bit)

This This coun counte terr is incr increm emen ente ted d ever every y time time a tran transm smit it pack packet et is drop droppe ped d due due to lack lack of resour resources ces (e.g., (e.g., transm transmit it FIFO FIFO underf underflow low), ), or an intern internal al MAC sublay sublayer er transmit error not counted by either the TxLateCollision or the TxExcessiveCollision counters.

TxOc TxOcte tets ts (64 (64 bit) bit)

The The tota totall numb number er of good good byte bytes s of data data tran transm smit itte ted d by a port port (exc (exclu ludi ding ng preamble but including FCS).

TxBroa TxBroadca dcastP stPkts kts (32 bit) bit)

The number number of good good pack packets ets transm transmitt itted ed by a port port that that are direct directed ed to a broadcast address. This counter does not include errored broadcast packets or valid multicast packets.

TxMult TxMultica icastP stPkts kts (32 bit) bit)

The number number of good good packet packets s transm transmitt itted ed by a port port that that are direct directed ed to a multicast address. This counter does not include errored multicast packets or valid broadcast packets.

TxCo TxColli llisi sion ons s (32 (32 bit) bit)

The The numb number er of colli collisio sions ns expe experi rien ence ced d by a port port duri during ng pack packet et tran transm smis issio sions ns..

TxUn TxUnic icas astP tPkt kts s (32 (32 bit) bit)

The The numb number er of good good pack packet ets s tran transm smit itte ted d by a port port that that are are addr addres esse sed d to a unicast address.

TxSing TxSingleC leColli ollisio sion n (32 bit) bit)

The number number of packet packets s succes successfu sfully lly transm transmitt itted ed by a port port that that have have experienced exactly one collision.

TxMult TxMultiple ipleCol Collisi lision on (32 (32 bit) bit)

The number number of pack packets ets succes successfu sfully lly transm transmitt itted ed by by a port port that that have have experienced more than one collision.

TxDeferred TxDeferredTrans Transmit mit (32 bit)

The number of packet packets s transm transmitted itted by a port for which the first transmissio transmission n attempt is delayed because the medium is busy. This only applies to the Half Duplex mode, while the Carrier Sensor Busy.

TxLate TxLateCol Collisi lision on (32 bit) bit)

The number number of times times that that a collisi collision on is detect detected ed later later than than 512 bit-ti bit-times mes into into the transmission of a packet.

TxExcessiveC TxExcessiveCollisio ollision n (32 bit) bit)

The number number of of packets packets that that are are not transmitte transmitted d from from a port port because because the the packet experienced 16 transmission attempts.

TxPa TxPaus useP ePkt kts s (32 (32 bit) bit)

The The numb number er of PA PAUS USE E even events ts at each each port port..

TxFram TxFrameIn eInDis Disc c (32 bit) bit)

The number number of valid valid packet packets s receiv received ed which which are discar discarded ded by the forwar forwarding ding process due to lack of space on an output queue (not maintained or reported in the MIB counte counters) rs).. Locate Located d in the Conges Congestio tion n Manage Managemen mentt regist registers ers (Page (Page 0Ah). This attribute attribute only increments increments if a network device is not acting in complia compliance nce with with a flow flow contro controll reques request, t, or the BCM531 BCM53128 28 intern internal al flowflow-con contro trol/ l/ buffering scheme has been configured incorrectly.

TxQ0 TxQ0PK PKT( T(32 32 bit) bit)

The The tota totall numb number er of good good pack packet ets s tran transm smit itte ted d on COS0 COS0,, whic which h is spec specif ifie ied d in MIB queue select register when QoS is enabled. enabled.










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BCM53128 Data Sheet

MIB Engine

Table 21: Transmit Counters Only Only (19) Description of Counter (Cont.) Field

Description



Transmit or Receive Counters (10) Description of Counter Table 22: Transmit Transmit or Receive Receive Counters (10) Descriptio Description n of Counter Counter Field

Description

Pkts Pkts64 64Oc Octe tets ts (32 (32 bit) bit)

The The numb number er of pack packet ets s (inc (inclu ludi ding ng erro errorr pack packet ets) s) that that are are 64 byte bytes s long. long.

Pkts65to127 Pkts65to127Octe Octets ts (32 (32 bit) bit)

The number number of packets packets (including (including error packets) packets) that are between between 65 and 127 bytes long.

Pkts128to25 Pkts128to255Oct 5Octets ets (32 bit)

The number of packet packets s (includi (including ng error error packets) packets) that are between between 128 128 and and 255 bytes long.

Pkts Pkts25 256t 6to5 o511 11Oc Octe tets ts (32 (32 bit) bit)

The The numb number er of pack packet ets s (inc (includ ludin ing g erro errorr pack packet ets) s) that that are are betw betwee een n 256 256 and and 511 511 bytes long.

Pkts512to10 Pkts512to1023Oct 23Octets ets (32 bit)

The number number of packet packets s (including (including error error packets) packets) that are are between between 512 and and 1023 bytes long.

Pkts1024toMaxPktOctets (32 bit)

The number of packets that (include error packets) are between 1024 and the standa standard rd maximu maximum m pack packet et size size incl inclusiv usive. e.

The total number of counters per port is 43. Table 23 identifies 23 identifies the mapping of the BCM53128 MIB counters and their generic mnemonics to the specific counters and mnemonics for each of the key IETF MIBs that are supported. Direct mappings are defined. However, there are several additional statistics counters, which are indirectly supported that make up the full complement of the counters required to fully support each MIB. These are shown in Table 24 on page 88. 88. Finally, Table Finally, Table 25 on page 89 identifies 89 identifies the additional counters supported by the BCM53128 and references the specific standard or reason for the inclusion of the counter. Table 23: Directly Directly Supported Supported MIB Counters Counters BCM53128 MIB

Ethernet-Like MIB Bridge MIB RFC 1643 RFC 1493

MIB II Interface RFC 1213/1573

RMON MIB RFC 1757

RxDropPkts

dot3StatsInternalM dot1 dot1dT dTpP pPor ortI tInD nDis isca card rds s ifIn ifInDi Disc scar ards ds ACReceiveErrors

–

RxOctets

–

–

ifInOctets

etherStatsOctets

RxBroadcastPkts

–

–

ifInBroadcastPkts

etherStatsBroadcast Pkts

RxMulticastPkts

–

–

ifInMulticastPkts

etherStatsMulticast Pkts

RxSAChanges

Note 2

Note 2

Note 2

Note 2

RxUndersizePkts

–

–

–

etherStatsUndersize Pkts


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BCM53128 Data Sheet

MIB Engine

Table 23: Directly Supported Supported MIB Counters Counters (Cont.) Ethernet-Like MIB Bridge MIB RFC 1643 RFC 1493


RMON MIB RFC 1757

RxOv RxOver ersi size zePk Pkts ts

dot3 dot3St Stat atsF sFra rame meTo Too o – Longs

–

etherStatsOverrsize Pkts

RxFragments

–

–

–

eytherStatsFragment s

RxJabbers

–

–

–

etherStatsJabbers

RxUnicastPkts

–

–

ifInUcastPkts

–

RxAlignment RxAlignmentError Errors s

dot3StatsA dot3StatsAlignme lignment nt – Errors

–

–

RxFCSErrors

dot3StatsFCSErrors –

–

–

RxGoodOctets

–

–

–

–

RxExcessSizeDisc

Note 2

Note 2

Note 2

Note 2

RxPausePkts

Note 2

Note 2

Note 2

Note 2

RxSymbolErrors

Note 2

Note 2

Note 2

Note 2

Note 1

–

–

ifInErrors

–

Note 1

–

–

ifInUnknownProtos –

Note 1

–

dot1dTpPortInFrames –

TxDropPkts

dot3StatsInternal – MACTransmitErrors

ifOutDiscards

–

TxOctets

–

–

ifOutOctets Note 3

–

Note 1

–

dot1dTpPortOutFrame – s

TxBroadcastPkts

–

–

ifOutBroadcastPkts –

TxMulticastPkts

–

–

ifOutMulticastPkts –

TxCollisions

–

–

–

etherStatsCollisions

TxUnicastPkts

–

–

ifOutUcastPkts

–

TxSing TxSingleC leColli ollisio sion n

dot3St dot3Stats atsSin Single gle CollisionFrames

–

–

–

TxMultipleCo TxMultipleCollision llision

dot3StatsM dot3StatsMultiple ultiple CollisionFrames

–

–

–

TxDeferred TxDeferredTrans Transmit mit

dot3StatsD dot3StatsDeferr eferred ed – Transmissions

–

–

TxLa TxLate teCo Coll llis isio ion n

dot3 dot3St Stat atsL sLat ate e Collision

–

–

–

TxExcessiveCollision dot3StatsExcessive – Collision

–

–

TxFrameInDisc

Note 2

Note 2

Note 2

Note 2

TxPausePkts

Note 2

Note 2

Note 2

Note 2

Note 4

dot3StatsCarrier SenseErrors

–

–

–

Note 1

–

–

ifOutErrors

–

BCM53128 MIB

–

–


Page 87


BCM53128 Data Sheet

MIB Engine

Table 23: Directly Supported Supported MIB Counters Counters (Cont.) BCM53128 MIB

Ethernet-Like MIB Bridge MIB RFC 1643 RFC 1493


RMON MIB RFC 1757

Pkts64Octets

–

–

–

etherStatsPkt64 Octets

Pkts65to127Octets

–

–

–

etherStatsPkt65to 127Octets

Pkts128to255Octets –

–

–



–

–



–

–


Pkts1024toMaxPkt Octets

–

–

–

etherStatsPkt1024to MaxPktOctets

Note 1

–

–

–

etherStatsDrop Events

Note 1

–

–

–

etherStatsPkts

Note 1

–

–

–

etherStatsCRCAlign Errors

Note 4

dot3StatsSQETest – Errors

–

–

Note 1: Derived 1: Derived by summing two or more of the supported counters. See Table 24 for 24 for specific details. Note 2: Extensions 2: Extensions required by recent standards developments or BCM53128 operation specifics. Note 3: The 3: The MIB II interfaces specification for if OutOctets includes preamble/SFD and errored bytes. Because IEEE 802.3-compliant MACs have no requirement to keep track of the number of transmit bytes in an errored frame, this count is impossible to maintain. The TxOctets counter maintained by the BCM53128 is consistent with good bytes transmitted, excluding preamble, but including FCS. The count can be adjusted to more closely match the if OutOctets definition by adding the preamble for TxGoodPkts and possibly an estimate of the octets involved in TxCollisions and TxLateCollision. Note 4: The 4: The attributes TxCarrierSenseErrors and TxSQETestErrors are not supported in the BCM53128. These attributes were originally defined to support coax-based AUI transceivers. The BCM53128 integrated transc transceiv eiver er design design means means these these error error condit condition ions s are elimin eliminate ated. d. MIBs MIBs intend intending ing to suppor supportt such such counte counters rs should should return a value of 0 (not supported).

Table 24: Indirectly Indirectly Supported Supported MIB Counters Counters Bridge MIB RFC 1493


RMON MIB RFC 1757

RxErrorPkts = – RxAlignmentErrors + RxFCSErrors + RxFragments + RxOversizePkts + RxJabbers

–

ifInErrors

–

–

–

ifInUnknownProtos

–

BCM53128 MIB

Ethernet-Like MIB RFC 1643


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BCM53128 Data Sheet

MIB Engine

Table 24: Indirectly Supported Supported MIB Counters Counters (Cont.) Ethernet-Like MIB RFC 1643

Bridge MIB RFC 1493


RMON MIB RFC 1757

RxGoodPkts = RxUnicastPkts + RxMulticastPkts + RxBroadcastPkts

–

dot1dTpPortIn Frames

–

–

DropEvents = RxDropPkts + TxDropPkts

–

–

–

etherStatsDrop Events

RxTotalPkts = RxGoodPkts + RxErrorPkts

–

–

–

etherStatsPkts

RxCRCAlignErrors = – RxCRCErrors + RxAlignmentErrors

–

–

etherStatsCRCAlign Errors

–

–

–

–

RxFramesTooLong = dot3StatsFrameToo – RxOversizePkts + Longs RxJabber

–

–

TxGoodPkts = TxUnicastPkts + TxMulticastPkts + TxBroadcastPkts

dot1dTpPortOut Frames

–

–

–

ifOutErrors

–

BCM53128 MIB

dot3StatsSQETest Errors

–

TxErrorPkts = – TxExcessiveCollision + TxLateCollision Note 1

Note 1: The 1: The number of packets transmitted from a port that experienced a late collision or excessive collisions. While some media types operate in half-duplex mode, frames that experience carrier sense errors are also summed in this counter. The BCM53128 integrated design means this error condition is eliminated.

Table 25: BCM53128 BCM53128 Supported Supported MIB Extensions Extensions BCM5 BCM531 3128 28 MIB MIB

Appr Approp opri riat ate e Stan Standa dard rds s Refe Refere renc nce e

RxSA RxSACh Chan ange ges s

IEEE IEEE 802. 802.3u 3u Clau Clause se 30—R 30—Rep epea eate terr Port Port Mana Manage ged d Obje Object ct Clas Class s a SourceAddressChanges.

RxExce RxExcessS ssSize izeDis Disc c

The BCM531 BCM53128 28 cannot cannot store store packet packets s in excess excess of 1536 1536 bytes bytes (exclu (excludin ding g preamb preamble/ le/ SFD, but inclusive of FCS). This counter indicates packets that were discarded by the BCM53128 due to excessive length.

RxPa RxPaus useP ePkt kts s

IEEE IEEE 802. 802.3x 3x Clau Clause se 30—P 30—PAU AUSE SE Enti Entity ty Mana Manage ged d Obje Object ct Clas Class s aPAUSEMACCtrlFramesReceived.

RxSy RxSymb mbol olEr Erro rors rs

IEEE IEEE 802. 802.3u 3u Clau Clause se 30—R 30—Rep epea eate terr Port Port Mana Manage ged d Obje Object ct Clas Class s aSymbolErrorDuringPacket.

TxFr TxFram ameI eInD nDis isc c

Inte Intern rnal al diag diagno nost stic ic use use for for opti optimi miza zati tion on of flow flow cont contro roll and and buff buffer er alloc allocat atio ion n algorithm.


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BCM53128 Data Sheet

Integrated High-Performance Memory

Table 25: BCM53128 Supported Supported MIB Extensions Extensions (Cont.) BCM5 BCM531 3128 28 MIB MIB

Appr Approp opri riat ate e Stan Standa dard rds s Refe Refere renc nce e

TxPa TxPaus useP ePkt kts s

The The num number ber of PA PAU USE even events ts at a give given n port port..

Integrated High-Performance Memory The BCM53128 embed a 192 KB high-performance SRAM for storing packet data. This eliminates the need for external memory and allows for the implementation of extremely low-cost systems. The internal RAM controller efficiently executes memory transfers and achieves nonblocking performance for stand-alone 8-port applications.

Switch Controller The core of the BCM53128 devices is a cost-effective and high-performance switch controller. The controller mana manage ges s pack packet et forw forwar ardin ding g betw betwee een n the the MAC MAC rece receiv ive e and and tran transm smit it port ports s thro throug ugh h the the fram frame e buff buffer er memo memory ry with with a store and forward architecture. The switch controller encompasses the functions of buffer management, memory arbitration, and transmit descriptor queueing.

Buffer Management The frame buffer memory is divided into pages (units of data consisting consisting of 256 bytes each). Each received received packet may be allocated more than one page. For example, six pages are required to store a 1522-byte frame. Frame data is stored in the buffer memory as the packet is received. After reception, the frame is queued to the egress port(s) transmit queue. This list tracks the transmission of the packet. After successful packet transmission, the buffer memory is released to the free buffer pool.

Memory Arbitration Processes requesting access to the internal memory include the receive and transmit frame data handlers, address resolution, the VLAN lookup, learning and aging functions, egress descriptor update, and output-port queu queue e mana manage gers rs.. Thes These e proc proces esse ses s are are arbi arbitr trat ated ed to prov provide ide fair fair acce access ss to the the memo memory ry and and minim minimiz ize e the the late latenc ncy y of critical processes to provide a fully nonblocking solution.

Transmit Transm it Outpu Outputt Port Queues Frames are maintained in the egress port using a linked list. Two levels of linked lists are used to maintain one output output queue (see the figure below). The first level is the TXQ linked list, and the second level is the buffer tag linked list. The TXQ linked list is used to maintain frame TC order for each port. For each frame, the buffer tag linked list is used to maintain the order of the buffer pages corresponding to each frame.


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BCM53128 Data Sheet

Switch Controller

Each egress port supports up to six transmit queues for servicing Quality of Service (QoS). All six transmit queues share the 768 entries of the TXQ table. The TXQ table is maintained as a linked list, and each node in the TXQ uses one entry in the TXQ table. The TXQ size for each priority can be programmed to up to 768 entries. When the QoS function has been turned off, the switch controller maintains one output queue for each egress port. The TXQ table is maintained in a per-port individual internal memory. Each node in the queue represents a pointer that points to a frame buffer tag. Each buffer tag includes includes frame information information and a pointer to the next buffer tag. Each buffer tag has an associated page allocated in the frame buffer. For a packet with a frame size larger than 256 bytes, multiple buffer tags are required. For instance, a 9720-byte jumbo frame requires 38 buffer tags for handling the frame. Figure Figure 11: TXQ and Buffer Buffer Tag Structure Structure

Priority 0 Priority 1 Priority 2 Priority 3

Data B uffer

TXQ

Buffer T ag

Frame 0 ,0 Frame 1 ,0 Frame 0 ,1 Frame 0 ,2 Empty Frame 3 ,0

Page 0 ,0,0 Page 1 ,0,0 Page 0 ,1,0 Page 0 ,2,0

256B 256B 256B

Page 0 ,1,1 Page 3 ,0,0

256B 256B

Frame 3 ,1 Empty

Page 3 ,1,0 Page 3 ,1,1

256B 256B

Empty

Empty

256B

256B


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BCM53128 Data Sheet

System Interfaces

S e c ti t i o n 4 : S y s t em e m I n t e rf rf a c e s Overview of System Interfaces The BCM53128 include the following interfaces: •

“Copper Interface”

•

“Frame Management Port Interface” Interface” on page 93

•

“Configuration Pins” on page 94

•

“Programming Interfaces” Interfaces” on page 95

•

“MDC/MDIO Interface” on page 112

•

“LED Interfaces” Interfaces” on page 119

Each interface interface is discussed discussed in detail in these sections. sections.

Copper Interface The internal PHYs transmit and receive data using the analog copper interface. This section discusses the following topics: •

“Auto-Negotiation” on page 92

•

“Line-side (Remote) Loopback Mode” on page 93

•

“Reverse MII Port (RvMII)” (RvMII)” on page 93

•

“GMIII Port” “GMI Port” on page page 94

•

“RGMII Port” on page 94

•

“SPI-Compatible Programming Programming Interface” on page 96

•

“EEPROM Interface” Interface” on page 110

•

“MDC/MDIO Interface Register Programming” on page 112

•

“PseudoPHY” on page 113

Auto-Negotiation The BCM53128 negotiate a mode of operation over the copper media using the auto-negotiation mechanism defined defined in the IEEE IEEE 802.3u 802.3u and IEEE IEEE 802.3a 802.3ab b specif specifica icatio tions. ns. When When the auto-n auto-nego egotia tiatio tion n functi function on is enable enabled, d, the BCM53128 automatically choose the mode of operation by advertising its abilities and comparing them with those received from its link partner. The BCM53128 can be configured to advertise the following modes: •

1000BASE-T 1000BASE-T full-duplex full-duplex and/or half-duplex half-duplex

•

100BASE-TX 100BASE-TX full-duplex full-duplex and/or and/or half-duplex half-duplex

•

10BASE-T 10BASE-T full-duplex full-duplex and/or half-duplex half-duplex


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BCM53128 Data Sheet

Frame Management Port Interface

The transceiver negotiates with its link partner and chooses the highest common operating speed and duplex mode, commonly referred to as highest common denominator (HCD). Auto-negotiation can be disabled by software control, but is required for 1000BASE-T operation.

Line-side (Remote) Loopback Mode The line-side loopback loopback mode allows the testing of the copper interface interface from the link partner. partner. This mode is enabled by setting bit 15 of the Miscellaneous Test register. The MDI receive packet is passed through the PCS and sent back out as the MDI transmit packet. packet. The PCS receive data appears on the internal MAC interface. interface.

Frame Management Port Interface The dedicated frame management port provides high-speed connection to transfer management packets to an external management agent. For more information about frame management, see “Frame see “Frame Management” on page 79. 79. The port is configurable to Reverse MII (RvMII), GMII, or RGMII using strap pins or software configuration.

MII Interface The Media Independent Interface (MII) serves as a digital data interface between the BCM53128 and an external 10/100 Mbps management entity or a PHY entity. The BCM53128 provides a fully IEEE 802.3ucompatible MII interface.

TMII (Turbo MII) and RvTMII (Reverse TMII) Interface The TMII and RvTMII interfaces use the same hardware interface signals as the MII interface. The TMII mode requires the SPEED setting bits in the IMP Port States Override Register (Page 00h: Address 0Eh) bits[3:2] to be set. The TMII mode supports 200 Mbps data rate over the existing MII interface by running the interface at (up to) 50 MHz. The original MII timing is designed such that it can support 50 MHz clocking over the existing design.

Reverse MII Port (RvMII) The media media indepe independe ndent nt interf interface ace (MII) (MII) serves serves as a digital digital data data interf interface ace betwee between n the BCM531 BCM53128 28 and an extern external al 10/100 10/100 Mbps Mbps manage managemen mentt entity entity.. Revers Reverse e MII notati notation on reflec reflects ts the MII port port interf interfaci acing ng to a MAC-ba MAC-based sed extern external al agent. The RvMII contains all the signals required to transmit and receive data at 100 Mbps and 10 Mbps for both full-duplex and half-duplex operation. See Figure See Figure 12 on page 94 for 94 for connection information.


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BCM53128 Data Sheet

Configuration Pins

Figure Figure 12: RvMII RvMII Port Connection Connection MII-Compliant MAC

Reverse MII Port

RXD[3:0]

TXD[3:0]

RXC

TXC

RXDV

TXEN

CRS

NC

TXER

RXER and COL TXD[3:0]

RXD[3:0]

TXC

RXC

TXEN TXER

RXDV NC RXER

GMII Port The Gigabit Media Independent Interface (GMII) serves as a digital data interface between the BCM53128 and an external gigabit management management entity. Transmit Transmit and receive receive data is clocked on the rising edge of the clocks. clocks. The GMII transmits data synchronously using the TXD[7:0] and RXD[7:0] data signals.

RGMII Port The Reduced Gigabit Media Independent Interface (RGMII) serves as a digital data interface between the BCM53128 and an external gigabit management entity. Transmit and receive data is clocked on the rising and falling edge of the clocks. This reduces the number of data signals crossing the MAC interface without affecting the data transmission rate. The RGMII transmits data synchronously using the TXD[3:0] and RXD[3:0] data signals.

Configuration Pins Initial configuration of the BCM53128 takes place during power-on/reset by loading internal control values from hardware strap pins. The value of the pin is loaded when the reset sequence completes, and the pin transitions to normal operation. operation. Pull-up or pull-down pull-down resistors resistors can be added to these pins to control the device configuration. If the pins are left floating, the default value is determined based on the internal pull-up or pulldown configuration. See “Signal See “Signal Descriptions” on page 125 for 125 for more information.


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BCM53128 Data Sheet

Programming Interfaces

Programming Programmin g Interfaces The BCM53128 can be programmed using the SPI interface or the EEPROM interface. The interfaces share a common pin set that is configured using the CPU_EPROM_SEL strap pin. The “SPI-Compatible The “SPI-Compatible Programming Interface” provides Interface” provides access for a general-purpose microcontroller, allowing read and write access to the internal BCM53128 register space. It is configured to be compatible with the Motorola Serial Peripheral Interface (SPI) protocol. Alternatively, the “EEPROM the “EEPROM Interface” on page 110 can 110 can be connected to an external EEPROM for writing register values upon power-up initialization. The internal address space of the BCM53128 devices is broken into a number of pages. Each page groups a logical logical set of registers registers associated associated with a specific specific function. Each page provides provides a logical address address space of 256 bytes, although, in general, only a small portion of the address space in each page is utilized. An explanation follows for using the serial interface with an SPI-compatible CPU (“SPI-Compatible Programming Interface” on page 96) 96) or an EEPROM (“EEPROM (“EEPROM Interface” on page 110). 110). Either mode can be selected with the strap pin, CPU_EPROM_SEL. Either mode has access to the same register space.

Serial Flash Interface The BCM53128 offers a serial flash interface to store program code for the internal microcontroller (8051 processor). The BCM53128 detects a flash memory device automatically and downloads the memory contents upon power-up. The main purpose of the stored code is to configure and run the power savings mode, such as Green mode or any application that the user wishes to run that can fit in the internal 8051 memory. The embedded 8051 microcontroller has 128 KB of SRAM and 64 KB of ROM, supports receiving and transmitting packets, and supports interleaved ROM/RAM access. The interface comprises four signal pins: chip select (FCS), (FCS), Flash clock (FCLK), (FCLK), Flash Serial Out (FSO), and Flash Serial In (FSI).

GPIO BCM53128 supports up to 8 GPIO pins. These GPIO pins can be used to connect to various external devices. Upon power-up and reset, these pins become tristated. Enable GPIO pins through the GPIO Enable Register in 8051 Memory-Map Memory-Mapped ped Registers. Registers. They can be programme programmed d to be either input or output pins via the GPIO registers in 8051 Memory-Mapped Registers. The internal pull-up/pull-down of GPIOs is user-configurable through GPIO registers setting in 8051 Memory-Mapped Registers. Refer to the BCM53128 the BCM53128 Programmer's Reference Guide (document Guide (document number 53128-PG1xx-R) for 8051 Memory-Mapped Registers detail information.


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BCM53128 Data Sheet


SPI-Compatible Programming Interface One way to access access the BCM531 BCM53128 28 intern internal al regist registers ers is to use the serial serial periphe peripheral ral interc interconn onnect ect (SPI) (SPI) compat compatible ible interf interface ace.. This four-p four-pin in interf interface ace is design designed ed to suppor supportt a fully fully functi functiona onal, l, bi-dir bi-direct ection ional al Motoro Motorola la serial serial periph periphera erall interface (SPI) for register read/write accesses. The maximum speed of operation is 25 MHz. The SPI interface shares pins with the EEPROM interface. To select the SPI interface, pull up or float the CPU_EPROM_SEL pin. (The internal pull-up resistor defaults SPI interface over EEPROM interface.) The SPI is a four-pin four-pin interface consisting consisting of: •

Device select (SS: slave slave select, select, input to BCM53128 BCM53128))

•

Device clock clock (SCK: (SCK: which operat operates es at speeds speeds up to 25 MHz, MHz, input to to BCM53128) BCM53128)

•

Data write write line line (MOSI: (MOSI: Master Master Out/Sl Out/Slave ave In, input to to BCM53128) BCM53128)

•

Data read read line (MISO: (MISO: Master Master In/Slave In/Slave Out, Out, output output from BCM531 BCM53128) 28) Note: All Note: All the RoboSwitch™ SPI interfaces are designed to operate in slave mode. Therefore, the SCK and SS signals signals are driven by the external master master host device when accessing accessing the BCM53128 BCM53128 registers. For more detailed descriptions reader may refer to the Motorola SPI spec MC68HC08AS20Rev. 4.0 .

SS: Slave Select The SS signal is used to select a slave device and to indicate the beginning of transmission. The BCM53128 SPI interface operates in the clock phase one (CPHA = 1) transmission format. In this format, the SS signal is driven active low while the SCK signal is high, and remains low throughout the transmission including multiplebyte transfers. The minimum time requirement between SS operation is 200 ns.

SCK: Serial Clock The serial clock SCK maximum maximum operating operating frequency frequency is 25 MHz for the BCM53128 family family of devices. devices. The SCK is used to clock data into and out of the Slave ROBO device. The SCK signal is expected to remain high when the interface is idle. This is because the BCM53128 SPI design is based on CPOL = 1 (Clock Polarity = 1). This is not programmable on BCM53128. The BCM53128 is designed so that data is driving by the falling edge and sampling sampling by the rising edge of the SCK clock. This clock is not a free-runnin free-running g clock, it is generated only during a data transaction, and remains high when the clock is idle.

MOSI: Master Output Slave Input The MOSI signal is used by the master device to transmit the data to the slave device. The data is put on the bus and is expected to be clocked in by a rising edge of the SCK clock signal. This line is used to issue a command and to set the register page and address value of read/write operations.


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BCM53128 Data Sheet


MISO: Master Input Slave Output The MISO signal is used by the Slave device to output the data to the master device. The data is put on the bus and and is expe expect cted ed to be cloc clocke ked d out out by a risi rising ng edge edge of the the SCK SCK cloc clock k sign signal al.. This This line line is used used to tran transm smit it the the stat status us and the content content of the register of read operation. operation. A layer of protocol is added to the basic SPI definition to facilitate transfers from the BCM53128. This protocol esta establ blish ishes es the the defi definit nitio ion n of the the firs firstt 2 byte bytes s issu issued ed by the the mast master er to the the BCM5 BCM531 3128 28 slav slave e duri during ng an SPI tran transf sfer er.. The first byte issued from the SPI master in any transaction is defined as a command byte, which is always followed by a register address byte, and any additional bytes are data bytes. The SPI mode supports two different access mechanisms, normal SPI and fast SPI, determined by the content of the command byte. Figure byte. Figure 13 shows 13 shows the normal SPI command byte, and Figure and Figure 14 on page 97 shows 97 shows the Fast SPI command byte. These two mechanisms should not be mixed in an implementation; the CPU should always initiate transfers consistently with only one of the two mechanisms. Figure Figure 13: Normal Normal SPI Command Command Byte 0

1

1

MODE = 0

CHIP ID 2 (MSB)

CHIP ID 1

CHIP HIP ID 0 (LSB)

Read/Write (0/1)

CHIP HIP ID 0 (LSB)

Read/Write (0/1)

Figure Figure 14: Fast SPI Comman Command d Byte Byte Offset (MSB)

Byte Byte Offset Offset

Byte Byte Offset Offset (LSB)

MODE = 1

CHIP HIP ID 2 (MSB)

CHIP ID 1

The MODE bit (bit 4) of the command byte determines the meaning of bits 7:5. If bit 4 is a 0, it is a normal SPI command byte, and bits 7:5 should be defined as 011b. If bit 4 is a 1, bits 7:5 indicate a fast SPI command byte, and bits 7:5 indicate the byte offset into the register that the BCM53128 starts to read from (byte offsets are not supported for write operations). In command bytes, bits[3:1] indicate the CHIP ID to be accessed. Because the BCM53128 operates as a singlechip system, the CHIP ID is 000. Note: The Note: The SS signal must also be active for any BCM53128 device to recognize that it is being accessed. Bit 0 of the command byte is the R/W signal (0 = Read, 1 = Write) and determines the transmission direction of the data. The byte following the command byte is an 8-bit register address. Initially, this sets the page address, followed by another command byte that contains the register base address in that page, which is used as the location to store the next byte of data received received in the case of a write operation, or the next address address from which to retrieve data data in the the case case of a read read oper operat atio ion. n. This This base base addr addres ess s incr increm emen ents ts as each each byte byte of data data is tran transm smit itte ted/ d/re rece ceiv ived ed,, allowing allowing a contiguous contiguous block data from a register to be stored/read stored/read in a single transmissio transmission. n. When the fast SPI comm comman and d byte byte mode mode is used used,, the the actu actual al star startt loca locati tion on of a read read oper operat ation ion can can be modi modifi fied ed by the the offs offset et cont contai aine ned d in bits 7:5 of the command byte. Reading/writing data from/to separate registers, even if those registers are contiguous in the current page, must be performed by supplying a new command byte and register address for each register, with the address as defined in the appropriate page register map.


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BCM53128 Data Sheet


Noncontiguous blocks are also stored/read through the use of multiple transmissions, which allow a new command byte and register base address to be specified. The SS signal must remain low for the entire read or write transaction, as shown in the following figures, with the transaction terminated by the deassertion of the SS line by the master. Figure 15: SPI Serial Serial Interface Interface Write Operation Operation

Figure 16: SPI Serial Serial Interface Interface Read Operation

Figure 17 and 17 and Figure Figure 18 on page 99 show 99 show the typical connection block diagram for SPI interface with/without external PHY devices.

Without External PHY Figure 17: SPI Interface Without Without External PHY PHY Device

Slave Master

RoboSwitch

MOSI

MOSI

MISO

MISO

SCK

SCK

SS#

SS#

SPI Device


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BCM53128 Data Sheet


External PHY Registers The BCM53128 also uses the MDIO/MDC interface for polling registers of an external PHY. In this case, the MDIO/MDC interface polls the external PHY registers pulling the data internal to the BCM53128. Then, the exte extern rnal al PHYs PHYs and and retr retrie ieve ved d from from the the regis registe terr data data using using the the SP SPII inte interf rfac ace. e. The The MDIO MDIO/M /MDC DC inte interf rfac ace e is not not used used as a method to access internal PHY registers. This must be done using the SPI interface. Figure 18: Accessing External PHY Registers Registers

RoboSwitch Slave

Switch Internal Registers

Switch Includes polled

Master

MOSI

MOSI

MISO

MISO

SCK

SCK

SS# SS #

SS# SS #

SPI Device

registers of Ext PHY

MDC MDIO

External PHY registers are accessed by the SPI comaptible device via the SPI access to the switch registers .

Slave

Ext PHY

Reading and Writing BCM53128 Registers Using SPI BCM53128 internal register read and write operations are executed by issuing a command followed by multiple accesses of the SPI registers in the BCM53128. There are three SPI interface registers in the BCM53128 that are used by the master device to access the internal switch registers. The SPI interface registers are: •

SPI Page register register (page: (page: global, global, address: address: FFh): used used to specify specify the value of the specific specific register register pages. pages.

•

SPI Data I/O register register (page: (page: global, address: address: F0h): F0h): used to write and read the specific specific register’ register’s s content. content.

•

SPI Status Status Register Register (page: (page: global, address: address: FEh): FEh): used to check check for an operation operation completio completion. n. – Bit 7: SPIF, SPI read/write complete flag – Bit 6: Reserved – Bit 5: RACK, SPI read data ready acknowledgement – Bit 4:3: Reserved – Bit 2: MDIO_Start, Start/Done MDC/MDIO operation – Bit 1: Reserved – Bit 0: Reserved


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BCM53128 Data Sheet


The BCM53128 SPI interface supports the following operating modes. •

Norm Normal al read read mode mode

•

Fast Fast read read mode mode

•

Normal Normal write write mode mode Note: The Note: The RoboSwitch family does not support fast-write mode.

The details of each modes are described in the following paragraphs.

Normal Read Operation Normal Read operation consists of five transactions (five SS operations): 1. Issue a Normal Read Command Command (opcode = 0x60) to poll the SPIF bit in the SPI Status register (0xFE) (0xFE) to determine the operation can start. 2. Issue a Normal Write command (opcode (opcode = 0x61) to write the register page value into the SPI Page register 0xFF. 3. Issue a Normal Read command (opcode = 0x60) to setup the required RoboSwitch register address. address. 4. Issue a Normal Read command command (opcode (opcode = 0x60) to poll the RACK bit in the SPI status register(0 register(0xFE) xFE) to determine the completion of read (register content gets loaded in SPI Data I/O register). 5. Issue a Normal Read command command (opcode (opcode = 0x60) to read the specific registers registers'' content placed in the SPI Data I/O register (0xF0).


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BCM53128 Data Sheet


Figure 19: Normal Normal Read Operation Operation

Normal Read Mode Start

Step 1 Issue Normal Read Command (opcode=60) to poll data from SPI Status Register (0xFE) (0xFE)

No No

SPIF (bit 7) =0?

Software Timeout ?

Yes

Yes

Is accessed Register page same as previous?

Yes

No

Step 2 Issue Normal Write Command (opcode=61) to write the accessed acces sed register page value into SPI Page Register (0xFF)

Step 3 Issue Normal Read Command (opcode=60) to setup the accessed acces sed register address

Step 4 Issue Normal Read Command (opcode=60) to poll data from SPI Status Register (0xFE)

No RACK (bit 5) =1?

No

Software Timeout ? Yes

Yes Step 5 Issue Normal Read Command (opcode=60) to read data from SPI Data I/O Register (0xF0) [MSB first, continute if more bytes]

Issue Normal Write Command (opcode=61) to write the accessed register page value into SPI Page Register (0xFF)

Done

Task Abort


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BCM53128 Data Sheet


Example: Read from 1000BASE-T Control register (Page 10h, Offset 12h). 1. Issue a Normal Read command command (opcode (opcode = 0x60) to check the SPIF bit in the SPI Status register register (0xFE). (0xFE). • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Read Read Command Command Byte: Byte: 0 1 1 0 0 0 0 0 (opcode (opcode = 0x60) 0x60) • Clock in the SPI Status Status registe registerr address address (0xFE) (0xFE) • Clock out out the SPI Status Status register register value: value: 0 0 0 0 0 0 0 0 (SPIF bit bit 7=0) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 20: Normal Normal Read Mode to Check the SPIF Bit of SPI Status Register Register

2. Issue a Normal Write Write command (opcode (opcode = 0x61) and write the accessed accessed register register page value of 0x10 into SPI Page Reigster(0xFF)—this step is required only if previous read/write was not to/from Page 10h. • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Write Write Command Command Byte: Byte: 0 1 1 0 0 0 0 1 (opcode (opcode = 0x61) • Clock in offset offset of of Page Page register register (0xFF) (0xFF) • Clock in the the accessed accessed register register page page value,: value,: 0 0 0 1 0 0 0 0 (Page register: register: 0x10) 0x10) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 21: Normal Normal Read Mode to Setup the Accessed Register Register Page Value Value


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BCM53128 Data Sheet


3. Issue a Normal Read command (opcode (opcode = 0x60) and write the accessed register address value 0x12, and clock out 8 bits to complete the read cycle, but discard result (this is where the state machine triggers a internal data transfer from Address 0x12 to the SPI Data I/O register) • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Read Read Command Command Byte: Byte: 0 1 1 0 0 0 0 0 (opcode (opcode = 0x60) 0x60) • Clock in the the address address of accessed accessed register register addres address s value (0x12) (0x12) • Clock out out eight clocks clocks for for the dummy dummy read, and and discard discard results results on MISO MISO • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 22: Normal Normal Read Mode to Setup Setup the Accessed Accessed Register Register Address Value (Dummy (Dummy Read)

Note: This Note: This dummy read is always eight clock cycles, whether or not it is an 8-bit register.

4. Issu Issue e a Norm Normal al Read Read comm comman and d (opc (opcod ode e = 0x60 0x60)) to read read the the SP SPII Stat Status us to chec check k the the RACK RACK bit bit for for comp complet letio ion n of the register content transfer to the SPI Data I/O register.(this step may be repeated until the proper bit set is read.) • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Read Read Command Command Byte: Byte: 0 1 1 0 0 0 0 0 (opcode (opcode = 0x60) 0x60) • Clock in offset offset for SPI Status Status Register Register (0xFE): (0xFE): 1 1 1 1 1 1 1 0 • Clock out the the content content of SPI Status Status bits bits • Repeat Repeat the polling until until the content content of SPI Status Status Register Register value: 0 0 1 0 0 0 0 0 (RACK bit 5= 1) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 23: Normal Normal Read Mode to Check the SPI Status for Completion Completion of Read


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BCM53128 Data Sheet


5. Issue a Normal Read command command (opcode (opcode = 0x60) to read the data from the SPI Data I/O register: register: • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock Clock in Comm Command and Byte: Byte: 0 1 1 0 0 0 0 0 (opco (opcode de = 0x60) 0x60) • Clock in offset offset of SPI SPI Data I/O Registe Registerr (0xF0) (0xF0) • Clock Clock out first first data data byte byte on MISO line: line: 0 0 0 0 0 0 0 0 (Byte (Byte 0: Bit 7 to Bit 0: MSB to LSB) LSB) • Clock out out next byte byte (in this this case, last) last) on MISO MISO line: 0 0 0 0 1 1 1 0 (Byte (Byte 1: Bit 15 to Bit 8) 8) • [Cont [Continu inue e if more more bytes bytes]] • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 24: Normal Normal Read Mode to Obtain the Register Register Content

Fast Read Operation Fast Read operation consists of 3 transactions (three SS operations) 1. Issue a Normal Read Command Command (opcode = 0x60) to poll the SPIF bit in the SPI Status Register Register (0xFE) to determine the operation can start. 2. Issue a Fast Read command (opcode (opcode = 0x10) to setup the accessed Register Register Page value into the Page register (0xFF). 3. Issue a Fast Read command (opcode (opcode = 0x10) to setup the accessed register register address value, value, to trigger an actual read, and retrieve the accessed register content till the completion Fast Read mode process is different from Normal Read mode, once the switch receives a fast read command followed by the register page and address information, the status and the data (register content) will be put on the the MISO MISO line line with withou outt goin going g thro throug ugh h the the SPI Stat Status us regis registe terr or SP SPII Data Data I/O I/O regi regist ster er.. Once Once RACK RACK bit bit of the the byte bytes s following the Fast Read command with Address information is recognized the register content will be put on MISO MISO line line imme immedi diat ately ely follo followi wing ng the the byte byte with with RACK RACK bit bit set. set. The The Fast Fast Read Read proc proces ess s is desc descri ribe bed d in the the follo followi wing ng paragraphs with a flowchart followed by a step by step description.


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BCM53128 Data Sheet


Figure Figure 25: Fast Read Read Operation Operation

Fast Read Mode Start

Step 1 Issue a Normal Read Command (opcode=60) to poll data from SPI SPI Status Regi Register ster (0xFE)

No SPIF (bit 7) =0?

No

Software Timeout ?

Yes

Yes


Yes

No Step 2 Issue a Normal Write Command (opcode=61) (opcode=61) t o write the accessed register page value value into SPI Page Register (0xFF)

Step 3

Issue a Fast Read Command (opcode=10) to setup the accessed acces sed register address value to trigger an actual read

Retrieve the first byte data to Retrieve check RACK is ready No No

RACK=1

Software Timeout ?

Yes

Yes

Retrieve the data starting from the lowest byte

Done

Issue a Normal Write Command (opcode=61) to write the accessed register page value value into SPI SPI Page Register (0xFF)

Task Abort


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BCM53128 Data Sheet


Example: Read from 1000BASE-T Control register (Page 10h, Offset 12h). 1. Issue a Normal Read command command (opcode (opcode = 0x60) to check the SPIF bit in the SPI Status register register (0xFE). (0xFE). • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Read Read Command Command Byte: Byte: 0 1 1 0 0 0 0 0(opcode 0(opcode = 0x60) • Clock in the SPI Status Status registe registerr address address (0xFE) (0xFE) • Clock in the the accessed accessed register register page page value: 0 0 0 0 0 0 0 0 (SPIF bit 7=0) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 26: Normal Normal Read Mode to Check the SPIF Bit of SPI Status Register Register

2. Issue a Normal Write Write command (opcode (opcode = 0x61) and write the accessed accessed register register page value of 0x10 in to SPI Page Reigster(0xFF) —this step is required only if previous read/write was not to/from Page 10h. • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock Clock in a Fast Fast Read Comm Command and Byte: Byte: 0 11 0 0 0 0 0 1 (opcod (opcode e = 0x61) • Clock in offset offset of of Page Page register register (0xFF) (0xFF) • Clock in the the accessed accessed register register page page value: 0 0 0 1 0 0 0 0 (Page register: register: 0x10) 0x10) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 27: Fast Read Mode Mode to Setup New Page Value Value


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BCM53128 Data Sheet


3. Issue a Fast Read command (opcode = 0x10), followed by the Address of the accessed register (0x12), check for a read completion by checking the RACK bit in the SPI Status register, and finally clock out the read data. • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock Clock in a Fast Fast Read Comm Command and Byte: Byte: 0 0 0 1 0 0 0 0 0 (opcode (opcode = 0x10) 0x10) • Clock in the Address Address of of accessed accessed register register (0x12) (0x12) • Clock Clock out Byte Bytes s Until Until Bit 0 or Bit Bit 1 = 1 : 0 0 0 0 0 0 0 1 (RACK bit bit 0=1) 0=1) • Clock Clock out firs firstt data byte byte:: 0 0 0 0 0 0 0 0 (Byte (Byte 0: Bit Bit 7 to Bit 0) • Clock out out next data data (in this this case, last) last) byte: byte: 0 0 0 0 1 1 1 0 (Byte 1: Bit 15 to to Bit 8) • [Cont [Continu inue e if more more bytes bytes]] • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure 28: Fast Read to Read the Register Register

Note: There Note: There is an errata on the RACK output timing in Fast Read mode. The RACK (bit 0) must be sampled prior to toggling the clock to shift out the bit 0.

Normal Write Operation Normal Write operation consists of 3 transactions (three SS operations) 1. Issue a Normal Read Command Command (opcode = 0x60) to poll the SPIF bit in the SPI Status register (0xFE) (0xFE) to determine the operation can start. 2. Issue a Normal Write Write command (opcode (opcode = 0x61) to setup the accessed accessed register register page value into the page register (0xFF). 3. Issue a Normal Write command (opcode = 0x61) to setup the accessed register address value, followed by the write content starting from a lower byte. The Normal Write Mode process is described in the following paragraphs with a flowchart followed by a step by step description. Note: The Note: The RoboSwitch does not support Fast Write Mode.


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BCM53128 Data Sheet


Figure 29: Normal Normal Write Operation Operation

Normal Norm al Wr Write ite Mode Mode Start

Step 1 Issue a Normal Read Command (opcode=60 (opcode=60)) to poll data from SPI Status SPI Status Register (0xFE)

No No

SPIF=0?

Software Timeout ?

Yes


Yes

Yes

No Step 2 Issue a Normal Nor mal Write Write Command (opcode=61) to write the acces accessed sed register page value into SPI Page Register (0xFF)

Issue a Normal Write Command (opcode=61) to write the accessed accessed register page value value into SPI SPI Page Register (0xFF)

Step 3 Issue a Normal Nor mal Write Write Command (opcode=61) to setup the accessed register address,, followed by the write address content starting from the lowest byte

Task Abort

Done

Example: 0x1600h is written to 1000BASE-T Control Register (Page 0x10, Offset 0x12). 1. Issue a Normal Read command command (opcode (opcode = 0x60) to check the SPIF bit in the SPI Status register register (0xFE). (0xFE). • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Read Read Command Command Byte: Byte: 0 1 1 0 0 0 0 0 (opcode (opcode = 0x60) 0x60) • Clock in the SPI Status Status registe registerr address address (0xFE) (0xFE) • Clock in the the accessed accessed register register page page value,: value,: 0 0 0 0 0 0 0 0 (SPIF bit 7=0) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state


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BCM53128 Data Sheet


Figure Figure 30: Normal Normal Read Mode to Check the SPIF Bit of SPI Status Register Register

2. Issue a Normal Write Write command (opcode (opcode = 0x61) and write the accessed accessed register register page value of 0x10 into SPI Page register (0xFF)—this step is required only if previous read/write was not from/to Page 0x10. • Assert Assert SS SS while while SCK SCK is high high idle stat state e • Clock in a Normal Normal Write Write Command Command Byte: Byte: 0 1 1 0 0 0 0 1 (opcode (opcode = 0x61) • Clock in offset offset of of Page Page register register (0xFF) (0xFF) • Clock in 1 byte byte of the accessed accessed regist register er page value value (Page regist register er 0x10) • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 31: Normal Normal Write to Setup the Register Register Page Value

3. Issue a Normal Write command command (opcode = 0x61) and write the Address Address of the accessed register followed by the write content starting from a lower byte. •

Assert Assert SS while while SCK is high high idle idle stat state e • Clock in a Normal Normal Write Write Command Command Byte: Byte: 0 1 1 0 0 0 0 1 (opcode (opcode = 0x61) • Clock in Offset Offset of Address Address of accessed accessed registe registerr (0x12) (0x12) • Clock Clock in lower lower data data byte firs first: t: 0 0 0 0 0 0 0 0 (Byte (Byte 0: Bit 7 to Bit 0) 0) • Clock Clock in upper upper data data byte byte next: next: 0 0 0 1 0 1 1 0 (Byte (Byte 1: Bit 15 15 to Bit 8) • [Cont [Continu inue e if more more bytes bytes]] • Deassert Deassert SS SS while while SCK SCK is high high idle idle state state Figure Figure 32: Normal Normal Write to Write the Register Register Address Address Followed by Written Data


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BCM53128 Data Sheet


EEPROM Interface The BCM53128 can be connected using the serial interface to a low-cost external serial EEPROM, enabling it to download download register-pr register-program ogramming ming instruction instructions s during power-on power-on initializati initialization. on. For each programmin programming g instructio instruction n fetched from the EEPROM, the instruction executes immediately and affects the register file. During During the chip-i chip-init nitiali ializat zation ion phase, phase, the data data is sequen sequentia tially lly read-i read-in n from from the EEPROM EEPROM after after the intern internal al memory memory has been cleared. The first data read-in is the HEADER and it matches a predefined magic code. In the case where the HEADER data does not match the instruction fetch, the process stops, and the EEPROM controller treats it as if no EEPROM exists. If the magic code matches, the fetch instruction process continues until it reaches the instruction length defined in the HEADER. Due to the differ different ent access access cycles cycles of differ different ent capacit capacity y EEPROMs EEPROMs,, the strap strap pins pins EEPROM_ EEPROM_TYPE TYPE[1: [1:0] 0] are used used to support the various EEPROM devices according to Table to Table 26. 26. Table 26: EEPROM_TYPE[1:0] EEPROM_TYPE[1:0] Settings Settings EEPROM_TYPE[1:0]

EEPROM

00

93C46

01

93C56

10

93C66

11

93C86 Figure 33: Serial EEPROM EEPROM Connection

BCM53128

93C46/56/66/86

SS

CS

SCK

SK

MOSI

DI

MISO

DO

EEPROM Format The EEPROM should be configured configured to x16 word format. The header contains key and length length informatio information n as shown in Table in Table 27. 27. The actual data stored in the EEPROM is byte-swapped as shown in Table in Table 28. 28. •

Upper 5 bits bits are magic magic code 15h, 15h, which indicat indicates es that valid valid data follows follows..

•

Bit 10 is for speed speed indication indication.. A 0 means normal normal speed. speed. A 1 indicates indicates speedup. speedup. The default default is 0.

•

Lower 10 10 bits indicat indicate e the total total length length of all all entries. entries. For example: example: – 93C46 up to 64 words – 93C56 up to 128 words – 93C66 up to 256 words – 93C86 up to 1024 words


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BCM53128 Data Sheet


Table 27: EEPROM EEPROM Header Header Format Bits [15:11}

Bit 10

Bits [9:0]

Magic code, 15h

Speed

Total entry number 93C46: 0 ~ 63 93C56: 0 ~ 127 93C66: 0 ~ 255 93C86: 0 ~ 1023

Table 28: EEPROM EEPROM Contents Contents Bits [7:0]

Bits [15:11]

Bit 10

Bits [9:8]

Total entry number

Magic code, 15h

Speed

Total entry number

Figure 34 shows 34 shows an EEPROM programming example. Figure 34: EEPROM Programming Example Example 15 00

7 101010001 101010101

6 0

5

0

0000000000 10 A890

Page:10'h Page:11'h

01

FFFF

01

FF01

02

00

1 00 2

: 101010101 0010 MCMC:

03

3 00 6

01

3001

04

0 41 3

2 31C

013C

FF

01

FF01

05

0 20 2

11

07

30

01

08

0 66 1

3C

06

Write Offset Off set :30'h Data:013C’ h Offset Off set :30'h Data:013C’ h

S : 0 (Normal)

Address FF’h (Page) Page # 00'h

0011 3001

Offset 30’h Data 01'h Address FF’h (Page)

. .

. .

Data Entry Num . # 01 Page # 10'h Data Entry Num . # 01

Data 3C'h Data Entry Num . # 01

013C Page # 00'h

. .

TOTAL TOTAL ENTRY ENTRY NUM NUM : 08 08 'h

Offset 30’h Data 01'h

Page # 11'h Data Entry Num . # 01

Data 3C'h

3F

EEPROM EEPR OM Serial Stream: Stream: 90 A8 01 FF F F 10 00 01 30 3C 01 01 FF 11 00 01 30 3 C 01


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BCM53128 Data Sheet

MDC/MDIO Interface

MDC/MDIO Interface BCM53128 offers an MDC/MDIO interface for accessing the switch registers as well as the PHY registers. An external management entity can access the switch registers through this interface when the SPI interface is not used. (i.e., when the SPI clock is in idle mode.) The switch registers are accessed through the Pseudo PHY interface, and the PHY registers are accessed directly by using PHY addresses. Exte Extern rnal al PHY PHY can can be conn connec ecte ted d to GMII GMII inte interf rfac ace e of IMP IMP port port.. Thro Throug ugh h the the SP SPII inte interf rfac ace, e, by acce access ssin ing g the the Page Page 88h, the external PHY MII registers registers can be accessed. The actual PHY address address can be assigned through the MDIO IMP Port Address register. Note: The Note: The PHY registers are not accessible through the Pseudo PHY operation.

MDC/MDIO Interface Register Programming The The BCM5 BCM531 3128 28 are are desi design gned ed to be fully fully comp complia liant nt with with the the MII MII clau clause se of the the IEEE IEEE 802. 802.3u 3u Ethe Ethern rnet et spec specif ific icat atio ion. n. The MDC pin of the BCM53128 sources a 2.5-MHz clock. Serial bidirectional data transmitted using the MDIO pin is synchronized synchronized with the MDC clock. clock. Each MII read or write write instruction instruction is initiated by the BCM53128 and contains the following: •

Preamble (PRE). (PRE). To signal the beginning of an MII instruction instruction after reset, reset, at least 32 consecutive 1-bits 1-bits must be written to the MDIO pin. A preamble of 32 1-bits is required only for the first read or write following reset. reset. A preamble preamble of fewer fewer than 32 1-bits causes the remainder remainder of the instruction instruction to be ignored.

•

Start of Frame ( Frame (ST). ST). A A 01 pattern indicates that the start of the instruction instruction follows.

•

Operation Code ( Code (OP) OP).. A read instruction is indicated by 10, while a write instruction is indicated by 01.

•

PHY Address ( Address (PHYAD) PHYAD).. A 5-bit PHY address follows, with the MSB transmitted first. The PHY address allows a single MDIO bus to access multiple PHY chips.

•

Register Address ( Address (REGAD) REGAD).. A 5-bit register address follows, with the MSB transmitted first.

• Turnaround ( Turnaround (TA). TA). The The next bit times are used to avoid contention contention on the MDIO pin when a read operation operation is performed. When a write operation is being performed, 10 must be sent by the BCM53128 chip during these two bit times. When a read operation is being performed, the MDIO pin of the BCM53128 must be put in a high-impedance state during these bit times. The external PHY drives the MDIO pin to 0 during the second bit time. • Data. The Data. The last 16 bits of the Instruction are the actual data bits. During a write operation, these bits are written to the MDIO pin with the most significant bit (MSB) transmitted first by the BCM53128. During a read operation, the data bits are driven by the external PHY with the MSB transmitted first.


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BCM53128 Data Sheet

MDC/MDIO Interface

PseudoPHY The MDC/MDIO can be used by an external management entity to read/write register values internal to the BCM531 BCM53128. 28. This This mode mode offers offers an altern alternati ative ve progra programmi mming ng interf interface ace to the chip. chip. The BCM531 BCM53128 28 operat operate e in slave slave mode with a PHY address of 30d. The following figures show the register setup flow chart for accessing the registers using the MDC/MDIO interface. Figure 35: PseudoPHY MII MII Register Definitions

Reg 0

IEEE Reserved

Reg 15

P age Number

Res erv ed

Regi s ter A ddres s

Res erv ed

Acc ess Status

A OP

Reg 16 Reg 17 Reg 18

Reserved

Ac ces s regis ter bits [15:0]

Reg 24

Acc ess register bi ts [31:16]

Reg 25

Acc ess register bit s [47:32] [47:32]

Reg 26

Ac ces s regis ter bits [63:48]

Reg 27

Reserved

Reg 31


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BCM53128 Data Sheet

MDC/MDIO Interface

Figure 36: PseudoPHY MII Register 16: Register Register Set Access Control Bit Definition Definition 15

14

13

12

11

10

9

8

7

5

6

Page Number

4

3

2

1

Reserved

0

Bit #

A

Reg 1 6

Bits [15:8] => Pa ge number ( RW) Bits [71] => Re served Bit 0 => Re gister s et MD C/ MDI MDIO a ccess e nable ( RW)

Note: The Note: The bit 0 (MDC/MDIO Access Enable) in register 16 should be released (set to 0) after a transaction is completed. This allows the SPI interface to access the switch register if required. Figure 37: PseudoPHY MII Register Register 17: Register Set Read/Write Control Control Bit Definition 15

14

13

12

11

10

9

8

7

6

Register A ddress

5

4

3

2

Reserved

1

0

OP

Bit #

Reg 1 7

Bits [15:8] => Re gister a ddress ( RW) Bits [7:2] => Re served Bits [1:0] => OP cod e ( RW/SC),00 = No operation 01 = Wr ite operation 10 = Rea d o peration 11 = Re served


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BCM53128 Data Sheet

MDC/MDIO Interface

Figure 38: PseudoPHY MII Register 18: Register Register Access Status Bit Definition Definition 15

14

13

12

11

10

9

8

7

6

5

4

3

2

Reserved

1

0

Bit #

E

P

Reg 1 8

Bits [15:1] => Re served Bit 1 => Operation Error ( RO/ LH), LH), when o p_code = 2 'b11, t his bit is set to show o peration error. Bit 0 => Pr ohibit A ccess ( RO/ LH), LH), for Pa ge Number = 8'h1X, w hich are PHY MII re gisters.

Figure 39: PseudoPHY MII Register Register 24: Access Register Bit Definition Definition 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Access re gister bits [15:0]

Bit #

Reg 24

Bits [15:0] => A ccess re gister bits [15:0] ( RW)


14

13

12

11

10

9

8

7

6

5

4

3

2


1

0

Bit #

Reg 25



Page 115


BCM53128 Data Sheet

MDC/MDIO Interface


14

13

12

11

10

9

8

7

5

6

4

3

2

1

0


Bit #

Reg 2 6



14

13

12

11

10

9

8

7

6

5

4

3

2


1

0

Bit #

Reg 2 7



Page 116


BCM53128 Data Sheet

MDC/MDIO Interface

Figure 43: Read Access to the Register Set Using the PseudoPHY PseudoPHY (PHYAD = 11110) MDC/MDIO MDC/MDIO Path

Write MII re gister 1 6: Set bit 0 as 1 Set Pa ge Number to bits [15:8]

Write MII re gister 1 7: Set Operation C ode as 10 Set register address to bits [ 15:8]

Read MII re gister 1 7: Check o p_code = 00 ?

No

Yes Read MII re gister 24: for A ccess re gister bits [15:0]

Read MII re gister 25: for A ccess re gister bits [31:16]

Read MII re gister 2 6: for A ccess re gister bits [47:32]

Read MII re gister 2 7: for A ccess re gister bits [63:48]

No

New Pa ge Access?

Yes


Page 117


BCM53128 Data Sheet

MDC/MDIO Interface

Figure 44: Write Access to the Register Set Using Using the PseudoPHY (PHYAD (PHYAD = 11110) MDC/MDIO Path Path Write MII re gister 1 6: Set bit 0 as 1 Set Pa ge Number to bits [ 15:8]

Write MII re gister 24: for A ccess re gister bits [15:0]

Write MII re gister 25: for A ccess re gister bits [31:16]

Write MII re gister 2 6: for A ccess re gister bits [47:32]

Write MII re gister 2 7: for A ccess re gister bits [63:48]

Write MII re gister 1 7: Set Operation C ode as 01 Set register address to bits [ 15:8]

Read MII re gister 1 7: Check o p_code = 00 ?

No

Yes

No

New Pa ge A ccess?

Y es


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BCM53128 Data Sheet

LED Interfaces

Table 29 summarizes 29 summarizes the complete management frame format. Table 29: MII Management Management Frame Frame Format Operation

PRE

ST

OP

PHYAD

10

AAAAA

RRRRR

AAAAA

RRRRR

Read

1 ... 1

01

Write

1 ... 1

01

01

RE REGAD

TA TA ZZ ZZ Z0 10 10

Data

Direction

Z ... Z D ... D

Driven by master Driven by slave

D ... D

Driven to master

See “MDC/MDIO See “MDC/MDIO Interface” on page 112 for 112 for more information regarding the timing requirements.

LED Interfaces The BCM531 BCM53128 28 provid provides es flexib flexible le visibil visibility ity per-po per-port rt status status of variou various s functi functions ons.. The LED Interf Interface ace offers offers an option option to display different different functions for each port given the number of LED bits available. available. The BCM53128 BCM53128 provides a total of 32 LED pins. In a 5-port switch application, these are dedicated as four LED pins per port as shown in Table 30 on page 120. 120. If one or more ports are not used in an application and are disabled using LED Enable Map register (Page 00h: Address 16h), and no more than four LED pins are to be used per port, the locations of the pins for the enabled ports are the same as if all eight ports were used, with four pins reserved per port, regardless of whether the port is enabled. For example, if Port7~2 LED displays are disabled (value of register page 00h, address 16h = 0003), Port0 and Port1 LED display are still from LED pins LEDP28~31 (Port0), LEDP24~27 (Port1), just as if all eight ports were used. If Port1 and Port0 LED displays are disabled (value of register page 00h, address 16h = 00FC), Port5, Port6, and Port7 are still from LED pins LEDP8~11 (Port5), LEDP4~7 (Port6), and LEDP0~3 (Port7), also just as if all eight ports were used. To set up the LED interface, configure strap pins LED_MODE[1:0] or select the desired display the functions in the LED Function 0 Control register/LED Function 1 Control register. The per-port LED display is fixed with four functions. •

To configure configure the strap strap pins, set the the predefined predefined functions functions to be displayed displayed by setting setting the strap strap pins LED_MODE[1:0]. The predefined functions are described in “Signal in “Signal Descriptions” on page 125. 125. Per-port LED display is fixed four functions and occupy four LED pins.

•

To configure configure LED display display function function in the two LED Function Function Control Control registers, registers, assign assign each port to one of the LED Function 0 Control register and LED Function 1 Control register by enabling the bits in the LED Function Map register. The LED interface shifts out the status of the selected functions for ports enabled in the LED Enable Map register.

Only Only four four or less less than than four four func functi tion ons s can can be sele select cted ed,, and and the the perper-po port rt LED LED disp displa lay y occu occupie pies s four four LED LED pins pins (fixe (fixed d four four func functi tion ons) s).. For For exam exampl ple, e, if LED LED disp displa lay y func functi tion on usin using g LED LED Func Functi tion on 1 Cont Contro roll regis registe terr is conf config igur ured ed and and the the value is set to 0324h (four LED functions) functions) or 0320h (three LED functions), functions), the per-port LED display has four fixed functions and occupies four LED pins per port, Port7 (LEDP0~3), Port6 (LEDP4~7), ....Port0 (LEDP28~31). The status of enabled ports is sent out from a higher port number to the lowest port number. The output order that is in the shift out is from LEDP[0], LEDP[1], LEDP[2],…..LEDP[31]. The output port order for LED is from high port number to low port number, and the output bit order within the port LED is form MSB to LSB.


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BCM53128 Data Sheet

LED Interfaces

The LED MODE MAP 0 and 1 registers can be set to select: •

LED to blink blinkin ing, g,

•

LED LED on, on, or

•

LED auto auto mode mode..

Bit 7, LED_EN, of the LED Refresh register is default enabled. When this bit 7 is enabled, the LED display of each port status is normal and truly reflects each port link up/link down status. If bit 7 is disabled, the LED status is latched in its current state. LED LED sign signals als are are acti active ve low, low, and and for for the the dual dual func functi tion on LEDs LEDs,, LNK, LNK, DPX, DPX, and and Spee Speed d stat state e are are acti active ve low. low. The The ACT ACT (activity) indicator is indicated by blinking. Table 30: LED Output Output Pins Per Per Port Port

LED Output Pins

Port 7

LEDP [0:3]

Port 6

LEDP [4:7]

Port 5

LEDP [8:11]

Port 4

LEDP [12:15]

Port 3

LEDP [16: 19]

Port 2

LEDP [20:23]

Port 1

LEDP [24:27]

Port 0

LEDP [28: 31]

Figure 45 shows 45 shows the LED Interface register structure.


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BCM53128 Data Sheet

LED Interfaces

Figure 45: LED Interface Register Structure Structure Diagram LED Function Control Register 0 Availab Ava ilable le Functi Functions ons

LED Function Control Register 1 Availa Av ailable ble Functi Functions ons

Selected Functions

Selected Functions

15 : Reserved

15 : Reserved

14 : BroadSync HD Link

14 : BroadSync HD Link

13 : 1G/ACT

13 : 1G/ACT

12 : 10/100M/ACT

12 : 10/100M/ACT

11 : 100M/ACT

11 : 100M/ACT

10 : 10M/ACT

10 : 10M/ACT

1G/ACT

9 : SPD1G

9 : SPD1G

LNKL/ACTG

8 : SPDI00M

DPX/COL

8 : SPDI00M

7 : SPD10M

LNK

7 : SPD10M

LNKG/ACTL

6 : DPX/COL

6 : DPX/COL

SPD100M

5 : LNK/ACT

5 : LNK/ACT

4 : COL

4 : COL

3 : ACT

3 : ACT

2 : DPX

2 : DPX

1 : LNK

1 : LNK

0 : Reserved

0 : Reserved

Reserved

0 0

1

0

1 1

0

0

LED Function Map Register

Reserved

1 1

1

1

1 1

0

0

LED Enable Map Register

1 1

1 0

1 0

1

1 Port Mode Map 0 Register 0 1 0 1

1 0

0

1 1

0

0 Port Mode Map 1 Register 0 0 1 1

Reserved

7

1

6 5 4

3

2

1

0

Port/ Po rt/ Bit #

LED AUTO LED BLINK LED ON LED OFF

The BCM53128 offers two LED Interfaces, Parallel LED Interface and Serial Interface. As shown in Figure in Figure 46 on page 122, 122, the source of LED status stream is the same for both interfaces; the status bit stream is based on the programmed register settings. The Parallel LED Interface provides all the shifting and storing of the status internally, so that it does not require any external shift registers, but it requires more I/O pins to be connected on the part. The The Seria Seriall LED LED Inte Interf rfac ace e is bein being g outp output ut thro throug ugh h two two pins pins (LED (LEDDA DATA TA,, LEDC LEDCLK LK). ). It save saves s the the numb number er of I/O I/O pins pins,, but it requires requires the user to design in the external external shift registers. registers.


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BCM53128 Data Sheet

LED Interfaces

Figure Figure 46: LED Interface Interface Block Diagram Diagram

LED I/O Block LED C ontr ontrol ol Block LEDCLK LEDDATA LED[0]

Q

D

LED[1]

Q

D

LED[3]

Q

D

LED[31]

Q

D

Dual LED is used for displaying more than one status using one LED cell. By packing packing two different different colors LED into one holder, dual LED can display more than two states in one cell. Figure cell. Figure 47 shows 47 shows a typical dual LED usage. Green LED is to display LNKG/ACT status, while Yellow LED is to display LNKF/ACT status. Figure Figure 47: Dual LED Usage Usage Example Example

LNKF/ACT

Green LED

LNKG/ACT

Yellow LED


Page 122


BCM53128 Data Sheet

LED Interfaces

Dual Input Configuration/LED Output Function There are LED pins that have secondary functions. These pins serve as input pins during the power-on/reset sequence. sequence. The logic level of the pin is sampled at reset and configures configures the secondary secondary function. function. After the reset process is completed, the pin acts as an output LED during normal operation. The polarity of the output LED is determined based on the latched input value at reset. For example, if the value at the pin is high during reset, the LED output during normal operation is active-low. The user must first decide, based on the individual application, application, the values of the input configuration configuration pin shown in the following following table to provide provide the correct correct device configuration. The LED circuit must then be configured to accommodate either an active-low or active-high LED output (see Figure (see Figure 48). 48). Figure 48: LED Circuit for Dual Input Configuration/LED Configuration/LED Output Pins Pins


Page 123


BCM53128 Data Sheet

Hardware Signal Definition Table

S e c ti t i o n 5 : H a r d wa w a r e S i g n al a l D e f in i n i t i on on Table I/O Signal Types The following conventions conventions are used to identify the I/O types shown in Table in Table 31. 31. The I/O pin type is useful in referencing the DC-pin characteristics. Table 31: I/O Signal Signal Type Definitions Definitions Abbreviation

Description

XYZ

Active low signal

A

Analog pin type

B

Bias pin type

CS

Continuously sampled

D

Digital pin type

DNC

Do not connect

GND

Ground

I

Input

I/O

Bidirectional

IPU

Input with internal pull-up

O3S

Tristated Signal

ODO

Open-drain output

O

Output

OPU

Output with internal pull-up

OPD

Output with internal pull-down

PD

Internal pull-down

SOR

Sample on reset

PWR

Power pin supply

PU

Internal pull-up

XT

Crystal pin type


Page 124


BCM53128 Data Sheet

Signal Descriptions

Signal Descriptions Table 32: Signal Signal Type Definition Definitions s Signal Name

Type

Description

I A/O A

Transmit/Receive Pairs. In Pairs. In TRD [pair number]_[port number]± 1000BASE-T mode, differential data from the media is transmitted and received on all four signal pairs. In auto-negotiation and 10BASE-T and 100BASE-TX modes, the BCM53128 normally transmits on TRD[0]_[port number]± and receives on TRD[1]_{port number}±. Auto-MDIX operation can reverse the pairs TRD[0]_{7:0}± and TRD[1]_{7:0}±

IPU

Hardware Reset Input. Input. Active low Schmitt-triggered input. Resets the BCM53128.

Serial Interface TRD0_0+/TRD1_0+/TRD2_0+/TRD3_0+/TRD0_1+/TRD1_1+/TRD2_1+/TRD3_1+/TRD0_2+/TRD1_2+/TRD2_2+/TRD3_2+/TRD0_3+/TRD1_3+/TRD2_3+/TRD3_3+/TRD0_4+/TRD1_4+/TRD2_4+/TRD3_4+/TRD0_5+/TRD1_5+/TRD2_5+/TRD3_5+/TRD0_6+/TRD1_6+/TRD2_6+/TRD3_6+/TRD0_7+/TRD1_7+/TRD2_7+/TRD3_7+/Clock/Reset RESET


Page 125


BCM53128 Data Sheet

Signal Descriptions

Table 32: Signal Type Definitions Definitions (Cont.) (Cont.) Signal Name

Type

Description

XTALI

IXT

XTALO

OXT

25 MHz Crystal Oscillator Input/Output. Input/Output. A continuous 25 MHz reference clock must be supplied to the BCM53128 by connecting a 25 MHz MHz crys crysta tall betw betwee een n thes these e two two pins pins or by driv drivin ing g XTAL XTALII with with an exte extern rnal al 25 MHz oscillator clock. When using a crystal, connect a loading capa capaci cito torr from from each each pin pin to GND. GND. When When usin using g an oscil oscilla lato tor, r, leave leave XTAL XTALO O unconnected.

IMP Interface

MII/TMI MII/TMIII Transmit Transmit Clock. Clock. This This is an inpu inputt pin pin in MII MII mode mode,, or GMII GMII mode mode but speed is 100Mbps/10Mbps. It synchronizes the TXD[3:0] and conn connec ects ts to the the PHY PHY Enti Entity ty TX TXC. C. In 100 100 Mbps Mbps mode mode,, this this is 25 MHz, MHz, and and in 10 Mbps mode, this is 2.5 MHz. In 200 Mbps mode (TMII), this is 50 MHz. RvMII/RvTMII Receive Clock. This Clock. This is an output pin in RvMII mode. It synchronizes the TXD[3:0] in RvMII mode and connects to the MAC/ Management Management Entity Entity RXC. In 100 Mbps mode, this is 25 MHz, and in 10 Mbps mode, this is 2.5 MHz. In 200 Mbps mode (RvTMII), this is 50 MHz. This output output pin has an internal 25 -series -series termination termination resistor. resistor. This clock is not use in the other conditions.

IMP_TXCLK

I/O

IMP_TXD[3:0]

O

GMII Transmit Data Output (first nibble). nibble). Data bits TXD[3:0] are clocked on the rising edge of TXCLK. RGMII Transmit Data Output. Output. For 1000 Mbps operation, data bits TXD[3:0] are clocked on the rising edge of TXCLK, and data bits TXD[7:4] are clocked on the falling edge of TXCLK. For 10 Mbps and 100 Mbps, data bits TXD[3:0] TXD[3:0] are clocked on the rising edge of TXCLK. TXCLK. RvMII/RvTMII Receive Data Output. Output. Clocked on the rising edge of TXCLK and connected to the RXD pins of the external MAC/ Management entity. MII/TMII Transmit Data Output. Output. Clocked on the rising edge of TXCLK supplied by MAC/Management entity. These output output pins have internal internal 25 -series -series termination termination resistor. resistor.

IMP_TXD[7:4]

O

GMII Transmit Data Output (second nibble). nibble). Data bits [7:4] are clocked on the rising edge of TXCLK. These output pins have internal 25 -series -series terminat termination ion resistor resistor..

IMP_TXEN

O

GMII/MII/TMII GMII/MII/TMII Transmit Enable. Enable. Active high. TXEN indicates the data on the TXD pins are encoded encoded and transmitt transmitted. ed. RGMII RGMII Transmit Transmit Control Control.. On the the risin rising g edge edge of TXCL TXCLK, K, TXEN TXEN indic indicat ates es that a transmit frame is in progress, and the data present on the TXD[3:0] output pins is valid. On the falling edge of TXCLK, TXEN is a derivative derivative of GMII mode TXEN and TXER signals. RvMII/Rv RvMII/RvTMII TMII Receive Receive Data Valid Valid. Acti Active ve high. high. Conn Connec ecte ted d to RXDV RXDV pin of MAC/Management entity. Indicates that a receive frame is in progress, progress, and the data present on the TXD[3:0] TXD[3:0] output pins is valid. This output output pin has an internal 25 -series -series termination termination resistor. resistor.

IMP_TXER

O

GMII/MII GMII/MII/TMI /TMIII Transmit Transmit Error Error . Active Active high. high. Assert Asserting ing TXER TXER when when TXEN is high indicates a transmission error. TXER is also used to indicate Carrier Extension when operating in half-duplex mode. This output pin has an internal internal 25 -series -series termination termination resistor resistor..


Page 126


BCM53128 Data Sheet

Signal Descriptions


Type

Description

IMP_RXCLK

I

GMII Receive Clock. Clock. 125 MHz for 1000 Mbps operation. RGMII Receive Clock. Clock. 125 MHz for 1000 Mbps operation, 25 MHz for 100 Mbps operation, and 2.5 MHz for 10 Mbps operation. Data bits RXD[3:0] are clocked in on the rising edge of the RXCLK, and data bits RXD[7:4] are clocked in on the falling edge of the RXCLK. MII Receiv Receive e Clock. Clock. 25 MHz MHz for for 100 100 Mbps Mbps oper operat atio ion, n, and and 2.5 2.5 MHz MHz for for 10 Mbps operation. TMII Receive Clock. 50 Clock. 50 MHz for 200 Mbps operation.

O

RvMII/RvTMII Transmit Clock. Synchronizes Clock. Synchronizes the RXD[3:0] in RvMII/ RvTMII mode and connects to the MAC/Management entity TXC. RvMII RvMII Transmit Transmit Clock. Clock. 25 MHz MHz for for 100 100 Mbps Mbps mode mode,, and and 2.5 2.5 MHz MHz for for 10 Mbps mode. RvTMII Transmit Clock. 50 Clock. 50 MHz for 200 Mbps operation. This output pin has an internal 25-series termination resistor.

IMP_RXD[3:0]

I

GMII Receive Data Inputs (first nibble). nibble). Data bits RXD[3:0] are clocked on the rising edge of RXCLK. RGMII Receive Data Inputs. Inputs. For 1000 Mbps operation, data bits RXD[3:0] RXD[3:0] are clocked-out clocked-out on the rising edge of RXCLK, and data bits RXD[ RXD[7: 7:4] 4] are are cloc clocke ked d on the the fall fallin ing g edge edge of RXCL RXCLK. K. In 10 Mbps Mbps and and 100 100 Mbps modes, data bits RXD[3:0] RXD[3:0] are clocked on the rising edge of RXCLK. RvMII/RvTMII Transmit Data Inputs. Inputs. Clocked on the rising edge of RXCLK and connected to the TXD pins of the external MAC/ Management entity. MII/TMII Receive Data Input. Data Input. Data bits RXD[3:0] are clocked on the rising edge of RXCLK. RXCLK.

IMP_RXD[7:4]

I

GMII Receive Data Inputs (second nibble). nibble). Data bits RXD[7:4] are clocked out on the rising edge of RXCLK.

IMP_RXDV

I

GMII/MII/TMII GMII/MII/TMII Receive Data Valid. Valid. Active high. RXDV indicates that a receive frame is in progress, and the data present on the RXD output pins is valid. RGMII RGMII Receive Data Valid Valid. Functional Functional equivalent equivalent of GMII RXDV RXDV on the rising edge of RXCLK and functional equivalent of a logical derivative of GMII RXDV and RXER on the falling edge of RXCLK. RvMII/RvTMII Transmit Enable. Enable. Active high. Indicates the data on the RXD[3:0] pins are encoded and transmitted. Connects to the TXEN of the external MAC/Management entity.

IMP_RXER

I

GMII/MII/TMII GMII/MII/TMII Receive Error . Indicates an error during the receive frame.

IMP_CRS

I

Carrier Sense. Active-high, Sense. Active-high, indicates traffic on link

IMP_COL

I

Collision Collision Detect. Detect. In half-d half-dupl uplex ex mode, mode, active active-hi -high gh input input indica indicates tes that that a colli collisi sion on has has occu occurr rred ed.. In full full-d -dup uple lex x mode mode,, COL COL rema remains ins low. low. COL COL is an asynchronous input signal.


Page 127


BCM53128 Data Sheet

Signal Descriptions


Type

Description

IMP_GTX_CLK

O

GMII Transmit clock. This clock. This clock is driven to synchronize synchronize the transmit transmit data in 1000 Mbps speed in GMII mode. RGMII Transmit Clock. This Clock. This clock is driven to synchronize the transmit data in RGMII mode(125 MHz for 1000 Mbps operation, 25 MHz for 100 Mbps operation, and 2.5 MHz for 10 Mbps operation). In RGMII mode, both edges of the clock are used to align with TXD[3:0]. IMP_GTX_CL IMP_GTX_CLK K is used in RGMII and 1000 Mbps speed in GMII mode. IMP_TXCLK is used for MII mode, and 10/100 Mbps speed in GMII mode. This output output pin has an internal internal 25 -series -series termination termination resistor. resistor.

MDIO

I/OPD

Management Data I/O. In I/O. In master mode, this serial input/output data signal is used to read from and write to the MII registers of the external transceivers. In slave mode, it is used by an external entity to read/write to the switch registers via the Pseudo-PHY. See the MDC/MDIO interface for more information.

MDC

I/OPD

Management Data Clock. In Clock. In master mode, this 2.5 MHz clock sourced by BCM53128 to the external PHY device. In slave mode, it is sourced by an external entity.

MDC/MDIO Interface


Page 128


BCM53128 Data Sheet

Signal Descriptions


Type

Description

TCK

IPU

JTAG Test Clock Input. Clock Input. Clock Input used to synchronize JTAG control and data transfers. If unused, may be left unconnected.

TDI

IPU

JTAG Test Data Input. Serial Input. Serial data input to the JTAG TAP Controller. Samp Sample led d on the the risi rising ng edge edge of TCK. TCK. If unus unused ed,, may may be left left unco unconn nnec ecte ted. d. Shared with MOSI.

TDO

O

JTAG Test Data Output.

TM S

IPU

JTAG Mode Select Input.

TRST

IPU

JTAG Test Reset. Active low. Resets the JTAG controller. This signal must be pulled low during normal operation. operation.

Test Interface

Configuration/GPIO Pins CLK_FREQ1 or GPIO bit 1 CLK_FREQ0 or GPIO bit 0 System Clock Selection. Determines Selection. Determines rate of system clock via CLK_FREQ[1:0] value. 00 = 83 MHz 01 = 91 MHZ (normal operation) 10 = 100 MHz 11 = 111 MHz

CLK_ CLK_FR FREQ EQ1/ 1/GP GPIO IO1 1

IPD, SOR

CLK_ CLK_FR FREQ EQ0/ 0/GP GPIO IO0 0

IPU, SOR

CPU_ CPU_EE EEPR PROM OM_S _SEL EL

IPU, SO SOR R

CPU CPU or EEP EEPRO ROM M Inte Interf rfac ace e Selec Selecti tion on.. CPU_EEPROM_SEL = 0: Enable EEPROM interface. CPU_EEPROM_SEL = 1: Enable SPI Interface, The SPI interface has to be enabled (CPU_EEPROM_SEL = 1) for Pseudo-PHY accesses through the MDC/MDIO Interface. See ““Programming ““Programming Interfaces” on page 95 for 95 for more information.

HW_FWDG_EN/ GPIO7

IPD, SOR

HW_FWDG_EN or GPIO bit7 HW_FWDG_EN. Forw Forwar ardi ding ng Enab Enable. le. Acti Active ve high. high. If this this pin pin is pulle pulled d low low at power-up, frame forwarding is disabled.


Page 129


BCM53128 Data Sheet

Signal Descriptions


Type

Description

LED MODE[1]/GPIO4 LED MODE[0]/GPIO3

Bit 0: IPD, Bit 1: IPU, SOR

The following are LED Mode descriptions. LED Mode[1] or GPIO bit4, LED_MODE[0] or GPIO bit3 LED Mode. Users Mode. Users can select predefined functions to be displayed for each port by setting the bits accordingly. When LED MODE[1:0] = 00 FE configuration SPD100M LNK/ACT PHYLED4 GbE configuration SPD1G SPD100M LNK/ACT PHYLED4 When LED MODE[1:0] = 01 FE configuration 100M/ACT 10M/ACT DPX/COL PHYLED4 GbE configuration 1G/ACT 10/100M/ACT DPX/COL PHYLED4 When LED MODE[1:0] = 10 FE configuration SPD100M LNK/ACT DPX GbE configuration SPD1G SPD100M LNK/ACT DPX


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BCM53128 Data Sheet

Signal Descriptions


Type

Description When LED MODE[1:0] = 11 FE configuration 100M/ACT 10M/ACT DPX GbE configuration 1G/ACT 100M/ACT 10M/ACT DPX

LED MODE[1]/GPIO4 LED MODE[0]/GPIO3 (continued from previous page)

IMP_ IMP_SP SPD_ D_SE SEL[ L[1: 1:0] 0]

Bit Bit 0: IPD, Bit 1: IPU

IMP Port Speed Select. 00 = 10 Mbps 01 = 100 Mbps 10 = 1000 Mbps (default) 11 = 200 Mbps

IMP_MODE[1]/GPIO6 IMP_MODE[0]/GPIO5

Bit 0: IPU, Bit 1: IPU SOR

IMP Mode[1] or GPIO bit6, IMP_MODE[0] or GPIO bit5 IMP Port Mode. Sets Mode. Sets the mode of the IMP port based on the value of the pins IMP_MODE[1:0] at power-on reset. 00 = RGMII mode 01 = MII/TMII mode 10 = RvMII/RvTMII mode 11 = GMII mode

IMP_DUPLEX

IPU

IMP Port Duplex Mode. 0 = IMP in half-duplex mode 1 = IMP in full-duplex mode

IMP_LINK

IPD

IMP Port Link. 0 = IMP link-down 1 = IMP link-up

IMP_PAUSE_C IMP_PAUSE_CAP_RX AP_RX IPU

Enable IMP Port Pause Capable in RX. 0 = Disable Pause capable 1 = Enable Pause capable

IMP_PAUSE_C IMP_PAUSE_CAP_TX AP_TX IPU

Enable IMP Port Pause Capable Capable in TX. 0 = Disable Pause capable 1 = Enable Pause capable

IMP_ IMP_VO VOL_ L_SE SEL[ L[1: 1:0] 0]

IPD

IMP Interf Interface ace Voltag Voltage e Contro Control. l. RGMII need needs s to be set set to 01 for for 2.5V 2.5V or 1x for 1.5V. GMII/MII/TMII/RvMII/RvTMII needs to be set to 00 for 3.3V. 00: 3.3V 01: 2.5V 10 or 11: 1.5V

April 6, 2016 • 53128-DS07-R

Page 131

Broadcom ®


BCM53128 Data Sheet

Signal Descriptions


Type

Description

EN_CLK25_OUT/ CLK25_OUT

O, I PD, SOR Enable Enable CLK25 CLK25 Out and CLK_25 CLK_25 Output Output.. En_C En_CLK LK25 25_O _Out ut is a stra strap p pin pin function. 0 = Disable clock out 1 = Enable clock out


O, I PD, SOR Enable Enable CLK50 CLK50 Out and CLK_50 CLK_50 Output Output.. En_C En_CLK LK50 50_O _Out ut is a stra strap p pin pin function. 0 = Disable clock out 1 = Enable clock out

ACT_LOOP_DET

IPD

Loop Detection Feature Activation. 0 = Disable 1 = Enable

LOOP LOOP_D _DET ETEC ECTE TED D

OPD

Loop Found. This Found. This signal is to indicate there is a loop detected in the local network connection. 0 = Not detected 1 = Loop detected

EN_EEE

IPU

EN_EEE (Energy Efficient Ethernet). Enables Ethernet). Enables EN_EEE feature for switch MAC. 0 = Disable 1 = Enable

EN_8051_TxRx

IPD

GPIO2

I/O

EN_8051_TxRx. Enables EN_8051_TxRx. Enables 8051 transmitting and receiving packets capability. 0 = Disable 1 = Enable GPIO bit 2


Page 132


BCM53128 Data Sheet

Signal Descriptions


Type

Description

LEDP0

O

Port 7 Parallel LED Indicators. Active Indicators. Active low.

LEDP1

O


LEDP2

O

Port 7 Parallel LED Indicators. Active Indicators. Active high.

LEDP3/ P3/En_Green

O, IPD, SOR This is a dual dual func functio tion n pin: pin: Port Port 7 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. Green Mode Enable. Sampled on reset. 1= Enable Green Green mode 0= Disable Green mode

LEDP4

O

Port 6 parallel LED Indicators. Active Indicators. Active low.

LEDP5

O


LEDP6

O


LEDP7

O

Port 6 parallel LED Indicators. Active Indicators. Active high.

LEDP8

O


LEDP9

O


LEDP10/ EEPROM_TYPE0

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port Port 5 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. Extended EEPROM Interface Selection. Sampled Selection. Sampled on reset. EEPROM_TYPE[1:0] = 00: Supports 93C46 EEPROM EEPROM_TYPE[1:0] = 01: Supports 93C56 EEPROM EEPROM_TYPE[1:0] = 10: Supports 93C66 EEPROM EEPROM_TYPE[1:0] = 11: Supports 93C86 EEPROM

LEDP11/ EEPROM_TYPE1

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port Port 5 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. Extended EEPROM Interface Selection. Sampled Selection. Sampled on reset. EEPROM_TYPE [1:0] = 00: Supports 93C46 EEPROM EEPROM_TYPE [1:0] = 01: Supports 93C56 EEPROM EEPROM_TYPE [1:0] = 10: Supports 93C66 EEPROM EEPROM_TYPE [1:0] = 11: Supports 93C86 EEPROM

LEDP12

O


LEDP13

O


LEDP14/ LOOP_DET_EN

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port Port 4 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. Enable Loop Detection Mode. Sampled Mode. Sampled on reset. 0 = Disable 1 = Enable

LED Interface


Page 133


BCM53128 Data Sheet

Signal Descriptions


Type

Description

LEDP15/ LOOP_IMP_SEL

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port Port 4 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. Exclude IMP Port in Loop Detection Function. Sampled Function. Sampled on reset. 0 = Exclude IMP port from loop detection function function 1 = Include IMP port in loop detection function

LEDP16

O


LEDP17

O


LEDP18/ BC_SUPP_EN

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port 3 Parallel LED Indicators. Polarity Indicators. Polarity determined at reset. “Dual reset. “Dual Input Configuration/LED Output Function” on page 123. 123. Broadcast Suppression Enable. Sampled Enable. Sampled on reset. See “Rate See “Rate Control” on page 45 for 45 for more information. 0=Disable rate-based broadcast suppression. 1=Enable rate-based broadcast suppression.

LEDP19

O

Port 3 Parallel LED Indicators. Active Indicators. Active high.

LEDP20

O


LEDP21

O


LEDP22 P22/ DIS_IMP

O, IPD, SOR This is a dual dual func functio tion n pin. pin. Port Port 2 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. Disables IMP Port. Sampled Port. Sampled on reset. 0 = Enable IMP port 1 = Disable IMP port, and external pull-up resister resister is required. required.

LEDP23/ O, I PD, SOR This is a dual dual func functio tion n pin. pin. IMP_DUMB_FWDG_E Port Port 2 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual N Input Configuration/LED Output Function” on page 123. 123. IMP Port in Blocking State for Unmanaged Mode. Sampled Mode. Sampled on reset. When When this this pin is pulled pulled up, up, the IMP IMP port port is not in manage managemen mentt mode, mode, the the IMP port is in a regular port. 0 = Blocking for dumb mode 1 = Forwarding for dumb mode LEDP24

O


LEDP25

O


LEDP26/ ENFDXFLOW O, IPU, SOR This is a dual dual func functio tion n pin. pin. Port 1 Parallel LED Indicators. Polarity determined at reset. See “Dual See “Dual Input Configuration/LED Output Function” Functi on” on page 123. 123. Enable Automatic Full-Duplex Flow Control. Sampled Control. Sampled on reset. In combination with the results of auto-negotiation, sets the flow control mode. See “Flow See “Flow Control” on page 69 for 69 for more information.


Page 134


BCM53128 Data Sheet

Signal Descriptions


Type

Description

LEDP27/ ENHDXFLOW

O, I PU, SOR This is a dual dual funct function ion pin. Port 1 Parallel LED Indicators. Polarity determined at reset. See “Dual See “Dual Input Configuration/LED Output Function” Functi on” on page 123. 123. Enable Automatic Backpressure. Sampled Backpressure. Sampled on reset. When this pin is pulled high, it enables enables half-duplex backpressur backpressure e flow control when a port is configured to half-duplex. See “Flow See “Flow Control” on page 69. 69.

LEDP28

O


LEDP29

O


LEDP30/ IMP_TXC_DELAY

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port Port 0 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. TXCLK Clock Timing Delay. Sampled Delay. Sampled on reset. Active high. This pin enables the TXCLK to data timing delay in RGMII mode. See “RGMII See “RGMII Interface Timing” on page 304. 304.

LEDP31/ IMP_RXC_DELAY

O, I PD, SOR This is a dual dual func functio tion n pin. pin. Port Port 0 Parall Parallel el LED Indica Indicator tors. s. Polarit Polarity y determ determined ined at reset. reset. See “Dual Input Configuration/LED Output Function” on page 123. 123. RXCLK Clock Timing Delay. Sampled Delay. Sampled on reset. Active high. This pin enable enables s the RXCLK RXCLK to data-s data-samp ampling ling timing timing delay. delay. See“RGM See“RGMII II Inter Interface face Timing” on page 304. 304.

LEDCLK

OPD

LED Shift Shift Clock. Clock. This This cloc clock k is peri period odic icall ally y acti active ve to enab enable le LEDD LEDDATA ATA to shift into external registers.

LEDDATA

OPD

Serial Serial LED Data Data Output Output.. Seri Serial al LED LED data data for for all all port ports s is shif shifte ted d out out when when LEDCLK is active. LEDMODE[1:0] pins set the serial data content. See “LED Interface” on page 133 for 133 for a functional description of this signal.

Programming Interfaces SCK

SS/CS

IPD

SPI Serial Clock. The Clock. The clock input to the BCM53128 SPI interface is supplie supplied d by the SPI master master,, which which supports supports up to 2 MHz, and is enabled enabled if CPU_EPROM_SEL is high during power-on reset.

OPD

EEPROM Serial Clock. The Clock. The clock output to an external EEPROM device, and is enabled if CPU_EPROM_SEL is low during power-on reset. See the programming interfaces for more information.

IPU

OPU

SPI Slave Slave Select Select.. Active low signal which enables an SPI interface read or write write operat operation ion.. Enable Enable if CPU_EP CPU_EPROM ROM_SE _SEL L is high high during during powerpower-on on reset. EEPROM Chip Select. Active Select. Active high control signal that enables a read operation from an external EEPROM device. Enable if CPU_EP CPU_EPROM ROM_SE _SEL L is low during during powerpower-on on reset. reset. See the progra programmi mming ng interfaces for more information.


Page 135


BCM53128 Data Sheet

Signal Descriptions


Type

Description

MOSI/DI

IPU

SPI Master-Out/Slave-in. Master-Out/Slave-in. Input Input signal which receives control and address information for the SPI interface, as well as serial data during write write operat operation ions. s. Enable Enabled d if CPU_EPR CPU_EPROM_ OM_SEL SEL is high during during powerpower-on on reset.

OPU

EEPROM Data In. Serial In. Serial data input of an external EEPROM device. Enabled if CPU_EPROM_SEL is low during power-on reset. See the programming interfaces for more information.

OPU

SPI Master-In/Slave-Out. Master-In/Slave-Out. Output Output signal which transmits serial data during an SPI interface read operations. Enabled if CPU_EPROM_SEL is high during power-on reset.

IPU

EEPROM Data Out. Serial Out. Serial data output of an external EEPROM device. Enable if CPU_EPROM_SEL is low during power-on reset. See the programming interfaces for more information.

F SO

OPD

Serial Data Output.

FCSB

OPD

Chip Select.

FCLK

O

Clock Output.

FSI

IPD

Serial Data Input.

MISO/DO

Serial Flash Interfaces

Interrupt Pin INT

O3S

Interrupt. This Interrupt. This interrupt pin generates an interrupt based on the configuration of the Interrupt Enable Register and the Interrupt Status Register.

Bias GPHY1_RDAC

B

A 1.24-k

resistor to GND is required.

GPHY2_RDAC

B

A 1.24-k

resistor to GND is required.

AVDDH

PWR

3.3V Analog I/O Power.

AVDDL

PWR

1.2V Analog Core Power. P ower.

DVDD

PWR

1.2V Digital Core Power.

OVDD

PWR

Power for GMII/RGMII/MII/RvMII/ GMII/RGMII/MII/RvMII/TMII/RvTMII TMII/RvTMII of IMP. Depends on IMP_VOL_SEL[1:0] configuration. 00 = 3.3V if IMP_VOL_SEL[1:0] 01 = 2.5V if IMP_VOL_SEL[1:0] 10 or 11 = 1.5V if IMP_VOL_SEL[1:0]

OVDD2

PWR

3.3V Digital I/O Power.

GPHY1_BAVDD

PWR

3.3V Analog Power.

GPHY2_BAVDD

PWR

3.3V Analog Power.

PLL_AVDD

PWR

1.2V Analog Power.

GPHY1_PLLDVDD

PWR

1.2V Analog Power.

GPHY2_PLLDVDD

PWR

1.2V Analog Power.

XTAL_AVDD

PWR

3.3V Analog Power.

IMP_VOL_REF

PWR

IMP Interface Reference Power. Connect Power. Connect this pin to ground.

Power Interfaces


Page 136


BCM53128 Data Sheet

Signal Descriptions


Type

Description

PLL_AVSS

GND

Shared Digital Ground.

XTAL_AVSS

GND

Shared Digital Ground.

EXPOSEPAD

GND

Ground.

DNC

Do not connect.

No Connect NC


Page 137


BCM53128 Data Sheet

Pin Assignment

S e c ti t i o n 6 : P i n A s s ig i g n m e nt nt BCM53128KQLE Pin List by Signal Name Signal

Ball

ACT_LOOP_DETEC 59 T

Signal

Ball

CPU_EEPROM_SEL 18 DVDD

16

AVDDH

74

AVDDH

80

AVDDH

86

AVDDH

92

DVDD

53

AVDDH

103

DVDD

135

AVDDH

109

DVDD

148

AVDDH

115

DVDD

162

AVDDH

121

DVDD

169

AVDDH

203

DVDD

183

AVDDH

209

EN_8051_TxRx

47

AVDDH

215

AVDDH

221

AVDDH

232

AVDDH

238

AVDDH

244

AVDDH

250

AVDDL

71

AVDDL

77

AVDDL

83

AVDDL

89

AVDDL

95

AVDDL AVDDL AVDDL

100 106 112

DVDD

27

DVDD

31

DVDD

40


26


21

EN_EEE

38

EXPOSEPAD

H

FCSB

65

FSCLK

66

FSI

67

F SO

64

GPHY1_BVDD

227

GPHY GPHY1_ 1_PL PLLV LVDD DD

226 226

GPHY1_RDAC

228

GPHY2_BVDD

97

GPHY GPHY2_ 2_PL PLLV LVDD DD

98

GPHY2_RDAC

96

GPIO2

10 9

AVDDL

118

AVDDL

124

AVDDL

200

AVDDL

206

HW_FWDG_EN/ GPIO7

AVDDL

212

IMP_COL

159

AVDDL

218

IMP_CRS

143

AVDDL

224

IMP_DUPLEX

52

AVDDL

229

IMP_GTXCLK

132

AVDDL

235

IMP_LINK

54

AVDDL

241

IMP_MODE0/ IMP_MODE0/GPIO GPIO5 5 7

AVDDL

247

IMP_MODE1/ IMP_MODE1/GPIO GPIO6 6 8

AVDDL

253

IMP_PAUSECAP_R 55 X

CLK_FREQ0 CLK_FREQ0/GPI /GPIO0 O0 14 CLK_FREQ1 CLK_FREQ1/GPI /GPIO1 O1 15

Signal

Ball

Signal

Ball

IMP_PAUSECAP_T X

56

LEDP6

176

LEDP7

177

IMP_RXCLK

144

LEDP8

178

IMP_RXD0

150

LEDP9

179

IMP_RXD1

151 152

LEDP10/ EPROM_TYPE0

181

IMP_RXD2 IMP_RXD3

154

182

IMP_RXD4

155

LEDP11/ EPROM_TYPE1

IMP_RXD5

156

LEDP12

184

IMP_RXD6

157

LEDP13

185

LEDP14/ 186 LOOP_DETECT_EN

IMP_RXD7

158

IMP_RXDV

149 147


188

IMP_RXER IMP_SPEED0

51

LEDP16

189

IMP_SPEED1

50

LEDP17

190

IMP_TXCLK

141

191

IMP_TXD0

137

LEDP18/ BC_SUPP_EN

IMP_TXD1

136

LEDP19

192

IMP_TXD2

134

LEDP20

194

IMP_TXD3

131

LEDP21

195

IMP_TXD4

130

LEDP LEDP22 22/D /DIS IS_I _IMP MP

196 196

IMP_TXD5

128

IMP_TXD6

127

LEDP23/ 197 IMP_DUMB_FWDG_ EN

IMP_TXD7

126

LEDP24

198

IMP_TXEN

139

LEDP25

199

IMP_TXER

140 146

LEDP26/ ENFDXFLOW

254

IMP_VOL_REF IMP_V MP_VO OL_S L_SEL0 EL0

49

255

IMP_V MP_VO OL_S L_SEL1 EL1

48

LEDP27/ ENHDXFLOW

INTR_B

60

LEDP28

256

LEDCLK

167

LEDP29

1

LEDDATA

166


2


4

LEDMODE1/ LEDMODE1/GPIO4 GPIO4 13 LEDP0

168

LOOP_D LOOP_DETE ETECTE CTED D

58

LEDP1

170

MDC

62

LEDP2

171

MDIO

61

LEDP3/EN LEDP3/EN_GRE _GREEN EN 172

MISO

161

LEDP4

174

MOSI

164

LEDP5

175

NC

5

LEDMODE0/ LEDMODE0/GPIO3 GPIO3 12


Page 138


BCM53128 Data Sheet

BCM53128KQLE Pin List by Signal Name

Signal

Ball

Signal

Ball

Signal

Ball

NC

6

TRD[0]+{5}

94

TRD[3]+{4}

82

NC

20

TRD[0]+{6}

101

TRD[3]+{5}

84

NC

28

TRD[0]+{7}

123

TRD[3]+{6}

111

NC

37

TRD[0]-{0}

202

TRD[3]+{7}

113

NC

39

TRD[0]-{1}

222

TRD[3]-{0}

210

NC

41

TRD[0]-{2}

231

TRD[3]-{1}

214

NC

42

TRD[0]-{3}

251

TRD[3]-{2}

239

NC

45

TRD[0]-{4}

73

TRD[3]-{3}

243

NC

46

TRD[0]-{5}

93

TRD[3]-{4}

81

NC

69

TRD[0]-{6}

102

TRD[3]-{5}

85

NC

70

TRD[0]-{7}

122

TRD[3]-{6}

110

NC

99

TRD[1]+{0}

205

TRD[3]-{7}

114

NC

225

TRD[1]+{1}

219

TRST

36

OVDD

125

TRD[1]+{2}

234

XTALI

34

OVDD

129

TRD[1]+{3}

248

XTALO

33

OVDD

133

TRD[1]+{4}

76

XTAL_AVDD

35

OVDD

138

TRD[1]+{5}

90

XTAL_AVSS

32

OVDD

142

TRD[1]+{6}

105

OVDD

145

TRD[1]+{7}

119

OVDD

153

TRD[1]-{0}

204

OVDD2

3

TRD[1]-{1}

220

OVDD2

11

TRD[1]-{2}

233

OVDD2

19

TRD[1]-{3}

249

OVDD2

43

TRD[1]-{4}

75

OVDD2

44

TRD[1]-{5}

91

OVDD2

57

TRD[1]-{6}

104

OVDD2

63

TRD[1]-{7}

120

OVDD2

68

TRD[2]+{0}

207

OVDD2

165

TRD[2]+{1}

217

OVDD2

173

TRD[2]+{2}

236

OVDD2

180

TRD[2]+{3}

246

OVDD2

187

TRD[2]+{4}

78

OVDD2

193

TRD[2]+{5}

88

PLL_AVDD

29

TRD[2]+{6}

107

PLL_AVSS

30

TRD[2]+{7}

117

RESET

17

TRD[2]-{0}

208

SCK

163

TRD[2]-{1}

216

SS

160

TRD[2]-{2}

237

TC K

24

TRD[2]-{3}

245

TDI

23

TRD[2]-{4}

79

TD O

22

TRD[2]-{5}

87

TM S

25

TRD[2]-{6}

108

TRD[0]+{0}

201

TRD[2]-{7}

116

TRD[0]+{1}

223

TRD[3]+{0}

211

TRD[0]+{2}

230

TRD[3]+{1}

213

TRD[0]+{3}

252

TRD[3]+{2}

240

TRD[0]+{4}

72

TRD[3]+{3}

242


Page 139


BCM53128 Data Sheet

BCM53128KQLE Pin List by Ball Number

BCM53128KQLE Pin List by Ball Number Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

1

LEDP29

41

NC

83

AVDDL

127

IMP_TXD6

2


42

NC

84

TRD[3]+{5}

128

IMP_TXD5

43

OVDD2

85

TRD[3]-{5}

129

OVDD

3

OVDD2

44

OVDD2

86

AVDDH

130

IMP_TXD4

4


45

NC

87

TRD[2]-{5}

131

IMP_TXD3

5

NC

46

NC

88

TRD[2]+{5}

132

IMP_GTXCLK

6

NC

47

EN_8051_TxRx

89

AVDDL

133

OVDD

7

IMP_MODE0/GPIO5

48

IMP_VOL_SEL1

90

TRD[1]+{5}

134

IMP_TXD2

8

IMP_MODE1/GPIO6

49

IMP_VOL_SEL0

91

TRD[1]-{5}

135

DVDD

9

HW_FWDG_EN/ GPIO7

50

IMP_SPEED1

92

AVDDH

136

IMP_TXD1

51

IMP_SPEED0

93

TRD[0]-{5}

137

IMP_TXD0

10

GPIO2

52

IMP_DUPLEX

94

TRD[0]+{5}

138

OVDD

11

OVDD2

53

DVDD

95

AVDDL

139

IMP_TXEN

12

LEDMODE0/GPIO3

54

IMP_LINK

96

GPHY2_RDAC

140

IMP_TXER

13

LEDMODE1/GPIO4

55

97

GPHY2_BVDD

141

IMP_TXCLK

14

CLK_FREQ0/GPIO0

IMP_PAUSECAP_R X

98

GPHY2_PLLVDD

142

OVDD

15

CLK_FREQ1/GPIO1

56

IMP_PAUSECAP_T X

99

NC

143

IMP_CRS

16

DVDD

57

OVDD2

100

AVDDL

144

IMP_RXCLK

17

RESET

58

LOOP_DETECTED

101

TRD[0]+{6}

145

OVDD

18

CPU_EEPROM_SEL

59

102

TRD[0]-{6}

146

IMP_VOL_REF

19

OVDD2

ACT_LOOP_DETEC T

103

AVDDH

147

IMP_RXER

20

NC

60

INTR_B

104

TRD[1]-{6}

148

DVDD

21


61

MDIO

105

TRD[1]+{6}

149

IMP_RXDV

62

MDC

106

AVDDL

150

IMP_RXD0

22

TDO

63

OVDD2

107

TRD[2]+{6}

151

IMP_RXD1

23

TDI

64

FSO

108

TRD[2]-{6}

152

IMP_RXD2

24

TCK

65

FCSB

109

AVDDH

153

OVDD

25

T MS

66

FSCLK

110

TRD[3]-{6}

154

IMP_RXD3

26


67

FSI

111

TRD[3]+{6}

155

IMP_RXD4

OVDD2

AVDDL

156

IMP_RXD5

DVDD

68

112

27

NC

TRD[3]+{7}

157

IMP_RXD6

NC

69

113

28

NC

TRD[3]-{7}

158

IMP_RXD7

PLL_AVDD

70

114

29

AVDDL

AVDDH

159

IMP_COL

PLL_AVSS

71

115

30

TRD[0]+{4}

TRD[2]-{7}

160

SS

DVDD

72

116

31

TRD[0]-{4}

TRD[2]+{7}

161

MISO

XTAL_AVSS

73

117

32

AVDDH

AVDDL

162

DVDD

XTALO

74

118

33

TRD[1]-{4}

TRD[1]+{7}

163

SCK

XTALI

75

119

34

TRD[1]+{4}

TRD[1]-{7}

164

MOSI

XTAL_AVDD

76

120

35

AVDDL

AVDDH

165

OVDD2

TRST

77

121

36

TRD[2]+{4}

TRD[0]-{7}

166

LEDDATA

NC

78

122

37

TRD[2]-{4}

TRD[0]+{7}

167

LEDCLK

EN_EEE

79

123

38

AVDDH

AVDDL

168

LEDP0

NC

80

124

39

TRD[3]-{4}

OVDD

169

DVDD

DVDD

81

125

40

82

TRD[3]+{4}

126

IMP_TXD7

170

LEDP1


Page 140


BCM53128 Data Sheet

BCM53128KQLE Pin List by Ball Number

Ball

Signal

Ball

Signal

171

LEDP2

213

TRD[3]+{1}

172 172

LEDP LEDP3/ 3/EN EN_G _GRE REEN EN

214

TRD[3]-{1}

173

OVDD2

215

AVDDH

174

LEDP4

216

TRD[2]-{1}

175

LEDP5

217

TRD[2]+{1}

176

LEDP6

218

AVDDL

177

LEDP7

219

TRD[1]+{1}

178

LEDP8

220

TRD[1]-{1}

179

LEDP9

221

AVDDH

180

OVDD2

222

TRD[0]-{1}

181

LEDP10/ EPROM_TYPE0

223

TRD[0]+{1}

224

AVDDL

182

LEDP11/ EPROM_TYPE1

183

DVDD

184

LEDP12

185

LEDP13

186

LEDP14/ LOOP_DETECT_EN

225

NC

226 226

GPH GPHY1_ Y1_PLLV PLLVD DD

227

GPHY1_BVDD

228

GPHY1_RDAC

229

AVDDL

230

TRD[0]+{2}

187

OVDD2

231

TRD[0]-{2}

188


232

AVDDH

233

TRD[1]-{2}

189

LEDP16

234

TRD[1]+{2}

190

LEDP17

235

AVDDL

191

LEDP18/ BC_SUPP_EN

236

TRD[2]+{2}

192

LEDP19

237

TRD[2]-{2}

193

OVDD2

238

AVDDH

194

LEDP20

239

TRD[3]-{2}

195

LEDP21

240

TRD[3]+{2}

196 196

LEDP LEDP22 22/D /DIS IS_I _IMP MP

241

AVDDL

197

LEDP23/ IMP_DUMB_FWDG_ EN

242

TRD[3]+{3}

243

TRD[3]-{3}

244

AVDDH

198

LEDP24

245

TRD[2]-{3}

199

LEDP25

246

TRD[2]+{3}

200

AVDDL

247

AVDDL

201

T RD RD[0]+{0}

248

TRD[1]+{3}

202

T RD RD[0]-{0}

249

TRD[1]-{3}

203

AVDDH

250

AVDDH

204

T RD RD[1]-{0}

251

TRD[0]-{3}

205

T RD RD[1]+{0}

252

TRD[0]+{3}

206

AVDDL

253

AVDDL

207

T RD RD[2]+{0}

254

208

T RD RD[2]-{0}

LEDP26/ ENFDXFLOW

209

AVDDH

255

210

T RD RD[3]-{0}

LEDP27/ ENHDXFLOW

211

T RD RD[3]+{0}

256

LEDP28

212

AVDDL

H

EXPOSEPAD


Page 141


BCM53128 Data Sheet

Register Definitions

Section 7: Register Definitions Register Definition BCM53128 register sets can be accessed through the programming interfaces described on page on page 95. 95. The register space is organized into pages, each containing a certain set of registers. Table 33 lists 33 lists the pages defined in the BCM53128. To access a page, the page register (0xFF) is written with the page value. The registers contained in the page can then be accessed by their addresses. See “Programming Interfaces” on page 95 for 95 for more information.

Register Notations In the register description tables, the following notation in the R/W column is used to describe the ability to read or to write: •

R/W R/W = Read Read or writ write e

•

RO = Read Read only only

•

LH = Latc Latche hed d high high

•

LL = Latc Latche hed d low low

•

H = Fixe Fixed d high high

•

L = Fixe Fixed d low low

•

SC = Cle Clear ar on read read

Reserved Reserved bits must be written as the default value and ignored ignored when read.

Global Page Register Table 33: Global Global Page Register Register Map Page

Description

00h

“Page 00h: Control Registers” on page 144

01h

“Page 01h: Status Registers” on page 164

02h

“Page 02h: Management/Mirroring Registers” on page 168

03h

“Page 03h: Interrupt Control Register” on page 177

04h

“Page 03h: Interrupt Control Register” on page 177

05h

“Page 05h: ARL/VTBL Access Registers” on page 184

06h, 07h

Reserved

08h

Reserved

09h

Reserved


Page 142


BCM53128 Data Sheet

Global Page Register

Table 33: Global Global Page Register Register Map (Cont.) Page

Description

0Ah

Reserved

0Bh–0Fh

Reserved

10h–17h

“Page 10h–17h: Internal GPHY MII Registers” on page 194

18h–1Fh

Reserved

20h–28h

“Page 20h–28h: Port MIB Registers” on page 230

29h–2Fh

Reserved

30h

“Page 30h: QoS Regis Registers” ters” on page 235

31h

“Page 31h: Port-Based VLAN Registers” on page 245

32h

“Page 32h: Trunking Registers” on page 246

33h

Reserved

34h

“Page 34h: IEEE 802.1Q VLAN Regist Registers” ers” on page 248

35h

Reserved

36h

“Page 36h: DOS Preven Preventt Regis Register” ter” on page 257

37h–3Fh

Reserved

40h

“Page 40h: Jumbo Frame Control Register” on page 260

41h

“Page 41h: Broadcast Storm Suppression Register” on page 262

42h

“Page 42h: EAP Regis Register” ter” on page 268

43h

“Page 43h: MSPT Regis Register” ter” on page 272

44h–6Fh

Reserved

70h

“Page 70h: MIB Snapshot Control Register” on page 275

71h

“Page 71h: Port Snapshot MIB Control Register” on page 275

72h

“Page 72h: Loop Detection Register” on page 276

73h–7Fh

Reserved

80h–83h

Reserved

84h

Reserved

85h

Reserved

86h–87h

Reserved

88h

“Page 88h: IMP Port External PHY MII Registers Page Summary” on page 278

90h

“Page 90h: BroadSync HD Register” on page 279

91h

“Page 91h: Traffic Remarking Register” on page 286

92h

“Page 92h: EEE Cont Control rol Regis Register” ter” on page 288

93h-A0h

Reserved

A1h

Reserved

A2h–EFh

Reserved

Maps to all pages

“Global Registers” on page 295


Page 143


BCM53128 Data Sheet

Page 00h: Control Registers

Page 00h: Control Registers Table 34: Control Control Registers Registers (Page 00h) Address

Bits

Register Name

00h–07h

8/port

“Port Traffic Control Register (Page 00h: Address 00h)” on page 146

08h

8

“IMP Port Control Register (Page 00h: Address 08h)” on page 147

09h–0Ah

8

Reserved

0Bh

8

“Switch Mode Register (Page 00h: Address 0Bh)” on page 148

0Ch–0Dh

16

Reserved

0Eh

8

“IMP Port State Override Register (Page 00h: Address 0Eh)” on page 148

0Fh

8

“LED Refresh Register (Page 00h: Address 0Fh)” on page 149

10h–11h

16

“LED Function 0 Control Register (Page 00h: Address 10h)” on page 150

12h–13h

16

“LED Function 1 Control Register (Page 00h: Address 12h)” on page 151

14h–15h

16

“LED Function Map Register (Page 00h: Address 14h–15h)” on page 151

16h–17h

16

“LED Enable Map Regis Register ter (Page 00h: Addre Address ss 16h–1 16h–17h)” 7h)” on page 152

18h–19h

16

“LED Mode Map 0 Regist Register er (Page 00h: Addres Address s 18h–19 18h–19h)” h)” on page 152

1Ah–1Bh

16

“LED Mode Map 1 Regist Register er (Page 00h: Addres Address s 1Ah–1B 1Ah–1Bh)” h)” on page 152

1Ch

–

“LED Control Register (Page 00h: Address 1Ch)” on page 153

1Dh

8

“PHY LED Control Register (Page 00h: Address 1Dh)” on page 153

1Eh

–

Reserved

1Fh

8

Reserved

20h

–

Reserved

21h

8

“Port Forward Control Register (Page 00h: Address 21h)” on page 154

22h–23h

–

Reserved

24h–25h

16

“Protected Port Selection Register (Page 00h: Address 24h–25h)” on page 155

26h–27h

16

“WAN Port Select Register (Page 00h: Address 26h–27h)” on page 155

28h–2Bh

32

“Pause Capability Register (Page 00h: Address 28h–2Bh)” on page 155

2Ch–2Eh

–

Reserved

2Fh

8

“Reserved Multicast Control Register (Page 00h: Address 2Fh)” on page 156

30h

–

Reserved

31h

8

Reserved

32h–33h

16

“Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h)” on page 157

34h–35h

16

“Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h)” on page 157

36h–37h

16

“MLF IPMC Forward Map Register (Page 00h: Address 36h–37h)” on page 158

38h–39h

16

“Pause Pass Through for RX Register (Page 00h: Address 38h–39h)” on page 158

3Ah–3Bh

16

“Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh)” on page 158

3Ch–3Dh

16

“Disable Learning Register (Page 00h: Address 3Ch–3Dh)” on page 159

3Eh–3Fh

16

“Software Learning Register (Page 00h: Address 3Eh–3Fh)” on page 159

40h–49h

–

Reserved


Page 144


BCM53128 Data Sheet


Table 34: 34: Control Control Registers Registers (Page (Page 00h) 00h) (Cont.) (Cont.) Address

Bits

Register Name

4Ah–4Bh

–

Reserved

4Ch–57h

–

Reserved

58h–5Fh

8/port

“Port State Override Register (Page 00h: Address 58h)” on page 160

60h

8

“IMP RGMII Control Register (Page 00h: Address 60h)” on page 161

61h–74h

–

Reserved

75h

–

Reserved

78h

8

“MDIO “MDI O IMP Port Addres Address s Regist Register er (Page 00h: Addres Address s 78h)” on page 161

79h

8

“Software Reset Control Register (Page 00h: Address 79h)” on page 161

7Ah–7Fh

–

Reserved

80h

8

“Pause Frame Detection Control Register (Page 00h: Address 80h)” on page 162

81h–87h

–

Reserved

88h

8

“Fast-Aging Control Register (Page 00h: Address 88h)” on page 162

89h

8

“Fast-Aging Port Control Register (Page 00h: Address 89h)” on page 162

8Ah–8Bh

16

“Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh)” on page 163

B0h-B7h

64

“CPU Data 0 Share Regis Register ter (Page 00h: Addres Address s B0h-B7 B0h-B7h)” h)” on page 163

B8h-BFh

64

“CPU Data 1 Share Regis Register ter (Page 00h: Addres Address s B8h-BF B8h-BFh) h) ” on page 163

F0h–F7h

8

“SPI Data I/O Register (Global, Address F0h)” on page 295 295,, bytes 0-7

F8h–FDh

–

Reserved

8Ch–EFh

–

Reserved

FEh

8

“SPI Status Register (Global, Address FEh)” on page 295

FFh

8

“Page Register (Global, Address FFh)” on page 296


Page 145


BCM53128 Data Sheet


Port Traffic Control Register (Page 00h: Address 00h) .

Table 35: Port Traffic Control Control Register Address Summary Address

Description

00h

Port 0

01h

Port 1

02h

Port 2

03h

Port 3

04h

Port 4

05h

Port 5

06h

Port 6

07h

Port 7

Table 36: Port Control Control Register Register (Page 00h: Address 00h–07h) 00h–07h) BIt

Name

7:5 7:5

R/W

Description

Default

STP_ STP_ST STATE ATE[2 [2:0 :0]] R/W R/W

CPU CPU writ writes es the the curr curren entt comp comput uted ed stat states es of its its spanning tree algorithm for a given port. 000 = No spanning tree (default for unmanaged mode) 001 = Disabled state (default for managed mode) 010 = Blocking state 011 = Listening Listening state 100 = Learning Learning state 101 = Forwarding state 110–111 = Reserved

~ HW_FWDG_EN

4:2

Reserved

–

–

000

1

TX_DISABLE

R/W

0 = Enable the transmit function of the port at the MAC 0 level. 1 = Disable the transmit function of the port at the MAC level.

0

RX_D RX_DIS ISAB ABLE LE

R/W R/W

0 = Enab Enable le the the rece receiv ive e func functi tion on of the the port port at the the MAC MAC 0 level. 1 = Disa Disabl ble e the the rece receiv ive e func functi tion on of the the port port at the the MAC MAC level.


Page 146


BCM53128 Data Sheet


IMP Port Control Register (Page 00h: Address 08h) Table 37: IMP Port Control Control Register Register (Page 00h: Address Address 08h) Bit

Name

R/W

Description

Default

7:5

Reserved

R/W

–

–

4

RX_UCST_EN

R/W

Receive unicast enable 0 Allow unicast frames to be forwarded to the IMP, when the IMP is configured as the frame management port, and the frame was matching address table entry. When cleared, unicast frames that meet the mirror ingress/egress rules are forwarded to the frame management port. Ignored if the IMP is not selected as the Frame Management Port.

3

RX_MCST_EN

R/W

Receive multicast enable 0 Allow multicast frames to be forwarded to the IMP, when the IMP is configured as the Frame Management Port, and the frame was flooded due to no matching address table entry. When cleared, multicast frames that meet the mirror ingress/egress rules are forwarded to the frame management port.

2

RX_BCST_EN

R/W

Receive broadcast enable 0 Allow broadcast frames to be forwarded to the IMP, when the IMP is configured as the Frame Management Port. When cleared, multicast frames that meet the mirror ingress/egress rules are forwarded to the frame management port.

1:0

Reserved

R/W

–

0


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BCM53128 Data Sheet


Switch Mode Register (Page 00h: Address 0Bh) Table 38: Switch Switch Mode Register Register (Page 00h: Address Address 0Bh) Bit

Name

R/W

Description

Default

7:2

Reserved

RO

–

000001

1

SW_FWDG_EN

R/W

Software forwarding enable HW_FWDG_EN SW_FWDG_EN = 1: Frame forwarding is enabled. SW_FWDG_EN = 0: Frame forwarding is disabled. Managed switch implementations should be configured to disable forwarding on power-on to allow the processor to configure the internal address table and other parameters before frame forwarding is enabled.

0

SW_F SW_FW WDG_M G_MODE R/W

Sof Softwar tware e forw orwardi arding ng mode mode 0 = Unmanaged mode. 1 = Managed mode. The ARL treats reserved multicast addresses differently depending on this selection.

~HW_FWDG_EN

IMP Port State Override Register (Page 00h: Address 0Eh) Table 39: IMP Port State State Override Register Register (Page 00h: Address 0Eh) Bit

Name

R/W

Description

Default

7

MII_SW_OR

R/W

MII software override 0 = Use MII hardware pin status. 1 = Use contents of this register.

0

6

Reserved

R/W

Reserved

0

5

Tx Flow Flow Cont Contro roll Capa Capabi bili lity ty RO

Link Link part partne nerr flow flow cont contro roll capa capabi bili lity ty 0 = Not PAUSE capable 1 = PAUSE capable

0

4

Rx Flow Flow Cont Contro roll Capa Capabi bili lity ty R/W R/W

Link Link part partne nerr flow flow cont contro roll capa capabi bili lity ty 0 = Not PAUSE-capable 1 = PAUSE-capable

0

3:2

S P EE D

R/W

Speed 00 = 10 Mbps 01 = 100 Mbps 10 = 1000 Mbps 11 = 200 Mbps

10

1

FDX

R/W

Full-duplex 0 = Half-duplex Half-duplex 1 = Full-duplex Full-duplex

1


Page 148


BCM53128 Data Sheet


Table 39: IMP Port State Override Override Register (Page 00h: Address 0Eh) (Cont.) Bit

Name

R/W

Description

Default

0

LINK

R/W

Link status 0 = Link fail 1 = Link pass

0

LED Control Register (Page 00h: Address 0Fh–1Bh) Table 40: LED Control Control Register Address Address Summary Summary Address

Description

0Fh

LED refresh control register

10h–11h

LED function 0 control register

12h–13h

LED function 1 control register

14h–15h

LED function map control register

16h–17h

LED enable map register

18h–19h

LED mode map 0 register

1Ah–1Bh

LED mode map 1 register

LED Refresh Register (Page 00h: Address 0Fh) Table 41: LED Refresh Refresh Register Register (Page 00h: Address Address 0Fh) Bit

Name

R/W

Description

Default

7

LED_EN

R/W

Enable LED

1

6

POST_EXEC

R/W

Write 1 to re-start POST.

0

5

POST PO ST_P _PSC SCAN AN_E _EN N

R/W

When When enab enable led, d, swit switch ch scan scans s the the por port dur during ing the 0 POST period.

4

POSt PO St_C _Cab able le_d _dia iag g_en _en

R/W

Enab Enable le cabl cable e diag diagno nost stic ics s disp displa lay y duri during ng PO POST ST 0

3

Norm Normal al_C _Cab able le_d _dia iag_ g_en en

R/W R/W

Enab Enable le cabl cable e diag diagno nost stic ics s disp displa lay y in norm normal al mode

0

2:0 2:0

LED_ LED_Re Refr fres esh_ h_ra rate te

R/W R/W

LED LED refr refres esh h coun countt regi regist ster er (i.e (i.e., ., LED LED blin blinki king ng rate) Refresh time = (N+1) * 10 ms • 000: 000: Rese Reserv rved ed • 001: 001: 20 ms/2 ms/25 5 Hz • 010: 010: 30 ms/1 ms/16 6 Hz • 011: 011: 40 ms/1 ms/12 2 Hz • 100: 100: 50 ms/1 ms/10 0 Hz • 101: 101: 60 ms/8 ms/8 Hz • 110: 110: 70 ms/7 ms/7 Hz • 111: 111: 80 ms/6 ms/6 Hz

3h


Page 149


BCM53128 Data Sheet


LED Function 0 Control Register (Page 00h: Address 10h) Table 42: LED Function Function 0 Control Register Register (Page 00h: Address Address 10h – 11h) 11h) Bit

Name

R/W

Description

Default

15:0 15:0

LED LED_FU _FUNCTIO TION

R/W

The The foll follow owin ing g isthe isthe listof listof funct unctio ionsas nsassi sign gned ed to each bit: 15: Reserved 14: BroadSync HD Link 13: 1G/ACT 12: 10/100M/ACT 11: 100M/ACT 10: 10M/ACT 9: SPD1G 8: SPD100M 7: SPD10M 6: DPX/COL 5: LNK/ACT 4: COL 3: ACT 2: DPX 1: LNK 0: Reserved

LED MODE[1:0] = 00: 16'h0120 LED MODE[1:0] = 01: 16'h0C40 LED MODE[1:0] = 10: 16'h0124 LED MODE[1:0] = 11: 16'h0C04


Page 150


BCM53128 Data Sheet


LED Function 1 Control Register (Page 00h: Address 12h) Table 43: LED Function Function 1 Control Register Register (Page 00h: Address Address 12h – 13h) 13h) Bit

Name

R/W

Description

Default

15:0 15:0

LED_F LED_FUN UNCT CTIO ION N

R/W R/W

The The follo followi wing ng is the the list list of func functi tion ons s assig assigne ned d to each bit: 15: Reserved 14: BroadSync HD Link 13: 1G/ACT 12: 10/100M/ACT 11: 100M/ACT 10: 10M/ACT 9: SPD1G 8: SPD100M 7: SPD10M 6: DPX/COL 5: LNK/ACT 4: COL 3: ACT 2: DPX 1: LNK 0: Reserved

LED MODE[1:0] = 00: 16'h0320 LED MODE[1:0] = 01: 16'h3040 LED MODE[1:0] = 10: 16'h0324 LED MODE[1:0] = 11: 16'h2C04

LED Function Map Register (Page 00h: Address 14h–15h) Table 44: LED Function Function Map Register (Page (Page 00h: Address 14h – 15h) 15h) BIt

Name

R/W

Description

Default

15:9

Reserved

R/W

–

0

8:0 8:0

LED LED_FUN _FUNC C_MAP _MAP

R/W R/W

Per Per por port sele select ct func functtion ion bit. bit. Each Each port port LED LED 1FFh follows the function table specified for each port. 1: Select Function 1. 0: Select Function 0. Bits [7:0] correspond to ports [7:0].


Page 151


BCM53128 Data Sheet


LED Enable Map Register (Page 00h: Address 16h–17h) Table 45: LED Enable Enable Map Register (Page (Page 00h: Address 16h – 17h) 17h) BIt

Name

R/W

Description

Default

15:9

Reserved

R/W

–

0

8:0

LED_EN_MAP

R/W

Per port enable bit 1: Enable 0: Disable Bits [7:0] correspond to ports [7:0].

1FFh

LED Mode Map 0 Register (Page 00h: Address 18h–19h) Table 46: LED Mode Map 0 Register Register (Page (Page 00h: Address Address 18h – 19h) 19h) BIt

Name

R/W

Description

Default

15:9

Reserved

R/W

–

0

8:0

LED_MODE_MAP0

R/W

Combine ine with ith LED_MODE_MAP1 to decide per port LED output mode. Bits [7:0] correspond to ports [7:0].

1FFh

LED Mode Map 1 Register (Page 00h: Address 1Ah–1Bh) Table 47: LED Function Function Map 1 Control Control Register Register (Page 00h: Address Address 1Ah – 1Bh) 1Bh) BIt

Name

R/W

Description

Default

15:9

Reserved

R/W

–

0

8:0

LED_MODE_MAP1

R/W

Per port select function bit LED_FUNC_MAP[1:0] 00: LED off 01: LED on 10: LED blinking 11: LED auto

1FFh

See “LED See “LED Interfaces” on page 119 for 119 for more information.


Page 152


BCM53128 Data Sheet


LED Control Register (Page 00h: Address 1Ch) Table 48: LED Control Control Register Register (Page 00h: Address Address 1Ch) BIt

Name

R/W

7:4 7:4

POST PO ST_L _LED ED_C _CTR TRL L R/W R/W

Pos Post LED LED Contr ontrol ol 0xF The four bits control the LED ON/OFF state during POST to allow dual-color LED to be tested. Bits[7:4] Bits[7:4] control each port four LED pins as below. below. Port 0 LEDP[31:28] Port 1 LEDP[27:24] Port 2 LEDP[23:20] Port 3 LEDP[19:16] Port 4 LEDP[15:12] Port 5 LEDP[11:8] Port 6 LEDP[7:4] Port 7 LEDP[3:0] 1: The LED pin is activated during POST. 0: The LED pin is deactivated during POST.

3

DUAL DUAL_L _LED ED_C _CTR TRL L R/W R/W

Dual Dual-c -col olor or LED LED Test Test Cont Contro roll 0x0 1: One side of the dual-color LED, which corresponding POST_LED_CTRL bit = 1, will be tested during POST firstly, and then test the other side of the dual-color LED, which corresponding POST_LED_CTRL bit = 0. 0: Only one side of the dual-color LED, which corresponding POST_LED_CT POST_LED_CTRL RL bit = 1, will be tested tested during during POST.

2:0

Reserved

Reserved

R/W

Description

Default

0x0

PHY LED Control Register (Page 00h: Address 1Dh) Table 49: PHY LED Control Control Register Register (Page 00h: Address Address 1Dh) BIt

Name

R/W

Description

Default

7:4

PHY_LED_FUNC1

R/W

Bit 7: PHYLED4 of LED Function 1 LED Mode[1:0] = 00: 8'h88 Bit 6: PHYLED3 of LED Function 1 LED Mode[1:0] = 01: 8'h88 Bit 5: PHYLED2 of LED Function 1 Bit 4: PHYLED1 of LED Function 1

3:0

PHY_LED_FUNC0

R/W

Bit 3: PHYLED4 of LED Function 0 LED Mode[1:0] Mode[1:0] = 10: 8''h00 Bit 2: PHYLED3 of LED Function 0 LED Mode[1:0] = 11: 8'h00 Bit 1: PHYLED2 of LED Function 0 Bit 0: PHYLED1 of LED Function 0


Page 153


BCM53128 Data Sheet


Port Forward Control Register (Page 00h: Address 21h) Table 50: Port Forward Forward Control Register Register (Page 00h: Address 21h) BIt

Name

R/W

Description

Default

7

MCST_DLF_FWD_EN

R/ R/W

1 = Forward multicast lookup failed frames according ing 0 to multic multicast ast lookup lookup failed failed forwar forward d map regist register er (Page (Page 00h: Address 34h) 0 = Flood multicast packet if fail ARL table lookup

6

UCST ST_D _DLF LF_F _FW WD_EN D_EN

R/W

1 = For Forwar ward unic unicas astt look lookup up fail failed ed fram rames acco accord rdin ing g 0h to Unicast Lookup failed forward map register (Page 00h: Address 32h) 0 = Flood unicast packet if fail ARL table lookup

5:3

Reserved

R/W

Reserved

2

INR INRANGE ANGE_E _ER RR_DI _DIS

R/W

InIn-Rang Range e Err Error Disca iscard rd.. Whe When bit bit = 1, the ingr ingres ess s 0 port will discard the frames frames with Length field mismatch the frame length. The following is the definition of InRangeErrors. In-Range Errors Frames: The frames received with good CRC and one of the following” • The The valu value e of Leng Length th/T /Typ ype e fiel field d is betw betwee een n 46 and and 1500 1500 incl inclus usiv ive e and and does does not not matc match h the the numb number er of (MAC Client Data + PAD) data octets received. or • The value value of of Length/T Length/Type ype field field is less than than 46, 46, and and the the numb number er of data data octe octets ts rece receive ived d is grea greate ter r than 46 (which does not require padding).

1

OUTR UTRANGE ANGE_E _ER RR-DI -DIS

R/W

Out of Range ange Erro Errorr Disca iscard rd.. When hen bit bit = 1, the the 0 ingress port will discard the frames with length field between between 1500 and 1536 (exclude (exclude 1500 and 1536) and with good CRC. This option only controls the length field checking, but not the frame length checking.

0

Reserved

R/W

Reserved

0

1

See “Egress See “Egress PCP Remarking” Remarking” on page 57 for 57 for more information.


Page 154


BCM53128 Data Sheet


Protected Port Selection Register (Page 00h: Address 24h–25h) Table 51: Protected Port Selection Selection Register (Page (Page 00h: Address 24h – 25h) 25h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

PORT_SELECT

R/W

Protected port selection 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 1 = Port protected. Cannot send/receive to other protected ports. 0 = Port is not protected.

See “Protected See “Protected Ports” on page 47 for 47 for more information.

WAN Port Select Register (Page 00h: Address 26h–27h) Table 52: WAN Port Select Select Register Register (Page 00h: Address Address 26h – 27h) 27h) BIt

Name

R/W

Description

Default

15:10

Reserved

RO

Reserved

0

9

Reserved

R/W

Reserved

0

8

Reserved

R/W

Reserved

0

7:0

WAN_PO POR RT_MAP

R/W

Set assign igned WAN port to 1. Bits [7:0] correspond to ports [7:0], respectively.

0

Pause Capability Register (Page 00h: Address 28h–2Bh) Table 53: Pause Capabilit Capability y Register (Page 00h: Address Address 28h – 2Bh) 2Bh) BIt

Name

R/W

Description

Default

31:24

Reserved

RO

Reserved

0

23

EN_OVERIDE

R/W

Forces the content of this register setting to be used over the auto-negotiation result.

0

22:18

Reserved

R/W

Reserved

0

17:9 17:9

EN_R EN_RX_ X_PA PAUS USE_ E_CA CAP P

R/W R/W

Enab Enabli ling ng the the rece receiv ive e paus pause e capa capabi bili lity ty.. Bit 17: IMP port Bits [16:9] correspond to ports [7:0], respectively.

0h

8:0 8:0

EN_T EN_TX_ X_PA PAUS USE_ E_CA CAP P

R/W R/W

Enab Enable les s the the tran transm smit it paus pause e capa capabi bili lity ty.. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.

0h


Page 155


BCM53128 Data Sheet


Reserved Multicast Control Register (Page 00h: Address 2Fh) Table 54: Reserved Multicast Control Control Register (Page 00h: Address 2Fh) BIt

Name

R/W

Description

Default

7

Multicast Learning

R/W

Multicast learning enable 0 0 = Do not learn unicast source addresses of frames that have a reserved multicast destination address. 1 = Learn unicast source addresses even from frames that have a reserved multicast destination address. See “Address See “Address Management” on page 57 for 57 for more information.

6:5

Reserved

R/W

Reserved

4

En_Mul_4

R/W

Specifies if packets with the destination addresses in 0 the below range are to be forwarded to the appropriate port or dropped when operating in unmanaged mode. 01-80-C2-00-00-20 ~ 01-80-C2-00-00-2F 0 = Forward 1 = Drop

3

En_Mul_3

R/W


2

En_Mul_2

R/W

Specifies if packets with the destination address below 0 are to be forwarded forwarded to the appropriate appropriate port or dropped dropped when operating in unmanaged mode. 01-80-C2-00-00-10 0 = Forward 1 = Drop

1

En_mul_1

R/W


0

En_Mul_0

R/W

Specifies if packets with the destination address below 0 are to be forwarded forwarded to the appropriate appropriate port or dropped dropped when operating in unmanaged mode. 01-80-C2-00-00-00 0 = Forward 1 = Drop

0

See “Multicast See “Multicast Addresses” on page 61 for 61 for more information.


Page 156


BCM53128 Data Sheet


Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h) Table 55: Unicast Unicast Lookup Failed Forward Forward Map Register Register (Page 00h: Address Address 32h – 33h) 33h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0 8:0

UNI_D I_DLF_M LF_MAP AP

R/W

Unica nicast st look lookup up faile ailed d for forward ard map map 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. When the UCST_DLF_FWD_EN bit in “Port in “Port Forward Contro Con troll Reg Regist ister er (Pa (Page ge 00h 00h:: Add Addres ress s 21h 21h)” )” on pag page e 154 154is is enab enable led d and and a unic unicas astt look lookup up failu failure re occu occurs rs,, the the ARL ARL tabl table e forwards the frame according to the contents of this register. If this register remains in default value, the frame is dropped. 0 = Do not forward a unicast lookup failure to this port. 1 = Forward a unicast lookup failure to this port.

See “Unicast See “Unicast Addresses” on page 59 for 59 for more information.

Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h) Table 56: Multicast Multicast Lookup Failed Forward Forward Map Register (Page (Page 00h: Address Address 34h – 35h) 35h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

MCST_DLF_MAP

R/W

Multica icast loo lookup faile iled forward map 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. When the MCST_DLF_FWD_EN bit in port forward contro controll regist register er (Page (Page 00h:Ad 00h:Addre dress ss 21h) 21h) is enable enabled d and a multicast lookup failure occurs, the ARL table forwards the frame according to the contents of this register. If this register remains in default value, the frame is dropped. 0 = Do not forward a multicast lookup failure to this port. 1 = Forward a multicast lookup failure to this port.

See “Multicast See “Multicast Addresses” on page 61 for 61 for more information.


Page 157


BCM53128 Data Sheet


MLF IPMC Forward Map Register (Page 00h: Address 36h–37h) Table 57: MLF IMPC Forward Forward Map Register Register (Page 00h: Address Address 36h – 37h) 37h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

MLF_IPMC_FWD_MAP

R/W

IPMC forward map 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.

Pause Pass Through for RX Register (Page 00h: Address 38h–39h) Table 58: Pause Pass Through Through for RX Register Register (Page 00h: Address Address 38h – 39h) 39h) BIt

Name

R/W

Description

Default

15:8

Reserved

RO

Reserved

0

7:0

IGNORE_PAUSE FRAME _RX

R/W R/W

RX paus pause e pass pass thro throug ugh h map map 1: Ignore IEEE 802.3x 0: Comply with IEEE 802.3x pause frame receiving. Bits [7:0] correspond to ports [7:0], respectively.

0

Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh) Table 59: Pause Pass Through Through for TX Register (Page (Page 00h: Address 3Ah – 3Bh) 3Bh) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

IGNORE_PAUSE FRAME _TX

R/W R/W

TX paus pause e pass pass thro throug ugh h map map 0 1: Ignore IEEE 802.3x. 0: Comply with IEEE 802.3x pause frame receiving Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.


Page 158


BCM53128 Data Sheet


Disable Learning Register (Page 00h: Address 3Ch–3Dh) Table 60: Disable Disable Learning Learning Register (Page 00h: Address Address 3Ch – 3Dh) 3Dh) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

DIS_LEARNING

R/W

1 = Disable learning 0 0 = Enable learning Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.

Software Softw are Learni Learning ng Regist Register er (Page 00h: Addr Address ess 3Eh–3F 3Eh–3Fh) h) Table 61: Software Learning Control Control Register (Page 00h: 00h: Address 3Eh–3Fh) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

–

8:0

SW_LEARN_CNTL

R/W

1: Software learning control enabled. 0 Thebehaviorsareasfollows. • Forwarding Forwarding behavior: behavior: Incoming Incoming packet packet with unknown SA will be copied to CPU port. • Learning Learning behavior: behavior: Allow S/W to decide whether incoming packet learn or not. In S/ W learning mode, the H/W learning mechanism will be disabled automatically. • Refreshed Refreshed behavior: behavior: Allow refreshed refreshed mechanism to operate properly even thro throug ugh h the the H/W H/W lear learni ning ng had had been been disab disable led. d. 0: Software learning control disabled. Forwarding/Learning/Refreshed behavior to keep hardware operation. Bit 8: IMP port Bits [7:0] correspond to ports [7:0]


Page 159


BCM53128 Data Sheet


Port State Override Register (Page 00h: Address 58h) Table 62: Port State Override Override Register Address Summary Address

Description

58h

Port 0

59h

Port 1

5Ah

Port 2

5Bh

Port 3

5Ch

Port 4

5Dh

Port 5

5Eh

Port 6

5Fh

Port 7

Table 63: Port State State Override Register Register (Page 00h: Address 58h–5Fh) 58h–5Fh) BIt

Name

R/W

Description

Default

7

Reserved

R/W

Reserved

–

6

Software Override

R/W

Wr Writing 1 to this bit allows the values of the bits [7:0] 0 to be written to the external PHY. Writing 0 to this bit prevents these values from overriding the present external PHY conditions.

5

TXFlow low Control Enable

R/W

The value lue of this bit override ides the existing ing 0 cond condit itio ions ns of the the exte extern rnal al PHY PHY port port if bit bit 6 is writ writte ten n to 1. 0 = Flow control disabled for transmit traffic. 1 = Flow control enabled for transmit traffic.

4

RX Flow Flow Contr ontrol ol Enab Enable le

R/W

The The valu value e of this his bit bit over overrrides ides the exis existting ing 0 cond condit itio ions ns of the the exte extern rnal al PHY PHY port port if bit bit 6 is writ writte ten n to 1. 0 = Flow control disabled disabled for receive receive traffic. 1 = Flow control enabled for receive traffic. traffic.

3:2

Speed

R/W

The value of this bit overrides the existing 10 cond condit itio ions ns of the the exte extern rnal al PHY PHY port port if bit bit 6 is writ writte ten n to 1. 00 = 10 Mbps 01 = 100 Mbps 10 = 1000 Mbps 11 = Illegal state

1

Duplex Mode

R/W

The value of this bit overrides the existing 1 cond condit itio ions ns of the the exte extern rnal al PHY PHY port port if bit bit 6 is writ writte ten n to 1. 0 = Half-duplex Half-duplex 1 = Full-duplex Full-duplex


Page 160


BCM53128 Data Sheet


Table 63: Port State State Override Override Register Register (Page 00h: Address Address 58h–5Fh) (Cont.) (Cont.) BIt

Name

R/W

Description

Default

0

Link State

R/W

The value of this bit overrides the existing 1 cond condit itio ions ns of the the exte extern rnal al PHY PHY port port if bit bit 6 is writ writte ten n 1. 1 = Link-up 0 = Link-down

IMP RGMII Control Register (Page 00h: Address 60h) Table 64: IMP RGMII RGMII Control Register Register (Page 00h: Address 60h) BIt

Name

R/W

Description

Default

7:2

Re Reserved

R/W

Write as default. Ignore on read.

0

1

RGMI RGMII_ I_DL DLL_ L_RX RXC_ C_EN ENAB ABL L R/W E

1 = RGMII RGMII RXC clock clock delay delay by by DLL DLL is enab enabled led (delay mode) 0 = RGMII RXC clock delay by DLL is disabled (normal mode)

Strap pin IMP_RXC_DELA Y

0

RGMI RGMII_ I_DL DLL_ L_TX TXC_ C_EN ENAB ABL L R/W E

1 = RGMII RGMII TXC clock clock delay delay by DLL is enabled enabled (delay mode) 0 = RGMII TXC clock delay by DLL is disabled (normal mode)

Strap pin IMP_TXC_DELA Y

MDIO IMP Port Address Register (Page 00h: Address 78h) Table 65: MDIO IMP PORT PORT Address Register Register (Page 00h: Address 78h) BIt

Name

R/W

Description

Default

7:5

Reserved

RO

Reserved

0

4:0

IMP_MDIO_ADDRESS

R/W

IMP PORT MDIO address

18h

Software Reset Control Register (Page 00h: Address 79h) Table 66: Software Software Reset Control Control Register Register (Page 00h: Address 79h) BIt

Name

R/W

Description

Default

7

SW_RST

R/W

Software reset (Bit4 “EN_SW_RST” MUST be 0 enabled as well). Software reset, write “1” to activate a RESET, “0” to clear the reset state. 1 = Activate reset. 0 = Clear reset.

6:5

Reserved

R/O

Reserved

0

4

EN_SW_RST

R/W

Enable software reset.

0

3:0

Reserved

R/W

Reserved

0


Page 161


BCM53128 Data Sheet


Pause Frame Detection Control Register (Page 00h: Address 80h) Table 67: Pause Frame Detection Control Control Register (Page (Page 00h: Address 80h) BIt

Name

R/W

Description

Default

7:1

Reserved

RO

Reserved

0

0

PAUSE_IGNORE_D E_DA

R/W

0 = Check DA field on pause frame detection ion. 1 = Ignore DA field on pause frame detection.

0

Fast-Aging Control Register (Page 00h: Address 88h) Table 68: Fast-Aging Fast-Aging Control Control Register Register (Page 00h: Address 88h) BIt

Name

R/W

Description

Default

7

Fast_Age Age_Sta Start/Done

R/W

Set Set bit to 1 trigg iggers the fast aging process. When the fast aging process is done, this bit is cleared to 0.

0

6

Reserved

R/W

Reserved

0

5

EN_AGE_MCAST

R/W

Enable Aging Multicast Entry 0 1: Aging multicast multicast Entries in ARL Table 0: Disable Aging Multicast Entries in ARL Table Note: The EN_AGE EN_AGE_MC _MCAST AST and the EN_AGE EN_AGE_Po _Port rt can not enable (set to 1) at the same time.

4

EN_AGE_SPT

R/W

When set, check spanning tree ID.

0

3

EN_AGE_VLAN

R/W

When set, check VLAN ID.

0

2

EN_AGE_Port

R/W

When set, check port ID.

0

1

EN_AGE_Dynamic

R/W

When set, age out dynamic entry.

1

0

EN_AGE_Static

R/W

Wh W hen set, age out static entry.

0

Fast-Aging Port Control Register (Page 00h: Address 89h) Table 69: Fast-Agin Fast-Aging g Port Control Register Register (Page 00h: Address 89h) Bit

Name

R/W

Description

Default

7:4

Reserved

R/W

Reserved

0

3:0

Fast Age Single Port

R/W

Fast age single port select Writing bits [3:0] selects the port to be fast-aged.

0


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BCM53128 Data Sheet


Fast-Aging Fast-A ging VID Cont Control rol Register (Page 00h: Addre Address ss 8Ah–8Bh 8Ah–8Bh)) Table 70: Fast-Aging VID Control Control Register (Page (Page 00h: Address 8Ah – 8Bh) 8Bh) Bit

Name

R/W

Description

Default

15:12

Reserved

R/W

Reserved

0

11:0

Fast Age Single VID

R/W

Fast age single VID select 0 Writ Writin ing g bits bits [11: [11:0] 0] selec selects ts the the VID VID to be fast fast-a -age ged. d.

CPU Data 0 Share Register (Page 00h: Address B0h-B7h) Table 71: CPU Data 0 Share Register Register (Page 00h: Address Address B0h–B7h) B0h–B7h) Bit

Name

R/W

Description

Default

63:0 63:0

CPU_D PU_DAT ATA_ A_SH SHAR ARE E

R/W

Data ata to be shar shared ed by int interna ernall 8051 8051 and and ext externa ernall 0x0 CPU .

CPU Data 1 Share Register (Page 00h: Address B8h-BFh) Table 72: CPU Data 1 Share Register Register (Page 00h: Address Address B8h– BFh) BFh) Bit

Name

R/W

Description

Default

63:0 63:0

CPU_D PU_DAT ATA_ A_SH SHAR ARE E

R/W

Data ata to be shar shared ed by int interna ernall 8051 8051 and and ext externa ernall 0x0 CPU .


Page 163


BCM53128 Data Sheet

Page 01h: Status Registers

Page 01h: Status Registers Table 73: Status Status Registers Registers (Page 01h) 01h) Address

Bits

Register Name

00h–01h

16

“Link Status Summary (Page 01h: Address 00h)” on page 164

02h–03h

16

“Link Statu Status s Chang Change e (Page 01h: Addres Address s 02h)” on page 165

04h–07h

32

“Port Speed Summary (Page 01h: Address 04h)” on page 165

08h–09h

16

“Duplex Status Summary (Page 01h: Address 08h)” on page 166

0Ah–0Dh

32

“Pause “Paus e Statu Status s Summa Summary ry (Page 01h: Addres Address s 0Ah)” on page 166

0Eh–0Fh

16

“Source Address Change Register (Page 01h: Address 0Eh)” on page 167

10h–45h

48/port

“Last Source Address Register (Page 01h: Address 10h)” on page 167

46h–EFh

–

Reserved

F0h–F7h

8

“SPI Data I/O Register (Global, Address F0h)” on page 295 295,, bytes 0–7

F8h–FDh

–

Reserved

FEh

8


FFh

8


Link Status Summary (Page 01h: Address 00h) Table 74: Link Status Status Summary Register Register (Page 01h: Address 00h–01h) 00h–01h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

LINK_STATUS

RO

Link status Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Link fail 1 = Link pass

0


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BCM53128 Data Sheet


Link Status Change (Page 01h: Address 02h) Table 75: Link Status Status Change Register (Page (Page 01h: Address 02h–03h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0 8:0

LIN LINK_ST K_STAT ATU US_C S_CHAN HANGE

RO

Link Link stat status us chan change ge.. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. Upon change of link status, a bit remains set until cleared cleared by a read operation. operation. 0 = Link status constant. 1 = Link status change.

0x1FF

Port Speed Summary (Page 01h: Address 04h) Table 76: Port Speed Summary Summary Register Register (Page 01h: Address 04h–07h) 04h–07h) BIt

Name

R/W

Description

Default

31:18

Reserved

PO

Reserved

0

17:0

PORT_SPEED

RO

Port speed The speed of each port is reported based on the mapping below: • Bits Bits [17:16 [17:16]] = IMP IMP port port • Bits Bits [15 [15:1 :14] 4] = Por Portt 7 • Bits Bits [13 [13:1 :12] 2] = Por Portt 6 • Bits Bits [11 [11:1 :10] 0] = Por Portt 5 • Bits Bits [9: [9:8] 8] = Por Portt 4 • Bits Bits [7: [7:6] 6] = Por Portt 3 • Bits Bits [5: [5:4] 4] = Por Portt 2 • Bits Bits [3: [3:2] 2] = Por Portt 1 • Bits Bits [1: [1:0] 0] = Por Portt 0 The value of the bits are: • 00 = 10 Mbps Mbps • 01 = 100 100 Mbps Mbps • 10 = 1000 1000 Mbps Mbps • 11 = 200 200 Mbps Mbps (for (for IMP IMP port port only) only)

0x2AAAA


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BCM53128 Data Sheet


Duplex Status Summary (Page 01h: Address 08h) Table 77: Duplex Status Summary Summary Register (Page 01h: Address 08h–09h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

DUPLEX_STATE

RO

Duplex state Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Half-duplex Half-duplex 1 = Full-duplex

0x1FF

Pause Status Summary (Page 01h: Address 0Ah) Table 78: PAUSE Status Status Summary Register Register (Page 01h: Address 0Ah–0Dh) 0Ah–0Dh) BIt

Name

R/W

Description

Default

31:18

Reserved

RO

Reserved

0

17:9 17:9

RECE RECEIV IVE_ E_PA PAUS USE_ E_ST STAT ATE E RO

Paus Pause e stat state. e. Rece Receiv ive e paus pause e capa capabi bili lity ty 0x100 Bit 17: IMP port Bits Bits [16:9] [16:9] corres correspon pond d to ports ports [7:0], [7:0], respec respectiv tively ely.. 0 = Disabled 1 = Enabled

8:0

TRANSMIT_PAUSE_STAT RO E

Tran Transm smit it paus pause e capa capabi bilit lity y 0x100 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Disabled 1 = Enabled


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BCM53128 Data Sheet


Source Address Change Register (Page 01h: Address 0Eh) Table 79: Source Source Address Change Register Register (Page 01h: Address Address 0Eh–0Fh) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

SRC_ADDR_CHANGE

RC

Source address change 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. The value of this bit is 1 if a change in the source address address is detected detected on the given port. The bit remains set until cleared by a read operation. 0 = No change in source address since last read. 1 = Source address has changed since last read.

Last Source Address Register (Page 01h: Address 10h) .

Table 80: Last Source Source Address Register Register Address Summary Summary Address

Description

10h–15h

Port 0

16h–1Bh

Port 1

1Ch–21h

Port 2

22h–27h

Port 3

28h–2Dh

Port 4

2Eh–33h

Port 5

34h–39h

Port 6

3Ah–3Fh

Port 7

40h–45h

IMP port

Table 81: Last Source Source Address (Page (Page 01h: Address 10h–45h) 10h–45h) BIt

Name

R/W

Description

Default

47:0 47:0

LAST LAST_S _SO OURCE_AD E_ADD D

RO

The The 48-b 48-bit it sour source ce addr addres ess s dete detect cted ed on the last last 0 packet ingressed.


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BCM53128 Data Sheet

Page 02h: Management/Mirroring Registers

Page 02h: Management/Mirroring Registers Table 82: Aging/Mirroring Registers (Page 02h) Address

Bits

Register Name

00h

8

“Global Management Configuration Register (Page 02h: Address 00h)” on page 169

01h

8

“IMP Port ID Regis Register ter (Page 02h: Addre Address ss 01h)” on page 169

02h

8

Reserved

03h

8

“IMP Port ID Regis Register ter (Page 02h: Addre Address ss 01h)” on page 169

04h–05h

16

“RMON MIB Steering Register (Page 02h: Address 04h)” on page 170

06h–09h

32

“Aging Time Control Register (Page 02h: Address 06h)” on page 170

0Ah–0Fh

–

Reserved

10h–11h

16

“Mirror Capture Control Register (Page 02h: Address 10h)” on page 171

12h–13h

16

“Ingress Mirror Control Register (Page 02h: Address 12h)” on page 171

14h–15h

16

“Ingress Mirror Divider Register (Page 02h: Address 14h)” on page 172

16h–1Bh

48

“Ingress Mirror MAC Address Register (Page 02h: Address 16h)” on page 172

1Ch–1Dh

16

“Egress Mirror Control Register (Page 02h: Address 1Ch)” on page 173

1Eh–1Fh

16

“Egress Mirror Divider Register (Page 02h: Address 1Eh)” on page 174

20h–25h

48

“Egress Mirror MAC Address Register (Page 02h: Address 20h)” on page 174

26h–EFh

–

Reserved

30h–33h

8

Device ID number

34h–3Fh

–

Reserved

40h

8

Revision ID number

41h–4Fh

–

Reserved

50h–53h

32

“High-Level Protocol Control Register (Page 02h: Address 50h–53h)” on page 175

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8



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BCM53128 Data Sheet


Global Management Configuration Register (Page 02h: Address 00h) Table 83: Global Management Configuration Configuration Register (Page (Page 02h: Address 00h) Bit

Name

R/W

Description

Default

7:6

En_IMP_Port

R/W

IMP port enable 00 00 = No frame management port. 01 = Reserved 10 = Enable IMP port only. All traffic to CPU from LAN and WAN ports will be forwarded to IMP port. 11 = Reserved These bits are ignored when SW_FWD_MODE = Unmanaged in the “Switch the “Switch Mode Register (Page 00h: Address 0Bh)” 0B h)” on page 148 148..

5

Re Reserved

R/W

Reserved

0

4

Re Reserved

R/W

Reserved

0

3:2

Reserved

R/W

Reserved

0

1

En_Rx_BPDU

R/W

Receive BPDU enable 0 Enables all ports to receive BPDUs and forwards to the IMP port. This bit must be set to globally allow BPDUs to be received.

0

Reset MIB

R/W

Reset MIB counters 0 Resets all MIB counters for all ports to 0 (pages 20h– 28h). This bit must be set and then cleared in successive write cycles to activate the reset operation.

IMP Port ID Register (Page 02h: Address 01h) Table 84: IMP Port ID Register Register (Page 02h: Address Address 01h) Bit

Name

R/W

Description

Default

7:4

Reserved

RO RO

Reserved

0x0

3:0

IMP_PRT_ID

RO

IMP Port ID The field specifies the port ID of the IMP port. The BCM53128 IMP is fixed at Port 8.

0x8


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BCM53128 Data Sheet


Broadcom Header Control Register (Page 02h: Address 03h) Table 85: Broadcom Broadcom Tag Control Register Register (Page 02h: Address 03h) Bit

Name

R/W

Description

Default

7:1

Reserved

RO

Reserved

0

0

BRCM BRCM_H _HD DR_EN R_EN

R/W

Broa Broadc dcomTa omTag g enab enablefo leforr IMP.Enab P.EnableBr leBroa oadc dcomhe omhead aderfo erfor r 1 IMP port. 1 = Additio Additional nal header header inform informati ation on is insert inserted ed into into the origin original al frame, between original SA field and Type/Length fields. The tag includes includes the Broadcom Broadcom Tag field. 0 = Without additional header information.

RMON MIB Steering Register (Page 02h: Address 04h) Table 86: RMON MIB Steering Steering Register Register (Page 02h: Address 04h–05h) 04h–05h) Bit

Name

R/W

Description

Default

15:9

Reserved

R/ R /W

Reserved

0

8:0

Override RMON Receive

R/W R/W

Over Overri ride de RMON RMON rece receiv ive e 0 Forces the RMON packet size bucket counters from the normal default of snooping on the receive side of the MAC to the the tran transm smit it side side.. This This allow allows s the the RMON RMON buck bucket et coun counte ters rs to snoop either transmit or receive, allowing full-duplex MAC support. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.

Aging Time Control Register (Page 02h: Address 06h) Table 87: Aging Time Control Control Register Register (Page 02h: Address 06h–09h) 06h–09h) BIt

Name

R/W

Description

Default

31:21

Reserved

RO

Reserved

0

20

Age Change

R/W

Age change enable 0 1 = Set age time via bits [19:0] immediately. 0 = Age time will be changed by the new value specified in bit[19:0], after the original age time value in bit[19:0] times up.

19:0

AGE AG E_TIME

R/W

Specifies ies the aging time ime in seconds for dynamically 300d learned addresses. Maximum age time is 1,048,575s. Setting the AGE_TIME to 0 disables the aging process. For more information information on ARL table aging, see “Address see “Address Aging” on page 64 64..


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BCM53128 Data Sheet


Mirror Capture Control Register (Page 02h: Address 10h) Table 88: Mirror Capture Control Control Register (Page 02h: Address 10h–11h) BIt

Name

R/W

Description

Default

15

Mirror Enable

R/W

Global mirror enable 0 = Disable mirror capture feature 1 = Enable mirror capture feature

0

14

BLK_ BLK_N NOT_MI T_MIR R

R/W R/W

When hen ena enabled bled,, all all traf raffic fic to MIRRO RROR_CAP _CAPTU TUR RE_PO E_POR RT 0 is blocked, except for mirror traffic. Nonmirror traffic is disabled. 0 = No traffic blocking on mirror capture port 1 = Traffic to mirror capture port blocked unless mirror traffic

13:6

Reserved

R/W

Reserved

0

5:4

Reserved

R/W

Reserved

0

3:0

Capture Port

R/W

Mirror capture port ID Binary value identifies identifies the single unique port that is designated as the port where all ingress and/or egress traffic is mirrored.

0

For additional information about port mirroring, see “Port see “Port Mirroring” on page 48. 48.

Ingress Mirror Control Register (Page 02h: Address 12h) Table 89: Ingress Ingress Mirror Control Control Register Register (Page 02h: Address 12h–13h) BIt

Name

R/W

15:1 15:14 4

IN_M IN_MIR IRRO ROR_ R_FI FILT LTER ER R/W R/W

Ingr Ingres ess s mirr mirror or filt filter er 0 Filters frames to be forwarded to the mirror capture port, specified in “Mirror in “Mirror Capture Control Register (Page 02h: Address 10h)” on page 171 171.. 00 = Mirror all ingress frames. 01 = Mirror all ingress frames with DA = IN_MIRROR_MAC. 10 = Mirror all ingress frames with SA = IN_MIRROR_MAC. 11 = Reserved IN_MIRROR_MAC is specified in “Ingress in “Ingress Mirror MAC Address Register (Page 02h: Address 16h)” on page 172 172..

13

IN_DIV_EN

Ingress divider enable

R/W

Description

Default

0

The ingress divider mirrors every nth ingress frame that has passed through the IN_MIRROR_FILTER (n represents represents the IN_MIRRO IN_MIRROR_DI R_DIV V defined defined in “Ingr “Ingress ess Mirro Mirror r Dividerr Register (Page 02h: Address 14h)” on page 172). Divide 172). 0 = Disable ingress divider feature. 1 = Enable ingress ingress divider feature.


Page 171


BCM53128 Data Sheet


Table 89: Ingress Mirror Control Control Register (Page 02h: Address 12h–13h) (Cont.) BIt

Name

R/W

Description

Default

12:9

Reserved

R/W

Reserved

0

8:0

IN_MIRROR_MASK

R/W

Ingress mirror port mask 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. Ports with the corresponding bit set to 1 have ingress frames frames mirrored mirrored to the MIRROR_C MIRROR_CAPTUR APTURE_POR E_PORT. T. While multiple ports can be set as an Ingress Mirror port, severe congestion and/or frame loss may occur if excessive bandwidth from the ingress mirrored port (s) is directed to the MIRROR_CAPTURE_PORT. Setting a mirror filter via bits [15:14] or divider via bit 13 may be helpful.


Ingress Mirror Divider Register (Page 02h: Address 14h) Table 90: Ingress Mirror Divider Divider Register (Page 02h: Address 14h–15h) BIt

Name

R/W

Description

Default

15:10

Reserved

R/W

Reserved

0

9:0

IN_MIRROR_DIV

R/W

Ingress mirror divider 0 Receive frames that have passed the IN_MIRROR_FILTER rule can further be pruned to reduce the overall number of frames returned to the MIRROR_CAPTURE_PORT. When the IN_DIV_EN bit in the “Ingress the “Ingress Mirror Control Register (Page 02h: Address 12h)” on page 171 171 is is set, frames frames that pass the IN_MIRROR_FILTER rule are further divided by n, where n = IN_MIRROR_DIV + 1.


Ingress Mirror MAC Address Register (Page 02h: Address 16h) Table 91: Ingress Mirror MAC Address Register (Page 02h: Address 16h–1Bh) BIt

Name

R/W

Description

Default

47:0

IN_MIRROR_MAC

R/W

Ingress mirror MAC address MAC address that is compared against ingress frames in accordance with the IN_MIRROR_FILTER rules in “Ingress in “Ingress Mirror Control Register (Page 02h: Address 12h)” on page 171. 171.

0



Page 172


BCM53128 Data Sheet


Egress Mirror Control Register (Page 02h: Address 1Ch) Table 92: Egress Mirror Control Control Register (Page 02h: Address 1Ch–1Dh) BIt

Name

R/W

15:1 15:14 4

OUT_ OUT_MI MIRR RROR OR_F _FIL ILTE TE R/W R/W R

Egre Egress ss mirr mirror or filt filter er 0 Filters egress frames that are forwarded to the mirror capture port, specified in “Mirror in “Mirror Capture Control Register Regis ter (Page 02h: Addre Address ss 10h)” on page 171. 171. 00 = Mirror all egress frames. 01 = Mirror all egress frames with DA = OUT_MIRROR_MAC. 10 = Mirror all egress frames with SA = OUT_MIRROR_MAC. 11 = Reserved. OUT_MIRROR_MAC is specified in “Egress in “Egress Mirror MAC Address Register (Page 02h: Address 20h)” on page 174. 174.

13

OUT_DIV_EN

Egress divider enable

R/W

Description

Default

0

The egress divider mirrors every nth egress frame that has passed through the OUT_MIRROR_FILTER (n represents the OUT_MIRROR_DIV defined in “Egress in “Egress Mirror Divider Register (Page 02h: Address 1Eh)” on page 174). 174). 0 = Disable Disable egress divider feature. 1 = Enable egress divider feature. feature. 12:9

Reserved

R/W

8:0 8:0

OUT_ OUT_MI MIRR RROR OR_M _MAS ASK K R/W R/W

Reserved

0

Egre Egress ss mirr mirror or port port mask mask 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. Ports with the corresponding bit set to 1 have egress frames mirrored to the MIRROR_CAPTURE_PORT. While multiple ports can be set as an egress mirror port, severe congestion and/or frame loss may occur if excessive bandwidth from the egress mirrored port (s) is directed to the MIRROR_CAPTURE_PORT. Setting a mirror filter via bits [15:14] or a divider via bit 13 may be helpful.



Page 173


BCM53128 Data Sheet


Egress Mirror Divider Register (Page 02h: Address 1Eh) Table 93: Egress Mirror Divider Divider Register (Page 02h: Address 1Eh–1Fh) BIt

Name

R/W

Description

Default

15:10

Reserved

R/W

Reserved

0

9:0

OUT_MIRROR_DIV

R/W

Egress mirror divider 0 Egressed frames that have passed the OUT_M OUT_MIR IRROR ROR_FI _FILTE LTER R rule rule can furthe furtherr be pruned pruned to reduce the overall number of frames returned to the MIRROR_CAPTURE_PORT. When the OUT_DIV_EN bit in the “Egress the “Egress Mirror Control Register (Page 02h: Address 1Ch)” on page 173 is 173 is set, frames that pass the OUT_MIRROR_FILTER rule are further divided by n, where n = OUT_MIRROR_DIV + 1.


Egress Mirror MAC Address Register (Page 02h: Address 20h) Table 94: Egress Mirror MAC Address Register (Page 02h: Address 20h–25h) BIt

Name

R/W

Description

Default

47:0

OUT_MIRROR_MAC

R/W

Egress mirror MAC address 0 MAC address that is compared against egress frames in accordance with the OUT_MIRR OUT_MIRROR_F OR_FILTER ILTER rules defined defined in “Egress Mirror Control Register (Page 02h: Address 1Ch)” on page 173. 173.


Device ID Register (Page 02h: Address 30h–33h) Table 95: Device Device ID Register (Page (Page 02h: Address 30h–33h) 30h–33h) BIt

Name

R/W

Description

Default

31:0

Device_ID

RO

Device ID

32'0005_3128

Revision Number Register (Page 02h: Address 40h) Table 96: Egress Egress Mirror MAC Address Register Register (Page 02h: Address Address 40h) BIt

Name

R/W

Description

Default

7:0

Revision_ID

RO

Revision number

0


Page 174


BCM53128 Data Sheet


High-Level High -Level Protocol Control Register (Page 02h: Address 50h–53h 50h–53h)) Table 97: High-Level Protocol Control Control Register (Page (Page 02h: Address 50h–53h) BIt

Name

R/W

Description

Default

31:19

Reserved

R/W

Reserved

–

18

MLD_QRY_FWD_MODE

R/W

MLD Query Message Forwarding Mode 0 1: MLD MLD Quer Query y mess messag age e fram frames es will will be trap trappe ped d to CPU port only. 0: MLD MLD Quer Query y mess messag age e fram frames es will will be forw forwar arde ded d by L2 result and also copied to CPU.

17

MLD_QRY_EN

R/W

MLD Query Message Snooping/Redirect Enable 0 1: Enable MLD query message snooping/ redirect 0: Disable

16

MLD_RPTDONE_FWD_MO R/W DE

MLDRepo MLDReport/ rt/Don DoneMess eMessageFo ageForwa rwardi rdingMod ngMode e 0 1: MLD report/done message frames will be trapped to CPU port only 0: MLD report/done message frames will be forwarded by L2 result and also copied to CPU

15

MLD_RPTDONE_EN

R/W

MLD Report/Done Message Snooping/Redirect 0 Enable 1: Enable MLD report/done message snooping/ redirect 0: Disable

14

IGM IGMP_UK P_UKN N_FWD _FWD_M _MO ODE

R/W

IGM IGMP Unkno nknow wn Messa essage ge Forw Forwar ardi ding ng Mode Mode 0 1: IGMP unknown message frames will be trapped to CPU port only 0: IGMP unknown message frames will be forwarded by L2 result and also copied to CPU

13

IGMP_UKN_EN

R/W

IGMP Unknown Message Snooping/Redirect Enable 1: Enable IGMP unknown message snooping/ redirect 0: Disable

12

IGM IGMP_QR P_QRY_ Y_FW FWD D_MOD _MODE E

R/W

IGM IGMP Query uery Mes Message sage For Forwardi arding ng Mode ode 0 1: IGMP query message frames will be trapped to CPU port only 0: IGMP query message message frames will be forwarded by L2 result and also copied to CPU

11

IGMP_QRY_EN

R/W

IGMP Query Message Snooping/Redirect Enable 1: Enable IGMP query message Snooping/ Redirect 0: Disable

0

0


Page 175


BCM53128 Data Sheet


Table 97: High-Level High-Level Protocol Protocol Control Control Register Register (Page 02h: Address Address 50h–53h) 50h–53h) (Cont.) (Cont.) BIt

Name

R/W

Description

Default

10

IGMP_RPTLVE_FWD_MOD R/W E

IGMP Report/Lea Report/Leave ve Message Message Forwarding Forwarding Mode 0 1: IGMP report/leave message frames will be trapped to CPU port only 0: IGMP report/leave message frames will be forwarded by L2 result and also copied to CPU

9

IGMP_RPTLVE_EN

R/W

IGMP Report/Leave Message Snooping/ Redirect Enable 1: Enable IGMP report/leave message Snooping/Redirect 0: Disable

8

IGMP_DIP_EN

R/W

IGMP L3 DIP checking Enable 0 In addition to the IP datagram with a protocol valu value e of 2, IGMP IGMP will will be clas classi sifi fied ed by matc matchi hing ng its its DIP with the Class D IP address(224.0.0.0~239.255.255.255).

7:6

Reserved

R/W

Reserved

5

ICMPv6_FWD_MODE

R/W

ICMPv6 (exclude MLD) Forwarding Mode 0 1: ICMPv6 frames will be trapped to CPU port only. 0: ICMPv6 frames will be forwarded by L2 result and also copied to CPU.

4

ICMPv6_EN

R/W

ICMPv6 (exclude MLD) Snooping/Redirect 0 Enable ICMPv6, with a next header value of 58, will be classified by IPv6 datagram.

3

ICMPv4_EN

R/W

ICMPv4 Snooping Enable 0 ICMPv6, with a next header value of 0 and exte extens nsion ion head header er next next head header er valu value e of 58, 58, will will be classified by IPv6 datagram. 1: ICMPv4 frames will be forwarded by L2 result and also copied to CPU. 0: ICMPv4 frames will be forwarded by L2 result.

2

DHCP_EN

R/W

DHCP Snooping Enable 0 1: DHCP frames will be forwarded by L2 result and also copied to CPU. 0: DHCP frames will be forwarded forwarded by L2 result.

1

RARP_EN

R/W

RARP Snooping Enable 0 1: RARP frames will be forwarded by L2 result and also copied to CPU. 0: RAPR frames will be forwarded by L2 result.

0

ARP_EN

R/W

ARP Snooping Enable 0 1: ARP ARP fram frames es will will be forw forwar arde ded d by L2 resu result lt and and also copied to CPU. 0: ARP frames will be forwarded by L2 result.

0

0


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BCM53128 Data Sheet

Page 03h: Interrupt Control Register

Page 03h: Interrupt Control Register Table 98: Page 03h: Interrupt Interrupt Control Register Register Address

Bits

Register Name

00h-03h

32

“Interrupt Status Register (Page 03h: Address 00h)”

08h-0Bh

32

“Interrupt Enable Register (Page 03h: Address 08h)”

10h-11h

16

“IMP Sleep Timer Register (Page 03h: Address 10h)” on page 178

18h

8

“Sleep Status Register (Page 03h: Address 18h)” on page 178

20h

8

“External CPU Interrupt Trigger Register (Page 03h: Address 20h)” on page 178

Interrupt Status Register (Page 03h: Address 00h) Table 99: Interrupt Interrupt Status Status Register (Page 03h: Address Address 00h) BIt

Name

R/W

Description

Default

31:25

Reserved

R/W

Reserved

–

24:1 24:16 6

Link Link Stat Status us Chang hange e Interrupt

R/W

Each Each bit bit is set when when the the corre correspo spondin nding g port port stat status us is is – changed. 0 = No link status change 1 = Link status change Bit [24]: IMP port Bits [23:16]: Port[7:0]

15:1

Reserved

R/W

Reserved

–

0

IMP_ IMP_Sl Slee eep_ p_Ti Tim mer_R er_Run un R/W R/W

Indic ndicat ates es the the IMP IMP por port tim timer has has been been trigg rigger ered ed..

–

Interrupt Enable Register (Page 03h: Address 08h) Table 100: Interrupt Interrupt Enable Register Register (Page 03h: Address Address 08h) BIt

Name

R/W

Description

Default

31:25

Reserved

R/W

Reserved

–

24:1 24:16 6

Link Link Stat Status us Chang hange e Interrupt Enable

R/W

Each Each bit bit is set when when the the corre correspo spondin nding g port port stat status us is is – changed. 0 = Disable Disable interrupt 1 = Enable interrupt interrupt Bit [24]: IMP port Bits [23:16]: Port[7:0]

15:1

Reserved

R/W

Reserved

–

0

IMP_Sleep_Timer_Run R/W R/W _Enable

Indic Indicat ates es the the IMP IMP port port time timerr has has been been trig trigge gere red. d.

–


Page 177


BCM53128 Data Sheet

Page 03h: Interrupt Control Register

IMP Sleep Timer Register (Page 03h: Address 10h) Table 101: IMP Sleep Sleep Timer Register Register (Page 03h: Address Address 10h) BIt

Name

R/W

Description

Default

15:13

Reserved

R/W

Reserved

0x0

12:0 12:0

IMP IMP Sleep Sleep Time Timerr

R/W R/W

The The conf config igur urat ation ion value value of IMP IMP port port slee sleep p time timerr to indi indica cate te 0x0 the desired sleep recovery time (i.e., wake-up time). When the timer is set by the CPU to a non-zero non-zero value, it puts the IMP port to sleep. The wake-up time is the set value decrease 1. The unit is in 1  sec.

Sleep Status Register (Page 03h: Address 18h) Table 102: Sleep Sleep Status Register Register (Page 03h: Address Address 18h) BIt

Name

R/W

Description

Default

7:1

Reserved

RO

Reserved

0x0

0

IMP_Port_Sleep_ST RO S

IMP IMP Port Port Slee Sleep p Stat Status us.. 0x0 0 = IMP port is not in IMP_Sleep mode, whenever either the reset or the counter of IMP Sleep Timer is equal to zero. Note: The Note: The port is in IMP_SLEEP INIT state. 1 = IMP port is in IMP_Sleep mode, when the counter of IMP Sleep Timer is not equal zero. Note: The Note: The port is not in IMP_SLEEP INIT state.

External CPU Interrupt Trigger Register (Page 03h: Address 20h) Table 103: External CPU Interrupt Trigger Register Register (Page 03h: Address 20h) BIt

Name

R/W

Description

Default

7:1

Reserved

RO

Reserved

0x0

0

EXT_ EX T_C CPU_I PU_IN NT

R/W

Ext Externa ernall CPU to inte interrnal nal 8051 8051 Int Interr errupt upt Trig Trigge ger. r. The External CPU trigger is an interrupt to the internal internal 8051 by setting the bit to 1.

0x0


Page 178


BCM53128 Data Sheet

Page 04h: ARL Control Register

Page 04h: ARL Control Register Table 104: ARL Control Control Registers Registers (Page 04h) Address

Bits

Register Name

00h

8

“Global ARL Configuration Register (Page 04h: Address 00h)” on page 180

01h–03h

–

Reserved

04h–09h

48

“BPDU Multicast Address Register (Page 04h: Address 04h)” on page 180

0Ah–0Dh

–

Reserved

0Eh–0Fh

16

“Multiport Control Register (Page 04h: Address 0Eh–0Fh)” on page 181

10h–17h

64

“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on page 182

18h–1Bh

32

“Multiport Vector N (N = 0–5) Register (Page 04h: Address 18h)” on page 183

1Ch–1Fh

–

Reserved

20h–27h

64


28h–2Bh

32


2Ch–2Fh

–

Reserved

30h–37h

64


38h–3Bh

32


3Ch–3Fh

–

40h–47h

64


48h–4Bh

32


4Ch–4Fh

–

Reserved

50h–57h

64


58h–5Bh

32


5Ch–5Fh

–

Reserved

60h–67h

64


68h–6Bh

32


6Ch–FEh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


Reserved


Page 179


BCM53128 Data Sheet


Table 104: 104: ARL Control Control Registers Registers (Page (Page 04h) (Cont.) (Cont.) Address

Bits

Register Name

FFh

8


Global ARL Configuration Register (Page 04h: Address 00h) Table 105: Global ARL Configuration Configuration Register (Page (Page 04h: Address 00h) BIt

Name

R/W

Description

Default

7:5

Reserved

RO

Reserved

0

4

Reserved

–

Reserved

0

3

Reserved

RO

Reserved

0

2

AGE_Accelerate

R/W

When enabled, the aging time is reduced by 1/128. 0 1 = Accelerate the aging 128 times 0 = Keep the original age process

1

Reserved

RO

–

0

Hash Disable

R/W

Hash function disable 0 Disables the hash function of the ARL table so that entries entries are directly directly mapped to the table instead of being hashed to an index. 1 = Disable hash function 0 = Enable hash function For more information see “Address see “Address Table Organization” on page 58. 58.

1

BPDU Multicast Address Register (Page 04h: Address 04h) Table 106: BPDU Multicast Multicast Address Register (Page (Page 04h: Address 04h – 09h) 09h) Bit

Name

R/W

Description

Default

47:0

BPDU_MC_ADDR

R/W

BPDU multicast address 1 01-80-c200-00-00 Defaults to the IEEE 802.1 defined reserved multicast address for the bridge group address. Programming to an alternate value allows support of proprietary protocols in place of the normal span spanni ning ng tree tree prot protoc ocol ol.. Fram Frames es with with a matc matchin hing g DA to this address are forwarded to the designated management port.


Page 180


BCM53128 Data Sheet


Multiport Multi port Control Register (Page 04h: Address 0Eh–0F 0Eh–0Fh) h) Table 107: Multiport Control Register (Page 04h: Address 0Eh–0Fh) Bit

Name

R/W

Description

Default

15

MPORT0_TS-EN

R/W

Mport 0 Time Sync Enable 0 1: Packet will be time-stamped if forwarded to CPU. MPORT_ MPORT_VEC VECTOR TOR0 0 should should be progra programme mmed d to CPU only if this bit is set. 0: Packet will not be time-stamped

14:12

Reserved

RO

Reserved

11:10

MPORT_CTRL5

R/W

Multiport 5 Control 00 00: Disable Multiport 5 Forward. 10: Compare MPORT_ADD5 only; Forward based on MPORT_Vector 5 if matched. 01: Compare MPORT_ETYPE5 only; Forward based on MPORT_Vector 5 if matched. 11: Compare MPORT_ETYPE5 and MPORT_ADD MPORT_ADD5; 5; Forward Forward based on MPORT_Vect MPORT_Vector or 5 if matched.

9:8

MPORT_CTRL4

R/W


7:6

MPORT_CTRL3

R/W


5:4

MPORT_CTRL2

R/W


0


Page 181


BCM53128 Data Sheet


Table 107: Multiport Control Register (Page 04h: Address Address 0Eh–0Fh) (Cont.) Bit

Name

R/W

Description

Default

3:2

MPORT_CTRL1

R/W


1:0

MPORT_CTRL0

R/W


Multiport Address N (N=0–5) Register (Page 04h: Address 10h) .

Table 108: Multiport Address Address Register Address Address Summary Address

Description

10h–17h

Multiport ETYPE Address 0

20h–27h


30h–37h


40h–47h


50h–57h


60h–67h


Table 109: Multiport Address Register Register (Page 04h: Address Address 10h–17h, 20h–27h, 30h–37h, 40h–47h, 50h– 57h, 60h–67h) BIt

Name

R/W

Description

Default

64:4 64:48 8

MPO POR RT_ET T_ETYP YPE E

R/W R/W

Multi ultipo port rt Ethe Ethern rnet et Type Type 0000 Allows a frames with a matching MPORT_ETYPE to this Length Type field to be forwarded to any programmable group of ports on the chip, as defined in the bit map in the Multiport Vector Register. Must be enabled using the MPORT_CTRL bit in the Multiport Control Register.


Page 182


BCM53128 Data Sheet


Table 109: Multiport Address Register Register (Page 04h: Address Address 10h–17h, 20h–27h, 30h–37h, 40h–47h, 50h– 57h, 60h–67h) 60h–67h) (Cont.) (Cont.) BIt

Name

R/W

Description

Default

47:0

MPORT_ADDR

R/W

Multiport Address 0000000 Allows a frames with a matching DA to this address to be 00000 forw forwar arde ded d to any any prog progra ramm mmab able le grou group p of port ports s on the the chip chip,, as defined in the bit map in the Multiport Vector Register. Must be enabled using the MPORT_CTRL bit in the Multiport Control Register.

Multiport Vector N (N = 0–5) Register (Page 04h: Address 18h) .

Table 110: Multiport Vector Register Address Summary Address

Description

18h–1Bh

Multiport Vector 0

28h–2Bh

Multiport Vector 1

38h–3Bh

Multiport Vector 2

48h–4Bh

Multiport Vector 3

58h–5Bh

Multiport Vector 4

68h–6Bh

Multiport Vector 5

Table 111: Multiport Vector Register (Page (Page 04h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h–4Bh, 58h– 5Bh, 68h–6Bh) BIt

Name

R/W

Description

Default

31:9

Reserved

R/O

Reserved

0

8:0

MPORT_VCTR_N

R/W

Mu Multiport Vector 0 A bit mask corresponding to the physical ports on the chip. A frame with a DA matching the content of the Multiport Address Register will be forwarded to each port with a bit set in the Multiport Vector bit map. Bits[7:0] correspond to ports[7:0] Bit 8: Management Port (MII Management)


Page 183


BCM53128 Data Sheet

Page 05h: ARL/VTBL Access Registers

Page 05h: ARL/VTBL Access Registers Table 112: ARL/VTBL ARL/VTBL Access Access Registers (Page (Page 05h) Address

Bits

Register Name

00h

8

“ARL Table Read/Write Control Register (Page 05h: Address 00h)” on page 185

01h–0Fh

–

Reserved

02h–07h

48

“MAC Address Index Register (Page 05h: Address 02h)” on page 185

08h–09h

16

“VLAN ID Index Regist Register er (Page 05h: Addres Address s 08h)” on page 186

0Ah–0Fh

–

Reserved

10h–17h

64

“ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on page 186

18h–1Bh

16

“ARL Table Data Entry N (N = 0–3) Regis Register ter (Page 05h: Addre Address ss 18h)” on page 187

1Ch–1Fh

–

Reserved

20h-27h

64


28h-2Bh

32


2Ch-2Fh

–

Reserved

30h-37h

64


38h-3Bh

32


3Ch-3Fh

–

Reserved

40h-47h

64


48h-4Bh

32


4Ch-4Fh

–

Reserved

50h

8

“ARL Table Searc Search h Contr Control ol Regis Register ter (Page 05h: Addre Address ss 50h)” on page 188

51h–52h

16

ARL Search Address

60h–77h

64

“ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address 60h)” on page 189

68h–7Bh

32

7Ch–7Fh

–

Reserved

80h

8

“VLAN Table Read/Write/Clear Control Register (Page 05h: Address 80h)” on page 191

81h–82h

16

“VLAN Table Address Index Register (Page 05h: Address 81h)” on page 192

83h–86h

32

“VLAN Table Entry Register (Page 05h: Address 83h–86h)” on page 192

67h–EFh

–

Reserved

F0h–F7h

8


“ARL “AR L Ta Tabl ble e Sea Searc rch h Da Data ta Re Resu sult lt N (N = 00-1) 1) Re Regi gist ster er (P (Pag age e 05 05h: h: Ad Addr dres ess s 68 68h) h)”” on page 190


Page 184


BCM53128 Data Sheet


Table 112: 112: ARL/VTBL ARL/VTBL Access Access Register Registers s (Page 05h) (Cont.) (Cont.) Address

Bits

Register Name

F8h–FDh

–

Reserved

FEh

8


FFh

8


ARL Table Read/Write Control Register (Page 05h: Address 00h) Table 113: ARL Table Read/Write Read/Write Control Control Register Register (Page 05h: Address 00h) BIt

Name

R/W

Description

Default

7

START/DONE

R/W (SC)

Start/done command 0 Write as 1 to initiate a read/write command to the ARL table. The bit returns to 0 to indicate that a read/ write operation is complete.

6:1

Reserved

RO

Reserved

–

0

ARL_R/W

R/W

ARL table read/write bit Specifies whether the ARL command is a read or write operation. 1 = Read 0 = Write

0

For more information, see “Accessing see “Accessing the ARL Table Entries” on page 63. 63.

MAC Address Index Register (Page 05h: Address 02h) Table 114: MAC Address Address Index Register (Page (Page 05h: Address 02h–07h) BIt

Name

R/W

Description

Default

47:0

MAC_ADDR_INDX

R/W

MAC address index 0 The ARL table read/write command uses this 48-bit address to index the ARL table. When IEEE 802.1Q is enabled, the ARL table is indexed by a combined hash of the MAC_ADDR_INDX and the VID_TBL_INDX, defined in the “VLAN the “VLAN ID Index Register (Page 05h: Address 08h)” on page 186. 186. For more more inform informati ation, on, see “Ac “Acces cessin sing g the ARL Tab Table le Entries” on page 63. 63.


Page 185


BCM53128 Data Sheet


VLAN ID Index Register (Page 05h: Address 08h) Table 115: VLAN ID Index Register Register (Page 05h: Address 08h–09h) 08h–09h) BIt

Name

R/W

Description

Default

15:12

Reserved

R/W

Reserved

11:0

VID_INDX

R/W

VLAN ID index 0 When IEEE 802.1Q is enabled, the VLAN ID Index is used with the MAC_ADDR_INDX, defined in the “MAC “MA C Add Addres ress s Ind Index ex Reg Regist ister er (Pa (Page ge 05h 05h:: Add Addres ress s 02h)” on page 185, 185, to form the hash index for which status is to be read or written. For more information, see “Accessing see “Accessing the ARL Table Entries” on page 63. 63.

0

ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h) .

Table 116: ARL Table MAC/VID Entry Entry N (N=0-3) Register Address Summary Summary Address

Description

10h–17h

ARL Table MAC/VID Entry 0

20h–27h


30h–37h


40h–47h


Table 117: ARL Table MAC/VID Entry N (N=0-3) Register (Page (Page 05h: Address 10h–17h, 20h–27h, 30h– 37h, 40h–47h) BIt

Name

R/W

Description

Default

63:60

Reserved

R/O

Reserved

0

59:48

VID_N

R/W

VID entry N 0 The VID field is either read from or written to the ARL table entry N. The The VID VID is a “don “don’t ’t-c -car are” e” fiel field d when when IEEE IEEE 802. 802.1Q 1Q is disabled.

47:0

MACADDR_N

R/W

MAC address entry N The 48-bit MAC Address field to be either read from or written to the ARL table entry N.

0

Note: Together, Note: Together, the “ARL the “ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on page 186 and 186 and the “ARL the “ARL Table Data Entry N (N = 0–3) Register (Page 05h: Address 18h)” on page 187 comp compos ose e a comp comple lete te entr entry y in the the ARL ARL tabl table. e. For For more more infor informa mati tion on,, see see “Ac “Acces cessin sing g the ARL Tab Table le Ent Entrie ries” s” on page 63. 63.


Page 186


BCM53128 Data Sheet


ARL Table Data Entry N (N = 0–3) Register (Page 05h: Address 18h) .

Table 118: ARL Table Data Entry N (N=0-3) Register Register Address Address Summary Address

Description

18h–1Bh

ARL Table Data Entry 0

28h–2Bh


38h–3Bh


48h–4Bh


Table 119: ARL Table Data Entry N (N=0-3) Register Register (Page 05h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h–4Bh) BIt

Name

R/W

Description

Default

31:17

Reserved

RO

Reserved

0

16

VALID_N

R/W

Va Valid bit entry N Write this bit to 1 to indicate that a valid MAC address is stored in the MACADDR_N field defined in the “ARL the “ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on page 186, 186, and that the entry has not aged out. Reset when an entry is empty. This information information is read from or written written to the ARL table during a read/write command.

0

15

STATIC_N

RW

Static bit entry N 0 Write this bit to 1 to indicate that the entry is controlled by the external register control. When cleared, the internal learning and aging process controls the validity of the entry. This information information is read from or written written to the ARL table during a read/write command.

14

AGE_N

R/W

Age bit entry N 0 Writ Write e this this bitto 1 to indic indicat ate e that that an addr addres ess s entr entry y has been learned or accessed. This bit is set to 0 by the internal internal aging algorithm. algorithm. If the internal internal aging process detects detects that a valid entry has remained unused for the period set by the AGE_TIME (defined in the “Aging the “Aging Time Control Regist Reg ister er (Pa (Page ge 02h 02h:: Add Addres ress s 06h 06h)” )” on pag page e 170 170)) and the entry has not been marked as static, the entry has the valid bit cleared. The age bit is ignored if the entry has been marked as Static. This information information is read from or written written to the ARL table during a read/write command.


Page 187


BCM53128 Data Sheet


Table 119: ARL Table Data Entry N (N=0-3) Register Register (Page 05h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h–4Bh) 48h–4Bh) (Cont.) (Cont.) BIt

Name

R/W

Description

Default

13:11

TC_N

R/W

TC bit for MAC-based QoS entry N These bits define the TC field for MAC-based MAC-based QoS packets. This information information is read from or written written to the ARL table during a read/write command.

0

10:9

Reserved

R/W

Reserved

0

8:0

FWD_PRT_MAP_N

R/W

Multicast Group Forward portmap entry N 0 For multicast entries, these bits define the forward port map. Bit 8: CPU port/MII port Bits [7:0] correspond to ports [7:0], respectively.

PORTID_N

Unicast Forward PortID entry N For unicast entries, entries, these bits define the port number associated with the entry of the ARL table. Bits [8:4]: Reserved Bits [3:0]: Port ID/Port Number which identifies where the station with unique MACADDR_N is connected.

0

ARL Table Search Control Register (Page 05h: Address 50h) Table 120: ARL Table Search Search Control Register Register (Page 05h: Address 50h) BIt

Name

R/W

Description

Default

7

START/DONE

R/W (SC)

Start/done 0 Write as 1 to initiate a sequential search of the ARL table. Each entry found by the search is returned to the “ARL Table Search Data Result N (N = 0-1) Register (Page 05h: Address 68h)” on page 190 and 190 and the “ARL the “ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address 60h)” on page 189. 189. Read Reading ing the the “A “ARL RL Ta Tabl ble e Se Sear arch ch Da Data ta Re Resu sult lt N (N = 0-1) Register Register (Page 05h: Address 68h)” on page 190 allows 190 allows the ARL table search to continue. BCM53128 clears this bit when the ARL table search is complete.

6:1

Reserved

RO

Reserved

0

ARL_SR_VALID

RC

ARL search result valid 0 Set Set by BCM5 BCM531 3128 28 to indi indica cate te that that an ARL ARL entr entry y is foun found d by the the ARL table search. The found entry is i s available in the “ARL the “ARL Table Search Data Result N (N = 0-1) Register (Page 05h: Address 68h)” on page 190 190.. This This bit bit auto automa mati tica call lly y retu return rns s to 0 afte afterr the the ARL ARL Sear Search ch Resu Result lt register is read.

0


Page 188


BCM53128 Data Sheet



ARL Search Address Register (Page 05h: Address 51h) Table 121: ARL Search Search Address Register Register (Page 05h: Address 51h–52h) 51h–52h) Bit

Name

R/W

15

ARL_ADDR_VALI RO D

ARL ARL addr addres ess s vali valid d Indicates the lower 15 bits of this register contain a valid internal representation of the ARL entry that is currently being accessed. Intended for factory test/diagnostic use only.

14:0

ARL_ADDR

ARL address 0 14-bit internal representation of the address of the ARL entry currently being accessed by the ARL search routine. This is not a direct address of the ARL location and is intended for factory test/diagnostic use only.

RO

Description

Default 0

ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address Addre ss 60h) .

Table 122: ARL Table Search MAC/VID MAC/VID Result N (N=0-1) Register Register Address Summary Address

Description

60h–67h

ARL Table Search MAC/VID Result 0

70h–77h

ARL Table Search MAC/VID Result 1

Table Table 123: 123: ARL Table Table Search Search MAC/V MAC/VID ID Result Result N (N=0-1 (N=0-1)) Regist Register er (Page (Page 05h: 05h: Addres Address s 60h–67 60h–67h, h, 70h–77 70h–77h) h) BIt

Name

R/W

Description

Default

63:60

Reserved

RO

Reserved

0

59:48

ARL_SR_VID_N

RO

ARL search VID result These bits store the VID of the ARL table entry found by the ARL table search function.

0

47:0

ARL_SR_MAC_N

RO

ARL search MAC address result. These bits store the MAC address of the ARL table entry found by the ARL table search function.

0



Page 189


BCM53128 Data Sheet


ARL Table Search Data Result N (N = 0-1) Register (Page 05h: Address Addre ss 68h) Table 124: ARL Table Search Data Result N (N=0-1) (N=0-1) Register Address Summary Address

Description

68h–6Bh

ARL Table Search Data Result 0

78h–7Bh

ARL Table Search Data Result 1

Table 125: ARL Table Search Data Result Result N (N=0-1) (N=0-1) Register (Page (Page 05h: Address 68h–6Bh, 68h–6Bh, 78h–7Bh) BIt

Name

R/W

Description

Default

31:17

Reserved

RO

Reserved

0

16

ARL_SR_VALID_N

RO

ARL search valid bit result. 0 This bit stores the valid bit of the ARL table entry foun found d by the the ARL ARL table table sear search ch func functi tion on.. Read Readin ing g this register clears the data from the register and allows the ARL table search function to continue searching.

15

ARL_SR_STATIC_N

RO

ARL search static bit result. 0 This This bit bit stor stores es the the stat static ic bit bit of the the ARL ARL tabl table e entr entry y foun found d by the the ARL ARL table table sear search ch func functi tion on.. Read Readin ing g this register clears the data from the register and allows the ARL table search function to continue searching.

14

ARL_SR_AGE_N

RO

ARL search age bit result. 0 This bit stores the Age bit of the ARL table entry foun found d by the the ARL ARL table table sear search ch func functi tion on.. Read Readin ing g this register clears the data from the register and allows the ARL table search function to continue searching.

13:11

ARL_SR_TC_N

RO

ARL search TC bits result. 0 These bits store the TC bits of the ARL table entry found by the ARL table search function. Reading Reading this register register clears the data from the regist register er and allows allows the ARL table table search search functi function on to continue searching.

10:9

Reserved

RO

Reserved

0


Page 190


BCM53128 Data Sheet


Table 125: ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address Address 68h–6Bh, 78h–7Bh) BIt

Name

R/W

Description

Default

8:0

FWD_PRT_MAP_N

R/W

Multicast Group Forward portmap entry N For multicast entries, these bits define the forward port map. Bit 8: CPU port/MII port Bits [7:0] correspond to ports [7:0]

0

Unicast Forward PortID entry N For unicast entries, entries, these bits define the port number associated with the entry of the ARL table. Bits [8:4]: Reserved Bits [3:0]: Port ID/Port Number which identifies where the station with unique MACADDR_N is connected.

0

PORTID_N


VLAN Table Read/W Read/Write/C rite/Clear lear Control Register (Page 05h: Addr Address ess 80h) Table 126: VLAN Table Read/Write/Clear Read/Write/Clear Control Register (Page (Page 05h: Address 80h) BIt

Name

R/W

Description

Default

7

START/DONE

R/W (SC)

Start/done command 0 Write as 1 to initiate a read or write or clear-table command to the VLAN table. The bit returns to 0 to indicate indicate that the read or write write or clear-table clear-table operation is complete.

6:2

Reserved

R/W

Reserved

0

1:0

VTBL_R/W/Clr

R/W

Read/Write/Clear-table Specifies whether the current VLAN table read/write/ clear-table command is a read or write or clear-table operation. 11 = Reserved Reserved 10 = Clear-table 01 = Read 00 = Write

0

See “Programming See “Programming the VLAN Table” on page 40 for 40 for more information.


Page 191


BCM53128 Data Sheet


VLAN Table Address Index Register (Page 05h: Address 81h) Table 127: VLAN Table Address Address Index Register Register (Page 05h: Address 81h–82h) 81h–82h) BIt

Name

R/W

Description

Default

15:12

Reserved

RO

Reserved

0

11:0

VTBL_ADDR_INDX

R/W

VLAN table address index 0 The curren currentt VLAN VLAN table table read/w read/writ rite e uses uses this this 12-bit 12-bit address address to index the VLAN table.


VLAN Table Entry Register (Page 05h: Address 83h–86h) Table 128: VLAN Table Table Entry Register (Page (Page 05h: Address 83h–86h) BIt

Name

R/W

Description

Default

31:22

Reserved

RO

Reserved

0

21

FWD_MODE

R/W

This indicates whether the packet forwarding 0 shou should ld be base based d on VLAN VLAN memb member ersh ship ip or base based d on ARL flow. 1: Based on VLAN membership (excluding Ingress port) 0: Based on ARL flow. Note that the VLAN membership based forwarding forwarding mode is only used for certain certain ISP Tagged packets received from ISP port when BCM53128 BCM53128 is operating operating in Double Tag Mode.

20:18

MSPT_INDEX

R/W

Index for 8 Spanning Trees

17:9

UNTAG_MAP

R/W

Un U ntagged Port Map 0 Bit 17: CPU Port/ MII Port Bits Bits [16:9] [16:9] corres correspon pond d to ports ports [7:0], [7:0], respec respectiv tively ely.. Ports written to 1 are designated as untagged VLAN ports. VLAN-tagged frames destined for these ports are untagged before they are forwarded. When the IEEE 802.1Q feature is enabled, frames sent via the CPU (MII port configured as a management port) are tagged. Note that the packet forwarded to IMP port should always be VLAN tagged. tagged.

0


Page 192


BCM53128 Data Sheet


Table 128: 128: VLAN Table Table Entry Register Register (Page (Page 05h: Address Address 83h–86h) 83h–86h) (Cont.) (Cont.) BIt

Name

R/W

Description

Default

8:0

FWD_MAP

R/W

Forward Port Map 0 The VLAN-tagged VLAN-tagged Frame is allowed allowed to be forwar forwarded ded to the destin destinati ation on ports ports corres correspon ponding ding bits set in the Map Ports written to 1 are designated designated as capable capable of receiving receiving VLAN-tagge VLAN-tagged d frames. Bit 8: CPU Port/ MII Port Bits [7:0] correspond to Ports [7:0], respectively.



Page 193


BCM53128 Data Sheet

Page 10h–17h: Internal GPHY MII Registers

Page 10h–17h: Internal GPHY MII Registers Table 129: 10/100/1000 10/100/1000 PHY Page Page Summary Page

Description

10h

Port 0 Internal PHY MII Registers

11h


12h


13h


14h


15h


16h


17h


Table 130: 130: Register Register Map (Page (Page 10h – 17h) 17h) SPI Offset Offset MII Number Address Address of Bits Bits Regist Register er Table Table 10BASE-T/100BASE-TX/1000BAS 10BASE-T/100BASE-TX/1000BASE-T E-T Registers 00h

00h

16

Table 131: “MII Control Register (Page 10h–17h: Address 00h–01h),” on page 196

02h

01h

16

Table 132: “MII Status Register (Page 10h–17h: Address 02h–03h),” on page 197

04h–06h

02h

32

Table 133: “PHY Identifier Register MSB (Page 10h–17h: Address 04–07h),” on page 198

08h

04h

16

Table 135: “Auto-Negotiation Advertisement Register (Page 10h–17h: Address 08h–09h),” on page 199

0Ah

05h

16

Table 136: “Auto-Negotiation Link Partner Ability Register (Page 10h–17h: Address 0Ah–0Bh),” 0Ah–0B h),” on page 200

0Ch

06h

16

Table 136: “Auto-Negotiation Link Partner Ability Register (Page 10h–17h: Address 0Ah–0Bh),” 0Ah–0B h),” on page 200

0Eh

07h

16

Table 138: “Next Page Transm Transmit it Regist Register er (Page 10h–17 10h–17h: h: Addre Address ss 0Eh–0F 0Eh–0Fh),” h),” on page 202

10h

08h

16

Table 139: “Link Partner Received Next Page Register (Page 10h–17h: Address 10h–11h),” on page 203

12h

09h

16

Table 140: “1000BASE-T Control Register (Page 10h–17h: Address 12h– 13h),” on page 204

14h

0Ah

16

Table 141: “1000B “1000BASE-T ASE-T Statu Status s Regis Register ter (Page 10h–17 10h–17h: h: Addres Address s 14h–15 14h–15h),” h),” on page 205

16h– 16h–1D 1Dh h

–

16

Reser eserve ved d (Do (Do not not read read from from or write rite to a reser eserv ved regis egistter. er.)

1Eh

0Fh

16

Table 142: “IEEE Extended Status Register (Page 10h–17h: Address 1Eh– 1Fh),” on page 206

20h

10h

16

Table 143: “PHY Extended Control Register (Page 10h–17h: Address 20h– 21h),” on page 207


Page 194


BCM53128 Data Sheet


Table 130: 130: Register Register Map (Page (Page 10h – 17h) 17h) (Cont.) SPI Offset Offset MII Number Address Address of Bits Bits Regist Register er Table Table 22h

11h

16

Table 144: “PHY Extended Status Register (Page 10h–17h: Address 22h– 23h),” on page 208

24h

12h

16

Table 145: “Receive Error Counter Register (Page 10h–17h: Address 24h– 25h),” on page 209

26h

13h

16

Table 146: “False Carrier Sense Counter Register (Page 10h–17h: Address 26h–27h),” on page 209

28h

14h

16

Table 148: “Receiver NOT_OK Counter Register (Page 10h–17h: Address 28h–29h),” on page 210

2Ah– 2Ah–2C 2Ch h

15h– 15h–16 16h h

2Eh

17h

16

Table 150: “Expansion Register Access Register (Page 10h–17h: Address 2Eh–2Fh),” on page 211

30h

18h

16

Table 155: “Auxiliary Control Register (Page 10h–17h: Address 30h, Shadow Value 000),” on page 213 Table 156: “10BASE-T Register (Page 10h–17h: Address 30h, Shadow Value 001),” on page 214 Table 157: “Powe “Power/MI r/MIII Cont Control rol Regis Register ter (Page 10h–1 10h–17h: 7h: Addres Address s 30h, Shadow Value 010),” on page 215 Table 158: “Miscellaneous Test Register (Page 10h–17h: Address 30h, Shadow Value 100),” on page 216 Table 159: “Miscellaneous Control Register (Page 10h–17h: Address 30h, Shadow Value 111),” on page 217

32h

19h

16

Table 160: “Auxiliary Status Summary Register (Page 10h–17h: Address 32h– 33h),” on page 218

34h

1Ah

16

Table 161: “Interrupt Status Register (Page 10h–17h: Address 34h–35h),” on page 219

36h

1Bh

16

Table 162: “Interrupt Mask Register (Page 10h–17h: Address 36h),” on page 220

38h

1Ch

16

Table 164: “Spare Control 2 Register (Page 10h–17h: Address 38h, Shadow Value 00100),” 00100),” on page 221 Table 164: “Spare Control 2 Register (Page 10h–17h: Address 38h, Shadow Value 00100),” 00100),” on page 221 Table 165: “Auto Power Power-Dow -Down n Regis Register ter (Page 10h–1 10h–17h: 7h: Addres Address s 38h, Shadow Value 01010),” 01010),” on page 222 Table 167: “Mode Control Register (Page 10h–17h: Address 38h, Shadow Value 11111),” 11111),” on page 225

3Ah

1Dh

16

Table 168: “Master/Slave Seed Register (Page 10h–17h: Address 3Ah–3Bh) Bit 15 = 0,” on page 226 Table 169: “HCD Status Register (Page 10h–17h: Address 3Ah–3Bh) Bit 15 = 1,” on page 227

3Ch

1Eh

16

Table 170: “Test Register 1 (Page 10h–17h: Address 3C–3Dh),” on page 228

3Eh

1Fh

16

Reserved (Do not read from or write to a reserved regist ister.)

Reser eserve ved d (Donotreadfr Donotreadfromor omor writ write e to a rese reserrved ved regi regist sterexc erexcep eptt foracces oraccessi sing ng the Expansion registers through register 15h.)


Page 195


BCM53128 Data Sheet


Table 130: 130: Register Register Map (Page (Page 10h – 17h) 17h) (Cont.) SPI Offset Offset MII Number Address Address of Bits Bits Regist Register er Table Table Expansion Registers: Read/Write through Register 2Ah (Accessed by Writing to Register 2Eh, Bits [11:0] = 1111 + Expansion Register Number) 00h

–

–

Table 171: “Expansion Register 00h: Receive/Transmit Packet Counter,” on page 229

01h

–

–

Table Tab le 172 172:: “Ex “Expan pansio sion n Reg Regist ister er 01h 01h:: Exp Expans ansion ion Int Interr errupt upt Sta Status tus,” ,” on pag page e 229

04h

–

–

–

05h

–

–

–

07h

–

–

–

45h

–

–

Table 173: “Expansion Register 45h: Transmit CRC,” on page 230

MII Control Register (Page 10h – 17h: 17h: Address 00h–01h 00h–01h)) Table 131: MII Control Control Register Register (Page 10h – 17h: 17h: Address 00h–01h) Bit

Name

R/W

Description

Default

15

Reset

R/W SC

1 = PHY reset 0 = Normal Normal operation

0

14

Internal Loopback

R/W

1 = Loopback mode 0 = Normal Normal operation

0

13

Speed Selection (LSB)

R/W

Bits [6,13]: 11 = Reserved Reserved 10 = 1000 Mbps 01 = 100 Mbps 00 = 10 Mbps

0

12

Auto Auto--nego negoti tiat atio ion n Enab Enable le

R/W

1 = Aut Auto-ne o-nego gottiat iation ion is enab enable led. d. 0 = Auto-negotiation is disabled.

1

11

Power Down

R/W

1 = Power-down 0 = Normal Normal operation

0

10

Isolate

R/W

1 = Electrically isolate PHY from GMII. 0 = Normal Normal operation

0

9

Restart Auto-negotiation

R/W SC

1 = Restarting auto-negotiation 0 = Auto-negotiation restart is complete.

0

8

Duplex Mode

R/W

1 = Full-duplex 0 = Half-duplex Half-duplex

1

7

Collision Test Enable

R/W

1 = Enable the collision test mode. 0 = Disable the collision test mode.

0

6

Speed Selection (MSB)

R/W

Works in conjunction with bit 13

1

5

Reserved

R/W

Write as 0, ignore on read.

0

4

Reserved

R/W

Write as 0 ignore on read

0

3

Reserved

R/W


0


Page 196


BCM53128 Data Sheet


Table 131: MII Control Control Register Register (Page 10h – 17h: 17h: Address Address 00h–01h) 00h–01h) (Cont.) (Cont.) Bit

Name

R/W

Description

Default

2

Reserved

R/W


0

1

Reserved

R/W


0

0

Reserved

R/W


0

MII Status Register (Page 10h – 17h: 17h: Address 02h) Table 132: MII Status Status Register Register (Page (Page 10h – 17h: 17h: Address 02h – 03h) 03h) Bit

Name

R/W

Description

Default

15

100BASE-T4 Capable

RO L

1 = 100BASE-T4 100BASE-T4 capable 0 = Not 100BASE-T4 capable

0

14

100B 100BAS ASEE-X X Full Full-D -Dup uple lex x Capable

RO H

1 = 100BASE-X full-duplex capable 0 = Not 100BASE-X 100BASE-X full-duplex full-duplex capable

1

13

100B 100BAS ASEE-X X Half Half-D -Dup uple lex x Capable

RO H

1 = 100BASE-X half-duplex capable 0 = Not 100BASE-X half-duplex capable

1

12

10BA 10BASE SE-T -T Full Full-D -Dup uple lex x Capable

RO H

1 = 10BASE-T 10BASE-T full-duplex capable 0 = Not 10BASE-T full-duplex full-duplex capable

1

11

10BA 10BASE SE-T -T Half Half-D -Dup uple lex x Capable

RO H

1 = 10BASE-T half-duplex capable 0 = Not 10BASE-T half-duplex capable

1

10

100B 100BAS ASEE-T2 T2 Full Full-D -Dup uple lex x Capable

RO L

1 = 100BASE-T2 full-duplex capable 0 = Not 100BASE-T2 full-duplex capable

0

9

100B 100BAS ASEE-T2 T2 Half alf-Dup -Duple lex x Capable

RO L

1 = 100BASE-T2 half-duplex capable 0 = Not 100BASE-T2 half-duplex capable

0

8

Extended Status

RO H

1 = Extended status information in reg 0Fh 0 = No extended status information in reg 0Fh

1

7

Reserved

RO

Ignore on read.

0

6

Management Frames Preamble Suppression

RO H

1 = Preamble can be suppressed. 0 = Preamble always required

1

5

Aut Auto-ne o-nego goti tiat atio ion n Compl omplet ete e

RO

1 = Aut Auto-ne o-nego gottiat iation ion is com complet plete. e. 0 = Auto-negotiation is in progress.

0

4

Remote Fault

RO LH

1 = Remote fault detected. 0 = No remote fault detected.

0

3

Auto-negotiation Ability

RO H

1 = Auto-negotiation capable 0 = Not auto-negotiation capable

1

2

Link Status

RO LL

1 = Link is up (link pass state). 0 = Link is down (link fail state).

0

1

Jabber Detect

RO LH

1 = Jabber condition detected. 0 = No jabber condition detected. detected.

0

0

Extended Capability

RO H

1 = Extended register capabilities 0 = No extended register capabilities

1


Page 197


BCM53128 Data Sheet


PHY Identifier Register (Page 10h – 17h: 17h: Address 04h) Table 133: PHY Identifi Identifier er Register Register MSB (Page 10h – 17h: 17h: Address 04 – 07h) 07h) Bit

Name

R/W

Description

Default

15:0

OUI

RO

Bits 3: 3 :18 of o f or organizationally un unique id i dentifier 0362

Table 134: PHY Identifie Identifierr Register Register LSB (Page 10h – 17h: 17h: Address 06h – 07h) 07h) Bit

Name

R/W

Description

Default

15:10

OUI

RO

Bits 19:24 of organizationally unique identifier

010111

9:4

MODEL

RO

Device model number

100001

3:0

REVISION

RO

Device revision number

na (hex)

a.

The revisi revision on number number (n) changes with each silicon revision.

The IEEE has issued an Organizationally Unique Identifier (OUI) to Broadcom Corporation. This 24-bit number allows devices developed by Broadcom to be distinguished from all other manufacturers. The OUI combined with model numbers and revision numbers assigned by Broadcom precisely identifies a device manufactured by Broadcom. The [15:0] bits of MII register 02h (PHYID HIGH) contain OUI bits [3:18]. The [15:0] bits of MII register 03h (PHYID LOW) contain the most significant OUI bits [19:24], six manufacturer’s model number bits, and four revision number bits. The two least significant OUI binary bits are not used. Broadcom Corporation's OUI is 00-1B-E9, expressed as hexadecimal values. The binary OUI is 0000-00000001-1011-1110-1001. The model number for the BCM53128 is 21H. Revision numbers start with 0h and increment by 1 for each chip modification. •

PHYID HIGH[15:0 HIGH[15:0]] = OUI[3:18] OUI[3:18]

•

PHYID LOW[15:0] LOW[15:0] = OUI[19:24 OUI[19:24]] + Model[5:0 Model[5:0]] + Revision Revision [3:0] [3:0]


Page 198


BCM53128 Data Sheet


Auto-Negotiation Advertisement Register (Page 10h – 17h: 17h: Address 08h) Table 135: Auto-Negotiation Advertisement Advertisement Register (Page (Page 10h – 17h: 17h: Address 08h – 09h) 09h) Bit

Name

R/W

Description

Default

15

Next Page

R/W

1 = Next page ability is supported. 0 = Next page ability is not supported.

0

14

Reserved

R/W


0

13

Remote Fault

R/W

1 = Advertise remote fault is detected. 0 = Advertise no remote fault is detected.

0

12

Reserved Technology

R/W


0

11

Asymmetric Pause

R/W

1 = Advertise asymmetric pause 0 = Advertise no asymmetric pause

1

10

Pause Capable

R/W

1 = Capable of full-duplex pause operation 1 0 = Not capable of pause operation

9

100BASE-T4 Capable

R/W

1 = 100BASE-T4 capable 0 = Not 100BASE-T4 capable

0

8

100BASE-TX FullDuplex Capable

R/W

1 = 100BASE 100BASE-TX -TX full-d full-dupl uplex ex capable capable 0 = Not 100BASE-TX full-duplex capable

1

7

100BASE-TX HalfDuplex Capable

R/W

1 = 100BASE 100BASE-TX -TX half-d half-duple uplex x capabl capable e 1 0 = Not 100BASE-TX half-duplex capable

6

10BASE-T Full-Duplex Capable

R/W

1 = 10BASE10BASE-T T full-d full-dupl uplex ex capabl capable e 0 = Not 10BASE-T 10BASE-T full-duplex full-duplex capable

1

5

10BASE-T Half-Duplex Capable

R/W

1 = 10BASE10BASE-T T half-d half-duple uplex x capabl capable e 0 = Not 10BASE-T 10BASE-T half-duplex half-duplex capable

1

4

Prot Protoc ocol ol Sele Select ctor or Fiel Field d

R/W

Bit Bits [4:0] 4:0] = 0000 00001 1 indi indica cattes IEEE 802.3 CSMA/CD

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

1


Page 199


BCM53128 Data Sheet


Auto-Negotiation Link Partner Ability Register (Page 10h – 17h: 17h: Address Addre ss 0Ah) Table 136: Auto-Negotiation Link Link Partner Ability Register (Page 10h – 17h: 17h: Address 0Ah – 0Bh) 0Bh) Bit

Name

R/W

Description

Default

15

Next Page

RO

1 = Link partner has next page ability. 0 = Link partner does not have next page ability.

0

14

Acknowledge

RO

1 = Link partner has received link code word. 0 = Link partner has not received link code word.

0

13

Remote Fault

RO

1 = Link partner has detected remote fault. 0 = Link partner has not detected remote fault.

0

12

Reserved Technology

RO


0

11

Link Link Partne Partnerr Asymm Asymmetr etric ic Pause Pause RO

1 = Link Link partne partnerr wants wants asymme asymmetri tric c pause. pause. 0 = Link partner does not want asymmetric pause.

0

10

Pause Capable

RO

1 = Link partner is capable of pause operation. 0 = Link partner is not capable of pause operation.

0

9

100BASE-T E-T4 Capable

RO

1 = Link partner is 100BAS ASE E-T4 capable. 0 = Link partner is not 100BASE-T4 capable.

0

8

100B 100BAS ASEE-TX TX Full Full-D -Dup uple lex x Capable

RO

1 = Link Link partne partnerr is 100BASE 100BASE-TX -TX full-d full-dupl uplex ex capa capable ble.. 0 0 = Link partner partner is not 100BASE-TX 100BASE-TX full-duplex full-duplex capable.

7

100B 100BAS ASEE-TX TX Half Half-D -Dup uple lex x Capable

RO

1 = Link partner partner is 100BASE-TX 100BASE-TX half-duplex half-duplex capable. capable. 0 0 = Link partner not 100BASE-TX half-duplex capable.

6

10BA 10BASESE-T T Full Full-D -Dup uple lex x Capa Capabl ble e RO

1 = Link Link part partne nerr is 10BAS 10BASEE-T T fullfull-du dupl plex ex capa capabl ble. e. 0 0 = Link partner is not 10BASE-T full-duplex capable.

5

10BASE10BASE-T T Half-D Half-Duple uplex x Capabl Capable e RO

1 = Link Link partne partnerr is 10BASE10BASE-T T half-d half-duple uplex x capabl capable. e. 0 = Link partner is not 10BASE-T half-duplex capable.

0

4

Protocol Selector Field

Link partner protocol selector field

0

RO

3

RO

0

2

RO

0

1

RO

0

0

RO

0

Note: As Note: As indicated by bit 5 of the 10BASE-T/100BASE-TX/1000BASE-T MII Status register, the values contai contained ned in the 10BASE10BASE-T/1 T/100B 00BASE ASE-TX -TX/10 /1000B 00BASE ASE-T -T Auto-n Auto-nego egotia tiatio tion n Link Link Partne Partnerr Ability Ability regist register er are only guaranteed to be valid after auto-negotiation has successfully completed.


Page 200


BCM53128 Data Sheet


Next Page BCM53128 returns a 1 in bit 15 when the link partner wants to transmit Next Page information.

Acknowledge BCM53128 returns a 1 in bit 14 when the link partner has acknowledged reception of the link code word; otherwise, BCM53128 returns a 0.

Auto-Negotiation Expansion Register (Page 10h – 17h: 17h: Address 0Ch) Table 137: Auto-Negotiation Expansion Register (Page 10h – 17h: 17h: Address 0Ch – 0Dh) 0Dh) Bit

Name

R/W

Description

Default

15

Reserved

R0

Ignore on read.

0

14

Reserved

R0

Ignore on read.

0

13

Reserved

R0

Ignore on read.

0

12

Reserved

R0

Ignore on read.

0

11

Reserved

R0

Ignore on read.

0

10

Reserved

R0

Ignore on read.

0

9

Reserved

R0

Ignore on read.

0

8

Reserved

R0

Ignore on read.

0

7

Reserved

R0

Ignore on read.

0

6

Next ext Page Page Recei eceive ve Loca Locati tion on Able

R/W

1 = Bit 5 in regist register er 06h determ determine ines s next next page page receive location. 0 = Bit 5 in register 06h does not determine next page receive location.

1

5

Next Next Page Page Rece Receiv ive e Loca Locati tion on

R/W R/W

1 = Next Next page pages s stor stored ed in regi regist ster er 08h. 08h. 0 = Next pages stored in register 05h.

1

4

Parallel Detection Fault

RO LH

1 = Parallel link fault is detected. 0 = Parallel link fault is not detected.

0

3

Link Link Part Partne nerr Next Next Page Page Abil Abilit ity y RO

1 = Link Link part partne nerr has has next next page page capa capabi bili lity ty.. 0 0 = Link Link part partne nerr does does not not have have next next page page capa capabil bilit ity. y.

2

Next Page Capable

RO H

1 = BCM53128 is next page capable. 0 = BCM53128 is not next page capable.

1

Page Received

RO LH

1 = New page has been received from link partner. 0 0 = New page has not been received.

0

Link Link Part Partne nerr Auto Auto-n -neg egot otia iati tion on Ability

RO

1 = Link partne partnerr has auto-n auto-nego egotia tiatio tion n capabi capability lity.. 0 = Link partner partner does not have auto-negotiation auto-negotiation..

1

0


Page 201


BCM53128 Data Sheet


Next Page Transmit Register (Page 10h – 17h: 17h: Address 0Eh) Table 138: Next Page Transmit Transmit Register Register (Page 10h – 17h: 17h: Address 0Eh – 0Fh) 0Fh) Bit

Name

R/W

Description

Default

15

Next Page

R/W

1 = Additional next pages follow. 0 = Sending last next page.

0

14

Reserved

RO

Ignore on read.

0

13

Message Page

R/W

1 = Formatted page 0 = Unformatted page

1

12

Acknowledge2

R/W

1 = Complies with message. 0 = Cannot Cannot comply with message. message. Note: Not Note: Not used with 1000BASE-T next pages.

0

11

Toggle

RO

Toggles be between ex exchanges of of di different ne next 0 pages.

10

Mess Messag age/ e/Un Unfo form rmat atte ted d Code Code Field

R/W

Next Next page page messag message e code code or unform unformatt atted ed data

9

R/W

0 0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

1


Page 202


BCM53128 Data Sheet


Link Partner Received Next Page Register (Page 10h – 17h: 17h: Addre Address ss 10h) Table 139: Link Partner Partner Received Received Next Page Register Register (Page 10h – 17h: 17h: Address 10h – 11h) 11h) Bit

Name

R/W

Description

Default

15

Next Page

RO

1 = Additional next pages follow. 0 = Sending last next page.

0

14

Acknowledge

RO

1 = Acknowledge 0 = No acknowledge

0

13

Message Page

RO

1 = Formatted page 0 = Unformatted page

0

12

Acknowledge2

RO

1 = Complies with message. 0 = Cannot comply with message. message. Note: Not Note: Not used with 1000BASE-T next pages.

0

11

Toggle

RO

Toggles be between ex exchanges of of di different ne next pa pages. 0

10

Message Code field

RO

Next page message code or unformatted data

0

9

RO

0

8

RO

0

7

RO

0

6

RO

0

5

RO

0

4

RO

0

3

RO

0

2

RO

0

1

RO

0

0

RO

0


Page 203


BCM53128 Data Sheet


1000BASE-T 1000BAS E-T Control Register (Page 10h – 17h: 17h: Address 12h) Table 140: 1000BASE-T Control Control Register (Page 10h – 17h: 17h: Address 12h – 13h) 13h) Bit

Name

R/W

Description

15

Test Mode

R/W

1 X X = Test mode 4—Transmitter distortion test. 0 0 1 1 = Test mode 3—Slave transmit jitter test. 0 0 1 0 = Test mode 2—Master transmit jitter test. 0 0 0 1 = Test mode 1—Transmit waveform test. 0 0 0 = Normal operation

14

R/W

13

R/W

Default

12

Master/Sla Slave Configuration Enable

R/W

1 = Enable master/sla master/slave ve manual manual configurati configuration on value. 0 = Automatic master/slave configuration

0

11

Master/Sla Slave Configuration Value

R/W

1 = Config Configure ure PHY as master master.. 0 = Configure PHY as slave.

1

10

Repeater/DTE

R/W

1 = Repeater/switch device ice port 0 = DTE device

1

9

Advertise 1000BAS ASE E- R/W R/W T Full-Duplex Capability

1 = Adve Advert rtis ise e 1000 1000BA BASE SE-T -T fullfull-du dupl plex ex capa capabil bilit ity. y. 1 0 = Advertise no 1000BASE-T full-duplex capability.

8

Advertise 1000BAS ASE E- R/W T Half-Duplex Capability

1 = Advert Advertise ise 1000BAS 1000BASE-T E-T half-d half-duple uplex x capability. 0 = Advertise no 1000BASE-T half-duplex capability.

1

7

Reserved

RO

Ignore on read.

0

6

Reserved

RO

Ignore on read.

0

5

Reserved

RO

Ignore on read.

0

4

Reserved

RO

Ignore on read.

0

3

Reserved

RO

Ignore on read.

0

2

Reserved

RO

Ignore on read.

0

1

Reserved

RO

Ignore on read.

0

0

Reserved

RO

Ignore on read.

0

Test Mode The BCM53128 can be placed in 1 of 4 transmit test modes by writing bits [15:13] of the 1000BASE-T Control register. register. The transmit test modes are defined defined in IEEE 802.3ab. 802.3ab. When read, these bits return the last value written. written. For test modes 1, 2, and 4, the PHY must have auto-negotiat auto-negotiation ion disabled and forced forced to 1000BASE-T 1000BASE-T mode and Auto-MDIX disabled. •

Disable Disable auto-negotia auto-negotiation tion and force force to 1000BASE-T 1000BASE-T mode (write (write to register register 00h = 0x0040) 0x0040)

•

Disable Disable Auto-MDIX Auto-MDIX (write (write to registe registerr 18h, shadow shadow value value 111, bit 9 = 0)

•

Enter test test modes modes (write (write to register register 09h, bits bits [15:13] [15:13] = the desired desired test test mode) mode)


Page 204


BCM53128 Data Sheet


Master/Slave Configuration Enable When bit 12 is set = 1, the BCM53128 master/sla master/slave ve mode is configured using the manual master/slave master/slave config configura uratio tion n value. value. When When the bit is cleare cleared, d, the master master/sl /slave ave mode mode is config configure ured d using using the automa automatic tic resolu resolutio tion n function. This bit returns a 1 when manual master/slave configuration is enabled; otherwise, it returns a 0.

1000BASE-T Status Register (Page 10h – 17h: 17h: Address 14h) Table 141: 1000BASE 1000BASE -T Status Register (Page 10h – 17h: 17h: Address 14h – 15h) 15h) Bit

Name

R/W

Description

Default

15

Mast Master er/S /Sla lave ve Conf Config igur urat atio ion n Faul Faultt

RO LH

1 = Master/slave configuration fault detected. 0 = No master/slave configuration fault detected.

0

14

Master Master/Sl /Slave ave Config Configura uratio tion n Resolution

RO

1 = Loca Locall tran transm smit itte terr is mast master er.. 0 = Local transmitter transmitter is slave.

0

13

Local Receiver Status

RO

1 = Local receiver is OK. 0 = Local receiver is not OK.

0

12

Remote Receiver Status

RO

1 = Remote receiver is OK. 0 = Remote receiver is not OK.

0

11

Link Link Partn Partner er 1000 1000BAS BASEE-T T Full-Duplex Capability

RO

1 = Link partne partnerr is 1000BA 1000BASESE-T T full-d full-dupl uplex ex capable. 0 = Link partner is not 1000BASE-T 1000BASE-T full-duplex capable.

0

10

Link Link Partn Partner er 1000 1000BAS BASEE-T T Half-Duplex Capability

RO

1 = Link partne partnerr is 1000BA 1000BASESE-T T half-du half-duple plex x capable. 0 = Link partner is not 1000BASE-T 1000BASE-T half-duplex capable.

0

9

Reserved

RO

Ignore on read.

0

8

Reserved

RO

Ignore on read.

0

7

Idle Error Count

RO CR

Number of idle errors since last read

0

6

RO CR

0

5

RO CR

0

4

RO CR

0

3

RO CR

0

2

RO CR

0

1

RO CR

0

0

RO CR

0


Page 205


BCM53128 Data Sheet


Note: As Note: As indicated by bit 5 of the MII Status register (0h), the values contained in bits 14, 11, and 10 of the 1000BASE-T Status register are guaranteed to be valid only after auto-negotiation has successfully completed.

IEEE Extended Status Register (Page 10h – 17h: 17h: Address 1Eh) Table 142: IEEE Extended Extended Status Status Register (Page 10h – 17h: 17h: Address 1Eh – 1Fh) 1Fh) Bit

Name

R/W

Description

Default

15

1000 1000BA BASE SE-X -X Full Full-D -Dup uple lex x Capable

RO L

1 = 1000BASE-X full-duplex capable 0 = Not 1000BASE-X full-duplex capable

0

14

1000 1000BA BASE SE-X -X Half Half--Duple uplex x Capable

RO L

1 = 1000BASE-X half-duplex capable 0 = Not 1000BASE-X half-duplex capable

0

13

1000 1000BA BASE SE-T -T Full Full-D -Dup uple lex x Capable

RO H

1 = 1000BASE-T full-duplex capable 0 = Not 1000BASE-T full-duplex capable

1

12

1000 1000BA BASE SE-T -T Half Half-D -Dup uple lex x Capable

RO H

1 = 1000BASE-T half-duplex capable 0 = Not 1000BASE-T half-duplex capable

1

11

Reserved

RO

Ignore on read.

0

10

Reserved

RO

Ignore on read.

0

9

Re R eserved

RO

Ignore on read.

0

8

Re R eserved

RO

Ignore on read.

0

7

Re R eserved

RO

Ignore on read.

0

6

Re R eserved

RO

Ignore on read.

0

5

Re R eserved

RO

Ignore on read.

0

4

Re R eserved

RO

Ignore on read.

0

3

Re R eserved

RO

Ignore on read.

0

2

Re R eserved

RO

Ignore on read.

0

1

Re R eserved

RO

Ignore on read.

0

0

Re R eserved

RO

Ignore on read.

0


Page 206


BCM53128 Data Sheet


PHY Extended Control Register (Page 10h – 17h: 17h: Address 20h) Table 143: PHY Extended Extended Control Register Register (Page 10h – 17h: 17h: Address 20h – 21h) 21h) Bit

Name

R/W

Description

Default

15

Reserved

R/W


0

14

Disa Disabl ble e Auto Automa mati tic c MDI MDI Crossover

R/W R/W

1 = Autom Automat atic ic MDI MDI cros crosso sove verr is disa disabl bled ed.. 0 = Automatic MDI crossover crossover is enabled. enabled.

0

13

Transmit Disable

R/W

1 = Transmitter outputs are disabled. 0 = Normal operation

0

12:11 Reserved

–

–

–

10

Bypa Bypass ss 4B/5 4B/5B B Enco Encode der/ r/ Decoder (100BASE-T)

R/W R/W

1 = Tran Transm smit it and and rece receiv ive e 5B code codes s over over MII MII pins. 0 = Normal MII

0

9

Bypa BypassScr ssScram ambl bler er/D /Des escr cram ambl bler er R/W (100BASE-T)

1 = Scramb Scrambler ler and descra descrambl mbler er are disabl disabled. ed. 0 0 = Scrambler and descrambler are enabled.

8

Bypa Bypass ss NRZI NRZI/M /MLT LT3 3 Enco Encode der/ r/ Decoder (100BASE-T)

R/W

1 = Bypass Bypass NRZI/M NRZI/MLT3 LT3 encode encoderr and decode decoder. r. 0 0 = Normal operation

7

Bypa Bypass ss Recei eceive ve Sym Symbol bol Alignment (100BASE-T)

R/W R/W

1 = The The 5B rece receiv ive e symb symbol ols s are are not not align aligned ed.. 0 0 = Rece Receive ive symb symbols ols align aligned ed to 5B boun bounda dari ries es

6

Rese Resett Scra Scramb mble lerr (100 (100BA BASE SE-T -T)) R/W R/W SC

1 = Reset scrambler to initial state. state. 0 = Normal scrambler operation

0

5:3

Reserved

–

–

–

2

Reserved

R/W


0

1

Reserved

R/W


0

0

1000 1000 Mbps bps PCS PCS Tran Transm smit it FIFO FIFO R/W Elasticity

1 = High lat latency 0 = Low latency

0


Page 207


BCM53128 Data Sheet


PHY Extended Status Register (Page 10h – 17h: 17h: Address 22h) Table 144: PHY Extended Extended Status Status Register Register (Page 10h – 17h: 17h: Address 22h – 23h) 23h) Bit

Name

R/W

Description

Default

15

Auto Auto-n -neg egot otiat iatio ion n Base Base Page Page Selector Field Mismatch

RO LH

1 = Link partner base page selector field mismatched advertised selector field since last read. 0 = No mismatch detected since last read.

0

14

Ethe Ethern rnet et@W @Wir ireS eSpe peed ed Downgrade

RO

1 = Auto-n Auto-nego egotia tiatio tion n advert advertise ised d speed speed downgr downgrade aded d0 0 = No advertised speed downgrade

13

MDI Crossover State

RO

1 = Crossover MDI mode 0 = Normal MDI mode

0

12

Interrupt Status

RO

1 = Unmasked interrupt is currently active. 0 = Interrupt is cleared.

0

11

Remote Receiver Status

RO LL

1 = Remote receiver is OK. 0 = Remote receiver is not OK since last read

0

10

Local Receiver Status

RO LL

1 = Local receiver is OK. 0 = Local receiver is not OK since last read.

0

9

Locked

RO

1 = Descrambler is locked. 0 = Descrambler Descrambler is unlocked. unlocked.

0

8

Link Status

RO

1 = Link pass 0 = Link fail

0

7

CRC Error Detected

RO LH

1 = CRC error detected. detected. 0 = No CRC error since last read.

0

6

Carr Carrie ierr Exte Extens nsio ion n Erro Error r Detected

RO LH

1 = Carrier extension error detected since last read. 0 0 = No carrier extension error since last read.

5

Bad SS SSD D Detected (False Carrier)

RO LH

1 = Bad SSD error detected since last read. 0 = No bad SSD error since last read.

0

4

Bad ES ESD D Detected (Premature End)

RO LH

1 = Bad ESD error detected since last read. 0 = No bad ESD error since last read.

0

3

Receive Error Detected

RO LH

1 = Receive error detected since last read. 0 = No receive error since last read.

0

2

Transmit Error Detected

RO LH

1 = Transmit error code received since last read. 0 0 = No transmit error error code received since last read.

1

Lock Error Detected

RO LH

1 = Lock error detected since last read. 0 = No lock error since last read.

0

0

MLT3 Code Error Detected

RO LH

1 = MLT3 code error detected since last read. 0 = No MLT3 code error since last read.

0


Page 208


BCM53128 Data Sheet


Receive Error Counter Register (Page 10h – 17h: 17h: Address 24h) Table 145: Receive Receive Error Counter Counter Register Register (Page 10h – 17h: 17h: Address 24h – 25h) 25h)a Bit

Name

R/W

Description

Default

15:0

Receive Error Counter

R/W CR

The number of noncollision packets with receive errors since last read

0000h

a.

Bits 15:0 of this register register become the 10BASE-T, 10BASE-T, 100BASE 100BASE-TX, -TX, 1000BASE 1000BASE-T -T Receive Error Counter Counter when register 38h, shadow value11011, bit 9 = 0.

Copper Receive Error Counter When bit 9 = 0 in register 38h, shadow value 11011, this counter increments increments each time BCM53128 receives receives a 10BASE-T, 100BASE-TX, 1000BASE-T noncollision packet containing at least one receive error. This counter freezes at the maximum value of FFFFh. The counter automatically clears when read.

False Carrier Sense Counter Register (Page 10h – 17h: 17h: Address 26h) Table 146: False Carrier Carrier Sense Counter Register Register (Page 10h – 17h: 17h: Address 26h – 27h) 27h)a Bit

Name

R/W

Description

Default

15:8

Reserved

RO

Ignore on read.

00h

7:0 7:0

Fals False e Carr Carrie ierr Sens Sense e Coun Counte terr R/W CR a.

The number of false carrier sense events since last 00h read.

Bits 7:0 of this register become the 10BASE-T/100BASE-TX 10BASE-T/100BASE-TX/1000BASE-T /1000BASE-T Carrier Sense Counter when register 38h, shadow 11011, bit 9 = 0 and register 3Ch, bit 14 = 0.

Copper False Carrier Sense Counter When bit 9 = 0 in register 1Ch, shadow value 11011 and bit 14 = 0 in register 3Ch, the False Carrier Sense Counter increments each time the BCM53128 detects a 10BASE-T, 100BASE-TX, 1000BASE-T false carrier sens sense e on the the rece receiv ive e input input.. This This coun counte terr free freeze zes s at the the maxim maximum um valu value e of FFh. FFh. The The coun counte terr auto automa mati tica call lly y clea clears rs when read.


Page 209


BCM53128 Data Sheet


10BASE-T/100BASE-TX/1000BASE-T Packets Received with Transmit Transm it Error Codes Coun Counter ter Table 147: 10BASE-T/100BASE-TX/1000BAS 10BASE-T/100BASE-TX/1000BASE-T E-T Transmit Error Code Counter Register (Address 13h)a Bit

Name

R/W

Description

Default

15:8

Reserved

RO


00h

7:0 7:0

Tran Transm smit it Erro Errorr Code Code Coun Counte terr R/W R/W CR a.

The number of packets received with transmit error 00h codes since last read.

Bits 7:0 of this register become the 10BASE-T/100BASE-TX 10BASE-T/100BASE-TX/1000BASE-T /1000BASE-T packets received with transmit error codes counter counter when register 38h, shadow 11011, bit 9 = 0 and register register 3Ch, bit 14 = 1.

Packets Received with Transmit Error Codes Counter The BCM53128 detects a 10BASE-T/100BASE-TX/1000BASE-T packet with a transmit error code violation when bit 9 = 0 in register 38h, shadow value 11011, and when bit 14 = 1 in register 1Eh, Packets Received with Transmit Error Codes Counter increments each time. This counter freezes at the maximum value of FFh. The counter automatically clears when read.

Receiver NOT_OK Counter Register (Page 10h – 17h: 17h: Address 28h) Table 148: Receiver NOT_OK Counter Register (Page (Page 10h – 17h: 17h: Address 28h – 29h) 29h)a Bit

Name

R/W

Description

Default

15:8 15:8

Local Local Receiv Receiver er NOT_OK NOT_OK Counter

R/W CR

The number of times local receiver was NOT_OK since last read.

00h

7:0 7:0

Remo Remote te Rece Receiv iver er NOT_ NOT_OK OK Counter

R/W CR

The number of times BCM53128 detected that the 00h remote receiver was NOT_OK since last read.

a.

Bits 15:0 of this register register become the 10BASE-T, 10BASE-T, 100BASE 100BASE-TX, -TX, or 1000BASE-T 1000BASE-T Receiver Receiver NOT_OK Counter Counter when register 38h, shadow 11011, bit 9 = 0 and register 3Ch bit 15 = 0.

Copper Local Receiver NOT_OK Counter When bit 9 = 0 in register 38h, shadow value 11011 and bit 15 = 0 in register 3Ch, this counter increments each time the 10BASE-T, 100BASE-TX, or 1000BASE-T local receiver enters the NOT_OK state. This counter freezes at the maximum value of FFh. The counter automatically clears when read.

Copper Remote Receiver NOT_OK Counter When bit 9 = 0 in register 38h, shadow value 11011 and bit 15 = 0 in register 3Ch, this counter increments each time the 1000BASE-T, 100BASE-TX, or 10BASE-T remote receiver enters the NOT_OK state. This counter freezes at the maximum value of FFh. The counter automatically clears when read.


Page 210


BCM53128 Data Sheet


Receive CRC Counter Register (Page 10h – 17h: 17h: Address 28h) Table 149: CRC Counter Counter Register Register (Page 10h – 17h: 17h: Address 28h – 29h) 29h)a Bit

Name

R/W

Description

Default

15:0

Receive CRC Counter

R/W CR

The number of times receive CRC errors were detected.

00h

a.

Bits 15:0 15:0 of this register register become the 10BASE10BASE-T, T, 100BASE-T 100BASE-TX, X, or 1000BASE-T 1000BASE-T Receive Receive CRC Counter Counter when register 38h, shadow 11011, bit 9 = 0 and register 3Ch bit 15 = 1.

Copper CRC Counter When bit 9 = 0 in register 38h, shadow value 11011 and bit 15 = 1 in register 3Ch, this counter increments each time the 10BASE-T, 100BASE-TX, or 1000BASE-T detects a receive CRC error. This counter freezes at the maximum value of FFh. The counter automatically clears when read.

Expansion Register Access Register (Page 10h – 17h: 17h: Address 2Eh) Table 150: Expansion Expansion Register Register Access Register Register (Page 10h – 17h: 17h: Address 2Eh – 2Fh) 2Fh) Bit

Name

R/W

Description

Default

15

Reserved

R/W


0

14

Reserved

R/W


0

13

Reserved

R/W


0

12

Reserved

R/W


0

11

Expa Expans nsio ion n Regi Regist ster er Sele Select ct

R/W R/W

1111 1111 = Expa Expans nsio ion n regi regist ster er is sele select cted ed.. 0000 = Expansion register is not selected.

0

10

R/W

0

9

R/W

8

R/W

7

Expa Expans nsio ion n Regi Regist ster er Acce Access ssed ed R/W R/W

6

R/W

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

0 All others = Reserved (Do not use)

0

Sets Sets the the expa expans nsio ion n regi regist ster er numb number er acce access ssed ed when read/write to register 2Ah.

0 0

Expansion Register Select Setting bits [11:8] to 1111 enables the reading from and writing to the Expansion registers in conjunction with register 2Ah. These bits should be cleared after the Expansion registers are accessed or when the Expansion registers are not being accessed. See “Expansion See “Expansion Registers” on page 229 for 229 for Expansion register detail.


Page 211


BCM53128 Data Sheet


Expansion Register Accessed The Expansion registers can be accessed through register 2Ah when bits [11:8] of this register are set to 1111. The available expansion registers are listed in Table in Table 151. 151. Table 151: Expansion Expansion Register Register Select Values Values Expans Expansion ion Regist Register er

Regist Register er Name Name

00h

“Expansion Register 01h: Expansion Interrupt Status”

Auxiliary Control Shadow Value Access Register (Page 10h – 17h: 17h: Address Addre ss 30h) Available 30h registers are listed in the Table the Table 152. 152. Table 152: Auxiliary Control Shadow Values Access Register Register (Page 10h – 17h: 17h: Address 30h) Shad Shadow ow Valu Value e

Regi Regist ster er Name Name

000

”Auxiliar ”Auxil iary y Con Contro troll Shad Shadow ow Valu Values es Acc Access ess Reg Regist ister er (Pa (Page ge 10h 10h–17 –17h: h: Add Addres ress s 30h 30h)” )” on pag page e 212

001

”10BASE-T Register (Page 10h–17h: Address 30h, Shadow Value 001)” on page 214

010

”Power/MII Control Register (Page 10h–17h: Address 30h, Shadow Value 010)” on page 215

100

”Miscellaneous Test Register (Page 10h–17h: Address 30h, Shadow Value 100)” on page 216

111

”Miscellaneous Control Register (Page 10h–17h: Address 30h, Shadow Value 111)” on page 217

Read from register 30h, shadow value zzz. Table 153: 153: Reading Reading Register Register 30h Register Reads/Writes

Description

Write register register 30h, 30h, bits bits [2:0] [2:0] = 111 111

This selects selects the miscella miscellaneous neous control control register register,, shadow shadow value value 111. 111. All reads must be done through the miscellaneous miscell aneous control register.

Bit 15 = 0

This allows only bits [14:12] and bits [2:0] to be written.

Bits [14:12] = zzz

This selects shadow value register zzz to be read.

Bits Bits [11: [11: 3] = >

When When bit bit 15 = 0, thes these e bits bits will will be igno ignore red. d.

Bits its [2:0] = 111

This sets the shadow regist ister select to 111 (miscella llaneous control register).

Read regist ister 30h

Data read back is the value from shadow regist ister zzz.

Write to register 30h, shadow value yyy.


Page 212


BCM53128 Data Sheet


Table 154: Writing Writing Register Register 30h Register Writes

Description

Set Bits [15:3] [15:3] = Preferred Preferred write values Bits [15:3] [15:3] contain contain the values to which the desired desired bits are written. written. Set Bits its [2:0] = yyy

This enables les shadow value regist ister yyy to be writt itten. For For shadow value 111, bit 15 must also be written.

Table 155: Auxiliary Control Control Register (Page (Page 10h – 17h: 17h: Address 30h, Shadow Value 000) Bit

Name

R/W

Description

Default

15

External Loopback

R/W

1 = External Loopback is enabled 0 = Normal operation

0

14

Receive Extended Packet Length

R/W

1 = Allow Allow recept reception ion of exte extende nded d lengt length h packe packets. ts. 0 0 = Allow reception of normal length Ethernet packets only.

13

R/W

12

Edge Rate Control (1000BASE-T)

00 = 4.0 ns 01 = 5.0 ns 10 = 3.0 ns 11 = 0.0 ns

11

Reserved

R/W


0

10

Reserved

R/W


1

9

Reserved

R/W


0

8

Reserved

R/W


0

7

Reserved

R/W


0

6

Reserved

R/W


0

5

R/W

00 = 4.0 ns 01 = 5.0 ns 10 = 3.0 ns 11 = 0.0 ns

0

4

Edge Rate Control (100BASE-TX)

3

Reserved

R/W

2

Shad Shadow ow Regi Regist ster er Sele Select ct R/W R/W

1

R/W

0

R/W

R/W

R/W

0 0

0

Write as 0, ignore on read

0

000 000 = Auxi Auxili liar ary y cont contro roll regi regist ster er 001 = 10BASE-T 10BASE-T register register 010 = Power/MII control register 100 = Miscellaneous test register 111 = Miscellaneous control register

0 0 0

External Loopback When bit 15 = 1, external external loopback operation operation is enabled. enabled. When the bit is cleared, cleared, normal operation operation resumes. resumes.


Page 213


BCM53128 Data Sheet


Receive Extended Packet Length When bit 14 = 1, BCM53128 can receive packets up to 9720 bytes in length when in SGMII mode. When the bit is cleared, the BCM53128 only receives packets up to standard maximum maximum size in length.

Edge Rate Control (1000BASE-T) Bits [13:12] control the edge rate of the 1000BASE-T transmit DAC output waveform.

Edge Rate Control (100BASE-TX) Bits [5:4] control the edge rate of the 100BASE-TX transmit DAC output waveform.

Shadow Register Select See See the the note note on “Au “Auxili xiliary ary Con Contro troll Sha Shadow dow Val Values ues Acc Access ess Reg Regist ister er (Pa (Page ge 10h 10h–17 –17h: h: Add Addres ress s 30h 30h)” )” on pag page e 212 describing reading from and writing to register 18h. The register set shown above is that for normal operation obtained when the lower 3 bits are 000.

10BASE-T Register Table 156: 10BASE-T 10BASE-T Register Register (Page 10h – 17h: 17h: Address 30h, Shadow Value 001) Bit

Name

R/W

Description

Default

15

Manchester Code Error

RO LH

1 = Manchester code error (10BASE-T) 0 = No Manchester code error

0

14

EOF Error

RO LH

1 = EOF error is detected detected (10BASE-T). (10BASE-T). 0 = No EOF error is detected.

0

13

Polarity Error

RO

1 = Channel polarity is inverted. 0 = Channel Channel polarity is correct. correct.

0

12

Block Block RX_D RX_DV V Exte Extens nsion ion (IPG (IPG)) R/W R/W

1 = Bloc Block k RX_D RX_DV V for for four four addi additi tion onal al RXC RXC cycl cycles es for for 0 IPG. 0 = Normal Normal operation

11

10BA 10BASE SE--T TX TXC C Inver nvertt Mode Mode

R/W R/W

1 = Inver nvertt TX TXC C outpu utputt. 0 = Normal Normal operation

0

10

Reserved

R/W


0

9

Jabber Disable

R/W

1 = Jabber function is disabled. 0 = Jabber function is enabled

0

8

Reserved

R/W


0

7

Reserved

R/W


0

6

10BASE-T Echo Mode

R/W

1 = Echo transmit data to receive data 0 = Normal Normal operation

0


Page 214


BCM53128 Data Sheet


Table 156: 10BASE-T 10BASE-T Register Register (Page 10h – 17h: 17h: Address 30h, Shadow Value 001) (Cont.) Bit

Name

R/W

Description

Default

5

SQE Enable Mode

R/W

1 = Enable SQE. 0 = Disable SQE.

0

4

10BASE-T No Dribble

R/W

1 = Correct 10BASE-T dribble nibble. 0 = Normal Normal operation

0

3

Reserved

R/W


0

2

Shadow Register Select

R/W

000 = Auxiliar iary control register 001 = 10BASE-T 10BASE-T register 010 = Power/MII control register 100 = Miscellaneous test register 111 = Miscellaneous control register

0

1

R/W

0

R/W

0 1

Power/MII Power /MII Control Register (Page 10h – 17h: 17h: Address 30h) Table 157: Power/MII Control Control Register (Page 10h – 17h: 17h: Address 30h, Shadow Value 010) Bit

Name

R/W

Description

Default

15

Reserved

R/W


0

14

Reserved

R/W


0

13

Reserved

R/W


0

12

Reserved

R/W


0

11

Reserved

R/W


0

10:7

Reserved

–

–

–

6

Reserved

R/W


1

5

Super Isolat late (Copper Only) R/W

1 = Isolat late mode with no lin link pulse lses transmitted. 0 = Normal operation

1

4

Reserved

R/W


0

3

Reserved

R/W


0

2


R/W

000 = Auxiliary control register 001 = 10BASE-T register 010 = Power/MII control register 100 = Miscellaneous test register 111 = Miscellaneous control register

0

1

R/W

0

R/W

1 0

Super Isolate (Copper Only) Setting bit 5 = 1, places the BCM53128 into the super isolate mode.


Page 215


BCM53128 Data Sheet


Shadow Register Select See See the the note note on “Au “Auxili xiliary ary Con Contro troll Sha Shadow dow Val Values ues Acc Access ess Reg Regist ister er (Pa (Page ge 10h 10h–17 –17h: h: Add Addres ress s 30h 30h)” )” on pag page e 212 describing reading from and writing to register 30h.

Miscellaneous Test Register (Page 10h – 17h: 17h: Address 30h) Table 158: Miscellane Miscellaneous ous Test Register (Page (Page 10h – 17h: 17h: Address 30h, Shadow Value 100) Bit

Name

R/W

Description

Default

15

Line-side [Remote] Loopback Enable

R/W R/W

1=E Enab nable le line-s line-side ide [remot [remote] e] loopbac loopback. k. 0 = Disable Disable loopback.

0

14

Reserved

R/W


0

13

Reserved

R/W


0

12

Reserved

R/W


0

11

Reserved

R/W


0

10

Reserved

R/W


0

9

Reserved

R/W


0

8

Reserved

R/W


0

7

Reserved

R/W


0

6

Reserved

R/W


0

5

Reserved

R/W


0

4

Swap RX MDIX

R/W

1 = RX and TX operate on same pair. 0 = Normal Normal operation

0

3

10BASE-T Halfout

R/W

1 = Transmit 10BASE-T at half amplitude. 0 = Normal Normal operation

0

2


R/W

000 = Auxilia liary control register 001 = 10BASE-T 10BASE-T register 010 = Power/MII control register 100 = Miscellaneous test register 111 = Miscellaneous control register

1

1

R/W

0

R/W

0 0


Page 216


BCM53128 Data Sheet


Miscellaneous Miscell aneous Control Register (Page 10h – 17h: 17h: Address 30h) Table 159: Miscellane Miscellaneous ous Control Register Register (Page 10h – 17h: 17h: Address 30h, Shadow Value 111) Bit

Name

R/W

Description

Default

15

Write Enable

R/W SC

1 = Write bits [14:3] 0 = Only write bits [14:12]

0

14

Shad Shadow ow Regis egistter Read Read Selector

R/W

These These bits bits are writte written n when when bit 15 is is not not set. set. This This 0 sets the shadow value for address 18h register 0 read. 0 000 = Normal operation 001 = 10BASE-T 10BASE-T register register 010 = Power control register 100 = Miscellaneous test register 111 = Miscellaneous control register

13 12

R/W R/W

11

Packet Counter Mode

R/W

1 = Receive packet counter. 0 = Transmit packet counter.

0

10

Reserved

R/W


0

9

For Force Aut Auto-M o-MDIX Mode ode

R/W

1 = Auto Auto--MDIX MDIX is enab enable led d when hen auto auto--nego negoti tiat atio ion n 0 is disabled. 0 = Auto-MDIX is disabled when auto-negotiation is disabled.

8

Reserved

R/W


0

7

Reserved

R/W


0

6

Reserved

R/W


0

5

Reserved

R/W


0

4

Ethe Ethern rnet et@W @Wir ireS eSpe peed ed Enab Enable le R/W R/W

1 = Enab Enable le Ethe Ethern rnet et@W @Wir ireS eSpe peed ed 0 = Disable Ethernet@WireSpeed

1

3

MDIO All PHY Select

R/W

1 = The PHY ports accepts MDIO writes to PHY address = 00000. 0 = Normal operation

0

2

Shadow Register Sel Select

R/W

000 = Auxili iliary control regist ister 001 = 10BASE-T 10BASE-T register register 010 = Power/MII control register 100 = Miscellaneous test register 111 = Miscellaneous control register

1

1

R/W

0

R/W

1 1


Page 217


BCM53128 Data Sheet


Auxiliary Status Summary Register (Page 10h – 17h: 17h: Address 32h) Table 160: Auxiliary Status Summary Register (Page (Page 10h – 17h: 17h: Address 32h – 33h) 33h) Bit

Name

R/W

Description

Default

15

Auto Auto-n -neg egot otia iati tion on Comp Comple lete te

RO

1 = Auto Auto-n -neg egot otia iati tion on is comp comple lete te.. 0 = Auto-negotiation Auto-negotiation is in progress. progress.

0

14

AutoAuto-ne nego goti tiat atio ion n Comp Comple lete te Acknowledge

RO LH

1 = Entered auto-negotiation link is good check state. 0 0 = State not entered since last read.

13

AutoAuto-ne nego goti tiat atio ion n Ackn Acknow owled ledge ge RO Detect LH

1 = Entered auto-negotiation acknowledge detect state. 0 = State not entered since last read

0

12

AutoAuto-ne nego goti tiat atio ion n Abil Abilit ity y Dete Detect ct RO LH

1 = Entered auto-negotiation ability detect state. 0 = State not entered since last read.

0

11

Auto Auto-n -neg egot otia iati tion on Next Next Page Page Wait

1 = Entered auto-negotiation next page wait state. 0 = State not entered since last read.

0

10

Auto Auto-n -neg egot otia iati tion on HCD HCD RO Current Operating Speed and RO Duplex Mode RO

111 = 1000BASE-T full-duplexa

0

110 = 1000BASE-T half-duplexa

0

101 = 100BASE-TX full-duplexa 100 = 100BASE-T4 100BASE-T4

0

9 8

RO LH

011 = 100BASE-TX half-duplexa 010 = 10BASE-T 10BASE-T full-duplex full-duplexa 001 = 10BASE-T 10BASE-T half-duplex half-duplexa 000 = No highest common denominator denominator or auto-negotiation is incomplete. 7

Parallel Detection Fault

RO LH

1 = Parallel link fault is detected. 0 = Parallel link fault is not detected.

0

6

Remote Fault

RO

1 = Link partner has detected a remote fault. 0 = Link partner has not detected a remote fault.

0

5

Aut Auto-ne o-neg gotia otiati tion on Page Page Received

RO LH

1 = New New page page has has been been rece receiv ived ed from from the the link link part partne ner. r. 0 0 = New page has not been received.

4

Link Link Part Partne nerr Auto Auto-n -neg egot otia iati tion on RO Ability

1 = Link Link partne partnerr has has autoauto-neg negoti otiati ation on capa capabili bility. ty. 0 = Link partner does not perform auto-negotiation.

3

Link Link Part Partne nerr Next Next Page Page Abili Ability ty RO

1 = Link Link part partne nerr has has next next page page capa capabil bilit ity. y. 0 0 = Link partner does not have next page capability.

2

Link Status

RO

1 = Link is up (link pass state). 0 = Link is down (link fail state).

0

1

Paus Pause e Resol esolut utio ion— n—R Recei eceive ve Direction

RO

1 = Enabl Enable e paus pause e rece receiv ive. e. 0 = Disable pause receive.

0

0

Paus Pause e Reso Resolu luti tion on—T —Tra rans nsmi mitt Direction

RO

1 = Enabl Enable e paus pause e tran transm smit it.. 0 = Disable pause transmit. transmit.

0

a.

0

Indicates Indicates the negotiate negotiated d HCD when Auto-neg Auto-negotiat otiation ion Enable Enable = 1, or indicates indicates the manually manually selected selected speed speed and duplex mode when Auto-negotiation Enable = 0.


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BCM53128 Data Sheet


Interrupt Status Register (Page 10h – 17h: 17h: Address 34h) Table 161: Interrupt Interrupt Status Status Register Register (Page 10h – 17h: 17h: Address 34h – 35h) 35h) Bit

Name

R/W

Description

Default

15

Energy Detect Change

RO LH

1 = Energ Energy y dete detect ct chan change ge sinc since e last last read read (ena (enabl bled ed 0 by register 1Ch, shadow 00101, bit 5 = 1). 0 = Interrupt cleared.

14

Il Illegal Pair Swap

RO LH

1 = Illegal pair swap is detected. 0 = Interrupt cleared.

0

13

MDIX Status Change

RO LH

1 = MDIX status changed since last read. 0 = Interrupt cleared.

0

12

Exceed Exceeded ed High High Counte Counterr Thresh Threshold old RO

1 = Value Value in one or more more counte counters rs is above above 32K. 32K. 0 0 = All counters below are 32K.

11

Exceed Exceeded ed Low Counte Counterr Thresh Threshold old RO

1 = Value Value in one or more more counte counters rs is above above 128K. 128K. 0 0 = All counters below are 128K.

10

Auto Auto-n -neg egot otia iati tion on Page Page Rece Receiv ived ed

RO LH

1 = Page received since last read. 0 = Interrupt cleared.

0

9

No No HCD Link

RO LH

1 = Negotiated Negotiated HCD, did not establish establish link. 0 = Interrupt cleared.

0

8

No HCD

RO LH

1 = Auto-negotiation returned HCD = none. 0 = Interrupt cleared.

0

7

Negotiated Unsupported HCD

RO LH

1 = Auto-negotiation HCD is not supported by BCM53128. 0 = Interrupt cleared.

0

6

Scra Scramb mble lerr Sync Synchr hron oniz izat atio ion n Erro Errorr

RO LH

1 = Scrambler synchronization error occurred since last read. 0 = Interrupt cleared.

0

5

Remo Remote te Rece Receiv iver er Stat Status us Chan Change ge

RO LH

1 = Remote receiver status changed since last read. 0 = Interrupt cleared.

0

4

Local Receiver Status Change

RO LH

1 = Local receiver receiver status changed since last read. 0 0 = Interrupt cleared.

3

Duplex Mode Change

RO LH

1 = Duplex mode changed since last read. 0 = Interrupt cleared.

0

2

Link Speed Change

RO LH

1 = Link speed changed since last read. 0 = Interrupt cleared.

0

1

Link Status Change

RO LH

1 = Link status changed since last read. 0 = Interrupt cleared.

0

0

Receive CRC Error

RO LH

1 = Receive Receive CRC error occurred since last read. 0 0 = Interrupt cleared.

The INTR INTR LED output output is assert asserted ed when when any bit in 10BASE 10BASE-T/ -T/100 100BASE BASE-TX -TX/10 /1000B 00BASE ASE-T -T interr interrupt upt status status regist register er is set and the corresponding bit in the 10BASE-T/100BASE-TX/1000BASE-T interrupt mask register is cleared.


Page 219


BCM53128 Data Sheet


Interrupt Mask Register (Page 10h–17h: Address 36h) Table 162: Interrupt Interrupt Mask Register Register (Page 10h–17h: Address Address 36h) Bit

Name

R/W

Description

Default

15

Signal Signal Detect Detect/En /Energ ergy y Detect Detect R/W R/W Change (enabled by register 1Ch, shadow 05h, bit 5 = 1)

1 = Inte Interr rrup uptt mask masked ed,, stat status us bits bits oper operat ate e norm normal ally ly.. 1 0 = Interr Interrupt upt enable enabled, d, status status bits bits operat operate e normal normally. ly.

14

Illegal Pair Swap

R/W

1 = Interrupt masked, status bits operate normally. 1 0 = Interrupt enabled, status bits operate normally.

13

MDIX Status Change

R/W

1 = Interrupt masked, status bits operate normally. 1 0 = Interr Interrupt upt enable enabled, d, status status bits bits operat operate e normal normally. ly.

12

Exce Exceed eded ed High High Coun Counte terr Thre Thresh shol old d R/W R/W


11

MDIX Status Change

R/W


10

Exceed Exceeded ed High High Counte Counterr Thres Threshol hold d R/W

1 = Interr Interrupt upt masked masked,, status status bits bits oper operate ate normal normally. ly. 1 0 = Interrupt enabled, status bits operate normally.

9

HCD No Link

R/W

1 = Interrupt masked, s ta tatus bits operate normally. 1 0 = Interrupt enabled, status bits operate normally.

8

No HCD

R/W

1 = In I nterrupt ma masked, st status bi b its op o perate no n ormally. 1 0 = Interrupt enabled, status bits operate normally.

7

Nego Negoti tiat ated ed Unsu Unsupp ppor orte ted d HCD HCD

R/W R/W


6

Scramb Scrambler ler Synchr Synchroni onizat zation ion Error Error

R/W

1 = Interr Interrupt upt masked masked,, status status bits bits operat operate e normal normally. ly. 1 0 = Interr Interrupt upt enable enabled, d, status status bits bits operat operate e normal normally. ly.

5

Remote Remote Receiv Receiver er Status Status Change Change

R/W

1 = Interr Interrupt upt masked masked,, status status bits bits operat operate e normal normally. ly. 1 0 = Interr Interrupt upt enable enabled, d, status status bits bits operat operate e normal normally. ly.

4

Loca Locall Rece Receiv ive e Stat Status us Chan Change ge

R/W R/W


3

Dupl Duplex ex Mode Mode Chang hange e

R/W

1 = Inter nterru rupt pt maske asked, d, stat status us bits bits oper operat ate e nor normall mally. y. 1 0 = Interr Interrupt upt enable enabled, d, status status bits bits operat operate e normal normally. ly.

2

Link ink Speed Change

R/W

1 = Interrupt masked, status bits operate normally. 1 0 = Interrupt enabled, status bits operate normally.

1

Link ink Status Change

R/W


0

CRC Error

R/W

1 = Interrupt ma m asked, st s tatus bi b its op o perate no n ormally. 1 0 = Interr Interrupt upt enable enabled, d, status status bits bits operat operate e normal normally. ly.

Interrupt Mask Vector When When bit bit n of the the Inte Interr rrup uptt Mask Mask regi regist ster er is writ writte ten n to 1, the the inte interr rrup uptt corr corres espo pond ndin ing g to the the same same bit bit in the the Inte Interr rrup uptt Status Status register is masked. masked. The status status bits still operate normally when the interrupt is masked, but do not generate an interrupt output. When this bit is written to 0, the interrupt is unmasked.


Page 220


BCM53128 Data Sheet


10BASE-T/100BASE-TX/1000BASE-T Register 38h Access Reading from and writing to 10BASE-T/100BASE-TX/1000BASE-T register 38h is though register 38h bits [15:10]. The bits [14:10] set the shadow value of register 38h, and bit 15 enables the writing of the bits [9:0]. Setting bit 15 allows writing to bits [9:0] of register 38h. Before reading register 38h shadow zzzzz, writes to register 38h should be set with bit 15 = 0, and bits [14:10] to zzzzz. The subsequent register read from register 38h contains the shadow zzzzz register value. Table value. Table 163 lists 163 lists all the register 38h shadow values. Table 163: 10BASE-T/100BASE-TX/1000BA 10BASE-T/100BASE-TX/1000BASE-T SE-T Register 38h Shadow Values Shad Shadow ow Valu Value e

Regi Regist ster er Name Name

00100

”Spare Control 2 Register (Page 10h–17h: Address 38h, Shadow Value 00100)” on page 221

00101

–

01000

–

01001

–

01010

”Auto Pow ”Auto Powerer-Dow Down n Reg Regist ister er (Pa (Page ge 10h 10h–17 –17h: h: Add Addres ress s 38h 38h,, Sha Shadow dow Val Value ue 010 01010) 10)”” on pag page e 222

01101

–

01110

”LED ”LE D Sel Select ector or 2 Reg Regist ister er (Pa (Page ge 10h 10h–17 –17h: h: Add Addres ress s 38h 38h,, Sha Shadow dow Valu Value e 011 01110) 10)”” on pag page e 223

11111

”Mode Control Register (Page 10h–17h: Address 38h, Shadow Value 11111)” on page 225

Spare Control 2 Register (Page 10h – 17h: 17h: Address 38h) Table 164: Spare Control Control 2 Register Register (Page (Page 10h – 17h: 17h: Address 38h, Shadow Value 00100) Bit

Name

R/W

Description

Default

15

Write Enable

R/W

1 = Write bits [9:0] 0 = Read bits [9:0]

0

14

Shadow Register Selector

R/W

00100 = Spare control 2 register

0

13

R/W

0

12

R/W

1

11

R/W

0

10

R/W

0

9

Reserved

R/W

Write as 0, ignore when read.

0

8

Reserved

–

–

–

7

Reserved

R/W


0

6

Reserved

R/W


0

5

Reserved

R/W


0


Page 221


BCM53128 Data Sheet


Table 164: Spare Control Control 2 Register Register (Page (Page 10h – 17h: 17h: Address Address 38h, Shadow Value Value 00100) (Cont.) (Cont.) Bit

Name

R/W

Description

4

Ethernet@WireSpeed Retry Limit

RO

000 = Downgrade Downgrade after 2 failed auto-negoti auto-negotiation ation attempts. attempts. 0 001 = Downgrade after 3 failed auto-negotiation attempts. 1 010 = Downgrade after 4 failed auto-negotiation attempts. 1 011 = Downgrade after 5 failed auto-negotiation attempts. 100 = Downgrade after 6 failed auto-negotiation attempts. 101 = Downgrade after 7 failed auto-negotiation attempts. 110 = Downgrade after 8 failed auto-negotiation attempts. 111 = Downgrade after 9 failed auto-negotiation attempts.

3 2

Default

1

Energy Detect on INTR R/W LED Pin

1 = Route Routes s energy energy dete detect ct to to interr interrupt upt sign signal. al. Use Use LED LED selectors (register 38h shadow 01101 and 01110) and program to INTR mode. 0 = INTR LED pin performs the Interrupt function.

0

0

Reserved


0

R/W

Auto Power-Down Register (Page 10h – 17h: 17h: Address 38h) Table 165: Auto Power-Do Power-Down wn Register Register (Page 10h – 17h: 17h: Address 38h, Shadow Value 01010) Bit

Name

R/W

Description

Default

15

Write Enable

R/W


0

14


R/W

01010 = Auto power-down register

0

13

R/W

1

12

R/W

0

11

R/W

1

10

R/W

0

9

Reserved

R/W


0

8

Reserved

R/W


0

7

Reserved

R/W


0

6

Reserved

R/W


0

5

Aut Auto Pow Power-D er-Dow own n Mode ode

R/W

1 = Auto Auto powe powerr-dow -down n mode mode is enab enable led. d. 0 = Auto power-down mode is disabled.

0

4

Sleep Timer Select

R/W

1 = Sleep timer is 5.4 seconds. 0 = Sleep timer is 2.7 seconds.

0

3

Wakeake-up up Time Timerr Sele Select ct

R/W

Coun Countter for wake wake-u -up p time timerr in unit nits of 84 ms 0001 = 84 ms 0010 = 168 ms ... 1111 = 1.26 sec.

0

2

R/W

1

R/W

0

R/W

0 0 1


Page 222


BCM53128 Data Sheet


LED Selector 2 Register (Page 10h – 17h: 17h: Address 38h) Table 166: 166: LED Selector Selector 2 Register Register (Page 10h – 17h: 17h: Address 38h, Shadow Value 01110) Bit

Name

R/W

Description

Default

15

Write Enable

R/W


0

14


R/ R/W

01110 = LED status register

0

13

R/W

1

12

R/W

1

11

R/W

1

10

R/W

0

9

Reserved

R/W


0

8

Reserved

R/W


0

7

LED4 Selector

R/W

0000 = LINKSPD[1] 0001 = LINKSPD[2] 0010 = XMITLED XMITLED 0011 = ACTIVITY 0100 = FDXLED 0101 = SLAVE 0110 = INTR 0111 = QUALITY 1000 = RCVLED RCVLED 1001 = WIRESPD_DOWNGRADE 1010 = MULTICOLOR[2] 1011 = CABLE DIAGNOSTIC OPEN/SHORT 1100 = RESERVED RESERVED 1101 = CRS (SGMII mode) 1110 = Off (high) 1111 = On (low)

0

6

R/W

5

R/W

4

R/W

1 1 0


Page 223


BCM53128 Data Sheet


Table 166: LED Selector Selector 2 Register Register (Page 10h – 17h: 17h: Address 38h, Shadow Value 01110) (Cont.) Bit

Name

R/W

Description

Default

3

LED3 Selector

R/W

0000 = LINKSPD[1] 0001 = LINKSPD[2] 0010 = XMITLED XMITLED 0011 = ACTIVITY 0100 = FDXLED 0101 = SLAVE 0110 = INTR 0111 = QUALITY 1000 = RCVLED RCVLED 1001 = WIRESPD_DOWNGRADE 1010 = MULTICOLOR[1] 1011 = CABLE DIAGNOSTIC OPEN/SHORT 1100 = RESERVED RESERVED 1101 = CRS (SGMII mode) 1110 = Off (high) 1111 = On (low)

0

2

R/W

1

R/W

0

R/W

0 1 1


Page 224


BCM53128 Data Sheet


Mode Control Register (Page 10h – 17h: 17h: Address 38h) Table 167: Mode Control Control Register Register (Page 10h – 17h: 17h: Address 38h, Shadow Value 11111) Bit

Name

R/W

Description

Default

15

Write Enable

R/W


0

14


R/ R/W

11 1 1111 = LED status register

1

13

R/W

1

12

R/W

1

11

R/W

1

10

R/W

1

9

Reserved

RO

Ignore on read.

0

8

Reserved

–

–

–

7

Copper Link

RO

1 = Link is good on the copper interface. 0 = Copper link is down.

0

6

Reserved

–

–

–

5

Coppe opperr Ener Energy gy Det Detect ect

RO

1 = Ener Energy gy det detect ected on the the copp copper er inte interrface face.. 0 = Energy not detected on the copper interface.

0

4

Reserved

RO

Ignore on read.

0

3

Reserved

RO

Ignore on read.

1

2

Mode Select

R/W

00 = GMII 01 = Reserved Reserved 10 = Reserved Reserved 11 = Reserved Reserved

0

–

–

1

0

Reserved

–

0


Page 225


BCM53128 Data Sheet


Master/Slave Seed Register (Page 10h – 17h: 17h: Address 3Ah) Table 168: Master/Sl Master/Slave ave Seed Register Register (Page 10h – 17h: 17h: Address 3Ah – 3Bh) 3Bh) Bit 15 = 0 Bit

Name

R/W

Description

15

Enab Enable le Shad Shadow ow Regis egiste terr

R/W

1 = Sele Select ct shad shadow ow regis egiste terr. 0 0 = Normal Normal operation Writ Writes es to the the selec selecte ted d regi regist ster er are are done done on a sing single le cycle.

14

Master/Slave Seed Match

RO LH

1 = Seeds match. 0 = Seeds do not match.

0

13

Link Link Part Partne nerr Repe Repeat ater er/D /DTE TE Bit Bit RO

1 = Link Link part partne nerr is a repe repeat ater er/s /swi witc tch h devi device ce.. 0 = Link partner is a DTE device.

0

12

Link Link Part Partne nerr Manu Manual al Mast Master er// Slave Configuration Value

RO

1 = Link Link partne partnerr is config configure ured d as master master.. 0 = Link partner is configured as slave.

0

11

Link Link Part Partne nerr Manu Manual al Mast Master er// Slave Configuration Enable

RO

1 = Link Link part partne nerr manu manual al mast master er/s /slav lave e conf configu igura rati tion on 0 is enabled. 0 = Link Link partne partnerr manual manual master master/sl /slave ave config configura uratio tion n is disabled.

10

Loca Locall Mast Master er/S /Sla lave ve Seed Seed Value

R/W R/W

Returns Returns the automatica automatically lly generated generated master/sla master/slave ve 0 random seed. 0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

0

R/W

0

9

Default


Page 226


BCM53128 Data Sheet


HCD Status Register (Page 10h – 17h: 17h: Address 3Ah) Table 169: HCD Status Status Register Register (Page (Page 10h – 17h: 17h: Address 3Ah – 3Bh) 3Bh) Bit 15 = 1 Bit

Name

15

R/W

Description

Default

Enab Enable le Shad Shadow ow Regi Regist ster er R/W R/W

1 = Selec Selectt Shad Shadow ow regi regist ster er.. 0 = Normal operation

0

14

Ethe Ethern rnet et@W @Wir ireS eSpe peed ed Disable Gigabit Advertising

RO

1 = Disa Disabl ble e adve advert rtisi ising ng gigab gigabit it.. 0 = Advertise gigabit based on register 09h.

0

13

Ethe Ethern rnet et@W @Wir ireS eSpe peed ed Disable 100TX Advertising

RO

1 = Disa Disabl ble e adve advert rtisi ising ng 100T 100TX. X. 0 = Advertise 100TX based on register 04h.

0

12

Ethe Ethern rnet et@W @Wir ireS eSpe peed ed Downgrade

RO LH

1 = Ethernet@WireSpeed downgrade occurred since last read. 0 = Ethernet@WireSpeed downgrade cleared.

0

11

HCD HCD 1000 1000BA BASE SE-T -T Full-Duplex

RO LH

1 = Gigabit full-duplex full-duplex occurred occurred since last read. 0 = HCD cleared.

0

10

HCD HCD 1000 1000BA BASE SE-T -T Half-Duplex

RO LH

1 = Gigabit half-duplex half-duplex occurred since last read. 0 = HCD cleared.

0

9

HCD 100BASE SE--TX Full-Duplex

RO LH

1 = 100BASE-TX full-duplex full-duplex occurred since last read. 0 = HCD cleared.

0

8

HCD 100BASE SE--T Half-Duplex

RO LH

1 = 100BASE-TX 100BASE-TX half-duplex half-duplex occurred occurred since last read. 0 = HCD cleared.

0

7

HCD 10BASE-T Full-Duplex

RO LH

1 = 10BASE-T full-duplex full-duplex occurred since last read 0 = HCD cleared.

0

6

HCD 10BASE-T Half-Duplex

RO LH

1 = 10BASE-T half-duplex half-duplex occurred since last read. 0 = HCD cleared.

0

5

HCD 1000BASE SE--T Full-Duplex (Link Never Came Up)

RO LH

1 = Gigabit full-duplex HCD and link and link never came up occurred up occurred 0 since the last read. 0 = HCD cleared.

4

HCD 1000BASE SE--T Half-Duplex (Link Never Came Up)

RO LH

1 = Giga Gigabi bitt half half-d -dup uplex lex HCD HCD and and link link neve neverr came came up occurred 0 since the last read. 0 = HCD cleared.

3

HCD 100BASE SE--TX Full-Duplex (Link Never Came Up)

RO LH

1 = 100BASE-TX full-duplex full-duplex HCD and link and link never came up occurred since the last read. 0 = HCD cleared.

0

2

HCD 100BASE SE--T Half-Duplex (Link Never Came Up)

RO LH

1 = 100BASE-TX half-duplex half-duplex HCD and link and link never came up occurred since the last read. 0 = HCD cleared.

0

1

HCD 10BASE-T Full-Duplex (Link Never Came Up)

RO LH

1 = 10BASE-T full-duplex full-duplex HCD and link and link never came up occurred since the last read. 0 = HCD cleared.

0


Page 227


BCM53128 Data Sheet


Table 169: HCD Status Status Register Register (Page 10h – 17h: 17h: Address 3Ah – 3Bh) 3Bh) Bit Bit 15 = 1 (Cont.) (Cont.) Bit

Name

R/W

Description

Default

0

HCD 10BASE-T Half-Duplex (Link Never Came Up)

RO LH

1 = 10BASE-T half-duplex half-duplex HCD and link and link never came up occurred since the last read. 0 = HCD cleared.

0

Note: Bits Note: Bits [12:0] are also cleared when auto-negotiation is disabled via MII register 00h, bit 12 = 1, or restarted via MII register 00h, bit 9 = 1.

Test Register 1 (Page 10h – 17h: 17h: Address 3Ch) Table 170: 170: Test Register Register 1 (Page (Page 10h – 17h: 17h: Address 3C – 3Dh) 3Dh) Bit

Name

R/W Description

15

CRC CRC Erro Errorr Coun Counte ter r R/W R/W 1 = Rece Receive iverr NOT_ NOT_OK OK coun counte ters rs (reg (regis iste terr 14h) 14h) beco become mes s 16 bitCRC 0 Selector error counter (CRC errors are counted only after this bit is set). 0 = Normal operation

14

Tran Transm smit it Erro Errorr Code Code R/W 1 = False carrier carrier sense sense counters counters (register (register 13h) 13h) counts counts packets packets Visibility received with transmit error codes. 0 = Normal operation

0

13

Reserved

0

12

Force Link R/W 1 = Force Force link state state machine machine into into link pass pass state. state. 10/100/1000BASE-T 0 = Normal operation

0

11

Reserved

R/W Write as 0, ignore when read.

0

10

Reserved


0

9

Reserved


0

8

Reserved


0

7

Manual Swap MDI State

R/W 1 = Manua Manually lly swap swap MDI MDI stat state. e. 0 0 = Normal operation Note: To chan change ge the the MDI MDI stat state e when when in forc forced ed 100B 100BASE ASE-T -TX X mode mode,, the PHY must first be put into a nonlink condition, then set bit 7 = 1 and finally set the PHY into force 100BASE-TX 100BASE-TX mode.

6

Reserved


0

5

Reserved


0

4

Reserved


0

3

Reserved


0

2

Reserved


0

1

Reserved


0

0

Reserved


0


Default

Note: Preamble Note: Preamble is still required on the first read or write. Preamble suppression cannot be disabled.


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BCM53128 Data Sheet

Expansion Registers

Expansion Registers Expansion Expan sion Register 00h: Receive/ Receive/Transm Transmit it Packet Counter Expansion register 00h is enabled by writing to “Expansion to “Expansion Register Access Register (Page 10h–17h: Address 2Eh–2Fh)” bits 2Eh–2Fh)” bits [11:0] = ‘F00’h, and read/write access is through register 2Ah. Table 171: Expansion Register 00h: Receive/Transmit Receive/Transmit Packet Counter Counter Bit

Name

R/W

Description

Default

15:0 15:0

Pack Packet et Coun Counte ter r (Copper Only)

R/W CR

Return Returns s the transm transmitt itted ed and receiv received ed packet packet count. count. 0000h 0000h

Packet Counter (Copper Only) The mode of this counter is set by bit 11 of “Miscellaneous of “Miscellaneous Control Register (Page 10h–17h: Address 30h, Shadow Sha dow Valu Value e 111 111)” )”.. When When bit bit 11 =1, =1, then then rece receiv ive e pack packet ets s (bot (both h good good and and bad bad CRC CRC erro errorr pack packet ets) s) are are coun counte ted. d. When bit 11 = 0, then transmit packets (both good and bad CRC error packets) are counted. This counter is cleared on read and freezes at FFFFh.

Expansion Expan sion Register 01h: Expansi Expansion on Interr Interrupt upt Status Expansion register 00h is enabled by writing to “Expansion to “Expansion Register Access Register (Page 10h–17h: Address 2Eh–2Fh)” bits 2Eh–2Fh)” bits [11:0] = ‘F01’h, and read/write access is through register 2Ah. Table 172: Expansion Register 01h: Expansion Expansion Interrupt Status Status Bit

Name

R/W

Description

Default

15:1

Reserved

RO


0

0

Transmit CRC Error

RO LH

1 = Transmit CRC error detected since last read. 0 = No transmit CRC error detected.

0

Transmit CRC Error This bit indicates indicates that a transmit transmit CRC error has been detected detected since the last read.


Page 229


BCM53128 Data Sheet

Page 20h–28h: Port MIB Registers

Expansion Expan sion Register 45h: Transmi Transmitt CRC Enable Expansion register 00h is enabled by writing to “Expansion to “Expansion Register Access Register (Page 10h–17h: Address 2Eh–2Fh)” bits 2Eh–2Fh)” bits [11:0] = ‘F45’h, and read/write access is through register 2Ah. Table 173: Expansion Expansion Register Register 45h: Transmit CRC Bit

Name

R/W

Description

Default

15:13

Reserved

R/W


000

12

Transmit CRC enable

R/W

1 = Enable transmit CRC checker. 0 0 = Disable transmit CRC checker. Register 18h, shadow value 100, bit 15 must be set to a 1.

11:0

Reserved

R/W


0

Transmit CRC Checker When register 30h, Shadow Value 100, bit 15 = 1 and Expansion Register 45h, bit 12 = 1, the transmit CRC checker checker is enabled. enabled. When a transmit transmit CRC error occurs, Expansion Expansion Register Register 01h, bit 0 = 1.

Page 20h–28h: Port MIB Registers Table 174: Port MIB Register Registers s Page Summary Page

Description

20h

Port 0

21h

Port 1

22h

Port 2

23h

Port 3

24h

Port 4

25h

Port 5

26h

Port 6

27h

Port 7

28h

IMP port

Table 175: Page 20h–28h 20h–28h Port MIB Registers Registers ADDR

Bits

Name

Description

00h–07h

64

TxOctets

The total number of good bytes of data transmitted by a port (excluding preamble, but including FCS).


Page 230


BCM53128 Data Sheet


Table 175: Page 20h–28h 20h–28h Port MIB Registers Registers (Cont.) (Cont.) ADDR

Bits

Name

Description

08h–0Bh

32

TxDropPkts

This counter is incremented every time a transmit packet is dropped due to lack of resources (e.g., transmit FIFO underflow), or an internal MAC sublayer transmit error not counted by either the TxLateCollision or the TxExcessiveCollision counters.

0Ch–0Fh

32

TxQ0PKT

The total number of good packets transmitted on COS0, which is spec specif ifie ied d in MIB MIB queu queue e sele select ct regi regist ster er when when QoS QoS is enab enable led. d.

10h– 10h–13 13h h

32

TxBr TxBroa oadc dcas astP tPkt kts s

The The num number ber of good good pack packet ets s trans ransm mitt itted by a por port that that are are direct directed ed to a broadc broadcast ast addres address. s. This counte counterr does does not includ include e errored broadcast packets or valid multicast packets.

14h– 14h–17 17h h

32

TxM TxMult ulticas icastP tPkt kts s

The The num number ber of good good pack packet ets s trans ransm mitt itted by a por port that that are are directed to a multicast address. This counter does not include errored multicast packets or valid broadcast packets.

18h– 18h–1B 1Bh h

32

TxU TxUnica nicast stPk Pktts

The The num number ber of good good pack packet ets s trans ransm mitt itted by a por port that that are are addressed to a unicast address.

1Ch– 1Ch–1F 1Fh h

32

TxC TxColli ollisi sion ons s

The The num number ber of coll collis isio ions ns exp experie erienc nced ed by a port port duri during ng pac packet ket transmissions.

20h– 20h–23 23h h

32

TxSi TxSing ngle leCo Coll llis isio ion n

The The numb number er of pack packet ets s succ succes essf sful ully ly tran transm smit itte ted d by a port port that that experienced exactly one collision.

24h– 24h–27 27h h

32

TxMu TxMult ltip iple le Colli Collisi sion on

The The numb number er of pack packet ets s succ succes essf sful ully ly tran transm smit itte ted d by a port port that that experienced more than one collision.

28h– 28h–2B 2Bh h

32

TxD TxDefer eferre redT dTrransm ansmit it

The The num number ber of pac packets kets trans ransm mitt itted by a port port for which hich the firs firstt transmission attempt is delayed because the medium is busy.


32

TxLa TxLate teCo Coll llis isio ion n

The The numb number er of time times s that that a coll collis isio ion n is dete detect cted ed late laterr than than 512 512 bit-times into the transmission of a packet.

30h– 30h–33 33h h

32

TxEx TxExce cess ssive iveCo Coll llisi ision on

The The numb number er of pack packet ets s that that are are not not tran transm smit itte ted d from from a port port because the packet experienced 16 transmission attempts.

34h– 34h–37 37h h

32

TxFr TxFram ameI eInD nDis isc c

The The num number ber of vali valid d pack packet ets s recei eceive ved d that that are are disc discar arde ded d by the forwarding process due to lack of space on an output queue. (Not maintained or reported in the MIB counters and located in the congestion management registers [Page 0Ah].) This attribute only increments if a network device is not acting in compliance with a flow-control request, or the BCM53128 internal flow control/buffering scheme has been misconfigured.

38h–3Bh

32

TxPausePkts

The number of PAUSE events on a given port.

3Ch–3Fh

32

TxQ1PKT

The total number of good packets transmitted on COS1, which isspecifiedin isspecifiedin MIBqueue MIBqueue selectregi selectregiste sterr when when QoSis enabled enabled..

40h–43h

32

TxQ2PKT


44h–47h

32

TxQ3PKT


48h–4Bh

32

TxQ4PKT


4Ch–4Fh

32

TxQ5PKT



Page 231


BCM53128 Data Sheet



Bits

Name

Description

50h–57h

64

RxOctets

The number of bytes of data received by a port (excluding preamble, but including FCS), including bad packets.

58h– 58h–5B 5Bh h

32

RxUn RxUnde ders rsiz izeP ePkt kts s

The The numb number er of good good pack packet ets s rece receiv ived ed by a port port that that are are less less than 64 bytes long (excluding (excluding framing bits, but including including the FCS).

5Ch–5Fh

32

RxPausePkts

The number of PAUSE frames received by a port. The PAUSE frame must have a valid MAC control frame EtherType field (88–08h), have a destination MAC address of either the MAC control frame reserved multicast address (01-80-C2-00-0001) or the unique MAC address address associated associated with the specific specific port, a valid PAUSE Opcode (00–01), be a minimum of 64 bytes in length (excluding (excluding preamble but including including FCS), and have a valid CRC. Although an IEEE 802.3-compliant MAC is only permitted to transmit PAUSE frames when in full-duplex mode with flow control enabled and with the transfer of PAUSE frames determined by the result of auto-negotiation, an IEEE 802.3 MAC receiver is required to count all received PAUSE frames, regardless of its half/full-duplex status. An indication indication that a MAC is in half-duplex half-duplex with the RxPausePkts RxPausePkts incrementing indicates a noncompliant transmitting device on the network.

60h– 60h–63 63h h

32

Pkts Pkts64 64Oc Octe tetts

The The num number ber of pack packet ets s (incl includ udin ing g err error pack packet ets) s) that that are are 64 bytes long.

64h– 64h–67 67h h

32

Pkts Pkts65 65to to12 127O 7Oct ctet ets s

The The numb number er of pack packet ets s (inc (inclu ludi ding ng erro errorr pack packet ets) s) that that are are between 65 and 127 bytes long.

68h– 68h–6B 6Bh h

32

Pkts Pkts12 128t 8to2 o255 55Oc Octe tets ts

The The numb number er of pack packet ets s (inc (includ ludin ing g erro errorr pack packet ets) s) that that are are between 128 and 255 bytes long.


32

Pkts Pkts25 256t 6to5 o511 11Oc Octe tets ts

The The numb number er of pack packet ets s (inc (includ ludin ing g erro errorr pack packet ets) s) that that are are between 256 and 511 bytes long.

70h– 70h–73 73h h

32

Pkts Pkts51 512t 2to1 o102 023O 3Oct ctet ets s The The numb number er of pack packet ets s (inc (includ ludin ing g erro errorr pack packet ets) s) that that are are between between 512 and 1023 bytes long.

74h–77h

32

Pkts1024toMaxPktOct The number of packets (including error packets) that are ets between 1024 and MaxPacket bytes long.

78h– 78h–7B 7Bh h

32

RxO xOve vers rsiz izeP ePkt kts s

The The num number ber of good good pack packet ets s recei eceiv ved by a por port that that are are greater than standard max frame size.

7Ch–7Fh

32

RxJabbers

The number of packets received by a port that are longer than 1522 bytes and have either an FCS error or an alignment error.

80h– 80h–83 83h h

32

RxAl RxAlig ignm nmen entE tErr rror ors s

The The numb number er of pack packet ets s rece receiv ived ed by a port port that that have have a leng length th (excluding framing bits, but including FCS) between 64 and standard max frame size, inclusive, and have a bad FCS with a nonintegral number of bytes.

84h–87h

32

RxFCSErr Errors

The number of packets received by a port that have a length (excluding framing bits, but including FCS) between 64 and standard max frame size, inclusive, and have a bad FCS with an integral number of bytes.

88h– 88h–8F 8Fh h

64

RxG xGoo oodO dOct ctet ets s

The The total otal num number ber of byt bytes in all all good good pack packet ets s rece receiv ived ed by a port (excluding framing bits but including FCS).


Page 232


BCM53128 Data Sheet



Bits

Name

Description

90h–93h

32

RxDropPkts

The number of good packets receive ived by a port that were drop droppe ped d due due to lack lack of reso resour urce ces s (e.g (e.g., ., lack lack of input input buff buffer ers) s) or were dropped due to lack of resources before a determination of the validity of the packet was able to be made (e.g., receive FIFO FIFO over overfl flow ow). ). The The coun counte terr is only only incr increm emen ente ted d if the the rece receiv ive e error was not counted by the RxAlignmentErrors or the RxFCSErrors counters.

94h–97h

32

RxUnica icastPkts

The number of good packets receive ived by a port that are addressed to a unicast address.

98h– 98h–9B 9Bh h

32

RxMul xMultticas icastP tPkt kts s

The The num number ber of good good pack packet ets s recei eceiv ved by a por port that that are are directed to a multicast address. This counter does not include errored multicast packets or valid broadcast packets.


32

RxBro xBroad adca cas stPkt tPkts s

The The num number ber of good good pack packet ets s recei eceiv ved by a por port that that are are directed to the broadcast address. This counter does not include errored broadcast packets or valid multicast packets.

A0h–A3h

32

RxSAChanges

The number of times the SA of good receive packets has changed changed from the previous value. A count greater greater than 1 generally indicates the port is connected to a repeater-based network.

A4h–A7h

32

RxFragments

The number of packets received by a port that are less than 64 byte bytes s (exc (exclu ludin ding g fram framing ing bits bits)) and and have have eith either er an FCS FCS erro errorr or an alignment error.

A8h–ABh

32

JumboPkt

The number of frames received with frame size greater than the Standard Maximum Size and less than or equal to the Jumbo Frame Size, regardless of CRC or Alignment errors. Note: InFrame Note: InFrame count should count "the JumboPkt count with good CRC."

ACh–AFh

32

RXSymbolError

The total number of times a valid length packet was received at a port and at least one invalid data symbol was detected. Counter only increments once per carrier event and does not increment on detection of collision during the carrier event.

B0h–B3h

32

InRangeErrors

The number of frames received with good CRC and the following conditions. The value of Length/Type field is between 46 and 1500 inclu inclusi sive ve,, and and does does not not matc match h the the numb number er or (MAC (MAC Clie Client nt Data Data + PAD) data octets received, OR The The valu value e of Leng Length th/T /Typ ype e field field is less less than than 46, 46, and and the the numb number er of data octets received is greater than 46 (which does not require padding).

B4h– B4h–B7 B7h h

32

OutO OutOfR fRan ange geEr Erro rors rs

The The numb number er of fram frames es rece receiv ived ed with with good good CRC CRC and and the the valu value e of Length/Type field is greater than 1500 and less than 1536.

B8h-BBh

32

EEE Low-Power Idle Event

In asymmetric mode, this is simply a count of the number of times that the lowPowerAssert control signal has been asserted asserted for each MAC. In symmetric symmetric mode, this is the count of the number of times both lowPowerAssert and the lowPowerIndicate (from the receive path) are asserted simultaneously.


Page 233


BCM53128 Data Sheet



Bits

Name

Description

BCh-BFh

32

EEE Low-Power Duration

This counter accumulates the number of microseconds that the associated associated MAC/PHY is in the low-power low-power idle state. The unit is 1 used.

C0h–C3h

32

RxDiscard

The number of good packets received by a port that were discarded by the Forwarding Process.

F0h–F7h

64

“SPI Data I/O Register – (Global, (Glob al, Addres Address s F0h)” on page 295, 295, bytes 0– 7

F8h–FDh

–

Reserved

FEh

8

“SPI Status Register – (Global, (Glob al, Addre Address ss FEh)” on page 295

FFh

8

“Page Register – (Global, (Glob al, Addres Address s FFh)” on page 296

–


Page 234


BCM53128 Data Sheet

Page 30h: QoS Registers

Page 30h: QoS Registers Table 176: 176: Page 30h QoS QoS Registers Registers Address

Bits

Description

00h

8

“QoS Global Contr Control ol Regis Register ter (Page 30h: Addre Address ss 00h)” on page 236

01h–02h

16

Reserved

03h

–

Reserved

04h–05h

16

“QoS IEEE 802.1p Enable Register (Page 30h: Address 04h)” on page 236

06h–07h

16

“QoS DiffServ Enable Register (Page 30h: Address 06h)” on page 237

08h–0Fh

–

Reserved

10h–33h

32/port

“Port N (N = 0-7, 8) PCP_To PCP_To_TC _TC Regist Register er (Page 30h: Addres Address s 10h)” on page 237

34h–3Fh

–

Reserved

40h–45h

48

“DiffServ Priority Map 0 Register (Page 30h: Address 40h)” on page 238

46h–4Bh

48


4Ch–51h

48

“DiffServ Priority Map 2 Register (Page 30h: Address 4Ch)” on page 239

52h–57h

48


48h–61h

–

Reserved

62h–63h

16

“TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” on page 241

64h–67h

32

“CPU_To_COS Map Register (Page 30h: Address 64h–67h)” on page 242

68h–7Fh

–

Reserved

80h

8

“TX Queue Contr Control ol Regis Register ter (Page 30h: Addre Address ss 80h)” on page 243

81h

8

“TX Queue Weight Register (Page 30h: Address 81h)” on page 243 243,, Queue 0

82h

8


83h

8


84h

8


85h–86h

16

“COS4 Service Weight Register (Page 30h: Address 85h–86h)” on page 244

875h–9Fh

–

Reserved

A0h

–

Reserved

A1h

–

Reserved

A2h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8



Page 235


BCM53128 Data Sheet


QoS Global Control Register (Page 30h: Address 00h) Table 177: QoS Global Control Control Register Register (Page 30h: Address 00h) Bit

Name

R/W

Description

Default

7

Aggr Aggreg egat atio ion n Mode Mode

R/W R/W

When When enab enable le this this bit, bit, the the IMP IMP oper operat ated ed as the the upli uplink nk port port to 0 the upstream network processor and the COS is decided from the TC based on the normal packet classification flow. Otherwise, the IMP operated as the interface to the management CPU, and the COS is decided based on the reasons for forwarding the packet to the CPU.

6

PORT_QOS_EN

R/W

Port-based QoS enable 0 When port-based QoS is enabled, ingress frames are assigned a priority ID value based on the PORT_QOS_PRI bits in the “Default the “Default IEEE 802.1Q Tag Register (Page 34h: Address 10h)” on page 255 255.. IEEE 802.1p 802.1p and DiffServ DiffServ priorities are disregarded. 0 = Disable port-based port-based QoS. 1 = Enable port-based QoS. See “Quality See “Quality of Service” on page 34 for 34 for more information.

5:4

Reserved

R/W

Reserved

3:2 3:2

QOS_LA S_LAYE YER R_SEL _SEL

R/W

QoS QoS prio priori rity ty sele select ctio ion n 0 These bits determine which QoS priority scheme is associated with the frame. See Table See Table 1 on page 36 for 36 for more information.

1:0

Reserved

R/W

Reserved

0

0

QoS IEEE 802.1p Enable Register (Page 30h: Address 04h) Table 178: QoS.1P QoS.1P Enable Register Register (Page 30h: Address 04h–05h) 04h–05h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

802_1P_EN

R/W

QoS IEEE 802.1p port mask 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Disable IEEE 802.1p priority for individual ports. 1 = Enable IEEE 802.1p priority priority for individual individual ports. ports. See “IEEE See “IEEE 802.1Q VLAN” on page 39 for 39 for more information.


Page 236


BCM53128 Data Sheet


QoS DiffServ Enable Register (Page 30h: Address 06h) Table 179: QoS DiffServ Enable Register (Page (Page 30h: Address 06h–07h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

DIFFSERV_EN

R/W

DiffServ port mask Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Disable DiffServ priority for individual ports. 1 = Enable DiffServ priority for individual ports.

0

See “Quality See “Quality of Service” on page 34 for 34 for more information.

Port N (N = 0-7, 8) PCP_To_TC Register (Page 30h: Address 10h) .

Table 180: Port N (N=0-7,8) PCP_To_TC Register Register Address Summary Address

Description

10h–13h

Port 0

14h–17h

Port 1

18h–1Bh

Port 2

1Ch–1Fh

Port 3

20h–23h

Port 4

24h–27h

Port 5

28h–2Bh

Port 6

2Ch–2Fh

Port 7

30h–33h

IMP Port

These bits map the IEEE 802.1p priority level to one of the eight priority ID levels in the “TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” on page 241. 241. Table 181: Port N (N=0-7,8) (N=0-7,8) PCP_To_TC Register Register (Page 30h: Address Address 10h–33h) BIt

Name

R/W

Description

Default

31:24

Reserved

RO

Reserved

0

23:21

1P_111_MAP

R/W

IEEE 802.1p priority tag field 111

111

20:18

1P_110_MAP

R/W


110

17:15

1P_101_MAP

R/W


101

14:12

1P_100_MAP

R/W


100

11:9

1P_011_MAP

R/W


011

8:6

1P_010_MAP

R/W


010

5:3

1P_001_MAP

R/W


001

2:0

1P_000_MAP

R/W


000


Page 237


BCM53128 Data Sheet



DiffServ Priority Map 0 Register (Page 30h: Address 40h) These bits map the DiffServ priority level to one of the eight Priority ID levels in the “TC_To_COS the “TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” on page 241. 241. Table 182: DiffServ DiffServ Priority Priority Map 0 Register Register (Page 30h: Address 40h–45h) 40h–45h) Bit

Name

47:45

R/W

Description

Default

DIFFSERV_ 001111_MAP R/W

DiffSer Serv DSCP priority tag field 001111

0

44:42



0

41:39



0

38:36



0

35:33



0

32:30



0

29:27



0

26:24



0

23:21



0

20:18



0

17:15



0

14:12



0

11:9


DiffServ DSCP priority tag field 000011

0

8:6



0

5:3



0

2:0



0



Page 238


BCM53128 Data Sheet


DiffServ Priority Map 1 Register (Page 30h: Address 46h) These bits map the DiffServ priority level to one of the eight Priority ID levels in the “TC_To_COS the “TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” on page 241. 241. Table 183: DiffServ Priority Priority Map 1 Register (Page 30h: Address 46h–4Bh) Bit

Name

47:45

R/W

Description

Default

DIFFSERV_ 011111_MAP R/W R/W

DiffServ DSCP priority tag fiel ield 011111

0

44:42



0

41:39



0

38:36



0

35:33



0

32:30



0

29:27



0

26:24



0

23:21



0

20:18



0

17:15



0

14:12



0

11:9

DIFFSERV_ 010011_MAP R/ R/W


0

8:6



0

5:3



0

2:0



0


DiffServ Priority Map 2 Register (Page 30h: Address 4Ch) These bits map the DiffServ priority level to one of the eight priority ID levels in the “TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” on page 241. 241. Table 184: DiffServ DiffServ Priority Priority Map 2 Register Register (Page 30h: Address Address 4Ch–51h) Bit

Name

R/W

Description

Default

47:45

DIFFSERV_ 101111_MAP

R/W

Diff iffServ DSCP prior iority ity tag field 101111

0

44:42


R/W


0

41:39


R/W


0

38:36


R/W


0

35:33


R/W


0

32:30


R/W


0

29:27


R/W


0

26:24


R/W


0

23:21


R/W


0


Page 239


BCM53128 Data Sheet


Table 184: DiffServ Priority Priority Map 2 Register (Page 30h: Address 4Ch–51h) (Cont.) Bit

Name

R/W

Description

Default

20:18


R/W


0

17:15


R/W


0

14:12


R/W


0

11:9


R/W


0

8:6


R/W


0

5:3


R/W


0

2:0


R/W


0


DiffServ Priority Map 3 Register (Page 30h: Address 52h) These bits map the DiffServ priority level to one of the eight priority ID levels in the “TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” on page 241. 241. Table 185: DiffServ DiffServ Priority Priority Map 3 Register Register (Page 30h: Address 52h–57h) 52h–57h) Bit

Name

47:45

R/W

Description

Default

DIFFSERV_111111_MAP R/W


0

44:42

DIFFSERV_111110_MAP R/W


0

41:39


R/W


0

38:36


R/W


0

35:33


R/W


0

32:30


R/W


0

29:27


R/W


0

26:24


R/W


0

23:21


R/W


0

20:18


R/W


0

17:15


R/W


0

14:12


R/W


0

11:9


R/W


0


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BCM53128 Data Sheet


Table 185: DiffServ DiffServ Priority Priority Map 3 Register Register (Page 30h: Address Address 52h–57h) (Cont.) (Cont.) Bit

Name

R/W

Description

Default

8:6


R/W


0

5:3


R/W


0

2:0


R/W


0


TC_To_COS TC_To _COS Mapping Register (Page 30h: Addres Address s 62h–63h) All the bits in Table in Table 186 map 186 map the priority ID to one of the TX queues. Table 186: TC_To_COS Mapping Register Register (Page 30h: Address 62h–63h) Bit

Name

R/W

Description

Default

15:14

PRI_111_QID

R/W

Priority ID 111 mapped to TX Queue ID

00

13:12

PRI_110_QID

R/W


00

11:10

PRI_101_QID

R/W


00

9:8

PRI_100_QID

R/W


00

7:6

PRI_011_QID

R/W


00

5:4

PRI_010_QID

R/W


00

3:2

PRI_001_QID

R/W


00

1:0

PRI_000_QID

R/W


00



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BCM53128 Data Sheet


CPU_To_COS Map Register (Page 30h: Address 64h–67h) Table 187: CPU_To_CO CPU_To_COS S Map Register Register (Page 30h: Address Address 64h–67h) BIt

Name

R/W

Description

Default

31:18

Reserved

RO

–

0

17:1 17:15 5

Exce Except ptio ion/ n/Fl Floo oodi ding ng R/W Processing to CPU COS Map

The packet packet forwar forwarded ded to the CPU for Except Exception ion 0 Processing/Flooding reason. The COS selection is based on the highest COS values among all the reasons for the packet.

14:1 14:12 2

Prot Protoc ocol ol Snoo Snoopi ping ng to CPU CPU COS Map

R/W

The packet packet forwar forwarded ded to the CPU for Protoc Protocol ol 0 Snooping reason. The COS selection is based on the highest COS values among all the reasons for the packet.

11:9 11:9

Prot Protoc ocol ol Ter Termina minati tion on to CPU CPU R/W COS Map

The packet packet forwar forwarded ded to the CPU for Protoc Protocol ol 0 Termination reason. The COS selection is based on the highest COS values among all the reasons for the packet.

8:6 8:6

Swit Switch chin ing g to CPU CPU COS COS Map Map R/W R/W

The The pack packet et forw forwar arde ded d to the the CPU CPU for for Swit Switch chin ing g 0 reason. The COS selection is based on the highest COS values among all the reasons for the packet.

5:3

SA Learning to CPU COS Map

R/W

The packet packet forwar forwarded ded to the CPU for SA 0 Learning reason. The COS selection is based on the highest COS among all the reasons reasons for the packet.

2:0 2:0

Mirro irrorr to CPU COS Map

R/W

The The pac packet ket for forwarde arded d to the the CPU for for mirro irrorring ing 0 reason. The COS selection is based on the highest COS values among all the reasons for the packet.


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BCM53128 Data Sheet


TX Queue Control Register (Page 30h: Address 80h) Table 188: TX Queue Control Control Register Register (Page 30h: Address Address 80h) Bit

Name

R/W

Description

Default

7:4

Reserved

R/W

Reserved

0

3:2

Reserved

R/W

Reserved

0

1:0

QOS_PRIORITY_ R/W R/W CTRL

Best Best Effort Effort Queues Queues Priori Priority ty Contro Controll 00 This This field field contro controls ls the best best effort effort queues queues’’ schedu scheduling ling priori priority. ty. It doesn’t affect the behavior of COS4 and COS5. 00: all queues are weighted round robin 01: COS3 is strict priority, COS2-COS0 are weighted round robin. 10: COS3 and COS2 is strict priority, COS1-COS0 are weighted round robin. 11: COS3, COS2, COS1 and COS0 are in strict priority. Strict priority: When it is in strict priority, the priority is COS3 > COS2 > COS1 > COS0. The G_TXPORT will always serve the higher queue first if it is not empty. In this mode, the service weight are don’t care. Weighted Weighted round robin: robin: When it is in weighted round robin mode, the queues are scheduled in a round robin way according according to the service weight of each queue.


TX Queue Weight Register (Page 30h: Address 81h) Table 189: TX Queue Weight Register Register Queue[0:3] Queue[0:3] (Page 30h: Address Address 81h–84h) Bit

Name

R/W

7:0 7:0

QSER QS ERV_ V_WE WEIG IGHT HT R/W R/W

Description

Default

Queu Queue e weig weight ht regi regist ster er The binary value of these bits sets the service weight of the given queue. The value of 1 allows the queue to send one packet for every round; the value of 4 allows the queu queue e to send send four four pack packet ets s for for ever every y roun round. d. It is sugg sugges este ted d that the weight of each queue be Q3 > Q2 > Q1 > Q0 > 0. Note: The Note: The maximum allowable transmit queue weight is 31h. Programming Programming a higher weight than 31h can yield unexpe unexpecte cted d result results. s. This This field field must must not be progra programme mmed d as zero.

Queue: 0: 0001 1: 0010 2: 0100 3: 1000



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BCM53128 Data Sheet


COS4 Service Weight Register (Page 30h: Address 85h–86h) Table 190: COS4 Service Weight Register (Page (Page 30h: Address 85h–86h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8

COS4 Strict Priority

R/W

COS4 Strict Priority 1 When When this this fiel field d is set set to ‘1’, ‘1’, the the C4 serv servic ice e weig weight ht is don’t care and Class 4 is in strict priority over the best effort queues (COS3–COS0).

7:0

COS4 Weight

R/W

COS4 Service Weight 1 This field defines the service weight between Class 4 traffic and the Best Effort COS3-COS0. When When this this field field is N, it means means ClassClass-4:B 4:Best est-Ef -Effor fortt = N:1 When in weighted round robin mode, it is meaningless meaningless to set this field as zero.


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BCM53128 Data Sheet

Page 31h: Port-Based VLAN Registers

Page 31h: Port-Based VLAN Registers Table 191: Page 31h VLAN Registe Registers rs Address

Bits

Description

00h–11h

16/port

“Port-Based VLAN Control Register (Page 31h: Address 00h)”

1Fh–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


Port-Based VLAN Control Register (Page 31h: Address 00h) Table 192: Port-Based VLAN Control Register Address Address Summary Address

Description

00h–01h

Port 0

02h–03h

Port 1

04h–05h

Port 2

06h–07h

Port 3

08h–09h

Port 4

0Ah–0Bh

Port 5

0Ch–0Dh

Port 6

0Eh–0Fh

Port 7

10h–11h

IMP port

Table 193: Port VLAN Control Control Register Register (Page 31h: Address 00h–11h) 00h–11h) BIt

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

FORWARD_MASK

R/W

VLAN forwarding mask Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Disable VLAN forwarding to egress port. 1 = Enable VLAN forwarding to egress port.

1FFh

For more information, see “Port-Based see “Port-Based VLAN” on page 38. 38.


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BCM53128 Data Sheet

Page 32h: Trunking Registers

Page 32h: Trunking Registers Table 194: Page 32h Trunking Trunking Registers Registers Address

Bits

Description

00h

8

“MAC Trunking Control Register (Page 32h: Address 00h)”

01h–0Fh

–

Reserved

10h–11h

16

Trunk group 0 register

12h–13h

16

Trunk group 1 register

14h–15h

–

Reserved

16h–17h

–

Reserved

18h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


MAC Trunking Control Register (Page 32h: Address 00h) Table 195: MAC Trunk Control Control Register Register (Page 32h: Address 00h) Bit

Name

R/W

Description

Default

7:4

Reserved

R/W

Reserved

0

3

MAC_BASE_TRNK_E R/W N

Enable MAC base trunking

0

2

Re Reserved

R/W

Reserved

0

1:0

TRK_HASH_INDX

R/W

Trunk hash index selector 00 = Use hash [DA,SA] to generate index. 01 = Use hash [DA] to generate index. 10 = Use hash [SA] to generate index. 11 = Illegal state

0

See “Port See “Port Trunking/Aggregation” on page 44 for 44 for more information.


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BCM53128 Data Sheet

Page 32h: Trunking Registers

Trunking Group 0 Register (Page 32h: Address 10h) Table 196: Trunk Group 0 Register Register (Page 32h: Address Address 10h–11h) Bit

Name

R/W

Description

Default

15:9

Reserved

R/W

Reserved

0

8:0

Tru Trunk Group Enable

R/W

Trunk group enable 1 = Enable trunk group. 0 = Disable trunk group. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.

0

See “Port See “Port Trunking/Aggregation” on page 44 for 44 for more information.

Trunking Group 1 Register (Page 32h: Address 12h) Table 197: Trunk Group 1 Register Register (Page 32h: Address Address 12h–13h) Bit

Name

R/W

Description

Default

15:9

Reserved

R/W

Reserved

0

8:0

Trunk Group Enable

R/W

Trunk group enable 1 = Enable trunk group. 0 = Disable trunk group. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.

0


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BCM53128 Data Sheet

Page 34h: IEEE 802.1Q VLAN Registers

Page 34h: IEEE 802.1Q VLAN Registers Table 198: Page 34h IEEE 802.1Q 802.1Q VLAN Registers Registers Address

Bits

Description

00h

8

“Global IEEE 802.1Q Register (Pages 34h: Address 00h)” on page 248

01h

8

“Global IEEE 802.1Q VLAN Control 1 Register (Page 34h: Address 01h)” on page 250

02h

8

“Global “Glob al VLAN Contr Control ol 2 Regist Register er (Page 34h: Addres Address s 02h)” on page 251

03h–04h

16


05h

8


06h

8


07h

8

Reserved

0Ah–0Bh

16

“” on page 254

Reserved

32

Reserved

10h–21h

16/port

“Default IEEE 802.1Q Tag Register (Page 34h: Address 10h)” on page 255

20h–2Fh

–

Reserved

30h–31h

16

“Double Tagging TPID Register (Page 34h: Address 30h–31h)” on page 256

32h–33h

16

“ISP Port Selection Portmap Register (Page 34h: Address 32h–33h)” on page 256

34h–3Fh

–

Reserved

40h–43h

32

Reserved

44h–48h

32

Reserved

49h–EFh

–

–

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


Global IEEE 802.1Q Register (Pages 34h: Address 00h) Table 199: Global Global IEEE 802.1Q Register Register (Pages 34h: Address Address 00h) Bit

Name

R/W

Description

7

Enable IEEE 802.1Q

R/W

Enable IEEE 802.1Q VLAN 0 = Disable IEEE 802.1Q VLAN. 1 = Enable IEEE 802.1Q VLAN. See “Progra See “Programming mming the VLAN Table” on page 40 40 for for more information. Note: This Note: This bit must be set if double tagging mode enable in “Global in “Global VLAN Control 4 Register (Page 34h: Address 05h)” on page 252. 252.

Default 0


Page 248


BCM53128 Data Sheet


Table 199: Global Global IEEE 802.1Q 802.1Q Register Register (Pages 34h: Address Address 00h) (Cont.) (Cont.) Bit

Name

R/W

Description

6:5

VLAN Learning Mode R/ R/W

VLAN lea learning mode 11 00 = SVL (Shared VLAN learning mode) (MAC hash ARL table) 11 = IVL (Individual VLAN learning mode) (MAC and VID hash ARL table) 10 = Illegal setting 01 = Illegal setting Note: Applied Note: Applied to 802.1Q enable and DT_Mode.

4

Reserved

R/W

Reserved

0

3

Change_1Q_VID

R/W

Change 1Q VID to PVID 1= • For a singl single e tag fram frame e with with VID not not = 0, chan change ge the VID to PVID.

0

•

Default

For a doub double le tag fram frame e with with outer outer VID VID not = 0, change outer VID to PVID.

0 = No change for 1Q/ISP tag if VID is not 0. 2

Reserved

R/W

Reserved

0

1

Reserved

R/W

Reserved

1

0

Reserved

R/W

Reserved

1

See “IEEE See “IEEE 802.1Q VLAN” on page 39 for 39 for more information.


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BCM53128 Data Sheet


Global IEEE 802.1Q VLAN Control 1 Register (Page 34h: Address 01h) Table 200: Global Global VLAN Control 1 Register (Page (Page 34h: Address 01h) Bit

Name

R/W

Description

Default

7

Reserved

R/W

Reserved

0

6

Mult Multic icas astt Unta Untag g Chec Check k

R/W R/W

Mult Multic icas astt VLAN VLAN unta untagg gged ed map map chec check k bypa bypass ss 0 1 = Multicast frames are not checked checked against the VLAN untagged map. 0 = Multicast frames are checked against the VLAN untagged untagged map. Does not apply to the frame frame management port.

5

Mult Multic icas astt Forw Forwar ard d Chec Check k R/W R/W

Mult Multic icas astt VLAN VLAN forw forwar ard d map map chec check k bypa bypass ss 0 1 = Multicast frames are not checked checked against the VLAN forward map. 0 = Multicast frames are checked against the VLAN forward map. Note: Applied Note: Applied to 802.1Q enable and DT_Mode.

4

Reserved

R/W

It is illegal to set 1.

3

Reserved Multicast Untag Check

R/W R/W

Rese Reserv rved ed mult multica icast st (exc (excep eptt GMRP GMRP and and GV GVRP RP)) VLAN VLAN 0 untagged untagged map check bit 1 = Reserved multicast (except GMRP and GVRP) frames are checked against the VLAN untagged map. 0 = Reserved multicast (except GMRP and GVRP) frames are not checked against the VLAN untagged map. Does not apply to the frame management management port.

2

Reserved Multicast Forward Check

R/W R/W

Rese Reserv rved ed mult multica icast st (exc (excep eptt GMRP GMRP and and GV GVRP RP)) VLAN VLAN 0 forward map check bit 1 = Reserved multicast (except GMRP and GVRP) frames are checked against the VLAN forward map. 0 = Reserved multicast (except GMRP and GVRP) frames are not checked against the VLAN forward map. Note: Applied Note: Applied to 802.1Q enable and DT_Mode.

1

Reserved

R/W

It is illegal to set 0.

1

0

Reserved

R/W

Reserved

0

0

For more information, see “IEEE see “IEEE 802.1Q VLAN” on page 39. 39.


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BCM53128 Data Sheet


Global VLAN Control 2 Register (Page 34h: Address 02h) Table 201: Global Global VLAN Control 2 Register (Page (Page 34h: Address 02h) Bit

Name

R/W

Description

Default

7

Reserved

R/W

Reserved

0

6

GMRP/GVRP Untag Check

R/W

GMRP GMRP or GVRP GVRP VLAN VLAN untag untag map check check bit 0 1 = GMRP or GVRP frames are checked against the VLAN untagged map. 0 = GMRP or GVRP frames are not checked against the VLAN untagged map. Note: Does Note: Does not apply to the frame management port.

5

GMRP/GVRP Fo Forward R/W Check

GMRP GMRP or or GVRP GVRP VLAN VLAN forwar forward d map check check bit 0 1 = GMRP or GVRP frames are checked against the VLAN forward map. 0 = GMRP or GVRP frames are not checked against the VLAN forward map. Note: Does Does not not apply apply to the the fram frame e mana manage geme ment nt port port.. Applied to 802.1Q enable and DT_Mode.

4

Reserved

R/W

Reserved

1

3

Reserved

R/W

Reserved

0

2

IMP Frame Forward Bypass

R/W

IMP Frame Frame VLAN VLAN forwar forward d map check check bit 1 = IMP frames are not checked against the VLAN forward map. 0 = IMP frames are checked against the VLAN forward map. Note: Applied Note: Applied to 802.1Q enable and DT_Mode.

0

1:0

Reserved

R/W

Reserved

00


Global VLAN Control 3 Register (Page 34h: Address 03h) Table 202: Global Global VLAN Control 3 Register (Page (Page 34h: Address 03h–04h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

–

–

7:0

Drop Non1Q Frames R/W R/W

Drop non1Q frames 0 When enabled, any frame without an IEEE 802.1Q tag is dropped by this port. This field does not apply to IMP port. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively.


Page 251


BCM53128 Data Sheet



Name

R/W

Description

7:6

Source Membership Check

R/W

Source Source member membership ship check check bit 11 Fram Frames es with with a VID VID matc matchin hing g a corr corres espo pond ndin ing g entr entry y in the VLAN table can be checked for source membership. The source is a member only when the sour source ce addr addres ess s of the the fram frame e is includ included ed as a memb member er in the corresponding VLAN entry. 00 = Forward frame, but do not learn the SA into the ARL table. 01 = Drop frame. 10 = Forward frame, and learn the SA into the ARL table. 11 = Forward frame to IMP, but not learn. Note: Does Note: Does not apply to IMP port.

5

Forward GVRP to Management

R/W

Forwar Forward d all all GVRP GVRP frames frames to the frame frame manage managemen mentt 0 port bit. 1 = GVRP frames are forwarded to the management port. 0 = GVRP frames are not forwarded to the management port.

4

Forward GMRP to Management

R/W R/W

Forw Forwar ard d All GMRP GMRP Fram Frames es to the the fram frame e mana manage geme ment nt 0 port bit. 1 = GMRP frames are forwarded to the management port. 0 = GMRP frames are not forwarded to the management port.

3:2

En_DT_Mode

R/W

00 = Disable double tagging mode 01 = Enable DT_Mode DT_Mode (double tagging mode) 10 = Reserved 11 = Reserved

1

RSV_MCAST_FLOO R/W D

When When the the BCM531 BCM53128 28 is config configure ured d to to oper operate ate in double tag feature management mode. 1 = Flood (including all data port and CPU), reserved mcast is based on the VLAN rule. 0 = Trap reserved mcast to CPU. Reserved mcast include: 01-80-C2-00-00(00,02~2F)

0

Reserved

Reserved

R/W

Default

2'b00

0



Page 252


BCM53128 Data Sheet



Name

R/W

Description

Default

7

Reserved

R/W

Reserved

0

6

Tag Tag Stat Status us Pres Prese erve rve

R/W

IEEE IEEE 802. 802.1Q 1Q tag/u ag/unt ntag ag stat tatus pres preser erv ved at egr egress. ess. 0 1 = Regardless Regardless of untag map in VLAN table, non-1Q non-1Q frames frames (includ (including ing 802.1p 802.1p frames frames)) will will not be change changed d at TX (egress). This field has no effect in double tagging mode (DT_Mode).

5

Reserved

R/W

Reserved

4

Trunk Check Bypass

R/W

Trunk check bypass 1 1 = Egress directed frames issued from the IMP port bypass trunk checking. 0 = Egress directed frames issued from the IMP port are subject to trunk checking and redirection.

3

Drop Invalid VID

R/W

Drop frames with invalid VID. 0 Frames with an invalid VID do not have a corresponding entry in the VLAN table. 1 = Ingress frames with invalid VID are dropped. 0 = Ingress frames with invalid VID are forwarded to the IMP port.

2

VID_FFF_Fwding

R/W

Enable VID FFF forward 1 = Forward frame 0 = Comply with standard, drop frame

0

1

Reserved

R/W

Reserved

0

0

Management CRC Check Bypass

R/W

Bypass Bypass CRC check check at the frame frame manage managemen mentt port port.. 0 1 = Ignore CRC check 0 = Check CRC

0



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BCM53128 Data Sheet


VLAN Multiport Address Control Register (Page 34h: Address 0Ah– 0Bh) Table 205: VLAN Multiport Address Control Control Register (Page 34h: Address 0Ah–0Bh) Bit

Name

R/W

Description

Default

15:12

Reserved

RO

Reserved

0

11

EN_MPORT5_untagmap

R/W

When set to 1, MPORT_ADD5 is checked by 0 VLAN untag map. Note: Does Does not not appl apply y to the the fram frame e mana manage geme ment nt port.

10

EN_MPORT5 _fwdmap

R/W

When set to 1, MPORT_ADD5 is checked by 0 VLAN forward map. Note: Does Does not not appl apply y to the the fram frame e mana manage geme ment nt port.

9

EN_MPORT4_untagmap

R/W

When set to 1, MPORT_ADD4 will be checked 0 by VLAN untag map. Note: Does Does not not appl apply y to the the fram frame e mana manage geme ment nt port.

8

EN_MPORT4 _fwdmap

R/W

When set to 1, MPORT_ADD4 will be checked 0 by VLAN forward map. Note: Does Does not not appl apply y to the the fram frame e mana manage geme ment nt port.

7

EN_MPORT3_untagmap

R/W


6

EN_MPORT3 _fwdmap

R/W


5

EN_MPORT2_untagmap

R/W


4

EN_MPORT2 _fwdmap

R/W


3

EN_MPORT1_untagmap

R/W


2

EN_MPORT1 _fwdmap

R/W



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BCM53128 Data Sheet


Table 205: VLAN Multiport Multiport Address Address Control Register Register (Page 34h: Address Address 0Ah–0Bh) (Cont.) (Cont.) Bit

Name

R/W

Description

Default

1

EN_MPORT0_untagmap

R/W


0

EN_MPORT0 _fwdmap

R/W


Default IEEE 802.1Q Tag Register (Page 34h: Address 10h) Table 206: Default IEEE 802.1Q Tag Register Address Address Summary Address

Description

10h–11h

Port 0

12h–13h

Port 1

14h–15h

Port 2

16h–17h

Port 3

18h–19h

Port 4

1Ah–1Bh

Port 5

1Ch–1Dh

Port 6

1Eh–1Fh

Port 7

20h–21h

IMP port

Table 207: Default Default IEEE 802.1Q Tag Register Register (Page 34h: Address 10h–21h) 10h–21h) Bit

Name

R/W

Description

Default

15:13

DEFA FAU ULT_PRI/ PORT_QOS_PRI

R/W

Defaul Defaultt IEEE IEEE 802.1Q 802.1Q priori priority ty 000 If an IEEE 802.1Q tag is added to an incoming untagged frame (IEEE 802.1Q VLAN or DoubleTagging enabled), these bits are the default priority value for the new tag. See “IEEE See “IEEE 802.1Q VLAN” on page 39 and 39 and “Double-Tagging” “Double-Tagging” on page 41 for 41 for more information. Port-based QoS priority map bits When port-based QoS is enabled in the Table the Table : “QoS Global Control Register (Page 30h: Address 00h),” on page 236, 236, these bits represent the TC for the ingress port. The TC determines the TX queue for each frame based on the “TC_To_COS the “TC_To_COS Mapping Register (Page 30h: Address 62h–63h)” 62h–63h)” on page 241. 241.

12

CFI

R/W

Conical form indicator

0


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BCM53128 Data Sheet


Table 207: Default IEEE 802.1Q Tag Register (Page (Page 34h: Address 10h–21h) (Cont.) (Cont.) Bit

Name

R/W

Description

Default

11:0

DEFAULT_VID

R/W

Default IEEE 802.1Q VLAN ID 001 If an IEEE 802.1Q tag is tagged to an incoming nonIEEE 802.1Q frame (IEEE 802.1Q VLAN or DoubleTagging Tagging enabled), enabled), then these bits are the default default VID for the new tag. See “IEEE See “IEEE 802.1Q VLAN” on page 39 and “Doub “Double-Tag le-Tagging” ging” on page 41 for more informatio information. n.

Double Tagging TPID Register (Page 34h: Address 30h–31h) Table 208: Double Double Tagging TPID Register Register (Page 34h: Address 30h–31h) 30h–31h) Bit

Name

R/W

Description

Default

15:0

ISP_TPID

R/W

The TPID used to identify double tagged frame.

9100

ISP Port Selection Portmap Register (Page 34h: Address 32h–33h) Table 209: ISP Port Selection Selection Portmap Register Register (Page 34h: Address 32h–33h) Bit

Name

R/W

Description

Default

15:9

RESERVED

RO

Reserved

0

8:0 8:0

ISP_ ISP_Po Port rtma map p

R/W R/W

Bitm Bitmap ap that that defi define nes s whic which h port port is desi design gnat ated ed as the the ISP ISP port. Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Indicates that it is not an ISP port. 1 = Indicates that it is an ISP port.

0


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BCM53128 Data Sheet

Page 36h: DOS Prevent Register

Page 36h: DOS Prevent Register Table 210: DOS Prevent Prevent Register Register Address

Bits

Description

00h–03h

32

“DOS Control Register (Page 36h: Address 00h–03h)”

04h

8

“Minimum “Minim um TCP Heade Headerr Size Regis Register ter (Page 36h: Addre Address ss 04h)” on page 259

08h–0Bh

32

“Maximum ICMPv4 Size Register (Page 36h: Address 08h–0Bh)” on page 259

0Ch–0Fh

32

“Maximum ICMPv6 Size Register (Page 36h: Address 0Ch–0Fh)” on page 259

10h

8

“DOS Disable Learn Register (Page 36h: Address 10h)” on page 259

F0h–F7h

8

“SPI Data I/O Register (Global, Address F0h)” on page 295

F8h–FDh

–

Reserved

FEh

8


FFh

8


DOS Control Register (Page 36h: Address 00h–03h) Table 211: DOS Control Control Register Register (Page 36h: Address 00h–03h) Bit

Name

R/W

Description

Default

31:14

Reserved

RO

Reserved

0

13

ICMP ICMPv6 v6_L _Lon ongP gPin ing_ g_DR DROP OP_E _EN N

R/W R/W

The The ICMP ICMPv6 v6 ping ping (ech (echo o requ reques est) t) prot protoc ocol ol 0 data unit carried in an unfragmented IPv6 datagram with its payload length indicating a value greater than the MAX_ICMPv6_Size. 1= Drop 0= Do not drop

12

ICMP ICMPv4 v4_L _Lon ongP gPin ing_ g_DR DROP OP_E _EN N

R/W R/W

The The ICMP ICMPv4 v4 ping ping (ech (echo o requ reques est) t) prot protoc ocol ol 0 data unit carried in an unfragmented IPv4 datagram with its Total Length indicating a value greater than the MAX_ICMPv4_Size + size of IPv4 header. 1= Drop 0= Do not drop

11

ICMP ICMPv6 v6_F _Fra ragm gmen ent_ t_DR DROP OP_E _EN N

R/W R/W

The The ICMP ICMPv6 v6 prot protoc ocol ol data data unit unit carr carrie ied d in a 0 fragmented IPv6 datagram. 1= Drop 0= Do not drop

10

ICMP ICMPv4 v4_F _Fra ragm gmen ent_ t_DR DROP OP_E _EN N

R/W R/W

The The ICMP ICMPv4 v4 prot protoc ocol ol data data unit unit carr carrie ied d in a 0 fragmented IPv4 datagram. 1= Drop 0= Do not drop


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BCM53128 Data Sheet


Table 211: DOS Control Register Register (Page 36h: Address Address 00h–03h) (Cont.) Bit

Name

R/W

Description

Default

9

TCP_FragError_DROP_EN

R/W

The Fragment_Offset = 1 in any fragment of 00 a fragmented IP datagram carrying part of TCP data. 1 = Drop 0 = Do not drop

8

TCP_ShortHDR_DROP_E P_EN

R/W

The len length of a TCP header carried in an unfragmented IP datagram or the first fragment of a fragmented IP datagram is less than MIN_TCP_Header_Size. 1 = Drop 0 = Do not drop

7

TCP_SYNErr Error_DROP_EN

R/W

SYN = 1, ACK ACK = 0, and SRC_Port<1024 in 0 a TCP header carried carried in an unfragmented unfragmented IP datagram or in the first fragment of a fragmented IP datagram. 1= Drop 0= Do not drop

6

TCP_SYNFIN FINScan_DROP_EN

R/W

SYN = 1 and FIN = 1 in a TCP header 0 carried in an unfragmented IP datagram or in the first fragment fragment of a fragmented fragmented IP datagram. 1= Drop 0= Do not drop

5

TCP_XMASScan_DROP_E P_EN

R/W

Seq_Num = 0, FIN = 1, URG = 1, and PS PSH H 0 = 1 in a TCP header carried in an unfragmented IP datagram or in the first fragment of a fragmented IP datagram. 1 = Drop 0 = Do not drop

4

TCP_NULLScan_DROP_EN

R/W

Seq_Num = 0 and all TCP_FLAGs = 0 in a 0 TCP header carried in an unfragmented IP datagram or in the first fragment of a fragmented IP datagram. 1= Drop 0= Do not drop

3

UDP_BLAT_DROP_EN

R/W

DPort = SPort i n a UDP header c ar arried in an 0 unfragmented IP datagram or in the first fragment of a fragmented IP datagram. 1= Drop 0= Do not drop

2

TCP_BLAT_DROP_EN

R/W

DP DPort = SPort i n a TCP header ca c arried i n an an 0 unfragmented IP datagram or in the first fragment of a fragmented IP datagram. 1= Drop 0= Do not drop

00


Page 258


BCM53128 Data Sheet


Table 211: DOS Control Register Register (Page 36h: Address Address 00h–03h) (Cont.) Bit

Name

R/W

Description

Default

1

IP_LAN_DRIP_EN

R/W

IPDA = IPSA in an IPv4/v6 datagram. 1=Drop 0=Do not drop

0

0

RESERVED

R/W

Reserved

1

Minimum TCP Header Size Register (Page 36h: Address 04h) Table 212: Minimum Minimum TCP Header Size Register Register (Page 36h: Address 04h) Bit

Name

R/W

Description

Default

7:0 7:0

MIN_TC N_TCP_ P_H HDR_SZ R_SZ

R/W

Minim inimum um TCP TCP head header er size size allo allow wed (0–25 0–256 6 byt bytes) es). 8'h1 8'h14 4

Maximum ICMPv4 Size Register (Page 36h: Address 08h–0Bh) Table 213: Maximum ICMPv4 ICMPv4 Size Register (Page (Page 36h: Address 08h-0Bh) Bit

Name

R/W

Description

Default

31:0

MAX_ICMPv4_SIZE

R/W

Max ICMPv4 size allowed (0–9.6K bytes).

32'd512

Maximum ICMPv6 Size Register (Page 36h: Address 0Ch–0Fh) Table 214: Maximum ICMPv6 ICMPv6 Size Register (Page (Page 36h: Address 0Ch-0Fh) Bit

Name

R/W

Description

Default

31:0

MAX_ICMPv6_SIZE

R/W

Max ICMPv6 size allowed (0–9.6K bytes).

32'd512

DOS Disable Learn Register (Page 36h: Address 10h) Table 215: DOS Disable Disable Learn Register Register (Page 36h: Address 08h-0Bh) 08h-0Bh) Bit

Name

R/W

Description

Default

7:1

RESERVED

R/W

Reserved

–

0

DOS Disable Lrn

R/W

When this bit enabled, all frames dropped by DOS 0 prevent prevent will not be learned. learned.


Page 259


BCM53128 Data Sheet

Page 40h: Jumbo Frame Control Register

Page 40h: Jumbo Frame Control Register Table 216: Page 40h Jumbo Frame Control Control Register Register Address

Bits

Description

00h

–

Reserved

01h–04h

32

“Jumbo Frame Port Mask Register (Page 40h: Address 01h)”

05h–06h

16

“Standard Max Frame Size Register (Page 40h: Address 05h)” on page 261

07h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


Jumbo Frame Port Mask Register (Page 40h: Address 01h) Table 217: Jumbo Frame Port Mask Registers Registers (Page 40h: Address Address 01h–04h) BIt

Name

R/W

Description

Default

31:25

Reserved

RO

Reserved

0

24:9

Reserved

R/W

Reserved

0

8:0 8:0

JUMB JUMBO_ O_PO PORT RT_M _MAS ASK K R/W R/W

Jumb Jumbo o fram frame e port port mask mask 0 Bit 8: IMP port Bits [7:0] correspond to ports [7:0], respectively. 0 = Disable jumbo frame capability on the port. 1 = Enable jumbo frame capability on the port. Jumbo frames can be ingressed and egressed only to the ports enabled via this port mask. Jumbo frame port mask has no effect on the traffic of normal sized frames. See “Jumbo “Jumb o Frame Suppor Support” t” on page 44 for 44 for more information.

Note: When Note: When the Jumbo Frame feature is enabled, the assigned Weight value for the WRR scheduling cannot be applied fairly over the queues. This is due to the internal Packet Buffer Memory size limitation. Note: The Note: The Jumbo Frame feature is only supported in 1000 Mbps mode.


Page 260


BCM53128 Data Sheet

Page 40h: Jumbo Frame Control Register

Standard Max Frame Size Register (Page 40h: Address 05h) Table 218: Standard Standard Max Frame Size Registers Registers (Page 40h: Address 05h–06h) Bit

Name

R/W

Description

Default

15:14

Reserved

RO

Reserved

0

13:0

Standard Max Frame Size

R/W R/W

Stan Standa dard rd Max Max Fram Frame e Size Size ‘d2000 Defines the standard maximum frame size for MAC and MIB counter. This register only allowed to be configured as 14'd1518 or 14'd2000. When jumbo is disabled, the content content of this register register is used to define good frame length. • If it is configur configured ed as 1518, 1518, the tagged tagged frames frames will be drop droppe ped d if the the fram frame e lengt length h is large largerr than than 1522 1522 bytes; and the untagged frames will be dropped if the frame length is larger than 1518 bytes. • If itit is configured configured as 2000, 2000, both both tagged tagged and untagged untagged frames will be dropped dropped if the frame length length is larger than 2000 bytes. When jumbo is enabled, all frames will be dropped if the frame length is larger than 9720 bytes. The register setting affects the following MIB parameters: • RxSA RxSACh Chan ange ge • RxGood RxGoodOct Octets ets • RxUnic RxUnicast astPkt Pkts s • RxMult RxMultica icastP stPkts kts • RxBroa RxBroadca dcastP stPkts kts • RxOver RxOverSize SizePkt Pkts s


Page 261


BCM53128 Data Sheet

Page 41h: Broadcast Storm Suppression Register

Page 41h: Broadcast Storm Suppression Register Table 219: Broadcast Storm Suppression Register (Page 41h) Address

Bits

Description

00h–03h

32

“Ingress Rate Control Configuration Register (Page 41h: Address 00h)”

04h–0Fh

–

Reserved

10h–33h

32/port

“Port “Po rt Rec Receiv eive e Rat Rate e Con Contro troll Reg Regist ister er (Pa (Page ge 41h 41h:: Add Addres ress s 10h 10h)” )” on pag page e 264

34h–4Fh

–

Reserved

50h–73h

–

Reserved

74h–7Fh

–

Reserved

80h–91h

16/port

“Port Egress Rate Control Configuration Register (Page 41h: Address 80h– 91h)” on page 266

92h–BFh

–

Reserved

C0h

8

“IMP Port Egress Rate Control Configuration Register (Page 41h: Address C0h)” on page 267

C2h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


Ingr In gres ess s Ra Rate te Co Cont ntro roll Co Conf nfig igur urat atio ion n Re Regi gist ster er (P (Pag age e 41 41h: h: Ad Addr dress ess 00h 00h)) Table 220: Ingress Rate Control Configuration Register (Page 41h: Address 00h–03h) BIt

Name

R/W Description

Default

31:19 Reserved

RO

Reserved

0

18

XLENEN

R/W

Pa Packet Length Selection 0 = RX rate excludes IPG. 1 = RX rate includes IPG (and Preamble + SFD).

0

17

BUCK1_ BRM_SEL

R/W R/W Bit rate rate mode mode sele selecti ction on 0 0 = Absolute bit rate mode—The rate count in the “Port Receive Rec eive Rat Rate e Con Contro troll Reg Regist ister er (Pa (Page ge 41h 41h:: Addr Address ess 10h 10h)” )” on page 264 represents 264 represents the incoming bit rate as an absolute data rate. 1 = Bit rate normalized normalized to link speed mode—The mode—The rate count in the “Port the “Port Receive Rate Control Register (Page 41h: Address 10h)” on page 264 264 represents represents the incoming bit rate normalized normalized with respect to the link speed mode. See “Rate See “Rate Control” on page 45 for 45 for more details.

16

Reserved

R/W Reserved

1


Page 262


BCM53128 Data Sheet


Table 220: Ingress Ingress Rate Control Configurat Configuration ion Register Register (Page 41h: Address 00h–03h) 00h–03h) (Cont.) (Cont.) BIt

Name

R/W Description

Default

15:9 15:9

BUCK1_ BUCK1_PAC PACKET KET_ _ R/W Suppressed Suppressed packet type mask. 0 TYPE This This bitmask dete determ rmin ines es the the type type of pack packet ets s to be moni monito tore red d by bucket 1. 0 = Disable suppression for the corresponding packet type. 1 = Enable suppression suppression for the correspondi corresponding ng packet type. The bits in this bit field are defined as follows: Bit 9: Unicast lookup hit Bit 10: Multicast Multicast lookup hit Bit 11: Reserved MAC Address Frame Bit 12: Broadcast Bit 13: Multicast lookup failure Bit 14: Unicast lookup failure Bit 15: Reserved See “Rate See “Rate Control” on page 45 for 45 for more details.

8

BUCK0_ BRM_SEL

R/W R/W Bit rate rate mode mode sele selecti ction on BC_SUPP_EN 0 = Absolute bit rate mode—The rate count in the “Port Receive Rec eive Rat Rate e Con Contro troll Reg Regist ister er (Pa (Page ge 41h 41h:: Addr Address ess 10h 10h)” )” on page 264 represents 264 represents the incoming bit rate as an absolute data rate. 1 = Bit rate normalized normalized to link speed mode—The mode—The rate count in the “Port the “Port Receive Rate Control Register (Page 41h: Address 10h)” on page 264 264 represents represents the incoming bit rate normalized normalized with respect to the link speed mode. See “Rate See “Rate Control” on page 45 for 45 for more details.

7

Reserved

R/ R /W Reserved

1

6

XLEN XLENEN EN_E _EG G

R/W R/W Pack Packet et leng length th sele select ctio ion n for for egre egress ss rate rate cont contro rol. l. 0 = TX Rate Exclude IPG 1 = TX Rate Include IPG (and Preamble + SFD)

0

5:0 5:0

BUCK BUCK0_ 0_PA PACK CKET ET_ _ R/W Suppressed Suppressed packet type mask. BC_SUPP_EN: TYPE This This bitmask dete determ rmin ines es the the type type of pack packet ets s to be moni monito tore red d 1: 001000 by bucket 0. 0: 000000 0 = Disable suppression for the corresponding packet type. 1 = Enable suppression suppression for the correspondi corresponding ng packet type. The bits in this bit field are defined as follows: Bit 0: Unicast lookup hit Bit 1: Multicast Multicast lookup hit Bit 2: Reserved MAC address frame Bit 3: Broadcast Bit 4: Multicast lookup failure Bit 5: Unicast lookup failure See “Rate See “Rate Control” on page 45 for 45 for more details.


Page 263


BCM53128 Data Sheet


Port Receive Rate Control Register (Page 41h: Address 10h) Table 221: Port Rate Control Control Register Address Summary Summary Address

Description

10h–13h

Port 0

14h–17h

Port 1

18h–1Bh

Port 2

1Ch–1Fh

Port 3

20h–23h

Port 4

24h–27h

Port 5

28h–2Bh

Port 6

2Ch–2Fh

Port 7

30h–33h

IMP port for BCM53128

Table 222: Port Rate Control Control Register Register (Page 41h: Address 10h–33h) 10h–33h) BIt

Name

R/W

Description

Default

31:29

Reserved

RO

Reserved

0

28

STRM STRM_S _SUP UPR_ R_EN EN R/W R/W

Enabl Enable e stor storm m supp suppre ress ssio ion n (Sup (Suppo port rted ed by buck bucket et1) 1).. 0 = Disable 1 = Enable

Reflects the strap pin BC_SUPP_ EN

27

RsvM RsvMC_ C_SU SUPR PR_E _EN N R/W R/W

Enabl Enable e rese reserv rved ed mulit mulitca cast st stor storm m supp suppre ress ssion ion.. 0 = Disable 1 = Enable

0

26

BC_ BC_SUPR SUPR_E _EN N

R/W

Enab Enable le broa broadc dcas astt stor storm m supp supprressi ession on.. 0 = Disable 1 = Enable

0

25

MC_S MC_SU UPR_E PR_EN N

R/W

Enab Enable le mult multic icas astt stor torm supp suppre res ssion sion.. 0 = Disable 1 = Enable

0

24

DLF_S LF_SUP UPR R_EN _EN

R/W

Enab Enable le DLF DLF stor storm m supp suppre ress ssio ion. n. 0 = Disable 1 = Enable

0

23

Enab Enable le Buck Bucket et1 1

R/W R/W

Enab Enable le rate rate cont contro roll of the the ingr ingres ess s port port,, buck bucket et 1. 0 = Disable 1 = Enable

0

22

Enab Enable le Buck Bucket et0 0

R/W R/W

Enab Enable le rate rate cont contro roll of the the ingr ingres ess s port port,, buck bucket et 0. 0 = Disable 1 = Enable

Reflects the strap pin BC_SUPP_ EN


Page 264


BCM53128 Data Sheet


Table 222: Port Rate Control Register (Page 41h: Address 10h–33h) (Cont.) BIt

Name

R/W

Description

21:19

BUCK1_SIZE

R/W

Bucket size 000 This bit determines the maximum size of bucket 1. This is specified on a per port basis. 000 = 4 KB 001 = 8 KB 010 = 16 KB 011 = 32 KB 100 = 64 KB 101 = 500 KB 110 = 500 KB 111 = 500 KB See “Rate See “Rate Control” on page 45 for 45 for more details.

18:1 18:11 1

BUCK BUCK1_ 1_Ra Rate te_C _Cnt nt R/W R/W

Rate Rate coun countt 10h The rate count is an integer that increments the rate at which traffic can ingress the given port without being suppressed. This value is specified on a per port basis. The programmed programmed values of the rate count and the bit rate mode of the “Ingress the “Ingress Rate Control Configuration Register (Page 41h: Address 00h)” on page 262 determine 262 determine the bucket bit rate in kilobytes. The bucket bit rate represents the average upper limit for incoming packets selected in the suppressed suppressed packet type mask in the “Ingress the “Ingress Rate Control Configuration Register (Page 41h: Address 00h)” on page 262. 262. See “Rate See “Rate Control” on page 45 for 45 for more details. Values written to these bits must be with the ranges specified by Table by Table 3 on page 47. 47. Values outside outside these ranges are not valid.

10:8

BUCK0_SIZE

Bucket size 000 This bit determines the maximum size of bucket 0. This is specified on a per port basis. 000 = 4 KB 001 = 8 KB 010 = 16 KB 011 = 32 KB 100 = 64 KB 101 = 500 KB 110 = 500 KB 111 = 500 KB See “Rate See “Rate Control” on page 45 for 45 for more details.

R/W

Default


Page 265


BCM53128 Data Sheet


Table 222: Port Rate Control Register (Page 41h: Address 10h–33h) (Cont.) BIt

Name

R/W

Description

Default

7:0

BUCK0_Rate_Cnt

R/W

Rate count 10h The rate count is an integer that increments the rate at which traffic can ingress the given port without being suppressed. This value is specified on a per port basis. The programmed programmed values of the rate count and the bit rate mode of the “Ingress the “Ingress Rate Control Configuration Register (Page 41h: Address 00h)” on page 262 determine 262 determine the bucket bit rate in kilobytes. The bucket bit rate represents the average upper limit for incoming packets selected in the Suppressed Suppressed packet type mask in the “Ingress the “Ingress Rate Control Configuration Register (Page 41h: Address 00h)” on page 262. 262. See “Rate See “Rate Control” on page 45 for 45 for more details.

Port Egress Rate Contr Control ol Config Configurati uration on Regist Register er (Page (Page 41h: Addres Address s 80h–91h) Table 223: Port Egress Rate Control Control Configuration Register Register Address Summary Summary Address

Description

80h–81h

Port 0

82h–83h

Port 1

84h–85h

Port 2

86h–87h

Port 3

88h–89h

Port 4

8Ah–8Bh

Port 5

8Ch–8Dh

Port 6

8Eh–8Fh

Port 7

90h–91h

IMP port

Table 224: Port Egress Rate Control Configuration Configuration Registers (Page 41h: Address 80h–91h) BIt

Name

R/W

Description

Defaul t

15:12

Reserved

RO

Reserved

0

11

ERC_EN

R/W

Egress rate control enable ((Absolute Bit Rate)

0


Page 266


BCM53128 Data Sheet


Table 224: Port Egress Egress Rate Control Configurat Configuration ion Registers Registers (Page 41h: Address 80h–91h) 80h–91h) (Cont.) (Cont.) Defaul t

BIt

Name

R/W

Description

10:8

BKT_SZE

R/W

Bu Bucket size 0 This bit determines the maximum size of bucket 0. This is specified on a per port basis. 000 = 4 KB 001 = 8 KB 010 = 16 KB 011 = 32 KB 100 = 64 KB 101 = 500 KB 110 = 500 KB 111 = 500 KB See “Rate See “Rate Control” on page 45 for 45 for more details.

7:0

RATE_CNT

R/W

Rate count for bucket

0

IMP Port Egress Rate Control Configuration Register (Page 41h: Address Addre ss C0h) Table 225: IMP Port Egress Rate Control Control Configuration Register Address Summary Summary Address

Description

C0h

IMP Port

Table 226: IMP Port Egress Rate Control Control Configuration Registers (Page 41h: Address Address C0h) BIt

Name

R/W

Description

Defaul t

7:6

RESERVED

RO

Reserved

0

5:0 5:0

Rate Rate_I _Ind ndex ex

R/W R/W

Rate Rate_I _Ind ndex ex is used used to conf config igur ure e diff differ eren entt egre egress ss rate rates s for for IMP IMP in 6'd63 packet per second (pps). See Table See Table 227: “Using Rate_Index to Configure Conf igure Different Different Egress Rates for IMP in pps,” on page 268. 268. When set to 0, the egress rate is limited to a maximum of 384 pps. When set to 63, the egress rate control function is disabled and all packets are transmitted at wire-speed. Note: If Note: If the Rate_Index is configured as a certain value, the egress rate is limited to the corresponding speed whether the switch is running at 10 Mbps, 100 Mbps, or 1 Gbps. Note: The Note: The Rate_Index Rate_Index should be a reasonable reasonable value under the corresponding network speed configuration. It does not make sense to set a value of 63 with the network configuration at 10 Mbps. In that case, the egress rate is limited up to 10 Mbps.


Page 267


BCM53128 Data Sheet

Page 42h: EAP Register

Table 227: Using Rate_Index to Configure Different Different Egress Rates for IMP in pps Rate_Index

pp s

Rate_Index pps

Rate_Index pps

Rate_Index

pp pps

0

384

16

5376

32

25354

48 48

357143

1

512

17

5887

33

27382

49 49

423729

2

639

18

6400

34

29446

50 50

500000

3

768

19

6911

35

31486

51 51

568182

4

1024

20

7936

36

35561

52

641026

5

1280

21

8960

37

39682

53

714286

6

1536

22

9984

38

42589

54

781250

7

1791

23

11008

39 39

56818

55

862069

8

2048

24

12030

40 40

71023

56

925926

9

2303

25

13054

41 41

85324

57

1000000

10

2559

26 26

14076

42

99602

58

1086957

11

2815

27 27

15105

43

113636

59

1136364

12

3328

28 28

17146

44

127551

60

1190476

13

3840

29 29

19201

45

142045

61

1250000

14

4352

30 30

21240

46

213675

62

1315789

15

4863

31 31

23299

47

284091

63

1388889

Page 42h: EAP Register Table 228: Broadcast Storm Suppression Register (Page 42h) Address

Bits

Description

00h

8

“EAP Global Contr Control ol Regist Register er (Page 42h: Addres Address s 00h)” on page 269

01h

8

“EAP Multiport Address Control Register (Page 42h: Address 01h)” on page 269

02h–09h

64

“EAP Dest Destination ination IP Regis Register ter 0 (Page 42h: Addres Address s 02h)” on page 270

0Ah–12h

64

“EAP Dest Destination ination IP Regis Register ter 1 (Page 42h: Addres Address s 0Ah)” on page 270

20h–5Fh

64

“Port EAP Configuration Register (Page 42h: Address 20h)” on page 271

60h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8



Page 268


BCM53128 Data Sheet


EAP Global Control Register (Page 42h: Address 00h) Table 229: EAP Global Global Control Registers Registers (Page 42h: Address Address 00h) BIt

Name

R/W

Description

Defaul t

7

Reserved

R/W

Reserved

0

6

EN_RARP

R/W

When EAP_BLK_MODE is set: 1: Allow RARP to pass. 0: Drop RARP

0

5

EN_BPDU

R/W

When EAP_BLK_MODE is set: 1: BPDU Addresses are allowed to pass. 0: Drop

0

4

EN_RMC

R/W

When EAP_BLK_MODE is set: 1: Allows DA = 01-80-C2-00-00-02, 04~0F to pass. 0: Drop DA = 01-80-C2-00-00-02, 04~0F to pass.

0

3

EN_DHCP

R/W

When EAP_BLK_MODE is set: 1: Allows DHCP to pass 0: Drop DHCP

0

2

EN_ARP

R/W

When EAP_BLK_MODE is set: 1: Allows ARP to pass 0: Drop ARP

0

1

EN_2DIP

R/W

When EAP_BLK_MODE bit is set: 0 1: Two subnet IP addresses defined in EAP destination IP registers 0 and 1 are allowed to pass. 0: Drop

0

Reserved

R/W

Reserved

0

EAP Multiport Address Control Register (Page 42h: Address 01h) Table 230: EAP Multiport Address Control Register Register (Page 42h: Address 01h) BIt

Name

R/W

Description

Default

7:6

Reserved

RO

Reserved

0

5

EN_MPORT5

R/W

1: Al A llow Mu M ultiport ET E TYPE A dd ddress 5 define at a t “Multiport 0 Address N (N=0–5) Register (Page 04h: Address 10h)” on page 182 to 182 to pass. 0: Drop

4

EN_MPORT4

R/W


3

EN_MPORT3

R/W



Page 269


BCM53128 Data Sheet


Table 230: EAP Multiport Multiport Address Address Control Control Register Register (Page 42h: Address Address 01h) (Cont.) (Cont.) BIt

Name

R/W

Description

Default

2

EN_MPORT2

R/W


1

EN_MPORT1

R/W


0

EN_MPORT0

R/W


EAP Destination IP Register 0 (Page 42h: Address 02h) Table 231: EAP Destinati Destination on IP Registers Registers 0 (Page 42h: Address 02h–09h) BIt

Name

R/W

Description

Default

63:32

DIP_SUB 0

R/W

EAP destination IP subnet register 0

0

31: 0

DIP_MSK 0

R/W

EAP destination IP mask register 0

0

EAP Destination IP Register 1 (Page 42h: Address 0Ah) Table 232: EAP Destinati Destination on IP Registers 1 (Page 42h: Address 0Ah–12h) 0Ah–12h) BIt

Name

R/W

Description

Default

63:32

DIP_SUB 1

R/W

EAP destination IP subnet register 1

0

31:0

DIP_MSK 1

R/W

EAP destination IP mask register 1

0


Page 270


BCM53128 Data Sheet


Port EAP Configuration Register (Page 42h: Address 20h) Table 233: Port EAP Configuration Configuration Register Address Address Summary Address

Description

20h–27h

Port 0

28h–2Fh

Port 1

30h–37h

Port 2

38h–3Fh

Port 3

40h–47h

Port 4

48h–4Fh

Port 5

50h–57h

Port 6

58h–5Fh

Port 7

Table 234: Port EAP Configuration Configuration Registers (Page (Page 42h: Address 20h–47h) BIt

Name

R/W

Description

Default

63:55

Reserved

RO

Reserved

0

52:51

EAP EA P_MODE

R/W

00 = Basic mode, do not check SA. 0 01 = Reserved Reserved 10 = Extend mode, check SA and port number, drop if SA is unknown. 11 = Simplified mode, check SA and port number trap to management port if SA is unknown.

50:4 50:49 9

EAP_ EA P_BL BLK_ K_MO MODE DE R/W R/W

00: 00: Do not not chec check k EA EAP_ P_BL BLK_ K_MO MODE DE.. 0 01: To check EAP_BLK MODE on ingress port, only the frame defined in EAP_GCFG will be forwarded. Otherwise, the frame will be dropped. 10: reserved 11: 11: To chec check k EA EAP_ P_BL BLK K MODE MODE on both both ingr ingres ess s and and egre egress ss port, only the frame defined in EAP_GCFG will be forwarded. The forwarding process will verify that each egress port is at block mode.

48

EAP_EN_DA

R/W

Enable EAP frame with DA

0

47:0

EAP_DA

R/W

EAP frame DA register

00-00-0000-00-00


Page 271


BCM53128 Data Sheet

Page 43h: MSPT Register

Page 43h: MSPT Register Table 235: Broadcast Storm Suppression Register (Page 43h) Address

Bits

Description

00h

8

“MSPT Control Register (Page 43h: Address 00h)”

01h

–

Reserved

02h–05h

32

“MSPT Aging Control Register (Page 43h: Address 02h)”

06h–0Fh

–

Reserved

10h–2Fh

32

“MSPT Table Regist Register er (Page 43h: Addres Address s 10h)” on page 273

30h–4Ah

–

Reserved

50h–51h

16

“SPT Multiport Address Bypass Control Register (Page 43h: Address 50h–51h)” 50h–51 h)” on page 274

52h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


MSPT Control Register (Page 43h: Address 00h) Table 236: MSPT Control Registers Registers (Page 43h: Address Address 00h–01h) BIt

Name

R/W

Description

Defaul t

7:1

Reserved

R/W

Reserved

0

0

EN_802.1S

R/W

0: Disable 1: Enable

0

MSPT Aging Control Register (Page 43h: Address 02h) Table 237: MSPT Aging Control Control Registers (Page 43h: Address 02h–05h) BIt

Name

R/W

Description

Defaul t

31:8

Reserved

R/W

Reserved

0

7: 0

MSPT_AGE_MAP

R/W

Per spanning tree aging enable

0


Page 272


BCM53128 Data Sheet


MSPT Table Register (Page 43h: Address 10h) Table 238: MSPT Table Register Register Address Address Summary Address

Description

10h–13h

MSPT 0

14h–17h

MSPT 1

18h–1Bh

MSPT 2

1Ch–1Fh

MSPT 3

20h–23h

MSPT 4

24h–27h

MSPT 5

28h–2Bh

MSPT 6

2Ch–2Fh

MSPT 7

Table 239: MSPT MSPT Table Registers (Page (Page 43h: Address 10h–2Fh) BIt

Name

R/W

Description

Defaul t

31:27

Reserved

RO

Reserved

0

26:24

Reserved

R/W

Reserved

0

23:21

Reserved

R/W

Sp Spanning tree state for port 7

0

20:18

Reserved

R/W


0

17:15

SPT_STA5

R/W

Sp S panning tree state for port 5

0

14:12

SPT_STA4

R/W

Spanning tree state for port 4 000 = No spanning tree 001 = Disabled 010 = Blocking 011 = Listening Listening 100 = Learning 101 = Forwarding

0

11:9

SPT_STA3

R/W


0

8:6

SPT_STA2

R/W


0

5:3

SPT_STA1

R/W


0

2:0

SPT_STA0

R/W


0


Page 273


BCM53128 Data Sheet


SPT Multiport Address Bypass Control Register (Page 43h: Address 50h–51h) Table 240: SPT Multiport Address Address Bypass Control Register Register (Page 43h: Address Address 50h–51h) BIt

Name

R/W

Description

Default

15:6

Reserved

RO

Reserved

–

5

EN_MPORT5_BYPAS ASS S_SP R/W R/W T

1: The The MPOR MPORT_ T_AD ADD_ D_5 5 of “Multiport “Multiport Address N – (N=0–5) Register (Page 04h: Address 10h)” on page 182 is 182 is not checked by SPT status. 0: The MPORT_ADD MPORT_ADD_5 _5 is checked checked by SPT status.

4


1: The The MPOR MPORT_ T_AD ADD_ D_4 4 of “Multiport “Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on page 182 is 182 is not checked by SPT status. 0: The MPORT_ADD_4 will be checked by SPT status.

3



2



1



0


1: The The MPOR MPORT_ T_AD ADD_ D_0 0 of “Multiport “Multiport Address N 0 (N=0–5) Register (Page 04h: Address 10h)” on page 182 is 182 is not checked by SPT status. 0: The MPORT_ADD MPORT_ADD_0 _0 is checked checked by SPT status.

–


Page 274


BCM53128 Data Sheet

Page 70h: MIB Snapshot Control Register

Page 70h: MIB Snapshot Control Register Table 241: MIB Snapshot Snapshot Control Control Register Register Address

Bits

Description

00h

8

“MIB Snapshot Control Register (Page 70h: Address 00h)”

01h–EFh

–

Reserved

F0h–F7h

8

“SPI Data I/O Register (Global, Address F0h)” on page 295 295 bytes bytes 0-7

F8h–FDh

–

Reserved

FEh

8


FFh

8


MIB Snapshot Control Register (Page 70h: Address 00h) Table 242: MIB Snapshot Snapshot Control Register Register (Page 70h: Address Address 00h) Bit

Name

R/W

Description

Default

7

SNAPSHOT_START/ DONE

R/W SC

Write Write 1'b1 1'b1 to initiat initiate e MIB snapsh snapshot ot access access,, clear clear to 0 1'b0 when MIB snapshot access is done

6

SNAPSHOT_MIRROR

R/W

1'b1: enable read address to port MIB, but data from MIB snapshot memory. 1'b0: enable to read from port MIB memory memory

0

5:4

Reserved

R/W

Reserved

0

3:0

SNAPSHOT_PORT

R/W

Port Number for MIB snapshot function

0

Page 71h: Port Snapshot MIB Control Register Table 243: Port Snapshot Snapshot MIB Control Control Register Register Address

Bits

Description

71h

–

The Port Snapshot MIB Registers are same as registers in “MII Control Register (Page 10h–17h: Address 00h–01h)” on page 196


Page 275


BCM53128 Data Sheet

Page 72h: Loop Detection Register

Page 72h: Loop Detection Register Table 244: Loop Detection Detection Control Register Register (Page 72h) Address

Bits

Description

00h–01h

16

“Loop Detection Control Register (Page 72h: Address 00h)”

02h

8

“Discovery Frame Timer Control Register (Page 72h: Address 02h)” on page 276

03h–04h

16

“LED Warnin Warning g Port Port Map Regis Register ter (Page 72h: Addre Address ss 03h)” on page 277

05h–0Ah

48

Module ID 0

0Bh–10h

48

Module ID 1

11h– 16h

48

Loop detect frame SA

17h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


Loop Detection Control Register (Page 72h: Address 00h) Table 245: Loop Detection Control Registers Registers (Page 72h: Address Address 00h–01h) BIt

Name

R/W

Description

Default

15:13

Reserved

R/W

Reserved

0

12

EN_L EN_LO OOP_DE P_DETE TEC CT

R/W

Enab Enable le loop loop dete detect ctio ion n featu eaturre. 0 = Disable 1 = Enable

Strap

11

LOOP_IMP_SEL

R/W

Enable IMP loop detection feature. 0 = Disable 1 = Enable

Strap

10:3 10:3

LED LED_RST _RST_T _TIM IMR R_CTR _CTR R/W L

Number Number of miss missed ed disc discove overy ry time time before before LED warning warning portmap to be reset.

0x4

2

OV_PAUSE SE_ _ON

1 = Transmit frame in high ighest queue even the port is in pause on state. 0 = Transmit frame follow the pause state rule.

0x1

1:0

DISCOVERY_FRAME R/W R/W _QUEUE_SEL

R/W

Spec Specif ifie ies s whic which h queu queue e to be put put for for the the rece receiv ived ed disc discov over ery y 0x1 frame.

Discovery Frame Timer Control Register (Page 72h: Address 02h) Table 246: Discovery Discovery Frame Timer Control Control Registers Registers (Page 72h: Address 02h) BIt

Name

R/W

Description

Default

7:4

Reserved

R/W

Reserved

0


Page 276


BCM53128 Data Sheet

Page 72h: Loop Detection Register

Table 246: Discovery Discovery Frame Timer Control Control Registers Registers (Page 72h: Address 02h) BIt

Name

R/W

3:0 3:0

Disc Discov over er_F _Fra rame me_T _Tim imer er R/W R/W

Description

Default

From From 1 seco second nd (def (defau ault lt)) to 15 seco second nds. s. Scale Scale = 1s. 1s. 0000 = 1s 0001 = 2s 0002 = 3s . . . 1110 = 15s

0

LED Warning Port Map Register (Page 72h: Address 03h) Table 247: LED Warning Warning Port Map Registers Registers (Page 72h: Address Address 03h–04h) BIt

Name

R/W

Description

Defaul t

15:9

Reserved

R/O

Reserved

0

8:0

LED_ ED_WARNING_POR R/O TMAP

Bit Bit 8: IMP IMP por port Bits [7:0] correspond to ports [7:0], respectively. Each bit shows the status of Loop Detected on the corresponding port.

0

Module ID 0 Register (Page 72h: Address 05h) Table 248: Module Module ID 0 Registers Registers (Page (Page 72h: Address 05h–0Ah) 05h–0Ah) BIt

Name

R/W

Description

Default

47:0

Module_ID_SA

RO

–

0


Page 277


BCM53128 Data Sheet

Page 88h: IMP Port External PHY MII Registers Page Summary

Module ID 1 Register (Page 72h: Address 0Bh) Table 249: Module Module ID 1 Registers Registers (Page (Page 72h: Address 0Bh–10h) 0Bh–10h) BIt

Name

R/W

47

Modu Module le_I _ID_ D_AV AVAI AILA LABL BLE E RO RO

Modu Module le ID is avai availa lable ble when when the the firs firstt pack packet et is rece receiv ived ed.. 0 0 = Unavailable 1 = Available

46:40

Reserved

Reserved

0

39:3 39:32 2

MODU MODULE LE_I _ID_ D_PO PORT RT_N _N RO O

This is an 8-bit port number for module ID.

0

31:0

MODULE_ID_CRC

This is an 32-bit CRC for module ID.

0

RO

RO

Description

Default

Loop Detect Source Address Register (Page 72h: Address 11h) Table 250: Loop Detect Source Source Address Registers Registers (Page 72h: Address 11h–16h) 11h–16h) BIt

Name

R/W

Description

Default

47:0

LD_SA

R/W

Loop detection frame SA

01-80-C2-00-00-01

Page Pa ge 88 88h: h: IM IMP P Po Port rt Ex Exte tern rnal al PH PHY Y MI MIII Re Regi gist ster ers s Pa Page ge Su Sum mma mary ry Table 251: IMP Port External External PHY MII MII Registers Page Summary Summary Address

Bits

Description

88h 88h

–

MII MII addr addres ess s from from 00h 00h to 0Ah 0Ah are are IEEE IEEE stan standa dard rd regi regist ster ers s and and the the desc descri ript ptio ions ns for for the the registers are “Page are “Page 10h–17h: Internal GPHY MII Registers” on page 194


Page 278


BCM53128 Data Sheet

Page 90h: BroadSync HD Register

Page 90h: BroadSync HD Register Table 252: BroadSync BroadSync HD Register Register Address

Bits

Description

00h–01h

16

“BroadSync HD Enable Control Register (Page 90h: Address 00h–01h)” on page 280

02h

8

“BroadSync HD Time Stamp Report Control Register (Page 90h: Address 02h)” on page 280

03h

8

“BroadSync HD PCP Value Control Register (Page 90h: Address 03h)” on page 280

04h–05h

8

“BroadSync HD Max Packet Size Register (Page 90h: Address 04h)” on page 281

06h–09h

–

Reserved

10h–13h

32

“BroadSync HD Time Base Register (Page 90h: Address 10h–13h)” on page 281

14h–17h

32

“BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17)” on page 281

18h–1Bh

32

“BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh)” 18h–1B h)” on page 282

1Ch–1Fh

32

“BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh)” on page 282

20h–2Fh

–

Reserved

30h–3Fh

16

“BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h)” on page 283

40h–5Fh

–

Reserved

60h–6Fh

16

“BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h)” on page 283

70h–8Fh

–

Reserved

90h–AFh

32

“BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h)” on page 284

B0h–CFh

–

Reserved

D0h

8

“BroadSync HD Egress Time Stamp Status Register (Page 90h: Address D0h)” on page 284

D1h–DFh

–

Reserved

E0h–E1h

16

“BroadSync HD Link Status Register (Page 90h: Address E0h–E1h)” on page 285

B2h–EFh

–

Reserved

F0h–F7h

8

“SPI Data I/O Register (Global, Address F0h)” on page 295 295 bytes bytes 0-7

F8h–FDh

–

Reserved

FEh

8


FFh

8



Page 279


BCM53128 Data Sheet


Broa Br oadS dSyn ync c HD En Enab able le Co Cont ntro roll Re Regi giste sterr (P (Pag age e 90h 90h:: Ad Addr dress ess 00h 00h–01 –01h) h) Table 253: BroadSync HD Enable Enable Control Register (Page 90h: Address 00h–01h) BIt

Name

R/W

Description

Default

15:8

Reserved

RO

Reserved

0

7:0

BroadSync HD Enable

R/W

BroadSync HD enable. Bits [7:0] correspond to ports [7:0]

0

BroadSync HD Time Stamp Report Control Register (Page 90h: Address Addre ss 02h) Table 254: BroadSync HD Time Stamp Report Control Control Register (Page 90h: Address 02h) BIt

Name

R/W

Description

Default

7:1

Reserved

RO

Reserved

0

0

TSRPT_PKT_EN

R/W

This field is to allow the Time Stamp Reporting 0 Packet to IMP port when the time synchronization packet transmitted on egress port.

BroadSync HD PCP Value Control Register (Page 90h: Address 03h) Table 255: BroadSync BroadSync HD PCP Value Control Control Register (Page (Page 90h: Address 03h) BIt

Name

R/W

Description

Default

7:6

Reserved

RO

Reserved

0

5:3

ClassB_PCP

R/W

BroadSync HD Class B PCP value. This field is used to qualify the PCP value of BroadSync HD packet. This BroadSync HD packet will be sent to Queue4.

3'd4

2:0

ClassA_PCP

R/W

BroadSync HD Class A PCP value. This field is used to qualify the PCP value of BroadSync HD packet. This BroadSync HD packet will be sent to Queue5.

3'd5


Page 280


BCM53128 Data Sheet


BroadSync HD Max Packet Size Register (Page 90h: Address 04h) Table 256: BroadSync BroadSync HD Max Packet Size Register Register (Page 90h: Address 04h) BIt

Name

R/W

Description

Default

15:12

Reserved

RO

Reserved

0

11:0

MAX_BroadSync HD_PACKET_SIZE

R/W

This This field field is is to define define the the max max packe packett size size of of Broad BroadSyn Sync c 12’d1518 HD. The ingress port uses it to qualify if the packet is allowed allowed to pass through a BroadSync BroadSync HD link. The egress prot uses it to perform perform shaping gate.

BroadSync HD Time Base Register (Page 90h: Address 10h–13h) Table 257: BroadSync BroadSync HD Time Base Register Register (Page 90h: Address 10h–13h) BIt

Name

R/W

Description

Default

31:0

TIME BASE

RO

Time Base 0 This is a 32-bit free running clock (running at 25 MHz) for BroadSync HD time base. Ingress port and Egress port use it for Time Synchronization Packet Time Stamp.

BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17) Table 258: BroadSync HD Time Time Base Adjustment Register Register (Page 90h: Address Address 14h–17h) BIt

Name

R/W

Description

Default

31:12

Reserved

RO

Reserved

0

11:8 11:8

TIME TIME ADJU ADJUST ST PE PER RIOD IOD R/W

Time Time Adju Adjus st Per Period iod 41. 4’h0 This field defines the tick numbers to apply the adjust adjusted ed Time Time Increm Increment ent (when (when Time Time Increm Increment ent does does not equal to 40). For example, to increment the Time Base for 10 ticks with with 41 ns per per tick tick,, Time Time Adju Adjust st Peri Period od is 10, 10, and and Time Time Increment is 41.

7:6

Reserved

RO

Reserved

5:0

TIME INCREMENT

R/W

Time Increment 6’d40 This field defines the value to add into Time Base in each 25-MHz tick. Default is 40.

0


Page 281


BCM53128 Data Sheet


BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh) Table 259: BroadSync HD Slot Number and Tick Counter Counter Register (Page 90h: Address 18h–1Bh) BIt

Name

R/W

Description

Default

31:28

Reserved

RO

Reserved

0

27:16

TICK COUNTER

R/W

12’h0 Tick Counter This is the tick counter which defines when will Slot Slot Numb Number er incr increm emen ent. t. It runs runs from from 1 to 3125 3125 (or (or 3124, or 3126, depends on “BroadSync on “BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh)” on page 282 282 setting) setting) under 25 MHz.

15:5

Reserved

RO

Reserved

0

4:0

SLOT NUMBER

R/W

This field specifies the Slot Number for BroadSync HD.

8’h0

BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch– 1Fh) Table 260: BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh) 1Ch–1Fh) BIt

Name

R/W

Description

Default

31:18

Reserved

RO

Reserved

0

17:16

MACRO SLOT PERIOD

R/W

Macro Slot Period 2’h0 This field defines the slot time of a macro slot for Class 4 traffic. 00 = 1 ms 01 = 2 ms 10 = 4 ms 11 = Reserved Class 5 traffic slot time is always 125s period.

15:12

Reserved

RO

Reserved

11:8

SLOT ADJUST PERIOD

R/W

Slot Adjust Period 8’h0 This This field field defi define nes s the the numb number er of slot slots s to appl apply y the the alterable slot adjustment.

7:2

Reserved

RO

Reserved

1:0

SLOT ADJUSTMENT

R/W

Slot Adjustment 2’h0 This field defines when the slot number counter increment by 1. Default is 40. 00 = Slot Number increased by 1 when tick counter rolls over 3125. 01 = 3126 10 = 3124 11 = Reserved

0

0


Page 282


BCM53128 Data Sheet


BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address Addre ss 30h) .

Table 261: BroadSync HD Class Class 5 Bandwidth Control Control Register Address Summary Summary Address

Description

30h–31h

Port 0

32h–33h

Port 1

34h–35h

Port 2

36h–37h

Port 3

38h–39h

Port 4

3Ah-3Bh

Port 5

3Ch–3Dh

Port 6

3Eh-3Fh

Port 7

Table 262: BroadSync HD Class 5 Bandwidth Control Control Register (Page 90h: Address 30h–31h, 32h–33h, 34h–35h, 36h–37h, 38h–39h) BIt

Name

R/W

Description

Default

15

C5_WI 5_WIND NDO OW

R/W

The The purp purpos ose e is to cont contro roll the the cred credit it car carryry-over over unde under r 1’b0 different link speed. For a 100M link, the 125-s slot is too small such that BroadSync HD packet could easily “slip slot”, so the credit carry-over should be allowed. For a 1G link, 125-s slot is reasonably big such that the BW reservation could be done in a conservative way to prevent “slot slipping”, so credit carry-over is not needed.

14

Reserved

RO

Reserved

13:0 13:0

C5_BA C5_BAND NDWI WIDT DTH H

R/W R/W

This This fiel field d defi define nes s the the byte byte coun countt allow allowed ed for for Clas Class s 5 traf traffi fic c 14’h0 transmission within a slot time.

0

BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address Addre ss 60h) .

Table 263: BroadSync HD Class 4 Bandwidth Control Control Register Address Summary Address

Description

60h–61h

Port 0

62h–63h

Port 1

64h–65h

Port 2

66h–67h

Port 3

68h–69h

Port 4

6Ah-6Bh

Port 5

6Ch–6Dh

Port 6

6Eh-6Fh

Port 7


Page 283


BCM53128 Data Sheet


Table 264: BroadSync HD Class 4 Bandwidth Control Control Register (Page 90h: Address 60h–61h, 62h–63h, 64h–65h, 66h–67h, 68h–69h) BIt

Name

R/W

Description

Default

15:14

Reserved

RO

Reserved

0

13:0

C4_BANDWIDTH

R/W

This field defines the byte count allowed for Class 4 traffic transmission within a slot time.

14’h0

BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h) .

Table 265: BroadSync HD Egress Egress Time Stamp Register Register Address Summary Address

Description

90h–93h

Port 0

94h–97h

Port 1

98h–9Bh

Port 2

9Ch–9Fh

Port 3

A0h–A3h

Port 4

A4h-A7h

Port 5

A8h–ABh

Port 6

ACh-AFh

Port 7

Table Table 266: 266: BroadS BroadSync ync HD Egress Egress Time Time Stamp Stamp Regist Register er (Page (Page 90h: 90h: Addres Address s 90h–93 90h–93h, h, 94h–97 94h–97h, h, 98h–9B 98h–9Bh, h, 9Ch–9Fh, A0h–A3h, A4h–A7h) BIt

Name

R/W

31:0 31:0

EGR EG RES ESS_ S_TS TS R

Description

Default

Egre Egress ss Time Time Sync Synchr hron onou ous s Pack Packet et Tim Time Stam Stamp p 32’h0 This field reports the time stamp of egress time synchronous packet. It uses 32-bit time base as time stamping. The time between the departure of first byte of MAC DA and the time stamping point should be constant.

BroadSync HD Egress Time Stamp Status Register (Page 90h: Address Addre ss D0h) Table 267: BroadSync BroadSync HD Egress Time Stamp Status Status Register (Page (Page 90h: Address D0h) BIt

Name

R/W

Description

Default

7:0

VALID STATUS

RO

Valid Status 8’h0 8-bit field indicating indicating the valid status for each “BroadSync each “BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h)” on page 284. 284. When “BroadSync When “BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h)” is 90h)” is read out by SPI, the valid status will be cleared, respectively.


Page 284


BCM53128 Data Sheet


BroadSync HD Link Status Register (Page 90h: Address E0h–E1h) Table 268: BroadSync BroadSync HD Link Status Status Register Register (Page (Page 90h: Address Address E0h–E1h) E0h–E1h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0

8:0

Port BroadSync HD Link Status

R/W R/W

9'h0 Broa BroadS dSyn ync c HD Link Link Stat Status us When software writes the port BroadSync HD link status and select bit 14 in LED Function Control Register. The BroadSync HD link status is shown on the LED. Bits [8:0] correspond to ports [8:0].


Page 285


BCM53128 Data Sheet

Page 91h: Traffic Remarking Register

Page 91h: Traffic Remarking Register Table 269: Traffic Traffic Remarking Remarking Register Register Address

Bits

Description

00h–03h

32

“Traffic Remarking Control Register (Page 91h: Address 00h)”

04h–0Fh

–

Reserved

10h-57h

32

“Egress Non-BroadSync HD Packet TC to PCP Mapping Register (Page 91h: Address 10h)” on page 287

58h–EFh

–

Reserved

F0h–F7h

8


F8h–FDh

–

Reserved

FEh

8


FFh

8


Traffic Remarking Control Register (Page 91h: Address 00h) Table 270: Traffic Remarking Control Control Register (Page (Page 91h: Address 00h) BIt

Name

R/W

Description

Default

31:25

Reserved

RO

Reserved

0

24:16

PCP_R P_REMARKING_EN

R/W

0 PCP Remarking Enable Bit 24: IMP port Bits[23:16] Bits[23:16] correspond correspond to ports [7:0], [7:0], respectivel respectively y

15:9

Reserved

R/W

Reserved

–

8:0

Reserved

R/W

Reserved

0


Page 286


BCM53128 Data Sheet

Page 91h: Traffic Remarking Register

Egress Non-BroadSync HD Packet TC to PCP Mapping Register (Page 91h: Address 10h) Table 271: Egress Non-BroadSync HD Packet Packet TC to PCP Mapping Register Address Summary Summary Address

Description

10h-17h

Port 0

18h-1Fh

Port 1

20h-27h

Port 2

28h-2Fh

Port 3

30h-37h

Port 4

38h-3Fh

Port 5

40h-47h

Port 6

48h-4Fh

Port 7

50h-57h

IMP

Table 272: Egress Egress Non-BroadSyn Non-BroadSync c HD Packet TC to PCP Mapping Register Register (Page 91h: Address Address 10h– 17h, 18h–1Fh, 20h–27h, 28h–2Fh, 30h–37h, 38h–3Fh, 50h-57h) Bit

Na Name

63:32

Reserved

31:28

R/W

Description

Default

R/W

Reserved

4'b1111

{CFI,PCP} for TC = 7

R/W

The {CFI,PCP} field for TC = 7

4'b0111

27:24


R/W


4'b0110

23:20


R/W


4'b0101

19:16


R/W


4'b0100

15:12


R/W


4'b0011

11:8


R/W


4'b0010

7:4


R/W


4'b0001

3:0


R/W


4'b0000


Page 287


BCM53128 Data Sheet

Page 92h: EEE Control Register

Page 92h: EEE Control Register Table 273: Page 92h: EEE Control Control Register Register Address

Bits

Description

00h-01h

16

“EEE Enable Control Register (Page 92h: Address 00h)”

02h-03h

16

“EEE LPI Asser Assertt Regis Register ter (Page 92h: Addre Address ss 02h)” on page 289

04h-05h

16

“EEE LPI Indic Indicate ate Regist Register er (Page 92h: Addres Address s 04h)” on page 289

06h-07h

16

“EEE RX Idle Symbo Symboll Regis Register ter (Page 92h: Addre Address ss 06h)” on page 289

0Ch-0Fh

32

“EEE Pipelin Pipeline e Timer Regis Register ter (Page 92h: Addre Address ss 0Ch) 0Ch)”” on page 290

10h-30h

32

“EEE Sleep Timer Gig Regist Register er (Page 92h: Addres Address s 10h)” on page 290

34h-54h

32

“EEE Sleep Timer FE Regis Register ter (Page 92h: Addre Address ss 34h)” on page 291

58h-78h

32

“EEE Min LP Timer Gig Regist Register er (Page 92h: Addres Address s 58h)” on page 291

7Ch-9Ch

32

“EEE Min LP Timer FE Regis Register ter (Page 92h: Addre Address ss 7Ch)” on page 292

A0h-B0h

16

“EEE Wake Timer Gig Regist Register er (Page 92h: Addres Address s A0h)” on page 292

B2h-C2h

16

“EEE Wake Timer FE Regis Register ter (Page 92h: Addre Address ss B2h)” on page 293

C4h

16

“EEE GLB Congs Congstt TH Regist Register er (Page 92h: Addres Address s C4h)” on page 293

C6h-D0h

16

“EEE TXQ Cong TH Regis Register ter (Page 92h: Addre Address ss C6h) C6h)”” on page 293

EEE Enable Control Register (Page 92h: Address 00h) Table 274: EEE Enable Enable Control Register Register (Page 92h: Address 00h) Bit

Name

R/W

Description

Default

15:9

Reserved

R/W

Reserved

0

8:0

EN_EEE

R/W

Enables EEE function per port 1 = Enable EEE 0 = Disable EEE Bit[8]: IMP port Bits [7 :0]: Ports [7:0]

–


Page 288


BCM53128 Data Sheet


EEE LPI Assert Register (Page 92h: Address 02h) Table 275: EEE LPI Assert Assert Register Register (Page 92h: Address Address 02h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0x0

8:0

LPI_Assert_Status

RO

Low Power assert inp input sign ignal status. 0x0 1 = Low Power asserted 0 = Low Power deasserted Bit [8]: IMP port Bits [7:0]: Ports [7:0] Each bit indicates that LowPowerAssert input signal that commands the transmit MAC to generate lowpowe powerr idle idle symb symbol ols s to the the PHY PHY afte afterr the the tran transm smit it MAC MAC completes transmitting inprocess packet data.

EEE LPI Indicate Register (Page 92h: Address 04h) Table 276: EEE LPI Indicate Indicate Register Register (Page 92h: Address 04h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0x033

8:0

LPI_Indicate

RO

Low Power Indicate output signal status. 0x0 1 = Low Power Indicate asserted 0 = Low Power Indicate deasserted Bit [8]: IMP port Bits [7:0]: Ports [7:0] Each bit indicates that LowPowerIndicate output signal is asserted asserted whenever the receive PHY is sending low-power idle symbols to the receive MAC.

EEE RX Idle Symbol Register (Page 92h: Address 06h) Table 277: EEE RX Idle Symbol Symbol Register Register (Page 92h: Address Address 06h) Bit

Name

R/W

Description

Default

15:9

Reserved

RO

Reserved

0x0

8:0

Rx_Idle_Symbol

RO

Receivin iving g IdleSymbols output sign ignal status. 0x0 1 = Idle Symbol output asserted 0 = Idle Symbol output deasserted Bit [8]: IMP port Bits [7:0]: Ports [7:0] Each bit indicates that receiving IdleSymbols output signal is asserted asserted whenever the received PHY is sending sending normal normal idle symbols symbols to the received MAC.


Page 289


BCM53128 Data Sheet


EEE Pipeline Timer Register (Page 92h: Address 0Ch) Table 278: EEE Pipeline Pipeline Timer Register Register (Page 92h: Address 0Ch) Bit

Name

R/W

Description

Default

31:0

Pipeline Timer

R/W

EEE pipeline delay timer load value. 0x20 The unit is system clock rate (e.g., if system clock = 100 MHz, unit = 10 nsec).

Table 279: EEE Sleep Sleep Timer Gig Register Register (Page 92h: Address Address 10h) Address

Description

10h – 13h

Port 0

14h – 17h

Port 1

18h – 1Bh

Port 2

1Ch – 1Fh

Port 3

20h – 23h

Port 4

24h – 27h

Port 5

28h – 2Bh

Port 6

2Ch – 2Fh

Port 7

30h – 33h

IMP

EEE Sleep Timer Gig Register (Page 92h: Address 10h) Table 280: EEE Sleep Sleep Timer Gig Register Register (Page 92h: Address Address 10h) Bit

Name

R/W

Description

Default

31:0 31:0

Slee Sleep p Time Timerr Gig

R/W

EEE slee EEE sleep p dela delay y time timerr load load valu value e for 1G oper operat atio ion. n. 0x4 The unit is 1  sec.

Table 281: EEE Sleep Sleep Timer FE Register Register (Page 92h: Address Address 34h) Address

Description

34h – 37h

Port 0

38h – 3Bh

Port 1

3Ch – 3Fh

Port 2

40h – 43h

Port 3

44h – 47h

Port 4

48h – 4Bh

Port 5

4Ch – 4Fh

Port 6

50h – 53h

Port 7

54h – 57h

IMP


Page 290


BCM53128 Data Sheet


EEE Sleep Timer FE Register (Page 92h: Address 34h) Table 282: EEE Sleep Sleep Timer FE Register Register (Page 92h: Address Address 34h) Bit

Name

R/W

Description

Default

31:0 31:0

Slee Sleep p Time Timerr FE

R/W

EEE slee EEE sleep p dela delay y time timerr load load valu value e for for 100M 100M oper operat atio ion. n. 0x28 The unit is 1  sec.

Table 283: EEE Min LP Timer Gig Register Register (Page 92h: Address Address 58h) Address

Description

58h – 5Bh

Port 0

5Ch – 5Fh

Port 1

60h – 63h

Port 2

64h – 67h

Port 3

68h – 6Bh

Port 4

6Ch – 6Fh

Port 5

70h – 73h

Port 6

74h – 77h

Port 7

78h – 7Bh

IMP

EEE Min LP Timer Gig Register (Page 92h: Address 58h) Table 284: EEE Min LP Timer Gig Register Register (Page 92h: Address Address 58h) Bit

Name

R/W

Description

Default

31:0

Min LP Timer G

R/W

EEE minimum low low-power duration delay lay timer loa load value for 1G operation. The unit is 1  sec.

0x32

Table 285: EEE Min LP Timer FE Register Register (Page 92h: Address Address 7Ch) Address

Description

7Ch – 7Fh

Port 0

80h – 83h

Port 1

84h – 87h

Port 2

88h – 8Bh

Port 3

8Ch – 8Fh

Port 4

90h – 93h

Port 5

94h – 97h

Port 6

98h – 9Bh

Port 7

9Ch – 9Fh

IMP


Page 291


BCM53128 Data Sheet


EEE Min LP Timer FE Register (Page 92h: Address 7Ch) Table 286: EEE Min LP Timer FE Register Register (Page 92h: Address Address 7Ch) Bit

Name

R/W

Description

Default

31:0 31:0

Min Min LP Time Timerr FE

R/W

EEE EE E mini minimu mum m low low-pow -power er dur duratio ation n dela delay y tim timer load load value for 100M operation. The unit is 1  sec.

0x1F4

Table 287: EEE Wake Timer Timer Gig Register (Page (Page 92h: Address A0h) Address

Description

A0h – A1h

Port 0

A2h – A3h

Port 1

A4h – A5h

Port 2

A6h – A7h

Port 3

A8h – A9h

Port 4

AAh – ABh

Port 5

ACh – ADh

Port 6

AEh – AFh

Port 7

B0h – B1h

IMP

EEE Wake Timer Gig Register (Page 92h: Address A0h) Table 288: EEE Wake Timer Timer Gig Register Register (Page 92h: Address A0h) A0h) Bit

Name

R/W

Description

Default

15:0 15:0

Wake Wake Time Timerr Gig

R/W

EEE EE E wake ake trans ransit itio ion n dela delay y timer imer load load valu value e for for 1G operation. The unit is 1  sec.

0x11

Table 289: EEE Wake Timer Timer FE Register (Page (Page 92h: Address B2h) Address

Description

B2h – B3h

Port 0

B4h – B5h

Port 1

B6h – B7h

Port 2

B8h – B9h

Port 3

BAh – BBh

Port 4

BCh – BDh

Port 5

BEh – BFh

Port 6

C0h – C1h

Port 7

C2h – C3h

IMP


Page 292


BCM53128 Data Sheet


EEE Wake Timer FE Register (Page 92h: Address B2h) Table 290: EEE Wake Timer Timer FE Register (Page (Page 92h: Address B2h) Bit

Name

R/W

Description

Default

15:0 15:0

Wake Wake Time Timerr FE

R/W

EEE EE E wake ake tran ransit sition ion dela delay y time timerr load load valu value e for for 100M 100M 0x24 operation. The unit is 1  sec.

EEE GLB Congst TH Register (Page 92h: Address C4h) Table 291: EEE GLB Congst Congst TH Register (Page (Page 92h: Address C4h) Bit

Name

R/W

Description

Default

15:11

Reserved

RO

Reserved

0x0

10:0

GLB_C B_CONG_TH

R/W

EEE Global packet buffer congestion threshold. If this 0x1a0 threshold is set to zero, then EEE is effectively disabled. If this threshold is set equal to or greater than 768 (the number of cells implemented in the packet buffer), then protections against packet loss are disable. The unit is “Buffer Cell Size”: 256-byte cell.

Table 292: EEE TXQ CONG CONG TH Register (Page (Page 92h: Address C6h) Address

Description

C6h

C7hEEE TXQ 0 CONG TH Register

C8h

C9hEEE TXQ 1 CONG TH Register

CAh

CBhEEE TXQ 2 CONG TH Register

CCh

CDhEEE TXQ 3 CONG TH Register

CEh

CFhEEE TXQ 4 CONG TH Register

D0h

D1hEEE TXQ 5 CONG TH Register

EEE TXQ Cong TH Register (Page 92h: Address C6h) Table 293: EEE TXQ Cong TH Register Register (Page 92h: Address Address C6h) Bit

Name

R/W

Description

Default

15:11

Reserved

RO

Reserved

0x0


Page 293


BCM53128 Data Sheet


Table 293: EEE TXQ Cong TH Register Register (Page 92h: Address Address C6h) Bit

Name

R/W

Description

10:0 10:0

GLB_C LB_CO ONG_TH G_TH

R/W

EEE TX EEE TXQ Q pack packet et buf buffer fer conge ongest stio ion n thr thresho eshold ld.. • If this this thre thresh shol old d is set set to zero zero,, then then EE EEE E for for que queue ue N is effectively disabled. • If this this thre thresh shol old d is set set equa equall to to or grea greate terr than than 768 768 (the number of cells implemented in the packet buffer), then protections against packet loss are disabled. The unit is “Buffer Cell Size”: 256-byte cell. EEE TXQ0: 0x64 EEE TXQ1: 0x64 EEE TXQ2: 0x64 EEE TXQ3: 0x1 EEE TXQ4: 0x1 EEE TXQ5: 0x1

Default


Page 294


BCM53128 Data Sheet

Global Registers

Global Registers Table 294: 294: Global Global Registers Registers (Maps to to All Pages) Pages) Address

Bits

Description

F0h

8

“SPI Data I/O Register (Global, Address F0h)” F0h)”,, 0

F1h

8

“SPI Data I/O Register (Global, Address F0h)” F0h)”,, 1

F2h

8

“SPI Data I/O Register (Global, Address F0h)” on page 295 295,, 2

F3h

8


F4h

8


F5h

8


F6h

8


F7h

8


F8–FDh

–

Reserved

FEh

8


FFh

8


SPI Data I/O Register (Global, Address F0h) Table 295: SPI Data I/O Register Register (Maps to All Registers, Address F0h–F7h) Bit

Name

R/W

Description

Default

7:0

SPI Data I/O

R/W

SPI data bytes [7:0]

0

SPI Status Register (Global, Address FEh) Table 296: SPI Status Status Register (Maps (Maps to All Registers, Registers, Address Address FEh) Bit

Name

R/W

Description

Default

7

SPIF

RO

SPI read/write complete flag

0

6

Reserved

RO

Reserved

0

5

RACK

RO (SC)

SPI read read data data ready ready acknow acknowled ledgem gement ent (self(self-cle cleari aring) ng)

0

4:2

Reserved

RO

Reserved

0

1

Reserved

RO

Reserved

0

0

Reserved

RO

Reserved

0


Page 295


BCM53128 Data Sheet

Global Registers

Page Register (Glob (Global, al, Addre Address ss FFh) Table 297: Page Register Register (Maps to All Registers, Registers, Address Address FFh) Bit

Name

R/W

Description

Default

7:0 7:0

PAGE PA GE_R _REG EG

R/W

The The bina binarry valu value e dete deterrmine mines s the the valu value e of the acc accesse essed d register page.

0


Page 296


BCM53128 Data Sheet

Electrical Characteristics

Section 8: Electrical Characteristics Absolute Maximum Ratings Table 298: Absolute Absolute Maximum Maximum Ratings Ratings Symbol

Parameter and Pins

Minimum

Maximum

Units

–

Supply voltage: PLL_AVDD, DVDD, AVDDL

GND–0.3

1.32

V

–

Supply voltage: OVDD2, AVDDH, OVDD, XTAL_AVDD

GND–0.3

3.63

V

II

Input current

–

–

mA

TSTG

Storage temperature

–40

+125

C

VESD

Electrostatic discharge

–

2000

V

–

Input voltage: di gital input pins

–

–

V

Note: These Note: These specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect long-term reliability of the device.

Recommended Operating Conditions Table 299: Recommended Operating Operating Conditions Symbol

Parameter

Pins

Minimum

Maximum Units

VDD

Supply voltage

AVDDL, DVDD, PLL_AVDD

1.14

1.26

V

OVDD2, AVDDH, XTAL_AVDD

3.14

3.47

V

–

–

–

V

–

–

–

V

VIH

High-level input voltage

All digital inputs

2.0

–

V

VIL

Low-level input voltage

All digital inputs

–

0.8

V

T A

Ambient operating temperature

–

0

70

C


Page 297


BCM53128 Data Sheet

Electrical Characteristics

Electrical Characte Characteristics ristics Table 300: Electrical Characteristics Symbo l Parameter IDD

Pins

Conditions

Minimum Typical Maximum Units

Estimated

–

1130

–

mA

Estimated

–

496

–

mA

Estimated

–

36

–

mA

Estimated

–

1130

–

mA

Estimated

–

496

–

mA

Estimated

–

26

–

mA

–

–

–

–

mA

Digital Digital output output pins pins at 3.3V IOH =  8 mA

2.1

–

–

V


2.0

–

–

V


1.1

–

–

V

Digital Digital output output pins pins at 3.3V IOL = 8 mA

–

–

0.5

V


–

–

0.4

V


–

–

0.4

V

Digital Digital input pins at 3.3V and 2.5V

–

1.7

–

–

V

Digital input pins at 1.5V

–

0.85

–

–

V

XTALI

–

2.0

–

–

V


–

–

–

0.9

V


–

–

–

0.7

V


–

–

–

0.65

V

XTALI

–

–

–

0.8

V

Digi Digita tall inpu inputs ts w/ pull-up resistors

–

–

–

–

µA

Digital inputs w/ pull-up resistors

–

–

–

–

µA

Digital inputs w/ pull-down resistors

–

–

–

–

µA

Digital inputs w/ pull-down resistors

–

–

–

–

µA

All other digital di gital inputs

–

–

–

–

µA

Maximum supply 1.2V power rail current (for GMII/ 3.3V power rail RvMII/MII OVDD (3.3V for GMII/ operation) RvMII/MII)

IDD

Maximum supply 1.2V power rail current current (for RGMII RGMII 3.3V power rail operation) 2.5V power rail 1.5V power rail

VOH High-level output voltage

VOL

VIH

VIL

II

Low-level output voltage

High-level input voltage

Low-level input voltage

Inpu Inputt curr curren entt


Page 298


BCM53128 Data Sheet

Timing Characteristics

Section 9: Timing Characteristics Reset and Clock Timing Figure 49: 49: Reset and and Clock Timing Timing

Power Rails

t104

t106 t103

t101 XTALI t102

t10 7

t10 8

RESET t105 t109 Configuration Strap Stra p Sign Signals als

Valid

Table 301: 301: Reset and and Clock Timing Timing Description

Parameter

Minimum

Typical

Maximum

XTALI period

t101

39.998 ns

40 ns

40.002 ns

XTALI high time

t102

18 ns

–

22 ns

XTALI low time

t103

18 ns

–

22 ns

RESET low pulse duration

t104

80 ms

100 ms

–

RESET rise time

t105

–

–

25 ns

Configuration valid setup to RESET rising

t107

100 ns

–

–

Configuration valid hold from RESET rising

t108

–

–

100 ns

Hardware initialization is complete. All the strap pin t109 t109 values are clocked in, and the internal registers can be accessed.

5 ms befo before re the the regi regist ster ers s can can be acce access ssed ed


Page 299


BCM53128 Data Sheet

MII Interface Timing

MII Interface Timing The following specifies timing information regarding the MII Interface pins.

MII Input Timing Figure 50: MII Input t402 t401

t404

t403

RXC (Input)

RXDV RXD

Table 302: 302: MII Input Input Timing Timing Parameter

Description

Min

Typ

Max

t401

RXDV, RXD, to RXC rising setup time

10 ns

–

–

t402

RXC clock period (10BASE-T mode)

–

400 ns

–

RXC clock period (100BASE-TX mode)

–

40 ns

–

RXC high/low time (10BASE-T mode)

160 ns

–

240 ns

RXC high/low time (100BASE-TX mode)

16 ns

–

24 ns

t404

RXDV, RXD, to RXC rising hold time

10 ns

–

–

–

Duty cycle

–

–

–

t403

MII Output Timing Figure Figure 51: MII Output Output Timing Timing

t405

t406

TXC  TXEN

TXD


Page 300


BCM53128 Data Sheet

TMII Interface Timing

Table 303: 303: MII Output Output Timing Timing Parameter

Description

Min

t405

TXC high to TXEN, TXD valid

t406

TXC high to TXEN, TXD invalid (hold)

Typ

Max

0 ns

–

25 ns

0 ns

–

–

TMII Interface Timing The following specifies timing information regarding the TMII Interface pins.

TMII Input Timing Figure Figure 52: TMII Input Input t402 t401

t404

t403

RXC (Input)

RXDV RXD

Table 304: 304: TMII Input Input Timing Timing Parameter

Description

Min

Typ

Max

t401

RXDV, RXD, to RXC rising setup time

5 ns

–

–

t402

RXC clock period (100BASE-TX mode)

–

20 ns

–

t403

RXC high/low time (100BASE-TX mode)

8 ns

–

12 ns

t404

RXDV, RXD, to RXC rising hold time

5 ns

–

–

–

Duty cycle

–

–

–


Page 301


BCM53128 Data Sheet

Reverse MII/TMII Interface Timing

TMII Output Timing Figure Figure 53: TMII Output Output Timing Timing

t406

t405 TXC  TXEN

TXD

Table 305: 305: TMII Output Output Timing Timing Parameter

Description

Min

t405

TXC high to TXEN, TXD valid

t406

TXC high to TXEN, TXD invalid (hold)

Typ

Max

0 ns

–

12.5 ns

0 ns

–

–

Reverse MII/TMII Interface Timing The following specifies timing information regarding the Reverse MII/TMII Interface pins.

Reverse MII/TMII Input Timing Figure Figure 54: Reverse Reverse MII Input Timing Timing

t402  t401 

t404 

t403 

RXC (Output)

RXDV RXD

Table 306: Reverse Reverse MII Input Timing Timing Description

Parameter

Min

Typ

Ma Max

Units

RXDV, RXD to RXC rising setup time

t401R

10

–

–

ns


Page 302


BCM53128 Data Sheet

Reverse MII/TMII Interface Timing

Table 306: Reverse Reverse MII Input Timing Timing Description

Parameter

Min

Typ

Ma Max

Units

RXC (output) clock period (10BASE-T mode)

t402R

–

400

–

ns

–

40

–

ns

160

–

240

ns

16

–

24

ns

0

–

–

ns

RXC clock period (100BASE-TX mode) RXC high/low time (10BASE-T mode)

t403R

RXC high/low time (100BASE-TX mode) RXDV, RXD to RXC rising hold time

t404R

Table 307: Reverse Reverse TMII Input Timing Timing Description

Parameter

Min

Typ

Ma Max

Units

RXDV, RXD to RXC rising setup time

t401R

7.5

–

–

ns

RXC (output) clock period

t402R

–

20

–

ns

RXC high/low time (10BASE-T mode)

t403R

8

–

12

ns

RXDV, RXD to RXC rising hold time

t404R

0

–

–

ns

Reverse MII Output Timing Figure Figure 55: Reverse Reverse MII Output Output Timing

t405 t40 5R

t407 t40 7R t408 t40 8R

TXC (Output)

t406R

TXEN

TXD

Table 308: Reverse Reverse MII Output Output Timing Description

Parameter

Min

Ty Typ

Max

Units

Output (TXD, TX_EN) setup to TXC rising

t405R

15

–

25

ns

Output (TXD, TX_EN) hold from TXC rising

t406R

11

–

–

ns

TXC clock period

t407R

–

40

–

ns

TXC high/low time

t408R

15

–

22

ns

Table 309: Reverse Reverse TMII Output Output Timing Description

Parameter

Min

Ty Typ

Max

Units

Output (TXD, TX_EN) setup to TXC rising

t405R

5

–

–

ns


Page 303


BCM53128 Data Sheet

RGMII Interface Timing

Table 309: Reverse Reverse TMII Output Output Timing Description

Parameter

Min

Ty Typ

Max

Units

Output (TXD, TX_EN) hold from TXC rising

t406R

5

–

–

ns

TXC clock period

t407R

–

20

–

ns

TXC high/low time

t408R

7.5

–

11

ns

RGMII Interface Timing The following specifies timing information regarding the IMP interface pins when configured in RGMII mode.

RGMII Output Timing (Normal Mode) Figure Figure 56: RGMII RGMII Output Timing Timing (Normal Mode) Mode)

GTX_CLK (at source )

TXD[3:0] TX_CTL t201

t201

Table 310: RGMII RGMII Output Timing Timing (Normal Mode) Mode) Description

Parameter

Min

Typ

Max

Units

GTX_CLK clock period (1000M mode)

–

7.2

8

8.8

ns


–

36

40

44

ns


–

360

400

440

ns

TskewT: data to clock output skew

t201

–500 (1000M) 0

+500 (1000M) ps

Duty cycle for 1000M (GE)

–

45

50

55

%

Duty cycle for 10/100M (FE)

–

40

50

60

%

Note: The Note: The output timing in 10/100M operation is always as specified in the delayed mode.


Page 304


BCM53128 Data Sheet


RGMII Output Timing (Delayed Mode) RGMII output timing defaults to the delayed mode when the TXC_DELAY pin is pulled high at power-on reset. Figure Figure 57: RGMII RGMII Output Timing Timing (Delayed (Delayed Mode)

GTX_CLK (internal) Delayed GTX_CLK (actual output o utput at source)

t201D

t202D

TXD[3:0] TX_CTRL t202D t201D

Table 311: RGMII RGMII Output Timing Timing (Delayed (Delayed Mode) Description

Parameter

Min

Typ

Max

Units


–

7.2

8

8.8

ns


–

36

40

44

ns


–

360

400

440

ns

TsetupT Data valid to clock transition: Available setup time at the output source (delayed mode)

t201D

1.2 (all speeds)

2.0

–

ns

TholdT Clock transition to data valid: Available hold time at the output source (delayed mode)

t202D

1.2

2.0

–

ns


–

45

50

55

%


–

40

50

60

%


Page 305


BCM53128 Data Sheet


RGMII Input Timing (Norm (Normal al Mode) Figure Figure 58: RGMII RGMII Input Timing (Normal (Normal Mode) Mode)

RXCLK

t301

t302 t301

t302

RXD[3:0] RX_CTRL

Table 312: RGMII RGMII Input Timing (Normal (Normal Mode) Description

Parameter

Min

Typ

Max

Units

RXCLK clock period (1000M mode)

–

7.2

8

8.8

ns


–

36

40

44

ns


–

360

400

440

ns

TsetupR Input setup time: valid data to clock

t301

1.0

2.0

–

ns

TholdR Input hold time: clock to valid data

t302

1.0

2.0

–

ns


–

45

50

55

%


–

40

50

60

%


Page 306


BCM53128 Data Sheet


RGMII Input Timing (Delaye (Delayed d Mode) RGMII Input Timing defaults to the delayed mode when the RXC_DELAY pin is pulled high at power-on reset. Figure Figure 59: RGMII RGMII Input Timing (Delayed (Delayed Mode)

RXCLK

Delayed RXCLK (Actual destination)

t302D t302D t301D

RXD[3:0] RX_CTRL t301D

Table 313: RGMII RGMII Input Timing (Delayed (Delayed Mode) Description

Parameter

Min

Typ

Max

Units

TsetupR Input setup time (delayed mode)

t301D

–1.0 (1000M)

–

–

ns

–1.0 (10/100M)

–

–

ns

TholdR Input hold time (delayed mode)

t302D

3.0 (1000M)

–

–

ns

9.0 (10/100M)

–

–

ns


Page 307


BCM53128 Data Sheet

GMII Interface Timing

GMII Interface Timing The following specifies timing information regarding the IMP interface pins when configured in GMII mode.

GMII Interface Outpu Outputt Timin Timing g Figure Figure 60: GMII Output Output Timings Timings

t502 GTX_CLK

TXEN

t501

TXD

Table 314: 314: GMII Output Output Timing Timing Description

Parameter

Min

Typ

Max

Units


–

7.5

8

8.5

ns

Output (TXD, TX_EN) setup to GTX_CLK rising

t501

2.5

–

–

ns

Output (TXD, TX_EN) hold from GTX_CLK rising

t502

0.5

–

5.5

ns

GMII Interface Input Timin Timing g Figure 61: 61: GMII Input Input Timings Timings

t503 t504 RXCLK

RXDV

RXD


Page 308


BCM53128 Data Sheet

MDC/MDIO Timing

Table 315: 315: GMII Input Input Timing Timing Description

Parameter

Min

Typ

Max

Units


–

–

8

–

ns

(RXD, RX_DV) Setup to RX_CLK rising t503

2.0

–

–

ns

(RXD, RX_DV) Hold from RX_CLK rising

0.0

–

–

ns

t504

MDC/MDIO Timing The following specifies timing information regarding the MDC/MDIO interface pins. Figure Figure 62: MDC/MDIO MDC/MDIO Timing Timing (Slave Mode) t401

t402

MDC t402

MDIO (Into PHY)

t403

t404

MDIO (From PHY) t405

Table 316: MDC/MDIO MDC/MDIO Timing Timing (Slave Mode) Mode) Description

Parameter

Minimum Typical

Maximum Unit

MDC cycle time

t401

80

–

–

ns

MDC high/low

–

30

–

–

ns

MDC rise/fall time

t402

–

–

10

ns

MDIO input setup time to MDC rising

t403

7.5

–

–

ns

MDIO input hold time from MDC rising

t404

7.5

–

–

ns

MDIO output delay from MDC rising

t405

0

–

45

ns

Table 317: MDC/MDIO Timing (Master Mode) Description

Parameter

Minimum Typical

Maximum Unit

MDC cycle time

t401

400

–

–

ns

MDC high/low

–

160

–

240

ns


Page 309


BCM53128 Data Sheet

Serial LED Interface Timing

Table 317: MDC/MDIO Timing (Master Mode) Description

Parameter

Minimum Typical

Maximum Unit

MDC rise/fall time

t402

–

–

10

ns

MDIO input setup time to MDC rising

t403

80

–

–

ns

MDIO input hold time from MDC rising

t404

0

–

–

ns

MDIO output delay from MDC rising

t405

15

–

90

ns

Serial LED Interface Timing The following specifies timing information regarding the LED interface pins. Figure Figure 63: Serial Serial LED Interface Interface Timing t301 t302 t304 t303 LEDCLK

LEDDATA

S0

S1

SN

S2

S0

t305

Table 318: Serial Serial LED Interface Interface Timing Description

Parameter

Minimum Typical

Maximum Unit

LED update cycle period

t301

–

42

–

ms

LEDCLK period

t302

–

320

–

ns

LEDCLK high-pulse width

t303

150

–

170

ns

LEDCLK low-pulse width

t304

150

–

170

ns

LEDCLK to LEDDATA output time

t305

140

–

180

ns


Page 310


BCM53128 Data Sheet

SPI Timings

SPI Timings Figure 64: SPI Timings, Timings, SS Asserted Asserted During SCK High

t601 t603

t602

t604

SCK t608 = 20 ns SS

t607 = 10 ns

MOSI

t605

t606

MISO

Note: Advanced Note: Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.

Table 319: 319: SPI Timings Timings Description

Parameter

Minimum

Typical

Maximum

SCK clock period

t601

40 ns

500 ns

–

SCK high/low time

t602

20 ns

–

–

MOSI to SCK setup time

t603

5 ns

–

–

MOSI to SCK hold time

t604

5 ns

–

–

SCK to MISO valid

t605

–

–

13 ns

/SS to MISO invalid

t606

–

–

10 ns

Time interval from assert of /SS to beginning the operation of SCK

t607

10 ns

–

–

20 ns

–

–

Time Time inter interva vall from from oper operat atio ion n end end of SCK SCK to t608 de-assert of /SS


Page 311


BCM53128 Data Sheet

EEPROM Timing

EEPROM Timing Figure Figure 65: EEPROM EEPROM Timing Timing

t701 t701 t702 t7 02

SCK

t703 t703

SS

t704 t704

MISO t705 t7 05

t706 t70

MOSI

Table 320: 320: EEPROM EEPROM Timing Timing Description

Parameter

Minimum

Typical

Maximum

SCK clock frequency

t701

–

200 kHz

–

SCK high/low time

t702

–

2.5  s

–

MISO to SCK rising setup time

t703

50 ns

–

–

MISO to SCK rising hold time

t704

10 ns

–

–

SCK low to SS, MOSI valid time

t705

30 ns

–

100 ns

SCK low to SS, MOSI invalid time

t706

30 ns

–

–


Page 312


BCM53128 Data Sheet

Serial Flash Timing

Serial Flash T iming Figure Figure 66: Serial Serial Flash Timing Timing

Table 321: 321: Serial Serial Flash Timing Timing Description

Parameter

Minimum

Typical

Maximum

FSCLK clock frequency

t801

–

22.72 MHz

50 MHz

FSI to FSCLK rising setup time

t802

10 ns

–

–

FSI to FSCLK rising hold time

t803

0 ns

–

–

FSCLK to FSO delay

t804

5 ns

–

FSCLK cycle time - 5 ns

The falling edge of FCSB to first rising edge t805 of FSCLK

5 ns

–

–

The The last last risi rising ng edge edge of FSCLK FSCLK to risin rising g edge edge t806 of FCSB

5 ns

–

–


Page 313


BCM53128 Data Sheet

Thermal Characteristics

Section 10: Thermal Characteristics Note: The Note: The maximum allowed junction temperature is 125 ºC. Table ºC. Table 322 and 322 and Table Table 323 on page 314 show the estimated junction temperature with heat sink.

Table 322: BCM53128K BCM53128KQLE QLE Package Package without Heat Sink, 4-Layer 4-Layer Board, P = 3.1W Device Device power power dissip dissipati ation, on, P (W)

3.1

Ambient air temperature Ta (ºC)

70

JA

is still air (ºC/W)

17.48

JB

(ºC/W)

0.98

JC

(ºC/W)

14.12 Package Thermal Performance Data

Air Velocity

TJ_max

T T

JA

JT

JB

m/s

ft/min

(ºC)

(ºC)

(ºC/W)

(ºC/W)

(ºC/W)

0

0

124.19

122.86

17.48

0.43

9.35

0.508

100

118.59

117.26

15.67

0.43

9.38

1.016

200

115.70

114.25

14.74

0.47

9.44

2.032

400

112.74

111.07

13.79

0.54

9.46

3.048

600

111.10

109.01

13.26

0.68

9.40

Table 323: BCM53128K BCM53128KQLE QLE Package Package with Heat Sink, 2-Layer Board, P = 3.1W Device Device power power dissip dissipati ation, on, P (W)

3.1


70

JA


16.22

JB

(ºC/W)

0.98

JC

(ºC/W)

14.12

External heat sink

Heat sink: 28 mm x 28 mm x 15 mm, k = 180 (W/m*k), aluminium blade-fin. Thermal interface: Loctite 384, 0.1 mm thick, k = 0.757 W/m-k Package Thermal Performance Data

Air Velocity

TJ_max

T T

JA

JT

JB

m/s

ft/min

(ºC)

(ºC)

(ºC/W)

(ºC/W)

(ºC/W)

0

0

120.29

96.93

16.22

7.53

10.10

0.508

100

112.94

88.80

13.85

7.79

9.89

1.016

200

111.07

86.80

13.25

7.83

9.85

2.032

400

109.30

85.00

12.68

7.84

9.85


Page 314


BCM53128 Data Sheet

Thermal Characteristics

Table 323: BCM53128K BCM53128KQLE QLE Package Package with Heat Sink, 2-Layer Board, P = 3.1W 3.048

600

108.40

84.00

12.39

7.87

9.82

Table 324: BCM53128IQLE Package Package with Heat Sink, Sink, 4-layer Board, P=3.1W P=3.1W Device Device power power dissip dissipati ation, on, P (W)

3.1


85

JA


12.60

JB

(ºC/W)

0.98

JC

(ºC/W)

14.12

External heat sink

Heat sink: 28 mm x 28 mm x 15 mm, k = 180 (W/m*k), aluminium blade-fin. Thermal interface: Loctite 384, 0.1 mm thick, k = 0.757 W/m-k Package Thermal Performance Data

Air Velocity

TJ_max

T T

JA

JT

JB

m/s

ft/min

(ºC)

(ºC)

(ºC/W)

(ºC/W)

(ºC/W)

0

0

124.07

106.76

12.6

5.58

7.16

0.508

100

118.36

100.33

10.76

5.81

7.03

1.016

200

116.69

98.55

10.22

5.85

7.03

2.032

400

114.97

96.84

9.67

5.85

7.03

3.048

600

114.25

96.12

9.43

5.85

7.02


Page 315


BCM53128 Data Sheet

Mechanical Information

Section 11: Mechanical Information Figure 67: BCM53128 Mechanical Mechanical Specifications Specifications


Page 316


BCM53128 Data Sheet

Ordering Information

Section 12: Ordering Information Table 325: Ordering Ordering Information Information Part Number

Package

Ambient Temperature

BCM53128KQLE(G)

256 eLQFP

0°C to 70°C

BCM53128IQLE(G)

256 eLQFP

–45°C to 85°C

Note: (G) Note: (G) represents the lead-free package option.


Page 317


BCM53128 Data Sheet

Broadcom® reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Inform Informati ation on furnis furnished hed by Broadc Broadcom om is believ believed ed to be accurat accurate e and reliab reliable.Howeve le.However, r, Broadc Broadcom om does does not assume assume any liabil liability ity arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

Broadcom Web: www.broadcom.com Corporate Headquarters: San Jose, CA © 2016 by Broadcom. All rights reserved. 53128-DS07-R

April 6, 2016

BCM53128

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