Schematic Diagrams
Syst ystem em Block Bloc k Diagram Diagram CLICK BOARD
Calpella Sys Sys te tem m Blo ck Diagr am
6-71-E51Q2-D01A
POWER SWITCH BOARD
POWER GPU
POWER SWITCH+HOTKEY X 3 6-71-E51QS-D01A
Clock Generator RTM875N-632-VB-GRT
AUDIO A UDIO BOAR BOARD D
Arrandal Arran dale e PROCESSOR rPGA989/988
USB+EARPHONE+EXT.MIC 6-71-C4508-D02A
EXTERNAL ODD BOARD EXT. ODD 6-71-E51QN-D01
s m a r g a i D c i t a m e h c S . B
VDD3,V V DD3,VDD DD5 5
14.318 MHz
5V,3V,5VS,3VS,1.5VS,
800/1067 MHz DDR3 / 1.5V
DDRIII SO-DIMM0
SYSTEM SMBUS DDRIII SO-DIMM1
0.1"~13
SHEET 11
FDI HDMI
Sheet 1 of 42 System Block Diagram
CLICK BOARD
<8" LVDS SWITCH
Ibex Peak-M Platform Controller Hub (PCH)
INTERNAL GRAPHICS
SPI
AZALIA MDC MODULE
TPM
128pins LQFP
27x27mm 1071 10 71 Ba ll FC BG BGA A AZALI AZALIA A LINK
LPC 0.5"~11" INT. K/B
BIOS SPI SP I
EC SMBUS
PCIE THERMAL SENSOR W83 W 83L7 L771 71AW AWG G
SMART FAN
SMART BATTERY
SATA I/II 3.0Gb/s
HP OUT
INT SPK R AMP
Azalia Azal ia Cod odec ec VIA VI A VT VT18 1812 12
N7101 INT SPK L
MDC M DC CO CON N
33 MHz
14*14*1.6mm
MIC IN
RJ-11
32.768 KHz
EC ITE 8502E
1.1VS_V 1.1VS _VTT TT
AUDI AU DIO O BO BOAR ARD D INTERNAL GRAPHICS
Synaptic LCD CONNECTOR,
VCORE V CORE
<=8"
<15" CRT SWITCH
810602-1703
1.5V,0.75VS(VTT_MEM)
DMI*4
0.5"~6.5"
CRT CONNECTOR
TOUCH PAD
1.8VS
Memory Memo ry Termination
100 MHz
INT MIC
24 MHz <12"
32.768KHz
USB2.0 480 Mbps
<12"
New Car New ard d SOCKET (USB3)
3G CARD (USB9)
Mini PCI CIE E SOCKET (USB2)
JMICRO
JMC251 C LAN LA N
CARD READER
25 MHz MHz
1"~16"
RJ-45
SATA HDD
SATA ODD
USB0
USB1
USB4
Bluetooth (USB11)
AUDIO AUDI O BOARD
http://hobi-elektronika.net B - 2 System Blo ck Diagram
CCD (USB5)
7IN1 SOCKET
Schematic Diagrams
Clock Generator CLKGEN POWER
CLOCK GENERATOR CL K _ V CC 1
CL K_ V CC 2
3 .3 V S CL K _ VCC1
U7 1 5 17 24 29
R 13 4
15 CL K_ BU F _ R E F 14
3 3_ 0 4
XO UT XIN
27 28
REF _ 0 /CP U_ S EL
30
CL K _ SDAT A CL K _ SCL K
31 32
VD D_ DO T VD D_ 2 7 VD D _ S RC VD D_ CPU VD D_ REF
D OT _ 96 DO T_ 9 6# 27M 2 7 M_ SS
XT AL _O UT XT AL _IN
R E F _ 0/C P U_ S E L
2 8 9 12 21 26 33
V DD_ S R C_ I/O V DD_ CP U_ I/O
SD A SC L
S RC _1 /SA T A S RC_ 1 #/S ATA# S RC _2 S R C_ 2#
CP U_ S T OP#
VS S _D OT VS S _2 7 VS S _SA T A VS S _SR C VS S _C PU VS S _R EF GN D
CPU _1 CP U _ 1# CPU _0 CP U _ 0# CK P W RGD /P D#
15 18
L15
3 4
C LK _B U F _D OT 9 6_ P 1 5 C LK _B U F _D OT 9 6_ N 15
C2 0 5
C 19 7
C2 07
0 .1u _ 1 6V _ Y5 V _ 0 4
0 .1 u_ 1 6 V _Y 5V _ 0 4
1u _ 6.3 V _ X5R _0 4
* 15 m i _l s ho rt_ 0 6
6 7
0.1uF near the every power pin
10 11 13 14
16
C LK _S AT A 1 5 C LK _S AT A# 1 5 C LK _P C IE_ ICH 1 5 C LK _PC IE_ ICH# 1 5
CP U _S T O P #
R 1 48
2. 2 1 K _1 _1 % _ 04
20 19 23 22 25
3 .3 V S
1 .1 V S_V TT C LK _V C C2 L 14
C LK _B U F _B CL K _P 15 C LK _B U F _B CL K _N 1 5
C2 06
C1 9 6
0.1 u _ 16 V_ Y 5 V _ 04
1 u_ 6 .3 V _X 5 R_ 0 4
* 1 5 m i l _ s h o r t _0 _0 6
CL K _ P W RG D
VD D_I/ O can b e rangin g from 1.05V to 3.3V
3 .3 V S
SL G 8S P5 8 5
Sl ego SLG8SP5 SLG8SP585 85 6- 02-0 8585- EQ0 Real tek RTM875N- 632- VB- GRT
R 14 9 1 0 K_1 % _ 04
Sheett 2 of 42 Shee Clock Generator
0.1uF near the every power pin
D
SMBus
36
CL KE N #
Q1 2
R 14 6
MT N7 00 2 Z HS3
1 M_ 0 4
G S
Q1 1A MT DN 70 0 2Z H S6 R
EMI EM I
2
D 15
S CL K _ SCL K
SMB _ CL K 6
CL K _ S CL K 1 0 ,11
6- 22-1 4R31- 1B7 6- 22-1 4R31- 1B6
1
G
3 .3V S X1
5 VS
1 2
4 3
RN 15 2 .2K _ 4 P 2 R_ 04
2
XI N
HS X5 30 G_ 1 4 .31 8 18 M Hz 1
X OUT
R E F _ 0/C P U_ S EL
C 1 94
* 1 0 p _5 0 V _ N P O _ 0 6
G 3
15
4
SMB _ DAT A
D
CL K _ SDAT A
CL K _ S DA T A 1 0 ,11
S
C1 99
C 20 2
33 p _50 V_ NP O_ 0 4
3 3 p_ 5 0 V _N PO _ 0 4
EMI Capactior
5
Q1 1B MT DN 70 0 2Z H S6 R
CPU_SEL_During CK_PEWGD Latch Pinl
3 .3V S
P IN _ 3 0 R 13 6
*4 . 7 K _0 _0 4
R 13 7
1 0K _ 0 4
CPU_0
C P U_ 1
0(default)
133MHz
133MHz
1(0.7V-1.5V)
100MHz
100MHz
RE F _0 /CP U _ S EL
5VS 1 3 ,17 ,2 0,2 0,2 1 ,2 6,2 6,2 7 ,3 0,3 1 ,35 ,3 6 3.3 V 3 ,4 ,12 ,1 4,1 5 ,1 6,1 8 ,1 9,2 0 ,21 ,2 3 ,24 ,2 5 ,29 ,3 0, 31 ,3 3,3 4 ,3 5 3.3 VS 1 0 ,11 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 ,18 ,1 9 ,20 ,2 1 ,23 ,2 4,2 5 ,2 6,2 7 ,2 8,2 9 ,30 ,3 1 ,35 ,3 6 1.1 VS _ VT T 4 ,6 ,7 ,14 ,1 5 ,16 ,1 9, 20 ,2 1,3 4 ,3 5,3 6
http://hobi-elektronika.net Clock Ge Generator nerator B - 3
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
Clock Generator CLKGEN POWER
CLOCK GENERATOR CL K _ V CC 1
CL K_ V CC 2
3 .3 V S CL K _ VCC1
U7 1 5 17 24 29
R 13 4
15 CL K_ BU F _ R E F 14
3 3_ 0 4
XO UT XIN
27 28
REF _ 0 /CP U_ S EL
30
CL K _ SDAT A CL K _ SCL K
31 32
VD D_ DO T VD D_ 2 7 VD D _ S RC VD D_ CPU VD D_ REF
D OT _ 96 DO T_ 9 6# 27M 2 7 M_ SS
XT AL _O UT XT AL _IN
R E F _ 0/C P U_ S E L
2 8 9 12 21 26 33
V DD_ S R C_ I/O V DD_ CP U_ I/O
SD A SC L
S RC _1 /SA T A S RC_ 1 #/S ATA# S RC _2 S R C_ 2#
CP U_ S T OP#
VS S _D OT VS S _2 7 VS S _SA T A VS S _SR C VS S _C PU VS S _R EF GN D
CPU _1 CP U _ 1# CPU _0 CP U _ 0# CK P W RGD /P D#
15 18
L15
3 4
C LK _B U F _D OT 9 6_ P 1 5 C LK _B U F _D OT 9 6_ N 15
C2 0 5
C 19 7
C2 07
0 .1u _ 1 6V _ Y5 V _ 0 4
0 .1 u_ 1 6 V _Y 5V _ 0 4
1u _ 6.3 V _ X5R _0 4
* 15 m i _l s ho rt_ 0 6
6 7
0.1uF near the every power pin
10 11 13 14
16
C LK _S AT A 1 5 C LK _S AT A# 1 5 C LK _P C IE_ ICH 1 5 C LK _PC IE_ ICH# 1 5
CP U _S T O P #
R 1 48
2. 2 1 K _1 _1 % _ 04
20 19 23 22 25
3 .3 V S
1 .1 V S_V TT C LK _V C C2 L 14
C LK _B U F _B CL K _P 15 C LK _B U F _B CL K _N 1 5
C2 06
C1 9 6
0.1 u _ 16 V_ Y 5 V _ 04
1 u_ 6 .3 V _X 5 R_ 0 4
* 1 5 m i l _ s h o r t _0 _0 6
CL K _ P W RG D
VD D_I/ O can b e rangin g from 1.05V to 3.3V
3 .3 V S
SL G 8S P5 8 5
Sl ego SLG8SP5 SLG8SP585 85 6- 02-0 8585- EQ0 Real tek RTM875N- 632- VB- GRT
R 14 9 1 0 K_1 % _ 04
Sheett 2 of 42 Shee Clock Generator
0.1uF near the every power pin
D
SMBus
36
CL KE N #
Q1 2
R 14 6
MT N7 00 2 Z HS3
1 M_ 0 4
G S
Q1 1A MT DN 70 0 2Z H S6 R
EMI EM I
2
D 15
S CL K _ SCL K
SMB _ CL K 6
CL K _ S CL K 1 0 ,11
6- 22-1 4R31- 1B7 6- 22-1 4R31- 1B6
1
G
3 .3V S X1
5 VS
1 2
4 3
RN 15 2 .2K _ 4 P 2 R_ 04
2
XI N
HS X5 30 G_ 1 4 .31 8 18 M Hz 1
X OUT
R E F _ 0/C P U_ S EL
C 1 94
* 1 0 p _5 0 V _ N P O _ 0 6
G 3
15
4
SMB _ DAT A
D
CL K _ SDAT A
CL K _ S DA T A 1 0 ,11
S
C1 99
C 20 2
33 p _50 V_ NP O_ 0 4
3 3 p_ 5 0 V _N PO _ 0 4
EMI Capactior
5
Q1 1B MT DN 70 0 2Z H S6 R
CPU_SEL_During CK_PEWGD Latch Pinl
3 .3V S
P IN _ 3 0 R 13 6
*4 . 7 K _0 _0 4
R 13 7
1 0K _ 0 4
CPU_0
C P U_ 1
0(default)
133MHz
133MHz
1(0.7V-1.5V)
100MHz
100MHz
RE F _0 /CP U _ S EL
5VS 1 3 ,17 ,2 0,2 0,2 1 ,2 6,2 6,2 7 ,3 0,3 1 ,35 ,3 6 3.3 V 3 ,4 ,12 ,1 4,1 5 ,1 6,1 8 ,1 9,2 0 ,21 ,2 3 ,24 ,2 5 ,29 ,3 0, 31 ,3 3,3 4 ,3 5 3.3 VS 1 0 ,11 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 ,18 ,1 9 ,20 ,2 1 ,23 ,2 4,2 5 ,2 6,2 7 ,2 8,2 9 ,30 ,3 1 ,35 ,3 6 1.1 VS _ VT T 4 ,6 ,7 ,14 ,1 5 ,16 ,1 9, 20 ,2 1,3 4 ,3 5,3 6
http://hobi-elektronika.net Clock Ge Generator nerator B - 3
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
CPU 5/7 (Graphics Power) PROCESSOR VG F X_ CO RE
s m a r g a i D c i t a m e h c S . B
9 . 5 * 6 . 6 * 6 . 6 _ V 5 . 2 _ u 0 6 5 +
( GRAPHICS POWER )
U 1 6G
C364
C 34 9
1 0 u _ 6. 3V _ X5 R _ 0 6
1 0 u _6 .3 V_ X5 R _0 6
C 3 50
C3 6 2
2 2 u _ 6. 3V _X5 R _ 08
2 2 u_ 6 .3 V_ X5 R_ 0 8
1 7 3 C
Sheet 7 of 42 CPU 5/7 (Graphics Power)
5/7
Please note that the VTT Rail Values are Auburndale VTT=1.05V Clarksfield VTT=1.1V
1 .1 VS_ VT T C3 1 4
C3 0 8
22 u _ 6 .3 V_ X5 R_ 0 8
22 u _ 6 .3 V_ X5 R_ 0 8
AT 2 1 AT 1 9 AT 1 8 AT 1 6 AR 2 1 AR 1 9 AR 1 8 AR 1 6 A P2 1 A P1 9 A P1 8 A P1 6 AN 2 1 AN 1 9 AN 1 8 AN 1 6 AM 2 1 AM 1 9 AM 1 8 AM 1 6 AL 2 1 AL 1 9 AL 1 8 AL 1 6 A K2 1 A K1 9 A K1 8 A K1 6 AJ 2 1 AJ 1 9 AJ 1 8 AJ 1 6 AH 2 1 AH 1 9 AH 1 8 AH 1 6
J24 J23 H25
VAXG 1 VAXG 2 VAXG 3 VAXG 4 VAXG 5 VAXG 6 VAXG 7 VAXG 8 VAXG 9 VAXG 1 0 VAXG 1 1 VAXG 1 2 VAXG 1 3 VAXG 1 4 VAXG 1 5 VAXG 1 6 VAXG 1 7 VAXG 1 8 VAXG 1 9 VAXG 2 0 VAXG 2 1 VAXG 2 2 VAXG 2 3 VAXG 2 4 VAXG 2 5 VAXG 2 6 VAXG 2 7 VAXG 2 8 VAXG 2 9 VAXG 3 0 VAXG 3 1 VAXG 3 2 VAXG 3 3 VAXG 3 4 VAXG 3 5 VAXG 3 6
VT T 1 _ 45 VT T 1 _ 46 VT T 1 _ 47
E S S E N N E I S L
VAXG _ SEN SE VSSAXG _ SEN SE
GF X_ VI D[0 ] GF X_ VI D[1 ] GF X_ VI D[2 ] GF X_ VI D[3 ] GF X_ VI D[4 ] GF X_ VI D[5 ] GF X_ VI D[6 ]
s D I V
G R A P H I C S
S C I H P A R G
G F X_ VR _E N G F X_ DP RSL PV R GF X_ IM O N
S L I A R
F D I
R E W O P
V 5 . 1 3 R D D
AR2 2 AT 2 2
AM2 2 AP2 2 AN2 2 AP2 3 AM2 3 AP2 4 AN2 4
AR2 5 AT 2 5 AM2 4
GP UVC C SEN SE 3 5 G P U V S S S E N S E 35
DF DF DF DF DF DF DF
GT GT GT GT GT GT GT
GF XVR _ D PRS LP VR T P_ GF X_ IM ON
_ VID _ VID _ VID _ VID _ VID _ VID _ VID
_ _ _ _ _ _ _
0 1 2 3 4 5 6
R 36 1 R 45
3 3 3 3 3 3 3
5 5 5 5 5 5 5 1 .1 VS_ VT T
D F GT_ VR _ EN 3 5
* 1K _ 0 4 1 00 _ 1 % _ 0 4
GF X_ IM O N 3 5
1. 5V S_ CP U
V DD Q1 V DD Q2 V DD Q3 V DD Q4 V DD Q5 V DD Q6 V DD Q7 V DD Q8 V DD Q9 VDD Q1 0 VDD Q1 1 VDD Q1 2 VDD Q1 3 VDD Q1 4 VDD Q1 5 VDD Q1 6 VDD Q1 7 VDD Q1 8
VT T 0 _5 9 VT T 0 _6 0 VT T 0 _6 1 VT T 0 _6 2
AJ 1 AF 1 AE 7 AE 4 AC1 AB 7 AB 4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
VDDQ 6A C5 5
C3 3 6
C330
C6 1
C5 8
1u _ 6 .3 V_ X5 R_ 0 4
2 2 u_ 6 .3 V_ X5 R_ 0 8
2 2 u _ 6. 3V _ X5 R _ 08
10 u _ 6 .3 V_ X5 R_ 0 6
1 0 u_ 6 .3 V_ X5 R_ 0 6
C3 4 1
C3 4 3
C39
C6 0
1u _ 6 .3 V_ X5 R_ 0 4
1 u _6 .3 V_ X5 R _0 4
1 u _ 6 .3 V_ X5R _ 0 4
1u _ 6 .3 V_ X5 R_ 0 4
+C5 3 10 0 u _ 6 .3 V_ B_ A
1 .1 VS _V TT
P1 0 N1 0 L1 0 K1 0
C3 2 0
C6 4
10 u _ 6 .3 V_ X5 R_ 0 6
1 0 u_ 6 .3 V_ X5 R_ 0 6
1 .1 VS_ VT T
1 .1 VS_ VT T C3 0 6
C3 0 7
22 u _ 6 .3 V_ X5 R_ 0 8
22 u _ 6 .3 V_ X5 R_ 0 8
1 .1 VS _V T T
C3 0 9 C3 9 6 0 .0 1u _ 5 0 V_ X7 R _ 0 4
C3 5 1 0. 01 u _ 5 0 V_ X7R _ 0 4
22 u _ 6 .3 V_ X5 R_ 0 8
C3 0 2
K2 6 J27 J26 J25 H27 G28 G27 G26 F26 E2 6 E2 5
VT T 1 _ 48 VT T 1 _ 49 VT T 1 _ 50 VT T 1 _ 51 VT T 1 _ 52 VT T 1 _ 53 VT T 1 _ 54 VT T 1 _ 55 VT T 1 _ 56 VT T 1 _ 57 VT T 1 _ 58
22 u _ 6 .3 V_ X5 R_ 0 8
P E G
V 1 . 1
&
VT T 1 _6 3 VT T 1 _6 4 VT T 1 _6 5 VT T 1 _6 6 VT T 1 _6 7 VT T 1 _6 8
D M I
J2 2 J2 0 J1 8 H2 1 H2 0 H1 9
C3 1 5
C3 1 3
22 u _ 6 .3 V_ X5 R_ 0 8
2 2 u_ 6 .3 V_ X5 R_ 0 8
C4 1
C3 7
C38
C52
C56
C5 4
1u _ 6 .3 V_ X5 R_ 0 4
1 u _6 .3 V_ X5 R _0 4
2 .2 u _ 1 6V _ X5 R _ 06
4 .7 u _ 6 .3 V _ X5 R _ 0 6
1 0 u _ 6 .3V _ X5 R _ 0 6
10 u _ 6 .3 V_ X5 R_ 0 6
1 .8 VS
V 8 . 1
VC CP LL 1 VC CP LL 2 VC CP LL 3
L2 6 L2 7 M2 6
VCCPLL 0.6A
PZ 98 9 2 7 -3 6 41 -0 1 F
1 .5 VS _ CPU 1 . 8V S V GF X_ C OR 1 .1 VS _ VT T 1 .5 V
http://hobi-elektronika.net B - 8 CPU 5/7 (Graphic s Power)
4 ,3 1 2 0 , 33 E 35 2 ,4, 6, 14 ,1 5,1 6 ,1 9 ,2 0 ,21,3 4 ,3 5 ,3 6 4 ,9 ,1 0 ,1 1,2 1 ,2 3 ,2 7 ,2 9 ,3 1, 33 ,3 6
Schematic Diagrams
CPU 6/7 (GND) PROCESSOR
6/7
( GND )
U16H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS1 0 VSS1 1 VSS1 2 VSS1 3 VSS1 4 VSS1 5 VSS1 6 VSS1 7 VSS1 8 VSS1 9 VSS2 0 VSS2 1 VSS2 2 VSS2 3 VSS2 4 VSS2 5 VSS2 6 VSS2 7 VSS2 8 VSS2 9 VSS3 0 VSS3 1 VSS3 2 VSS3 3 VSS3 4 VSS3 5 VSS3 6 VSS3 7 VSS3 8 VSS3 9 VSS4 0 VSS4 1 VSS4 2 VSS4 3 VSS4 4 VSS4 5 VSS4 6 VSS4 7 VSS4 8 VSS4 9 VSS5 0 VSS5 1 VSS5 2 VSS5 3 VSS5 4 VSS5 5 VSS5 6 VSS5 7 VSS5 8 VSS5 9 VSS6 0 VSS6 1 VSS6 2 VSS6 3 VSS6 4 VSS6 5 VSS6 6 VSS6 7 VSS6 8 VSS6 9 VSS7 0 VSS7 1 VSS7 2 VSS7 3 VSS7 4 VSS7 5 VSS7 6 VSS7 7 VSS7 8 VSS7 9 VSS8 0
U16I
VSS
PZ98 927-3 641-0 1F
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9
VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233
Sheet 8 of 42 CPU 6/7 (GND)
VSS
F T C N
VSS_NC TF1 VSS_NC TF2 VSS_NC TF3 VSS_NC TF4 VSS_NC TF5 VSS_NC TF6 VSS_NC TF7
AT35 AT1 AR34 B34 B2 B1 A35
PZ9 8927- 3641- 01F
http://hobi-elektronika.net CPU 6/7 (GND) B - 9
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
CPU 7/7 (RESERVED) PROCESSOR
7/7
( RESERVED ) 1 .5 V
U1 6 E RS V D3 2 RS V D3 3
PCI - Express Conf igurati on Sel ect
CFG0
s m a r g a i D c i t a m e h c S . B
CFG0
1 : Singl e PEG 0 : Bi f urcati on enable R 22 7
* 3 . 01 K _ 0 4
R 35 R 39
1 0 MVR EF _ D Q_ DI M0 1 1 MVR EF _ D Q_ DI M1
*0 _ 04 *0 _ 04
VR E F _ C H_ A _ DI MM VR E F _ C H_ B _ DI MM
CFG3 - PCI- Expr ess St ati c Lane Reversal
Sheet 9 of 42 CPU 7/7 (RESERVED)
CFG3 CFG3
C F G0
C F G3 C F G4
C F G7
0 : Enabled; An external Di spl ay Por t devi ce i s connected t o the E m bedded ispl ay Por t
R 22 0
* 3 . 01 K _ 0 4
S S S S S S S S S S S S S S
VD VD VD VD VD VD VD VD VD VD VD VD VD VD
1 2 3 4 5 6 7 8 9 1 1 1 1 1
RS V D3 4 RS V D3 5 RS V D3 6 R SV D _ NC TF _3 7 RS V D3 8 RS V D3 9 0 1 2 3 4
R 211
*0 _ 0 4
R SVD8 6
A M3 0 A M2 8 A P3 1 A L3 2 A L3 0 A M3 1 A N2 9 A M3 2 A K3 2 A K3 1 A K2 8 A J2 8 A N3 0 A N3 2 A J3 2 A J2 9 A J3 0 A K3 0 H1 6
B1 9 A1 9 CFG7
R 22 4
* 3 . 01 K _ 0 4 R 20 5 R 20 4
*1 5 m il _ s h ort _0 6 *1 5 m il _ s h ort _0 6
H _R S VD 1 7_ R H _R S VD 1 8_ R
A2 0 B2 0 U9 T9 AC 9 AB 9
C1 A3
J2 9 J2 8 A3 4 A3 3 C3 5 B3 5
A L2 6 AR 2
Q8 *A O 3 4 0 2L S D
* 1 K_ 1% _ 0 4 MV R EF _ D Q_ DIM 0
R 2 12 G * 1 00 K _ 1 % _ 0 4
R3 7 * 1 K_ 1% _ 0 4
A J2 6 A J2 7
R SV D _ NC TF _4 0 R SV D _ NC TF _4 1
DR A MR ST _ CT R L 4,1 9
AP1 A T2 1 .5 V A T3 AR 1
C C C C C C C C C C C C C C C C C C R
F G [0] F G [1] F G [2] F G [3] F G [4] F G [5] F G [6] F G [7] F G [8] F G [9] F G [10 ] F G [11 ] F G [12 ] F G [13 ] F G [14 ] F G [15 ] F G [16 ] F G [17 ] S VD _ TP _8 6
D E V R E S E R
R R R R
SV SV SV SV
D D D D
_ _ _ _
RS V D4 5 RS V D4 6 RS V D4 7 RS V D4 8 RS V D4 9 RS V D5 0 RS V D5 1 RS V D5 2 RS V D5 3 NC TF _5 4 NC TF _5 5 NC TF _5 6 NC TF _5 7 RS V D5 8
R S VD _ TP _5 9 R S VD _ TP _6 0 K EY RS V D6 2 RS V D6 3 RS V D6 4 RS V D6 5
A L2 8 A L2 9 A P 30 A P 32 A L2 7 A T3 1 A T3 2 A P 33 A R3 3 A T3 3 A T3 4 A P 35 A R3 5 A R3 2
E 15 F 15 A2 D15 C15 A J1 5 A H1 5
V R E F _ C H _ B _ D IM M
R3 8
Q9 *A O 3 4 0 2L S D
* 1 K_ 1% _ 0 4 MV R E F _ D Q_ D IM 1
R 2 14 * 1 00 K _ 1 % _ 0 4 G
R4 0 * 1 K_ 1% _ 0 4 DR A MR ST _ CT R L 4,1 9
? ? IBEX CONTROL
RSV D6 4 _R RSV D6 5 _R
R 2 17 R 2 18
*1 5 m i _l s h o rt _ 06 *1 5 m i _l s h o rt _ 06
R S VD 1 5 R S VD 1 6 R S VD 1 7 R S VD 1 8 R S VD 1 9 R S VD 2 0 R S VD 2 1 R S VD 2 2
R S VD _ NC TF _2 3 R S VD _ NC TF _2 4
R S VD 2 6 R S VD 2 7 R S VD _ NC TF _2 8 R S VD _ NC TF _2 9 R S VD _ NC TF _3 0 R S VD _ NC TF _3 1
R R R R R R R R R R
S S S S S S S S S S
VD VD VD VD VD VD VD VD VD VD
_ _ _ _ _ _ _ _ _ _
TP TP TP TP TP TP TP TP TP TP
_6 _6 _6 _6 _7 _7 _7 _7 _7 _7
6 7 8 9 0 1 2 3 4 5
R R R R R R R R R R
S S S S S S S S S S
VD VD VD VD VD VD VD VD VD VD
_ _ _ _ _ _ _ _ _ _
TP TP TP TP TP TP TP TP TP TP
_7 _7 _7 _7 _8 _8 _8 _8 _8 _8
6 7 8 9 0 1 2 3 4 5
AA5 AA4 R8 AD 3 AD 2 AA2 AA1 R9 AG 7 AE3
V4 V5 N2 AD 5 AD 7 W 3 W 2 N3 AE5 AD 9
A P 34 V SS
PZ 9 89 2 7 -3 6 41 -0 1 F
1.5 V
http://hobi-elektronika.net B - 10 CPU 7/7 (RESERVED)
V R E F _ CH _ A_ DIM M
? ? IBEX CONTROL
RSV D86 Connect t o GND
CFG7 Cl ar k sf i el d ( o nl y f or e a r l y s ampl es pre- ES1) - Connect to GND wi t h 3.01K Ohm/ 5% r e si s t or
R3 6
A H2 5 A K 26
AP23 02GN
* 3 . 01 K _ 0 4
1 : Di sabl led; No physi cal Displ ay Por t att ached to Embedded Dis pl ay Port
CFG4
R R R R R R R R R R R R R R
R SV D _ NC TF _4 2 R SV D _ NC TF _4 3
CFG4 - Di spl ay Por t Pr esence
CFG4
A P2 5 A L2 5 A L2 4 A L2 2 A J3 3 AG 9 M2 7 L2 8 J1 7 H1 7 G2 5 G1 7 E3 1 E3 0
1 : Normal Operat i on 0 : Lane Numbers Rever sed 15 - > 0, 14 - > 1, . . . R 22 1
AP2302GN A J1 3 A J1 2
4 ,1 0, 11 ,2 1 ,2 3 ,2 7,2 9 ,3 1 ,3 3, 36
TP _R S VD 8 6
VSS (AP34) can be left NC is CRB implementation ; EDS/DG recommendation to GND
Schematic Diagrams
LVDS, Inverter 3 .3 VS
EDID Mode
PANEL CONNECTOR VIN
2 1
3 RN6 4 2 .2 K_ 4P2 R _0 4
VIN _L CD
L 25
J _ LC D1
80m ils
* 1 5 m il _ s ho r t _ 06
C3 0 0
C2 9 7
0 .1 u_ 5 0V _Y 5V _0 6
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
C2 9 4
0 .1 u_ 5 0V _Y 5V _0 6
0. 1u _ 50 V_ Y5 V_ 0 6
CLOSE TO LVDS CONN. PIN
17 17
LVD S-L CL KN L VDS-L CL KP
17 17
L VDS-L 1 N L VD S -L 1P
17 17
L VDS-L 0 N L VD S -L 0P
LVD S-L CL KN LVD S-L CL KP LVD S-L 1 N LVD S-L 1 P LVD S-L 0 N LVD S-L 0 P
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 87 2 1 6-3 0 0 6
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
P_ DD C_ DAT A P_ DD C_ CL K BRI GHT N ESS
BRIG HT NESS
P_ D DC_ D ATA 17 P_ D DC_ C LK 17
28
INV_ BL ON LVD S-L 2N LVD S-L 2P
LVD S-L 2N 1 7 LVD S-L 2P 17 3.3 VS
C 2 91 0 .1 u _1 6 V_ Y5 V _ 04
PLVD D C4
C6
4.7 u _ 6.3 V_ X5R _ 06
0 .1 u _1 6 V_ Y5 V _ 04
Sheet 12 of 42 LVDS, Inverter
PANEL POWER
3 .3V S
2A
R 16
*1 5 m il _ s ho rt_ 0 6
C1 5 C1 7
0 .1 u_ 1 6 V_Y 5 V _0 4
3 .3V
*0 .01 u _ 50 V_ X7R _ 04 D1 5
PL VDD U1 4 5
VI N VI N
1
VO UT
C
2A
BRIG HT NESS
AC
C2 9 0 *0 .1 u_ 1 6 V_Y 5 V_0 4
A *BAV 9 9 REC TIF IE R
3
1 7 NB_ ENAV DD
2 EN
R1 3
GN D APL 3 51 2 A
10 0 K_ 1% _ 0 4
G5243A 6- 02- 05243- 9C0 APL3512A 6- 02-03512-9C0
INVERTER CONNECTOR 28
BKL _E N
R6 8
* 1 0 m il _ s ho r t _ 04
BKL _ EN_ R
R 67
C90
*1 0 0 K_ 1% _ 04
* 0 .47 u _ 10 V_ Y5 V _ 0 4
3.3 V 4 1
1
3.3 V U3 A 7 4L VC 08 PW 3
1 7 BL ON
4 1
Z 1 2 01
C8 9
4
2
BL ON
3. 3V
U 3B 7 4 LVC 0 8PW 6
*0 .1 u _1 6 V_ Y 5 V_ 04
5 7
R 69
7
1 0 0K_ 1 % _0 4
4 1
19
SB_B LO N
Z 1 2 02
2 8,3 0
L ID_ SW #
8
1 0 0K _ 1 % _ 0 4
IN V_BL O N
Z 1 2 03 1 0 4 1
1 6,2 8 AL L _SY S_ PW RG D
U 3C 7 4 LVC 0 8PW
9
3.3 V R7 0
U 3D 7 4 LVC 0 8PW
12 11
7
R71
C9 3
1 M _0 4
0 .1u _ 1 6V_ Y 5V_ 0 4
13 7
3 0, 31 ,3 2 ,33 ,3 4 , 35 ,3 6 ,37 3 ,4 ,1 4,1 5 , 1 6,1 8 ,1 9,2 0 ,2 1, 23 ,2 4, 25 ,2 9 ,30 ,3 1 ,33 ,3 4 , 35 2 ,1 0,1 1 ,1 3,1 4 ,1 5,1 6 ,1 7,1 8 ,1 9,2 0 ,2 1,2 3 ,2 4, 25 ,2 6, 27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,36 3 1 ,32
VIN 3 .3 V 3 .3 VS SY S15 V
http://hobi-elektronika.net LVDS, Invert er B - 13
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
IBEXPEAK - M 3/9 IBEXPEAK - M (DMI,FDI,GPIO) U2 0 C
1 .1 V S _ V T T
R 26 1
3 3 3 3
D MI_ RX N 0 D MI_ RX N 1 D MI_ RX N 2 D MI_ RX N 3
3 3 3 3
D MI_ R X P 0 D MI_ R X P 1 D MI_ R X P 2 D MI_ R X P 3
3 3 3 3
DM I _ TXN 0 DM I _ TXN 1 DM I _ TXN 2 DM I _ TXN 3
3 3 3 3
DM I_ TX P 0 DM I_ TX P 1 DM I_ TX P 2 DM I_ TX P 3 49 . 9 _ 1 %_ 0 4
B C 24 B J 22 A W 20 B J 20 B D 24 B G 22 B A 20 B G 20
D MI0 R XP D MI1 R XP D MI2 R XP D MI3 R XP
B E 22 B F 21 B D 20 B E 18
D MI 0 T X P D MI 1 T X P D MI 2 T X P D MI 3 T X P
B H 25
R R R R R R R R
XN XN XN XN XN XN XN XN
0 1 2 3 4 5 6 7
RX P 0 RX P 1 RX P 2 RX P 3 RX P 4 RX P 5 RX P 6 RX P 7
BA18 B H1 7 B D1 6 BJ16 BA16 BE14 BA14 B C1 2 B B1 8 BF17 B C1 6 B G1 6 AW16 B D1 4 BB14 B D1 2
F F F F F F F F
DI DI DI DI DI DI DI DI
_TX _TX _TX _TX _TX _TX _TX _TX
N0 N1 N2 N3 N4 N5 N6 N7
3 3 3 3 3 3 3 3
F F F F F F F F
DI DI DI DI DI DI DI DI
_T X _T X _T X _T X _T X _T X _T X _T X
P0 P1 P2 P3 P4 P5 P6 P7
3 3 3 3 3 3 3 3
BJ14
I I D M D F
D MI_ Z C OM P
B F 25
DI_ DI_ DI_ DI_ DI_ DI_ DI_ DI_
F D I_ F D I_ F D I_ F D I_ F D I_ F D I_ F D I_ F D I_
D MI 0 T X N D MI 1 T X N D MI 2 T X N D MI 3 T X N
B D 22 B H 21 B C 20 B D 18
DMI _C OM P _ R
F F F F F F F F
D MI0 R XN D MI1 R XN D MI2 R XN D MI3 R XN
F D I_IN T 3
F D I_IN T BF13
F D I_FS Y N C0 3
F DI_ F S Y N C 0 B H1 3
F D I_FS Y N C1 3
F DI_ F S Y N C 1
D MI_ IR CO MP
BJ12
F D I_L S Y NC 0 3
F D I_ LS Y NC 0 B G1 4
3.3 V S
R 11 1
1 0 K _ 04
S Y S _ RE S E T #
T6
S Y S _ P W R OK
M6
S B _ PW RO K
B 17
S Y S _ RE S E T #
W AKE#
S Y S _ P W R OK
C L K RU N# / GP IO3 2
t n e m eS US _S TA T# / GP IO6 1 M E P W R OK g a n S USC L K / GP IO6 2 L A N _ RS T # a M D RA M P W R OK r S LP _ S5 # / GP I O6 3 e w R S MR S T # SLP_S4# o P S US _ P W R _A CK / G P IO3 0 m SLP_S3# e t P W RB T N # S L P _M # s y S A CP R E S ENT / G P IO 31 TP23
Sheet 16 of 42 IBEXPEAK - M 3/9
F D I_L S Y NC 1 3
F D I_ LS Y NC 1
J 12
P CIE _W A K E #
Y1
P M_ C LK RUN #
P8
S 4 _S TA T E #
P C IE _W A K E # 2 3,2 5 P M _C L K RU N#
24 3 .3 V
P W RO K P M_ MP W RO K
R 29 7
A UX P P W R O K _ R
10 K _ 0 4
R S MR S T#
D9
1 8,2 8
C 16
RS M RS T# 10 K _ 0 4
R 30 0
S U S _P W R_ A C K
28 S U S _ P W R_ A C K
28
A 10
EXT-LAN
4 P M_ DR A M _PW RG D
28
K5
P W R _B T N #
P W R _B T N #
M1
P5 P7
A C _P R E S E N T
A C _P R E S E N T
P M_ B A T L OW #
A6
28
S W I#
S W I#
* 10 K _ 0 4
S W I#
R 13 0
1 0K _0 4
S US _ P W R _ A CK
R 28 4
1 0K _0 4
P W R_ B T N #
R 10 9
* 10 K _ 0 4
A C_ P R E S E NT
R 11 5
1 0K _0 4
P M_ B A T L OW #
R 29 6
8 . 2 K _0 4
P M _C L K RU N#
R 27 1
8 . 2 K _0 4
A L L _ S Y S _ PW R G D
R 14 3
1 0K _0 4
E4 H7 S US C # P12
S US B #
SUSB#
2 8 ,33 2 3 ,28 , 3 1
3 .3 V S
K8 N2
F6 RI #
1 K _ 1% _ 0 4
R 12 7
S 4 _ STA TE # 2 4
H_ P M _ S YN C 4
P M S Y N CH
F 14
R 12 1
P M_ S L P _ L A N#
F3
BJ10 B A TL O W # / GP IO 7 2
P CIE _ W A K E #
S L P _ LA N #
P M_ S L P _ L A N# 2 8, 36
Ibe x P e a k- M_ Re v 0 _ 9
V C OR E _ ON
R1 3 9
*1 0 m il _ s ho rt_ 0 4
P M_ M P W RO K
3 .3 V 3 .3 V 3.3 V
3 .3V U8 A 7 4 L V C0 8 P W
4 1
33
DD R 1 .5 V _ PW R GD SUSB#
4 1
4 3 3 1.8 V S _ PW RGD
1
3
U8 B 74 L V C 08 P W 6
4 1
4 ,3 3,3 4 1 .1 V S _ V T T_ P W R GD 1 .1 V S _ V T T_ E N
9
U 8C 7 4 LV C0 8 P W
4 1
12 4 ,3 6 DE L A Y _ P W RG D
8
U8 D 7 4 LV C 0 8P W 11
13
A L L_ SY S _ P W RG D
S B _P W RO K
*1 0 m il _ s ho rt_ 0 4
S Y S _ PW R OK
R1 4 5
7 7
A L L _ SY S _ P W R GD
7 7
*1 0 m il _ s ho rt_ 0 4
R1 4 2
10
5
2
R1 4 4
10 K _ 0 4
1 2 ,28
34 1 .1 V S _ V T T _E N R 14 1
2K _1 % _ 04
H_ V T T P W R GD
4
C 4 70
ON
R 13 8 1 u _ 6.3 V _ X 5 R _ 0 4 1 K _ 1% _ 0 4
3 .3V S 2 ,10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 7 ,1 8,1 9 ,2 0, 21 ,2 3 ,2 4,2 5 ,2 6, 27 ,2 8 ,29 ,3 0 ,3 1,3 5 ,3 6 3 .3V 3 ,4,1 2 ,1 4 ,15 ,1 8 ,1 9,2 0 ,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3 ,3 4,3 5 1 .1V S _V TT 2 ,4 ,6 ,7, 14 ,1 5 ,19 ,2 0 ,2 1,3 4 ,3 5 ,36
http://hobi-elektronika.net IBEXPEAK - M 3/9 B - 17
B . S c h e m a t i c D i a g r a m s
Schematic Diagrams
IBEXPEAK - M 4/9 IBEXPEAK - M (LVDS,DDI) U20D 12 BLON 12 NB_ENAVDD
12 P_DDC_CLK 12 P_DDC_DATA
3.3VS
s m a r g a i D c i t a m e h c S . B
R 96 R 97
* 10K_04 * 10K_04
L _CTRL_CLK L _CTRL_DATA
R83
2.3 7K_ 1% _04
L VDS_ I BG
T48 T47 L_BKLTEN L_VDD_EN Y48 L_BKLTCTL
BJ46 SDVO_ TVCLKI NN BG46 SDVO_TVCLKINP BJ48 SDVO_STALLN BG48 SDVO _STALLP BF45 SDVO_INTN BH45 SDVO_INTP
AB48 Y45 L_DDC_CLK L_DDC_DATA AB46 V48 L_CTRL_CLK L_CTRL_DATA AP39 AP41 LVD_IBG LVD_VBG
T51 SDV O_CTRLCLK T53 SDVO_CTRLDATA
AT43 AT42 LVD_VREFH LVD_VREFL 12 LVDS-LCLKN 12 LVDS-LCLKP
Sheet 17 of 42 IBEXPEAK - M 4/9
12 LVDS-L0N 12 LVDS-L1N 12 LVDS-L2N
12 LVDS-L0P 12 LVDS-L1P 12 LVDS-L2P
DAC_BLUE
13 DAC_GREEN 13 DAC_RED
R105
0_04
DAC_BLU E_R
*33p_50V_NPO_04
R99
0_04
DAC_GREEN_R
*33p_50V_NPO_04
R91
0_04
DAC_RED_R
C174
AY51 AT48 LVDSB_DATA0 AU50 LVDSB_DATA1 AT51 LVDSB_DATA2 LVDSB_DATA3
C170 C166 *33p_50V_NPO_04
NEAR PCH
R1 04 R9 8 R9 2
150_1% _04 150_1%_04 150_1%_04
DAC_BLUE_R DAC_GREEN_R DAC_RED_R
13 DAC_DDCACLK 13 DAC_DDCADATA
13 13 R8 8
1K_ 1%_04
S D V L
AP48 AP47 LVDSB_CLK# LVDSB_CLK AY53 AT49 LVDSB_DATA#0 AU52 LVDSB_DATA#1 AT53 LVDSB_DATA#2 LVDSB_DATA#3
EMI 13
AV53 AV51 LVDSA_CLK# LVDSA_CLK BB47 BA52 LVDSA_DATA#0 AY48 LVDSA_DATA#1 AV47 LVDSA_DATA#2 LVDSA_DATA#3 BB48 BA50 LVDSA_DATA0 AY49 LVDSA_DATA1 AV48 LVDSA_DATA2 LVDSA_DATA3
DAC_HSYNC DAC_VSYNC DA C_IREF_R
AA52 AB53 CRT_BLUE AD53 CRT_GREEN CRT_RED
e c a f r e t n I y a l p s i D l a t i g i D
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
Y53 Y51 CRT_HSYNC CRT_VSYNC
T R C
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38
B t r o P RN5 2.2K_4P2R_0 4 3 2 4 1
BE44 DDPC _AUX N BD44 DDPC_AUXP AV40 DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
O V D S
y a l p s i D
3.3VS
Y49 DDPC_CTRLCLK AB49 DDPC_CTRLDATA
DDPD_CTRLCLK DDPD_CTRLDATA
V51 V53 CRT_DDC_CLK CRT_DDC_DATA
AD48 AB51 DAC_I RE F CRT_IRTN
BG44 DDPB_AUXN BJ44 DDPB_AUXP AU38 DDPB_HPD
HDMI_CTRL CLK 13 HDMI_CTRL DATA 13
PCH_DDPC_HPD HDMIB_D2BN_C HDM IB _D2BP_C HDMIB_D1BN_C HDM IB _D1BP_C HDMIB_D0BN_C HDM IB _D0BP_C HDM IB _CLKBN_C HDM IB _CLKBP_C
C125 C126 C111 C112 C113 C114 C115 C116
0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04 0.1u_10V_X 7R_04
HDMIB_D2BN 13 HDMIB_D2BP 13 HDMIB_D1BN 13 HDMIB_D1BP 13 HDMIB_D0BN 13 HDMIB_D0BP 13 HDMIB_CLKBN 13 HDMIB_CLKBP 13
U50 U52
C t r o P y a l p s i D
5VS
BC46 DDPD _AUX N BD46 DDPD_AUXP AT 38 DDPD_HPD
G PCH_DDPC_HPD
S
BJ40 DDPD_0N BG40 DDPD_0P BJ38 DDPD_1N BG38 DDPD_1P BF37 DDPD_2N BH37 DDPD_2P BE36 DDPD_3N BD36 DDPD_3P
Q 7 M TN70 02Z HS3 D
PORTC _HPD 13 R34 100K_1%_04
D t r o P y a l p s i D
IbexPeak-M_ Rev0_9
Connect to G ND PC H_DDPC_HP D R33
*0_04
PO RTC_ HPD
No Connect External Grap hics (PCH Int egrated G raphics Disable) External Graphics (PCH Integrated Graphics Disable)
2,10,11,12,13,14,15,16,18,19, 20,21,23,24,25,26,27, 2 8,29,30,31,35,36 3.3VS 2,13,20,21 ,2 6,27,30,31,35,36 5VS
http://hobi-elektronika.net B - 18 IBEXPEAK - M 4/9
