apple-macbook-air-a1369-1-8203023a-schematics.pdf

CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2011-04-18

www.laptopblue.vn

SCHEM,EVT,MLB,K21 SCHEM,EVT,MLB,K21 04/18/11

(.csa)

Date

Page TABLE_TABLEOFCONTENTS_HEAD

Contents

1 TABLE_TABLEOFCONTENTS_ITEM

MASTER

Table of Contents

MASTER

System Block Diagram

K6_MLB

12/11/2009

19/01/2011

TABLE_TABLEOFCONTENTS_ITEM


MASTER

BOM Configuration

K17_REF

Functional Test / No Test

(K99_MLB)

MASTER 05/28/2009

(02/16/2010)

8


8

05/15/2010

Signal Aliases

9

01/10/2011

CPU DMI/PEG/FDI/RSVD


10

01/10/2011

CPU CLOCK/MISC/JTAG


11

01/10/2011

CPU DDR3 INTERFACES

CPU POWER

13

CPU GROUNDS

CPU DECOUPLING-I


15

16

PCH SATA/PCIE/CLK/LPC/SPI

17

PCH PCI/FLASHCACHE/USB


PCH MISC

K21_MLB

22

PCH POWER

K21_MLB

PCH GROUNDS

K78_MLB

PCH DECOUPLING

23

CPU & PCH XDP

USB HUBS

25

Clock (CK505) and Chipset Support

CPU Memory S3 Support

27

32


35

DDR3 DRAM Channel B (32-63)

SecureDigital Card Reader

T29 Host (1 of 2)

K78_MLB

CPU IMVP7 & AXG VCore Output

K78_MLB

CPU VCCIO (1.05V) Power Supply

K78_MLB

Misc Power Supplies

K78_MLB

Power FETs

K78_MLB

Power Control 1/ENABLE

K78_MLB

Internal DisplayPort Connector

K78_MLB

DisplayPort/T29 A MUXing

K21_MLB

DisplayPort/T29 A Connector

K78_MLB

LCD Backlight Driver

K78_MLB

CPU Constraints

K21_CONSTRAINTS

Memory Constraints

K21_CONSTRAINTS

PCH Constraints 1

K21_CONSTRAINTS

PCH Constraints 2

K21_CONSTRAINTS

Ethernet/FW Constraints

K21_CONSTRAINTS

T29 Constraints

K21_CONSTRAINTS

SMC Constraints

K21_CONSTRAINTS

Project Specific Constraints

K21_CONSTRAINTS

PCB Rule Definitions

K21_CONSTRAINTS

01/10/2011

01/10/2011

12/07/2010

01/10/2011

77

01/16/2011

78

01/10/2011

79

02/10/2011

12/13/2010

94

12/07/2010

01/16/2011

97

04/06/2011

101

04/06/2011

102

04/06/2011

103

04/06/2011

104

04/06/2011

105

04/06/2011

106


75

C

01/10/2011

04/06/2011

108

04/06/2011

109

04/06/2011


K78_MLB (MASTER) (MASTER)

B

01/10/2011 K78_MLB 01/10/2011

T29 Host (2 of 2)

K78_MLB

T29 Power Support

K78_MLB

X21 WIRELESS CONNECTOR

K21_MLB

SATA CONNECTOR

K78_MLB

External USB Connectors

K21_MLB

Left I/O (LIO) Connector

K21_MLB

SMC

K78_MLB

SMC Support

K78_MLB

LPC+SPI Debug Connector

K78_MLB

SMBus Connections

K78_MLB

38

36

CPU IMVP7 & AXG VCore Regulator

01/16/2011

12/16/2010

37


K78_MLB

K78_MLB

36

34

1.5V DDR3 Supply

01/16/2011

76

73

35

33

K78_MLB

100


K78_MLB

5V / 3.3V Power Supply

12/03/2010

75

72

K78_MLB

K78_MLB

93


K78_MLB

System Agent Supply

08/20/2010

90


K78_MLB

K78_MLB

74

71

K21_MLB

01/10/2011 FSB/DDR3/FRAMEBUF Vref Margining


12/13/2010


PBus Supply & Battery Charger

73

70

34



K78_MLB

33

31

11/29/2010

12/07/2010

DDR3 DRAM CHANNEL B (32-63)



12/07/2010

DDR3 DRAM CHANNEL B (0-31)

30

12/13/2010

01/10/2011 K78_MLB

JACK_K90I

72

69

32



12/07/2010

DDR3 DRAM CHANNEL A (32-63)

29

12/13/2010

K21_MLB

31



12/07/2010

DDR3 DRAM CHANNEL A (0-31)

28


01/10/2011

01/10/2011 K78_MLB

DC-In & Battery Connectors

71

68

30



01/10/2011

K21_MLB

29


12/13/2010

K78_MLB

AUDI0: SPEAKER AMP

70

67

28


12/13/2010

K78_MLB

27


62

66

26




01/10/2011

69

65

25




01/16/2011

01/10/2011

IPD / KBD Backlight

64

24



12/13/2010

K78_MLB

SPI ROM

63

23


59

K21_MLB

22


58

K21_MLB

21

19


12/13/2010

PCH DMI/FDI/GRAPHICS

18

02/08/2011

57

K21_MLB

20



12/13/2010

19


01/10/2011

K78_MLB

18


01/10/2011

01/10/2011

CPU DECOUPLING-II


K78_MLB

17



K78_MLB

16

14


K78_MLB

14



K78_MLB

13



K78_MLB

12


52

K78_MLB

11

K78_MLB

62


K91_MLB

10

K78_MLB

Thermal Sensors

61


K91_MLB

9



51 05/15/2010

Power Aliases

High Side Current Sensing

Fan 57

50

7



49

Revision History 5


01/16/2011

56

48

4

Sync

55


Power Block Diagram


Contents 54

47

3

3

D

Date

Page TABLE_TABLEOFCONTENTS_HEAD

46

2


(.csa)

Sync

1

01/10/2011


40

37

12/13/2010


45

38

01/10/2011


46


12/13/2010

47


11/09/2010

49


01/10/2011

50


01/10/2011

51


01/10/2011

52


01/10/2011

53

45

01/10/2011

Voltage & Load Side Current Sensing

K78_MLB


A DRAWING TITLE

SCHEM,MOCKUP,MLB,K21 DRAWING NUMBER

atic / PCB #’s NUMBER

QTY

Apple Inc. DESCRIPTION

1-8870

1

SCHEM,MLB,K21

0-3023

1

PCBF,MLB,K21

REFERENCE DES

CRITICAL

SCH

CRITICAL

PCB

CRITICAL

BO M O PT ION

PRODUCT SAFETY REQUIREMENTS: PCB,UL RECOGNIZED, MIN. 130-C TEMP RATING AND V-O FLAME RATING PER UL 796 & UL 94 PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP RATING AND V-O FLAME RATING

r 18 17:52:39 2011

8

7

6

051-8870 REVISION

3.13.0

R

5

4

3

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT SHEET III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

1 OF 109

2

1

1 OF 75

D

8

7

www.laptopblue.vn

6

5

4

3

2

1

1G/2GB

J2500

CPU XDP CONN

JTAG U2900,U3030

PG 10

MEMORY

U1000

PG 23

D

64-Bit

INTEL CPU

J9000

INTERNAL DISPLAY CONN

EDP

PG 63

PG 9

D

DDR3-1066/1333MHZ A

PG 27,38

1G/2GB MEMORY

SANDYBRIDGE SFF

U7000

U3100,3230

1.6 GHZ

MEMORY CHARGER

DDR3-1066/1333MHZ B

POWER CIRCUITRY

64-Bit

PCIE PG 9

PG 52-60

PG 29,30

FDI

PG 52

DMI

PG 9

PG 9

PG 11

TEMP SENSOR PG 47

RTC

FDI

DMI

GPIO

PG 17

PG 15

VOLTAGE/CURRENT SENSOR

U2700 PG 46

SYSTEM CLOCK

PG 16

PG 17

U6100

J5600

SPI

CLOCK BUFFER

PG 25

BOOTROM

FAN CONN

PG 16 PG 50

PG 48

PG16

MISC

J4501

U4900

SSD CONN

C

S MB _B SA

SATA

S MB _B /0

ADC

FAN0

PG 19

C

J5100 PG 38

LPC+SPI CONN

LPC

PG 16

U1800

SERIAL PORT

SMC

PG 16 PG 43

EDP OUT

PWR CTRL

INTEL PCH

PM_SLP S3/S4

HDMI OUT

U3600

SMB_A U2600

COUGAR POINT

DVI OUT

PCIE

0

TMDS OUT

SD CARD CONTROLLER

2

LVDS OUT 3

T29 ROUTER

LID

U3500

USB HUB-1

1

PG 24

J3500

SDCARD CONN

PG 33

PG 33

4

1

5

PG 34,35

J5700

U9390

J9400

DISPLAY PORT+ T29 CONN PG 65

6

DP

DP OUT

USB

MUX

IPD FLEX CONN

U2650

7

USB HUB-2

8

PG 17

PG 49

PG 64

J4600

9

RIGHT EXT USB CONN

PG 24

0

0 1

JTAG

J4610

1 1

PCH XDP CONN PG 16

PCIE J4001

PCIE

X21 WIRELESS CONN PG 37

PG 39

2 1

PG 23

B

PG 41

PG 17

RGB OUT

PG 16

3 1

PG 18

PCI

SMB

PG 18

HDA

PG 16

B

PG 16

USB

U6210

J4700

USB CAM

HDA

USB EXT

SPK

LEFT I/O CONN

SPEAKER AMP PG 51

J6903

RIGHT SPEAKER CONN PG 52

I2C

PG 40

J4702

U6201

AUDIO CODEC

J4610

CAMERA+ALS CONN

LEFT EXT USB CONN

PG 6

PG 5

PG 7

LIO BOARD U6620

A

SPEAKER AM P

LINE IN F IL TE R

HEADPHONE FILTER

PG 9

PG 11

PG 8

SYNC_MASTER=K6_MLB

SYNC_DATE=12/11/2009

PAGE TITLE

J6955

HALL EFFECT

System Block Diagram DRAWING NUMBER

PG 51 J6702

Apple Inc.

J6700

LEFT SPEAKER CONN

HEADPHONE/ LINE IN JACK

PG 10

PG 10

SIZE

051-8870 REVISION

3.13.0

R


BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

PAGE

2 OF 109

D

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

1G/2GB

J2500

CPU XDP CONN

JTAG U2900,U3030

PG 10

MEMORY

U1000

PG 23

D

64-Bit

INTEL CPU

J9000

INTERNAL DISPLAY CONN

EDP

PG 63

PG 9

D

DDR3-1066/1333MHZ A

PG 27,38

1G/2GB MEMORY

SANDYBRIDGE SFF

U7000

U3100,3230

1.6 GHZ

MEMORY CHARGER

DDR3-1066/1333MHZ B

POWER CIRCUITRY

64-Bit

PCIE PG 9

PG 52-60

PG 29,30

FDI

PG 52

DMI

PG 9

PG 9

PG 11

TEMP SENSOR PG 47

RTC

FDI

DMI

GPIO

PG 17

PG 15

VOLTAGE/CURRENT SENSOR

U2700 PG 46

SYSTEM CLOCK

PG 16

PG 17

U6100

J5600

SPI

CLOCK BUFFER

PG 25

BOOTROM

FAN CONN

PG 16 PG 50

PG 48

PG16

MISC

J4501

U4900

SSD CONN

C

S MB _B SA

SATA

S MB _B /0

ADC

FAN0

PG 19

C

J5100 PG 38

LPC+SPI CONN

LPC

PG 16

U1800

SERIAL PORT

SMC

PG 16 PG 43

EDP OUT

PWR CTRL

INTEL PCH

PM_SLP S3/S4

HDMI OUT

U3600

SMB_A U2600

COUGAR POINT

DVI OUT

PCIE

0

TMDS OUT

SD CARD CONTROLLER

2

LVDS OUT 3

T29 ROUTER

LID

U3500

USB HUB-1

1

PG 24

J3500

SDCARD CONN

PG 33

PG 33

4

1

5

PG 34,35

J5700

U9390

J9400

DISPLAY PORT+ T29 CONN PG 65

6

DP

DP OUT

USB

MUX

IPD FLEX CONN

U2650

7

USB HUB-2

8

PG 17

PG 49

PG 64

J4600

9

RIGHT EXT USB CONN

PG 24

0

0 1

JTAG

J4610

1 1

PCH XDP CONN PG 16

PCIE J4001

PCIE

X21 WIRELESS CONN PG 37

PG 39

2 1

PG 23

B

PG 41

PG 17

RGB OUT

PG 16

3 1

PG 18

PCI

SMB

PG 18

HDA

PG 16

B

PG 16

USB

U6210

J4700

USB CAM

HDA

USB EXT

SPK

LEFT I/O CONN

SPEAKER AMP PG 51

J6903

RIGHT SPEAKER CONN PG 52

I2C

PG 40

J4702

U6201

AUDIO CODEC

J4610

CAMERA+ALS CONN

LEFT EXT USB CONN

PG 6

PG 5

PG 7

LIO BOARD U6620

A

SPEAKER AM P

LINE IN F IL TE R

HEADPHONE FILTER

PG 9

PG 11

PG 8

SYNC_MASTER=K6_MLB


PAGE TITLE

J6955

HALL EFFECT

System Block Diagram DRAWING NUMBER

PG 51 J6702

Apple Inc.

J6700

LEFT SPEAKER CONN

HEADPHONE/ LINE IN JACK

PG 10

PG 10

SIZE

051-8870 REVISION

3.13.0

R


BRANCH


PAGE

2 OF 109

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6

5

4

D6905

PPDCIN_G3H_OR_PBUS

2

ENABLE PP3V42_G3H_REG

LT3470A

2

3

3.425V G3HOT

PPVIN_G3H_P3V42G3H

R6905

3

(PAGE 52)

1

J6900

D

AC

A

A

ADAPTER

U7000

ISL95870 U7600

EN

21

PPVBAT_G3H

VIN

ISL6259HRTZ

1

SMC_DCIN_ISENSE

PBUS SUPPLY/ BATTERY CHARGER

R7050

SMC_RESET_L

V

U3816/U3815

24

25

T29_PWR_EN

PPVCORE_S0_CPU_REG

CPU VCORE MAX15092GTL

V

U7400

CPUIMVP_VR_ON

(PAGE 53)

VR_ON

R5330 SMC_GFX_VSENSE

PPVCORE_S0_AXG_REG

VOUT

Q7055 PPVBAT_G3H_CHGR_R

PPVBATT_G3H_CONN

PP1V05_T29_FET

EN

R5320 SMC_CPU_VSENSE

VOUT

A

D

TPS22924 (PAGE 36)

VIN

SMC_BATT_ISENSE

J6950

22-1

CPUVCCIOS0_PGOOD

PGOOD

(PAGE 59)

22

PPCPUVCCIO_S0_REG SMC_CPU_FSB_ISENSE

VOUT

IN

4

CPUVCCIOS0_EN

A

1.05VVOUT

VCC

SMC_RESET_L

R7640

VIN

PP5V_S0_CPUVCCIOS0.

R7020

DCIN(14.5V)

15

R5400

F7040

PPBUS_G3H

F6905 6A FUSE

4

SMC POWER SN0903048 U5010 (PAGE 42)

U6990

R6920

1

(PAGE 57) CPUIMVP_PGOOD

PGOOD

) V 4 . 8

26

25-1

COUGAR-POINT (PCH)

P 3 S 2 O

26-1

CPUIMVP_AXG_PGOOD

PGOODG

CHGR_BGATE

T

RSMRST#

6 (

VIN DDRREG_EN

K78/K21 POWER SYSTEM ARCHITECTURE C

PWRBTN#

SYS_RERST#

DDRVTT_EN

0.75V

16

PPDDR_S3_REG

27

PLTRST#

CPU_PWRGD PROCPWRGD

6

RC

P60

P3V3S5_EN

U7801

U2850

(PAGE 17~21)

30

P1V5CPU_EN

7

PP1V5_S3RS0_FET

DELAY

SMC_PM_G2_EN

PP5V_S0_VCCSA

(PAGE 41)

22

PVCCSA_EN

VCC

ISL95870A U7100

EN

CPU_VCCSA_VID<1>

(PAGE 54) VID1

R7140 VOUT

PPVCCSA_S0_REG

SM_DRAMPWROK

A

PGOOD

23

CPU U1000

PM_SLP_S5_L

PG 17

11

(PCH)

PM_SLP_SUS_L

SLP_SUS#

U7940

RC

P5V_3V3_SUS_EN

RC

10-1

13-1

PG61

P3V3S3_EN

PG62

DELAY

DDRREG_EN

PG62

7

13

P5VS3_EN EN1

14

VIN 5V

VOUT1

P5VS3_EN

B

PG62

PP3V3_S5_REG

3.3V

F9700

PM_SLP_S4_L

PG 17

13

14-1

P5VS3_PGOOD

PP3V3_SUS_FET

CPUVCCIOS0_PGOOD

10-4 R7962

PP3V3_S3_FET

PP5V_S0_VMON

RSMRST_IN(P13) RSMRST_OUT(P15)

10

5

B

PM_RSMRST_L

99ms DLY PWR_BUTTON(P90)

IMVP_VR_ON(P16)

SYSRST(PA2)

V4MON P17(BTN_OUT)

PP5V_SUS_FET

PM_DSW_PWRGD

12

4

PPVOUT_SW_LCDBKLT VOUT

(PAGE 66)

CPUIMVP_VR_ON

26

PM_SYSRST_L

PM_PWRBTN_L

6-1

(PAGE 62)

10-2

PM_SLP_S5_L

Q7840 R7978

P15

PWRGD(P12)

ISL88042IRTEZ V3MON

PP1V05_S0_VMON

U9701

9

SMC_ONOFF_L

U7960

V2MON

PP1V5_S3RS0_VMON

P3V3S3_EN

EN

S5_PWRGD

VDD

Q7810

PPBUS_SW_LCDBKLT_PWR

25

6

14-1

VIN LP8550

SMC

PVCCSA_PGOOD ALL_SYS_PWRGD

9

LCD_BKLT_EN

14

(PAGE 17~21)

U7740

PP3V3_S0_VMON

&& BKLT_PLT_RST_L PM_SLP_S3_L PG 17 SLP_S3#(F4)

PP1V05_SUS_LDO

TPS720105

(PAGE 60)

Q7820 P5V_3V3_SUS_EN

P3V3S5_PGOOD

SLP_S4#(H4)

P5VS3_PGOOD

P3V3S5_PGOOD

10-3

(PAGE 55) PGOOD

P1V8S0_PGOOD

P5VS0_EN

TPS51980 U7201

Q9706

RESET*

CPUIMVP_AXG_PGOOD

15

8

(R/H)

(PAGE 9~15)

23-1 PP5V_S0_FET

PP3V3_S5

VOUT2

EN2

15 13-2

PVCCSA_PGOOD Q7860

PP5V_S3_REG

(L/H)

P3V3S5_EN

DELAY

U1800

UNCOREPWRGOOD

PPVIN_S5_P5VP3V3

SLP_S5#(E4)

COUGAR-POINT

C

DRAMPWROK

DDRREG_PGOOD

(PAGE 56)

U4900

29

28

PM_MEM_PWRGD

16-1 PGOOD

PM_DSW_PWRGD

PLT_RERST_L

PM_PCH_PWRGD

PPVTT_S0_DDR_LDO

VOUT2

TPS51916 U7300

SMC

A

VOUT1

S3

U1800 DPWROK

R7350

VLDOIN

1.5V

S5

PM_PWRBTN_L PM_SYSRST_L PM_RSMRST_L

SLP_S5_L(P95)

PM_SLP_S4_L

RES*

SMC_RESET_L

4

SLP_S4_L(P94)

PG62 PM_SLP_S3_L

P5V_3V3_SUS_EN

16

PP3V3_S0

Q5300

SLP_S3_L(P93)

P1V8S0_PGOOD U4900 (PAGE 41)

SMC_PBUS_VSENSE PM_SLP_S3_R_L ISL8014A

P1V8_S0_EN

EN

17

PBUSVSENS_EN

1V05_S0_LDO_EN

RC

A

CPUVCCIOS0_EN

DELAY

RC

PVCCSA_EN

21 21 22

RC

RC DELAY

19

P1V8S0_EN

19 17

TPS720105

1V05_S0_LDO_E N

EN

P3V3S0_EN

14-1 14-1

PBUSVSENS_EN

14-1

U7780

PP1V05_S0_LDO.

(PAGE 60)

U7770

TPS72015

T29_A_HV_EN

(PAGE 60)

VIN

P1V5S0_EN


18

(PAGE 60)

Q3880

P5VS0_EN

DELAY

DELAY

U7720

PP1V8_S0_REG

T29BST_EN_UVLO

O L LT3957 V U / U3890 N E

Q7830 TPS22924

T29_PWR_EN

EN

VOUT

(PAGE 36)

PP15V_T29_REG

P3V3S0_EN

14

PP1V5_S0_REG

A PAGE TITLE

Power Block Diagram

EN

U3810

DRAWING NUMBER

Apple Inc.

PP3V3_T29_FET

PP1V5S0_EN

SIZE

051-8870 REVISION

3.13.0

R

(PAGE 36)


BRANCH


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www.laptopblue.vn 5

BOM Variants TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

BOM OPTIONS TABLE_BOMGROUP_ITEM

085-2684

K21i MLB DEVELOPMENT BOM

4

3

2

1

Bar Code Labels / EEEE #’s PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

K21_DEVEL:ENG

825-7563

1

LABEL,LIO,K99

[EEEE_DP1F]

CRITICAL

EEEE:DP1F

825-7563

1

LABEL,LIO,K99

[EEEE_DP1G]

CRITICAL

EEEE:DP1G

825-7563

1

LABEL,LIO,K99

[EEEE_DP1H]

CRITICAL

EEEE:DP1H

825-7563

1

LABEL,LIO,K99

[EEEE_DP1J]

CRITICAL

EEEE:DP1J

825-7563

1

LABEL,LIO,K99

[EEEE_DP1K]

825-7563

1

LABEL,LIO,K99

[EEEE_DP1L]

CRITICAL

EEEE:DP1L

825-7563

1

LABEL,LIO,K99

[EEEE_DP1M]

CRITICAL

EEEE:DP1M

825-7563

1

LABEL,LIO,K99

[EEEE_DP1N]

CRITICAL

EEEE:DP1N

825-7563

1

LABEL,LIO,K99

[EEEE_DP1P]

CRITICAL

EEEE:DP1P

825-7563

1

LABEL,LIO,K99

[EEEE_DP1Q]

CRITICAL

EEEE:DP1Q

825-7563

1

LABEL,LIO,K99

[EEEE_DP1R]

CRITICAL

EEEE:DP1R

825-7563

1

LABEL,LIO,K99

[EEEE_DP1T]

CRITICAL

EEEE:DP1T

TABLE_BOMGROUP_ITEM

607-8041

CMN PTS,PCBA,MLB,K21

K21_COMMON TABLE_BOMGROUP_ITEM

639-2553

PCBA,MLB,1.8GHZ,HY 2GB,K21

K21_CMNPTS,EEEE:DP1F,CPU:1.8GHZ,DDR3:HYNIX_2GB TABLE_BOMGROUP_ITEM

639-2554

PCBA,MLB,1.7GHZ,SA 4GB,K21

K21_CMNPTS,EEEE:DP1G,CPU:1.7GHZ,DDR3:SAMSUNG_4GB TABLE_BOMGROUP_ITEM

639-2558

PCBA,MLB,1.8GHZ,EL 4GB,K21

K21_CMNPTS,EEEE:DP1H,CPU:1.8GHZ,DDR3:ELPIDA_4GB

CRITICAL

EEEE:DP1K

D

TABLE_BOMGROUP_ITEM

D

639-2549

PCBA,MLB,1.7GHZ,EL 4GB,K21

K21_CMNPTS,EEEE:DP1J,CPU:1.7GHZ,DDR3:ELPIDA_4GB TABLE_BOMGROUP_ITEM

639-2555


K21_CMNPTS,EEEE:DP1K,CPU:1.8GHZ,DDR3:HYNIX_4GB

639-2557


K21_CMNPTS,EEEE:DP1L,CPU:1.8GHZ,DDR3:SAMSUNG_4GB

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

639-2548


K21_CMNPTS,EEEE:DP1M,CPU:1.7GHZ,DDR3:HYNIX_2GB

639-2550

PCBA,MLB,1.8GHZ,MI 2GB,K21

K21_CMNPTS,EEEE:DP1N,CPU:1.8GHZ,DDR3:MICRON_2GB

639-2551


K21_CMNPTS,EEEE:DP1P,CPU:1.7GHZ,DDR3:HYNIX_4GB

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

639-2552


K21_CMNPTS,EEEE:DP1Q,CPU:1.7GHZ,DDR3:SAMSUNG_2GB TABLE_BOMGROUP_ITEM

639-2556


K21_CMNPTS,EEEE:DP1R,CPU:1.8GHZ,DDR3:SAMSUNG_2GB TABLE_BOMGROUP_ITEM

639-2559

PCBA,MLB,1.7GHZ,MI 2GB,K21

K21_CMNPTS,EEEE:DP1T,CPU:1.7GHZ,DDR3:MICRON_2GB

C

C

B

B

A

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PAGE TITLE

Revision History DRAWING NUMBER

Sub BOM PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

085-2684

1

K21 MLB DEVELOPMENT

DEVEL

CRITICAL

607-8041

1

CMN PTS,PCBA,MLB,K21

CMNPTS

CRITICAL

BOM OPTION DEVEL_BOM K21_CMNPTS

Apple Inc.

SIZE

051-8870 REVISION

3.13.0

R


BRANCH


PAGE

4 OF 109

D

A

8

7

6

www.laptopblue.vn 5

K21 BOM GROUPS

4

3

2

1

Module Parts TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS TABLE_BOMGROUP_ITEM

K21_COMMON

ALTERNATE,COMMON,K21_MI SC,K21_DEBUG:ENG,K21_PROGPA RTS,USBHUB_2513B,T29BST:Y, EDP,PCH:B3 TABLE_BOMGROUP_ITEM

K21_MISC

PART NUMBER

TABLE_BOMGROUP_ITEM

K21_PROGPARTS

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

1

SNB,QAYS,QS ,J1,1.8,17W,2 +2,1.20,4M,B GA

U1000

CRITICAL

CPU:1.8GHZ

337S4119

1

SNB,QAYM,QS ,J1,1.7,17W,2 +2,1.20,3M,B GA

U1000

CRITICAL

CPU:1.7GHZ

337S4101

1

SNB,QAM1,QS ,J1,1.6,17W, 2+2,1.1,4M,B GA

U1000

CRITICAL

CPU:1.6GHZ

337S4100

1

SNB,QAM2,QS ,J1,1.5,17W, 2+2,1.1,4M,B GA

U1000

CRITICAL

CPU:1.5GHZ

337S4099

1

SNB,QAM3,QS ,J1,1.4,17W,2 +2,1.05,3M,B GA

U1000

CRITICAL

CPU:1.4GHZ

337S4098

1

SNB,QALV,QS ,J1,1.3,17W,2 +2,1.05,3M,B GA

U1000

CRITICAL

CPU:1.3GHZ

337S4080

1

COUGAR POINT,SLHAG,PRQ,BD82QS6 7

U1800

CRITICAL

PCH:B2

337S4091

1

COUGAR POINT,B3,SLJ4K,PRQ,BD82Q S67

U1800

CRITICAL

PCH:B3

338S0976

1

U3600

CRITICAL

T29:YES

333S0585

4

333S0585

4

IC,SDRAM,1GBIT,DDR3-133 3,78P FBGA,T-DIE,HYNIX

333S0585

4

IC,SDRAM,1GBIT,DDR3-133 3,78P FGBA,T-DIE,HYNIX

U3100,U3110,U3120,U3130

CRITICAL

333S0585

4


U3200,U3210,U3220,U3230

CRITICAL

333S0586

4

IC,SDRAM,2GBIT,DDR3-133 3,78P FBGA,B-DIE,HYNIX

U2900,U2910,U2920,U2930

CRITICAL

333S0586

4


U3000,U3010,U3020,U3030

CRITICAL

BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG TABLE_BOMGROUP_ITEM

K21_DEVEL:ENG

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG TABLE_BOMGROUP_ITEM

K21_DEVEL:PVT

LPCPLUS,XDP_CONN,XDP_PCH

K21_DEBUG:ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

QTY

337S4121

CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL

K21_DEBUG:PVT

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

K21_DEBUG:PROD

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

D

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DDR3:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB TABLE_BOMGROUP_ITEM

DDR3:HYNIX_4GB

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:SAMSUNG_2GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

TABLE_BOMGROUP_ITEM

IC,T29 Eagle Ridge,192 FCBGA,8x9MM

TABLE_BOMGROUP_ITEM

DDR3:SAMSUNG_4GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB TABLE_BOMGROUP_ITEM

DDR3:MICRON_2GB

DRAM_CFG0:H,DRAM_CFG1:L ,DRAM_CFG2:L,DRAM_CFG3:L,D RAM_TYPE:MICRON_2GB

DDR3:ELPIDA_4GB

DRAM_CFG0:H,DRAM_CFG1:H ,DRAM_CFG2:H,DRAM_CFG3:L,D RAM_TYPE:ELPIDA_4GB

TABLE_BOMGROUP_ITEM

C

QTY

335S0550

1

341T0352

1

337S3997

1

341T0353

1

338S0895

1

341T0348

1

335S0809

1

335S0803

1

341T0349

1

DESCRIPTION

REFERENCE DES

IC,EEPROM,SERIAL,SPI,1Kx8,1.8V,MLP8,LF

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

IC,T29-MCU,K21

IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF

IC,SMC,K21

64

MBIT

SPI

64 MBIT SPI

SERIAL

DUAL

I/O

FLASH,Macronix

SERIAL DUAL I/O FLASH,Numonyx

IC,EFI ROM,K21 K78

Alternate Parts TABLE_ALT_HEAD

P AR T N UM BE R

ALTERNATE FOR PART NUMBER

B OM O PT IO N

REF DES COMMENTS: TABLE_ALT_ITEM

376S0855

376S0613

ALL

U3690 U3690

IC,T29-ROM,K21

CRITICAL CRITICAL CRITICAL

CRITICAL

U3000,U3010,U3020,U3030

CRITICAL

DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_2GB DRAM_TYPE:HYNIX_4GB DRAM_TYPE:HYNIX_4GB

333S0586

4

IC,SDRAM,2GBIT,DDR3-133 3,78P FGBA,B-DIE,HYNIX

U3100,U3110,U3120,U3130

CRITICAL

333S0586

4


U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:HYNIX_4GB

333S0587

4

IC,SDRAM,1GBIT,DDR3-1333 ,78P FBGA,G-DIE,SAMSUNG

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

333S0587

4


U3000,U3010,U3020,U3030

CRITICAL

333S0587

4

IC,SDRAM,1GBIT,DDR3-1333 ,78P FGBA,G-DIE,SAMSUNG

T29ROM:BLANK

333S0587

4


T29ROM:PROG

333S0588

4

IC,SDRAM,2GBIT,DDR3-1333 ,78P FBGA,D-DIE,SAMSUNG

Programmable Parts PART NUMBER

U2900,U2910,U2920,U2930


BOM OPTION

U3100,U3110,U3120,U3130

CRITICAL

U3200,U3210,U3220,U3230

CRITICAL

U2900,U2910,U2920,U2930

U9330

CRITICAL

T29MCU:BLANK

333S0588

4


U9330

CRITICAL

T29MCU:PROG

333S0588

4

IC,SDRAM,2GBIT,DDR3-1333 ,78P FGBA,D-DIE,SAMSUNG

U4900

CRITICAL

SMC_BLANK

333S0588

4


U4900

CRITICAL

SMC_PROG

333S0590

4

IC,SDRAM,1GBIT,DDR3-1333 ,78P FBGA,V68A-D,MICRON

U2900,U2910,U2920,U2930

U6100

CRITICAL

BOOTROM_BLANK

333S0590

4


U3000,U3010,U3020,U3030

IC,SDRAM,1GBIT,DDR3-1333 ,78P FGBA,V68A-D,MICRON

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030 U3100,U3110,U3120,U3130 U3200,U3210,U3220,U3230

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:SAMSUNG_2GB DRAM_TYPE:SAMSUNG_2GB DRAM_TYPE:SAMSUNG_2GB

CRITICAL


CRITICAL


CRITICAL


CRITICAL


CRITICAL

DRAM_TYPE:MICRON_2GB

CRITICAL


CRITICAL


U6100

CRITICAL

BOOTROM_BLANK

333S0590

4

U6100

CRITICAL

BOOTROM_PROG

333S0590

4


U3200,U3210,U3220,U3230

CRITICAL


333S0589

4

IC,SDRAM,2GBIT,DDR3-133 3,78P FBGA,C-DIE,ELPIDA

U2900,U2910,U2920,U2930

CRITICAL

DRAM_TYPE:ELPIDA_4GB

333S0589

4


U3000,U3010,U3020,U3030

CRITICAL


333S0589

4

IC,SDRAM,2GBIT,DDR3-133 3,78P FGBA,C-DIE,ELPIDA

U3100,U3110,U3120,U3130

CRITICAL


333S0589

4


U3200,U3210,U3220,U3230

CRITICAL


353s2929

1

C

Diodes alt to Toshiba TABLE_ALT_ITEM

376S0977

376S0859

ALL

Diodes alt to Toshiba

376S0972

376S0612

ALL

Rohm alt to Toshiba

377S0107

377S0066

ALL

ONsemi alt to Semtech

138S0676

138S0691

ALL

Murata alt to Samsung

IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28

U7000

CRITICAL

T29FENCE

CRITICAL

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

37 1 S0 6 7 9

3 7 1 S 06 5 2

ALL

B

138S0678

ALL

806-2333

1

K21, T29 Fence

806-2356

1

K21, T29 Can

T29CAN

CRITICAL

806-2347

1

K21, T29 Filter Can

T29FILTERCAN

CRITICAL

806-2376

1

K78, mDP Can

MDPCAN

CRITICAL

806-2377

1

K78, mDP Spring

MDPSPRING

CRITICAL

NOSTUFF

NXP alt to NXP TABLE_ALT_ITEM

138S0679

PD Module Parts

B

Murata/Samsung to Taiyo TABLE_ALT_ITEM

138S0671

138S0673

ALL

Taiyo alt to Murata

337S4092

337S4100

ALL

EARLY 1.5GHZ CPU SAMPLES

NOSTUFF

TABLE_ALT_ITEM

TABLE_ALT_ITEM

337S4093

337S4101

ALL

EARLY 1.4GHZ CPU SAMPLES

353S3312

353S3055

ALL

NXP alt to Pericom

37 6 S0 7 9 0

3 7 6 S 09 2 8

ALL

TI alt to Fairchild

128S0333

128S0294

ALL

Sanyo alt for Sanyo/Frederick

152S1462

152S1295

ALL

Toko alt for NEC inductor

104S0035

104S0011

ALL

Panasonic alt to Cyntec

152S1085

152S1307

ALL

Toko alt for Cyntec

51 4 -0 7 4 4

9 9 8 39 4 1

ALL

Old

376S0874

376S0895

ALL

FDMC0202S alt to RJK03E0DNS

138S0703

138S0648

ALL

Murata alt to Taiyo Yuden

138S0684

138S0660

ALL

Murata alt to Taiyo Yuden

338S0721

338S0923

ALL

SMSC USX2061 alt to USB2513B

152S1493

152S1300

ALL

Coilcraft alt to Murata

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

DRAM CFG CHART

J9400 alt to New J9400 TABLE_ALT_ITEM

VENDOR

CFG 1

CFG 0

TABLE_ALT_ITEM

HYNIX

0

0

1

0

MICRON

0

1

ELPIDA

1

1

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SAMSUNG

TABLE_ALT_ITEM

A

SYNC_MASTER=K17_REF


PAGE TITLE SIZE

CFG 2

DIE REV

CFG 3

BOM Configuration DRAWING NUMBER

2GB

0

A

0

B

1

Apple Inc.

1

SIZE

051-8870 REVISION

3.13.0

R

4GB


BRANCH


PAGE

5 OF 109

D

A

8

7

www.laptopblue.vn

6

5

4

3

2

Functional Test Points J4001: AirPort / BT Connector

J5600: Fan Connector

FUNC_TEST

FUNC_TEST

TRUE

PP3V3_WLAN_F

37

TRUE

=PP5V_S0_FAN

7 48

I627

TRUE

TRUE

WIFI_EVENT_L

37 41

TRUE

FAN_RT_TACH

48

I626

TRUE

TRUE

PCIE_AP_R2D_N

37 70

TRUE

FAN_RT_PWM

48

TRUE

PCIE_AP_R2D_P

37 70

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

TRUE

D

FUNC_TEST

TRUE

USB_BT_P USB_BT_N

TRUE

PCIE_AP_D2R_P

TRUE

(Need 5 TPs)

49

I624

PP3V3_TPAD_CONN

16 37 70

TRUE

PP5V_TPAD_FILT

16 37 70

TRUE

17 37

TRUE

AP_RESET_CONN_L

37

TRUE

USB_TPAD_CONN_N

49 74

AP_CLKREQ_Q_L

37

TRUE

=I2C_TPAD_SDA

44 49

=PP3V3_S3_BT

7 37

TRUE

=I2C_TPAD_SCL

44 49

TRUE

SMC_ONOFF_L

41 42 49

TRUE

SMC_LID

6 40 41 42 49

SMC_TPAD_RST_L

42 49

FUNC_TEST

I623

TRUE

TRUE

PP3V3_S0_HDD_R

38

TRUE

SATA_HDD_D2R_C_P

38 69

TRUE

SATA_HDD_D2R_C_N

38 69

FUNC_TEST

SATA_HDD_R2D_N

38 69

TRUE

SATA_HDD_R2D_P

38 69

TRUE

TRUE

SMC_HDD_OOB_TEMP_CONN

38

TRUE

SMC_HDD_TEMP_CTL_CONN

38

(Need 5 TPs)

SMC_PME_S4_WAKE_L

=PP18V5_DCIN_CONN

TRUE

=PP5V_S3_LIO_CONN

=PP3V42_G3H_ONEWIRE

7 40

TRUE

=PP3V3_S0_AUDIO

7 40

TRUE

=PP3V3R1V5_S0_AUDIO

7 40

TRUE

SYS_ONEWIRE

40 41

TRUE

SMC_BC_ACOK

40 41 42

TRUE

7 52

(Need 6 TPs)

NO_TEST Nets

TP_PCIE_CLK100M_PE4N


16

TP_PCIE_CLK100M_PE5P

16


16


16


J6950: Battery Connector PPVBAT_G3H_CONN

52 53

TRUE

SMC_LID

6 40 41 42 49

TRUE

=SMBUS_BATT_SDA

44 52

TRUE

SYS_DETECT_L

TRUE

=I2C_LIO_SDA

40 44

TRUE

=I2C_LIO_SCL

40 44

(Need to add 4 GND TPs near

TRUE

=I2C_MIKEY_SCL

40 44

J6950 and 1 for shield)

TRUE

=I2C_MIKEY_SDA

40 44

AUD_GPIO_3 SPKRAMP_INR_N SPKRAMP_INR_P

TRUE

17

TP_CRT_IG_BLUE

17

TP_CRT_IG_GREEN

17

TP_CRT_IG_RED

(Need 4 TPs)

52

17

TP_CRT_IG_DDC_CLK

17

TP_CRT_IG_DDC_DATA

17

TP_CRT_IG_HSYNC

17

TP_CRT_IG_VSYNC

J9000: Internal DP Connector

19 40

16


TP_PCH_LVDS_VBG

TRUE

18 40

TRUE

40 51

TRUE

40 51 74 24 40 69

TRUE

TRUE

USB_EXTD_P

24 40 69

TRUE

18 40 69

TRUE

PP3V3_SW_LCD I2C_TCON_SDA_R

TRUE

40 51 74

PPVOUT_SW_LCDBKLT

I2C_TCON_SCL_R LED_RETURN_6

LED_RETURN_5 LED_RETURN_4 LED_RETURN_3

63 66 63

(Need 2 TPs) (Need 2 TPs) 16

TP_HDA_SDIN1

16

TP_HDA_SDIN2

16

TP_HDA_SDIN3

63 63 63 66

TRUE

18 40 69

TRUE

TRUE

HDA_SDOUT

16 40 70

TRUE

LED_RETURN_2

63 66

TRUE

HDA_BIT_CLK

16 40 70

TRUE

LED_RETURN_1

63 66

TRUE

HDA_SDIN0

16 40 70

TRUE

DP_INT_HPD_CONN

63

16

TP_CLINK_CLK

24 40

TRUE

DP_INT_AUX_CH_C_N

63 70

16

TP_CLINK_DATA

16 40 70

TRUE

DP_INT_AUX_CH_C_P

63 70

16

TP_CLINK_RESET_L

TRUE

DP_INT_ML_F_P<0>

HDA_RST_L

TRUE TRUE

USB_EXTD_OC_L

HDA_SYNC

16 40 70

(Need to add 5 GND TPs)

TRUE

TRUE

J4800: SD Card Connector

TRUE TRUE

DP_INT_ML_F_P<1> DP_INT_ML_F_N<1>

TRUE

PP3V3_SW_SD_PWR SD_CLK SD_CMD

63 66

18

63 66

18

TP_PCIE_CLK100M_PEBN

16

TP_PCIE_CLK100M_PEBP

Misc Voltages & Control Signals

SD_D<7..0>

33

SD_CD_L

33

I628

TRUE

PPBUS_G3H

7 52

SD_WP

33

I629

TRUE

PPVIN_SW_T29BST

7 36

I630

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

7

I631

TRUE

I632

TRUE

PPDCIN_G3H PP3V42_G3H

I633

TRUE

PPVRTC_G3H

I634

TRUE

I636

TRUE

PP5V_S5 PP5V_SUS

I635

TRUE

PP3V3_S5

7 74

I638

TRUE

PP3V3_SUS

7

TRUE

PP3V3_S3

7

TRUE

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS

TRUE

LPC_AD<3..0>

16 41 43 70

TRUE

SPI_ALT_MOSI

43

7 43 7 43

FUNC_TEST

7 7 7 7 7

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

16 41 43 70

I639

TRUE

PP1V8_S0

TRUE

PM_CLKRUN_L

17 41 43

I641

TRUE

PP3V3_S0

7 74

17

TP_SDVO_TVCLKINN

TRUE

SMC_TMS

41 42 43

I640

TRUE

PP1V5_S3

7 68

17

TP_SDVO_TVCLKINP

TRUE

LPCPLUS_RESET_L

25 43

I643

TRUE

PP1V5_S3RS0

7 68 17

TP_SDVO_STALLN

43

I637

TP_SATA_D_D2RN

16

TP_SATA_D_D2RP

16

TP_SATA_D_R2D_CN

16

TP_SATA_D_R2D_CP

16

TP_SATA_E_D2RN

16

TP_SATA_E_D2RP

16

TP_SATA_E_R2D_CN

16

TP_SATA_E_R2D_CP

16

TP_SATA_F_D2RN

TRUE MAKE_BASE=TRUE

NC_SATA_F_D2RN

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_SATA_F_D2RP

TRUE MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

NC_HDA_SDIN2

16

TP_SATA_F_R2D_CN

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN3

16

TP_SATA_F_R2D_CP

SMC_TDO

41 42 43

I642

TRUE

PP1V5_S0

7

SMC_TRST_L

TRUE

PP1V05_S0

TP_SDVO_STALLP

I644

17

41 43

7

TRUE

SMC_MD1

41 43

I646

TRUE

PPVTTDDR_S3

7

17

TP_SDVO_INTN

TRUE

SMC_TX_L

39 41 42 43

I645

TRUE

PP0V75_S0_DDRVTT

7

17

TP_SDVO_INTP

25 43 70

I648

TRUE

19 43 50

I647

TRUE

PPVCCSA_S0_CPU PP1V05_SUS

43

I649

TRUE

PP15V_T29

7

43

I650

TRUE

PP3V3_T29

7

TRUE

LPC_CLK33M_LPCPLUS SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

7

TRUE

16 41 43

I651

TRUE

PP1V05_T29

7 36

TRUE

LPC_PWRDWN_L

17 41 43

I653

TRUE

PP1V05_S0_PCH_VCCADPLL

7

TRUE

SMC_TDI

41 42 43

I652

TRUE

PPVCORE_S0_CPU

7

TRUE

SMC_TCK

41 42 43

I654

TRUE

PPVCORE_S0_AXG

7

TRUE

SMC_RESET_L

41 42 43 53

I655

TRUE

PP1V5_S3_CPU_VCCDQ

7

TRUE

SMC_NMI

41 43

I657

TRUE

PP1V05_S0_CPU_VCCPQE

7

TRUE

SMC_RX_L

39 41 42 43

I656

TRUE

PP1V8_S0_CPU_VCCPLL_R

7

TRUE

LPCPLUS_GPIO

19 43


NC_SATA_B_D2RP

C

NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP

NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP

NC_SATA_F_R2D_CN

NC_PCI_PME_L NC_PCI_CLK33M_OUT3 TP_PCH_TP18

TRUE MAKE_BASE=TRUE

NC_PCH_TP17

TP_PCH_TP16

TRUE MAKE_BASE=TRUE

NC_PCH_TP16

TP_PCH_TP15

NC_PCH_TP15

TRUE MAKE_BASE=TRUE

NC_CLINK_DATA TP_PCH_TP14

TRUE MAKE_BASE=TRUE

NC_PCH_TP14

TP_PCH_TP13

TRUE MAKE_BASE=TRUE

NC_PCH_TP13

NC_CLINK_RESET_L NC_PCIE_CLK100M_PEBN


NC_PCH_TP18

TRUE MAKE_BASE=TRUE

TP_PCH_TP17 NC_CLINK_CLK

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TP_PCH_TP12

NC_PCH_TP12

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP TP_PCH_TP10

TRUE MAKE_BASE=TRUE

NC_PCH_TP10

TP_PCH_TP9

TRUE MAKE_BASE=TRUE

NC_PCH_TP9

TP_PCH_TP8

TRUE MAKE_BASE=TRUE

NC_PCH_TP8

TP_PCH_TP7

TRUE MAKE_BASE=TRUE

NC_PCH_TP7

TP_PCH_TP6

TRUE MAKE_BASE=TRUE

NC_PCH_TP6

I593

TRUE

XDP_PCH_AP_PWR_EN

I592

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

23

TP_PCH_TP5

TRUE MAKE_BASE=TRUE

NC_PCH_TP5

I595

TRUE

XDP_PCH_SDCONN_STATE_RST_L

23

TP_PCH_TP4

TRUE MAKE_BASE=TRUE

NC_PCH_TP4

I594

TRUE

XDP_PCH_ENET_PWR_EN

23

TP_PCH_TP3

TRUE MAKE_BASE=TRUE

NC_PCH_TP3

I596

TRUE

XDP_PCH_SDCONN_DET_L

23

TP_PCH_TP2

I597

TRUE

XDP_PCH_S5_PWRGD

23

TP_PCH_TP1

I598

TRUE

XDP_PCH_PWRBTN_L

23

I599

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

I600

TRUE

XDP_FW_CLKREQ_L

I601

TRUE

I602

TRUE

XDP_AP_CLKREQ_L

23

23

XDP_PCH_AUD_IPHS_SWITCH_EN

TRUE

PCH_VSS_NCTF<1>

70

I567

TRUE

PCH_VSS_NCTF<2>

70

I568

TRUE


NC_SDVO_TVCLKINN


NC_SDVO_STALLN


NC_SDVO_INTN

23

TP_XDP_PCH_OBSFN_A<0..1>

23

TP_XDP_PCH_OBSFN_B<0..1>

23

TP_XDPPCH_HOOK2

23

TP_XDPPCH_HOOK3

23

TP_XDP_PCH_OBSFN_D<0..1>

23

TP_XDP_PCH_HOOK4

23

TP_XDP_PCH_HOOK5

16

TP_PCH_GPIO64_CLKOUTFLEX0

16


16

TP_PCH_GPIO66_CLKOUTFLEX2 TP_PCH_GPIO67_CLKOUTFLEX3

NC_PCH_TP1

TRUE MAKE_BASE=TRUE

I566

PCH_VSS_NCTF<5>

70

PCH_VSS_NCTF<9>

I570

TRUE

I571

TRUE

PCH_VSS_NCTF<11>

I569

TRUE

PCH_VSS_NCTF<12>

70 70 70

B

NC_PCH_TP2

TRUE MAKE_BASE=TRUE

23

I500

TRUE

PCH_VSS_NCTF<15>

70

I499

TRUE

PCH_VSS_NCTF<17>

70

I501

TRUE

PCH_VSS_NCTF<19>

6 70

I502

TRUE

PCH_VSS_NCTF<19>

6 70

I503

TRUE

PCH_VSS_NCTF<21>

70

I504

TRUE

PCH_VSS_NCTF<25>

70

TRUE

PCH_VSS_NCTF<27>

70

TRUE

PCH_VSS_NCTF<29>

70

I505

NC_SDVO_TVCLKINP

8

TP_LVDS_IG_B_CLKN

8

TP_LVDS_IG_B_CLKP

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLP TP_LVDS_IG_BKL_PWM

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

TRUE

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE TRUE

NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

NC_SDVO_INTP SMC_BS_ALRT_L

7

SPI_ALT_CS_L LPC_SERIRQ


NC_SATA_B_D2RN

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

I506

TRUE

TRUE

16

TP_SATA_F_D2RP

7

TRUE

TRUE

NC_SATA_D_D2RN

TP_SATA_B_R2D_CP

63 70

FUNC_TEST

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

16

16

63 70

J5100: LPC+SPI Connector

NC_PSOC_P1_3

TP_SATA_B_R2D_CN

NC_HDA_SDIN1

TRUE

16

33


NC_PCIE_CLK100M_PE7P

16



TP_PCI_CLK33M_OUT3

63 70

TRUE

TRUE

TP_PCI_PME_L

63 70

TRUE

TRUE

NC_PCIE_CLK100M_PE7N

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TP_SATA_B_D2RP

33 33


TP_SATA_B_D2RN


FUNC_TEST TRUE

DP_INT_ML_F_N<0>


63 66

USB_CAMERA_N USB_CAMERA_P


16

NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE


16

NC_CRT_IG_DDC_DATA

NC_CRT_IG_HSYNC



NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK


MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TP_PSOC_P1_3


TP_LVDS_IG_CTRL_DATA

FUNC_TEST

18 40

USB_EXTD_N

TRUE

9

TRUE MAKE_BASE=TRUE TRUE

NC_CRT_IG_GREEN


TP_LVDS_IG_CTRL_CLK

TRUE

TRUE

NC_CRT_IG_BLUE


FUNC_TEST

44 52

9

=PEG_D2R_N<15..4>


TP_PCIE_CLK100M_PE4P 16

NO_TEST

(Need 2 TPs)

=SMBUS_BATT_SCL

TRUE

A

51 52 74

TRUE

9

=PEG_D2R_P<15..4>

MAKE_BASE=TRUE

51 52 74

TRUE

AUD_I2C_INT_L

TRUE

NC_PEG_D2RN<15..4>

7 52

39 40 62

TRUE

NC_PEG_D2RP<15..4>

41 42 49

=USB_PWR_EN

AUD_IP_PERIPHERAL_DET

=PEG_R2D_C_N<15..4>

MAKE_BASE=TRUE MAKE_BASE=TRUE

TRUE

TRUE

B

SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT (Need to add 3 GND TPs)

TRUE

TRUE

NC_PEG_R2D_CN<15..4>

J6903: Speaker Connector

TRUE

TRUE

9

MAKE_BASE=TRUE 49 74


FUNC_TEST

AUD_IPHS_SWITCH_EN

D

=PEG_R2D_C_P<15..4>


J4700: LIO Connector

TP_CPU_RSVD<8..27>

TRUE

NC_PEG_R2D_CP<15..4>

7 49

FUNC_TEST

TRUE

TP_CPU_RSVD<30..45>

J6900: DC-In Connector


C

TP_CPU_THERMDC

TRUE

49

TRUE

TRUE

TP_CPU_THERMDA

TRUE

49

TRUE

J4501: SATA SSD Connector

TP_EDP_AUX_N

TRUE

MAKE_BASE=TRUE

TRUE


TRUE

MAKE_BASE=TRUE

NC_CPU_RSVD<8..27>

TRUE

9

TP_EDP_AUX_P

TRUE

NC_CPU_RSVD<30..45>

J5700: IPD Flex Connector

24 37 69

9

TP_EDP_TX_N<0..3>

TRUE

MAKE_BASE=TRUE

FUNC_TEST

24 37 69

TP_EDP_TX_P<0..3>

TRUE

MAKE_BASE=TRUE

NC_CPU_THERMDA

(Need to add 2 GND TP)

16 37 70 16 37 70

TRUE

MAKE_BASE=TRUE

TRUE

TRUE

49

KBDLED_ANODE

NC_CPU_THERMDC

=PP3V42_G3H_TPAD USB_TPAD_CONN_P

TRUE

KBDLED_FB

(Need to add 1 GND TP)

PCIE_AP_D2R_N PCIE_WAKE_L

TRUE

NC_EDP_TXP<0..3> MAKE_BASE=TRUE NC_EDP_TXN<0..3> MAKE_BASE=TRUE NC_EDP_AUXP MAKE_BASE=TRUE NC_EDP_AUXN

J5715: KB BKLT CONNECTOR

1

TRUE MAKE_BASE=TRUE

NC_SMC_BS_ALRT_L

NC_TP_XDP_PCH_OBSFN_A<0..1> NC_TP_XDP_PCH_OBSFN_B<0..1> NC_TP_XDPPCH_HOOK2 NC_TP_XDPPCH_HOOK3

S YN C_ MA ST ER =( K9 9_ ML B)

Functional Test / No Test DRAWING NUMBER

NC_TP_XDP_PCH_OBSFN_D<0..1>

Apple Inc.

NC_TP_XDP_PCH_HOOK4 NC_TP_XDP_PCH_HOOK5

S YN C_ DA TE =( 02 /1 6/ 20 10 )

PAGE TITLE

051-8870 3.13.0


BRANCH

NC_PCH_GPIO65_CLKOUTFLEX1


PAGE


SIZE

REVISION

R



7 OF 109

D

A

8

7

6

"G3Hot" (Always-Present) Rails 53

=PPBUS_G3H

PPBUS_G3H

55

=PP3V3_S5_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE

PPVIN_SW_T29BST VOLTAGE=12.8V

5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

46

=PPVIN_S5_HS_COMPUTING_ISNS

61

45

=PP3V3_S3_P3V3S3FET

61

=PPVIN_SW_T29BST

8 36

=PP3V3_S5_CPU_VCCDDR

26

46

=PP3V3_S5_LCD

63

=PPVIN_S5_P5VP3V3

55

=PP3V3_S5_PCH

17 19

=PP3V3_S5_PCHPWRGD

25

=PP3V3_S5_SMCBATLOW

42

=PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG

52 6

=PP18V5_DCIN_CONN

=PP3V3_S5_SYSCLK

=PP3V42_G3H_REG

C

49

PPDCIN_G3H

=PP3V3_S4_DPAPWRSW

65

6

=PP3V3_S4_SMC

42

25

=PPVRTC_G3_OUT

=PP3V3_SUS_PCH_VCCSUS_USB

20 22

=PP3V3_SUS_PCH_VCCSUS_GPIO

20 22

=PP3V3_S5_SMC

41 42

=PP3V3_SUS_PCH_VCCSUS

20

=PP3V42_G3H_CHGR

53

=PP3V3_SUS_GPIO

16 17 18 19

=PP3V42_G3H_PWRCTL

62

=PP3V3_SUS_PCH

22

=PP3V42_G3H_SMBUS_SMC_BSA

44

=PP3V3_SUS_PWRCTL

62

=PP3V42_G3H_SMCUSBMUX

39

=PP3V3_SUS_P1V05SUSLDO

60

=PP3V42_G3H_TPAD

6 49

=PP3V3_SUS_SMC

42

42 25

6 40

PPVRTC_G3H

61

=PP3V3_S3_FET

=PPVRTC_G3_PCH

PP5V_S5

=PP5V_S5_P1V5DDRFET

61

=PP5V_SUS_FET

=PP5V_S3_REG

26 44 44

16 17 20

61

=PPVIN_S0_DDRREG_LDO

56

PP1V5_S3RS0

=PP1V5_S0_REG

10 12 15 26

=PP1V5_S3RS0_VMON

62

=PP3V3R1V5_S0_PCH_VCCSUSHDA

16 20 22

56 31

=PPVTT_S3_DDR_BUF

PPVTTDDR_S3

=PPVTT_S0_DDR_LDO

PP0V75_S0_DDRVTT

24 31

=PP0V75_S0_MEM_VTT_A

32

=PP3V3_S3_WLAN

37

=PP0V75_S0_MEM_VTT_B

32

=PP3V3_S3_WLANISNS

46

=PPVTT_S0_VTTCLAMP

26

=PP3V3_S3_BMON_ISNS

46

=PP3V3_S3_PCH_GPIO

18 19

=PP3V3_S3_1V5S3ISNS

46

=PP3V3_S3_DBGLEDS

52

=PPVCCSA_S0_REG

PPVCCSA_S0_CPU

=PP1V05_SUS_LDO

12 15

PP1V05_SUS

6

45

6 40 66

=PP3V3_S0_HS_COMPUTING_ISNS

46

=PP3V3_S0_CPUTHMSNS

47

=PP3V3_S0_CPU_VCCIO_SEL

12

=PP3V3_S0_DP_DDC

8

=PP3V3_S0_FAN

48

=PP1V05_S0_PCH

16 22

=PP3V3_S0_P3V3T29FET

36

=PP1V05_S0_PCH_VCCIO

20 22

60

=PP1V05_S0_PCH_VCCIO_PCIE

17

=PP3V3_S0_P1V8S0

=PP5V_S3_P5VS0FET =PP5V_S3_RTUSB =PP5V_S3_LIO_CONN

=PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO 51 56 26 61 39

6 52

PP5V_S0

=PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_VCC3_3_GPIO =PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC

=PPCPUVCCIO_S0_REG ? mA

23

PP1V05_S0

6

=PP1V05_S0_PCH_VCCIO_PLLPCIE =PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCASW

22

=PP1V05_S0_PCH_VCCIO_USB

20 22

=PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_VMON

20 22

=PP1V05_S0_PCH_VCCIO_CLK

20 22

=PP1V05_S0_PCH_VCCSSC

20 22

=PP3V3_S0_PWRCTL

62

=PP1V05_S0_PCH_V_PROC_IO

20 22 20

25 25

=PP1V05_S0_PCH_VCC_DMI

20 22

=PP1V05_S0_PCH_VCCIO_PLLFDI

20

44

=PP1V05_S0_PCH_VCCDMI_FDI

20

=PP5V_S0_CPUIMVP

57

=PP3V3_S0_SMBUS_SMC_B_S0

44

=PPVCCIO_S0_XDP

23

=PP5V_S0_CPUVCCIOS0

59

=PP3V3_S0_SMC

42

=PPVCCIO_S0_SMC

41

=PP5V_S0_FAN

6 48

=PP3V3_S0_HDD

38


36

6 43

=PP3V3_S0_HDDISNS

46

=PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS

6

B

16 20 22

=PP3V3_S0_SB_PM

=PP3V3_S0_DPSDRVA

PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

57

=PP1V05_S0_PCH_VCCIO_PLLUSB

49

=PP1V8_S0_CPU_VCCPLL_R

20 22

16 17 19

62

6

62

44

=PP5V_S0_KBDLED

PP1V05_S0_CPU_VCCPQE

20 22

=PP3V3_S0_SMBUS_SMC_0_S0

22

=PP1V05_S0_CPU_VCCPQE

20 22

=PP3V3_S0_SMBUS_PCH

=PP5V_S0_PCH =PP5V_S0_VMON

6

20 22

=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_VMON =PP3V3_S0_P1V5S0 =PP3V3_S0_T29PWRCTL

45

PP1V5_S3_CPU_VCCDQ

16 20 22

66

54

9 12 15

=PPGFXVCORE_S0_VSENSE

9 10 12 14

=PP5V_S0_BKL

=PP5V_S0_LPCPLUS =PP5V_S0_VCCSA

6

=PPVCORE_S0_CPU_VCCAXG

20

22

20 22

PPVCORE_S0_AXG

C

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

18

16 19 22

45


14 12

=PP1V05_SUS_PCH_JTAG

=PPVCCIO_S0_CPUIMVP =PP1V05_S0_PCH_VCCDIFFCLK

=PP3V3_S0_RSTBUF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE


59

9 12 14

=PPCPUVCORE_S0_VSENSE


14 12

=PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

22

VOLTAGE=3.3V MAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDQ

6


60

6

=PPVCORE_S0_CPU


15 12

54

6 74

=PPVCORE_S0_AXG_REG

6

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

=PP3V3_S0_BKL_VDDIO

PP5V_S3

PPVCORE_S0_CPU

6

=PP3V3_S0_AUDIO

6

=PPVCORE_S0_CPU_REG


58

56

20

Chipset "VCore" Rails


8 24

6


=PP1V05_S0_PCH_VCCADPLL

58

6 40

35

PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_LDO

6

=PP3V3R1V5_S0_AUDIO

=PP3V3_S0_CPUVCCIOISNS

PP5V_SUS


1V05 S0 LDO

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP3V3_S3_VREFMRGN

PP3V3_S0

D

=PP1V05_T29_RTR

60


PP1V5_S0

=PP1V05_T29_FET

6 68

49

=PP5V_S3_MEMRESET

A

=PP3V3_S0_FET

=PP1V5_S3_P1V5S3RS0_FET

61

=PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG

61

61

29 30 32

=PP5V_S5_TPAD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_FET

33

=PP3V3_S3_SMBUS_SMC_MGMT

61

27 28 32

=PP1V5_S3_MEM_B

=PP5V_S5_P5VSUSFET

=PP5V_SUS_PCH

55

6 37

=PP3V3_S3_CARDREADER =PP3V3_S3_SMBUS_SMC_A_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

B

=PP3V3_S3_BT =PP3V3_S3_MEMRESET


36 26

=PP1V5_S3_MEM_A

6

=PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET

6

6

6 68

=PP1V5_S3_MEMRESET


6

5V Rails =PP5V_S5_LDO

PP1V5_S3


60

PP3V3_S3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

=PP1V5_S3RS0_FET

6

6 43

=PP3V42_G3H_ONEWIRE

=PPDDR_S3_REG


=PP3V3_S5_LPCPLUS

=PPVBAT_G3_SYSCLK

60


61


55

56 62

PP3V3_SUS

25

6 36

61

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

65

PP3V3_T29 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP1V05_T29

20 22

=PP3V3_S5_TPAD

=PP3V3_SUS_FET

=PP3V3_T29_FET

16 19

=PP3V3_S5_P3V3SUSFET

=PPVIN_S5_SMCVREF

=PP1V8_S0_P1V5S0

36 20

34 35 36

=PP3V3_S5_PCH_VCC_SPI

61

60

25

58

6

18 20 22

=PP1V8_S0_P1V05S0LDO

6

=PPHV_SW_DPAPWRSW

=PP3V3_T29_PCH_GPIO

54

45

=PP1V8_S0_PCH_VCC_DFTERM

PP15V_T29 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE

=PP3V3_T29_RTR

59

PP3V42_G3H

14

62

56

=PPDCIN_S5_VSENSE

=PP1V8_S0_CPU_VCCPLL

=PP15V_T29_REG

25

=PPVIN_S0_CPUAXG


36 8

=PPVDDIO_T29_CLK

=PPVIN_S0_VCCSAS0

53

6

20 22

=PPVIN_S0_CPUVCCIOS0

=PPDCIN_S5_CHGR

PP1V8_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE

=PP1V8R1V5_S0_PCH_VCCVRM =PPVDDIO_S0_SBCLK

24

=PP3V3_S5_VMON =PP3V3_S5_PWRCTL

57 58

=PP1V8_S0_REG 2A max supply

50

=PP3V3_S5_USB_RESET =PP3V3_S5_PCH_VCCDSW


52

60

=PPVIN_S5_HS_COMPUTING_ISNS_R

6

1

T29 Rails (off when no cable) 23

=PP3V3_S0_P3V3S0FET

PPBUS_S5_HS_COMPUTING_ISNS

2


=PP3V3_S5_XDP 66

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE

3

6 74

=PP3V3_S5_ROM

D

4

1.8V/1.5V/1.2V/1.05V Rails

PP3V3_S5

=PPBUS_S0_VSENSE

=PPBUS_S0_LCDBKLT

36 6

www.laptopblue.vn 3.3V Rails

6 52

62 60 36 64 60

SYNC_MASTER=K91_MLB

23

=PP3V3_S0_T29I2C

44

=PP3V3_S0_BKLTISNS

46

=PP3V3_S0_SYSCLKGEN

25


PAGE TITLE

Power Aliases

45

=PP3V3_S0_XDP

DRAWING NUMBER

Apple Inc.

SIZE

051-8870 REVISION

3.13.0

R


BRANCH


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D

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6

5

4

3

CPU signals MEMVTT_EN

26

Plated Board Slot

=DDRVTT_EN

9

=PEG_R2D_C_P<3..0>

67

PEG_R2D_C_P<3..0>

9

=PEG_R2D_C_N<3..0>

67

PEG_R2D_C_N<3..0>

9

=PEG_D2R_P<3..0>

67

PEG_D2R_P<3..0>

9

=PEG_D2R_N<3..0>

67

PEG_D2R_N<3..0>

26 56

MAKE_BASE=TRUE

2

1 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

34 70

PCIE_T29_R2D_C_N<3..0>

34 70

PCIE_T29_D2R_P<3..0>

34 70

PCIE_T29_D2R_N<3..0>

34 70

MAKE_BASE=TRUE

DP_EXTA_ML_C_P<3..0>

70 64

69

DP_IG_ML_P<3..0>

TP_DP_IG_B_MLP<3..0>

17

69

DP_IG_ML_N<3..0>

TP_DP_IG_B_MLN<3..0>

17

69

DP_IG_AUX_CH_P

DP_IG_B_AUX_P

17

69

DP_IG_AUX_CH_N

DP_IG_B_AUX_N

17

MAKE_BASE=TRUE

SL0900

DP_EXTA_ML_C_N<3..0>

70 64

TH-NSP

MAKE_BASE=TRUE

1

=PP3V3_S0_DP_DDC

8 7

DP_EXTA_AUXCH_C_P

70 64

17

1

DP_EXTA_AUXCH_C_N

70 64

R0921

2 .2 K

2 .2 K

5% 1/20W MF 201 2

CPU Heat Sink Mounting Bosses

PCIE_EXCARD_D2R_N

16

16

PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N

16

PCIE_EXCARD_R2D_C_P

16

Z0913

Z0910

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

1

1

Z0911

70 16

Z0912

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

PCIE_CLK100M_EXCARD_N

70 16

PCIE_CLK100M_EXCARD_P

70 16

PEG_CLK100M_P

70 16

PEG_CLK100M_N

NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_R2D_CN

17

TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA

NC_PCIE_EXCARD_R2D_CP

17

TP_DP_IG_D_CTRL_CLK

NC_PCIE_CLK100M_EXCARDN

17

TP_DP_IG_D_CTRL_DATA

17


MEM_A_CLK_P<1>

68 11

MEM_A_CLK_N<1>

68 11

MEM_A_CKE<1>

68 11

MEM_A_CS_L<1>

68 11

Fan Boss

X21 Boss

Z0905

SSD Boss

Z0914

STDOFF-4.5OD1.8H-SM

Z0915

STDOFF-4.5OD1.9H-SM

STDOFF-4.5OD1.9H-SM

1

1

860-1327

MEM_B_CLK_P<1>

68 11

MEM_B_CLK_N<1>

68 11

1

860-1327

68 11

NC_PEG_CLK100MN

860-1327

68 11

MEM_B_CS_L<1>

68 11

MEM_B_ODT<1>

68 11

MEM_A_A<15>

68 11

MEM_B_A<15>

1

NC_MEM_A_CKE<1>

MAKE_BASE=TRUE

64

NC_MEM_A_CS_L<1>

EMI I/O Pogo Pins

MAKE_BASE=TRUE

NC_MEM_A_ODT<1>

MAKE_BASE=TRUE

64

64

TP_MEM_B_CLKN<1>

MAKE_BASE=TRUE

CRITICAL

ZS0906 POGO-2.0OD-3.6H-K86-K87

SM

SM

1

17

TP_DP_IG_D_HPD

1

100K

1

R0925 2.2K 5% 1/20W MF 201

2

LVDS Aliases 6

2

DP_IG_B_DDC_DATA

17

DP_IG_B_HPD

17

10 67

2

66

CRITICAL

MAKE_BASE=TRUE

3

74 46

OUT

69

LVDS_IG_B_DATA_P<0..3>

69

LVDS_IG_B_DATA_N<0..3>

69

LVDS_IG_A_DATA_P<3>

69

LVDS_IG_A_DATA_N<3>

69

LVDS_IG_BKL_PWM

17

LVDS_IG_PANEL_PWR

17

LVDS_IG_BKL_ON

17

NO_TEST=TRUE

MAKE_BASE=TRUE

1

OUT

69

LVDS_IG_B_CLK_N

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>


74 46

LVDS_IG_B_CLK_P

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

10 67

DPLL_REF_CLKP

TP_LVDS_IG_B_CLKN NC_LVDS_IG_B_DATAP<0..3>

0.5% 1W MF 0612-1

NO_TEST=TRUE

LCD_BKLT_PWM MAKE_BASE=TRUE

R0910 66

TP_LVDS_IG_B_CLKP MAKE_BASE=TRUE

6

17

63

0.01

DPLL_REF_CLK_P

34 72

R0909

100K 5% 1/20W MF 201

DPLL_REF_CLKN

D

34 72

DP_IG_D_HPD

NC_LVDS_IG_A_DATAP<3>

TP_MEM_B_A<15>

DPLL_REF_CLK_N

34 72

DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_MEM_A_A<15>

MAKE_BASE=TRUE

34 72

DP_T29SNK0_ML_C_N<3..0>

MAKE_BASE=TRUE

R0908

LCD_IG_PWR_EN MAKE_BASE=TRUE

66

LCD_BKLT_EN

2

PPBUS_SW_BKL

4

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.37 5 MM VOLTAGE=12.6V MAKE_BASE=TRUE

ISNS_LCDBKLT_P

=PPBUS_SW_BKL

ISNS_LCDBKLT_N

NC_USB_HUB1_OCS4

66

=USB_HUB1_OCS4

NC_USB_HUB2_OCS4

24

=USB_HUB2_OCS4

24

SATA Aliases Unused SATA ODD Signals

MAKE_BASE=TRUE

870-1938

C

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

870-1938

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_MEM_B_ODT<1>

MAKE_BASE=TRUE

34

DP_T29SNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_EXTA_HPD

NC_MEM_B_CS_L<1>

MAKE_BASE=TRUE

CRITICAL

ZS0905

MAKE_BASE=TRUE

TP_DP_IG_C_AUXP TP_DP_IG_C_AUXN

1

USB/SD Card Pogo

POGO-2.0OD-3.6H-K86-K87

MAKE_BASE=TRUE

5% 1/20W MF 201 2

DP_IG_B_DDC_CLK

DP_EXTA_DDC_DATA

NC_MEM_B_CKE<1>

MAKE_BASE=TRUE

TP_PCH_CLKOUT_DPP

17

MAKE_BASE=TRUE

MAKE_BASE=TRUE 16

17

MAKE_BASE=TRUE

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

DP_EXTA_DDC_CLK

MAKE_BASE=TRUE

DisplayPort Pogo

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

C

TP_DP_IG_C_MLP<3..0>

17

DP_IG_D_CTRL_DATA

5% 1/20W MF 201

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

TP_PCH_CLKOUT_DPN

DP_T29SNK0_HPD

17

DP_IG_D_CTRL_CLK

R0924

TP_MEM_A_CLKP<1> MAKE_BASE=TRUE

MEM_B_CKE<1>

5% 1/20W MF 201 2

=PP3V3_S0_DP_DDC

8 7

NC_PEG_CLK100MP MAKE_BASE=TRUE

MEM_A_ODT<1>

2.2K

5% 1/20W MF 201 2

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDP

2.2K 68 11

1

R0923

2.2K

DP_IG_C_CTRL_CLK MAKE_BASE=TRUE DP_IG_C_CTRL_DATA

1

4x 860-1327

1

R0922

5% 1/20W MF 201 2

NC_PCIE_EXCARD_D2RN

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE 1

1

R0920

MAKE_BASE=TRUE

D

TP_DP_IG_C_HPD MAKE_BASE=TRUE

MAKE_BASE=TRUE

SL-2.3X3.9-2.9X4.5

T29 DP Ports

69 16

IN

SATA_ODD_R2D_C_P

69 16

IN

SATA_ODD_R2D_C_N

OUT

SATA_ODD_D2R_P

OUT

SATA_ODD_D2R_N

T29_A_BIAS caps

NC_SATA_ODD_R2DCP MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_R2DCN MAKE_BASE=TRUE

NO_TEST=TRUE

SIGNAL_MODEL=EMPTY

R0926

DisplayPort PCB Stiffener

65 8

T29_A_BIAS_R

1

51

69 16

2

T29_A_BIAS_D2RP1

69 16 5%

(Provides PCB support for small finger above J9400)

T29BST:N 36 7

=PPVIN_SW_T29BST

1

0

1

1/20W

=PP15V_T29_REG

2

7 36

10% 10V

MAKE_BASE=TRUE

2

NO_TEST=TRUE

SIGNAL_MODEL=EMPTY

X5R 201

1/8W MF-LF

SM-SP

805

1

SIGNAL_MODEL=EMPTY

R0927

806-1176 65 64

65 8

T29_A_BIAS

T29_A_BIAS_R

1

51

2

T29_A_BIAS_D2RN1

5%

1

1/20W

Digital Ground GND

0.01UF

201

10%

0.01UF 10% 10V X5R 201

65

C0907

MF

C0960 1

B

NO_TEST=TRUE

NC_SATA_ODD_D2RN

0.01UF

5%

STIFFENER-K16-K99

MAKE_BASE=TRUE

C0906

MF 201

R0960 NO STUFF

MT0900

65

NC_SATA_ODD_D2RP

10V X5R

2

SIGNAL_=EMPTY

B

201

2

T29_A_BIAS caps

VOLTAGE=0V MIN_NECK_WIDTH=0.075MM MIN_LINE_WIDTH=0.6MM

SIGNAL_MODEL=EMPTY

R0931 65 8

T29_A_BIAS_R

51

1

T29_A_BIAS_R2DP0

2

5% 1/20W MF 201

T29 Can Slots

1

64

DP_A_BIAS caps

C0901 0.01UF 10% 10V X5R 201

2

SIGNAL_MODEL=EMPTY

64

DP_A_BIAS_P_2

SL0901 TH-NSP 1

SL0902 TH-NSP 1

SL-1.1X0.4-1.4X0.7

SL-1.1X0.4-1.4X0.7

SL0903

SL0904

R0932 65 8

T29_A_BIAS_R

51

1

2

T29_A_BIAS_R2DN0

5% 1/20W MF 201

1

1

64

SL0905 TH-NSP 1 S L -1 . 1X 0. 4 5- 1 .4 X0 . 75

2

TP_DDRREG_PGOOD

P1V5S3RS0_RAMP_DONE

IN

61

DDRREG_PGOOD

IN

56

MAKE_BASE=TRUE

2

0.01UF 10% 10V X5R 201

R0990

SIGNAL_MODEL=EMPTY 23 19 64

TH-NSP

DP_A_BIAS_N_2

64

IN

DP_A_BIAS_N_0

JTAG_ISP_TCK

JTAG_T29_TCK_R

1

0

2

JTAG_T29_TCK

MAKE_BASE=TRUE

OUT

34

5% 1/20W MF

1 SL-1.1X0.45-1.4X0.75

SIGNAL_MODEL=EMPTY

1

R0933 65 8

A

10% 10V X5R 201

T29 JTAG

SIGNAL_MODEL=EMPTY

SL-1.1X0.45-1.4X0.75

TP_P1V5S3RS0_RAMP_DONE MAKE_BASE=TRUE

0.01UF

C0902

2

TH-NSP

C0964 1

0.01UF 10% 10V X5R 201

Unused PGOOD signal

DP_A_BIAS_P_0

64

C0962 1 SIGNAL_MODEL=EMPTY

T29_A_BIAS_R

1

51

2

SIGNAL_MODEL=EMPTY

1

0.01UF

T29_A_BIAS_R2DP1

5% 1/20W MF 201

SL0906 TH-NSP

C0905

1

2

64

C0908

19

IN

19

OUT

0.01UF

10% 10V X5R 201

2

10% 10V X5R 201

201

JTAG_ISP_TDI

2

10% 10V X5R 201

JTAG_ISP_TDO

51

34

SYNC_MASTER=K91_MLB

T29 Aliases

2

24 7

T29_A_BIAS_R2DN1 1

2

10% 10V X5R 201

Signal Aliases

=PP3V3_S3_USB_HUB

DRAWING NUMBER 1

R0915

64

10K

C0904 0.01UF

5% 1/20W MF 201

NO STUFF

SIGNAL_MODEL=EMPTY 69 64

T29_A_RSVD_N

69 64

T29_A_RSVD_P


PAGE TITLE

Unused USB ports

5% 1/20W MF 201

IN

MAKE_BASE=TRUE

SIGNAL_MODEL=EMPTY

R0934 1

34

JTAG_T29_TDO

MAKE_BASE=TRUE

C0903

SIGNAL_MODEL=EMPTY

T29_A_BIAS_R

OUT

0.01UF

1 S L -1 . 1X 0 .4 5- 1 .4 X 0. 75

65 8

JTAG_T29_TDI

R0917 201 R09181/20W 201 1/20W

0 0

1

2 5%

1

2 5%

MF MF

Apple Inc.

1

R0916 10K

2

2

USB_T29A_N

24 69

USB_T29A_P

24 69

SIZE

051-8870 REVISION

3.13.0

R

5% 1/20W MF 201


BRANCH


PAGE

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D

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6

5

4

3

OMIT_TABLE

67

D

IN

67 17

IN

67 17

IN

67 17

IN

67 17

IN

67 17

IN

67 17

IN

67 17

IN

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT OUT

67 17

OUT OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

OUT

67 17

IN

67 17

IN

67 17 14 12 10 9 7

OUT

67 17

67 17

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

OUT

67 17

67 17

C

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

R1030 1

24.9 1% 1/20W MF 201

67 17

IN

67 17

IN

2

70 63 70 63

6 6

70 63 70 63

B

6 6

Intel Doc 438297 Huron River SFF DG rev1.0

DMI_RX_1*

SANDY-BRIDGE

PEG_ICOMPO

G1

P1

DMI_RX_2*

MOBILE-2C-35W

PEG_RCOMPO

G4

P10

DMI_RX_3*

BGA

(1 OF 9)

PEG_RX_0*

H22

DMI_RX_0

PEG_RX_1*

J21

DMI_RX_1

PEG_RX_2*

B22

P3

DMI_RX_2

PEG_RX_3*

D21

P11

DMI_RX_3

PEG_RX_4*

A19

PEG_RX_5*

D17

PEG_RX_6*

B14

PEG_RX_7*

D13

PEG_RX_8*

A11

PEG_RX_9*

B10

DMI_TX_0* DMI_TX_1*

N4

DMI_TX_2*

I M D

DMI_TX_3*

DMI_TX_0

PEG_RX_10*

G8

DMI_TX_1

PEG_RX_11*

A8

DMI_TX_2

PEG_RX_12*

B6

PEG_RX_13*

H8

PEG_RX_14*

E5

FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3>

U7

PEG_RX_15*

K7

EDP_HPD_L

FDI0_TX_1*

W1

FDI0_TX_2*

AA6

FDI0_TX_3*

W6

FDI1_TX_0*

V4

FDI1_TX_1*

Y2

FDI1_TX_2*

AC9

FDI1_TX_3*

U6

FDI0_TX_0

W10

FDI0_TX_1

W3

FDI0_TX_2

AA7

FDI0_TX_3

W7

FDI1_TX_0

T4

FDI1_TX_1

AA3

FDI1_TX_2

AC8

FDI1_TX_3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

FDI0_LSYNC

AG8

FDI1_LSYNC

AD2

EDP_ICOMPO

AF3

EDP_COMPIO

AG11

DP_INT_ML_P<0> DP_INT_ML_P<1> TP_EDP_TX_P<2> TP_EDP_TX_P<3>

E C A F R E T N I Y A L P S I D

S L A N G I S

E L B I X E L F

E C A F R E T N I

L E T N I

D E S A B S S E R P X E I C P

FIXME: Pin should be EDP_HPD* T EDP_HPD R

AG4

EDP_AUX*

AF4

EDP_AUX

O P

AC3

EDP_TX_0*

AC4

EDP_TX_1*

AE11

EDP_TX_2*

AE7

EDP_TX_3*

AC1

EDP_TX_0

AA4

EDP_TX_1

AE10

EDP_TX_2

AE6

S L A N G I S

FDI_INT

AA10

DP_INT_AUX_CH_N DP_INT_AUX_CH_P DP_INT_ML_N<0> DP_INT_ML_N<1> TP_EDP_TX_N<2> TP_EDP_TX_N<3>

FDI0_TX_0*

W11

U11

FDI_LSYNC<0> FDI_LSYNC<1> EDP_COMP

DMI_TX_3

Y A L P S I D D E D D E B M E

EDP_TX_3

section 2.2.1 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal. Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor

(refer to latest Processor EDS for DC specifications). If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard. This signal can be left as no-connect if entire eDP interface is disabled.

67 23 9 67 23 9 67 23 9 67 23 9 67 23 9

NOSTUFF

1

67 23 9 67 23 9 67 23 9

EDP

1

R1042

R1044

1K

1K

5%

A

23 9

CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4> CPU_CFG<2> 1

R1040

R1047

1K

1K

5%

5%

1/16W

402

402

5%

1/16W

MF-LF

2

402

PEG_RX_0

K22

PEG_RX_1

K19

PEG_RX_2

C21

PEG_RX_3

D19

PEG_RX_4

C19

PEG_RX_5

D16

PEG_RX_6

C13

PEG_RX_7

D12

PEG_RX_8

C11

PEG_RX_9

C9

PEG_RX_10

F8

PEG_RX_11

C8

PEG_RX_12

C5

PEG_RX_13

H6

PEG_RX_14

F6

PEG_RX_15

K6

PEG_TX_0*

G22

PEG_TX_1*

C23

PEG_TX_2*

D23

PEG_TX_3*

F21

PEG_TX_4*

H19

PEG_TX_5*

C17

PEG_TX_6*

K15

PEG_TX_7*

F17

PEG_TX_8*

F14

PEG_TX_9*

A15

PEG_TX_10*

J14

PEG_TX_11*

H13

PEG_TX_12*

M10

PEG_TX_13*

F10

PEG_TX_14*

D9

PEG_TX_15*

J4

PEG_TX_0 PEG_TX_1

F22

PEG_TX_2

D24

PEG_TX_3

E21

PEG_TX_4

G19

PEG_TX_5

B18

PEG_TX_6

K17

PEG_TX_7

G17

PEG_TX_8

E14

=PEG_D2R_N<0> =PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3> =PEG_D2R_N<4> =PEG_D2R_N<5> =PEG_D2R_N<6> =PEG_D2R_N<7> =PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10> =PEG_D2R_N<11> =PEG_D2R_N<12> =PEG_D2R_N<13> =PEG_D2R_N<14> =PEG_D2R_N<15> =PEG_D2R_P<0> =PEG_D2R_P<1> =PEG_D2R_P<2> =PEG_D2R_P<3> =PEG_D2R_P<4> =PEG_D2R_P<5> =PEG_D2R_P<6> =PEG_D2R_P<7> =PEG_D2R_P<8> =PEG_D2R_P<9> =PEG_D2R_P<10> =PEG_D2R_P<11> =PEG_D2R_P<12> =PEG_D2R_P<13> =PEG_D2R_P<14> =PEG_D2R_P<15> =PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7> =PEG_R2D_C_N<8> =PEG_R2D_C_N<9> =PEG_R2D_C_N<10> =PEG_R2D_C_N<11> =PEG_R2D_C_N<12> =PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15> =PEG_R2D_C_P<0> =PEG_R2D_C_P<1> =PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4> =PEG_R2D_C_P<5> =PEG_R2D_C_P<6> =PEG_R2D_C_P<7> =PEG_R2D_C_P<8> =PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14> =PEG_R2D_C_P<15>

A23

PEG_TX_9

C15

PEG_TX_10

K13

PEG_TX_11

G13

PEG_TX_12

K10

PEG_TX_13

G10

PEG_TX_14

D8

PEG_TX_15

K4

Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals. OMIT_TABLE

=PP1V05_S0_CPU_VCCIO

2

CRITICAL 7 9 10 12 14

IN

8

IN

8

IN

8

IN

8

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

NOSTUFF

IN

6

R1064

IN

6

49.9

49.9

IN

6

IN

6

1% 1/20W MF 201

1% 1/20W MF 201

IN

6

IN

6

=PPVCORE_S0_CPU

1

2

R1070

2

PLACE_NEAR=U1000.H45:50.8MM PLACE_SIDE=BOTTOM Note. VOLTAGE=1.25V

8 8

IN

8

Note. VOLTAGE=1.05V

IN

8

Note. VOLTAGE=0V

IN

6

IN

6

IN

6

IN

6

IN

6

Note. VOLTAGE=0V

NOSTUFF

6 6

IN

6

IN

6

IN

6

IN

6

IN

67 23 9

IN

67 23 9

IN

67 23 9

IN

67 23 9

IN

67 23 9

IN

67 23 9

IN

67 23

IN

67 23

IN

67 23

IN

67 23

IN

7 12 15

1

IN

IN

67 23 9

23 67

IN

67 23

IN

67 23

IN

67 23

IN

23 9

IN

23

IN

NOSTUFF

IN

IN

IN

7 12 14


NOSTUFF

1

R1065

49.9 1% 1/20W MF 201

67 23 9

49.9 1% 1/20W MF

2

BGA

E G D I R B Y D N A S

A51 CFG_4 C53 CFG_5 C55 CFG_6 H49 CFG_7 A55 CFG_8 H51 CFG_9 K49 CFG_10 K53 CFG_11

OUT

RSVD_31 L42 NC RSVD_33 L47 NC RSVD_34 M13 NC RSVD_35 M14 NC RSVD_36

Intel validation sense lines per

NC

RSVD_40 K24 NC RSVD_41 AH2 NC RSVD_42 AG13

NC

NC RSVD_43 AM14 RSVD_44 AM15 NC

RSVD_45

VSS_VAL_SENSE

DC_TEST_A4

H48 RSVD_6 K48 RSVD_7

N50

NC

A4

DC_TEST_C4 C4

TP_CPU_DC_TEST_A4 CPU_DC_TEST_C4_D3

DC_TEST_D3 D3 DC_TEST_D1 D1

BA19 RSVD_8

PLACE_NEAR=U1000.K43:50.8MM PLACE_SIDE=BOTTOM

U14

RSVD_37 W14 NC RSVD_38 P13 NC

D52 CFG_16 L53 CFG_17

NC AV19 NC AT21 NC BB21 NC BB19 NC AY21 NC BA22 NC AY22 NC AU19 NC AU21 NC BD21 NC BD22 NC BD25 NC BD26 NC BG22 NC BE22 NC BG26 NC BE26 NC BF23 NC BE24 NC

2 201

D

RSVD_32 L45 NC

L51 CFG_14 F51 CFG_15

F48 VCC_DIE_SENSE

74 47

W 5 3 C 2 E L I B O M

RSVD_39 AT49 NC

TP_CPU_VCC_DIE_SENSE CPU_THERMD_P CPU_THERMD_N

9

RSVD_30 N42 NC

F53 CFG_12 G53 CFG_13

H45 VAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE

OUT

CPU_MEM_VREFDQ_A

RSVD_29 BG7 NC

(5 OF 9) RESERVED

CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N

74 47

RSVD_28 BE7

U1000

B54 CFG_2 D53 CFG_3

H43 VCC_VAL_SENSE K43

PLACE_NEAR=U1000.K45:50.8MM PLACE_SIDE=BOTTOM

NOTE:

B50 CFG_0 C51 CFG_1

CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

1

R1071

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>

RSVD_9

A58

RSVD_10

DC_TEST_A58 DC_TEST_A59

RSVD_11

DC_TEST_C59 C59

RSVD_12

DC_TEST_A61

RSVD_13

DC_TEST_C61 C61

RSVD_14

D61

A59 A61

TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_A58 CPU_DC_TEST_C59_A59

C

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_D61 DC_TEST_D61 DC_TEST_BD61 BD61 TP_CPU_DC_TEST_BD61 DC_TEST_BE61 BE61 CPU_DC_TEST_BE59_BE61

IN

6

OUT

8

OUT

8

OUT

8

OUT

8

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

NOTE:

OUT

6

This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.

OUT

8

OUT

8

OUT

8

OUT

8

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

RSVD_15 RSVD_16

DC_TEST_BE59 BE59 DC_TEST_BG61 BG61

RSVD_17 RSVD_18 RSVD_20

DC_TEST_BG59 BG59 DC_TEST_BG58 BG58

RSVD_21

DC_TEST_BG4 BG4

RSVD_22

DC_TEST_BG3 BG3

RSVD_23

DC_TEST_BE3 BE3

RSVD_24

DC_TEST_BG1 BG1

RSVD_25 RSVD_26

DC_TEST_BE1 DC_TEST_BD1

RSVD_19

CPU_DC_TEST_BG59_BG61 TP_CPU_DC_TEST_BG58 TP_CPU_DC_TEST_BG4 CPU_DC_TEST_C4_BE3_BG3 CPU_DC_TEST_C4_BE1_BG1

BE1 BD1

TP_CPU_DC_TEST_BD1

RSVD_27

Intel is investigating future processor VREF_DQ generation to replace M1 and M2.

NOSTUFF

R1021 68 31 30 29 28 27

PP0V75_S3_MEM_VREFDQ_A

1

0 5% 1/20W MF 201

CPU_MEM_VREFDQ_A

2

9

B

1NOSTUFF

R1020 1K

2

1% 1/20W MF 201

402

=PP1V05_S0_CPU_VCCIO PLACE_NEAR=U1000.AG11:12.7MM

R1031 1K

N OS T UF F

N OS T UF F

1

1

R1041

R1043

1K

1K

402

5%

402

1

R1049 5%

SSM3K15FV

MF-LF

2

402

5% 1/20W MF 201

EDP_HPD_L

Q1031

1K 1/16W

MF-LF

2

2

NOSTUFF

1/16W

MF-LF

2

9 7

1

1/16W

MF-LF

2

14 12 10

5%

1/16W

MF-LF

2

1

1K

5%

1/16W

MF-LF

2

CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>

NOSTUFF

1

24.9

1

CPU_CFG<16>

NOSTUFF

R1046

1/16W

402

NOSTUFF

1K

MF-LF

2

1

R1045

5%

1/16W MF-LF 402

NOSTUFF

1

1% 1/20W MF 201

P7

M8

CPU_PEG_COMP PLACE_NEAR=U1000.G3:12.7MM

N3

T3

PLACE_NEAR=U1000.AF3:12.7MM

70 63

P6

P4

FDI_INT

9

G3

M7

FDI_FSYNC<0> FDI_FSYNC<1>

70 63

PEG_ICOMPI

K3

FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>

67

U1000

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3>

IN

DMI_RX_0*

R2

FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>


M2

K1

NOTE:

R1010

CRITICAL

DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>

67 17

2

9

D 3

A

SOD-VESM-HF

2

PAGE TITLE

CPU DMI/PEG/FDI/RSVD 1 These can be Placed close to

J2500 and Only for debug access 63

FOR SANDYBRIDGE PROCESSOR CFG [7] :PEG DEFER TRAINING

G

S 2

DRAWING NUMBER

Apple Inc.

DP_INT_HPD

CFG [6:5] :PCIE BIFURCATION

11 = 1 X16 (DEFAULT)

CFG [4] :eDP ENABLE/DISABLE

1 = DISABLED

CFG [3] :PCIE x4 LANE REVERSAL

1

10 = 2 X8

01 = RSVD

0 = ENABLED

NORMAL OPERATION

0

0 = WAIT FOR BIOS

051-8870

LANES REVERSED

00 = X8, X4, X4

SIZE

D

REVISION

3.13.0

R

1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB


BRANCH


PAGE

10 OF 109

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D

14 12 10

9 7

OMIT_TABLE


CRITICAL

NOSTUFF

NOSTUFF

R11001 5% 1/20W MF 201

R1101 62

2

5% 1/20W MF 201

OUT

C 67

67 41 19

R1103 67 57 42

7

BI

CPU_PROCHOT_L

1

56

1

51

2

2

MOBILE-2C-35W

1K

5% 1/20W MF 201

2

BGA

5% 1/20W MF 201

(2 OF 9)

OUT

BI

67 19

OUT

S K C O L C

F49 PROC_SELECT*

CPU_PROC_SEL_L

A48 PECI

CPU_PECI

C45 PROCHOT* D45 THERMTRIP*

PM_THRMTRIP_L

L A M R E H T

1% 1/20W MF 201 2 67 26 17

IN

67 17

R1121

PM_MEM_PWRGD

1

130

67 23 19

IN

PM_SYNC

IN

CPU_PWRGD

C48 PM_SYNC B46 UNCOREPWRGOOD

PM_MEM_PWRGD_R

2

1% 1/20W MF 201

BE45 SM_DRAMPWROK D44 RESET*

PLT_RESET_LS1V1_L 26

OUT

=MEM_RESET_L

AT30 SM_DRAMRST*

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

67 67 67

14 12 10

9 7

J3 H2 AG3

DPLL_REF_CLK*

AG1

BCLK_ITP

N59

BCLK_ITP*

N58

BF44 SM_RCOMP_0 BE43 SM_RCOMP_1 BG43 SM_RCOMP_2


T M G M R W P

C S I M 3 R D D

(IPU)

PRDY*

N53

(IPU)

PREQ*

N55

TCK

L56

(IPU)

TMS

L55

(IPU)

TRST*

J58

(IPU)

TDI

M60

TDO

(IPU)

R1120 200

BCLK BCLK*

DPLL_REF_CLK

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

IN

16 67

IN

16 67

DPLL_REF_CLKP DPLL_REF_CLKN

IN

8 67

IN

8 67

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

IN

16 67

IN

16 67

C

C49 CATERR*

CPU_CATERR_L

CPU_PROCHOT_R_L

2

5% 1/20W MF 201


R1104 1R1102

C57 PROC_DETECT* NC 18

26 15 12

U1000 SANDY-BRIDGE

1

1K

1

NOSTUFF

M P B & G A T J

XDP_CPU_PRDY_L XDP_CPU_PREQ_L XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L

OUT

23 67

IN

23 67

IN

23 67

IN

23 67

IN

23 67

IN

23 67

L59

XDP_CPU_TDI XDP_CPU_TDO

OUT

23 67

DBR*

K58

XDP_DBRESET_L

OUT

23 25 67

(IPU) BPM_0* (IPU) BPM_1*

G58


E59


G59


J59

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

E55 G55 H60 J61

BI

23 67

BI

23 67

BI

23 67

BI

23 67

BI

23 67

BI

23 67

BI

23 67

BI

23 67

1 NOSTUFF

R1115

1

B

25.5

200

1% 1/20W MF 201

1% 1/20W MF 201

1% 1/20W MF 201

25 23

IN

CPU_RESET_L

2 2

1

140

75 1% 1/20W MF 201

1

R1112 R1113 R1114

1

R1126

2

2

4.99K

2

1% 1/20W MF 201

1

R1111 10K

B

5% 1/20W MF

2 201

R1125 1

43.2

2

1% 1/20W MF 201

A

A PAGE TITLE

CPU CLOCK/MISC/JTAG DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

11 OF 109

8

7

www.laptopblue.vn

6

5

4

3

OMIT_TABLE

D

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 27 68 27

BI

68 27

BI BI

68 27

BI

68 27

BI

68 27

BI

68 27

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28 68 28 68 28 68 28 68 28

B

BI

68 27

68 27

C

BI

BI BI BI BI BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 28

BI

68 32 28 27

OUT

68 32 28 27

OUT

68 32 28 27

OUT

68 32 28 27

OUT

68 32 28 27

OUT

68 32 28 27

OUT

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

AG6

SA_DQ_0

U1000

AJ6

SA_DQ_1

BGA

AP11

SA_DQ_2

AL6

SA_DQ_3

AJ10

SA_DQ_4

AJ8

SA_DQ_5

AL8

SA_DQ_6

AL7

SA_DQ_7

(3 OF 9) E G D I R B Y D N A S

W 5 3 C 2 E L I B O M

CRITICAL SA_CK_0

AU36

SA_CK_0*

AV36

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

SA_CKE_0

AY26

MEM_A_CKE<0>

SA_CK_1

AT40

SA_CK_1*

AU40

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

SA_CKE_1

BB26

MEM_A_CKE<1>

AR11

SA_DQ_8

AP6

SA_DQ_9

AU6

SA_DQ_10

AV9

SA_DQ_11

AR6

SA_DQ_12

SA_ODT_0

AY40

AP8

SA_DQ_13

SA_ODT_1

BA41

AT13

SA_DQ_14

AU13

SA_DQ_15

SA_DQS_0*

AL11

BC7

SA_DQ_16

SA_DQS_1*

AR8

SA_CS_0*

BB40

SA_CS_1*

BC41

BB7

SA_DQ_17

SA_DQS_2*

AV11

BA13

SA_DQ_18

SA_DQS_3*

AT17

BB11

SA_DQ_19

SA_DQS_4*

AV45

BA7

SA_DQ_20

SA_DQS_5*

BA9

SA_DQ_21

SA_DQS_6*

AY51 AT55

BB9

SA_DQ_22

SA_DQS_7*

AK55

AY13 AV14

SA_DQ_23 SA_DQ_24

AR14

SA_DQ_25

AY17

SA_DQ_26

AR19

SA_DQ_27

A L E N N A H C Y R O M E M

SA_DQS_0

AJ11

SA_DQS_1

AR10

SA_DQS_2

AY11

SA_DQS_3

AU17

SA_DQ_28

SA_DQS_4

AW45

AU14

SA_DQ_29

SA_DQS_5

AV51

BB14

SA_DQ_30

SA_DQS_6

AT56

BB17

SA_DQS_7

AK54

BA45

SA_DQ_31 SA_DQ_32

AR43

SA_DQ_33

SA_MA_0

BG35

AW48

SA_DQ_34

SA_MA_1

BB34

BC48

SA_DQ_35

SA_MA_2

BE35

BC45

SA_DQ_36

SA_MA_3

BD35

AR45

SA_DQ_37

SA_MA_4

AT34

AT48

SA_DQ_38

SA_MA_5

AU34

AY48

SA_DQ_39

SA_MA_6

BB32

BA49

SA_DQ_40

SA_MA_7

AT32

AV49

SA_DQ_41

SA_MA_8

AY32

BB51

SA_DQ_42

SA_MA_9

AV32

AY53

SA_DQ_43

SA_MA_10

BE37

SA_MA_11

BA30

SA_MA_12

BC30

SA_MA_13

AW41

SA_MA_14 SA_MA_15

AY28

AU49 BA53 BB55

SA_DQ_44 SA_DQ_45 SA_DQ_46

BA55

SA_DQ_47 SA_DQ_48

AV56

SA_DQ_49

AP50 AP53

SA_DQ_50 SA_DQ_51

AV54

SA_DQ_52

AT54 AP56

SA_DQ_53 SA_DQ_54

AP52

SA_DQ_55

AN57

MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0> MEM_A_ODT<1> MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

OUT

27 28 32 68

68 29

BI

OUT

27 28 32 68

68 29

BI

68 29

OUT

27 28 32 68

BI

68 29

BI

OUT

8 68

OUT

8 68

OUT

8 68

68 29

BI

68 29

BI

68 29

BI

68 29

BI

68 29

BI

OUT

27 28 32 68

68 29

BI

OUT

8 68

68 29

BI

68 29

BI

OUT

27 28 32 68

68 29

BI

OUT

8 68

68 29

BI

68 29

BI

BI

27 68

68 29

BI

BI

27 68

68 29

BI

BI

27 68

68 29

BI

BI

27 68

68 29

BI

BI

28 68

68 29

BI

BI

28 68

68 29

BI

BI

28 68

68 29

BI

BI

28 68

68 29

BI

68 29

BA14

BB49

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

BI

BI

27 68

68 29

BI

27 68

68 29

BI

BI

27 68

68 29

BI

BI

27 68

68 29

BI

BI

BI

28 68

68 29

BI

BI

28 68

68 29

BI

BI

28 68

68 29

BI

BI

28 68

68 29

BI

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

BI

OUT

27 28 32 68

68 30

OUT

27 28 32 68

68 30

OUT

27 28 32 68

68 30

OUT OUT

27 28 32 68 27 28 32 68

68 30 68 30

BI BI BI BI BI

OUT

27 28 32 68

68 30

BI

OUT

8 68

68 30

BI

68 30

BI

68 30

BI

68 30

BI

68 30

BI

68 30

BI

68 30

BI

68 30

BI

SA_DQ_56

68 30

BI

AN53

SA_DQ_57

68 30

BI

AG56

SA_DQ_58

68 30

BI

AG53

SA_DQ_59

68 30

BI

AN55

SA_DQ_60

68 30

BI

AN52

SA_DQ_61

68 30

BI

AG55

SA_DQ_62

68 30

BI

68 30

BI

AK56

SA_DQ_63

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

BD37 BF36

SA_BS_0 SA_BS_1

BA28

SA_BS_2

MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L

BE39 BD39 AT41

1

OMIT_TABLE

CRITICAL

68 27

2

AU26

68 32 30 29

OUT

68 32 30 29

OUT

68 32 30 29

OUT

SA_CAS*

68 32 30 29

OUT

SA_RAS*

68 32 30 29

OUT

SA_WE*

68 32 30 29

OUT

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

U1000

AL4

SB_DQ_0

AL1

SB_DQ_1

BGA

AN3

SB_DQ_2

(4 OF 9)

AR4

SB_DQ_3

AK4

SB_DQ_4

AK3

SB_DQ_5

E W G 5 D 3 I R C B 2 - Y E D L N I A B S O M

SB_CK_0

BA34

SB_CK_0*

AY34

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

SB_CKE_0

AR22

MEM_B_CKE<0>

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

8 68

OUT

8 68

OUT

8 68

SB_CK_1

BA36

SB_CK_1*

BB36

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

SB_CKE_1

BF27

MEM_B_CKE<1>

SB_CS_0*

BE41

29 30 32 68

BE47

MEM_B_CS_L<0> MEM_B_CS_L<1>

OUT

SB_CS_1*

OUT

8 68

SB_DQ_12

SB_ODT_0

AT43

OUT

29 30 32 68

AR3

SB_DQ_13

SB_ODT_1

BG47

MEM_B_ODT<0> MEM_B_ODT<1>

OUT

8 68

AY2

SB_DQ_14

BA3

SB_DQ_15

BE9

SB_DQ_16

AN4

SB_DQ_6

AR1

SB_DQ_7

AU4

SB_DQ_8

AT2

SB_DQ_9

AV4

SB_DQ_10

BA4

SB_DQ_11

AU3

BD9

SB_DQ_17

BD13

SB_DQ_18

BF12

SB_DQ_19

BF8

SB_DQ_20

BD10

SB_DQ_21

BD14

SB_DQ_22

BE13 BF16

SB_DQ_23 SB_DQ_24

BE17

SB_DQ_25

BE18

SB_DQ_26

BE21

SB_DQ_27

B L E N N A H C Y R O M E M

SB_DQS_0*

AL3

SB_DQS_1*

AV3

SB_DQS_2*

BG11

SB_DQS_3*

BD17

SB_DQS_4*

BG51

SB_DQS_5* SB_DQS_6*

BA59 AT60

SB_DQS_7*

AK59

SB_DQS_0

AM2

SB_DQS_1

AV1

SB_DQS_2

BE11

SB_DQS_3

BD18

BE14

SB_DQ_28

SB_DQS_4

BE51

BG14

SB_DQ_29

SB_DQS_5

BA61

BG18

SB_DQ_30

SB_DQS_6

AR59

BF19

SB_DQS_7

AK61

BD50

SB_DQ_31 SB_DQ_32

BF48

SB_DQ_33

SB_MA_0

BF32

BD53

SB_DQ_34

SB_MA_1

BE33

BF52

SB_DQ_35

SB_MA_2

BD33

BD49

SB_DQ_36

SB_MA_3

AU30

BE49

SB_DQ_37

SB_MA_4

BD30

BD54

SB_DQ_38

SB_MA_5

AV30

BE53

SB_DQ_39

SB_MA_6

BG30

BF56

SB_DQ_40

SB_MA_7

BD29

BE57

SB_DQ_41

SB_MA_8

BE30

BC59

SB_DQ_42

SB_MA_9

BE28

AY60

SB_DQ_43

SB_MA_10

BD43

SB_MA_11

AT28

SB_MA_12

AV28

SB_MA_13

BD46

SB_MA_14 SB_MA_15

AT26

BE54 BG54 BA58 AW59

SB_DQ_44 SB_DQ_45 SB_DQ_46

AW58

SB_DQ_47 SB_DQ_48

AU58

SB_DQ_49

AN61 AN59

SB_DQ_50 SB_DQ_51

AU59

SB_DQ_52

AU61 AN58

SB_DQ_53 SB_DQ_54

AR58

SB_DQ_55

AK58

SB_DQ_56

AL58

SB_DQ_57

AG58

SB_DQ_58

AG59

SB_DQ_59

AM60

SB_DQ_60

AL59

SB_DQ_61

AF61

SB_DQ_62

AH60

SB_DQ_63

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

BG39 BD42

SB_BS_0 SB_BS_1

AT22

SB_BS_2

MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L

AV43

SB_CAS*

BF40

SB_RAS*

BD45

SB_WE*

AU22

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7> MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7> MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

BI

29 68

BI

29 68

BI

29 68

BI

29 68

BI

30 68

BI

30 68

BI

30 68

BI

30 68

BI

29 68

BI

29 68

BI

29 68

BI

29 68

BI

30 68

BI

30 68

BI BI

D

30 68

C

30 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

29 30 32 68

OUT

8 68

B

A

SYNC_DATE=01/10/2011 PAGE TITLE

CPU DDR3 INTERFACES DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

12 OF 109

A

8

7

www.laptopblue.vn

6

5

4

15 12 9 7

14 12 9 7

D

OMIT_TABLE

=PP1V5_S3_CPU_VCCDDR VAXG_1

AB47

VAXG_2

AB50

VAXG_3

U1000

VCCIO_1

AF46

BGA

VCCIO_3

AG48

AB51

VAXG_4

A31 VCC_3 A34 VCC_4

(6 OF 9)

VCCIO_4

AG50

AB52

VAXG_5

VCCIO_5

AG51

AB53

VAXG_6

VCCIO_6

AJ17

AB55

VAXG_7

VCCIO_7

AJ21

VCCIO_8

C32 VCC_11 C34 VCC_12


W 5 3 C 2 E L I B O M

C37 VCC_13 C39 VCC_14 C42 VCC_15 D27 VCC_16

AD47

VAXG_12

VDDQ_10

AM36

VCCIO_12

AK51

AD48

VAXG_13

VDDQ_11

AM40

VCCIO_13

AL14

AD50

VAXG_14

VDDQ_12

AN30

VCCIO_14

AL15

AD51

VAXG_15

VDDQ_13

AN34

VCCIO_15

AL16

AD52

VAXG_16

VDDQ_14

AN38

VCCIO_16

AL20

AD53

VAXG_17

VDDQ_15

AR26

AD55

VAXG_18

VDDQ_16

AR28

VDDQ_17

AR30

VDDQ_18

AR32

VDDQ_19

AR34

VAXG_21

VCCIO_21

AM16

D42 VCC_21 E26 VCC_22

VCCIO_22

AM17

VCCIO_23

AM21

E28 VCC_23 E32 VCC_24

VCCIO_24

AM43

VCCIO_25

AM47

E34 VCC_25 E37 VCC_26

VCCIO_26

AN20

VCCIO_27

AN42

E38 VCC_27 F25 VCC_28

VCCIO_28 VCCIO_29

AE46

P48 VAXG_25 P50 VAXG_26 P51 VAXG_27 P52 VAXG_28

AN48

VCCIO_30

AA14

VCCIO_31

AA15

P56 VAXG_31 P61 VAXG_32

VCCIO_32

AB17

VCCIO_33

AB20

VCCIO_34

AC13

VCCIO_35

AD16

VCCIO_36

AD18

Y L L P U S

VCCIO_37

AD21

VCCIO_38

AE14

VCCIO_39

AE15

E R O C

VCCIO_40

AF16

VCCIO_41

AF18

VCCIO_42

AF20

VCCIO_43

AG15

VCCIO_44

AG16

VCCIO_45 VCCIO_46

AG17

VCCIO_47

AG21

VCCIO_48 VCCIO_49

AJ14

VCCIO_50

W16

J32 VCC_51 J34 VCC_52

VCCIO_51

W17

J35 VCC_53 J37 VCC_54

VCCIO_SEL

K27 VCC_59 K29 VCC_60 K32 VCC_61 K34 VCC_62 K35 VCC_63 K37 VCC_64 K39 VCC_66 K42 VCC_67 L25 VCC_68 L28 VCC_69 L33 VCC_70 L36 VCC_71 L40 VCC_72 N26 VCC_73 N30 VCC_74 N34 VCC_75 N38 VCC_76

T59 VAXG_35 T61 VAXG_36

VCCPQE_2

AN22

A44

VIDSCLK

B43

VIDSOUT

C44

VCC_SENSE

F43

VSS_SENSE

G43

VCCIO_SENSE

VSS_SENSE_VCCIO

AN16 AN17

AV41

VDDQ_23

AW26

VDDQ_24

BA40

VDDQ_25

BB28

VDDQ_26

BG33

VCCDQ_1

AM28

15 12 7

26 15 12 10

AN26

BC43

E VSS_SENSE_VDDQ S E N N VCCSA_SENSE E I S L

BA43

=PP3V3_S0_CPU_VCCIO_SEL

7

1


R1320

15 12 9 7

7 9 10 12 14


R1380

PLACE_NEAR=U1000.BC43:50.8mm 100 1% PLACE_SIDE=BOTTOM 1/20W MF 201 2

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N

U10

CPU_VCCSASENSE

VCCSA_VID_0

D48

VCCSA_VID_1

D49

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1> CPU_DDR_VREF

AY43

VOLTAGE=0.75V

R1302 130

R1300

1% PLACE_NEAR=U1000.C44:2.54mm 1/20W MF

2 201

CPU_VCCIO_SEL =PP1V05_S0_CPU_VCCPQE

1

R1310 1 / 2

0 W1

2011/20W

01

43

75

2 25

NOSTUFF 1

R1370

1% 1/20W MF 201

100

PLACE_NEAR=U1000.F45:50.8mm PLACE_SIDE=BOTTOM

CPU_VIDALERT_L

% M F

IN

57 67

OUT

57 67

1% 1/20W MF

V59 VAXG_47 W50 VAXG_48

5% 1/20W MF 201

1

10K

R1311 25%

CPU_VIDSCLK

MF

01

OUT

CPU_AXG_SENSE_P CPU_AXG_SENSE_N 14 7

R1312 2011/20W

OUT

67 57

25%

CPU_VIDSOUT

MF

CPU_VCCSENSE_P CPU_VCCSENSE_N

BI

Note. VOLTAGE=1.05V Note. VOLTAGE=0V


57 67

=PPVCORE_S0_CPU =PP1V05_S0_CPU_VCCIO

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

NOSTUFF 7 9 12 14

R1371

NOSTUFF

NOSTUFF 1

R1360

1

R1362

100

100 1% 1/20W MF 201

MF 201

2

2

100 1% 1/20W MF 201

2

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM

PLACEMENT NOTE: Note. VOLTAGE=1.25V Note. VOLTAGE=0V Note. VOLTAGE=1.05V Note. VOLTAGE=0V

OUT

57 67

OUT

57 67

OUT

59 67

OUT

59 67

OUT

OUT

12

R13811

2

1

R1313

2

10K

2

5% 1/20W MF 201

PLACEMENT NOTE:

W61 VAXG_54 Y48 VAXG_55

Please place all sense line resistors on BOTTOM side.

F45 VAXG_SENSE G45 VSSAXG_SENSE BB3 VCCPLL_1 BC1 VCCPLL_2

E E S N N I E L S

26 15 12 10

7


B

=PP1V5_S3_CPU_VCCDDR SM_VREF_EXT 1

R1330 PLACE_NEAR=U1000.AY43:2.54mm

V L 8 I . A 1 R

100 5% 1/20W MF

201 2

CPU_DDR_VREF

SM_VREF_EXT

L17 VCCSA_1 L21 VCCSA_2

PLACE_NEAR=U1000.AY43:2.54mm

N16 VCCSA_3 N20 VCCSA_4 N22 VCCSA_5 P17 VCCSA_6 P20 VCCSA_7 R16 VCCSA_8 R18

VCCSA_9

1

100

C1330 0.1UF

5% 1/20W

MF 201

L I A R

12

SM_VREF_EXT

1

R1331

2 2

10% 16V X5R-CERM 0201

PLACE_NEAR=U1000.AY43:2.54mm

A S

R21 VCCSA_10 U15 VCCSA_11 V16 VCCSA_12 V17 VCCSA_13 V18 VCCSA_14 V21 VCCSA_15

NOSTUFF

NOSTUFF 1

R1361 PLACE_NEAR=U1000.G43:50.8mm PLACE_SIDE=BOTTOM

100 1% 1/20W MF 201 2

W20 VCCSA_16

1

R1363 100

1% 1/20W MF 2 201

PLACE_NEAR=U1000.AN17:50.8mm PLACE_SIDE=BOTTOM

SYNC_MASTER=K78_MLB


PAGE TITLE

CPU POWER DRAWING NUMBER

PLACEMENT NOTE:

54

54

1% PLACE_NEAR=U1000.BA43:50.8mm 1/20W PLACE_SIDE=BOTTOM MF 201

=PPVCCSA_S0_CPU

1

7 9 10 12 14

PLACE_NEAR=U1000.G45:50.8mm PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.F43:50.8mm 1% PLACE_SIDE=BOTTOM1/20W

15 12 7

Note. VOLTAGE=0V

Y61 VAXG_56

2 201

67 57

Note. VOLTAGE=1.05V

VAXG_51

W55 VAXG_52 W56 VAXG_53

7 14

CPU_VIDALERT_L_R CPU_VIDSCLK_R CPU_VIDSOUT_R

C

7 15

100

R1314

W53

PLACE_NEAR=R1310.2:2.54mm

1

=PPVCCSA_S0_CPU


R13821

V56 VAXG_45 V58 VAXG_46

W51 VAXG_49 W52 VAXG_50

10K 5% 1/20W MF 201 2

7

PLACE_NEAR=U1000.U10:50.8mm 100 1% 1/20W MF 1 201 2


BC4 VCCPLL_3 E S S E N N E I S L

AR40

VDDQ_22

SM_VREF


AJ15

VCCPQE_1

VIDALERT*

AR36

VDDQ_21

VCCDQ_2

(IPU)


2 0 1

D I V S

VDDQ_20

VDDQ_SENSE

U46 VAXG_37 V47 VAXG_38

For Future Compatibility

T E L I I A U R Q

T E L I I U A Q R

T48 VAXG_33 T58 VAXG_34

AG20

AM25

(IPU)

D

P53

AN45

BC22

S L I A S R C I V H 5 P . R 1 G 3 R D D

VAXG_22

N45 VAXG_23 P47 VAXG_24

VAXG_29 P55 VAXG_30

J42 VCC_57 K26 VCC_58

AM33

AK50

AD59

J38 VCC_55 J40 VCC_56

AL42

VDDQ_9

VCCIO_11

AL48

J28 VCC_49 J29 VCC_50

AL38

VDDQ_8

VAXG_11

VCCIO_20

J25 VCC_47 J26 VCC_48

AL34

VDDQ_7

VAXG_10

D37 VCC_19 D39 VCC_20

H38 VCC_45 H40 VCC_46

VDDQ_6

VAXG_9

VAXG_20

H35 VCC_43 H37 VCC_44

AL30

VAXG_8

AD58

H32 VCC_41 H34 VCC_42

AJ40

VDDQ_5

AC61

AL45

H28 VCC_39 H29 VCC_40

AJ36

VDDQ_4

AB59

VCCIO_19

H25 VCC_37 H26 VCC_38

AJ33

VDDQ_3

AB58

VAXG_19

F42 VCC_35 G42 VCC_36

VDDQ_2

AB56

VCCIO_18

F37 VCC_33 F38 VCC_34

AJ28

AJ47

AD56

G E P

VDDQ_1

AJ43

AL26

D N A

9) W 5 3 C 2 E L I B O M

AJ25

VCCIO_17

R D D

BGA

(7 OF E G D I R B Y D N A S

VCCIO_9

D32 VCC_17 D34 VCC_18

F32 VCC_31 F34 VCC_32

U1000

VCCIO_10

AL22

F26 VCC_29 F28 VCC_30

1

CRITICAL

(NOT controlled by VCCIO_SEL) Fixed at 1.05V

AA46

A26 VCC_1 A29 VCC_2

C26 VCC_9 C27 VCC_10

A



CRITICAL

A39 VCC_7 A42 VCC_8

B

2

OMIT_TABLE

=PPVCORE_S0_CPU

A35 VCC_5 A38 VCC_6

C

3

Apple Inc.


051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

13 OF 109

A

8

7

6

www.laptopblue.vn 5

4

3

2

1

OMIT_TABLE CRITICAL

OMIT_TABLE CRITICAL

VSS

U1000

VSS

M11

BG17

VSS

BGA

VSS

M15

BG21

VSS

VSS

M58

BG24

VSS

VSS

N1

BG28

VSS

VSS

N17

BG37

VSS

VSS

N21

BG41

VSS

VSS

N25

VSS

N28

VSS

N33

BG13

D

BG45

VSS

BG53

VSS

W 5 3 C 2 E L I B O M

VSS

N36

VSS

VSS

N40

VSS

VSS

N43

VSS

VSS

N47

VSS

VSS

N48

VSS

VSS

N51

VSS

VSS

N52

VSS

VSS

N56

VSS

VSS

N61

VSS

VSS

P9

VSS

VSS

P14

D29

VSS

VSS

P16

D35

VSS

VSS

P18

D40

VSS

VSS

P21

D43

VSS

VSS

P58

D46

VSS

VSS

P59

VSS

R4

VSS

R17

VSS

R20

VSS

R46

VSS

VSS

T1

VSS

VSS

T47

VSS

VSS

T50

VSS

VSS

T51

VSS

VSS

T52

VSS

VSS

T53

F19

VSS

VSS

T55

F29

VSS

VSS

T56

F35

VSS

VSS

U8

F40

VSS

VSS

U13

F55

VSS

VSS

V20

G6

VSS

VSS

V61

G48

VSS

VSS

W8

G51

VSS

VSS

W13

G61

VSS

VSS

W15

VSS

W18

VSS

W21

VSS

W46

VSS

Y4

VSS

VSS

Y47

VSS

VSS

Y58

VSS

VSS

Y59

D6 D10 D14 D18 D22 D26

D50 D54 D58 E3 E25 E29 E35 E40 F13 F15

H4 H10 H14 H17 H21 H53 H58 J1 J49 J55 K8 K11 K21

VSS VSS VSS VSS

VSS VSS VSS VSS

VSS

VSS_NCTF

A57

L16

VSS

VSS_NCTF

BC61

L20

VSS

VSS_NCTF

BD3

L22

VSS

VSS_NCTF

BD59

L26

VSS

VSS_NCTF

BE4

L30

VSS

VSS_NCTF

BE58

L34

VSS

VSS_NCTF

BG5

L38

VSS

VSS_NCTF

BG57

VSS_NCTF

C3

VSS

VSS_NCTF VSS_NCTF

C58

VSS

VSS_NCTF

E1

VSS

VSS_NCTF

E61

L61 M4 M6

VSS VSS

AM45

VSS

AM48

VSS

AM58

VSS

AN1

VSS

AN21

VSS

AN25

VSS

AN28

W 5 3 C 2 E L I B O M

VSS

A37

VSS

A40

VSS

A45

VSS

A49

VSS

VSS

AN33

A53

VSS

VSS

AN36

AA1

VSS

VSS

AN40

AA8

VSS

VSS

AN43

AA13

VSS

VSS

AN47

AA50

VSS

VSS

AN50

AA51

VSS

VSS

AN54

AA52

VSS

VSS

AP7

AA53

VSS

VSS

AP10

AA55

VSS

VSS

AP51

AA56

VSS

VSS

AP55

AB16

VSS

VSS

AR7

AB18

VSS

VSS

AR13

AB21

VSS

VSS

AR17

AB48

VSS

VSS

AR21

AB61

VSS

VSS

AR41

VSS

VSS

AR48

AC10

VSS

VSS

AR61

AC14

VSS

VSS

AT4

AC46

VSS

VSS

AT14

VSS

VSS

AT19

AD17

VSS

VSS

AT36

AD20

VSS

VSS

AT45

AD61

VSS

VSS

AT52

VSS

VSS

AT58

VSS

VSS

AU1

VSS

VSS

AU7

AF17

VSS

VSS

AU11

AF21

VSS

VSS

AU28

AF47

VSS

VSS

AU32

AF48

VSS

VSS

AU51

AF50

VSS

VSS

AV17

AF51

VSS

VSS

AV21

AF52

VSS

VSS

AV22

AF53

VSS

VSS

AV34

AF55

VSS

VSS

AV40

AF56

VSS

VSS

AV48

AF58

VSS

VSS

AV55

AF59

VSS

VSS

AW7

VSS

VSS

AW13

AG10

VSS

VSS

AW43

AG14

VSS

VSS

AW61

AG18

VSS

VSS

AY4

AG47

VSS

VSS

AY9

AG52

VSS

VSS

AY14

AG61

VSS

VSS

AY19

VSS

VSS

AY30

VSS

VSS

AY36

AH58

VSS

AM42

VSS


VSS

AH4

VSS

AM38

VSS

A33

AG7

VSS

AM34

VSS

A28

AF1

VSS

VSS

BGA

VSS

VSS

AE13

VSS

VSS

U1000 (8 OF 9)

A25

AE8

A5

L48

VSS

AD4

VSS_NCTF

K51

VSS

A17

AC6

VSS

L43

A


C35

D4

B

VSS

VSS

A21

C29

C40

C

VSS

BG49

(9 OF 9)

A9 A13

AJ7

VSS

VSS

AY41

AJ13

VSS

VSS

AY45

AJ16

VSS

VSS

AY49

AJ20

VSS

VSS

AY55

AJ22

VSS

VSS

AY58

AJ26

VSS

VSS

BA1

AJ30

VSS

VSS

BA11

AJ34

VSS

VSS

BA17

AJ38

VSS

VSS

BA21

AJ42

VSS

VSS

BA26

AJ45

VSS

VSS

BA32

AJ48

VSS

VSS

BA48

VSS

VSS

BA51

AK52

VSS

VSS

BB53

AL10

VSS

VSS

BC5

AL13

VSS

VSS

BC13

AL17

VSS

VSS

BC57

AL21

VSS

VSS

BD8

AL25

VSS

VSS

BD12

AL28

VSS

VSS

BD16

AL33

VSS

VSS

BD19

AL36

VSS

VSS

BD23

AL40

VSS

VSS

BD27

AL43

VSS

VSS

BD32

AL47

VSS

VSS

BD36

AL61

VSS

VSS

BD40

VSS

VSS

BD44

AM13

VSS

VSS

BD48

AM20

VSS

VSS

BD52

AM22

VSS

VSS

BD56

AM26

VSS

VSS

BE5

AM30

VSS

VSS

BG9

D59 AK1

AM4

D

C

B

A PAGE TITLE

CPU GROUNDS DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

14 OF 109

8

7

www.laptopblue.vn

6

5

4

3

2

1

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

Processor Load Line : -2.9 mOhms

CPU VCORE DECOUPLING Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

12 9 7

=PPVCORE_S0_CPU

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

C1600

1

1

2.2UF

20% 4V 2 X5R 402

D

C1601

1

2.2UF

C1602 1 C1603 1 C1604 1 C1605 1 C1606 2.2UF

20% 4V 2 X5R 402

20% 4V 2 X5R 402

2.2UF

20% 4V 2 X5R 402

2.2UF

2.2UF

20% 4V 2 X5R 402

1

2.2UF

20% 4V 2 X5R 402

C1607 2.2UF

20% 4V 2 X5R 402

20% 4V 2 X5R 402

1

C1608 2.2UF

20% 4V 2 X5R 402

C1609

1

2.2UF

20% 4V 2 X5R 402

CRITICAL 1

C1610 2.2UF

20% 4V 2 X5R 402

CRITICAL 1

C1611

CRITICAL 1

2.2UF

C1612 2.2UF

20% 4V 2 X5R 402

20% 4V 2 X5R 402

CRITICAL CRITICAL CRITICAL 1

C1613 1 C1614 2.2UF

20% 4V 2 X5R 402

2.2UF

20% 4V 2 X5R 402

1

C1615 2.2UF

20% 4V 2 X5R 402

D

PLACEMENT_NOTE (C1655-C1666): Place close to U1000 on top side.

CRITICAL 1

CRITICAL

C1655

1

22UF

C

CRITICAL

C1656

1

22UF

20% 4V 2 X5R 402

CRITICAL

C1657

1

22UF

20% 4V 2 X5R 402

C1658

CRITICAL 1

22UF

20% 4V 2 X5R 402

CRITICAL CRITICAL

C1659

1

22UF

20% 4V 2 X5R 402

C1660

1

22UF

20% 4V 2 X5R 402

CRITICAL

C1661

1

22UF

20% 4V 2 X5R 402

CRITICAL

C1662

1

22UF

20% 4V 2 X5R 402

CRITICAL

C1663

1

22UF

20% 4V 2 X5R 402

CRITICAL

C1664

1

22UF

20% 4V 2 X5R 402

CRITICAL

C1665

1

22UF

20% 4V 2 X5R 402

C1666 22UF

20% 4V 2 X5R 402

20% 4V 2 X5R 402

C

PLACEMENT_NOTE (C1667-C1679):


1

1

C1680 270UF

1

C1681 270UF

20% 2 2V

1

C1682 270UF

20% 2 2V

TANT CASE-B2-SM

C1683 270UF

20% 2 2V

TANT CASE-B2-SM

1

C1679 270UF

20% 2 2V

TANT CASE-B2-SM

TANT CASE-B2-SM

20%

2 2V

TANT CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING CPU VCCPLL DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1646-C1671): 12 10 9 7


Place on bottom side of U1000 U100. Place near U1000 on top side

B

1

C1684

1

1UF

C1685

1

1UF

10% 10V 2 X5R 402

C1686

1

1UF

10% 10V 2 X5R 402

C1687

1

1UF

10% 10V 2 X5R 402

C1688

1

1UF

10% 10V 2 X5R 402

C1689

1

1UF

10% 10V 2 X5R 402

C1690

1

1UF

10% 10V 2 X5R 402

C1691

1

1UF

10% 10V 2 X5R 402

C1692

1

1UF

10% 10V 2 X5R 402

C1693

1

1UF

10% 10V 2 X5R 402

C1694

1

1UF

10% 10V 2 X5R 402

C1695

1

1UF

10% 10V 2 X5R 402

C1696 1UF

10% 10V 2 X5R 402

10% 10V 2 X5R 402

R1600 7

=PP1V8_S0_CPU_VCCPLL

1

0

5% 1/16W MF-LF 402

PLACE_NEAR=U1000.BB3:2. 54 mm:NO_VIA


B

7 12

2 1

C160X 1UF

10% 2 10V X5R 402

1

C160Y 1UF

10% 2 10V X5R 402

1

C160Z

PLACE_NEAR=U1000.BC2:5mm

270UF

20% 2 2V

TANT CASE-B2-SM

PLACE_NEAR=U1000.BC1:2.5 4 mm:NO_VIA

1

C1697

1

1UF

C1698

1

1UF

10% 10V 2 X5R 402

C1699

1

1UF

10% 10V 2 X5R 402

C169A

1

1UF

10% 10V 2 X5R 402

C169B

1

1UF

10% 10V 2 X5R 402

C169C

1

1UF

10% 10V 2 X5R 402

C169D

1

1UF

10% 10V 2 X5R 402

C169E

1

1UF

10% 10V 2 X5R 402

C169F

1

1UF

10% 10V 2 X5R 402

C161A 1UF

10% 10V 2 X5R 402

10% 10V 2 X5R 402

1

C161B 1UF

10% 10V 2 X5R 402

1

C161C 1UF

10% 10V 2 X5R 402

1

C161D 1UF

CPU VCCPLL Low pass filter

10% 10V 2 X5R 402

PLACEMENT_NOTE (C1672-C1681): Place near U1000 on bottom side

1

C161E

1

10UF

1

C167D 270UF

A

20% 2 2V

TANT CASE-B2-SM

C161F

1

10UF

20% 2 6.3V CERM-X5R 0402-1

1

270UF

C167G 270UF

TANT CASE-B2-SM

1

20% 2 2V

TANT CASE-B2-SM

C162B 10UF

20% 2 6.3V CERM-X5R 0402-1

1

C167E

20% 2 2V

C162A 10UF

20% 2 6.3V CERM-X5R 0402-1

20% 2 6.3V CERM-X5R 0402-1

1

1

C162C 10UF

20% 2 6.3V CERM-X5R 0402-1

1

C162D 10UF

20% 2 6.3V CERM-X5R 0402-1

1

C162E 10UF

20% 2 6.3V CERM-X5R 0402-1

1

C167A 10UF

20% 2 6.3V CERM-X5R 0402-1

1

C167B 10UF

20% 2 6.3V CERM-X5R 0402-1

1

C167C 10UF

20% 2 6.3V CERM-X5R 0402-1

C167H 270UF

20% 2 2V

TANT CASE-B2-SM SYNC_MASTER=K78_MLB


PAGE TITLE

CPU DECOUPLING-I

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

DRAWING NUMBER

R1601 0.010

1

2

1%

1/4W MF

0603

=PP1V05_S0_CPU_VCCPQE

Apple Inc.

7 12

C167F

051-8870

1UF

10% 10V 2 X5R 402

Note:The smallest 10mOhm available in the library are 0805s

SIZE

D

REVISION

3.13.0

R

1


BRANCH


PAGE

16 OF 109

A

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6

5

VAXG DECOUPLING

3

2

1

Graphics Load Line : -3.9 mOhms

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x

12 9 7

4

470uF(2 no-stuff)



Place on bottom side of U1000 U100.

CRITICAL

1

CRITICAL

1

C1700

D

2

CRITICAL

1

C1707

1UF

10% 10V X5R 402

2

CRITICAL

1

C1706

1UF

10% 10V X5R 402

2

CRITICAL

1

C1705

1UF

10% 10V X5R 402

2

CRITICAL

1

C1704

1UF

10% 10V X5R 402

2

CRITICAL

1

C1703

1UF

10% 10V X5R 402

2

CRITICAL

1

C1702

1UF

10% 10V X5R 402

2

CRITICAL

1

C1701

1UF

1UF

10% 10V X5R 402

2

CRITICAL

1

C1708 1UF

10% 10V X5R 402

2

C1709

CRITICAL

1

1UF

10% 10V X5R 402

2

10% 10V X5R 402

C1710 1UF

2

10% 10V X5R 402

D


CRITICAL 1

CRITICAL 1

C1711

CRITICAL 1

C1712

10UF

CERM-X5R

CERM-X5R

CERM-X5R

0402-1

CRITICAL

2

CERM-X5R

0402-1

CRITICAL 1

0402-1

C1716 10UF

20%

6.3V

2

C1715 10UF

20%

6.3V

2

1

10UF

20%

6.3V

0402-1

CRITICAL C1714

10UF

20%

2

1

C1713

10UF

20% 6.3V

2

20%

6.3V CERM-X5R

2

0402-1

6.3V CERM-X5R 0402-1


CRITICAL

CRITICAL

C1717

1

1

1

22UF

20% 6.3V X5R-CERM1 0603

2

CRITICAL

C1718

22UF 2

CRITICAL

C1719

1

C1720

22UF

20% 6.3V X5R-CERM1 0603

2

CRITICAL 1

20% 6.3V X5R-CERM1 0603

2

CRITICAL

C1721

22UF

1

C1722

22UF

20% 6.3V X5R-CERM1 0603

2

22UF

20% 6.3V X5R-CERM1 0603

2

20% 6.3V X5R-CERM1 0603


1

1

C1723 270UF

C

1

C1724 270UF

20%

C1725 20%

2 2V

TANT CASE-B2-SM

C

270UF

20%

2 2V

2 2V

TANT CASE-B2-SM

TANT CASE-B2-SM

CPU VDDQ/VCCDQ DECOUPLING Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

PLACEMENT_NOTE (C1738-C1747): 26 12 10

7

=PP1V5_S3_CPU_VCCDDR Place on bottom side of U100. U1000

1

1

C1738 1UF

2

X5R 402

1

C1740

1UF

10% 10V

2

CPU VCCSA DECOUPLING 1

C1739

1UF

10% 10V

1

1UF

10% 10V

2

X5R 402

C1741

2

X5R 402

10% 10V X5R 402

C1742

1

1UF 2

10% 10V X5R 402

1

C1743 1UF

2

1

C1744 1UF

10% 10V

2

X5R 402

C1745

1

1UF

10% 10V

2

X5R 402

10% 10V X5R 402

C1746

1

1UF 2

10% 10V X5R 402

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

C1747 1UF

2


10% 10V X5R 402

12 7

=PPVCCSA_S0_CPU

Place on bottom side of U1000 U100.

Place close to U1000 on bottom side 1

1

1

C1748 10UF

B

2

0402-1

1

10UF

20%

6.3V CERM-X5R

1

1 C1750

C1749 10UF

20%

2

2

0402-1

C1751

1

10UF

20%

6.3V CERM-X5R

2

0402-1

6.3V CERM-X5R 0402-1

C1752

1

10UF

20%

6.3V CERM-X5R

6.3V CERM-X5R 0402-1

C1753

1 C1754

10UF

20%

2

6.3V CERM-X5R 0402-1

1

10UF

20%

2

6.3V CERM-X5R 0402-1

C1755 20%

2

2

6.3V CERM-X5R

1

C1756

1

C1763

1

1

C1760 1UF

10% 10V X5R 402

2

6.3V CERM-X5R 0402-1

1

R1702

C1764

1

10UF

20%

2

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

1

C1759 1UF

2

10UF

20% 2V TANT CASE-B2-SM

1

C1761 1UF

10% 10V X5R 402

2

C1762 1UF

10% 10V X5R 402

2

10% 10V X5R 402

B

6.3V CERM-X5R 0402-1

C1765

1

10UF

20%

2

6.3V CERM-X5R 0402-1

1

C1766 10UF

20%

2

C1767 10UF

20%

2

20%

6.3V

2

CERM-X5R 0402-1

6.3V CERM-X5R 0402-1

C1768 270UF

0.010 1

10% 10V X5R 402

0402-1

270UF 2

C1758 1UF

10UF

20%

2

2

=PP1V5_S3_CPU_VCCDQ

1%

7 12

2


1/4W MF

1

0603

C1757 1UF 10%

2

10V X5R 402

A

SYNC_MASTER=K78_MLB


PAGE TITLE

CPU DECOUPLING-II DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

17 OF 109

A

8

7

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6

5

4

3

2

1

=PP1V05_S0_PCH_VCCIO_SATA =PP3V3_S0_PCH LPC_R_AD<0> A19

SYSCLK_CLK32K_RTC

IN

NC

D

PCH_SRTCRST_L

A23

RTC_RESET_L

F19

PCH_INTRUDER_L

K22

PCH_INTVRMEN_L

C21

U1800

RTCX1

C19

FWH0/LAD0 A37 A39 FWH1/LAD1 FWH2/LAD2 C39

COUGAR-POINT

RTCX2

MOBILE-SFF FCBGA (1 OF 10)

SRTCRST* RTCRST*

INTVRMEN

H35

HDA_BCLK

HDA_SYNC_R

H37

HDA_SYNC

C P L

F37

SERIRQ Y4

F35

HDA_SDIN0 TP_HDA_SDIN1 TP_HDA_SDIN2 TP_HDA_SDIN3

D36

HDA_SDOUT_R

K37

IN IN

HDA_SDO

JTAG_T29_TMS ENET_MEDIA_SENSE

K35

HDA_DOCK_EN*/GPIO33

M35

HDA_DOCK_RST*/GPIO13

C35 A35

M17

XDP_PCH_TCK

IN

XDP_PCH_TMS

M15

IN

XDP_PCH_TDI

U12

OUT

XDP_PCH_TDO

IN

C

B36

M12

HDA_RST*

AU3

SATA0TXP

AU1 AN6

HDA_SDIN1

AR3

SATA1TXN

AR1

SATA1TXP

AD4

SATA2RXN SATA2RXP

HDA_SDIN3

SATA2TXN

AL3

SATA2TXP

AL1

SATA3RXN

AD8

SATA3RXP

AD6

JTAG_TCK

JTAG_TDI JTAG_TDO

AG1

SATA3TXP SATA4RXN

AE3

SATA4RXP

AE1 AH6

SATA4TXP

AC3

AD12

SPI_CLK_R SPI_CS0_R_L

AB8

TP_SPI_CS1_L

AB6

SPI_CS1*

SPI_CLK SPI_CS0*

OUT

SPI_MOSI_R

W8

SPI_MOSI

IN

SPI_MISO

Y2

SPI_MISO

I P S

LPC_AD<3>

90.9

1% 1/20W MF 2012

R1820 10K

BI

5% 1/20W MF 2201

BI

IN IN

AJ3 AJ1

SATAICOMPO

AB10

SATAICOMPI

AB12

SATALED* SATA0GP/GPIO21

IN IN OUT

IN IN OUT OUT

IN IN OUT

W10

PCH_SATALED_L

M2

DP_AUXCH_ISOL SATARDRVR_EN

SATA3RCOMP0 AF10

=PP1V05_S0_PCH

1% 1/20W MF 201 2

10K

10K

B

5% 1/20W MF 201 2

PLACE_NEAR=U1800.AF12:2.54mm

750

10K

10K

4.7K

5% 1/20W MF 2012

5% 1/20W MF 201 2

4.7K

5% 1/20W MF 2012

=PPVRTC_G3_PCH

R18021 20K

5% 1/20W MF 201 2

R18001

1

R1803 20K

5% 1/20W MF 2 201

RTC_RESET_L PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

C1802

1

1.0UF

20%

6.3V 2 X5R

0201-MUR

1

NOSTUFF

C1803

R18341

5% 1/20W MF 201 2

5% 1/20W MF 2012

1.0UF

=PP3V3_SUS_GPIO

0201-MUR

R18481 R18471 R18501

20% 2 6.3V X5R

5% 1/20W MF 2012

PLACE_NEAR=R1813.1:2.54mm

10K

1

0

2

SPI_DESCRIPTOR_OVERRIDE_L OUT

5% 1/20W MF 201

1

R1866 10K

needed

for SPI_DESCRIPTOR_OVERR IDE_L?

PD

needed

for BCM_MEDIA_SENSE?

5% 1/20W MF 201

NOSTUFF

BJ37

PERN4

BL37 BD35

PERP4

BF35

PETP4

NC_PCIE_5_D2RN NC_PCIE_5_D2RP NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CP

BJ39

PERN5

BL39 AY35

PERP5 PETN5

CLKOUT_PEG_A_N

BB35

PETP5

CLKOUT_PEG_A_P


BH40

PERN6

CLKOUT_DMI_N

BB24

BK40 BD37

PERP6

CLKOUT_DMI_P

AY24

BF37

PETP6


BJ41

PERN7

BL41

PERP7

AY37

PETN7

PETN2

AY33

PETP2

BB37

PERP8

AY40

PETN8

BB40

PETP8

AD48 AD50 M4

S U B M S

IN

T29_CLKREQ_L

SML1ALERT*/PCHHOT*/GPIO74 SML1CLK/GPIO58 SML1DATA/GPIO75

PEG_A_CLKRQ*/GPIO47

* E I C P

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE2N CLKOUT_PCIE2P

T4

AA49 AA51

2

CLKOUT_PCIE3N

R1849

33

5% 1/20W MF 201

10K

HDA_SDOUT_R

D12 C11

SML_PCH_1_CLK SML_PCH_1_DATA

L3

TP_CLINK_CLK

J1

TP_CLINK_DATA

M8

TP_CLINK_RESET_L

R8

PEG_CLKREQ_L

AF44

PEG_CLK100M_N PEG_CLK100M_P

OUT

AF46

PCIECLKRQ3*/GPIO25

OUT BI

IN

OUT

OUT

CLKIN_GND1_N

BB26

PCH_CLKIN_GNDN1

CLKIN_GND1_P

AY26

PCH_CLKIN_GNDP1

OUT

OUT IN IN

M24

PCH_CLK96M_DOT_N

K24

IN

CLKIN_DOT_96P

PCH_CLK96M_DOT_P

IN

CLKIN_SATA_N

AK8

PCH_CLK100M_SATA_N

CLKIN_SATA_P

AK6

IN

PCH_CLK100M_SATA_P

IN

REFCLK14IN

J49

PCH_CLK14P3M_REFCLK

IN

CLKIN_PCILOOPBACK

E51

PCH_CLK33M_PCIIN

IN

SYSCLK_CLK25M_SB_R

1

R1871

10K

10K

5%

5%

1/20W

R1885 1

C

1

R1870

1/20W

MF

MF

2012

2201

SYSCLK_CLK25M_SB 2

IN

PLACE_NEAR=U1800.W49:5.1mm

604

NC

AC49

201 1% 1/20WMF

PCH_XCLK_RCOMP

1.5V -> 1.1V

H50


D48


G49


J51


1

R1886 1K

1% 1/20W MF 2201 PLACE_NEAR=R1885.1:2.54mm

CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4*/GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P

B

PCIECLKRQ5*/GPIO44

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

BI

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

AN10

D

OUT

PEG_B_CLKRQ*/GPIO56

AB44 CLKOUT_PCIE6N AB46 CLKOUT_PCIE6P

W44 W46 H4

PCIECLKRQ6*/GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7*/GPIO46

AR12 CLKOUT_ITPXDP_N AR10 CLKOUT_ITPXDP_P

ITPCPU_CLK100M_N

5%

NOSTUFF

MF

R1841 0

2

I TP CP U_ CL K1 00 M_ P

=PP3V3_SUS_GPIO

MF

1

R1854

HDA_BIT_CLK

10K

5% 1/20W MF 2201

OUT

PLACE_NEAR=U1800.H37:1.27mm

R1811 1

1

SML_PCH_1_ALERT_L

CLKIN_DMI_N BD17 CLKIN_DMI_P BF17

CLKOUTFLEX2/GPIO66

201

33

2

HDA_SYNC

10K

5% 1/20W MF 2 201

10K

5% 1/20W MF SYNC_MASTER=K21_MLB 2201 PAGE TITLE


PCH SATA/PCIE/CLK/LPC/SPI DRAWING NUMBER

Apple Inc.

SML_PCH_1_ALERT_L NOSTUFF

R1813 2

R1888 HDA_SDOUT

OUT

IN

SMC_SCI_L

1

0

2

PCH_GPIO11

051-8870

SIZE

D

REVISION

3.13.0

R

OUT

PLACE_NEAR=U1800.K37:1.27mm

33

R1855 1R1853

SML_PCH_0_ALERT_L HDA_RST_L

2

1

1

OUT

5% 1/20W MF 201

R1812

HDA_RST_R_L

C9

OUT

X E LCLKOUTFLEX3/GPIO67 F

CLKOUT_PCIE3P

AB42

J3

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

201

2

HDA_SYNC_R

A9

SML_PCH_0_CLK SML_PCH_0_DATA

TP_PCH_CLKOUT_DPN TP_PCH_CLKOUT_DPP

K CCLKOUTFLEX0/GPIO64 O LCLKOUTFLEX1/GPIO65 C

R1810 5% 1/20W MF 201

SML_PCH_0_ALERT_L

K12

XTAL25_IN W49 W51

PCIECLKRQ2*/GPIO20

AB40

K8

BI

H22

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

CLKIN_DOT_96N

K L C

CLKOUT_PCIE0P

AD42

OUT

CLKOUT_DP_P AN12

CLKOUT_DP_N

CLKOUT_PCIE0N

AD40

TP_PCIE_CLK100M_PE7N TP_PCIE_CLK100M_PE7P

5%

1

CL_RST1*

XCLK_RCOMP

M19

1/20W

HDA_BIT_CLK_R

CL_DATA1

XTAL25_OUT

WOL_EN

PLACE_NEAR=U1800.H35:1.27mm

33

CL_CLK1

PCIECLKRQ1*/GPIO18

Y50


1

L K R N T I N C L

CLKOUT_PCIE1P

PEG_B_CLKRQ_L_GPIO56

1/20W

I TP XD P_ CL K1 00 M_ P

SML0DATA

CLKOUT_PCIE1N

Y48

TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP

R1840 0

SML0CLK

AE51

B8

OUT

NOSTUFF 1

SML0ALERT*/GPIO60

AE49

PCIECLKRQ5_L_GPIO44

ITPXDP_CLK100M_N

SMBDATA

OMIT_TABLE

PETP7

BL43

SMBUS_PCH_CLK SMBUS_PCH_DATA

(2 OF 10)

PETN6

PERN8

1% 1/20W MF 201 2

PCH_GPIO11

SMBCLK F17 F10

MOBILE-SFF

PETN4

BJ43

U8

PCIE_CLK100M_T29_N PCIE_CLK100M_T29_P

10K

1

5% 1/20W MF 201

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

EXCARD_CLKREQ_L

5% 1/20W MF 201 2

PLACE_NEAR=U1800.F35:1.27mm

=PP3V3R1V5_S0_PCH_VCCSUSHDA NOSTUFF

Pullup


PCIECLKRQ0_L_GPIO73 PCIECLKRQ5_L_GPIO44 PEG_B_CLKRQ_L_GPIO56

R1880

HDA_SDOUT_R

PETP3

IN OUT

10K

5% 1/20W MF 201 2

NOSTUFF

PETN3

BD33


10K

5% 1/20W MF 201 2

PERP3

BF33

BB33

PCH_GPIO46

R18331 10K

10K

A

PLACE_NEAR=U1800.AH4:2.54mm


5% 1/20W MF 2 201

PERN3

BK36

OUT

JTAG_T29_TMS PCH_SPKR AP_CLKREQ_L PCH_SATALED_L EXCARD_CLKREQ_L T29_CLKREQ_L PEG_CLKREQ_L PCIECLKRQ2_L_GPIO20

1M

BH36

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

R1801

5% 1/20W MF 201 2


IN

1

330K

PERP2

AP_CLKREQ_L

R18781 R18421 R18771 R18761

5% 1/20W MF 201 2

PERN2

BL35

PCIECLKRQ2_L_GPIO20

1% 1/20W MF 2012

10K

BJ35


R1832

5% 1/20W MF 2012

PETP1

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

PCH_SATA3RBIAS

=PP3V3_T29_PCH_GPIO

5% 1/20W MF 2012

AY30

FCBGA

SMBALERT*/GPIO11

DOES THIS NEED LENGTH MATCH???

49.9


R18511 R18461 R18451 R18441

PETN1

OUT

OUT

R18311

1

5% 1/20W MF 201 2

BB30

PCIECLKRQ0_L_GPIO73

OUT

10K

COUGAR-POINT


ENET_MEDIA_SENSE

R18991

PERP1


PCH_SATA3COMP

AH4

SATA3RBIAS

PERN1

OUT

PCH_SATAICOMP

H12

BJ33 BL33

OUT

AF12

SATA3COMPI

OUT

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

R1

SATA1GP/GPIO19

OUT

BI

U1800


BI

TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

SATA5RXN AC1 SATA5RXP SATA5TXP

OUT

LPC_AD<2>

R18901

P L A C E T H I S R E S I S TRON E A R T H E P C H P I N

37.4

1

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

AH8

SATA4TXN

SATA5TXN

OUT

MF 201

BI

TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP

AG3

SATA3TXN

G A T J

JTAG_TMS

201

R1863 2

5% 1/20W

SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

AD2

HDA_SDIN2

A T A S

MF

LPC_AD<1>

R18301

TP_SATA_B_D2RN TP_SATA_B_D2RP TP_SATA_B_R2D_CN TP_SATA_B_R2D_CP

AN8

SATA1RXP

A D H I

HDA_SDIN0

1

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

AN1

SATA0TXN

SATA1RXN

HDA_RST_R_L IN

MF 201

R1862 2

BI

LPC_SERIRQ

AN3

SATA0RXN

SPKR

33

1

33

PLACE_NEAR=U1800.W49:2.54mm

R1861 2

LPC_AD<0>

(IPU)

SATA0RXP

N1

1

MF 201

2 LPC_FRAME_R_L LPC_FRAME_L 33 1 R1864 5% 1/20W MF 201 TP_LPC_DREQ0_L T29_PWR_EN_PCH OUT

H40

LDRQ0*

LDRQ1*/GPIO23

33

PLACE_NEAR=U1800.AB10:2.54mm

2

5% 1/20W

LPC_R_AD<3>

K40

FWH4/LFRAME*

C T R

INTRUDER*

1

5% 1/20W

LPC_R_AD<2>

OMIT_TABLE

HDA_BIT_CLK_R

PCH_SPKR

LPC_R_AD<1>

FWH3/LAD3 C37

=PP1V05_S0_PCH_VCCDIFFCLK

R1860

33

5% 1/20W


BRANCH


PAGE

18 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

=PP3V3_SUS_GPIO =PP1V05_S0_PCH_VCCIO_PCIE

R19051

1

R1900

10K

49.9

5% 1/20W MF 2012

1% 1/20W MF PLACE_NEAR=U1800.BF19:12.7mm 2201 IN IN

D

IN IN IN IN IN IN

OUT OUT OUT OUT OUT OUT OUT OUT

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

BL21

DMI0RXN

BL23

DMI1RXN

BJ19

DMI2RXN

BL17

DMI3RXN

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

BJ21

DMI0RXP

DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>

BJ23

DMI2RXP

BJ17

DMI3RXP

BD22

DMI0TXN

BB22

DMI1TXN

BB19 BB17

DMI2TXN

BF22

PCH_DMI2RBIAS

FDI_RXN3 BJ11 OMIT_TABLE FDI_RXN4 AY15 FDI_RXN5 AY12 FDI_RXN6

FDI_RXP0 BJ13 FDI_RXP1 BL15 FDI_RXP2 BF12 FDI_RXP3 BL11 FDI_RXP4 BB15

DMI1TXP DMI2TXP

BK20

DMI2RBIAS

FDI_RXP5 BB12

I I M D D F

DMI0TXP

AY19 AY17

R1920

PCH_DMI_COMP

750

1% 1/20W MF 2201

FDI_RXP6 FDI_RXP7

DMI3TXP

C

BK8

FDI_LSYNC0

DMI_IRCOMP

FDI_LSYNC1

IN

PM_PCH_SYS_PWROK

M10

IN

PM_PCH_PWROK

M22

OUT

PM_MEM_PWRGD

B12

IN

PM_DSW_PWRGD

A21

IN

PM_PCH_APWROK

G3

IN

PM_RSMRST_L

B20

OUT

PCH_SUSWARN_L

C13

IN

PM_PWRBTN_L

K19

IN

SMC_ADAPTER_EN

H19

IN

PM_BATLOW_L

H10 F12

PCH_RI_L

BH12

FDI_FSYNC1 DMI_ZCOMP

L1

BD10

FDI_FSYNC0

BD19

PM_SYSRST_L

BL9

FDI_INT BB10

BF19

IN

BJ9

FDI_RXN7 BF10

DMI3TXN

AY22

BL13

FDI_RXN1 BJ15 FDI_RXN2 BD12

FCBGA (3 OF 10)

PLACE_NEAR=U1800.BK20:2.54mm

1

FDI_RXN0

MOBILE-SFF

DMI1RXP

BL19

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

U1800

COUGAR-POINT

R E T W N O E P M E M G E A T N S A Y M S

SYS_RESET* SYS_PWROK PWROK DRAMPWROK DPWROK APWROK

RSMRST*

WAKE*

BK12 BH8

FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>

OUT

LVDS_IG_BKL_PWM

L49 L_BKLTCTL

FCBGA (4 OF 10)

L51 L_DDC_CLK K46

OMIT_TABLE

R19551 100K

5% 1/20W MF 2012

FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3> FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7> FDI_INT

FDI_LSYNC<0> FDI_LSYNC<1>

NC NC NC NC NC NC

OUT OUT

NC NC NC NC

OUT OUT

NC NC

MAKE_BASE=TRUE

CLKRUN*/GPIO32

SUS_STAT*/GPIO61 SUSCLK/GPIO62 SLP_S5*/GPIO63 SLP_S4*

SUSWARN*/SUSPWRDNACK/GPIO30

SLP_S3* SLP_A*

PWRBTN*

T2

PM_CLKRUN_L

BI

G6

LPC_PWRDWN_L

D3

PM_CLK32K_SUSCLK_R OUT

F6

PM_SLP_S5_L

OUT

K10

PM_SLP_S4_L

OUT

D4

PM_SLP_S3_L

OUT

C7

TP_PM_SLP_A_L

BB8

PM_SYNC

OUT

=PPVRTC_G3_PCH

ACPRESENT/GPIO31 BATLOW*/GPIO72

PMSYNCH

RI*

SLP_LAN*/GPIO29

A7

TP_CRT_IG_BLUE TP_CRT_IG_GREEN TP_CRT_IG_RED

R19151 390K

OUT

GPIO29_SLP_LAN_L

TP_CRT_IG_DDC_CLK TP_CRT_IG_DDC_DATA

R1909 100K

DSWVRMEN SLP_SUS* SUSACK*

F22 A15 F15

M42

L_BKLTEN L_VDD_EN

PM_SLP_SUS_L

R42 M40

L_CTRL_DATA

E C A F R E T N I

AR44 LVDSA_DATA0 AN51 LVDSA_DATA1 AN46 LVDSA_DATA2

NC NC NC NC

M46 R46 U46

S D V L

Y A L P S I D L A T I G I D

CRT_BLUE CRT_GREEN

CRT_RED

R49

CRT_DDC_CLK

N49

CRT_DDC_DATA

PCH_DAC_IREF

R51

N51

T48

1K

5% 1/20W PLACE_NEAR=U1800.R51:2.54mm MF 2 201

Set to Vss when Low Set to Vcc when High

DDPB_HPD AY42

LVDSA_DATA_0* AN49 LVDSA_DATA_1* AN44 LVDSA_DATA_2* AK40 LVDSA_DATA_3*

AM48 LVDSB_DATA0 AL51 LVDSB_DATA1 AJ49 LVDSB_DATA2 AH48 LVDSB_DATA3

R44

DDPB_AUXP AW49

AR46

AM50 LVDSB_DATA_0* AL49 LVDSB_DATA_1* AJ51 LVDSB_DATA_2* AH50 LVDSB_DATA_3*

W42

DDPB_AUXN AW51

LVDSA_CLK* AK46 LVDSA_CLK

M50

R1951

DF_TVS:DMI & FDI Term Voltage

SDVO_CTRLCLK

AK44

NC NC NC NC

SDVO_STALLN AR51 SDVO_STALLP AR49

SDVO_CTRLDATA

AG51 LVD_VREFH AG49 LVD_VREFL

AH46 LVDSB_CLK* AH44 LVDSB_CLK

AU40

SDVO_TVCLKINP AU42

SDVO_INTP AT48

L_CTRL_CLK

AK42 LVDSA_DATA3

SDVO_TVCLKINN

SDVO_INTN AT50

AH42 LVD_IBG AH40 LVD_VBG

TP_CRT_IG_HSYNC TP_CRT_IG_VSYNC

1

IN

MOBILE-SFF

L_DDC_DATA

CRT_HSYNC CRT_VSYNC

PCH_DSWVRMEN

PCH_SUSACK_L

COUGAR-POINT

DDPB_0N

AY48

DDPB_0P AY50 DDPB_1N AY44 DDPB_1P AY46 DDPB_2N DDPB_2P DDPB_3N

BB44 BB46 BA49

DDPB_3P BA51 DDPC_CTRLCLK

T50

DDPC_CTRLDATA

U44

DDPC_AUXN AU51 DDPC_AUXP AU49

DDPC_HPD

BE46

BC49 DDPC_0N DDPC_0P BC51 BD48 DDPC_1N DDPC_1P BD50 DDPC_2N BF46 DDPC_2P BF45 DDPC_3N BE49 DDPC_3P BE51 DDPD_CTRLCLK

M48

DDPD_CTRLDATA

U42

DDPD_AUXN AU46

5% 1/20W MF 2012

1

5% 1/20W MF 2 201

NC NC

NC NC

=T29_WAKE_LIN PCIE_WAKE_L IN

D8

NC NC

NC NC

OUT

FDI_FSYNC<0> FDI_FSYNC<1>

U1800

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

M44

OUT

OUT

DAC_IREF CRT_IRTN

DDPD_AUXP AU44

DDPD_HPD BK44

T R C

DDPD_0N BG51 DDPD_0P BG49 DDPD_1N BF42 DDPD_1P BD42 BJ47 DDPD_2N DDPD_2P BL47 BL45 DDPD_3N DDPD_3P BJ45

TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP

D

TP_SDVO_STALLN TP_SDVO_STALLP TP_SDVO_INTN TP_SDVO_INTP DP_IG_B_DDC_CLK DP_IG_B_DDC_DATA DP_IG_B_AUX_N DP_IG_B_AUX_P DP_IG_B_HPD TP_DP_IG_B_MLN<0> TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3> TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA TP_DP_IG_C_AUXN TP_DP_IG_C_AUXP TP_DP_IG_C_HPD

C

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1> TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2> TP_DP_IG_C_MLP<2> TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3> TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA TP_DP_IG_D_AUXN TP_DP_IG_D_AUXP TP_DP_IG_D_HPD TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1> TP_DP_IG_D_MLP<1> TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3> TP_DP_IG_D_MLP<3>

B

B R1986 PCH_SUSWARN_L

2

0

1

PCH_SUSACK_L

5% 1/20W MF 201


R19911 8.2K

5% 1/20W MF 2012

=PP3V3_SUS_GPIO

PM_CLKRUN_L

=PP3V3_S5_PCH =PP3V3_SUS_GPIO NOSTUFF 1

R1925 1K

1% 1/20W MF 201 2

A

1

1

R19821

R19831

5% 1/20W MF 201 2

5% 1/20W MF 2012

5% 1/20W MF 201 2

R1985 R1984 10K 1K

1% 1/20W 2 MF 201

10K

10K

PCH_SUSWARN_L GPIO29_SLP_LAN_L PM_BATLOW_L

A PAGE TITLE

PCH DMI/FDI/GRAPHICS

PM_PWRBTN_L PCIE_WAKE_L

DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

19 OF 109

8

7

6

www.laptopblue.vn 5

NC NC NC NC NC NC NC NC NC FIXME: NEED INTEL APPROVAL OF NC ON TPS NC NC TP_PM_TEST_RST_L

D

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

C

7

=PP3V3_S0_PCH_GPIO

R2010 R2011 R2012 R2013 R2016 R2017 R2018

2 10K 2 01 2 10K 2 01 2 10K 2 01 2 10K 2 01

2 10K 2 01 2 10K 2 01 2 10K 201

1 1 1 1 1 1 1

5% 1/ 20WMF 5% 1/ 20WMF 5% 1/ 20WMF 5% 1/ 20WMF 5% 1/ 20WMF 5% 1/ 20WMF 5% 1/20WMF 18 18 18

R2030 R2031

B

R2015

2 10K 201 2 10K 201

10K

1 1

NOSTUFF 1

2 201

5% 1/20WMF 5% 1/20WMF 63

IN

39 6

IN

39 6

5% 1/20WMF

IN

6

26 25

OUT

69 25

OUT

25

OUT

25

OUT

6

BH24 TP1 BK24 TP2

COUGAR-POINT

U1800

RSVD_BE3

MOBILE-SFF

RSVD_BE1

BH20 TP3 BK16 TP4

FCBGA (5 OF 10)

RSVD_AU8

BH16 TP5 AN42 TP6

RSVD_BA3

RSVD_AW3

TP10

RSVD_AW1

TP11

RSVD_AY6

E3

TP12

RSVD_AY2

TP13

RSVD_AY4

TP14

RSVD_BC3

TP15

RSVD_BC1

AD10 TP16

RSVD_BG1

AM4 AT4 AT2 B24 D24

TP17

RSVD_BG3

TP18

RSVD_BE6

AD44

TP19 AD46 TP20 BJ48 TP21 BL7

TP22

W40

TP23

K30

TP24 BH49 TP41 BB42 TP42

RSVD_BH4 RSVD_BF7

D V S R P T

BJ25 TP25 BJ27 TP26 BJ31 TP27 BJ29 TP28 BL25 TP29

F42 D44

GNT3*/GPIO55

PCI_INTE_L AUD_IP_PERIPHERAL_DET T29_MCU_INT_L AUD_I2C_INT_L

A47

PIRQE*/GPIO2

C41

PIRQF*/GPIO3

H42

B S U

F45 F40 H2 F7 G51

PIRQG*/GPIO4 PIRQH*/GPIO5 PME* PLTRST* CLKOUT_PCI0

I C P

J43 G45

CLKOUT_PCI3 CLKOUT_PCI4

A

NOSTUFF

R20541

5% 1/20W MF 2012

5% 1/20W MF 201 2

5% 1/20W MF 201 2

10K

10K

B28 H26

D32 B32 M28

USBP8P

K28

USBP9N

C29

USBP10P USBP11N

A29 C31 A31 H33

USBP11P

F33

USBP12N

H30

USBP12P USBP13N USBP13P

F30 M33 K33 C33

USB_HUB1_UP_N USB_HUB1_UP_P

BI

24 68

BI

24 68

NC_USB_1N NC_USB_1P

USB HUB 1

Unused

NC_USB_2N NC_USB_2P

Unused

NC_USB_3N NC_USB_3P

Unused

NC_USB_4N NC_USB_4P

Unused

NC_USB_5N NC_USB_5P

Unused

NC_USB_6N NC_USB_6P

Unused

NC_USB_7N NC_USB_7P

Unused

USB_HUB2_UP_N USB_HUB2_UP_P

BI

USB_CAMERA_N USB_CAMERA_P

BI

USB HUB 2

BI

B Camera

BI

NC_USB_10N NC_USB_10P NC_USB_11N NC_USB_11P

Unused

1

R2061

5% 1/20W MF 2201

Unused

NC_USB_13N NC_USB_13P

Unused

R20621

5% 1/20W MF 201 2

5% 1/20W MF 201 2

10K

PCH_USB_RBIAS

A17 A13 D16 A11

NOSTUFF

R20601

C17

OC4*/GPIO43

R20651

7 19

=PP3V3_SUS_GPIO

7 16 17 19

B16 C23 H15

10K

10K

1

R2068

10K

10K

NC_USB_12N NC_USB_12P

68

=PP3V3_S3_PCH_GPIO Unused

A33

OC3*/GPIO42

OC7*/GPIO14 NOSTUFF

D28

USBP7N

OC6*/GPIO10

R20531

K26

F26

OC5*/GPIO9

NOSTUFF

H28

USBP6P

OC2*/GPIO41

R20521

C25

M26

OC1*/GPIO40

PCH_PCI_GNT3_L PCH_PCI_GNT2_L PCH_PCI_GNT1_L

H24

USBP4N

OC0*/GPIO59

18

F24

F28

USBP10N

C

NC NC

USBP3P

E49

CLKOUT_PCI1 H48 CLKOUT_PCI2

NC NC

BF6

A27

USBP9P

CPU_PROC_SEL_L

2

5% 1/20W MF 201

BA1

C27

USBP8N

1K

1

NC

USBP2P

USBP7P

R2080 PCH_DF_TVS

BD4

USBP2N

USBP6N

5% 1/20W MF 201 2

BD2

USBP1P

USBP5P

2.2K

NC

A25

USBP5N

REQ2*/GPIO52

GNT2*/GPIO53

RSVD_BB6

BB6

USBP4P

REQ1*/GPIO50

GNT1*/GPIO51

BL5

USBP3N

F46 REQ3*/GPIO54

NC

BC7

USBP1N


R20811

AY8

DF_TVS

USBP0P

PIRQD*

NC AW3 NC AW1 NC AY6 NC AY2 NC AY4 NC BC3 NC BC1 NC BG1 NC BG3 NC BE6 NC BH4 NC BF7 NC BJ4 NC BJ5 NC BK6 NC

RSVD_BL5

USBP0N

BD28 TP39 BD30 TP40

PCH_PCI_GNT1_L PCH_PCI_GNT2_L PCH_PCI_GNT3_L

RSVD_AY8

RSVD_BF6

BF30 TP36 BD26 TP37 AY28 TP38

K44

RSVD_BK6

RSVD_BA1

BL29 TP32 BF26 TP33 BB28 TP34 BF28 TP35

JTAG_GMUX_TMS T29_A_HV_EN_L PCI_REQ3_L

RSVD_BJ5

RSVD_BD2 RSVD_BD4

BL27 TP30 BL31 TP31

C45

RSVD_BJ4

USBRBIAS

18

NC NC

AR42 TP9 M30

D

BA3

AU6

USBRBIAS*

18

NC NC NC NC

BJ7

BH3

D20

1

AU8

RSVD_AU6

G46

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

OMIT_TABLE

2

BE1

RSVD_BH3

D49 PIRQA* C48 PIRQB* C47 PIRQC*

PLT_RESET_L

RSVD_BJ7

3

BE3

AN40 TP7 AR40 TP8

PCI_INTA_L PCI_INTB_L PCI_INTC_L PCI_INTD_L

TP_PCI_PME_L

4

5% 1/20W MF 201 2 1

R2064 10K

5% 1/20W MF 2201

1

R2067 10K

5% 1/20W MF 2 201

PUs TO S0 INSTEAD?

10K

5% 1/20W MF 2 201

NOTE: PULLUP IS REQUIRED ON AP_PWR_EN IF ISOLATION RESISTOR R2090 IS UNSTUFFED

R20691

R2090

10K

5% 1/20W MF 201 2

2

PCH_GPIO59_OC0_L USB_HUB_SOFT_RESET_L SDCONN_STATE_RST_L 23 ENET_PWR_EN 23 PCH_GPIO43_OC4_L 23 SDCONN_STATE_CHANGE 23 PCH_GPIO10_OC6_L 23 PCH_GPIO14_OC7_L 23

0

1

AP_PWR_EN

5% 1/20W MF 201

SYNC_MASTER=K21_MLB

R20701


PAGE TITLE

22.6

1% 1/20W MF 2012

PCH PCI/FLASHCACHE/USB DRAWING NUMBER PLACE_NEAR=U1800.C33:2.54mm

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

20 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

=PP3V3_S0_PCH

R21501

1

10K

5% 1/20W MF 201 2

SMC_IG_THROTTLE_L FW_PME_L GMUX_INT SMC_RUNTIME_SCI_L NC_GPIO8 PCH_GPIO12 PCH_GPIO15

IN

D

IN IN

JTAG_ISP_TCK

=PP3V3_S0_PCH

IN

R21901

ODD_PWR_EN_L

100K

GMUX_INT

5% 1/20W MF 201 2

OUT

OUT

R21121

R21131

5% 1/20W MF 2012

5% 1/20W MF 201 2

5% 1/20W MF 201 2

20K

10K

10K

IN OUT

(PUnecessary?)

OUT

IN

(NC-ed per Intel chklist)

=PP3V3_SUS_GPIO

BI

C

R21921

R21931

R21941

5% 1/20W MF 201 2

5% 1/20W MF 201 2

5% 1/20W MF 201 2

5% 1/20W MF 201 2

10K

10K

10K

100K

JTAG_ISP_TDO JTAG_ISP_TDI FW_PWR_EN ENET_LOW_PWR SPIROM_USE_MLB MLB_RAM_CFG3 MLB_RAM_CFG2 MLB_RAM_CFG1 MLB_RAM_CFG0

NOSTUFF

R21951

LPCPLUS_GPIO ODD_PWR_EN_L PCH_GPIO24 SMC_SCI_L ISOLATE_CPU_MEM_L T29_SW_RESET_L PCH_GPIO35 PCH_GPIO36_SATA2GP JTAG_ISP_TCK

BMBUSY*/GPIO0 TACH1/GPIO1

C43

(IPU)

TACH2/GPIO6

A45

TACH3/GPIO7

H17

GPIO8

C5 (IPU)

AUD_IPHS_SWITCH_EN_PCH

BI

R21111

W1 B40

U1800

MOBILE-SFF

B44

TACH0/GPIO17

W3

PROCPWRGD

AU10

THRMTRIP*

BC9

TS_VSS1

AK10

TS_VSS2

AH12

TS_VSS3

AK12 AH10

TS_VSS4

GPIO24/MEM_LED

C15

GPIO28

R3

GPIO35

W6

SATA2GP/GPIO36

M6

SATA3GP/GPIO37

N3 U1

VSS_NCTF_A51

A51

VSS_NCTF_BH1

BH1 BJ1

VSS_NCTF_BJ3

BJ3

SATA5GP/GPIO49

K17

GPIO57

K42

TACH4/GPIO68

VSS_NCTF_BL1

TACH5/GPIO69

VSS_NCTF_BL3

TACH6/GPIO70 TACH7/GPIO71

VSS_NCTF_BL4 VSS_NCTF_BL48

A43 D40 A41

BJ49

VSS_NCTF_BJ51

BJ51

R21911

NOSTUFF1

R2130 1K

5% 1/20W MF 201 2


R21961

BL4

10K

BL48

VSS_NCTF_BL49

BL49

VSS_NCTF_BL51

BL51

NOSTUFF1

R2197 10K

5% 1/20W MF 201 2

C

5% 1/20W MF 201 2

C3

T29_SW_RESET_L SMC_RUNTIME_SCI_L

C49 C51 D1

VSS_NCTF_D1

D51

VSS_NCTF_D51

E1

VSS_NCTF_E1 (PUs

10K

PCH_INIT3V3_L

BL3

VSS_NCTF_C51 (PUnecessary?)

USING IT.

BL1

VSS_NCTF_C49

PCH_GPIO12 SPIROM_USE_MLB PCH_GPIO24 ISOLATE_CPU_MEM_L

PM_THRMTRIP_L IN

2 MF

ALL RSVD TPs NC-ed per INTEL approval

VSS_NCTF_BJ49

VSS_NCTF_C3

=PP3V3_S5_PCH

5% 201

BH51

VSS_NCTF_BJ1

AA1

390

A5

VSS_NCTF_A5

F T C N

SDATAOUT1/GPIO48

R2156

1 1/20W

A49

VSS_NCTF_A49

VSS_NCTF_BH51

SDATAOUT0/GPIO39

D OUT

A48

VSS_NCTF_A48

O I P G

SLOAD/GPIO38

U10

5% 1/20W MF 201

A4

VSS_NCTF_A4

STP_PCI*/GPIO34

W12

U40

NC_1

GPIO27

G1

10K

NOSTUFF

2 R2170 PCH_A20GATE 43 1 2 PCH_PECI CPU_PECI 1/20W MF R2140 PCH_RCIN_L 5% 201 0 1 2 PCH_PROCPWRGD CPU_PWRGD 201 1/20W 5% MF PM_THRMTRIP_L_R PCH_INIT3V3_L This has internal pull up and should not pulled low. THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT

C U S P I M C

SCLOCK/GPIO22

K15

R6

INIT3_3V*

GPIO15

SATA4GP/GPIO16

U6

RCIN*

FCBGA (6 OF 10)

LAN_PHY_PWR_CTRL/GPIO12

K6

AU12

PECI

OMIT_TABLE

AA3

U3

A20GATE

COUGAR-POINT

R2155

=PP3V3_T29_PCH_GPIO

necessary?)

5% 1/20W MF 2012

R21991 SMC_SCI_L

10K

=PP3V3_S3_PCH_GPIO 1

=PP3V3_T29_PCH_GPIO =PP3V3_S0_PCH_STRAPS

1

1

R2160 R2184 10K

5% 1/20W MF 201 2

C2152 0.1UF

2

1

5% 1/20W MF 201 2

R2185

10K

10K

5% 1/20W MF 201 2

5% 1/20W MF 201 2

1

R2186

T29_PWR_EN_PCH

IN

5

10K

5% 1/20W MF 201 2

PM_PCH_PWROK

6

10% 16V

X5R-CERM 0201

SOT833

A

U2150Y B

T29_PWR_EN

3

NOSTUFF OUT

08

B

R21981

R21101

5% 1/20W MF 201 2

5% 1/20W MF 2012

10K

4 IN

JTAG_ISP_TDI PCH_GPIO36_SATA2GP ENET_LOW_PWR

8 74LVC2G08GT


10K

B

R2152 JTAG_ISP_TDO

2

FW_PME_L FW_PWR_EN SMC_IG_THROTTLE_L

0

1 AUD_IPHS_SWITCH_EN_PCH_R

5% 1/20W MF 201

1

PM_PCH_PWROK

2

8 74LVC2G08GT

SOT833

A

AUD_IPHS_SWITCH_EN

U2150Y 7 B

OUT

08 4

WOL_EN

=PP3V3_SUS_GPIO

1

R21151

R2114 10K

10K

5% 1/20W MF 201 2

5% 1/20W MF 2012

PCH_GPIO46 GPIO[68:71] have 15K-45K internal PUs

MLB_RAM_CFG3


A

DRAM_CFG0:H

R21751 10K

5% 1/20W MF 201 2

DRAM_CFG1:H

DRAM_CFG2:H

R21741

R21731

5% 1/20W MF 201 2

5% 1/20W MF 201 2

10K

10K

MLB_RAM_CFG2 DRAM_CFG3:H

MLB_RAM_CFG1

R21721 10K

SYNC_MASTER=K21_MLB

MLB_RAM_CFG0

5% 1/20W MF 201 2

R2162

1

1K

MLB_RAM_CFG3


PAGE TITLE

DRAM_CFG3:L

5% 1/20W MF 201

DRAM_CFG2:L 1

R2163 1K 5% 1/20W MF

2

2 201

DRAM_CFG1:L

R2164

1

1K 5% 1/20W MF 201

DRAM_CFG0:L

PCH MISC

1

R2165

DRAWING NUMBER

1K

Apple Inc.

5% 1/20W MF

2

2 201

051-8870

SIZE

D

REVISION

3.13.0

R

MLB_RAM_CFG2


BRANCH

MLB_RAM_CFG1


PAGE

MLB_RAM_CFG0

21 OF 109

A

8

7

VCCACLK pin left as NC per DG

AC51 VCCACLK

NC

R12 VCCDSW3_3

=PP3V3_S5_PCH_VCCDSW

22 7

VCCAPLLDMI2 pin left as NC per DG

U1800

AW31 VCCAPLLDMI2 AP27 VCCIO_AP27

VCCSUS3_3_R29 B S U

AB27 VCCASW_AB27 AB29 VCCASW_AB29 AB31 VCCASW_AB31 AC27 VCCASW_AC27 AC29 VCCASW_AC29 AC31 VCCASW_AC31 AE27 VCCASW_AE27 AE29 VCCASW_AE29 AE31 VCCASW_AE31 U21 VCCASW_U21 V21 VCCASW_V21 V23 VCCASW_V23 V25 VCCASW_V25 Y21 VCCASW_Y21 Y23 VCCASW_Y23 Y25 VCCASW_Y25 Y27 VCCASW_Y27

R15

PPVOUT_G3_PCH_DCPRTC

1

C2210 0.1UF

20 7

10% 16V 2 X5R-CERM

20

0201

20

PLACE_NEAR=U1800.R15:2.54mm 22 16 7

DCPRTC_R15

A T A S

AC37 VCCDIFFCLKN_AC37 AE37 VCCDIFFCLKN_AE37

=PP1V05_S0_PCH_VCCDIFFCLK

MIN_LINE_WIDTH=0.2 mm

C2222

MIN_NECK_WIDTH=0.2 mm 22 7

0.1UF

10% 2 16V X5R-CERM

17 16 7

U17 DCPSST

VOLTAGE=3.3V


AM17 V_PROC_IO N16 VCCRTC

=PPVRTC_G3_PCH

0201

1

C2231 1UF

10% 2 6.3V CERM 402

1

C2232 0.1UF

10% 16V 2 X5R-CERM

0201

7

22

per DG

AM27

=PP3V3_SUS_PCH_VCCSUS

N36

=PP5V_S0_PCH_V5REF

R33


7

U35 7 22

22 7

=PP1V05_S0_PCH_VCCIO_PLLPCIE

AM21 VCCIO_AM21

TP_1V05_S0_PCH_VCCAPLLEXP

AP19 VCCAPLLEXP


AR15 VCCIO_AR15 AT13 VCCIO_AT13

AC19 R40

=PP1V05_S0_PCH_VCCIO_SATA

7 22

1

E S

C A T D R H

VCCASW_U19 U19 V19

VCCSUSHDA

V31

AJ37 T39

=PP3V3_S0_PCH_VCC3_3_HVCMOS

7 22

U37

VCCVRM_AU21

AU21

VCCVRM_AW21

AW21

VCCDMI_AM23

AM23

VCCCLKDMI

AP39

PP1V05_S0_PCH_VCCCLKDMI_F

VCCDFTERM_AJ13

AJ13


=PP1V8R1V5_S0_PCH_VCCVRM =PP1V05_S0_PCH_VCC_DMI

7 20

7 22

22

7 18 22

AJ15

O I C C V

VCCDFTERM_AJ15 I VCCDFTERM_AK15 AK15 P S VCCDFTERM_AL13 AL13 / D N VCCSPI Y19 A N

=PP3V3_S5_PCH_VCC_SPI

7 22

C

AU35 VCCIO_AU35 AW34 VCCIO_AW34

VCCAPLLSATA pin left as NC per DG

=PP1V8R1V5_S0_PCH_VCCVRM

7 20


22 7

=PP3V3_S0_PCH_VCC3_3_PCI

20 7


7 16 20 22

VCCAFDIPLL pin left as NC per DG

=PP1V05_S0_PCH_VCCASW

7 20 22

VCCASW_R19 R19 VCCASW_V19

D

AU29 VCCIO_AU29

VCCIO_AC15 AC15

U U P F C

AG39

VCCTX_LVDS_AJ37

I M D

AR29 VCCIO_AR29 AU23 VCCIO_AU23 AU25 VCCIO_AU25 AU27 VCCIO_AU27

7 16 20 22

AF37 AG37

VCCTX_LVDS_AG39

VCC3_3_U37

22

AE33

VCCTX_LVDS_AG37

HVCMOS

AR23 VCCIO_AR23 AR25 VCCIO_AR25 AR27 VCCIO_AR27

VCCIO_AF15 AF15 VCCAPLLSATA AM2 NC

AC33

7 22

U33

=PP3V3_S0_PCH_VCC3_3_SATA

AG33

AM33 VCCCORE_AM33 AM35 VCCCORE_AM35

22

R35

=PP3V3_S0_PCH_VCC3_3_GPIO

AF33

VCCALVDS_AG33

VCC3_3_T39

PP3V3_S0_PCH_VCCA_DAC_F

V50

VCCALVDS_AF33

AK29 VCCCORE_AK29 AK31 VCCCORE_AK31 AK33 VCCCORE_AK33

7

U51

S VSSALVDS_AC33 E D R V VSSALVDS_AE33 O L C VCCTX_LVDS_AF37

C C V

AJ27 VCCCORE_AJ27 AJ29 VCCCORE_AJ29 AJ31 VCCCORE_AJ31

AC35 VCCSSC

=PP1V05_S0_PCH_VCCSSC PPVOUT_S0_PCH_DCPSST 22 7

PLACE_NEAR=U1800.U17:2.54mm

=PP5V_SUS_PCH_V5REFSUS

VCCIO_AB15 AB15 VCCIO_AC13 AC13

AE39 VCCDIFFCLKN_AE39

1

V5REF_SUS M37

VCCVRM_AE19 AE19 VCCVRM_AF17 AF17

AJ17 VCCIO_AJ17

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCIO_PLLUSB

VCCIO_AG13 AG13 VCCIO_AG15 AG15

BF40 VCCADPLLA BD40 VCCADPLLB

PP1V05_S0_PCH_VCCADPLLA PP1V05_S0_PCH_VCCADPLLB

AJ21 VCCCORE_AJ21 AJ23 VCCCORE_AJ23 AJ25 VCCCORE_AJ25

N27

VCCIO_N18 N18

AB19

VSSADAC

AG25 VCCCORE_AG25 AG27 VCCCORE_AG27

VCCSUS3_3_U29 U29 VCCSUS3_3_N27

OMIT_TABLE VCCADAC CRT

AG21 VCCCORE_AG21 AG23 VCCCORE_AG23

7 22

VCCIO_AA13 AA13

AC39 VCCVRM_AC39


22 20 7

=PP3V3_SUS_PCH_VCCSUS_USB

1

U1800

AB21 VCCCORE_AB21 COUGAR-POINT AB23 VCCCORE_AB23 MOBILE-SFF AC21 VCCCORE_AC21 FCBGA AC23 VCCCORE_AC23 (7 OF 10) AE21 VCCCORE_AE21 AE23 VCCCORE_AE23

7 22

R29

VCC3_3_AF6 AF6

U15 DCPRTC_U15


Idle

VCCSUS3_3_U27 U27

C S VCCSUS3_3_AM27 I M / V5REF K C O C VCCSUS3_3_R33 P L C L VCCSUS3_3_R35 / O VCCSUS3_3_U33 I P VCCSUS3_3_U35 G / VCC3_3_AB19 I C VCC3_3_AC19 P VCC3_3_R40

Y29 VCCASW_Y29 Y31 VCCASW_Y31

MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.2 mm mm VOLTAGE=3.3V

Max, 474mA

2

AF21 VCCCORE_AF21 AF23 VCCCORE_AF23

DCPSUS_AU31 AU31 NC NC-ed

PCH output, for decoupling only

C


VCCSUS3_3_R27 R27

DCPSUS_V13

AR33 DCPSUS_AR33 NC AU33 DCPSUS_AU33 NC


A

OMIT_TABLE

AL24 left as NC per DG

22 20 7

1.44

VCCIO_U23 U23 VCCIO_U25 U25

V13

=PP1V05_S0_PCH_VCC_CORE

22 7

VCCIO_R23 R23 VCCIO_R25 R25

NC

3

FCBGA (8 OF 10)

NC


22 20 7

4

MOBILE-SFF

V37 VCC3_3_V37 V39 VCC3_3_V39

PP3V3_S0_PCH_VCC3_3_CLK_F

D

5

COUGAR-POINT

R10 DCPSUSBYP

TP_PPVOUT_PCH_DCPSUSBYP 22

www.laptopblue.vn

6

=PP3V3R1V5_S0_PCH_VCCSUSHDA

BK28 VCC3_3_BK28 AU19 VCCVRM_AU19 AW18 VCCVRM_AW18 AP13 VCCAFDIPLL_AP13 NC AP15 VCCAFDIPLL_AP15 NC

7

=PP1V05_S0_PCH_VCCIO_PLLFDI

AK21 VCCIO_AK21

7

=PP1V05_S0_PCH_VCCDMI_FDI

AU15 VCCDMI_AU15 AW16 VCCDMI_AW16

7 16 22

I D F

10 mA Max, 1mA Idle

C2233 0.1UF

10% 16V 2 X5R-CERM

0201

PLACE_NEAR=U1800.N16:2.54mm PLACE_NEAR=U1800.N16:2.54mm PLACE_NEAR=U1800.N16:2.54mm

B

B

PCH VCCADPLLA Filter

R2260 7

=PP1V05_S0_PCH_VCCADPLL

1

0

(PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA

2

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

5% 1/16W MF-LF 402

1

C2260 0.1UF

10% 16V 2 X5R-CERM

0201

1

C2261

20

68 mA

PLACE_NEAR=U1800.BF40:2.54MM

1UF

10% 2 6.3V CERM 402

PCH VCCADPLLB Filter

R2265 1

0

5% 1/16W MF-LF 402

(PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB

2

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1

C2265 0.1UF

10% 2 16V X5R-CERM

0201

1

C2266

20

69 mA

PLACE_NEAR=U1800.BF40:2.54MM

1UF

10% 2 6.3V CERM 402

A

A PAGE TITLE

PCH POWER DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


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22 OF 109

8

7

G7 VSS_G7 AA7 VSS_AA7 AA9 VSS_AA9

AA11 VSS_AA11 AA39 VSS_AA39

D

AA41 VSS_AA41 AA43 VSS_AA43 AA45 VSS_AA45 AB2 VSS_AB2 AB4

VSS_AB4

AB17 VSS_AB17 AB25 VSS_AB25 AB33 VSS_AB33

FCBGA (9 OF 10) VSS_AL7 VSS VSS_AL9

T F N F I S O P E - L R I A B G O U M O C

OMIT_TABLE

AL7 AL9

VSS_AL11 AL11 VSS_AL39 AL39 VSS_AL41 AL41 VSS_AL43 AL43 VSS_AL45 AL45 VSS_AM15 AM15 VSS_AM19 AM19 VSS_AM25 AM25 VSS_AM29 AM29 VSS_AM31 AM31

AB50 VSS_AB50

VSS_AP7 AP7

AC25 VSS_AC25 AC41 VSS_AC41 AC43 VSS_AC43 AC45 VSS_AC45 AE7 VSS_AE7 AE9 VSS_AE9 AE11 VSS_AE11 AE13 VSS_AE13

AE15 VSS_AE15 AE17 VSS_AE17 AE25 VSS_AE25 AE35 VSS_AE35 AE41 VSS_AE41 AE43 VSS_AE43 AE45 VSS_AE45 AF2 VSS_AF2 AF4 VSS_AF4 AF8 VSS_AF8 AF19 VSS_AF19 AF25 VSS_AF25

AF27 VSS_AF27 AF29 VSS_AF29

VSS_AP2 AP2 VSS_AP4 AP4 VSS_AP9

AP9

VSS_AP11 AP11 VSS_AP17 AP17 VSS_AP21 AP21 VSS_AP23 AP23 VSS_AP25 AP25 VSS_AP29 AP29 VSS_AP31 AP31 VSS_AP33 AP33 VSS_AP35 AP35 VSS_AP37 AP37 VSS_AP41 AP41 VSS_AP43 AP43 VSS_AP45 AP45 AP48 VSS_AP48 VSS_AP50 AP50 VSS_AR6 AR6 VSS_AR8 AR8 VSS_AR17 AR17 VSS_AR19 AR19 VSS_AR21 AR21 VSS_AR31 AR31 VSS_AR35 AR35 VSS_AR37 AR37 VSS_AT7

AT7

VSS_AT9

AT9


VSS_AT11 AT11 VSS_AT39 AT39


VSS_AT41 AT41 VSS_AT43 AT43

AG7

VSS_AG7 AG9 VSS_AG9 AG11 VSS_AG11 AG17 VSS_AG17

VSS_AT45 AT45 VSS_AU17 AU17 VSS_AU37 AU37

AG19 VSS_AG19 AG29 VSS_AG29

VSS_AV4 AV4 VSS_AV48 AV48

AG31 VSS_AG31 AG35 VSS_AG35 AG41 VSS_AG41

VSS_AV50 AV50 VSS_AW7 AW7

VSS_AV2 AV2

AW9

AG43 VSS_AG43 AG45 VSS_AG45

VSS_AW9 VSS_AW11 AW11 VSS_AW13 AW13

AH2 VSS_AH2 AJ7 VSS_AJ7

VSS_AW23 AW23 VSS_AW25 AW25

AJ9 VSS_AJ9

VSS_AW27 AW27 VSS_AW29 AW29

AJ11 VSS_AJ11 AJ19 VSS_AJ19 AJ33 VSS_AJ33 AJ35 VSS_AJ35 AJ39 VSS_AJ39 AJ41 VSS_AJ41 AJ43 VSS_AJ43 AJ45 VSS_AJ45 AK2 VSS_AK2 AK4 VSS_AK4 AK17 VSS_AK17 AK19 VSS_AK19 AK23 VSS_AK23

AK25 VSS_AK25 AK27 VSS_AK27 AK35 VSS_AK35 AK37 VSS_AK37

A

U1800

VSS_AM37 AM37

AC11 VSS_AC11 AC17 VSS_AC17

B

5

AB35 VSS_AB35 AB37 VSS_AB37 AB48 VSS_AB48 AC7 VSS_AC7 AC9 VSS_AC9

C

www.laptopblue.vn

6

VSS_AW36 AW36 VSS_AW39 AW39 VSS_AW41 AW41 VSS_AW43 AW43 VSS_AW45 AW45 VSS_AY10 AY10 VSS_B6 B6 VSS_B10 B10

VSS_B14 B14 VSS_B18 B18 VSS_B22 B22 VSS_B26 B26 VSS_B30

B30

BA11 VSS_BA11 BA13 VSS_BA13

VSS_BB48 BB48 VSS_BA31 BA31


VSS_BA34 BA34 VSS_BA36 BA36






VSS_BB4 BB4 VSS_BB2 BB2

G34

VSS_G39 G39 VSS_G41

G41

VSS_G43 G43 VSS_J7 J7 VSS_J9 J9

VSS_J11 J11 VSS_J13 J13 VSS_J18 J18 VSS_J21

J21

VSS_J23 J23 OMIT_TABLE

VSS_J25

J25

VSS_J27

J27

VSS_J36 J36

BE7 VSS_BE7 BE9 VSS_BE9

VSS_J39 J39


VSS_J45 J45

BE21 VSS_BE21 BE23 VSS_BE23 BE25 VSS_BE25 BE27 VSS_BE27

VSS_J31 J31 VSS_J34 J34

VSS_J41 J41 VSS_K2 K2 VSS_K4 K4

VSS_K48 K48 VSS_K50

K50

VSS_L7 L7 VSS_L9 L9

VSS_L11 L11


VSS_L13 L13

BE34 VSS_BE34 BE36 VSS_BE36 BE39 VSS_BE39

VSS_L18 L18

BE41 VSS_BE41 BE43 VSS_BE43 BE45 VSS_BE45 BF2 VSS_BF2

VSS_L25 L25

BF4 VSS_BF4

VSS_L34 L34

BF15 VSS_BF15 BF24 VSS_BF24

VSS_L36 L36

BF48 VSS_BF48 BF50 VSS_BF50

VSS_L41 L41

BH6 VSS_BH6

VSS_L45 L45

VSS_L16 L16 VSS_L21 L21 VSS_L23 L23 VSS_L27 L27

VSS_L39 L39 VSS_L43 L43 VSS_N7 N7 VSS_N9 N9

BH18 VSS_BH18 BH22 VSS_BH22

VSS_N11 N11


VSS_N21 N21


VSS_N25 N25

BH34 VSS_BH34 BH38 VSS_BH38 BH42 VSS_BH42

VSS_N31 VSS_N34 N34

BH44 VSS_BH44 BH46 VSS_BH46 BH48 VSS_BH48

VSS_N41 VSS_N43 N43

BK10 VSS_BK10 BK14 VSS_BK14 BK18 VSS_BK18

VSS_P2 P2 VSS_P4 P4

VSS_N13

N13

VSS_N23 N23 VSS_N29 N29 N31

VSS_N39 N39 N41

VSS_N45 N45

VSS_P48 P48

BK22 VSS_BK22 BK26 VSS_BK26

VSS_P50 P50


VSS_R21 R21


VSS_R37

D6 VSS_D6 D10 VSS_D10 D14 VSS_D14 D18 VSS_D18 D22 VSS_D22 D26 VSS_D26 D30 VSS_D30 D34 VSS_D34 D38

VSS_D38

VSS_R31 R31 R37

VSS_T7 T7 VSS_T9 T9

VSS_T11 T11 VSS_T13

T13

VSS_T41 T41 VSS_T43 T43 VSS_T45 T45 VSS_U31 U31 VSS_U49 U49 VSS_V2 V2 VSS_V4 V4 VSS_V7 V7 VSS_V9 V9

VSS_V11 V11 VSS_V15

V15

VSS_V17

V17

VSS_V27 V27

G9 VSS_G9 G11 VSS_G11

VSS_V33 V33


VSS_V41 V41

G18

VSS_V45

VSS_V29 V29 VSS_V35 V35 VSS_V43 V43 V45


VSS_V48 V48

G25

VSS_Y17

Y17

VSS_Y33

Y33

VSS_G25

G27 VSS_G27 G29 VSS_G29 G31 VSS_G31

B

VSS_R17 R17

F48 VSS_F48 F50 VSS_F50

VSS_G18

C

L29

VSS_L29 VSS_L31 L31



D

VSS_J16 J16

BD24 VSS_BD24


1

VSS_G36 G36

VSS_J29 J29

F2 VSS_F2 F4 VSS_F4

BA7

VSS_G34

2

BC43 VSS_BC43 BC45 VSS_BC45 BD15 VSS_BD15

B42

VSS_B46 B46 VSS_BA7

BC36 VSS_BC36 BC39 VSS_BC39 BC41 VSS_BC41

D42 VSS_D42 D46 VSS_D46

AK48 VSS_AK48 AK50 VSS_AK50

3

BB50 VSS_BB50 U1800 FCBGA BC11 VSS_BC11 BC13 VSS_BC13(10 OF 10) VSS BC16 VSS_BC16 T F BC18 VSS_BC18 N F I S BC21 VSS_BC21 O BC23 VSS_BC23 P E - L BC25 VSS_BC25 R I A B BC27 VSS_BC27 G O BC29 VSS_BC29 U M O BC31 VSS_BC31 C BC34 VSS_BC34

B34

VSS_B34 VSS_B38 B38 VSS_B42

4

VSS_Y15 Y15

VSS_Y35 Y35 VSS_Y37 Y37

SYNC_MASTER=K78_MLB


PAGE TITLE

PCH GROUNDS DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

23 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

PCH VCCSUS3_3 BYPASS

L2406

=PP1V05_S0_PCH

1

20 18 7

R2415

10UH-0.12A-0.36OHM 16 7

1 2 PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

20 16 7



(PCH SUSPEND USB 3.3V PWR)

1

2

0603

1

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE

5% 1/20W MF 201

1

20 7

=PP3V3_SUS_PCH_VCCSUS_USB 1

C2484

1

0.1UF

C2411

1

1

1UF

C2452 1UF

20% 2 6.3V X5R

0201

0201

0201

C2444

20% 2 6.3V X5R

10% 16V 2 X5R-CERM

2 X5R-CERM

0201

2 6.3V CERM-X5R 0402-1

PLACE_NEAR=U1800.AJ15:2.54mm

10% 16V

2 X5R-CERM

20%

C2413

C2440 0.1UF

0.1UF

10% 16V

10UF

PLACE_NEAR=U1800.AP39:2.54mm

1

20

PLACE_NEAR=U1800.AC13:2.54mm

0201

PLACE_NEAR=U1800.AG13:2.54mm

PLACE_NEAR=U1800.R27:2.54mm PCH

D

VCCSUSHDA

BYPASS

D

(PCH HD Audio 3.3V/1.5V PWR)


20 16 7

=PP3V3R1V5_S0_PCH_VCCSUSHDA 1

C2441

20 7

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

20 7

10% 2 16V X5R-CERM


1

4.7UF 20%

6.3V 2 X5R 402

PLACE_NEAR=U1800.AM17:2.54mm PLACE_NEAR=U1800.AM17:2.54mm PLACE_NEAR=U1800.AM17:2.54mm

1

C2417

1

0.1UF

1

C2475

20% 2 6.3V X5R

20% 2 6.3V X5R

0201


0201

C2430

C2476 1UF

1UF

0201


C2416 1


20 7

=PP1V05_S0_PCH_VCCSSC

0.1UF

10% 16V 2 X5R-CERM

10% 16V 2 X5R-CERM

0201

0201

20 7

=PP3V3_S5_PCH_VCC_SPI 1

C2442 1UF

R2450 7

=PP3V3_S0_PCH_VCCADAC

1

0

PP3V3_S0_PCH_VCCA_DAC_F

2

0201

20

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

5% 1/20W MF 201

C2451 1

10UF 20%

10%

1UF

0201

C2419

20% 2 6.3V X5R

0.01UF

20 7

=PP3V3_S5_PCH_VCCDSW

0201

10%

16V X5R-CERM 2 0201

6.3V CERM-X5R 2 0402

C2434

20% 2 6.3V X5R

PLACE_NEAR=U1800.AE37:2.54mm

1UF

C2455 1

0.1UF

=PP1V05_S0_PCH_VCCDIFFCLK 1

=PP1V05_S0_PCH_VCC_DMI 1

C2450 1

20 16 7

PCH VCCIO BYPASS

20 7

C

20% 2 6.3V X5R

PLACE_NEAR=U1800.Y19:2.54mm

16V X5R-CERM 2 0201

C

C2499 1 0.1UF

PLACE_NEAR=U1800.R12:2.54mm

10% 16V

PCH VCC3_3 BYPASS PLACE_NEAR=U1800.U51:2.54mm PLACE_NEAR=U1800.U51:2.54mm

X5R-CERM 2 0201

(PCH PCI 3.3V PWR)

PLACE_NEAR=U1800.U51:2.54mm PCH VCCIO BYPASS PLACE_NEAR=U1800.AM23:2.54mm (PCH USB 1.05V PWR)

20 7

=PP3V3_S0_PCH =PP5V_S0_PCH

19 16 7

7

(PCH Reference for 5V Tolerance on PCI)

7

1

R2405 NC

5% 1/20W MF 201

=PP3V3_S0_PCH_VCC3_3_CLK 1

D2400

5

100

N C

SOT-363

6

1

1

20


1

1


1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

0201

20%

2 6.3V X5R

6.3V CERM-X5R 2

0201

0402-1

<1 MA

=PP5V_S0_PCH_V5REF

PLACE_NEAR=U1800.V37:2.54mm PLACE_NEAR=U1800.V37:2.54mm

20

PCH VCCCORE BYPASS (PCH 1.05V CORE PWR)

20 7

=PP1V05_S0_PCH_VCC_CORE 1

C2481 1UF

20% 2 6.3V X5R

0201

B

=PP3V3_SUS_PCH =PP5V_SUS_PCH

7 7

20 7

2

NC

5% 1/20W MF 201

0.1UF 20% 10V

BAT54DW-X-G

SOT-363

1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

1UF

0201

<1 MA S0-S5

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S0_PCH_VCC3_3_PCI

C2414 1UF

20% 2 6.3V X5R

20 7

1UF

C2460 1 10UF 20%

6.3V CERM-X5R 2 0402

0201

B

1UF

1

C2463 C2401

1

1UF

10UF

0201

6.3V CERM-X5R 2 0402

20% 2 6.3V X5R

0201

20%

20 7

=PP1V05_S0_PCH_VCCIO_CLK 1

C2469

20% 2 6.3V X5R

1

0201

PLACE_NEAR=U1800.AJ17:2.54mm

C2423 0.1UF

0201

PLACE_NEAR=U1800.AF6:2.54mm

10% 16V 2 X5R-CERM

0201

20 7

A


1

=PP3V3_S0_PCH_VCC3_3_HVCMOS

C2424

C2407

=PP3V3_S0_PCH_VCC3_3_SATA

10% 16V 2 X5R-CERM

0.1UF

C2483

20% 2 6.3V X5R

0201

1UF

C2421

1

1

20% 6.3V 2 X5R

0201

PLACE_NEAR=U1800.AU25:2.54mm PLACE_NEAR=U1800.AU25:2.54mm PLACE_NEAR=U1800.AU25:2.54mm PLACE_NEAR=U1800.AU25:2.54mm PLACE_NEAR=U1800.AU25:2.54mm

PLACE_NEAR=U1800.BK28:2.54mm

C2426 1 C2456 1 C2496 C2428 1 1UF

20 7

=PP3V3_S0_PCH_VCC3_3_GPIO

10% 2 16V X5R-CERM PLACE_NEAR=U1800.T39:2.54mm

1

20

0.1UF

20 7

C2429

20% 2 6.3V X5R

PP5V_SUS_PCH_V5REFSUS

CERM 2 402

1

1

1UF

20% 2 6.3V X5R

D2400 NEED PWR CONSTRAINT

C2438 1

20 7

N C

3 2

PLACE_NEAR=U1800.M37:2.54mm

C2482

PLACE_NEAR=U1800.AF23:2.54mm PLACE_NEAR=U1800.AJ25:2.54mm PLACE_NEAR=U1800.AK33:2.54mm


(PCH Reference for 5V Tolerance on USB)

4

R2404 10

1

PLACE_NEAR=U1800.AC21:2.54mm PCH V5REF_SUS Filter & Follower

1

1 mA S0-S5

20% 2 6.3V X5R

C2454 1UF

10UF 20%

10% 10V X5R 2 402

C2446 1UF


PP3V3_S0_PCH_VCC3_3_CLK_F

C2453

NEED PWR CONSTRAINT

1UF

2

0603

PP5V_S0_PCH_V5REF

C2439 1


10UH-0.12A-0.36OHM

2 PP3V3_S0_PCH_VCC3_3_CLK_R

5% 1/16W MF-LF 402

BAT54DW-X-G

2

PLACE_NEAR=U1800.N36:2.54mm

R2451

PCH V5REF Filter & Follower

1

1 mA

L2451

1

0201

C2486 0.1UF 10% 16V

2 X5R-CERM

0201


1

20% 2 6.3V X5R

0201

1UF

20% 2 6.3V X5R

0201

1UF

20% 2 6.3V X5R

0201

22UF

20% 6.3V X5R-CERM1 2 0603

10% 16V

2 X5R-CERM

0201

PLACE_NEAR=U1800.R40:2.54mm

22UF

SYNC_MASTER=K78_MLB


PAGE TITLE

20% 6.3V X5R-CERM1 2 0603

PCH DECOUPLING DRAWING NUMBER

Apple Inc.

C2485 0.1UF

C2420 1

051-8870

SIZE

D

REVISION

3.13.0

R PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm


BRANCH


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24 OF 109

A

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6

5

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1

PROCESSOR MICRO2-XDP CONNECTOR

NOTE: This is not the standard XDP pinout Use with 920-0782 Adapter Flex to support chipset debug

DESIGN NOTE:

ODT AVAILABLE ON JTAG

=PPVCCIO_S0_XDP

XDP_CONN CRITICAL

=PP3V3_S0_XDP

PLACE_NEAR=U1000.L55:2.54MM PLACE_NEAR=U1000.M60

PLACE TDO TERM NEAR SNB XDP CONN

M-ST-SM

R2540

XDP

62

5%

D BI IN

IN

IN IN IN IN

XDP_BPM_L<4>R2560 XDP_BPM_L<5>R2561 XDP_BPM_L<6>R2562 XDP_BPM_L<7>R2563

0

1

5%

0

MF-LF

1

5%

1 1

1/16W

2

1/16W

2

1/16W

XDP_CPU:BPM

402

MF-LF

IN

XDP_CPU:BPM

402

0

MF-LF 5%

1/16W

2

402

0

MF-LF 5%

XDP_CPU:BPM

2

XDP_CPU:BPM

IN IN

402

IN IN

IN IN IN IN

CPU_CFG<12>R2564 CPU_CFG<13>R2565 CPU_CFG<14>R2566 CPU_CFG<15>R2567

0

1

5%

1

61

402

2

0

1

2

XDP_CPU:CFG

402

IN

2

OBSDATA_A2 OBSDATA_A3

CPU_CFG<10> CPU_CFG<11>

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1


PWRGD/HOOK0 HOOK1 VCC_OBS_AB

201

OUT

XDP_CPU_CFG<0> XDP_VR_READY

XDP

PLACE_NEAR=U4900.D10:2.54MM

R2502 1

5%

2

HOOK3

1/20W

MF

BI

201

XDP

CPU_CFG<0>

HOOK2

0

PM_PWRBTN_L

PLACE_NEAR=U1000.B50:2.54MM

OUT

OBSDATA_A1

1/20W

MF

C

OBSDATA_A0

XDP_BPM_L<2> XDP_BPM_L<3>

XDP_CPU_PWRGD XDP_CPU_PWRBTN_L

1K 1

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

1/16W

R2500 5%

OBSFN_A1

XDP_CPU:CFG

402

XDP

CPU_PWRGD

OBSFN_A0

1/16W

MF-LF

PLACE_NEAR=U1000.B46:1MM

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

IN

=SMBUS_XDP_SDA =SMBUS_XDP_SCL

SDA SCL

R2501 1K 5%

1

NC

TCK1 2

1/20W

OUT

XDP_CPU_TCK

TCK0

MF

3

6

5

8

7

OBSFN_C0 OBSFN_C1

IN


IN


IN

9 11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

R2515

34

33

0

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

64

63

OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1


MF-LF

402

402

2

IN

PLACE_NEAR=U1000.J58:2.54MM

XDP

XDP

1

R2513 IN

51

IN

1/20W

OBSDATA_D2 OBSDATA_D3

CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7>

D

2

1

R2514 51

5%

201

OBSDATA_D1

2

PLACE_NEAR=U1000.L56:2.54MM

IN

5% 1/20W

MF

OBSDATA_D0

5% 1/16W

MF-LF

402

XDP_CPU_TDO XDP_CPU_TDI XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L

IN

12

OBSDATA_C0

51

5% 1/16W

MF-LF

PLACE_NEAR=J2500.52:2.54MM


10

MF 201

2

2

PLACEMENT NOTE:

IN

PLACE TCK/TDI/TMS/TRST* TERM NEAR CPU

XDP

IN

IN

5%

1

5%

1

PLACE_NEAR=R1841.1:2.54MM

2

1/20W

ITPXDP_CLK100M_P

IN

MF

IN

201

XDP ITPCLK/HOOK4 ITPCLK#/HOOK5

XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N

RESET#/HOOK6 DBR#/HOOK7

TDI TMS

0

2

1/20W

ITPXDP_CLK100M_N

IN

MF

XDP_CPURST_L XDP_DBRESET_L

201

XDP

XDP_CPU_TDO XDP_CPU_TRST_L XDP_CPU_TDI XDP_CPU_TMS


R2505

OUT

1K 5%

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28 TDO TRSTn


R2516

VCC_OBS_CD

1

2

1/20W

CPU_RESET_L

IN

MF

IN

201

C

OUT OUT OUT

=PP1V05_SUS_PCH_JTAG

XDP_PRESENT#

5%

910

1

XDP

XDP

R2504

PM_PCH_SYS_PWROK

1

4

1

R2512

51

1/16W

XDP

201

OUT

2

XDP

1

R2511

51 5%

2

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_CPU:CFG

402 1/16W

1

MF-LF 5%

XDP_CPU:CFG 1/16W

2

0

MF-LF 5%

2

0

MF-LF 5%

XDP

1

R2510

1K 1/16W MF-LF 402

=PPVCCIO_S0_XDP

PLACEMENT NOTE:

J2500

DF40RC-60DP-0.4V

NOSTUFF1

1

2

1

C2500

1/16W

10%

402

16V

PLACEMENT NOTE:

C2501

PLACE TDO TERM NEAR PCH XDP CONN

0.1UF

0.1UF MF-LF

XDP

10%

2

X5R

998-2516

402

2

XDP

1

R2550

16V X5R

1

R2551

51

402

51

5%

XDP

5%

1/20W MF

MF

402

201

201

2

PLACE_NEAR=U1800.M15:2.54MM

1/20W

MF-LF

Even pins should be facing edge of the board

1

R2552 51

5%

1/16W

2

2

PLACE_NEAR=J2550.52:2.54MM. PLACE_NEAR=U1800.U12:2.54MM

XDP_PCH_TDO XDP_PCH_TDI XDP_PCH_TMS XDP_PCH_TCK

PCH MICRO2-XDP CONNECTOR

NOTE: This is not the standard XDP pinout Use with 920-0782 Adapter Flex to support chipset debug

PLACE_NEAR=U1800.M17:2.54MM

XDP

1

R2556

XDP_CONN

=PP3V3_S5_XDP

51

CRITICAL

5% 1/20W MF

J2550

201

2

DF40RC-60DP-0.4V M-ST-SM 62 61

XDP

B

PLACE_NEAR=U1800.H4:2.54MM

IN

PCH_GPIO59_OC0_L

R2582 5% 1 MF

0

2

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

1/20W 201

2

1

OBSFN_A0

4

3

OBSFN_A1

6

5

8

7

OBSDATA_A0

10

9

OBSDATA_C0

OBSDATA_A1

12

11

OBSDATA_C1

XDP PLACE_NEAR=U1800.A17:2.54MM

IN

USB_HUB_SOFT_RESET_L

IN

SDCONN_STATE_RST_L

R2580 5% 1 MF

0

2

1/20W 20 1

2

1/20W 201

XDP_PCH_GPIO59_OC0_L XDP_PCH_USB_HUB_SOFT_RST_L

XDP PLACE_NEAR=U1800.A13:2.54MM

XDP_PCH_SDCONN_STATE_RST_L XDP_PCH_ENET_PWR_EN

R2586 5% 1 MF

0

TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>

XDP PLACE_NEAR=U1800.D16:2.54MM

IN

ENET_PWR_EN

R2587 5% 1 MF

0

2

1/20W 20 1

IN

XDP PLACE_NEAR=U1800.B16:2.54MM

IN

SDCONN_STATE_CHANGE

R2581 5% 1 MF

0

2

1/20W 201

XDP PLACE_NEAR=J2550.39:2.54MM

IN

ALL_SYS_PWRGD

IN IN

PCH_GPIO43_OC4_L XDP_PCH_SDCONN_DET_L PCH_GPIO10_OC6_L PCH_GPIO14_OC7_L

1K

2

XDP_PCH_S5_PWRGD XDP_PCH_PWRBTN_L

1/16W 402

XDP PLACE_NEAR=U4900.D10:2.54MM

OUT

PM_PWRBTN_L

R2585 5% 1 MF

0

2

IN

=SMBUS_XDP_SDA =SMBUS_XDP_SCL

OUT

XDP_PCH_TCK

BI

A

14

13

16

15

OBSDATA_C2

18

17

OBSDATA_C3

20

19

22

21

24

23

OBSFN_B0 OBSFN_B1

OBSFN_D0 OBSFN_D1

26

25

OBSDATA_B0

28

27

OBSDATA_D0

OBSDATA_B1

30

29

OBSDATA_D1

32

31

34

33

36

35

38

37

PWRGD/HOOK0

40

39

HOOK1

42

41

ITPCLK#/HOOK5

VCC_OBS_AB

44

43

VCC_OBS_CD

HOOK2

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59


HOOK3

SDA SCL TCK1

NC

TCK0

OBSDATA_D3

ITPCLK/HOOK4

RESET#/HOOK6 DBR#/HOOK7

TRSTn TDI TMS

0

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST* TERM NEAR PCH

PLACE_NEAR=U1800.G1:2.54MM

2

1/20W 201

IS OL AT E_ CPU _M EM _L

IN

IN IN

TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1> PCH_GPIO36_SATA2GP JTAG_ISP_TCK

IN XDP

IN

XDP_PCH_AUD_IPHS_SWITCH_EN ENET_LOW_PWR IN

5% 1 MF

0

PLACE_NEAR=U1800.AA3:2.54MM

2 1/20W 201


IN

TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5 XDPPCH_PLTRST_L XDP_DBRESET_L XDP_PCH_TDO TP_XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

IN

1K series R on PCH Support P. 28

OUT

IN

OUT OUT

S YN C_ MA ST ER =K 21 _M LB

S YN C_ DA TE =1 2/ 13 /2 01 0

PAGE TITLE

CPU & PCH XDP

XDP_PRESENT#

1

64

63

1

DRAWING NUMBER

Apple Inc.

C2581 0.1UF

10% X5R


5% 1 MF

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

TDO

0.1UF

402

XDP

IN

XDP

C2580 16V

B

IN

X DP _P CH _I SOL AT E_ CP U_ ME M_L PCH_GPIO35 IN

R2579 OBSDATA_D2

XDP

Even pins should be facing edge of the board

PCH_GPIO15 SMC_IG_THROTTLE_L

R2578

OBSDATA_A3

TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3

1/20W 201

OBSFN_C1

OBSDATA_A2

R2584 5% 1 MF-LF

OBSFN_C0

10%

2

998-2516

2

051-8870

SIZE

D

REVISION

3.13.0

R

16V X5R 402


BRANCH


PAGE

25 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1 TABLE_BOMGROUP_HEAD

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_ITEM

24 8 7

BYPASS=U2600.5::5mm BYPASS=U2600.34::2mm BYPASS=U2600.23::2mm

=PP3V3_S3_USB_HUB

C2602 1

C2603 1

C2611 1

C2612 1

4.7UF

0.1UF

0.1UF

0.1UF

20% 6.3V X5R-CERM1 402

10% 16V X5R-CERM 0201

10% 16V X5R-CERM 0201

10% 16V X5R-CERM 0201

2

2

2

HUB1_ALLREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_1NONREM


HUB1_2NONREM


HUB1_3NONREM


TABLE_BOMGROUP_ITEM

BYPASS=U2600.15::2mm

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

2 TABLE_BOMGROUP_ITEM

HUB2_ALLREM


HUB2_1NONREM


HUB2_2NONREM


HUB2_3NONREM


TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BYPASS=U2600.23::5mm BYPASS=U2600.29::2mm

D

TABLE_BOMGROUP_ITEM


C2607 1

C2608 1

C2609 1

C2610 1

4.7UF

0.1UF

0.1UF

0.1UF

20% 6.3V X5R-CERM1 402

2

10% 16V X5R-CERM 0201

10% 16V X5R-CERM 0201

2

2

10% 16V X5R-CERM 0201

PPUSB_HUB1_CRFILT VOLTAGE=1.8V

2

CRITICAL

OMIT_TABLE

2

CRITICAL

SYM VER 1

1

R2630

18PF 5%

HUB1_NONREM1_1 1

HUB1_NONREM0_1 1

R2601

10K

R2603

R2605

5%

2

2

25V NP0-C0G 201

100

1

2

HUB1_NONREM1_0 1

1/20W

5%

MF

1/20W

24

MF

201

USB_HUB1_TEST

11

USB_HUB_RESET_L

26

RESET*

USB_HUB1_XTAL1

33

XTALIN/CLKIN

USB_HUB1_XTAL2

201

CRITICAL

10K

TEST

32

XTALOUT

USB_HUB1_NONREM0

28

SUSP_IND/LOCAL_PWR/NON_REM0

USB_HUB1_NONREM1

22

USB_HUB1_CFG_SEL0

24

SCL/SMBCLK/CFG_SEL0

USB_HUB1_CFG_SEL1

25

HS_IND/CFG_SEL1

201

HUB1_NONREM0_0 1

R2602

R2604 1

MF 2

2

201

R2606

1

10K

2

0

0

All ports are removable

0

1

Port 1 is non removable

1

0

Port 1 and 2 are non removable

1

1

Port 1, 2, and 3 are non removable

20% 6.3V X5R 0201

BOM TABLE

USBDP_DN1/PRT_DIS_P1

USB_T29A_N

8 69

2

BI

USB_T29A_P

BI

8 69

USBDM_DN2/PRT_DIS_M2

3

USB_SDCARD_N

BI

33 69


4

USB_SDCARD_P

BI

33 69


6

USB_EXTD_N

BI

6 40 69


7

USB_EXTD_P

BI

6 40 69

SDA/SMBDATA/NON_REM1

NC 8 NC 9

5%

1/20W

1/20W

MF

MF

201

2

12

TP_USB_HUB1_PRTPWR1

PRTPWR2/BC_EN2*

16

NC_USB_HUB1_PRTPWR2

PRTPWR3/BC_EN3*

18

NC_USB_HUB1_PRTPWR3

NC 20

NC_USB_HUB1_PRTPWR4

201

BYPASS=U2650.34::2mm BYPASS=U2650.15::2mm 1

C2653 1

C2661 1

4.7UF

0.1UF

0.1UF

0.1UF

20% 6.3V X5R-CERM1 402

10% 16V X5R-CERM 0201

10% 16V X5R-CERM 0201

10% 16V X5R-CERM 0201

2

DESCRIPTION

REFERENCE DESIGNATOR(S) C R IT I CA L

2

SMSC USB2514

U2600,U2650

338S0824

2

SMSC USB2514B

U2600,U2650

CRITICAL

B O M O P TI O N USBHUB_2514

IPU

OCS1*

13

IPU

OCS2*

17

IPU

OSC3*

19

USB_EXTD_OC_L

NC 21

=USB_HUB1_OCS4

RBIAS

35

VBUS_DET

27

CRITICAL

USBHUB_2514B TABLE_5_ITEM

T29

338S0923

2

CRITICAL

U2600,U2650

SMSC USX2513B

USBHUB_2513B

SDCARD(NA to K78)

LIO External D

=PP3V3_S3_USB_HUB

TP_USB_HUB1_OCS1

1

NC_USB_HUB1_OCS2

C

7 8 24

R2620 10K

IN

6 40

IN

8

5% 1/20W

MF 201

2

7

=PP3V3_S3_USB_RESET

7

=PP3V3_S5_USB_RESET

USB_HUB1_RBIAS

R2640

USB_HUB1_VBUS_DET

1

CRITICAL

USBDM_UP

30

USB_HUB1_UP_N

18 69

USBDP_UP

31

BI

USB_HUB1_UP_P

BI

18 69

1

20K

2

5% 1/20W

R2600

MF

12K

1

R2641

201

1%

THRM_PAD

C2662

QTY

338S0720

NC NC

PRTPWR1/BC_EN1*

10K

C2652 1

2

20% 6.3V X5R 0201

TABLE_5_ITEM

1


2

1UF 2

2

TABLE_5_ITEM


IPU

=PP3V3_S3_USB_HUB

10% 16V X5R-CERM 0201

C2618 1UF

10% 16V X5R-CERM 0201

2

C2616

D

DESCRIPTION

TABLE_5_HEAD

R2607

5%

2

24 8 7

1

PART#

5% 1/20W

MF

C2615 0.1UF

T L I F L L P

10K

5% 1/20W

1

QFN

2

MF 2

VOLTAGE=1.8V

USB2513B

1/20W

MF

201

1M

1

C2620 18PF

5%

5%

1/20W

C

2

10K

5%

201

25V NP0-C0G 201

1

0.1UF


4 3

NON_REM0

U2600

2X1.6X0.65-SM

C2619 1

4 1 T L I F R C

VDD33

Y2600 24.000M-150PPM-6PF 1

C2617

1

PPUSB_HUB1_PLLFILT 0 5 3 9 6 5 1 5 1 1 2 2 3

CRITICAL

NON_REM1


10K

1/20W

MF 2

7 3

1 1

100K 5%

1/20W

MF

2 201

5%

MF 201

C2641 100PF

1/20W

2

5%

NOSTUFF

R2642

201

2

2

25V CERM 201

USB_HUB_RESET

USB_HUB_RESET_L

6 3 D

BYPASS=U2650.23::5mm BYPASS=U2650.10::2mm P3V3S3_EN_RC


C2657 1

C2658 1

C2659 1

C2660 1

4.7UF

0.1UF

0.1UF

0.1UF

20% 6.3V X5R-CERM1 402

B

2

10% 16V X5R-CERM 0201

10% 16V X5R-CERM 0201

2

2

10% 16V X5R-CERM 0201

Y2650

24.000M-150PPM-6PF 1

OMIT_TABLE

2

CRITICAL

SYM VER 1

1

R2680

5%

HUB2_NONREM1_1 1

HUB2_NONREM0_1 1

R2651

10K

5%

1

1M

18PF

R2655

5% 2

2

5%

25V NP0-C0G 201

2

1

100

1

1/20W

5%

MF

1/20W

2

MF

201

10K

24

USB_HUB2_TEST

11

USB_HUB_RESET_L

26

RESET*

USB_HUB2_XTAL1

33

XTALIN/CLKIN

USB_HUB2_XTAL2

201

TEST

32

XTALOUT

USB_HUB2_NONREM0

28

SUSP_IND/LOCAL_PWR/NON_REM0

USB_HUB2_NONREM1

22

SDA/SMBDATA/NON_REM1

USB_HUB2_CFG_SEL0

24

SCL/SMBCLK/CFG_SEL0

USB_HUB2_CFG_SEL1

25

HS_IND/CFG_SEL1

201

R2654

MF

1

MF 2

2

201

R2656

1

10K

A

1

2

C2665

1

1UF

10% 16V X5R-CERM 0201

20% 6.3V X5R 0201

2

C2668 2

1UF

10% 16V X5R-CERM 0201

2

C2666

0.1UF

2

20% 6.3V X5R 0201

2

5

G

2N7002DW-X-G

S

SOT-363

4

10% 6.3V CERM-X5R 402

B D2600

IN

USB_HUB_SOFT_RESET_L

1

0

2

SOD-523

USB_HUB_SOFT_RESET_L_R

2

1

5% 1/20W

BAT54XV2T1

MF 201

1

USB_BT_N

BI

6 37 69

2

USB_BT_P

BI

6 37 69


3

USB_TPAD_HUB_N

BI

49


4

USB_TPAD_HUB_P

BI

49


6

USB_EXTA_N

BI

39 69


7

USB_EXTA_P

BI

39 69

NC 8 NC 9

R2657 5%

12

TP_USB_HUB2_PRTPWR1

PRTPWR2/BC_EN2*

16

NC_USB_HUB2_PRTPWR2

PRTPWR3/BC_EN3*

18

NC_USB_HUB2_PRTPWR3

NC 20

1/20W

1/20W

MF

MF

NC_USB_HUB2_PRTPWR4

2

201

IPU

OCS1*

13

IPU

OCS2*

17

IPU

OSC3*

19

IPU

NC 21

BlueTooth

Trackpad/Keyboard

Right USB A

NC NC

PRTPWR1/BC_EN1*

10K

5%

201

SOT-363

R2690 23 18


5% 1/20W

VOLTAGE=1.8V

T L I F L L P


10K

5% 1/20W

Q2640

2N7002DW-X-G

S

QFN

CRITICAL

HUB2_NONREM0_0 1

R2652

0.1UF


4 3

1

USB2513B

MF 2

HUB2_NONREM1_0

201

2

C2670

1/20W

MF 201

R2653 10K

5% 1/20W

25V NP0-C0G 201

C2667

U2650

2X1.6X0.65-SM

18PF

4 1 T L I F R C

VDD33

G

C2640 0.47UF

1

PPUSB_HUB2_PLLFILT 0 5 3 9 6 5 1 1 2 2 3

C2669 1

1

VOLTAGE=1.8V 2

2

1

PPUSB_HUB2_CRFILT MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

CRITICAL

CRITICAL

D

Q2640

TP_USB_HUB2_OCS1 NC_USB_HUB2_OCS2

=PP3V3_S3_USB_HUB

1

7 8 24

R2670 10K

USB_EXTA_OC_L

IN

39

=USB_HUB2_OCS4

IN

8

35

VBUS_DET

27

USB_HUB2_VBUS_DET

USBDM_UP

30

USB_HUB2_UP_N

18 69

31

BI

USBDP_UP

USB_HUB2_UP_P

BI

18 69

1/20W

S Y NC _ MA S TE R =K 2 1_ M LB

MF

PAGE TITLE

5%

2

RBIAS

D RA WI NG N UM BE R

Apple Inc.

CRITICAL 1

R2650

051-8870 REVISION

3.13.0

R

12K 1%

THRM_PAD

1/20W

MF 2

7 3

S Y NC _ DA T E= 1 2/ 1 3/ 2 01 0

USB HUBS

201

USB_HUB2_RBIAS

201


BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

26 OF 109

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PARTSHEET

24 OF 75

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

S IZ E

D

A

8

7

www.laptopblue.vn

6

5

4

3

System RTC Power Source & 32kHz / 25MHz Clock Generator

2

1

Platform Reset Connections Unbuffered R2781

=PPVBAT_G3_SYSCLK

7

VBAT (300ohm & 10uF RC)

IN

PLT_RESET_L

1

2

MAKE_BASE=TRUE

MF 201 1

3.42V G3Hot

R2782

3.3V S5

0

1

No bypass necessary

SB XTAL Power

7

=PPVDDIO_S0_SBCLK

5

T29 XTAL Power

7

=PPVDDIO_T29_CLK

M 5 2 _ D D V

C2722 1

0.1UF

1

10%

C2702

2

X5R-CERM

2

0201

10V

internally ORed to

VDDIO_25M_B VDDIO_25M_C

1

0

SYSCLK_CLK25M_X2

1

SYSCLK_CLK25M_X2_R

2

NO STUFF

5% 5%

NC NC

201

1

MF

CRITICAL

201

3

X2

4

X1

Y2705

2

3

1M

25.000MHZ-12PF-20PPM

12

SYSCLK_CLK32K_RTC

OUT

16 70

25MHZ_A

9

SYSCLK_CLK25M_SB

OUT

16 70

MF 2

OUT

34 70

25MHZ_B

8

25MHZ_C

15

7

201

SYSCLK_CLK25M_T29

OUT

31

XDPPCH_PLTRST_L

OUT

23

=T29_RESET_L

OUT

36

BKLT_PLT_RST_L

OUT

66

CPU_RESET_L

OUT

10 23

Series R is R3803

R2793 1

1

7 1

C2710

7

=PP3V3_S0_RSTBUF

10%

SYSCLK_CLK25M_X1

0

2

5% 1/20W MF 201

Buffered

1UF 10V X5R

5

402-1

U2780 74LVC1G07

NOTE: 30 PPM crystal required

5%

PCA9557D_RESET_L

7

For SB RTC Power

PAD

0 6 1 1

2

NC

1

SC70

25V

C

37

MF 201

2

2

OUT

5% 1/20W

THRM

GND

1/20W

SM-3.2X2.5MM

12PF

AP_RESET_L

XDP

1K

=PPVRTC_G3_OUT

5%

4

C2706

33

R2789 1

32KHZ_A

VDD_RTC_OUT

R2706

2 5% 1/20W MF

to reduce VBAT draw.

1/20W 1

25V

1

available ~3.3V power

201

R2705

12PF

NP0-C0G

1

VDDIO_25M_A

6 14

2

0

+V3.3A should be first

TQFN 11

R2771

create VDD_RTC_OUT.

CRITICAL

2

OUT

5% 1/20W MF 201

VBAT and +V3.3A are

SLG3NB148V

X5R 402-1

Ground VDDIO of unused CLK outputs for power savings

C2705

41

0

V 2 4 . 3 +

U2700

10%

16V

2

0201

A 3 . 3 V +

1UF

0.1UF

10%

16V X5R-CERM

OUT

SDCARD_PLT_RST_L

R2788 1

C2724 1

SMC_LRESET_L

D

2

5% 1/20W MF 201

3 1

2

2 5% 1/20W MF 201

Coin-Cell & No G3Hot: 3.3V S5

=PP3V3_S0_SYSCLKGEN

7

6 43

33

No Coin-Cell: GreenClk 25MHz Power Powered in S0

70

OUT

R2783

=PP3V3_S5_SYSCLK Coin-Cell & G3Hot:

D

OUT

MAKE_BASE=TRUE 5% 1/20W

No Coin-Cell: 3.42V G3Hot (no RC) 7

LPC_RESET_L LPCPLUS_RESET_L

33 26 18

Coin-Cell:

2

NP0-C0G

4

C

PLT_RST_BUF_L

201

MAKE_BASE=TRUE

NC 1

1

C2780 1

3

100K

NC

0.1UF 10% 16V X5R-CERM 0201

R2780

2

2

5% 1/20W MF 201

VTT voltage divider on CPU page

NO STUFF

PCH S0 PWRGD

R2763 0 1

25 7

=PP3V3_S5_PCHPWRGD

25 7

=PP3V3_S0_SB_PM

R2750

=PP3V3_S5_PCHPWRGD

1

1

0.1UF 10% 16V X5R-CERM 0201

5%

2

MF 201

1

ALL_SYS_PWRGD

PCH Reset Button

10% 16V X5R-CERM 0201

25 7

=PP3V3_S0_SB_PM

MC74VHC1G08

1

SC70-HF 4

5

PM_S0_PGOOD

1

MC74VHC1G08

4

U2760

10K

3.0K SYS_PWROK_R

1

2

3

PM_PCH_SYS_PWROK

2

5% 1/20W MF 201

3

B

R2795

R2762

SC70-HF

2

CPUIMVP_PGOOD

IN

C2760 0.1UF

2

5

IN

1

2

U2750 57

7 25

C2750

1K 1/20W

62 52 41 23

2

5% 1/20W MF 201

OUT

17 23

XDP

R2796

PLACE_NEAR=U1800.M10:5.54mm

NO STUFF 1

67 23 10

R2761

IN

0

1

XDP_DBRESET_L

0

41 36

1

B

17 41

NO STUFF

R2797

2

PM_PCH_PWROK

OUT

17 19

OUT

17

0

5% 1/16W MF-LF 2 402

MAKE_BASE=TRUE

5% 1/20W MF 201

BI

5%

201

1

0

SMC_DELAYED_PWRGD

PM_SYSRST_L

402 MF-LF

MF 2

5% 1/16W MF-LF 402

2

1/16W

5% 1/20W

R2760

2

PM_PCH_APWROK

SILK_PART=SYS RESET

CLOCK (CK505) UNUSED clock terminations for FCIM MODE

69 16

PCIE_CLK100M_PCH_N

69 16

PCIE_CLK100M_PCH_P

69 16

A

PCH_CLK14P3M_REFCLK

69 16

PCH_CLK100M_SATA_N

69 16

PCH_CLK100M_SATA_P

69 16

PCH_CLK96M_DOT_N

69 16

PCH_CLK96M_DOT_P

R2727 22

PLACE_NEAR=U1800.G51:5.1mm 70 18

1

R2757 10K 5% 1/20W MF

2

201

1

R2751 10K 5% 1/20W MF

2 201

1

R2752 10K 5% 1/20W MF

2 201

1

R2753 10K 5% 1/20W MF

2 201

1

R2754 10K 5% 1/20W MF

2 201

1

R2755 10K 5% 1/20W MF

2 201

IN

LPC_CLK33M_SMC_R

R2756 10K 5%

1

SYNC_MASTER=K78_MLB

PLACE_NEAR=U1800.E49:5.1mm

18

IN

LPC_CLK33M_SMC

2 5% 1/20W MF 201

1

LPC_CLK33M_LPCPLUS_R

OUT

41 70


PAGE TITLE

Clock (CK505) and Chipset Support R2726 1

22

DRAWING NUMBER 2

LPC_CLK33M_LPCPLUS

OUT

Apple Inc.

6 43 70

1/20W

5% 1/20W MF 201

MF

2 201

22

18

IN

PCH_CLK33M_PCIOUT

051-8870

1

2 5% 1/20W MF 201

PCH_CLK33M_PCIIN

OUT

16 69

SIZE

D

REVISION

3.13.0

R

R2729

PLACE_NEAR=U1800.G45:2.54MM:5.1mm


BRANCH


PAGE

27 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals. WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. WHEN LOW:

D

CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN

= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

MEMVTT_EN

= (ISOLATE_CPU_MEM_L + PLT_RST_L)

D

* PM_SLP_S3_L

1V5 S0 "PGOOD" for CPU

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

62 49 41 17

PM_SLP_S4_L

IN

7


CPUMEM_S0 1

R2805

PM_MEM_PWRGD pull-up to CPU VTT rail is on

CPU page

10K

5% 1/20W MF 2 201

P1V5CPU_EN 7

=PP3V3_S3_MEMRESET

CPUMEM_S0

Q2805

CPUMEM_S0

15 12 10 7

5% 1/20W MF 201 2

5% 1/20W MF 2 201

R28201

Q2800

D 3

3 D

Q2805

3

R2890 23 19

I SO LA TE _C PU _M EM _L

IN

2

0

5 G

S 4

4 S

5% 1/20W MF 201

C2820

33.2K

Q2820

S

DMB53D0UV

1

IN

1

1000PF

1% 1/20W MF 2012

G 5

PM_SLP_S3_L CPUMEM_S0

CRITICAL

4

NO STUFF

R28211

SOT563

1 SO LA TE _C PU _M EM _L _R I

Q2820 SOT-563

2 G

SOT-563

CPUMEM_S0

C

5

CPUMEM_S0

SSM6N37FEAPE

SOT563

D

PM_MEM_PWRGD_L

P1V5_S0_DIV

SSM6N37FEAPE

6

DMB53D0UV

1% 1/20W MF 2012

P1V5CPU_EN_L CPUMEM_S0

CRITICAL

27.4K

S 1

10 17 67

10K

61

D 6

2 G

OUT

R2822

OUT

SOT563

100K

PM_MEM_PWRGD 1

SSM6N37FEAPE

R28011


10% 16V X7R 2 201

C

17 41 62

1

R2810 10K

5% 1/20W MF 2 201 26 7

MEMVTT_EN

=PP5V_S3_MEMRESET CPUMEM_S0 CPUMEM_S0

Q2810

CPUMEM_S0

1

R2815

R2802

100K

8

MEMVTT Clamp

SOT563

100K

5% 1/20W MF 2012

OUT

D 6

SSM6N37FEAPE

1

5% 1/20W MF 201 2

Ensures CKE signals are held low in S3 2 G

S 1

3 D

Q2810

MEMVTT_EN_L 7

CPUMEM_S0

CPUMEM_S0

CPUMEM_S0

Q2800

Q2815

D 6

SSM6N37FEAPE

=PPVTT_S0_VTTCLAMP CPUMEM_S0

R28501

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

10

SOT563

G

2 G D

S

6

1

S 1

4 S

G 5 IN

18 25 26 7

B

=PP5V_S3_MEMRESET CPUMEM_S0

R28511 100K

1

C2817 16V X7R

=PP1V5_S3_MEMRESET

CPUMEM_S0

10%

Q2815

2

402

5

1

SOT563

G

R2816

10

IN

=MEM_RESET_L

S

CPU_MEM_RESET_L

MAKE_BASE=TRUE

20K

5% 1/20W MF 2 201

D

MEM_RESET_L

3

4

NOSTUFF 0.1UF

CPUMEM_S0

10% 16V

Q2850

2

0201

0

1

D 3

SSM6N37FEAPE OUT

B

D 6

SOT563

2 G

S 1

5 G 56 8

IN

NO STUFF

C2851 1 1000PF

SOT563

27 28 29 30

CPUMEM_S3

R2817

Q2850

VTTCLAMP_EN

C2816 1

X5R-CERM

CPUMEM_S0 SSM6N37FEAPE

5% 1/20W MF 201 2

7

CPUMEM_S0

SSM6N37FEAPE MEMRESET_ISOL_LS5V_L

60mW max power

VTTCLAMP_L PLT_RESET_L

0.047UF

75mA max load @ 0.75V

5% 1/10W MF-LF 603 2

2

SOT563

10% 16V X7R 2 201

S 4

=DDRVTT_EN

2

5% 1/20W MF 201

Step

ISOLATE_C PU_MEM_L

PLT_RES ET_L

0

1

1

1

1

1

CPU_MEM_RESET_L

1

0

1

1

1

1

1

1

1

2

0

0

1

1

1

1

0

1

3

0

0

0

1

X

1

0

0

4

0

0

1

1

X

1

0

to

5

0

1

1

1

0 (*)

1

1

6

0

1

1

1

1

1

S0

7

1

1

1

1

1

CPU_MEM_RESET_L

S0 to S3

A

PM_SLP_S3_L PM_SLP_S4_L

CPU _MEM_RESET_L

MEM_RESET_L

MEMVTT_EN 1

P1V5C PU_EN 1

1 1 SYNC_MASTER=K21_MLB

1 1

1


PAGE TITLE

1

CPU Memory S3 Support DRAWING NUMBER

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to

clear before deasserting ISOLATE_CPU_MEM_L GPIO.

Apple Inc. transition. must

Rails

will power-up

deassert ISOLATE_CPU_MEM_L

as if

from S3,

and then

but MEM_RESET_L

generate a

valid reset

will not

properly assert.

cycle on

CPU_MEM_RESET_L.

051-8870

Software

SIZE

D

REVISION

3.13.0

R

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0


BRANCH


PAGE

28 OF 109

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7

www.laptopblue.vn

6

5

4

3

2

1

D

D

PP0V75_S3_MEM_VREFCA_A

68 31 30 29 28 27

68 31 30 29 28 27

PP0V75_S3_MEM_VREFCA_A 68 31 30 29 28 27

29 28 27 9 PP0V75_S3_MEM_VREFDQ_A 68 31 30

C2900 1 C2901 1 20%

0.47UF CERM-X5R-1 201 4V

20%

2

0.47UF CERM-X5R-1 201 4V

2

2 E Q D F E R V

32 28 27 7

=PP1V5_S3_MEM_A 68 31 30 29 28 27 9

9 J

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

0 0 1 2 3 1 B C E E

1

C2902

C2910

0.47UF

A C F E R V

VDD


20% 4V

VDDQ

1

C2911

20%

2 CERM-X5R-1

1

20%

0.47UF 2 0.47UF 2 CERM-X5R-1 CERM-X5R-1

201

U2900

201 4V

201 4V

2 E Q D F E R V

32 28 27 7

9 J A C F E R V

DDR3-1333 68 32 28

27 11

30 29 28

27 26

MF 1%

C

MEM_A_ODT<0>

G2

MEM_RESET_L

N3

240

R29001

2

MEM_A_ZQ0

1/20W 201

H9

ZQ

MEM_A_A<0>

K4

68 32 28 27 11

MEM_A_A<1>

L8

68 32 28 27 11

MEM_A_A<2>

L4

68 32 28 27 11

MEM_A_A<3>

K3

A3

68 32 28 27 11

MEM_A_A<4>

L9

A4

68 32 28 27 11

MEM_A_A<5>

L3

A5

68 32 28 27 11

MEM_A_A<6>

M9

DQ0

B4 MEM_A_DQ<7>

11 68

DQ1

C8 MEM_A_DQ<4>

11 68

DQ2

C3 MEM_A_DQ<2>

11 68

DQ3

C9 MEM_A_DQ<3>

11 68

NF/DQ4

E4 MEM_A_DQ<5>

11 68

NF/DQ5

E9 MEM_A_DQ<1>

11 68

A6

NF/DQ6

D3 MEM_A_DQ<6>

11 68

NF/DQ7

E8 MEM_A_DQ<0>

11 68

C4 MEM_A_DQS_P<0>

11 68

A1 A2

MEM_A_A<7>

M3

A7

68 32 28 27 11

MEM_A_A<8>

N9

A8

68 32 28 27 11

MEM_A_A<9>

M4

MEM_A_A<10>

H8

MEM_A_A<11>

M8

68 32 28 27 11

MEM_A_A<12>

K8

68 32 28 27 11

MEM_A_A<13>

N4

68 32 28 27 11 68 32 28 27 11

MEM_A_A<14>

N8

A12/BC* A13 A14

11

MEM_A_BA<0>

J3

11

MEM_A_BA<1>

K9

11

MEM_A_BA<2>

J4

68 32 28 27

11

MEM_A_CLK_P<0>F8

CK

11

MEM_A_CLK_N<0>G8

CK*

G10 MEM_A_CKE<0>

CKE

MEM_A_CS_L<0> H3

CS*

27 11

11

11

MEM_A_RAS_L

F4

68 32 28 27 11

MEM_A_CAS_L

G4

68 32 28 27

MEM_A_WE_L

H4

68 32 28 27

11

DQS*

A11

68 32 28 27

68 32 28

DQS

A10/AP

68 32 28 27

68 32 28 27

MEM_A_ODT<0>

G2

ODT

30 29 28 27 26

MEM_RESET_L

N3

RESET*

240

MF 1%

D4 MEM_A_DQS_N<0>

DM/TDQS

B8

NF/TDQS*

A8 A1

BA0

A4

BA1 BA2

NC

RAS*

NC

MEM_A_A<0>

MEM_A_A<1>

L8

68 32 28 27 11

MEM_A_A<2>

L4

68 32 28 27 11

MEM_A_A<3>

K3

MEM_A_A<4>

L9

68 32 28 27 11

MEM_A_A<5>

L3

68 32 28 27 11

WE*

B VSS

VSSQ

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

1

C2912

VDDQ

2

U2910


20% 4V CERM-X5R-1 201

20%

20%

0.47UF

0.47UF

201 4V

CERM-X5R-1 201 4V

2 CERM-X5R-1

2

2 E Q D F E R V

32 28 27 7

9 J

MEM_A_A<6>

M9

3 2 9 0 0 B D B 1 1 C D

A3 A4

E4 MEM_A_DQ<10>

A1 A2

A6

NF/DQ5 E9 MEM_A_DQ<13> NF/DQ6 D3 MEM_A_DQ<11>

A7

NF/DQ7

MEM_A_A<7>

M3

MEM_A_A<8>

N9 M4

68 32 28 27 11

MEM_A_A<10>

H8

68 32 28 27 11

MEM_A_A<11>

M8

A11

68 32 28 27 11

MEM_A_A<12>

K8

A12/BC*

68 32 28 27 11

MEM_A_A<13>

N4

MEM_A_A<14>

N8

A14 BA0

27 11

MEM_A_BA<0>

J3

68 32 28

27 11

MEM_A_BA<1>

K9

MEM_A_BA<2>

J4

68 32 28

27 11

A9

11

MEM_A_CLK_N<0>G8

CK*

11

MEM_A_CKE<0> G10

CKE

CK

11

MEM_A_RAS_L

F4

RAS*

MEM_A_CAS_L

G4

CAS*

68 32 28 27

MEM_A_WE_L

H4

11

N3

2

H9

240

A C F E R V

NF/TDQS*

A8

A4

NC

WE*

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

1

C2922

2 E

C2930 1 C2931 1

0.47UF VDD

20% 4V

VDDQ

20%

2 CERM-X5R-1

0.47UF

201 4V

CERM-X5R-1 201 4V

2 CERM-X5R-1

U2920

Q D F E R V

20%

0.47UF

201

MF 1%

1/20W

2

32 28 27 7

9 J

VSSQ 3 2 9 0 0 B D B 1 1 C D

NC

ZQ

MEM_A_A<0>

K4

MEM_A_A<1>

L8

MEM_A_A<2>

L4

MEM_A_A<3>

K3

A3

68 32 28 27 11

MEM_A_A<4>

L9

A4

68 32 28 27 11

MEM_A_A<5>

L3

68 32 28 27 11

MEM_A_A<6>

M9

A6

NF/DQ4 E4 MEM_A_DQ<22> E9 MEM_A_DQ<16> NF/DQ5 NF/DQ6 D3 MEM_A_DQ<18>

68 32 28 27 11

MEM_A_A<7>

M3

A7

NF/DQ7 E8 MEM_A_DQ<21>

68 32 28 27 11

MEM_A_A<8>

N9

MEM_A_A<9>

M4

MEM_A_A<10>

H8

68 32 28 27 11

MEM_A_A<11>

M8

68 32 28 27 11

MEM_A_A<12>

K8

68 32 28 27 11

MEM_A_A<13>

11 68

68 32 28 27 11

MEM_A_A<14>

N4 N8

DQ0

A1

DQ1 C8 MEM_A_DQ<17> C3 MEM_A_DQ<23> DQ2 DQ3 C9 MEM_A_DQ<20>

A2

A5

A10/AP

A12/BC* A14

MEM_A_BA<0>

J3

MEM_A_BA<1>

K9

68 32 28 27

11

MEM_A_BA<2>

J4

68 32 28 27

11

MEM_A_CLK_P<0>F8

CK

68 32 28 27

11

MEM_A_CLK_N<0>G8

CK*

68 32 28 27

11

MEM_A_CKE<0> G10

CKE

68 32 28 27 11

MEM_A_CS_L<0> H3

CS*

68 32 28 27

MEM_A_RAS_L

F4

MEM_A_CAS_L

G4

MEM_A_WE_L

H4

11

DM/TDQS

A13

11

11

DQS*

A11

11

68 32 28 27

DQS C4 MEM_A_DQS_P<2>

A9

NF/TDQS*

D4 MEM_A_DQS_N<2> B8 A8 A1

BA0

A4

BA1 BA2

NC

MEM_A_ODT<0>

G2

30 29 28 27 26

MEM_RESET_L

N3

2

H9

240

MEM_A_ZQ3

1

C2932 20% 4V

VDDQ

2 CERM-X5R-1 201

U2930

MF 1% 1/20W 201

ZQ

68 32 28 27 11

MEM_A_A<0>

K4

68 32 28 27 11

MEM_A_A<1>

L8

68 32 28 27 11

MEM_A_A<2>

L4

68 32 28 27 11

MEM_A_A<3>

K3

A3

11 68

68 32 28 27 11

MEM_A_A<4>

L9

A4

11 68

68 32 28 27 11

MEM_A_A<5>

L3

11 68

68 32 28 27 11

MEM_A_A<6>

M9

A6


11 68

68 32 28 27 11

MEM_A_A<7>

M3

A7


68 32 28 27 11

MEM_A_A<8>

N9

MEM_A_A<9>

M4

A9

MEM_A_A<10>

H8

A10/AP

68 32 28 27 11

MEM_A_A<11>

M8

68 32 28 27 11

MEM_A_A<12>

K8

68 32 28 27 11

MEM_A_A<13>

11 68

68 32 28 27 11 68 32 28 27 11

11 68

MEM_A_A<14>

N4 N8

NC

68 32 28 27 11

MEM_A_BA<0>

J3

NC

68 32 28 27

11

MEM_A_BA<1>

K9

68 32 28 27

11

MEM_A_BA<2>

J4

DQ0

A1


A2

A5

A12/BC* A14

CK* CKE

68 32 28 27 11

CS*

F4 G4

MEM_A_WE_L

H4

NF/TDQS*

11 68 11 68 11 68

B8 A8 A1 A4

BA2

MEM_A_CS_L<0> H3

MEM_A_CAS_L

11 68

11 68

BA1

CK

MEM_A_RAS_L

11 68

11 68

BA0

MEM_A_CKE<0> G10

27 11

11 68

D4 MEM_A_DQS_N<3>

DM/TDQS

A13

MEM_A_CLK_N<0>G8

28 27 11 68 32

C

11 68


DQS*

A11

MEM_A_CLK_P<0>F8

68 32 28

11 68

A8

27 11

27 11

68 32 28

B4 MEM_A_DQ<28>

A0

68 32 28 27 11

68 32 28

68 32 28 27 11

NC

RAS*

NC NC

NC A11 NC F2 NC F10 NC H2 NC H10 NC J8 NC N1 NC N11 NC

CAS*

B

WE*

VSSQ 3 2 9 0 0 B D B 1 1 C D

OMIT_TABLE

RESET*

11 68

NC

A11 NC F2 NC F10 NC H2 NC H10 NC J8 NC N1 NC N11 NC

FBGA

ODT

11 68

WE*

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

11 68

CAS*

RAS*

VSS

0 0 1 2 3 1 B C E E

0.47UF

VDD

11 68

A8

68 32 28 27

68 32 28 27 11

B4 MEM_A_DQ<19>

A0

68 32 28 27

68 32 28 27 11

R29301

68 32 28 27 11

NC


201

=PP1V5_S3_MEM_A

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

A C F E R V

DDR3-1333

OMIT_TABLE

RESET*

68 32 28 27 11

11 68

11 68

MEM_A_ZQ2

FBGA

ODT

68 32 28 27 11

11 68

11 68

A1

VSS


68 31 30 29 28 27 9

0 0 1 2 3 1 B C E E

68 32 28 27 11

11 68

11 68

B8

CS*

68 32 28 27 11

G2

MEM_RESET_L

11 68

C4 MEM_A_DQS_P<1>

DM/TDQS

BA2

11

MEM_A_ODT<0>

27 26

68 32 28 27 11

BA1

68 32 28 27

27 11

30 29 28

11 68

E8 MEM_A_DQ<9>

D4 MEM_A_DQS_N<1> DQS*

A13

68 32 28 27

MEM_A_CS_L<0> H3

DQS

A10/AP

68 32 28 27

27 11

11 68

A8

MEM_A_CLK_P<0>F8

68 32 28

NF/DQ4

A5

MEM_A_A<9>

68 32 28

R29201

A0

=PP1V5_S3_MEM_A

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

DDR3-1333

OMIT_TABLE

DQ0 B4 MEM_A_DQ<8> C8 MEM_A_DQ<14> DQ1 C3 MEM_A_DQ<15> DQ2 DQ3 C9 MEM_A_DQ<12>

68 32 28 27 11

68 32 28

FBGA


68 31 30 29 28 27


C2920 1 C2921 1

0.47UF VDD

ZQ

68 32 28 27 11

68 32 28 27

CAS*

1/20W 201

H9

68 32 28 27 11

NC


MEM_A_ZQ1

68 32 28 27 11

68 32 28 27 11

11 68

2

K4

68 32 28 27 11

A9

68 32 28 27

68 32 28 27

68 32 28 27 11

R2910 1

A0

68 31 30 29 28 27 9

0 0 1 2 3 1 B C E E

DDR3-1333

OMIT_TABLE

RESET*

68 32 28 27 11

68 32 28 27 11

FBGA

ODT

=PP1V5_S3_MEM_A

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

VSSQ

VSS 2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

3 2 9 0 0 B D B 1 1 C D

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK

A

CONTROL

SYNC_MASTER=K78_MLB


PAGE TITLE

DDR3 DRAM CHANNEL A (0-31) DRAWING NUMBER

Apple Inc.

051-8870 REVISION

R

3.13.0


BRANCH


PAGE

29 OF 109

SIZE

D

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D


68 31 30 29 28 27


68 31 30 29 28 27


68 31 30 29 28 27


30 29 28 27 9 68 31

32 28 27 7

=PP1V5_S3_MEM_A 68 31 30 29 28 27

C3000

1

20%

C3001

1

20%

0.47UF 2 0.47UF 2 CERM-X5R-1 CERM-X5R-1 201 4V

201 4V

2 E Q D F E R V

9 J

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

0 0 1 2 3 1 B C E E

C3002

C3010 1 C3011 1

0.47UF

A C F E R V

VDD


9

32 28 27 7

20%

VDDQ

4V 2 CERM-X5R-1

20%

20%


201

U3000

201 4V

201 4V

2 E Q D F E R V

9 J

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

A C F E R V

DDR3-1333 68 32 28 27 11

MEM_A_ODT<0>

G2

MEM_RESET_L

N3

2

H9

FBGA

ODT

30 29 28 27 26

OMIT_TABLE

MEM_A_ODT<0>

C

MEM_A_ZQ8

1/20W

68 32 28 27 11 68 32 28 27 11 68 32 28 27 11

201

MEM_A_A<0>

K4

MEM_A_A<1>

L8

MEM_A_A<2>

L4

MEM_A_A<3>

K3

68 32 28 27 11

MEM_A_A<4>

L9

68 32 28 27 11

MEM_A_A<5>

L3

68 32 28 27 11

MEM_A_A<6>

M9

68 32 28 27 11

MEM_A_A<7>

M3

68 32 28 27 11

MEM_A_A<8>

N9

68 32 28 27 11

MEM_A_A<9>

M4

68 32 28 27 11

MEM_A_A<10>

H8

68 32 28 27 11

MEM_A_A<11>

M8

68 32 28 27 11

MEM_A_A<12>

K8

68 32 28 27 11

MEM_A_A<13>

N4

MEM_A_A<14>

MEM_A_BA<0>

J3

68 32 28 27 11

MEM_A_BA<1>

K9

68 32 28 27 11

MEM_A_BA<2>

J4

68 32 28 27 11

68 32 28 27 11

MEM_A_CLK_P<0>F8

68 32 28 27 11

MEM_A_CLK_N<0>G8

68 32 28 27 11

B

N8

MEM_A_CKE<0>

G10

68 32 28 27 11

MEM_A_CS_L<0> H3

68 32 28 27 11

MEM_A_RAS_L

F4

68 32 28 27 11

MEM_A_CAS_L

G4

68 32 28 27 11

MEM_A_WE_L

H4

C3012

C3020 1 C3021 1

20% 4V

VDDQ

20%

2 CERM-X5R-1

0.47UF

201

U3010

CERM-X5R-1 201 4V

G2

FBGA

ODT

RESET*

MEM_RESET_L

N3

RESET*

H9

ZQ

K4

A0

30 29 28 27 26

ZQ

R30101

A0 A1 A2 A3

DQ0

B4 MEM_A_DQ<39>

DQ1

C8 MEM_A_DQ<33>

DQ2

C3 MEM_A_DQ<34>

DQ3

C9 MEM_A_DQ<35>

11 68

11 68

A5

NF/DQ5

E9 MEM_A_DQ<37>

11 68

A6

NF/DQ6

D3 MEM_A_DQ<38>

11 68

A7

NF/DQ7

E8 MEM_A_DQ<32>

11 68

A8 C4 MEM_A_DQS_P<4>

DQS*

D4 MEM_A_DQS_N<4>

68 32 28 27 11

MEM_A_A<1>

L8

68 32 28 27 11

MEM_A_A<2>

L4

A2

68 32 28 27 11

MEM_A_A<3>

K3

A3

68 32 28 27 11

MEM_A_A<4>

L9

68 32 28 27 11

MEM_A_A<5>

L3

A5

68 32 28 27 11

MEM_A_A<6>

M9

A6

68 32 28 27 11

MEM_A_A<7>

M3

MEM_A_A<8>

N9

MEM_A_A<9>

M4

MEM_A_A<10>

H8

68 32 28 27 11 11 68 68 32 28 27 11

A10/AP A11

A12/BC*

DM/TDQS

A13 A14

NF/TDQS*

B8 A8 A1

BA0

A4

BA1 BA2 CK NC

CK* CKE CS*

RAS* CAS* WE*

VSS

VSSQ

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

3 2 9 0 0 B D B 1 1 C D

11 68

68 32 28 27 11

NC

A10/AP A11

K8

A12/BC*

N4

A13

N8

A14

MEM_A_BA<0>

J3

68 32 28 27 11

MEM_A_BA<1>

K9

68 32 28 27 11

MEM_A_BA<2>

J4

68 32 28 27 11

MEM_A_CLK_P<0>F8

CK

68 32 28 27 11

MEM_A_CLK_N<0>G8

CK*

G10 MEM_A_CKE<0>

CKE

68 32 28 27 11

68 32 28 27 11

MEM_A_CS_L<0> H3

C4 MEM_A_DQS_P<5> DQS

A9

M8

68 32 28 27 11

11 68

DQS* DM/TDQS

B8

NF/TDQS*

A8 A1

BA0

A4

BA1 BA2

NC

CS*

68 32 28 27 11

MEM_A_RAS_L

F4

RAS*

68 32 28 27 11

MEM_A_CAS_L

G4

CAS*

68 32 28 27 11

MEM_A_WE_L

H4

D4 MEM_A_DQS_N<5>

WE*

VSS 2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

VSSQ 3 2 9 0 0 B D B 1 1 C D

240

MF 1%

2

0.47UF CERM-X5R-1 201 4V

2

G2

MEM_RESET_L

N3

2

2 E Q D F E R V

9 J

=PP1V5_S3_MEM_A

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

A C F E R V

0 0 1 2 3 1 B C E E


68 31 30 29 28 27 9

1

C3022

2 E

C3030 1 C3031 1

0.47UF

VDD

VDDQ

2

20% 4V CERM-X5R-1 201

20%

0.47UF CERM-X5R-1 201 4V

U3020

MEM_A_ZQ10

NC

H9

Q D F E R V

20%

2

0.47UF CERM-X5R-1 201 4V

2

32 28 27

9 J

68 32 28 27 11

MEM_A_A<1>

L8

68 32 28 27 11

MEM_A_A<2>

L4

68 32 28 27 11

MEM_A_A<3>

K3

A3

68 32 28 27 11

MEM_A_A<4>

L9

A4

68 32 28 27 11

MEM_A_A<5>

L3

68 32 28 27 11

MEM_A_A<6>

M9

68 32 28 27 11

MEM_A_A<7>

M3

68 32 28 27 11

MEM_A_A<8>

N9

68 32 28 27 11

MEM_A_A<9>

M4

A9

68 32 28 27 11

MEM_A_A<10>

H8

A10/AP

68 32 28 27 11

MEM_A_A<11>

M8

68 32 28 27 11

MEM_A_A<12>

K8

68 32 28 27 11

MEM_A_A<13>

N4

11 68 11 68 11 68 11 68 11 68

11 68

MEM_A_A<14>

N8

DQ0

A1


A2

A6


A7


A5

A12/BC* A13

K9

68 32 28 27 11

MEM_A_BA<2>

J4

68 32 28 27 11

MEM_A_CLK_P<0>F8

CK

68 32 28 27

MEM_A_CLK_N<0>G8

CK*

G10 MEM_A_CKE<0>

CKE

68 32 28 27 11

MEM_A_CS_L<0> H3

CS*

68 32 28 27 11

MEM_A_RAS_L

F4

MEM_A_CAS_L

G4

MEM_A_WE_L

H4

D4 MEM_A_DQS_N<6>

DM/TDQS

B8

NF/TDQS*

A8 A1

BA0 BA2

NC

G2

MEM_RESET_L

N3

2

H9

MEM_A_ZQ11 201

0 0 1 2 3 1 B C E E

1

C3032 20% 4V

VDDQ

2 CERM-X5R-1 201

ZQ

MEM_A_A<0>

K4

11 68

68 32 28 27 11

MEM_A_A<1>

L8

11 68

68 32 28 27 11

MEM_A_A<2>

L4

11 68

68 32 28 27 11

MEM_A_A<3>

K3

A3

11 68

68 32 28 27 11

MEM_A_A<4>

L9

A4

11 68

68 32 28 27 11

MEM_A_A<5>

L3

11 68

68 32 28 27

MEM_A_A<6>

M9

11 68

68 32 28 27 11

MEM_A_A<7>

M3

68 32 28 27 11

MEM_A_A<8>

N9

68 32 28 27 11

MEM_A_A<9>

M4

A9

68 32 28 27 11

MEM_A_A<10>

H8

A10/AP

68 32 28 27 11

MEM_A_A<11>

M8

68 32 28 27 11

MEM_A_A<12>

K8

MEM_A_A<13>

N4

11 68

11

11 68

MEM_A_A<14>

NC

N8

DQ0

A1


A2

A6


A7


A5

A12/BC* A13 A14

MEM_A_BA<0>

J3

MEM_A_BA<1>

K9

68 32 28 27 11

MEM_A_BA<2>

J4

68 32 28 27 11

MEM_A_CLK_P<0>F8

CK

68 32 28 27 11

MEM_A_CLK_N<0>G8

CK*

68 32 28 27 11

MEM_A_CKE<0> G10

CKE

68 32 28 27 11

MEM_A_CS_L<0> H3

CS*

MEM_A_RAS_L

F4

MEM_A_CAS_L

G4

MEM_A_WE_L

H4

11 68 11 68 11 68 11 68 11 68 11 68

11 68

D4 MEM_A_DQS_N<7>

11 68

DM/TDQS

B8

NF/TDQS*

A8 A1

BA0

A4

BA1 BA2

NC

RAS*

NC NC


B

CAS* WE*

VSS

VSSQ 3 2 9 0 0 B D B 1 1 C D

11 68


DQS*

A11

68 32 28 27 11

68 32 28 27 11

C

11 68

A8

68 32 28 27 11

68 32 28 27 11

B4 MEM_A_DQ<59>

A0

NC

68 32 28 27 11

OMIT_TABLE

RESET*

68 32 28 27 11

WE*

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

U3030 FBGA

11 68

CAS*

RAS*

VSS

=PP1V5_S3_MEM_A

0.47UF

VDD

ODT


A4

BA1

MEM_A_ODT<0>

1/20W

68 32 28 27 11

A14

J3

MEM_A_BA<1>

68 32 28 27 11

DQS*

A11

MEM_A_BA<0>

68 32 28 27 11


240

MF 1%

A8

68 32 28 27 11

11

30 29 28 27 26

R30301

B4 MEM_A_DQ<50>

A0

68 32 28 27 11

68 32 28 27 11

68 32 28 27 11

ZQ

MEM_A_A<0>

7

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

A C F E R V

DDR3-1333

OMIT_TABLE

RESET*

68 32 28 27 11

NC


201

FBGA

ODT

K4

11 68

11 68

MEM_A_ODT<0>

1/20W

11 68

A8

MEM_A_A<12>

MEM_A_A<14>

NF/DQ6 D3 MEM_A_DQ<47> E8 MEM_A_DQ<42> NF/DQ7

A7

MEM_A_A<11>

MEM_A_A<13>

DQ3 C9 MEM_A_DQ<44> E4 MEM_A_DQ<45> NF/DQ4 NF/DQ5 E9 MEM_A_DQ<40>

A4

68 32 28 27 11 68 32 28 27 11

R30201

DQ0 B4 MEM_A_DQ<46> C8 MEM_A_DQ<41> DQ1 DQ2 C3 MEM_A_DQ<43>

A1

68 32 28 27 11

NC


201

MEM_A_A<0>

11 68

E4 MEM_A_DQ<36>

MEM_A_ZQ9

2 1/20W

11 68

NF/DQ4

DQS

240

MF 1%

68 32 28 27 11 11 68

A4

A9

20%

32 28 27 7

DDR3-1333

OMIT_TABLE 68 32 28 27 11

30 29 28 27 26

240

MF 1%

68 32 28 27 11

1

0.47UF VDD


9

DDR3-1333 68 32 28 27 11

R30001

0 0 1 2 3 1 B C E E


68 31 30 29 28 27

=PP1V5_S3_MEM_A 68 31 30 29 28 27

1

VSSQ

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

3 2 9 0 0 B D B 1 1 C D


A

CONTROL


S YN C_ DA TE =1 2/ 07 /2 01 0

PAGE TITLE

DDR3 DRAM CHANNEL A (32-63) DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

30 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D


68 31 30 29 28 27

68 31 30 29 28 27


68 31 30 29 28 27 9



68 31 30 29 28 27


30 29 28 27 9 68 31

C3100

1

C3101

20%

1

20%

0.47UF 2 0.47UF 2 CERM-X5R-1 CERM-X5R-1 201 4V

201 4V

32 30 29 7

2 E Q D F E R V

9 J

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

=PP1V5_S3_MEM_B 0 0 1 2 3 1 B C E E

C3102

C3110 1 C3111 1

0.47UF

A C F E R V

VDD

32 30 29 7

20%

VDDQ

4V 2 CERM-X5R-1

20%

20%


201

U3100

201 4V

201 4V

2 E Q D F E R V

9 J

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

A C F E R V

DDR3-1333 68 32 30 29

11

MEM_B_ODT<0>

G2

MEM_RESET_L

N3

FBGA

ODT

30 29 28 27

26

OMIT_TABLE

RESET* 30 29 28

240

2

MEM_B_ZQ0

MF 1% 1/20W 201

C

68 32 30 29 11 68 32 30 29 11 68 32 30 29 11 68 32 30 29 11

K4

MEM_B_A<1>

L8

MEM_B_A<2>

L4

MEM_B_A<3>

K3

68 32 30 29 11

MEM_B_A<4>

L9

68 32 30 29 11

MEM_B_A<5>

L3

68 32 30 29 11

MEM_B_A<6>

M9

68 32 30 29 11

MEM_B_A<7>

M3

68 32 30 29 11

MEM_B_A<8>

N9

68 32 30 29 11

MEM_B_A<9>

M4

68 32 30 29 11

MEM_B_A<10>

H8

68 32 30 29 11

MEM_B_A<11>

M8

68 32 30 29 11

MEM_B_A<12>

K8

68 32 30 29 11

MEM_B_A<13>

N4

MEM_B_A<14>

N8

68 32 30 29

11

MEM_B_BA<0>

J3

68 32 30 29

11

MEM_B_BA<1>

K9

68 32 30 29

11

MEM_B_BA<2>

J4

ZQ

A1 A2 A3

NF/DQ5

E9 MEM_B_DQ<0>

11 68

NF/DQ6

D3 MEM_B_DQ<7>

11 68

NF/DQ7

E8 MEM_B_DQ<1>

11 68

A9 A11

A12/BC* A14

DQS*

D4 MEM_B_DQS_N<0>

NF/TDQS*

BA2

CKE CS*

A8

A4

BA1

CK*

B8

A1

BA0

MEM_B_CS_L<0> H3

H4

C4 MEM_B_DQS_P<0>

DM/TDQS

A13

CK NC

RAS* WE*

VSSQ

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

3 2 9 0 0 B D B 1 1 C D

A0

MEM_B_A<2>

L4

A2

68 32 30 29 11

MEM_B_A<3>

K3

A3

68 32 30 29 11

MEM_B_A<4>

L9

68 32 30 29 11

MEM_B_A<5>

L3

A5

68 32 30 29 11

MEM_B_A<6>

M9

A6

68 32 30 29 11

MEM_B_A<7>

M3

MEM_B_A<8>

N9

MEM_B_A<9>

M4

MEM_B_A<10>

H8

68 32 30 29 11

68 32 30 29 11

C3112

C3120 1 C3121 1

20% 4V

VDDQ

20%

2 CERM-X5R-1

0.47UF

201

CERM-X5R-1 201 4V

20%

2

0.47UF CERM-X5R-1 201 4V

2

2 E Q D F E R V

32 30 29 7

9 J

A11

K8

A12/BC*

MEM_B_A<13>

N4

A13

MEM_B_A<14>

N8

A14

11

MEM_B_BA<0>

J3

11

MEM_B_BA<1>

K9

11

MEM_B_BA<2>

J4

B8

NF/TDQS*

A8 A1 A4

BA2

MEM_B_CLK_P<0>F8

CK

68 32 30

29 11

MEM_B_CLK_N<0>G8

CK*

68 32 30 29 11

MEM_B_CKE<0> G10

CKE

68 32 30 29

MEM_B_CS_L<0> H3

NC

CS*

29 11

MEM_B_RAS_L

F4

RAS*

68 32 30 29 11

MEM_B_CAS_L

G4

CAS*

68 32 30

MEM_B_WE_L

H4

D4 MEM_B_DQS_N<1>

DM/TDQS

BA1

29 11

29 11

DQS*

BA0

68 32 30

11

C4 MEM_B_DQS_P<1> DQS

A10/AP

M8

68 32 30 29

NF/DQ6 D3 MEM_B_DQ<11> E8 MEM_B_DQ<8> NF/DQ7

A9

MEM_B_A<12>

68 32 30 29

DQ3 C9 MEM_B_DQ<13> E4 MEM_B_DQ<14> NF/DQ4 NF/DQ5 E9 MEM_B_DQ<12>

11 68

11

30 29 28 27

26

240

MF 1%

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

A C F E R V

NC

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

VSSQ 3 2 9 0 0 B D B 1 1 C D

MEM_RESET_L

N3

MEM_B_ZQ2

2 201

H9

1

VDDQ

C3122


2 E

C3130 1 C3131 1

2

20% 4V CERM-X5R-1 201

20%

0.47UF CERM-X5R-1 201 4V

U3120

Q D F E R V

20%

2

0.47UF CERM-X5R-1 201 4V

2

32 30 29 7

0 0 0 3 1 8 9 3 2 1 2 1 A A D G G K K M M

9 J

MEM_B_A<1>

L8

68 32 30 29 11

MEM_B_A<2>

L4

68 32 30 29 11

MEM_B_A<3>

K3

A3

68 32 30 29 11

MEM_B_A<4>

L9

A4

68 32 30 29 11

MEM_B_A<5>

L3

68 32 30 29 11

MEM_B_A<6>

M9

68 32 30 29 11

MEM_B_A<7>

M3

68 32 30 29 11

MEM_B_A<8>

N9

68 32 30 29 11

MEM_B_A<9>

M4

A9

68 32 30 29 11

MEM_B_A<10>

H8

A10/AP

68 32 30 29 11

MEM_B_A<11>

M8

68 32 30 29 11

MEM_B_A<12>

K8

68 32 30 29 11

MEM_B_A<13>

N4

11 68 11 68 11 68 11 68

11 68

MEM_B_A<14>

N8

68 32 30 29 11

MEM_B_BA<0>

J3

68 32 30 29 11

MEM_B_BA<1>

K9

68 32 30 29 11

MEM_B_BA<2>

J4

68 32 30 29

11

68 32 30 29

DQ0

A1

DQ1 C8 MEM_B_DQ<17> C3 MEM_B_DQ<23> DQ2 DQ3 C9 MEM_B_DQ<21>

A6

NF/DQ4 E4 MEM_B_DQ<22> E9 MEM_B_DQ<16> NF/DQ5 NF/DQ6 D3 MEM_B_DQ<18>

A7

NF/DQ7 E8 MEM_B_DQ<20>

A5

A13

68 32 30 29

MEM_B_CS_L<0> H3

CS*

F4

MEM_B_CAS_L

G4

MEM_B_WE_L

H4

NF/TDQS*

A8 A1

G2

30 29 28

27 26

MEM_RESET_L

N3

1

240

NC

MEM_B_ZQ3

2 1/20W 201

VDD

H9

1

C3132 20% 4V

VDDQ

2 CERM-X5R-1

ZQ

K4

11 68

68 32 30 29 11

MEM_B_A<1>

L8

11 68

68 32 30 29 11

MEM_B_A<2>

L4

11 68

68 32 30 29 11

MEM_B_A<3>

K3

A3

11 68

68 32 30 29 11

MEM_B_A<4>

L9

A4

11 68

68 32 30 29 11

MEM_B_A<5>

L3

11 68

68 32 30 29 11

MEM_B_A<6>

M9

11 68

68 32 30 29 11

MEM_B_A<7>

M3

68 32 30 29 11

MEM_B_A<8>

N9

68 32 30 29 11

MEM_B_A<9>

M4

A9

68 32 30 29 11

MEM_B_A<10>

H8

A10/AP

68 32 30 29 11

MEM_B_A<11>

M8

68 32 30 29 11

MEM_B_A<12>

K8

MEM_B_A<13>

N4

11 68

11 68

MEM_B_A<14>

NC

N8

NC

68 32 30 29

11

MEM_B_BA<0>

J3

68 32 30 29

11

MEM_B_BA<1>

K9

MEM_B_BA<2>

J4

68 32 30 29

11

DQ0

A1

DQ1 C8 MEM_B_DQ<29> C3 MEM_B_DQ<26> DQ2 DQ3 C9 MEM_B_DQ<28>

A2

A6

NF/DQ4 E4 MEM_B_DQ<27> E9 MEM_B_DQ<25> NF/DQ5 NF/DQ6 D3 MEM_B_DQ<31>

A7

NF/DQ7 E8 MEM_B_DQ<24>

A5

A12/BC* A13 A14

CK CK* CKE

68 32 30 29 11

MEM_B_CS_L<0> H3

CS*

F4 G4 H4

B8

NF/TDQS*

A8 A1 A4

NC

RAS*

11 68 11 68 11 68

NC NC


B

CAS* WE*

VSS

VSSQ 3 2 9 0 0 B D B 1 1 C D

11 68

11 68

DM/TDQS

BA2

MEM_B_CKE<0> G10

MEM_B_WE_L

11 68

11 68

BA1

MEM_B_CLK_N<0>G8

MEM_B_CAS_L

11 68

D4 MEM_B_DQS_N<3>

BA0

MEM_B_CLK_P<0>F8

MEM_B_RAS_L

11 68

DQS C4 MEM_B_DQS_P<3>

DQS*

A11

68 32 30 29 11

68 32 30 29 11

C

11 68

A8

68 32 30 29 11

68 32 30 29 11

B4 MEM_B_DQ<30>

A0

68 32 30 29 11

68 32 30 29 11

OMIT_TABLE

RESET*

MEM_B_A<0>

WE*

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

0 0 1 2 3 1 B C E E

201

FBGA

68 32 30 29 11

CAS*

RAS*

VSS

U3130

ODT

11 68


A4

BA2

CKE

MEM_B_RAS_L

B8

BA1

CK*

D4 MEM_B_DQS_N<2>

DM/TDQS

BA0

CK

MEM_B_ODT<0>

68 32 30 29 11

A14

MEM_B_CKE<0> G10

68 32 30 29 11

DQS*

A12/BC*

MEM_B_CLK_N<0>G8

68 32 30 29 11

DQS C4 MEM_B_DQS_P<2>

A11

MEM_B_CLK_P<0>F8

29 11

MF 1%

A8

11

11

B4 MEM_B_DQ<19>

A0

68 32 30 29 11

68 32 30

R3130

A2

=PP1V5_S3_MEM_B

0.47UF

A C F E R V

DDR3-1333

OMIT_TABLE

ZQ

68 32 30 29 11

11 68

FBGA

RESET*

MEM_B_A<0>

68 32 30 29 11

WE*

VSS

0 0 1 2 3 1 B C E E

68 31 30 29 28 27 9

0.47UF

VDD

ODT

68 32 30 29 11

NC


G2

K4

11 68

11 68

MEM_B_ODT<0>

1/20W

11 68

A8

MEM_B_A<11>

68 32 30 29

R3120 1

DQ0 B4 MEM_B_DQ<10> C8 MEM_B_DQ<9> DQ1 DQ2 C3 MEM_B_DQ<15>

A7

=PP1V5_S3_MEM_B

DDR3-1333

OMIT_TABLE

A4

68 32 30 29 11

68 32 30 29

FBGA

A1

68 32 30 29 11

68 32 30 29 11

NC

ZQ

K4

68 32 30 29 11

NC


RESET*

H9

L8

11 68

11 68

N3

MEM_B_A<1>

68 32 30

CAS*

VSS

U3110

ODT

68 32 30 29 11

68 32 30 29 11

A10/AP

MEM_B_CKE<0> G10

G4

DQS

MEM_B_ZQ1

G2

MEM_B_A<0>

11 68

A8

MEM_B_CLK_N<0>G8

MEM_B_WE_L

C9 MEM_B_DQ<4>

A7

11

MEM_B_CAS_L

DQ3

MEM_RESET_L

2 1/20W 201

11 68

A6

11

11

C3 MEM_B_DQ<3>

27 26

240

MF 1%

MEM_B_ODT<0>

68 32 30 29 11 11 68

A5

11

68 32 30 29

DQ2

11 68

11 68

68 32 30 29

68 32 30 29 11

DQ1

C8 MEM_B_DQ<5>

E4 MEM_B_DQ<6>

68 32 30 29

68 32 30 29 11

B4 MEM_B_DQ<2>

NF/DQ4

68 32 30 29

F4

DQ0

A4

MEM_B_CLK_P<0>F8

MEM_B_RAS_L

R31101

A0

11

68 32 30 29

B

H9

MEM_B_A<0>

1

0.47UF VDD


9

DDR3-1333 68 32 30 29 11

R3100 1

0 0 1 2 3 1 B C E E


68 31 30 29 28 27

=PP1V5_S3_MEM_B 68 31 30 29 28 27

1

VSSQ

2 2 2 2 2 3 9 9 9 0 0 0 A B J L N F A D F 1 1 1 J L N

3 2 9 0 0 B D B 1 1 C D


A

CONTROL


S YN C_ DA TE =1 2/ 07 /2 01 0

PAGE TITLE

DDR3 DRAM CHANNEL B (0-31) DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

31 OF 109

A

www.laptopblue.vn

8

7

www.laptopblue.vn

6

5

4

3

2

1

NOTE: Must not enable more than two SO-DIMM margining

7

buffers at once or VRef source may

=PP3V3_S3_VREFMRGN

be overloaded.

VREFMRGN OMIT 56 7

R3318 SHORT 1

2

VREFMRGN

402

1

2.2UF 20% 6.3V CERM 402-LF

D

C3301

VREFMRGN

0.1UF 2

2

10% 16V X5R-CERM 0201

U3300

6

=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA

Addr=0x98(WR)/0x99(RD)

SCL

7

SDA

9

A0

10

A1

VOUTA

MSOP 4 7 5 5 C A D

1

A2

V+

PLACE_NEAR=U2900.E1:2.54mm


MAX4253 A1

A3

VREFMRGN_DQ_SODIMMA_BUF

1

2

VOUTC

4

VOUTD

5

D

2

1% 1/20W MF 201

A4

VB4

VOUTB

133

9 27 28 29 30 68

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=0.75V

R3304

UCSP

2

VREFMRGN_SODIMMA_DQ

VREFMRGN

U3302

B1

0.1UF

VREFMRGN

VDD

BI

2

VREFMRGN

C3303 1

CRITICAL

10% 16V X5R-CERM 0201 8

44

200

1/20W MF 201

VREFMRGN

C3300 1

IN

1

1%

mm mm

VOLTAGE=3.3V

44

=PPVTT_S3_DDR_BUF 10mA max load

PP3V3_S3_VREFMRGN_DAC MIN_LINE_WIDTH=0.3 MIN_NECK_WIDTH=0.2

NONE NONE NONE

R3303

PLACE_NEAR=U2900.J8:1mm

NC VREFMRGN_SODIMMS_CA VREFMRGN_MEMVREG_FBVREF

NOTE: MEMVREG and FRAMEBUF share

GND

VREFMRGN 1 VREFMRGN

a DAC output, cannot enable

3

both at the same time!

R3309

R3301

200

1

PLACE_NEAR=J2900.126:2.54mm

2

100K 1%

5%

1/20W MF 201

1/20W MF 201

V+

MAX4253

NONE NONE NONE

MIN_LINE_WIDTH=0.3 MIN_NECK_WIDTH=0.2 VOLTAGE=0.75V

R3310

UCSP C1

2

VREFMRGN

U3302

B1 C2

SHORT


VREFMRGN

2

OMIT

R3319 1

VREFMRGN_CA_SODIMMA_BUF

133

1

27 28 29 30 68

mm mm

2

PP3V3_S3_VREFMRGN_CTRL MIN_LINE_WIDTH=0.3 MIN_NECK_WIDTH=0.2

mm mm

C3

CRITICAL

VOLTAGE=3.3V

VREFMRGN

402

6 1

C3302 1 10% 6.3V X5R 201

P0

6

3

A0

P1

7

4

A1

P2

9

5

A2

P3

10

P4

11

P5

12

P6

13

P7

14

(OD)

44

IN BI

=I2C_PCA9557D_SCL

1

SCL

=I2C_PCA9557D_SDA

2

SDA THRM

PAD 7 1

25

IN

PLACE_NEAR=R3309.2:1mm

PCA9557

Addr=0x30(WR)/0x31(RD)

44

1% 1/20W MF 201

C4

B4

U3301

2

QFN

C

V-

VREFMRGN

VCC

0.1UF

RESET*

NC VREFMRGN_DQ_SODIMMA_EN

C

VREFMRGN

NC

1

R3307

VREFMRGN_CA_SODIMMA_EN

100K

NC

5% 1/20W

VREFMRGN_MEMVREG_EN

MF

2 201

VREFMRGN_FRAMEBUF_EN

NC

15

GND 8

PCA9557D_RESET_L

RST* on ’platform reset’ so that system watchdog will disable margining. NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

B

QTY

DESCRIPTION

116S0004

2

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

2

RES,MTL FILM,0,5%,0402,SM,LF

REFERENCE DES

CRITICAL

R3303

VREFMRGN

BOM OPTION

C3305 1

R3309

VREFMRGN

0.1UF

VREFMRGN_NOT

10% 16V X5R-CERM 0201

VREFMRGN_NOT

C2

V+

MAX4253

R3314

UCSP C1

C3

VREFMRGN

U3304

B1 2

Page Notes

VREFMRGN 1

5%

- =PPVTT_S3_DDR_BUF

1/20W

2

V+

56

U3304 UCSP A1

A3

- =I2C_VREFDACS_SDA

OUT

MAX4253

201

- =I2C_VREFDACS_SCL

DDRREG_FB PLACE_NEAR=R7315.2:1mm

VREFMRGN B1 A2

MF

Signal aliases required by this page:

2

VREFMRGN_FRAMEBUF_BUF

R3313 100K

- =PP3V3_S3_VREFMRGN

1 1% 1/20W MF 201

C4

VB4

Power aliases required by this page:

B

33.2K VREFMRGN_MEMVREG_BUF

unused buffer

A4

VB4

- =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA BOM options provided by this page: VREFMRGN

VREFMRGN 1

- Stuffs VREF Margining

R3315 100K

Circuitry.

5%

VREFMRGN_NOT - Bypasses VREF Margining

1/20W MF

Circuitry.

A

2

MEM A VREF DQ DAC Channel:

A

PCA9557D Pin:

1

Nominal value

MEM B VREF DQ

MEM A VREF CA

MEM B VREF CA

B

C

C

2

3

4

MEM VREG D 5

0.75V (DAC: 0x3A)

1.5V (DAC: 0x3A)

201

GPU Frame Buffer (1.8V, 70% VRef)


PAGE TITLE

FSB/DDR3/FRAMEBUF Vref Margining DRAWING NUMBER

6

1.267V (DAC: 0x8B)

Margined target:

0.300V - 1.200V (+/- 450mV)

1.998V - 1.002V (+/- 498mV)

1.056V - 1.442V (+/- 180mV)

DAC range:

0.000V - 1.501V (0x00 - 0x74)

0.000V - 1.501V (0x00 - 0x74)

0.000V - 3.300V (0x00 - 0xFF)

VRef current:

+3.4mA - -3.4mA (- = sourced)

+33uA -

+6.0mA - -5.0mA (- = sourced)

-33uA (- = sourced)

SYNC_MASTER=K78_MLB

D

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

33 OF 109

A

8

32 28 27 7

7

www.laptopblue.vn

6

=PP1V5_S3_MEM_A

32 28 27

7

5

4

3

2

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

=PP1V5_S3_MEM_A

7

1

C3408

1

2.2UF

D

1

C3400

1

2.2UF

20% 6.3V 2 CERM 402-LF

1

C3409

1

C3401

1

C3411

1

C3418

1

2.2UF

C3421

1

C3431

1

1

2.2UF

C3441

1

C3451

68 28 27 11

IN

68 28 27 11

IN

MEM_A_CKE<0> MEM_A_A<10>

68 28 27 11

IN

MEM_A_A<7>

68 28 27 11

IN

68 28 27 11

IN

MEM_A_BA<0> MEM_A_WE_L MEM_A_ODT<0>

68 28 27 11

IN

68 28 27 11

IN

68 28 27 11

IN

MEM_A_A<3> MEM_A_A<6>

68 28 27 11

IN

MEM_A_A<1>

68 28 27 11

IN

MEM_A_A<11>

68 28 27 11

IN

MEM_A_CS_L<0>

68 28 27 11

IN

MEM_A_A<4>

IN

MEM_A_BA<1>

2.2UF

20% 6.3V 2 CERM 402-LF

C3442 2.2UF

20% 6.3V 2 CERM 402-LF

2 CAPS ALONG PACKAGE EDGE

20% 6.3V 2 CERM 402-LF

20% 6.3V 2 CERM 402-LF

C3412

C3450 2.2UF

2.2UF

20% 6.3V 2 CERM 402-LF

2.2UF

1

20% 6.3V 2 CERM 402-LF

2.2UF

C3419

20% 6.3V 2 CERM 402-LF

C3440 2.2UF

20% 6.3V 2 CERM 402-LF

1 1

20% 6.3V 2 CERM 402-LF

C3430 2.2UF

20% 6.3V 2 CERM 402-LF

2.2UF

20% 6.3V 2 CERM 402-LF

1

1

20% 6.3V 2 CERM 402-LF

2.2UF

20% 6.3V 2 CERM 402-LF

C3420 2.2UF

20% 6.3V 2 CERM 402-LF

2.2UF

2.2UF

20% 6.3V 2 CERM 402-LF

C3410 2.2UF

20% 6.3V 2 CERM 402-LF

20% 6.3V 2 CERM 402-LF


68 28 27 11

1

C3404

1

2.2UF

C3414

1

2.2UF

20% 6.3V 2 CERM 402-LF

C3424

1

2.2UF

20% 6.3V 2 CERM 402-LF

1

C3434

1

2.2UF

20% 6.3V 2 CERM 402-LF

C3444

1

2.2UF

20% 6.3V 2 CERM 402-LF

C3454

68 28 27 11

IN

MEM_A_A<12>

68 28 27 11

IN

68 28 27 11

IN

MEM_A_A<13> MEM_A_BA<2>

68 28 27 11

IN

MEM_A_A<0>

IN

MEM_A_A<14>

68 28 27 11

IN

MEM_A_A<8>

68 28 27 11

IN

MEM_A_A<5>

68 28 27 11

IN

MEM_A_A<2>

68 28 27 11

IN

MEM_A_CAS_L

68 28 27 11

IN

MEM_A_RAS_L

68 28 27 11

IN

MEM_A_A<9>

68 28 27 11

=PP0V75_S0_MEM_VTT_A

RP3401 RP3402 RP3406 RP3403 RP3402 RP3401

36 36 36 36 36 36

4

5

2

7

2

7

1

8

1

8

2

7

RP3403 RP3407 RP3406

36 36 36

2

7

3

6

1

8

RP3406 RP3402 RP3404 RP3403 RP3404 RP3407 RP3402 RP3403 RP3407

36 36 36 36 36 36 36 36 36

4

5

3

6

3 4 1

8

2 4 3

6

1

8

5%1/32W

4X0201

5%1/32W

4X0201

5%1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5%1/32W

4X0201

5%1/32W

4X0201

5%1/32W

4X0201

6

5% 1/32W

4X0201

5

5%1/32W

4X0201

5% 1/32W

4X0201

7

5%1/32W

4X0201

5

5%1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5%1/32W

4X0201

0.47UF

D

C3405

1

2.2UF

C3415

1

2.2UF

20% 6.3V 2 CERM 402-LF

C

1

C3425

1

2.2UF

20% 6.3V 2 CERM 402-LF

C3435

1

2.2UF

20% 6.3V 2 CERM 402-LF

20% 4V 2 CERM-X5R-1 201

1

1

C3416

1

C3455 2.2UF

20% 6.3V 2 CERM 402-LF

2.2UF

0.47UF

1

20% 6.3V 2 CERM 402-LF

RP3407 RP3404 RP3404 RP3401 RP3401 RP3406

36 36 36 36 36 36

0.47UF

1

C3428

C3402

2.2UF

2.2UF

20% 6.3V 2 CERM 402-LF

1

C3429 2.2UF

20% 6.3V 2 CERM 402-LF

32 30 29

5

2

7

4

5

5%1/32W 4X0201

3

6

5% 1/32W

4X0201

1

8

5%1/32W

4X0201

3

6

5% 1/32W

4X0201

5%1/32W

4X0201

20% 6.3V CERM 402-LF

1

C3403 2.2UF

20% 6.3V 2 CERM 402-LF

1

2.2UF

1

C3471 2.2UF

20% 6.3V 2 CERM 402-LF

1

B

C3470

20% 6.3V 2 CERM 402-LF

1

C3422

1

2.2UF

1

20% 6.3V 2 CERM 402-LF

C3423 2.2UF

20% 6.3V 2 CERM 402-LF

C3438 2.2UF

20% 6.3V 2 CERM 402-LF

1

2.2UF

1 1

C3439 2.2UF

20% 6.3V 2 CERM 402-LF

C3432

20% 6.3V 2 CERM 402-LF

C3433 2.2UF

20% 6.3V 2 CERM 402-LF

C3472

1

C3406 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3407 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3474 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3475 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3490 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3491 2.2UF

20% 6.3V 2 CERM 402-LF

1

1

C3452 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3453 2.2UF

20% 6.3V 2 CERM 402-LF

C3426 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3427 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3436 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3437 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3494 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3495 2.2UF

20% 6.3V 2 CERM 402-LF


C3476

1

2.2UF

COLUMN OF THREE CAPS BETWEEN PACKAGES

20% 6.3V 2 CERM 402-LF

68 30 29 11

IN

MEM_B_CKE<0> MEM_B_A<8>

68 30 29 11

IN

MEM_B_BA<2>

68 30 29 11

IN

MEM_B_A<1>

68 30 29 11

IN

MEM_B_A<10>

68 30 29 11

IN

68 30 29 11

IN

MEM_B_A<13> MEM_B_BA<0>

68 30 29 11

IN

MEM_B_CAS_L

68 30 29 11

IN

68 30 29 11

IN

MEM_B_A<7> MEM_B_RAS_L

68 30 29 11

IN

MEM_B_A<9>

IN

MEM_B_WE_L MEM_B_A<0>

1

C3456 2.2UF

20% 6.3V 2 CERM 402-LF

1

C3457 2.2UF

4X0201

IN

MEM_B_A<3>

IN

MEM_B_CS_L<0>

68 30 29 11

IN

MEM_B_A<6>

68 30 29 11

IN

MEM_B_A<12>

68 30 29 11

IN

MEM_B_BA<1>

IN

MEM_B_A<14>

68 30 29 11

IN

MEM_B_A<2>

68 30 29 11

IN

68 30 29 11

IN

MEM_B_A<4> MEM_B_ODT<0>

68 30 29 11

IN

MEM_B_A<5>

68 30 29 11

IN

MEM_B_A<11>

RP3413 RP3410 RP3409 RP3411

RP3409 RP3410 RP3408 RP3413 RP3411 RP3413 RP3411 RP3409 RP3408 RP3408 RP3409 RP3410 RP3414 RP3408 RP3410 RP3414 RP3414 RP3413 RP3414 RP3411

36 36 36 36

20% 4V 2 CERM-X5R-1 201

1

C3485 0.47UF

20% 4V 2 CERM-X5R-1 201

1

C3487 0.47UF

20% 4V 2 CERM-X5R-1 201

C3488

20% 4V 2 CERM-X5R-1 201

1

C3489 0.47UF

C

36 36 36 36 36 36 36 36 36 36 36 36 36 36 36

36 36 36 36 36

=PP0V75_S0_MEM_VTT_B

1

8

1

8

1

8

4

5

3

1 5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

0.47UF

1

6 6

5%1/32W 4X0201

4

5

5%1/32W 4X0201

3

6

2

7

4

5

3

6

4

5

2

7

3

6

2

7

5% 1/32W 4X0201

4

5

5%1/32W

4

5

5% 1/32W

4X0201

1

8

5%1/32W

4X0201

2

7

5%1/32W

4X0201

5% 1/32W

4X0201

3

5%1/32W

4X0201

5%1/32W

4X0201

5%1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

5% 1/32W

4X0201

0.47UF

1

0.47UF

1

C3463 0.47UF

20% 4V 2 CERM-X5R-1 201

7 8

5% 1/32W

7

5%1/32W

4X0201

5% 1/32W

4X0201

5%1/32W

4X0201

5%1/32W

4X0201

8

1

C3462 0.47UF

20% 4V 2 CERM-X5R-1 201

4X0201

2

1

C3461

20% 4V 2 CERM-X5R-1 201

1

6

C3460

20% 4V 2 CERM-X5R-1 201

2

3

C3481

20% 4V 2 CERM-X5R-1 201

4X0201

1

1

C3464

B

0.47UF

20% 4V 2 CERM-X5R-1 201

C3465 0.47UF

20% 4V 2 CERM-X5R-1 201

1

C3466 0.47UF

20% 4V 2 CERM-X5R-1 201

MEM CLOCK TERMINATION

1

C3467 0.47UF

20% 4V 2 CERM-X5R-1 201

Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM

20% 6.3V 2 CERM 402-LF

R3468

C3496

1

MEM_A_CLK_N<0>

3.3PF

20% 6.3V 2 CERM 402-LF

5% 25V CERM 201

68 28 27 11

2

2

C3469 MEM_A_CLK_TERM_R 1

A

30

2

VOLTAGE=0V

0.1UF 10% X5R 201 6.3V

R3469 1

MEM_A_CLK_P<0>

30

5% 1/20W MF 201

C3468 1

2.2UF


IN

68 30 29 11

68 30 29 11

68 28 27 11

1

IN

68 30 29 11

C3492

20% 6.3V 2 CERM 402-LF

1

68 30 29 11

68 30 29 11

2.2UF

20% 6.3V 2 CERM 402-LF

0.47UF

20% 4V 2 CERM-X5R-1 201

68 30 29 11

2.2UF


5%1/32W

C3446

=PP1V5_S3_MEM_B

7

C3483

20% 6.3V 2 CERM 402-LF


=PP1V5_S3_MEM_B

1

0.47UF

4

7

30 29 7 32

C3486

20% 4V 2 CERM-X5R-1 201

2.2UF

20% 6.3V 2 CERM 402-LF


C3445

C3484

20% 4V 2 CERM-X5R-1 201

20% 6.3V 2 CERM 402-LF

2.2UF

20% 6.3V 2 CERM 402-LF

C3482 0.47UF

1

1

C3480

20% 4V 2 CERM-X5R-1 201

1

2.2UF

20% 6.3V 2 CERM 402-LF

1

2

5% 1/20W MF 201


68 30 29 11

1

MEM_B_CLK_N<0>

3.3PF

68 30 29 11

MEM_B_CLK_P<0>

2

30 5%

1

DDR3 DRAM Channel B (32-63) DRAWING NUMBER

2

Apple Inc.

VOLTAGE=0V

0.1UF

R3479 1

C3479

2 MEM_B_CLK_TERM_R

5% 1/20W MF 201

C3478 1 5% 25V CERM 201

30

S YN C_ DA TE =1 2/ 16 /2 01 0

PAGE TITLE

R3478

2

10% X5R 201 6.3V

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

34 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D

7

=PP3V3_S3_CARDREADER BYPASS=U3500.1:16:5 mm

SDCARD_IOVDD BYPASS=U3500.8:5 BYPASS=U3500.8:5 mm mm

C3503

1 2

SDCARD_PLLVDD

0.1UF 10%

CRITICAL

1

6.3V

2

L3500

X5R 201

0.22UH

C3502

1

0.1UF 2

C3501 0.1UF

10%

0805-1

10%

6.3V

2

X5R 201

6.3V X5R 201

R3505 is for rail discharge. recover from card error.

1

PP3V3_S3_CARDREADER_AVDD MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

Keep this net short!

C3514 1

1

4.7UF

1

C3507

10%

2

2

6.3V

D D V A

C USB_SDCARD_N

NO STUFF 1

R3507

D D V O I

DVDD

D D V L L P

U3500

22 GPIO0 6 GPIO1

R3506

1

1

715

10K

1% 1/20W MF 201

R3510

NC

1

2

2

5% 1/20W MF 201

C3513

PDMOD: POWER DOWN MODES NC = DISABLE (DEFAULT)

C3505 10%

2

2

6.3V X5R 201

X5R 201

D0

13 SD_D_R<0>

D1

14 SD_D_R<1>

D2

9

10 SD_D_R<3>

D4

18 SD_D_R<4>

D5

19 SD_D_R<5>

D6

20 SD_D_R<6>

D7

21 SD_D_R<7>

R3528 1 R3527 1 5% 1/16W

SD_D_R<2>

R3525 1 5 %1 /1 6 W

R3523 1 5 %1 /1 6 W

R3521 1 5% 1/16W

2

5% 1/16W 2 0 402 MF-LF

2

R3531 1

0

402

R3524 1

0

402

R3522 1 5%1/16W

SD_CMD

2

CMD

6

SD_D<0>

7

6

SD_D<1>

8

DAT0 DAT1

6

SD_D<2>

9

6

SD_D<3>

1

6

SD_D<4>

10

6

SD_D<5>

11

6

SD_D<6>

12

6

SD_D<7>

13

MF-LF

2 0 402 MF-LF

0

402

5

6

MF-LF

2

5% 1/16W

MF-LF

(IPD) (IPD) (IPU) (IPU)

SD_CLK

12

SD_WP

24

SD_CMD

11

SD_CDZ

23

MS_INS

25

SD_CLK_R

R35201 5%

SD_CMD_R

1/20W

R3519 1 5% 1/16W

2 33 SD_CLK_L1 MF 201

2 33NH

6

SD_WP

DAT6 DAT7 CARD_DETECT_SW CARD_DETECT_GND WRITE_PROTECT_SW

16

20 402

CD/DAT3 DAT4 DAT5

15

0402

4 MF-LF

6

NO STUFF

NC

C3515 1

STUFF 1NOC3521

STUFF 1NO C3523

STUFF 1NO C3525

10PF

10PF

10PF

10PF

5% 25V NPO

C3519 5% 50V CERM 402

2

1NO STUFF 2 C3520 10PF

201

2

5% 50V CERM 402

5% 50V CERM 402

2

NO STUFF

C3522 1 10PF 5% 50V CERM 402

5% 50V CERM 402

2

5% 50V CERM 402

5% 50V CERM 402

C3527 10PF

2

R3530 0 5% 1/16W MF-LF

2

2

VDD

17

SHLD_PIN

18

1NO STUFF

NO STUFF

1

NO STUFF

C3524 1 10PF

2

SD_CD_L

402

C

DAT2

14

L3504

(IPU)

17 GPIO2

VSS VSS CLK

SD_CLK

2 0 6 402 MF-LF

5% 1/16W

0

4 0 2 MF-LF

2

SD_CLK_R2

0

4 0 2 MF-LF

2

2 0 402 MF-LF

MF-LF

2

5% 1/16W

2

D

R3529 1

0

402

R3526 1

10PF

Q3500

3 6

1NO STUFF

2

J3500 F-RT-TH

5% 1/16W

10%

6.3V

10K HIGH = REMOTE WAKE UP ENABLE

CRITICAL SD-CARD-K16

Max Current = 800 mA

5% 1/20W MF 201

SD_CLK_R1

9 2

1

2

0.1UF

10K LOW = POWER SAVING MODE ENABLE


R3505 47K

0.1UF

S O M P

D3

THRM_PAD

NO STUFF

2

5 1

QFN

26 RSTZ* 27 TEST

GL137_RESET_L

10K

20% 6.3V X5R-CERM1 402

GL822

2

GL137_GPIO1

5% 1/20W MF 201

8 2

8

CRITICAL

GL137_GPIO0

R3509

6 1

4 RREF

GL137_RREF

10K 5% 1/20W MF 201

1 7

3 DP 2 DM

USB_SDCARD_P

BI BI

1

4.7UF

X5R 201

5

69 24

1

PP3V3_SW_SD_PWR

6

C3504 0.1UF

20% 6.3V X5R-CERM1 402

69 24

GL822 may cycle PMOS to

Off duration is 100ms and card

voltage must be less than 0.5V for at least 1ms per spec.

BYPASS=U3500.3:5:5 mm

SHLD_PIN

19

SHLD_PIN

20

SHLD_PIN

5% 50V CERM 402

NO STUFF

C3526 1

516-0237

10PF 5% 50V CERM 402

2

3

SSM6N37FEAPE SOT563

B R3590 23 18

IN

SDCONN_STATE_RST_L

2

0

1

5% 1/20W MF 201

5

SDCONN_STATE_RST_R

R3500

B S

4

SDCARD_PLT_RST

1

10K 5% 1/20W MF 201

G

Q3500

A

IN

6

S

1

SOT563

2

25

D

SSM6N37FEAPE 2

G

SDCARD_PLT_RST_L

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PAGE TITLE

SecureDigital Card Reader DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

35 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

CRITICAL OMIT_TABLE 70 8

IN

PCIE_T29_R2D_C_P<0>

C3600

70 8

IN

PCIE_T29_R2D_C_N<0>

C3601

70 8

70 8

70 8

D

IN

PCIE_T29_R2D_C_P<1>

IN

PCIE_T29_R2D_C_N<1>

70 8

C3602

C3604

PCIE_T29_R2D_C_P<2>

1

C3605

1

PCIE_T29_R2D_C_P<3>

IN

PCIE_T29_R2D_C_N<3>

C3606

1

0.1UF

70

PCIE_T29_R2D_P<0>

70

PCIE_T29_R2D_N<0>

U3600

P14 PERP_0 P15 PERN_0

EAGLE_RIDGE-192

PETP_0

T14

70

PCIE_T29_D2R_C_P<0>

PETN_0

T15

70

PCIE_T29_D2R_C_N<0>

C3640

6.3V

X5R

201

6 .3 V

X5R

201

70

PCIE_T29_R2D_P<1>

70

PCIE_T29_R2D_N<1>

1

6.3V

X5R

201

2 10%

1

6.3 V

X5R

70

PCIE_T29_R2D_P<2>

70

PCIE_T29_R2D_N<2>

1

6 .3 V

X 5R

201

6.3V

X5R

201

2

10%

E V I E C E R

F14 PERP_2 F15 PERN_2

70

PCIE_T29_R2D_P<3>

70

PCIE_T29_R2D_N<3>

T I M S N A R T

M14

70

PCIE_T29_D2R_C_P<1>

PETN_1

M15

70

PCIE_T29_D2R_C_N<1>

C3642 0.1UF

C3643

H14

70

PCIE_T29_D2R_C_P<2>

R3610

1

PETN_2

H15

70

PCIE_T29_D2R_C_N<2>

C3645

PETP_3

D14

70

TP_T29_MONOBSP

R3611

PCIE_T29_D2R_C_P<3>

PETN_3

D15

70

PCIE_T29_D2R_C_N<3>

1/20W

MF

201

5%

1/20W

MF

201

NO STUFF

C3615

1

2 10%

0.1UF

6.3 V

T29_MONOBSP

A13 MONOBSP

T29_MONOBSN

B13 MONOBSN

X5R

201

DEBUG: For monitoring clock

TP_T29_MONOBSN

C3616

1

36 35 34

2 10%

0.1UF

0.1UF

C3647

WAKE*

M2

T29_PCIE_WAKE_L

1

PERST*

C2

T29_RESET_L

RSENSE

C8

T29_RSENSE

R3651

6.3V

X5R

201

IN

X 5R -C ER0201 M

2

PCIE_T29_D2R_P<1> 16V

X 5 R- CE R0201 M

2

PCIE_T29_D2R_N<1>

1 0%

16V

X 5R -C ER0201 M

2

PCIE_T29_D2R_P<2>

1 0%

16V

X 5R -C ER0201 M

2

PCIE_T29_D2R_N<2>

1 0%

16V

2

PCIE_T29_D2R_P<3>

X 5R -C ER0201 M

10%

16V

2

PCIE_T29_D2R_N<3>

10%

1 6 V

X 5 R- CE R0201 M

X5R-CERM 02 0 1

1

OUT

8 70

OUT

8 70

OUT

8 70

OUT

8 70

OUT

8 70

OUT

8 70

OUT

8 70

OUT

8 70

D

7 34 35 36

2 5%

1/20W

MF

201

36

1

R3655 1.0K 0.1% 1/16W TF

=PP3V3_T29_RTR

7

1

X 5R -C ER0201 M

10%

10K

A15 MONDC1

T29_MONDC1

2

16V

PCIE_T29_D2R_N<0> 16V

=PP3V3_T29_RTR

A14 MONDC0

T29_MONDC0 5%

1

0

1

C3646

DEBUG: For monitoring current/voltage

TP_T29_MONDC1

1

0.1UF

0.1UF

2

0

1

C3644

NO STUFF TP_T29_MONDC0

1

0.1UF

PETP_2

PCIE_T29_D2R_P<0>

2 1 0%

0.1UF

E I C P

B15 PERP_3 B14 PERN_3

PETP_1

2 1 0%

1

0.1UF

2 N E G

201

2 1 0%

K14 PERP_1 K15 PERN_1

1

0.1UF

C3641

FCBGA

2 10%

0.1UF

C3607

201

2 1 0%

0.1UF

IN

20 1

X5R

2 10%

0.1UF

PCIE_T29_R2D_C_N<2>

X5R

6 .3 V

(1 OF 2)

0.1UF

C3603

6 . 3 V

2 1 0%

0.1UF

IN

70 8

2 10 %

1

0.1UF

IN

70 8

1

0.1UF

2 402

1

R3690 5% 1/20W MF 201

1

1

R3691

3.3K

1/20W

2

1

R3692

1.0UF

5%

2

C3690

MF 201

5% 1/20W MF 201

CRITICAL OMIT_TABLE

8

2

VCC 5

(T29_SPI_MOSI)

C

C

(T29_SPI_CS_L)

1

S_L

3

W_L

7

2

Q

OUT

=T29_CLKREQ_L

5% 1/20W MF 2 201

MLP

HOLD_L

THM PAD

4

T E S E R

T S E U Q E R

N O

K L C

3.3K

2KX8-1.8V

VSS

P1 PCIE_CLKREQ_0*

R3693

(T29_SPI_MISO)

M95160

6

T29ROM_HOLD_L

36

1

U3690

D

(T29_SPI_CLK)

T29ROM_WP_L

C7

T29_RBIAS

PCIE_RST_0*

R1

Not used in host mode. TP_T29_PCIE_RESET0_L

PCIE_RST_1*

L1

TP_T29_PCIE_RESET1_L

PCIE_RST_2*

L2


PCIE_RST_3*

G2


TDI

T3

JTAG_T29_TDI

G TMS A T TCK J

T5

JTAG_T29_TMS

R2

JTAG_T29_TCK

TDO

U4

JTAG_T29_TDO

3.3K

20% 6.3V 2 X5R 0201-MUR

3.3K

RBIAS

47

72

T29_SPI_MOSI

72

T29_SPI_MISO

72

T29_SPI_CS_L

72

T29_SPI_CLK

U6 EE_DI P2 EE_DO

R E W O P

C S I M

M O R

U3 EE_CS* P E E N1 EE_CLK B2 THERM_DP

TP_T29_THERM_DP

S K C O L C

Use B1 GND ball for THERM_DN

9

T29_TEST_EN

E2 TEST_EN

1

R3625 0 5%

T29_TEST_POINT_3

1/20W

D1 TEST_PWR_GOOD

T R O P T S E T

REFCLK_100_IN_P

A12

REFCLK_100_IN_N

B12

XTAL_25_IN

D11

XTAL_25_OUT

C11

TMU_CLK_OUT

U5

TMU_CLK_IN

M1

70

IN

8

IN

16

IN

8

OUT

8

PCIE_CLK100M_T29_P

IN

16 70

PCIE_CLK100M_T29_N

IN

16 70

=PP3V3_T29_RTR

R3698 10K 5% 1/20W

MF 2 201

R3695

SYSCLK_CLK25M_T29_R

1

TP_T29_XTAL25OUT T29_TMU_CLK_OUT

1K

T29_TMU_CLK_IN

5% 1/20W MF 201

NO STUFF

MF

1

R3699

806

2

SYSCLK_CLK25M_T29

IN

25 70

1% 1/20W MF 201

1

R3696

2 201

C

7 34 35 36

1

2

10K 1

R3629 0

SNK0 AC Coupling 72 8

IN

C3620

DP_T29SNK0_ML_C_P<0>

1

72 8

IN

DP_T29SNK0_ML_C_N<0>

C3621

72 8

IN


C3622

1

2

1

2

B

IN


1

IN


C3624

72 8

IN


C3625

1

2

2

IN


C3626

IN


C3627

1

2

1

0.1UF

BI

DP_T29SNK0_AUXCH_C_P

C3628

72 8

BI

DP_T29SNK0_AUXCH_C_N

C3629

2

34 72

8

OUT

DP_T29SNK0_ML_N<3>

72 34

DP_T29SNK0_ML_P<2>

72 34

DP_T29SNK0_ML_N<2>

72 34

DP_T29SNK0_ML_P<1>

72 34

DP_T29SNK0_ML_N<1>

72 34

DP_T29SNK0_ML_P<0>

72 34

DP_T29SNK0_ML_N<0>

72 34

DP_T29SNK0_AUXCH_P

72 34

DP_T29SNK0_AUXCH_N

T7 DPSNK0_AUX_CHP U7 DPSNK0_AUX_CHN

DP_T29SNK0_HPD

T4 DPSNK0_HDMI_IN_HOT_PLUG_DET

1

2

T11 DPSNK0_ML_LANE_0P_IN0_HDMI_TMDS_2_P U11 DPSNK0_ML_LANE_0N_IN0_HDMI_TMDS_2_N

1

34 72

DP_T29SNK0_ML_N<3>

34 72

5% 1/20W MF 201

2

DP_T29SNK0_AUXCH_P

34 72

DP_T29SNK0_AUXCH_N

34 72

5% 1/20W

MF 2 201

34

T29_HDMI_SCL_IN

34

T29_HDMI_SDA_IN

34 34

7 34 35 36

K N I S

DPSRC0_ML_LANE_3P_OUT0_HDMI_TMDS_2_P

T12

DP_T29SRC_ML_CP<3>

DPSRC0_ML_LANE_3N_OUT0_HDMI_TMDS_2_N

U12

DP_T29SRC_ML_CN<3>

R3661 R3662

1

2

01

2

0

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

0 T R O P E C R U O S

B DPSRC0_ML_LANE_0P_OUT0_HDMI_TMDS_CLK_P

N12

DP_T29SRC_ML_CP<0>

DPSRC0_ML_LANE_0N_OUT0_HDMI_TMDS_CLK_N

R12

DP_T29SRC_ML_CN<0>

R3663 R3664

1

2

01

2

0

100pF SRF > 40MHz

I U1 HDMI_5V_OUT M D H

=PP3V3_T29_RTR

10K

=PP3V3_T29_RTR

T R O P

T6

DP_T29SRC_HPD

DP_ATEST

U15

T29_DP_ATEST

DP_RES

U14

T29_DP_RES

DPSRC0_HOT_PLUG_DET

10% 16V X5R-CERM 0201

R3670

2

0

2

10% 1 6V X5R-CERM 0201 1

1

A

T10 DPSNK0_ML_LANE_1P_IN0_HDMI_TMDS_1_P U10 DPSNK0_ML_LANE_1N_IN0_HDMI_TMDS_1_N

R3630

TP_T29_HDMI_5V_OUT

36 35 34 7

T9 DPSNK0_ML_LANE_2P_IN0_HDMI_TMDS_O_P U9 DPSNK0_ML_LANE_2N_IN0_HDMI_TMDS_0_N

100K DP_T29SNK0_ML_P<3>

5% 1/20W MF 201

T8 DPSNK0_ML_LANE_3P_IN0_HDMI_TMDS_CLK_P U8 DPSNK0_ML_LANE_3N_IN0_HDMI_TMDS_CLK_N

10% 16V X5R-CERM 0201

0.1UF

0.1UF

34 72

DP_T29SNK0_ML_N<2>

10% 16V X5R-CERM 0201

0.1UF

72 8

DP_T29SNK0_ML_P<2>

10% 16V X5R-CERM 0201

DP_T29SNK0_ML_P<3>

72 34

34 72

10% 16V X5R-CERM 0201 1

0.1UF

72 8

34 72

10% 16V X5R-CERM 0201

0.1UF

72 8

34 72

DP_T29SNK0_ML_P<1> DP_T29SNK0_ML_N<1>

2

0.1UF 72 8

DP_T29SNK0_ML_N<0>

2

10% 16V X5R-CERM 0201

0.1UF 72 8

5% 1/20W MF 201

34 72

10% 16V X5R-CERM 0201

0.1UF

C3623

DP_T29SNK0_ML_P<0>

2

10% 16V X5R-CERM 0201

0.1UF

72 34

T R O / P I Y M A D L H P S I D

C3685 1 100PF

I M D H

HDMI_SCL_IN

B1

HDMI_SDA_IN

1

T29_HDMI_SCL_IN

34

A2

T29_HDMI_SDA_IN

34

HDMI_OUT_HOT_PLUG_DET

F3

T29_HDMI_OUT_HPD

PRT0_CIOT_P

R3685 14K

34

1% 1/20W MF 201

1

R3632 100K

2

2

5% 25V CERM 2 201

1

C3686 0.01UF

10% 10V 2 X5R 201

5% 1/20W MF 201

1

R3671 10K 5% 1/20W

MF 2 201

S T R O P

T29_CIO_PLUG_EVENT T29_HDMI_OUT_HPD

1

R3673 10K 5% 1/20W

MF

2 201

1

R3674

A6

T29_R2D_C_P<0>

OUT

PRT0_CIOT_N

B6

T29_R2D_C_N<0>

OUT

64 72

0 T PRT0_CIOR_P R O PRT0_CIOR_N P

A4

T29_D2R_P<0>

IN

64 72

B4

T29_D2R_N<0>

IN

64 72

CIO_0_LSEO

H2

T29_LSEO<0>

CIO_0_LSOE

5% 1/20W

MF

C1 CIO_MDC

64

IN

64

T29_LSOE<0>

B10

T29_R2D_C_P<1>

OUT

64 72

PRT1_CIOT_N

A10

T29_R2D_C_N<1>

OUT

64 72

IN

64 72

IN

64 72

T29_D2R_P<1>

B8

T29_D2R_N<1>

J1

T29_LSEO<1>

CIO_1_LSOE

K2

SYNC_MASTER=K78_MLB


PAGE TITLE

A8

CIO_1_LSEO

CIO_PLUG_EVENT I2C_T29_SCL

OUT

K1

PRT1_CIOT_P 1 T PRT1_CIOR_P R O P PRT1_CIOR_N

10K

2 201

64 72

T29_LSOE<1>

H1 T29_CIO_PLUG_EVENT

34

T29 Host (1 of 2) DRAWING NUMBER

Apple Inc.

64

051-8870

IN

64

SIZE

D

REVISION

3.13.0

R

OUT


BRANCH


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36 OF 109

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6

5

4

D

3

2

1

D

CRITICAL 35 7

U3600

H3

C3700 1

1

10UF

C3705

1

1.0UF

20% 6.3V CERM-X5R 0402

2

2

20% 6.3V X5R 0201-MUR

1

C3706 1.0UF

2

C3707

1

1.0UF

20% 6.3V X5R 0201-MUR

2

20% 6.3V X5R 0201-MUR

1

C3708 1.0UF

2

20% 6.3V X5R 0201-MUR

2

C3709

H6

FCBGA

1.0UF

H7

(2 OF 2)

20% 6.3V X5R 0201-MUR

VCC3P3

J3

C6

VCC3P3_CIO VCC1P0

VCC

J6

C3701

1

1

1

1

1

C3714

J7

10UF

1.0UF

1.0UF

1.0UF

1.0UF

1.0UF

J8

20% 6.3V CERM-X5R 0402

20% 6.3V X5R 0201-MUR

20% 6.3V X5R 0201-MUR

20% 6.3V X5R 0201-MUR

20% 6.3V X5R 0201-MUR

20% 6.3V X5R 0201-MUR

2

2

C3710

2

C3711

2

C3712

2

C3713

2

152 mA (Dual-Port) C3744 1

C3743 1

1.0UF

1.0UF

20% 6.3V X5R 0201-MUR

C3745 1

1

20% 6.3V X5R 0201-MUR

2

1.0UF 2

C3747 1.0UF

20% 6.3V X5R 0201-MUR

2

2

20% 6.3V X5R 0201-MUR

1

C3748

1

10UF

20% 6.3V 2 CERM-X5R 0402

R8 R10 N5

C12 VDD1P0_DP

D7 D8

0-ohms are placeholders for now, replace

R3750 PP3V3_T29_DP

N10

C10

EDP: 200 mA

C3749 10UF

20% 6.3V 2 CERM-X5R 0402

D5

N8 VCC3P3_DP

J10

1

C3753

C3752

1.0UF

1.0UF

20% 6.3V X5R 0201-MUR

1

20% 6.3V X5R 0201-MUR

2

C3751

1

C3750

1.0UF 20% 6.3V X5R 0201-MUR

2

1

0

1

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

5%

1/20W

MF

201

with proper values after characterization.

2

1.0UF 20% 6.3V X5R 0201-MUR

2

2

=PP1V05_T29_RTR

7 35

N6

2100 mA (Single Port)

R5

2250 mA (Dual Port)

R6

EDP: 3000 mA

R3720

D10 D12

1

C3746

1.0UF

20% 6.3V X5R 0201-MUR

2

D6

J5 1

D3

C5

H8 H10

7 34 36

135 mA (Single-Port) C3

EAGLE_RIDGE-192

H5

2250 mA (Dual Port) EDP: 3000 mA

=PP3V3_T29_RTR

OMIT_TABLE

=PP1V05_T29_RTR

2100 mA (Single Port)

PP1V05_T29_VDD_DP MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

VCC1P0_PE

F11

1

F12 G11

1

C3720

2

G12

1

C3721

C3722

1.0UF

1.0UF

1.0UF

20% 6.3V X5R 0201-MUR

20% 6.3V X5R 0201-MUR

20% 6.3V X5R 0201-MUR

2

2

0

1 5% MF

2

1/20W 201

C

C

A1

A3

F5

A5

F6

A7

F7

A9

F8

A11

F10

B3

G3

B5

G5

B7

G6

B9

G7

B11

G8

C14

G10

C15

L3 L5 L6

E14 E15

VSS

G14 VSSPE

L7 L8

H12

GND

M3

B

G15 H11

L10

J11

M5

J12

M6

J14

M7

J15

M8

L11

M10

L12

M11

L14

M12

L15

B

N14 N3

N15

N7

R14

N11

R15

R3 1

R3723 10K

5% 1/20W MF 201 2

A

1

R3722 10K

5% 1/20W MF

2 201

1

R3721

10K

5% 1/20W MF

2 201

1

R3724

R7

10K

R11

5% 1/20W MF

T13

2 201

VSSDP 1

R3733 10K 5% 1/20W MF 201

U13

T29_GPIO<0>

J2

T29_GPIO<4>

N2

GPIO_4

T29_GPIO<5>

U2

GPIO_5

T29_GPIO<6>

D2

GPIO_6

GPIO_0

GPIO_7

E1

T29_GPIO<7>

GPIO_8

F2

T29_GPIO<8>

GPIO_9 G1 GPIO_10 T2

T29_GPIO<9>

GPIO_11 T1

T29_GPIO<11>

2

1

1

1

R3732 R3731 R3730 10K

10K

10K

5% 1/20W MF 201

5% 1/20W MF 201

5% 1/20W MF 201

2

2

2

1

R3734 10K 5% 1/20W MF

2 201

T29_GPIO<10>


S YN C_ DA TE =0 1/ 10 /2 01 1

PAGE TITLE

T29 Host (2 of 2) DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


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6

5

Page Notes Power aliases required by this page:

CRITICAL

- =PPVIN_SW_T29BST

(8-13V Boost Input)

T29BST:Y

- =PP18V_T29_REG

(18V Boost Output)

Q3880

- =PP3V3_T29_P3V3T29FET

(3.3V FET Input)

- =PP3V3_T29_FET

8 7

(3.3V FET Output)

3

- =PP1V05_T29_P1V05T29FET

(1.05V FET Input)

- =PP1V05_T29_FET

(1.05V FET Output)

Vgs(max): +/-12V

BGA

R3820

for 2S.

1

T29BST:Y

R3880

1 1

5% 1/20W MF 201

- =T29_RESET_L

C3880

-1.4V

Rds(on):

46mOhm @ 4.5V Vgs

Id(max):

3.7A @ 70C

S

4

D

7 6

T29BST:Y

L3895

6.8UH-4.0A 1

PPVIN_SW_T29BST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

2

T29BST:Y

PPVIN_SW_T29BST_R

Voltage not specified here, add property on another page.

G

10% 25V X5R 402

10UF

10UF

10% 25V X5R 805

10% 25V X5R 805

R38911

1

2

T29BST_SNS1

8

T29BST_EN_UVLO

25

EN/UVLO

28

INTVCC

30

VC

SNS1

6

SNS2

3

D

3

C3892 1

Q3805

1

T29_A_HV_EN

1

4.7UF 10% 10V X5R 805

G

S

C3887

POWERDI-123

DFLS230L 2

2

XW3895 SM

2

5% 25V NP0-C0G 201

10K

T29BST_RT

33

RT

T29BST_SS

32

SS

2

T29BST:Y 1

R3892

2

1% 1/20W MF 201

T29BST:Y 1

C3893 3300PF

2

10% 10V X7R 201

35

34

T29BST:Y 1

2 2

3 4 7 2 2 3

5% 50V CERM 402

NO STUFF 1

4

2 1

3 4 5 1 1 1

C3889 100PF

2

6 7 1 1

133K 1% 1/16W MF-LF 402

=PP15V_T29_REG 2

5% 50V CERM 402

SGND shorted to

UVLO = 4.55V (falling), 4.95 (rising)

GND inside package,

C3895

1

15.8K 1% 1/16W MF-LF 402

2

2

T29BST:Y

Freq = 300KHz

10% 50V X7R-CERM 1206

C3898 1

4.7UF 10% 50V X7R-CERM 1206

Max Current = 1.0A

T29BST:Y

C3896 1 2

C3897 4.7UF

10% 50V X7R-CERM 1206

T29BST:Y 1

4.7UF 10% 50V X7R-CERM 1206

2

7 8

Vout = 15.1V

T29BST:Y 1

4.7UF

R3896

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

= UVLO(falling) + (2uA * R1)

T29BST:Y 1

T29BST:Y

GND_T29BST_SGND

UVLO(falling) = 1.22 * (R1 + R2) / R2

PLACE_NEAR=C3895.1:2 mm

R38951

T29BST_FBX

31

GND

SGND

10% 6.3V CERM-X5R 402

C3888 10PF

2

C3894 0.33UF

UVLO(rising)

1

SYNC

T29BST:Y

1

41.2K 1% 1/20W MF 201

NC

FBX

R3894

10

T29BST:Y

36

1% 1/20W MF 201 2

T29BST_VC_RC

73.2K

Supervisor & CLKREQ# Isolation

2

1

1

T29BST_VSNS

1

NC

R3893

47PF 2

D

T29BST:Y

D3895

T29BST_SNS2

QFN

T29BST:Y

T29BST:Y

SOD-VESM-HF

C3899 0.001UF

2

2

10% 50V X7R 402

Vout = 1.6V * (1 + Ra / Rb)

C

no XW necessary.

=PP3V3_S0_T29PWRCTL =PP3V3_T29_RTR

T29BST:Y

7 34 35

6

C3800 1

=T29_RESET_L

SLG4AP016V

19

IN

T29_SW_RESET_L

16

OUT

T29_CLKREQ_L

2

SENSE

S

G

2

6 7

3

MR*

6

EN

8

OUT

2

R3887

4

IN

7

T29_RESET_L

OUT

34

IN

34

2

D

T29_CLKREQ_ISOL_L

SOT563

S

G

5

SMC_DELAYED_PWRGD

IN

25 41

MAKE_BASE=TRUE

THRM

GND

Q3888 SSM6N37FEAPE

5% 1/20W MF 201

4

=T29_CLKREQ_L

5% 1/20W MF 201

T29BST:Y 3

330K

RESET*

DLY = 60 ms +/- 20%

PAD

5

B

2

T29BST:Y

0.7V

(OD)

Pull-up provided by SB page.

Max Vgs: 10V T29BST_SHDN_DIV

DLY 2

R3888 330K

1

1

5% 1/20W MF 201

T29BST:Y 1

SOT563

5% 1/20W MF 201

PP1V05_T29

+ -

10K

Q3888 SSM6N37FEAPE

R3807

TDFN

R3803

D

100K

VDD

U3800

2

1

Open-Drain GPIO

1

CRITICAL

1

0.1UF 10% 16V X5R-CERM 0201

Platform (PCIe) Reset IN

5% 1/20W MF 201

2

T29BST_VC

T29BST:Y

25

U3890

1

0

2

SSM3K15FV

IN

T29BST:Y

LT3957 T29BST_INTVCC

R3889 1

1 8 2 3

SW

CRITICAL

T29BST_PWREN_L

65 64

9 0 2

VIN

150K

5% 1/20W MF 201

CRITICAL

T29BST:Y 7 2

1% 1/20W MF 201 2

R38811

T29BST_BOOST MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

2

200K

T29BST_PWREN_DIV_L

T29BST:Y

C3891 1

2 PIMB062D-SM

T29BST:Y

C3890 1 T29BST:Y

0.1UF 2

2

BOM options provided by this page: T29BST:Y - Stuffs 18V boost circuitry.

2

1% 1/4W MF 805

T29BST:Y

470K

- =T29_CLKREQ_L

7

1

CRITICAL

Vgs(th):

3

0.010

Changes required

Signal aliases required by this page:

C

2

T29 18V Boost Regulator

Vds(max): -30V

SI8409DB

=PPVIN_SW_T29BST 8-13V Input

- =PP3V3_S0_T29PWRCTL

D

4

SI8409DB:

9

B

3.3V T29 Switch U3810 7

TPS22924


CSP

A2 B2

VIN

=PP3V3_T29_FET A1

VOUT

Max Current = 1.7A (85C)

B1

U3810 & U3815/U3816

CRITICAL

C3810 1

C2

ON GND

1UF 10% 6.3V CERM 402

1 C

2

7

Part

TPS22924C

Type

Load Switch

R(on)

18 mOhm Typ 50 mOhm Max

Max Output: 2A per IC

1.05V T29 Switch U3815 7

TPS22924


CSP

A2 B2

VIN

C3815 1 1UF 10% 6.3V CERM 402

=PP1V05_T29_FET A1

VOUT

7

Max Current = 3.4A (85C)

B1

CRITICAL C2

ON GND

2

1 C

A


S YN C_ DA TE =0 1/ 10 /2 01 1

PAGE TITLE

T29 Power Support

U3816 TPS22924 CSP

A2 B2

VIN

DRAWING NUMBER A1

VOUT

Apple Inc.

B1

IN

T29_PWR_EN

Pull-up provided by SB page.

C2

ON

U3816.A2:

GND 1 C

PLACE_NEAR=U3815.B2:3 mm

051-8870

SIZE

D

REVISION

3.13.0

R

CRITICAL 19


BRANCH


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6

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3

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1

3V S3 WLAN FET MOSFET

TPCP8102

CHANNEL

P-TYPE

RDS(ON)

20-30 MOHM @2.5V

LOADING

0.750 A (EDP)

D

D CRITICAL

CRITICAL

Q4050

R4052

TPCP8102

0.020

AIRPORT

MIN_LINE_WI DTH=1 mm MIN_NECK_WI DTH=0.25 mm VOLTAGE=3.3V

6

PP3V3_WLAN_F 1

1% TH=1 mm 0.25W MIN_LINE_WID MIN_NECK_WID TH=0.25 mm MF-LF VOLTAGE=3.3V 805 2 PP3V3_WLAN_R

3

4

23V1K-SM 8 3 7 S

D

=PP3V3_S3_WLAN

2

6

C4021 1

1

G

C4020

10%

20% 10V 2 X5R 603

6.3V 2 X5R 201

SSD-K99

PLACEMENT_NOTE=Place close to Q4050.

F-RT-SM1

WIFI_EVENT_L

2

5% 1/20W MF 2201

R4050

P3V3WLAN_SS

2

1

100K 2

PM_WLAN_EN_L IN

62

5% 1/20W MF 201

10% 16V X5R-CERM 0201

PLACEMENT_NOTE=Place close to Q4050.

1

10K

10% 16V X5R 2 402

0.1UF 1

R4051

0.033UF

C4050

J4001

1

C4051 1

4

10UF

0.1UF

CRITICAL

7 37

1 5

6 41

OUT

3

ISNS_AIRPORT_P ISNS_AIRPORT_N

4 5

70 6

1

PCIE_AP_R2D_N

2

10% 6.3V

6

0.1UF 201 X5R

OUT

46 74

OUT

46 74

PLACEMENT_NOTE=Place close to J4001.

8

PLACEMENT_NOTE=Place close to J4001.

9 10

IN

16 70

C4030

7

C

PCIE_AP_R2D_C_N

70 6

C4031 1 2

PCIE_AP_R2D_P

11

0.1UF

10%

PCIE_AP_R2D_C_P

IN

16 70

PCIE_CLK100M_AP_N

IN

6 16 70

PCIE_CLK100M_AP_P

IN

6 16 70

OUT

6 16 70

OUT

6 16 70

OUT

6 17

C

6.3V X5R 201

12

13 14 15 16 17

PCIE_AP_D2R_P PCIE_AP_D2R_N

18

19 20

PCIE_WAKE_L

21

514S0335

BLUETOOTH

B

USB_BT_N USB_BT_P

=PP3V3_S3_BT 1

BI

6 24 69

BI

6 24 69

B

6 7

C4032 0.1UF

10% 6.3V 2 X5R 201

=PP3V3_S3_WLAN 7

37


DLY = 60 MS +/- 20%

C4053

1

0.1UF 10%

6.3V 2 X5R

1 CRITICAL

201

VDD

R40531

R40541

5% 1/20W MF 2012

1% 1/20W MF 201 2

100K

U4002 SLG4AP016V

232K

TDFN 2

SENSE

0.7V

+ -

P3V3WLAN_VMON 6

AP_RESET_CONN_L

RESET*

IN

25

AP_PWR_EN

IN

18 62

R4090

DLY 4

AP_RESET_L

AP_CLKREQ_L_R MR* 3

6

AP_CLKREQ_Q_L

7

R4055 100K

1% 1/20W MF 201 2

1

AP_CLKREQ_L

OUT

16 23

OUT 8

IN

(OD)

THRM

A

0

5% 1/20W MF 201

EN 6

1

2

PAD

GND

9

5

SYNC_MASTER=K21_MLB


PAGE TITLE

X21 WIRELESS CONNECTOR DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


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40 OF 109

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6

5

4

3

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1

D

D

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

1

C4501 0.1UF

CRITICAL

10% 16V 2 X5R-CERM 0201

R4599 0.003 1% 1W MF


SATA SSD C

6

PP3V3_S0_HDD_R

2

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=5V

CRITICAL

0612

4

1

=PP3V3_S0_HDD

7

3

ISNS_HDD_P

J4501

SSD-K99

ISNS_HDD_N

F-RT-SM1 1

C OUT

46 74

OUT

46 74

TP_SSD_RSRVD

2 3

GND_VOID=TRUE

4

69 6

GND_VOID=TRUE

C4516 1

SATA_HDD_D2R_C_P

5

0.01UF

2 10% 10V X5R

SATA_HDD_D2R_P

OUT

16 69

SATA_HDD_D2R_N

OUT

16 69

IN

16 69

IN

16 69

201

PLACE_NEAR=J4501.3:1.5MM PLACE_NEAR=J4501.4:1.5MM

6 7

69 6

GND_VOID=TRUE

8

C4515 1

SATA_HDD_D2R_C_N

0.01UF

GND_VOID=TRUE

2 10%10V

X5R 201

9 10 11


12 69 6

C4511 1

SATA_HDD_R2D_N

0.01UF 13 14 15

NC NC

69 6

C4510 1

SATA_HDD_R2D_P

0.01UF

1 0% 1 0V

SATA_HDD_R2D_C_N X5R

2

2 01

SATA_HDD_R2D_C_P

10% 10V X5R

201


16

R4510

17 18

2

SMC_HDD_OOB_TEMP_CONN

6

0

1

SMC_HDD_OOB_TEMP

2

41

5% 1/20W

MF

19

B

201

20

B

R4511

21 6

SMC_HDD_TEMP_CTL_CONN

1

0

2

SMC_HDD_TEMP_CTL

41

5% 1/20W

MF 201

A

SYNC_MASTER=K78_MLB


PAGE TITLE

SATA CONNECTOR DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

45 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D

USB Port Power Switch Right USB Port A

CRITICAL CRITICAL

U4600

L4605

TPS2561DR

FERR-120-OHM-3A

SON

C 24

2

OUT

USB_EXTA_OC_L

NC 62 40 6

4 EN1 5 EN2

USB_EN2 CRITICAL

1

1

10UF 20% 6.3V CERM-X5R 0402

1

C4691

2

2

C4696

1

1

PP5V_S3_RTUSB_A_ILIM MIN_LINE_WID TH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

NC

2

C

PP5V_S3_RTUSB_A_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

0603

C4605 1

USB_ILIM

CRITICAL

0.01UF 10% 16V X5R-CERM 0201

J4600

CRITICAL

2

USB-RIGHT-K99

L4600

F-RT-TH

90-OHM-100MA

5

DLP11S

SYM_VER-1

THRM PAD

1

R4601

20% 2 6.3V POLY-TANT CASE-B2-SM1

10% 16V X5R-CERM 0201

ILIM 7

GND

220UF-35MOHM

0.1UF

OUT1 OUT2 8

10 FAULT1* 6 FAULT2*

=USB_PWR_EN

C4690

9

IN_0 3 IN_1

=PP5V_S3_RTUSB

7

R46001 23.2K

1 1

1% 1/16W MF-LF 402

0 5% 1/20W MF 201

C4695

1

74

USB2_EXTA_MUXED_N

4

3

10UF

2

20% 6.3V CERM-X5R 0402

74USB2_LT1_N

2

74

USB2_EXTA_MUXED_P

1

2

74USB2_LT1_P

1

VBUS

2

D-

3

D+

4

GND

2 2

6

VBUS

1

GND

5

3

4

6

C O C O N I N I

Current limit (R4600): 2.3A max D4600 RCLAMP0502N SLP1210N6

CRITICAL We can add protection to 5V

if we want, but leaving NC for

now

Place L4605 at connector pin

B

B USB/SMC Debug Mux

7

=PP3V42_G3H_SMCUSBMUX SMC_DEBUG_YES

1

R4650

SMC_DEBUG_YES

C4650 1

10K 9

0.1UF 10% 16V X5R-CERM 43 42 41

6

0201

5

M+

IN

SMC_RX_L

4

M-

OUT

SMC_TX_L

69 24

BI

USB_EXTA_P

7

D+

69 24

BI

USB_EXTA_N

6

D-

43 42 41 6

5% 1/20W MF

VCC

2

U4650

2 201

Y+

1

Y-

2

PI3USB102ZLE TQFN

CRITICAL

SMC_DEBUG_YES 8

A

OE*

SEL

10

USB_DEBUGPRT_EN_L

GND

SEL=0 Choose SMC

3

SEL=1 Choose USB

IN

41

SMC_DEBUG_NO SYNC_MASTER=K21_MLB

R4651 1

0 5% 1/20W


PAGE TITLE

External USB Connectors

2

DRAWING NUMBER

SMC_DEBUG_NO

MF

Apple Inc.

R4652

201

1

0 5% 1/20W MF 201

2

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

46 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D

CRITICAL

J4700

AXK736327G 7 6

41 6 42 41 6

(Right Speaker Enable)

=PP3V42_G3H_ONEWIRE

F-ST-SM

=PP3V3_S0_AUDIO

SYS_ONEWIRE

1

2

OUT

SMC_BC_ACOK

3

4

5

6

USB_EXTD_N

7

8

BI

6 7

IN

=USB_PWR_EN

BI

6 24 69

OUT

SMC_LID

USB_EXTD_P

BI

6 24 69

44 6

BI

=I2C_LIO_SDA

9

10

44 6

IN

=I2C_LIO_SCL

11

12

USB_CAMERA_N

BI

6 18 69

13

14

USB_CAMERA_P

BI

6 18 69

15

16

17

62 39 6 49 42 41

C

37

6

18

HDA_SDOUT

44 6

IN

=I2C_MIKEY_SCL

19

20

HDA_BIT_CLK

44 6

BI

=I2C_MIKEY_SDA

21

22

23

24

IN

6 16 70

IN

6 16 70

HDA_SDIN0

OUT

OUT

6 16 70

19 6

IN

AUD_IPHS_SWITCH_EN

25

26

18 6

OUT

AUD_IP_PERIPHERAL_DET

27

28

USB_EXTD_OC_L

18 6

OUT

AUD_I2C_INT_L

29

30

HDA_RST_L

IN

6 16 70

51 6

HDA_SYNC

IN

6 16 70

OUT

AUD_GPIO_3

31

32

74 51 6

OUT

SPKRAMP_INR_N

33

34

74 51 6

OUT

SPKRAMP_INR_P

35

36

C4710 1

38

0.1UF

10% 16V X5R-CERM 2 0201

516S0862

6 24

=PP3V3R1V5_S0_AUDIO


1


C

C4700 0.1UF

10% 16V 2 X5R-CERM 0201

6 7


1

C4720 0.1UF

10% 16V 2 X5R-CERM 0201

B

B

A


S YN C_ DA TE =1 1/ 09 /2 01 0

PAGE TITLE

Left I/O (LIO) Connector DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

47 OF 109

A

8

7

NOTE: Unused pins have "SMC_Pxx" names.

www.laptopblue.vn

6

5

4

3

2

1

Unused

pins designed as outputs can be left floating, those designated as inputs require pull-ups. 42 42 7

PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC

C4902 1

C4903

1

1

0.1UF

22UF

20% 10V X5R-CERM 805

2

C4904

1

0.1UF

20% 10V CERM 402

2

20% 10V CERM 402

2

C4905

1

0.1UF 2

C4906 0.1UF

20% 10V CERM 402

2

20% 10V CERM 402

D

BYPASS=U4900.E1:D2:3 mm

D

PLACE_NEAR=U4900.M12:3mm

R4999 4.7

1

2

62 52 25 23 62

P10

L13

A13

DF2117RVPLP20HV

P60

SMC_RSTGATE_L

P11

TLP-145V

P61

K12

IN

ALL_SYS_PWRGD

A12

P12

(1 OF 3)

P62

K11

IN

S5_PWRGD

B13

P13

P63

J12

D11

P14

P64

K13

C13

P15

P65

J10

SMC_P10

NC

17

OUT

36 25

OUT

SMC_DELAYED_PWRGD

C12

P16

P66

J11

23 17

OUT

PM_PWRBTN_L

D10

P17

P67

H12

SMC_P20

42

SMC_P24

42

SMC_P26

NC NC NC NC

IN

42

SMC_BIL_BUTTON_L

IN

42

N10

SMC_ADC0

IN

42

P71

M11

SMC_ADC1

IN

42

P72

L10

SMC_ADC2

IN

42

P73

N11

SMC_ADC3

IN

42

E13

P24

P74

N12

SMC_ADC4

IN

42

E12

P25

P75

M13

SMC_ADC5

IN

42

F13

P26

P76

N13

SMC_ADC6

IN

42

SMC_ADC7

IN

42

P27

P77

LPC_AD<0>

A9

P30

P80

A7

BI

LPC_AD<1>

D9

P31

P81

B6

BI

LPC_AD<2>

C8

P32

P82

C7

6

BI

NC

SMC_SCI_L

OUT

16 19

PM_CLKRUN_L

OUT

6 17 43

IN

6 17 43

LPC_AD<3>

B7

P33

P83

D5

6

IN

LPC_FRAME_L

A8

P34

P84

A6

IN

SMC_LRESET_L

D8

P35

P85

B5

IN

LPC_CLK33M_SMC

D7

P36

P86

C6

BI

LPC_SERIRQ

D6

P37

P90

J4

SMC_ONOFF_L

IN

6 42 49

OUT

SMC_HDD_TEMP_CTL

D4

P40

P91

G3

SMC_BC_ACOK

IN

6 40 42

IN

SMC_HDD_OOB_TEMP

A5

P41

P92

H2

SMC_PME_S4_WAKE_L

IN

6 42 49

B4

P42

P93

G1

PM_SLP_S3_L

IN

17 26 62

A1

P43

P94

H4

PM_SLP_S4_L

IN

17 26 49 62

C2

P44

P95

G4

PM_SLP_S5_L

IN

17 62

B2

P45

P96

F4

SMC_CLK32K

IN

42

C1

P46

P97

F1

43 16 6

38 38 44

BI

SMB_MGMT_DATA 42

(OC)

SMC_P43

NC NC

OUT

SMC_GFX_THROTTLE_L

49

OUT

SMC_SYS_KBDLED

C3

P47

6

OUT

SMC_TX_L

G2

P50

IN

SMC_RX_L

F3

P51

E4

P52

42

6 44

BI

SMB_0_S0_CLK

(OC)

SMC_PA0_PU

U4900

(OC)

N3

PA0

16

OUT

SPI_DESCRIPTOR_OVERRIDE_L

PA1

OUT

PM_SYSRST_L

(OC) (OC)

N1

25 17

M3

PA2

39

OUT

USB_DEBUGPRT_EN_L

(OC)

M2

PA3

42

BI

MEM_EVENT_L

(OC)

N2

37 6

BI

WIFI_EVENT_L

(OC)

40 6

BI

SYS_ONEWIRE

OUT

SMC_BATLOW_L

42

62 42

42 19

OUT

62 42

OUT

SMC_RUNTIME_SCI_L SMC_S4_WAKESRC_EN 42

LPC_PWRDWN_L

(OC)

(OC)

SMC_TX_L

OUT

6 39 41 42 43

SMC_RX_L

IN

6 39 41 42 43

SMB_MGMT_CLK

BI

SMB_0_S0_DATA

BI

PE0

K1

SMC_CASE_OPEN

PE1

J3

SMC_TCK

PE2

K2

SMC_TDI

PE3

J1

SMC_TDO

PA4

PE4

K4

SMC_TMS

IN

6 42 43

L1

PA5

PF0

K5

G3_POWERON_L

IN

42

(OC)

K3

PA6

(OC)

L2

PF1

N5

PF2

M6

SMC_LID

IN

6 40 42 49

IN

42

NC NC

SMC_PB4

NC

PA7

B8

PB0

PF3

L5

C9

PB1

PF4

M5

B9

PB2

PF5

N4

A10

PB3

PF6

L4

C10

PB4

PF7

M4

B10

PB5

PG0

M8

PG1

N7

NC

IN

42

IN

6 42 43

IN

6 42 43

OUT

6 42 43

VCL AVREF

R4909

U4900

NC

E5

5% 1/20W MF 201

2

OMIT_TABLE 53 43 42

6

SMC_RESET_L

D3

RES*

42

SMC_XTAL

A3

XTAL

42

SMC_EXTAL

A2

EXTAL

IN

MD1

D1

MD2

H1

NMI

E3

ETRST*

H3

AVSS

L9

R4901 10K

2

5% 1/20W MF 201

SMC_MD1

IN

6 43

SMC_NMI

IN

6 43

SMC_TRST_L

IN

6 43

NO STUFF 1

1

R4902

R4998

10K 0 1 5 1 1 C F B

1

SMC_KBC_MDE

VSS 2 3 D L

1

10K

NC

10K

5% 1/20W MF

XW4900 SM

5% 1/20W MF

2 201

2 201

1

R4903 0 5% 1/20W MF

2 201

1

C

PLACE_NEAR=U4900.L3:4mm

GND_SMC_AVSS

42 45 46

B

SMC_PF5

42

NC NC NC

IN

SMC_DP_HPD_L

C11

PB6

42

IN

SMC_GFX_OVERTEMP_L

A11

PB7

PG2

K8

(OC)

BI

44

OUT

SMC_FAN_0_CTL

G11

PC0

PG3

K7

SMB_BSA_CLK

BI

44

42

OUT

SMC_FAN_1_CTL

G13

PC1

PG4

K6

(OC) (OC)

SMB_A_S3_DATA

BI

44

42

OUT

SMC_FAN_2_CTL

F12

PC2

PG5

N6

(OC)

SMB_A_S3_CLK

BI

44

42

OUT

SMC_FAN_3_CTL

H13

PC3

PG6

M7

(OC)

SMB_B_S0_DATA

48

IN

SMC_FAN_0_TACH

G10

PC4

PG7

L6

(OC)

SMB_B_S0_CLK

42

IN

SMC_FAN_1_TACH

G12

PC5

E2

H11

PC6

SMC_PROCHOT

OUT

42

IN

SMC_FAN_2_TACH

PH0

42

OUT

42

IN

J13

SMC_THRMTRIP

42

SMC_FAN_3_TACH

PH1

F2

PH2

J2

42

IN

SMC_ADC8

M10

PD0

PECI/PH3

A4

42

IN

SMC_ADC9

N9

PD1

PEVREF/PH4

B3

PVCCIO_S0_SMC_R

42

IN

SMC_ADC10

K10

PD2

PEVSTP/PH5

C4

PM_PECI_PWRGD_R

42

IN

SMC_ADC11

L8

PD3

42

IN

SMC_ADC12

M9

PD4

42

IN

SMC_ADC13

N8

PD5

C4910 1

42

IN

SMC_ADC14

K9

PD6

0.1UF

42

IN

SMC_ADC15

L7

PD7

PC7

VCC

NC NC

48

42

AVCC

2

44

TLP-145V

OMIT_TABLE

20% 4V 2 CERM-X5R-1 201

44

DF2117RVPLP20HV (2 OF 3)

20% 10V CERM 402

2

25 70 25

A

SMC_PROCHOT_3_3_L

P70

BI

43 42 41 39

OUT

P23

6

0.47UF

1 1 L

1 E

0.1UF

17 42 62

P22

6

0 1 H

(3 OF 3)

SMC_ADAPTER_EN

P21

6

1 1 B M

TLP-145V

P20

E10

C4920

2 1 M

1

DF2117RVPLP20HV

F11

70 43 16

43 42 41 39

NC

C4907 1

62

D12

70 43 16

70 43 16

NC NC NC

OUT

E11

70 43 16

70 43 16

SMC_PM_G2_EN

D13

L12

NC

B

OMIT_TABLE

PM_DSW_PWRGD

42

C

U4900

B12

OUT

42 42

SMC_VCL

PLACE_NEAR=U4900.M12:3mm

PP3V3_S5_SMC_AVCC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=3.3V

5% 1/20W MF 201

NC

=SMC_SMS_INT SMB_BSA_DATA

BI BI

CPU_PECI_R

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

44 44

R4910 1

43

2

CPU_PECI

10 19 67

5% 1/20W MF 201

R4911

20% 10V CERM 402

1

0

2

=PPVCCIO_S0_SMC

7

5% 1/20W MF 201

2


1

0 5% 1/20W MF 201

S YN C_ DA TE =0 1/ 10 /2 01 1

PAGE TITLE

SMC

R4912 2

DRAWING NUMBER

PM_PECI_PWRGD

Apple Inc.

62

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

49 OF 109

A

8

7

www.laptopblue.vn

6

5

SMC Reset "Button", Supervisor & AVREF Supply 42 41 7

7

41

41

SMC_FAN_2_TACH

41

SMC_FAN_3_CTL

41

SMC_FAN_3_TACH

=PPVIN_S5_SMCVREF

10% 6.3V CERM-X5R 402

1

MR1*

(IPU) SN0903048

IN

7

MR2*

(IPU)

SMC_MANUAL_RST_L

4

RESET*

=PP3V3_S0_SMC

NC_SMC_FAN_3_TACH

REFOUT THRM

GND

41

C5001 1 10% 10V X5R 201

SMC_RESET_L

OUT

2

6 40 41 42

SMS_INT_L

SMC_ADC0

41

SMC_ADC1

41

SMC_ADC2

2

45

SILK_PART=SMC_RST

2

41

SMC_ADC3

SMC_DCIN_ISENSE

D

46

MAKE_BASE=TRUE

C5026

41

IN

41

IN

41

D

41

SMC_ADC4

41

SMC_ADC5

41

SMC_ADC6

Q5060 DMB53D0UV

SMC_GFX_VSENSE

45

2

CPU_PROCHOT_BUF

SMC_GFX_ISENSE

SOT-563

G

45

SMC_1V5S3_ISENSE

TO CPU

46

R5062

MAKE_BASE=TRUE 41

SMC_ADC7

41

SMC_ADC8

41

SMC_ADC9

SMC_CPUVCCIO_ISENSE

41

SMC_ADC10

41

SMC_ADC11

45

67 57 10

MAKE_BASE=TRUE 41 45 46


MR1* and MR2* must both be low to cause manual reset.

OUT

MAKE_BASE=TRUE

10% 10V X5R 201

GND_SMC_AVSS

PLACEMENT_NOTE=Place R5001 on BOTTOM side

TO SMC

6

45

MAKE_BASE=TRUE

0.01UF 2

5% 1/20W MF 201

45

SMC_DCIN_VSENSE

MAKE_BASE=TRUE 1

10uF 20% 6.3V X5R 603

2

SMC_PROCHOT_3_3_L

SMC_CPU_ISENSE

41


C5025 1

R5060 10K

5% 1/20W MF 201

MAKE_BASE=TRUE

9

2

1

R5061 100K

42

SMC_CPU_VSENSE

6 41 43 53

PAD

0.01UF

5% 1/10W MF-LF 603

1

SMC_BC_ACOK

=SMC_SMS_INT

MAKE_BASE=TRUE

5

8

=CHGR_ACOK

MAKE_BASE=TRUE

PP3V3_S5_AVREF_SMC

DELAY

OMIT

2

2

41

5% 1/20W MF 201

DFN

6

SMC_ONOFF_L

0

42 7

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

100K

VREF-3.3V-VDET-3.0V

SMC_TPAD_RST_L

R5001

R5000

U5010

2

53 45

1

3

VIN

V+

IN

1

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

0.47UF

6

1

MAKE_BASE=TRUE

C5020 1

49 6

2 PROCHOT Level Shifting to 3V3

MAKE_BASE=TRUE

=PP3V3_S5_SMC

Mobiles: 3.42V

49 42 41

3

NC_SMC_FAN_2_CTL MAKE_BASE=TRUE

Desktops: 5V

D

4

SMC_FAN_2_CTL

SMC_LCDBKLT_ISENSE

BI

CPU_PROCHOT_L

3.3K

1

46

6

MAKE_BASE=TRUE

Used on mobiles to support SMC reset via keyboard.

SMC_HDD_ISENSE SMC_PBUS_VSENSE

Q5060

5

S

DMB53D0UV 1

SOT-563 4

D

Q5059

S

G

SSM6N37FEAPE

46

SOT563

MAKE_BASE=TRUE

NOTE: Internal pull-ups are to VIN, not V+.

CPU_PROCHOT_L_R

2

5% 1/20W MF 201

46

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

3

45

MAKE_BASE=TRUE 41

SMC_ADC12

SMC_BMON_ISENSE

46

1

MAKE_BASE=TRUE

2

SMC_PROCHOT

41

SMC_ADC13

41

SMC_ADC15

41

SMC_P10

41

SMC_P20

TP_SMC_ADC13 MAKE_BASE=TRUE

19

TP_SMC_ADC15

OUT

PM_THRMTRIP_L_R

MAKE_BASE=TRUE

Debug Power "Buttons"

TP_SMC_P10

3

MAKE_BASE=TRUE

D

Q5059

S

G

SSM6N37FEAPE

TP_SMC_P20

SOT563

MAKE_BASE=TRUE

SMC_ONOFF_L OMIT

C

R5016 PLACE_SIDE=BOTTOM

6 41 42 49

41

1

1

41

R5015

2

SILK_PART=PWR_BTN

TP_SMC_P24

SMC_P26

SMC_BMON_MUX_SEL

46

4

MAKE_BASE=TRUE

0

2

SMC_P24

MAKE_BASE=TRUE

OMIT

0 5% 1/10W MF-LF 603

OUT

PLACE_SIDE=TOP 5% 1/10W MF-LF 603

41

SMC_P43

41

SMC_PF5

C

5

TP_SMC_P43

SMC_THRMTRIP

MAKE_BASE=TRUE

Check with SMC pullup S0=PP3V3_S0_SMC

TP_SMC_PF5 MAKE_BASE=TRUE

SILK_PART=PWR_BTN

41

SMC_RSTGATE_L

42 7

TP_SMC_RSTGATE_L MAKE_BASE=TRUE

41

R5075

MEM_EVENT_L

10K

1

2 5%

42 41 7

R5012 17

IN

PLACE_NEAR=U1800.N14:5.1mm

PM_CLK32K_SUSCLK_R

1

22

2

SMC_CLK32K

OUT

41

49 42 41

5% 1/20W MF 201

=PP3V3_S4_SMC

41

SMC_XTAL

1

NO STUFF 1

R5011 1M

B 2 41

SMC_EXTAL

5% 1/20W MF 201

0 5% 1/20W MF 201

2

15PF SMC_XTAL_R CRITICAL

1

4

20MHZ

SM-2.5X2.0MM

1

43 41 39

6

SMC_RX_L

43 41 6

SMC_TDO

R5020

43 41 6

SMC_TDI

100K

43 41 6

SMC_TCK

41

=PP3V3_S4_SMC

7 42

42 41 40

2 5% 25V NPO 201

3

Y5010

SMC_TX_L

SMC_TMS

SMC_DP_HPD_L

NC 2 NC

SMC_LID

43 41 6

5% 1/20W MF 2 201

C5010

R5010

Q5020

41

2

2

1

2

1

2

100K

1

2

10K

1

2

10K

1

2

10K

1

2

10K

1

2

10K

1

2

470K

1

2

10K

1

2

42 41 41 19

MAKE_BASE=TRUE

G

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

NOSTUFF

5% 1/20W MF 201

SMC_PME_S4_WAKE_L

2

IN

SMS_INT_L

2

1

10K

100K

15PF

64

SMC_BC_ACOK

1

10K

R5076

D 3

SSM3K15FV

1

SMC_BIL_BUTTON_L

R5077 R5078 R5079 R5080 R5081 R5087 R5093

10K

100K

1

C5011

5% 25V NPO 201

6 42

OUT

SOD-VESM-HF

1

G3_POWERON_L

6

7 42

R5070 R5072 R5071 R5073 R5074

SMC_ONOFF_L

6

43 41 39

1

SMC Crystal Circuit

6 41

49 41 40

MF

1/20W

=PP3V3_S5_SMC

SMC_PA0_PU SMC_RUNTIME_SCI_L

R5091 R5094

100K 100K

1 1

2 2

B

NOSTUFF

OUT

6 41 49

S 2 62 41 17

DP_A_EXT_HPD

SMC_ADAPTER_EN

41

SMC_CASE_OPEN

41

SMC_PB4

62 41

SMC_S4_WAKESRC_EN

R5085 R5086

10K

1

2

10K

1

2

R5088 R5090

10K

1

2

100K

1

2

BATLOW# Isolation 7

=PP3V3_S5_SMCBATLOW

1

R5040 100K

5% 1/20W MF 201

A

62 41

IN

=PP3V3_SUS_SMC 7 CRITICAL

Below connections are different from K91

Q5040

2

SMC_PA0_PU

HISIDE_ISENSE_OC

46

MAKE_BASE=TRUE

G

SOD-VESM-HF

41

SMC_FAN_1_CTL

41

SMC_FAN_1_TACH

NC_SMC_FAN_1_CTL MAKE_BASE=TRUE

D

SMC_BATLOW_L

42 41

1

SSM3K15FV

S

3

2

PM_BATLOW_L

OUT

NC_SMC_FAN_1_TACH MAKE_BASE=TRUE

17

SYNC_MASTER=K78_MLB

1

0

5% 1/20W MF 201


PAGE TITLE

SMC Support

R5041 2

41

SMC_ADC14

41

SMC_GFX_THROTTLE_L

SMC_HS_COMPUTING_ISENSE

DRAWING NUMBER 46

MAKE_BASE=TRUE

NOSTUFF

Apple Inc.

TP_SMC_GFX_THROTTLE_L MAKE_BASE=TRUE

=PP3V3_S5_SMC

Internal 20K pull-up on PM_BATLOW_L in PCH. 41

SMC_GFX_OVERTEMP_L

R5095

10K

1

051-8870

2 5%

1/20W

MF

201

SIZE

D

REVISION

3.13.0

R 42 41 7


BRANCH


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50 OF 109

A

8

7

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6

5

D

4

3

2

1

D

LPC+SPI Connector CRITICAL LPCPLUS

J5100

55909-0374 M-ST-SM 7 6

=PP3V3_S5_LPCPLUS

7 6

=PP5V_S0_LPCPLUS

31

32

2

LPC_CLK33M_LPCPLUS

LPC_AD<0>

3

4

LPC_AD<2>

LPC_AD<1>

5

6

LPC_AD<3>

7

8

9

10

SPIROM_USE_MLB SPI_ALT_CLK

1 70 41 16 6

BI

70 41 16 6

BI

43 6 43 6

SPI_ALT_MOSI

IN OUT

SPI_ALT_MISO

11

12

IN

6 25 70 6 16 41 70

BI

6 16 41 70

BI

6 19 50

OUT IN

6 43

IN

6 43

IN

LPC_FRAME_L

13

14

SPI_ALT_CS_L

41 17 6

OUT

PM_CLKRUN_L

15

16

LPC_SERIRQ

42 41 6

OUT

SMC_TMS

17

18

LPC_PWRDWN_L

IN

6 17 41

IN

LPCPLUS_RESET_L

19

20

SMC_TDI

OUT

6 41 42

OUT

SMC_TDO

21

22

SMC_TCK

OUT

6 41 42

41 6

IN

SMC_TRST_L

23

24

SMC_RESET_L

OUT

6 41 42 53

41 6

OUT

SMC_MD1

25

26

SMC_NMI

OUT

6 41

IN

SMC_TX_L

27

28

SMC_RX_L

OUT

6 39 41 42

29

30

LPCPLUS_GPIO

OUT

6 19

70 41 16 6

25 6 42 41 6

42 41 39 6

C

33

6 16 41

BI

C

34

516S0573

SPI Bus Series Termination

LPCPLUS

LPCPLUS

R5128

R5127

1

IN

B

SPI_CS0_R_L

1

R5111

PLACE_NEAR=U1800.AD12:5mm 70 16

IN

SPI_CLK_R

PLACE_NEAR=U1800.W8:5mm 70 16

IN

SPI_MOSI_R

1

R5112 1

15

5% 1/20W MF 201 70 16

OUT

SPI_MISO

2

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

15

2

15

2

6 43

SPI_ALT_CLK

6 43

SPI_ALT_CS_L

5% 1/20W MF 201

R5125

6 43

1

PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm

47

2

5% 1/20W MF 201

R5120 70

SPI_CS0_L

1

5% 1/20W MF 201 70

SPI_CLK

1

5% 1/20W MF 201

R5122 70

SPI_MOSI

1

R5123 1

15

47

5% 1/20W MF 201

47

2

SPI_MLB_CS_L

OUT

50 70

OUT

50 70

SPI_MLB_MOSI

OUT

50 70

SPI_MLB_MISO

IN

50 70


B SPI_MLB_CLK

2

5% 1/20W MF 201

47

5% 1/20W MF 201

R5121

5% 1/20W MF 201

A

2

47

R5110

PLACE_NEAR=U1800.AB8:5mm 70 16

1

47

6 43

SPI_ALT_MOSI

LPCPLUS

R5126

1

0

2

LPCPLUS

SPI_ALT_MISO


2 PLACE_NEAR=R5127.2:5mm

2 PLACE_NEAR=U6100.2:5mm


S YN C_ DA TE =0 1/ 10 /2 01 1

PAGE TITLE

LPC+SPI Debug Connector DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


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51 OF 109

A

8

7

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6

5

4

PCH SMBus "0" Connections 44 7

=PP3V3_S0_SMBUS_PCH

1K

5% 1/20W MF 201

U1800 (MASTER)

D

SMBUS_PCH_CLK

2

R5201

2

5% 1/20W MF 201

R52501

SMC

LED BACKLIGHT

1K

5% 1/20W MF 201

U4900 (MASTER)

66

41

1

R5251

4.7K

U9701 (WRITE: 0x58 READ: 0x59)

=I2C_BKL_1_SCL

SMB_0_S0_CLK

73

Internal DP

4.7K

2

2

R52801

SMC

=I2C_TCON_SCL

SMBUS_SMC_0_S0_SCL

5% 1/20W MF 201

U4900

(See Table)

(MASTER)

63

41

=I2C_BKL_1_SDA

66

41

SMB_0_S0_DATA

73

MAKE_BASE=TRUE

1

R5281

2.0K

J9000

5% 1/20W MF 201

SMB_BSA_CLK

73

MAKE_BASE=TRUE

SMBUS_PCH_DATA

1

7 =PP3V42_G3H_SMBUS_SMC_BSA

1


2 SMC "Battery A" SMBus Connections

7 =PP3V3_S0_SMBUS_SMC_0_S0

R52001

Cougar-Point

70 16

3

SMC "0" SMBus Connections

Battery Charger

2.0K

2

2

5% 1/20W MF 201

ISL6258 - U7000 (Write: 0x12 Read: 0x13)

SMBUS_SMC_BSA_SCL

=SMBUS_CHGR_SCL

=I2C_TCON_SDA

SMBUS_SMC_0_S0_SDA

63

41

SMB_BSA_DATA

73

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

=SMBUS_CHGR_SDA

53

MAKE_BASE=TRUE

VRef DACs

Battery

U3300

J6955

Battery

(Write: 0x98 Read: 0x99) 31

D

53

MAKE_BASE=TRUE

(See Table)

Battery Manager - (Write: 0x16 Read: 0x17)

=I2C_VREFDACS_SCL

=SMBUS_BATT_SCL

6 52

=SMBUS_BATT_SDA

6 52

Battery LED Driver - (Write: 0x36 Read: 0x37) 31

=I2C_VREFDACS_SDA

Battery Temp - (Write: 0x90 Read: 0x91)

Margin Control

SMC "Management" SMBus Connections

U3301

(* = Multiple options)

(Write: 0x30 Read: 0x31) 31

31

=I2C_PCA9557D_SCL

Internal DP

=I2C_PCA9557D_SDA

K21 Samsung

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88)

N

7 =PP3V3_S3_SMBUS_SMC_MGMT

K78

LGD Y

Samsung *

LGD

AUO

Y

*

Parade T-con

- (0x10-0x1F or 0x30-0x3F)

Y

N

*

N

*

DVR

- (Write: 0x4E Read: 0x4F)

Y

Y

Y

Y

N

Trackpad

U6800

(MASTER) =SMBUS_XDP_SCL

23

=SMBUS_XDP_SDA

SMB_MGMT_CLK

73

41

SMB_MGMT_DATA

73

5% 1/16W MF-LF 2 402

SMBUS_SMC_MGMT_SCL

=I2C_TPAD_SCL

6 49

=I2C_TPAD_SDA

6 49

C

MAKE_BASE=TRUE

=I2C_MIKEY_SCL

6 40

=I2C_MIKEY_SDA

6 40

SMC "A" SMBus Connections

J2600 & J2650

23

41

(Write: 0x72 Read: 0x73)

XDP Connectors

(Write: 0x90 Read: 0x91)

2.0K

5% 1/16W MF-LF 402 2

(MASTER)

J5700

R5291

1

2.0K

U4900

Mikey

C

R52901

SMC

NOTE: SMC RMT bus remains powered and may be active in

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

S3 state

T29 & Inlet Temp

7 =PP3V3_S3_SMBUS_SMC_A_S3

EMC1704: U5400 (Write: 0x98 Read: 0x99)

R52701

SMC

1K

SMB_A_S3_CLK

41

SMB_A_S3_DATA

1K

5% 1/20W MF 201 2

U4900 (MASTER)

41

R5271

1

73

5% 1/20W MF

2 201

Left I/O Board J4700

=I2C_T29_INLET_THMSNS_SCL

46

=I2C_T29_INLET_THMSNS_SDA

46

(See Table)

SMBUS_SMC_A_S3_SCL

=I2C_LIO_SCL

6 40

SMBUS_SMC_A_S3_SDA

=I2C_LIO_SDA

6 40

MAKE_BASE=TRUE 73

T29 I2C Connections

MAKE_BASE=TRUE

Left I/O Board ALS

- (write: 0x72 Read: 0x73)

7

=PP3V3_S0_T29I2C

Finstack Temp - (Write: 0x92 Read: 0x93) Microcontroller abstracts

R52301 5% 1/20W MF 201

U3600 (MASTER)

B

R5231

4 .7 K

2

2

T29 Plug uC

5% 1/20W MF 201

U9330 (Write: 0xA0 Read: 0xA1)

I2C_T29_SDA

72 34

PCH "SMLink 0" Connections

actual CDR(s) in plug.

1

4 .7 K

T29 IC

=I2C_T29AMCU_SDA

64

=I2C_T29AMCU_SCL

64

B

MAKE_BASE=TRUE

I2C_T29_SCL

72 34

MAKE_BASE=TRUE 44 7

=PP3V3_S0_SMBUS_PCH

SDRVI2C:MCU

R52101

Cougar-Point

8.2K 5% 1/20W MF 201

U1800 (MASTER)

70 16

2

R52341

R5211

R5235 0

5% 1/20W MF 201 2

8.2K

2

1

0

1

5% 1/20W MF 201

5% 1/20W MF 2 201

For Compliance Testing SDRVI2C:SB

SML_PCH_0_CLK MAKE_BASE=TRUE

70 16

SDRVI2C:MCU

R5236

0

R5237

0

1

5% MF

MAKE_BASE=TRUE

DP Re-driver

I2C_DPSDRVA_SCL

2

SML_PCH_0_DATA

1/20W 201

MAKE_BASE=TRUE

U9310 (Write: 0x94 Read: 0x95)

SDRVI2C:SB

SMC "B" SMBus Connections

1

I2C_DPSDRVA_SDA

2 5% MF

1/20W 201

MAKE_BASE=TRUE

7 =PP3V3_S0_SMBUS_SMC_B_S0

=I2C_DPSDRVA_SCL

64

=I2C_DPSDRVA_SDA

64

PCH "SMLink 1" Connections 1

44 7

R5260

SMC

=PP3V3_S0_SMBUS_PCH

4.7K

5% 1/20W MF 201

U4900 NO STUFF

Cougar-Point

A

U1800 (Write: 0x88 Read: 0x89)

70 16

SML_PCH_1_CLK

R52201 8.2K 5% 1/20W MF 201

2

NO STUFF

(MASTER)

1

R5221 8.2K

2

5% 1/20W MF 201

R5223 0

1

5% 1/20W MF 201

41

SMB_B_S0_CLK

73

SMBUS_SMC_B_S0_SCL

2

1

R5261 4.7K

2

5% 1/20W MF 201

CPU Temp EMC1414-A: U5570 (Write: 0x98 Read: 0x99) =I2C_CPUTHMSNS_SCL

47

=I2C_CPUTHMSNS_SDA

47

MAKE_BASE=TRUE 41

SMB_B_S0_DATA

73

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SYNC_MASTER=K78_MLB


PAGE TITLE 2

SMBus Connections


SML_PCH_1_DATA MAKE_BASE=TRUE

1

2

DRAWING NUMBER

R5222

Apple Inc.

0

SMLink 1 is slave port to access PCH & CPU via PECI.

5% 1/20W MF 201

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

52 OF 109

A

8

7

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6

5

4

PBUS Voltage Sense Enable & Filter

3

2

CPU VCore Load Side Current Sense / Filter =PP3V3_S0_IMVPISNS

7

Q5300

PLACE_NEAR=U5340.8:3MM 1

NTUD3169CZ PBUSVSENS_EN_L

6

D

D

62

=PBUSVSENS_EN

IN

1% 1/20W MF 201

74 58 57

Max VOut: 3.3V at 19.77V Input

D

7

1% 1/20W MF 201 2

4

SMC_PBUS_VSENSE

R5304

1% 1/20W MF 201 2

5.49K

1% 1/20W MF 201 2

PBUSVSENS_EN_L_DIV

487K

C5304

201

41 42 45 46

EDP: 33A

GND_SMC_AVSS

1/16W MF

470PF 1

41 42 45 46

Gain:110.181x

2

0.1%

C5345

Sense R is R7510 Sense R is 0.75mOhm

GND_SMC_AVSS

487K

NOSTUFF

1/16W MF 20402

X5R-X7R 2

0.22UF

C5341 0.22UF

1

0.1%

42

PLACE_NEAR=U4900.M11:5MM 1

R5345

R5344

470PF

OUT

20% 6.3V 2 X5R 0201

1

C5344 1

42

10% 16V

20% 6.3V 2 X5R 0201

4

9

CPUIMVP_ISUM_R_N

SMC_CPU_ISENSE

2

1% 1/20W MF 201

0402

NOSTUFF

OUT

4.53K

1

CPUIMVP_ISUM_IOUT

VTHRM

74

1

1/16W MF

PLACE_NEAR=U4900.L8:5MM 1

2

PLACE_NEAR=U4900.M11:5MM

R5341

DFN

V+

2

0.1%

RTHEVENIN = 4573 Ohms


1

OPA2333

8 3

4.42K

CPUIMVP_ISNS1_N

PLACE_NEAR=U4900.L8:5MM

P-CHANNEL

100K

IN

D

U5340

CPUIMVP_ISUM_R_P

74

R5343 74 58

27.4K

R53011

2

0.1%

1/16W MF

R53031

S

=PPBUS_S0_VSENSE

4.42K

1

CPUIMVP_ISNS1_P

0402 PLACE_NEAR=R7510.4:5MM

G

5

IN

2

PBUS_S0_VSENSE

3

CRITICAL

R5342

100K

S

1

10% 2 6.3V X5R 201

PLACE_NEAR=R7510.3:5MM

R53021

G

2

Enables PBUS VSense divider when in S0.

C5340 0.1UF

SOT-963

N-CHANNEL

1

SIGNAL_MODEL=EMPTY

0402

Scale: 12.1A / V Max VOut: 2.73V at 39.934A

2

10% SIGNAL_MODEL=EMPTY 16V X5R-X7R 201

TDP :28.05A

GFX/IG VCore Load Side Current Sense / Filter

C

C

DC-In Voltage Sense Enable & Filter CRITICAL

NTUD3169CZ

74 58

SOT-963

N-CHANNEL

6

IN

CPUIMVP_ISNS1G_P

IN

=CHGR_ACOK

100K 1% 1/20W MF 201

S 1

divider when AC present.

3

74 58

1% 1/20W MF 201

1

1% 1/20W MF 201

PDCINVSENS_EN_L_DIV

NOSTUFF

715K 0.1%

OUT

1/16W MF 402

470PF 1

715K 0.1%

C5355

1/16W MF 2 402

201

42

C5351 0.22UF

GND_SMC_AVSS

2

SIGNAL_MODEL=EMPTY

41 42 45 46

Gain:161.765x Scale: 8.24A / V Max VOut: 2.18V at 27.2A

2

10% SIGNAL_MODEL=EMPTY 16V X5R-X7R 201

42

PLACE_NEAR=U4900.N9:5MM 1

5.49K 2

R5354

OUT

PLACE_NEAR=U4900.M13:5MM 1

20% 6.3V 2 X5R 0201

1

1

X5R-X7R

SMC_DCIN_VSENSE

R5314

4

R5355

NOSTUFF Sense R is R7550 C5354 1 Sense R is 0.75mOhm 470PF 10% EDP: 18A TDP: 15.3A 16V 2

RTHEVENIN = 4573 Ohms

PLACE_NEAR=U4900.N9:5MM

SMC_GFX_ISENSE

2

1% 1/20W MF 201

9

CPUIMVP_ISUMG_R_N

74

4.53K

1

0.1%


P-CHANNEL 1

100K 1% 1/20W MF 201

THRM

1/16W MF

27.4K S

4

R5311

4.42K2

1


R5351

CPUIMVP_ISUMG_IOUT

7

V-

0402

G

5

CPUIMVP_ISNS1G_N

Max VOut: 3.3V at 19.77V Input

R5313 1 =PPDCIN_S5_VSENSE

IN

2

DCIN_S5_VSENSE

D

7

V+

6

R5353

1

OPA2333 DFN

5

0402

G

2

8

CPUIMVP_ISUMG_R_P

74

0.1%

1/16W MF

R5312

Enables DC-In VSense

4.42K2

1

DCINVSENS_EN_L

D

53 42

U5340

R5352

Q5310

C5314 0.22UF

2

20% 6.3V 2 X5R 0201

GND_SMC_AVSS

B

B

41 42 45 46

CPU 1.05V VCCIO Current Sense / Filter CPU Vcore Voltage Sense / Filter XW5320 =PPCPUVCORE_S0_VSENSE

1

2

=PP3V3_S0_CPUVCCIOISNS

R5320

SM

7

7

CPUVSENSE_IN

VCCIOISNS_ENG

4.53K2

SMC_CPU_VSENSE

1

1% 1/20W MF 201

PLACE_NEAR=R7510.2:5 MM

OUT

20% 6.3V 2 X5R 0201

GND_SMC_AVSS

74 59

10% 2 6.3V X5R 201

U5360


INA210

IN

CPUVCCIOS0_CS_N

5 IN-

IN

CPUVCCIOS0_CS_P

4 IN+ (200V/V) REF 1

SC70

C5360 0.1UF

V+

C5320 0.22UF


1

VCCIOISNS_ENG 3

42


OUT

6

VCCIOISNS_ENG

PLACE_NEAR=U4900.L12:5MM

R5361

CPUVCCIO_IOUT

CRITICAL 41 42 45 46

74 59

EDP: 8.5A

GFX/IG Vcore Voltage Sense / Filter XW5330

A

=PPGFXVCORE_S0_VSENSE

1

2

SMC_CPUVCCIO_ISENSE

OUT

42


C5361 VCCIOISNS_ENG 0.22UF

20% 6.3V 2 X5R 0201

2

Gain: 200x

GND_SMC_AVSS

41 42 45 46

Scale: 2.5A / V Max VOut: 3.3V at 8.25A

R5330

SM

7

TDP :7.225A

2

1% 1/20W MF 201

GND

Sense R is R7640, 2mOhm

4.53K

1

GFXVSENSE_IN

PLACE_NEAR=R7550.2:5 MM

4.53K

1

SMC_GFX_VSENSE

2

1% 1/20W MF 201


OUT

42


C5330


20% 6.3V 2 X5R 0201

GND_SMC_AVSS

SY NC _D AT E= 01 /1 0/2 01 1

PAGE TITLE

Voltage & Load Side Current Sensing

0.22UF

DRAWING NUMBER

Apple Inc. 41 42 45 46

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

53 OF 109

A

8 46 7

7

www.laptopblue.vn

6

5

4

3

2

1

COMPUTING High Side Current Sense / Filter


DC-IN (AMON) Current Sense Filter

DDR3 1V5R1V35 Current Sense / Filter

PLACE_NEAR=U4900.K10:5MM

1

3

2

U5450 IN

ISNS_HS_COMPUTING_N

5 IN-

46 74

IN

ISNS_HS_COMPUTING_P

4 IN+

INA214 SC70

OUT

53

10% 6.3V X5R 201

6

SCALE:

4.53K

2

SMC_HS_COMPUTING_ISENSE 1

PLACEMENT_NOTEs:

Scale: 2.5A / V

IN

ISNS_1V5_S3_N

5 IN-

74 56

IN

ISNS_1V5_S3_P

4 IN+

SC70

(100V/V)

OUT

6

1

SCALE:

4.53K

1

GND_SMC_AVSS

24 mV

42

OUT

42

0.22UF

EDP Current: 12 A Max Vdiff:

OUT

C5465

20% 6.3V 2 X5R 0201

5A / V

MAX VOUT: 2.4V AT 16.5A

2

SMC_1V5S3_ISENSE

2

1% 1/20W MF 201

GAIN: 100X

REF 1

D

R5465

ISNS_1V5S3_IOUT

GND

EDP Current: 3.5A

(For R and C)

10% 6.3V X5R 201

2

INA214

Max VOut: 1.4V at 8.25A

Place close to SMC

0.1UF

V+

U5460

74 56

ISL6259 Gain: 20x

41 42 45 46

C5460

1

3

Sense R is R7350, 2mOhm 41 42 45 46

DC-In AMON

GND_SMC_AVSS


0.22UF

GND_SMC_AVSS

20% 6.3V 2 X5R 0201

=PP3V3_S3_1V5S3ISNS

42

C5431

20% 6.3V 2 X5R 0201

0.22UF

5A/ V

31 mV

1

42

OUT

OUT

PLACE_NEAR=U4900.K10:5MM

1/20W MF 201

C5455

EDP Current: 15.5 A Max Vdiff:

SMC_DCIN_ISENSE


1% 1/20W MF 201

MAX VOUT: 3.1V at 16.5A

2

7 2

1%

ISNS_HS_COMPUTING_IOUT 1

GND

1

CHGR_AMON

IN

R5455

GAIN: 100X

REF 1

(100V/V)

D

4.53K

0.1UF

V+

46 74

R5431

C5450

41 42 45 46

PLACEMENT_NOTEs: Place close to SMC (For R and C)

COMPUTING High Side Current Sense / Filter & T29/Inlet Temp Sensor 46 7

AirPort Current Sense / Filter


7

1

=PP3V3_S3_WLANISNS

C5401 0.1UF 16V

1

CRITICAL

2

R5408 1

X5R-CERM 0201

5% 1/20W MF 201

EMC1704-2

C 7

IN

CRITICAL

R5400 1 1% 1W MF 0612

7

OUT

47

DP1

THERM*

47

INLET_THMSNS_D1_N 3

DN1

ALERT*

74 47

=T29THMSNS_D2_P

74 47

=T29THMSNS_D2_N

3

0.002

74 46 74 46

SENSE+

ISNS_HS_COMPUTING_N

15

SENSE-

HS_DUR_SEL 13 HS_TH_SEL14

R5405

1

82

TDP :13.175A

5% 1/20W MF 2012


R5406

HISIDE_ISENSE_OC

10

T29THMSNS_ALERT_L

11

10K

2

2

1

3

10% 6.3V

IN

ISNS_AIRPORT_N

5

IN-

74 37

IN

ISNS_AIRPORT_P

4

IN+

42

=I2C_T29_INLET_THMSNS_SDA

BI

44

=I2C_T29_INLET_THMSNS_SCL

BI

44

6

HS_ADDR_SEL

GPIO

7

INA210 SC70

(200V/V)

REF

6

ISNS_P5VWLAN_IOUT

1

Gain: 200x

130

4.53K

2

SMC_WLAN_ISENSE

2

AIRPORTISNS_ENG

1% 1/20W MF 201

1

C5475 0.22UF

GND_SMC_AVSS EDP Current: 0.750 A Max Vdiff:

1

NOSTUFF 1

PLACEMENT_NOTEs:

15 mV

R5412

0

Place close to SMC

THRM_PAD

0

5% 1/20W MF 201

7 1

R5413

2

HDD Current Sense / Filter

0

5% 1/20W MF 2012

5% 1/20W MF 2012

7

=PP3V3_S0_HDDISNS

HDDISNS_ENG

1

3

74 38

74 38

IN

ISNS_HDD_N

5

IN-

IN

ISNS_HDD_P

4

IN+

INA211 SC70

(500V/V)

HDDISNS_ENG C5480 0.1UF

V+

10% 6.3V

HDDISNS_ENG

2 X5R

U5480 Write Address: 0x98 Read Address: 0x99

R5485

201

OUT REF

6

ISNS_P5VHDD_IOUT

1

GAIN: 500X

1

4.53K

2

SMC_HDD_ISENSE

2

1

Max Vdiff:

0.22UF

20% 6.3V 2 X5R 0201

LCD Backlight Driver Input Current Sense / Filter 7

BMON:ENG 1

3


2

U5420


C5420 0.1UF

V+

CRITICAL

Charger/Load side

C5421

1

BMON:ENG

0.1UF

10% 6.3V X5R 201

10% 6.3V X5R 201

IN-

SC70

OUT

6

SC70

B1

IN

CHGR_CSO_R_N

4

IN+

SEL

6

SMC_BMON_MUX_SEL

42


REF

1 2

GND

VCC

5

74 8


Battery side

GND 3

4

B0

NOTE: Monitoring current from

BMON_AMUX_OUT

1%

BMON:ENG 1

across R7050 BMON:PROD

1

CHGR_BMON PLACE_NEAR=U5421.3:5MM

For engineering, stuff BMON_ENG

R5423 5%

0

IN

From charger

2

SMC_BMON_ISENSE

1/20W MF

IN

ISNS_LCDBKLT_P

4

2 5% 1/20W MF 201

2

1/20W MF 201

74 8

OUT

42


1

201

IN-

SC70

IN+

(500V/V) GND

C5422

2

LCDBKLTISNS_ENG

R5495

201

INA211 OUT

6

ISNS_LCDBKLT_IOUT

1

REF

GAIN: 500X SCALE:

1

4.53K 1% 1/20W MF 201

SMC_LCDBKLT_ISENSE

2

OUT

42

LCDBKLTISNS_ENG 1

C5495 0.22UF

20% 6.3V 2 X5R 0201

0.2A / V

MAX VOUT: 3.3V AT 0.66A

3300PF

100K

R5420 53

1

300K

A

VER 1

battery to PBUS (battery discharge)

IN

5

R5422

0

2

10% 6.3V

2 X5R

U5490

ISNS_LCDBKLT_N

C5490 0.1UF

V+ IN

1

(50V/V)

LCDBKLTISNS_ENG 1

3

NC7SB3157P6XG 1

BMON_INA_OUT

LCDBKLTISNS_ENG

U5421

2

INA213 5

=PP3V3_S0_BKLTISNS

BMON:ENG

BMON:ENG 74 53

B

Place close to SMC (For R and C)

=PP3V3_S3_BMON_ISNS

CHGR_CSO_R_P

41 42 45 46

PLACEMENT_NOTEs:

7.0 mV

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

IN

42

C5485

GND_SMC_AVSS EDP Current: 2.36A

B

OUT

HDDISNS_ENG

1% 1/20W MF 201

SCALE: 0.667A / V MAX VOUT: 3.3V AT 2.2A

GND

74 53

41 42 45 46

NOSTUFF 1


7

C

20% 6.3V 2 X5R 0201

(For R and C)

R5411

8

1% 1/20W MF 201 2

1

Scale: 0.25A / V MAX VOUT: 3V AT 0.825A

GND

HS_GPIO

TH_SEL GND

R5475

201

OUT

DUR_SEL

1

AIRPORTISNS_ENG

2 X5R

U5470 74 37

C5470 0.1UF

V+


5% 1/20W MF 201

12

SMCLK

DN2/DP3

16

9

AIRPORTISNS_ENG

R5409

ADDR_SEL

SMDATA

DP2/DN3

5

ISNS_HS_COMPUTING_P

2 4

=PPVIN_S5_HS_COMPUTING_ISNS

EDP: 15.5A

QFN

INLET_THMSNS_D1_P 2

=PPVIN_S5_HS_COMPUTING_ISNS_R

1

10K

VDD

U5400

4

AIRPORTISNS_ENG

NOSTUFF

10%

2

10% 10V

EDP Current: 0.67 A

X7R 201

GND_SMC_AVSS

Max Vdiff: 41 42 45 46

6.7 mV

GND_SMC_AVSS

PLACEMENT_NOTEs:

41 42 45 46

Place close to SMC (For R and C)

For production, stuff BMON_PROD

A

SYNC_MASTER=K78_MLB


PAGE TITLE

INA (Engineering) Solution

Charger BMON (Production) Solution

Gain: 50x

ISL6259 Gain: 36x

Scale: 2A / V

Scale: 2.78A / V



EDP Current: 10A

EDP Current: 310A

High Side Current Sensing DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

54 OF 109

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1

CPU Proximity Sensor T29 Die

R5510 7

=PP3V3_S0_CPUTHMSNS

1

47

PP3V3_S0_CPUTHMSNS_R

2


5% 1/20W MF 201

1

2

U5510

D

C5510 0.1UF

1 VDD

10% 6.3V X5R 201

R5511 1

EMC1413 DFN 74 9

BI

DP1

SIGNAL_MODEL=EMPTY

3

C5511 1

Detect CPU Die Temperature

74 9

2

CPU_THERMD_P

2200PF

PLACE_NEAR=U5510.2:5mm PLACE_NEAR=U5510.3:5mm

10% 10V X7R-CERM 0201

CRITICAL

DP2/DN3

5

DN2/DP3 GND 6

74

10K

2

2

34

5% 1/20W MF 201

BI

TP_T29_THERM_DP

SMDATA SMCLK

74

T29_THERMD_P

MAKE_BASE=TRUE

NOSTUFF

D

R55231 Detect T29 Die Temperature

PLACE_SIDE=BOTTOM

PLACE_NEAR=U3600.B1:2mm

8 CPUTHMSNS_ALERT_L

ALERT*

4

10K 5% 1/20W MF 201

R5512

7 CPUTHMSNS_THM_L 1

9

=I2C_CPUTHMSNS_SDA

BI

44

10

=I2C_CPUTHMSNS_SCL

BI

44

2

CPU_THERMD_N

BI

DN1

THERM*/ADDR

1

2

74

10K

5% 1/16W MF-LF 402 2

T29_THERMD_N

XW5520

Use GND pin B1 on U3600 for N leg

SM

THRM_PAD 11

Placement note:

CPUTHMSNS_D2_P

Place U5510 under CPU

SIGNAL_MODEL=EMPTY

3

C5512 1

Q5510

2200PF

1

10% 10V X7R-CERM 0201


BC846BMXXH SOT732-3 2 74

2

Write Address: 0x98 Read Address: 0x99

CPUTHMSNS_D2_N

Detect DDR/5V/3.3V Proximity Temperature

Placement note: Place Q5510 next to DDR/5V/3.3V supply on TOP side

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES C5361

117S0008

1

RES,MF,1/20W,100K

OHM,5,0201,SMD

117S0008

1

RES,MF,1/20W,100K

OHM,5,0201,SMD

117S0008

1

RES,MF,1/20W,100K

OHM,5,0201,SMD

C5485

117S0008

1

RES,MF,1/20W,100K

OHM,5,0201,SMD

C5495

CRITICAL

BOM OPTION VCCIOISNS_PROD

C5475

AIRPORTISNS_PROD

HDDISNS_PROD

LCDBKLTISNS_PROD

C

C Replacing caps with 100K PD on ISENSE SMC inputs

T29,MLB Bottom & Inlet Proximity Sensors INLET_THMSNS_D1_P

46

SIGNAL_MODEL=EMPTY

3

Q5530

C5523 1

Placement note:

2200PF

1

Place Q5530 between near rear vent on bottom side

10% 10V 2 X7R-CERM 0201

BC846BMXXH SOT732-3 2

INLET_THMSNS_D1_N

46

B

B =T29THMSNS_D2_P 3

Q5520

46 47 74

SIGNAL_MODEL=EMPTY

C5522 1

Placement note:

2200PF

1

10% 10V X7R-CERM 0201


Place Q5520 close to T29 on TOP side 2

=T29THMSNS_D2_N

46 47 74

=MLBBOT_THMSNS_D3_N

47

3

Q5540

Placement note:

1

Place Q5540 on MLB bottom side opposite U5400


=MLBBOT_THMSNS_D3_P

A

47

74 47 46

=T29THMSNS_D2_P

T29_MLBBOT_THMSNS_P

74 47 46

=T29THMSNS_D2_N

T29_MLBBOT_THMSNS_N

=MLBBOT_THMSNS_D3_P

47

=MLBBOT_THMSNS_D3_N

47



S YN C_ DA TE =0 1/ 16 /2 01 1

PAGE TITLE

Thermal Sensors DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

55 OF 109

A

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6

5

4

3

2

1

D

D

FAN CONNECTOR C

C 7 6

7

=PP5V_S0_FAN =PP3V3_S0_FAN

R5660 1 47K 5% 1/20W MF 201

R5665 41

SMC_FAN_0_TACH

1 47K2

CRITICAL

J5600

FF14A-4C-R11DL-B-3H

NC 2

1

FAN_RT_TACH

6

F-RT-SM 5

2 3

5% 1/20W MF 201

4

NC

5V DC TACH MOTOR CONTROL GND

6

R5661 1 100K 5% 1/20W MF 201

1

2

A

41

SMC_FAN_0_CTL

518S0793

SSM3K15FV SOD-VESM-HF

S

B

Q5660

G

2

D

6

FAN_RT_PWM

3

B

SYNC_MASTER=K78_MLB


PAGE TITLE

Fan DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

56 OF 109

A

8

7

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6

5

4

D

3

2

1

D

IPD Flex Connector 49 7

=PP3V3_S5_TPAD

CRITICAL

J5700

R5730 C5701 1

49 7

=PP3V3_S5_TPAD

10K 5% 1/20W MF 201

10% 16V X5R-CERM 0201

5% 1/20W 201


69 49

C5700 1 10% 6.3V X5R 201

VCC

BI

USB_TPAD_HUB_P

7

D+

BI

USB_TPAD_HUB_N

6

D-

U5700

USB_TPAD_P

BI

49 69

USB_TPAD_N

BI

49 69

8

=PP5V_S5_TPAD

10K

OE*

5% 1/20W MF 201 2

2

SMC_PME_S4_WAKE_L

42 41 6

OUT

74 49 6

BI

USB_TPAD_CONN_P

5

74 49 6

BI

USB_TPAD_CONN_N

6

49 44 6

BI

=I2C_TPAD_SDA

8

BI

=I2C_TPAD_SCL

9

2

49 44 6

6

MIN _NE CK_ WID TH= 0.2 0mm 49 42 41 6 OUT 49 42 41 40

6

IN

MIN _LI NE_ WID TH= 0.5mm

SMC_ONOFF_L

11

SMC_LID

12

20% 10V CERM 402

2

49 42 6

1

2

USB_TPAD_CONN_P

USB_TPAD_CONN_N

C5732 1


5% 25V CERM 201

2

1 5%

FIXME: CHECK SEL

0


5% 25V CERM 201

2

C5734 1

1/20W 201

NOSTUFF C5704 1

5% 25V CERM 201

2

6 42 49

1

C5735 100PF 5% 25V

2

C5736 1

C

100PF 5% 25V CERM 201

2

C5720 1

0.1UF 10% 16V X5R-CERM 0201

6 40 41 42 49

SMC_TPAD_RST_L


518S0794

MF

6 41 42 49

100PF

16

7 6=PP3V42_G3H_TPAD

6 44 49

SMC_LID


USB_TPAD_MUX_SEL

2

=I2C_TPAD_SCL

1

CERM 201

PM_SLP_S4_L

6 49 74

100PF


IN

6 49 74

BI

6 44 49

C5733

R5704 62 41 26 17

BI

=I2C_TPAD_SDA

SMC_ONOFF_L

100PF

14

SMC_TPAD_RST_L

OUT


C

3

USB_TPAD_N

13

0.1uF

3

BI

10

PP5V_TPAD_FILT

VOLTAGE=5V


C5710 1

69 49

7

0402-LF

GND

4

4

1

SEL 10

USB_TPAD_P

3

FERR-120-OHM-1.5A

SEL=1 Choose USB 7

1

R5702

2

L5720

SEL=0 Choose pull up/down

TQFN

CRITICAL

BI

1


Y+ 1 Y- 2

SYM_VER-1

MF

9

PI3USB102ZLE

24

MIN_NECK_WIDTH=0.20mm

DLP0NS

F-RT-SM 15

PP3V3_TPAD_CONN

0.1UF

USB_TPAD_M_P 5 M+ USB_TPAD_M_N 4 M24

6

2

2

L5710 90-OHM

FF14A-14C-R11DL-B-3H

2

VOLTAGE=3.3V

0.1UF 1

R5703

0

1

0.1UF 10% 6.3V X5R 201

2

2


Keyboard Backlight Driver & Detection CRITICAL 7

B

KB_BL

=PP5V_S0_KBDLED

L5750

Keyboard Backlight Connector

10UH-0.58A-0.35OHM BYPASS=U5750.1:2:2 MM 1

2

KB_BL

41

BI

MLF 3

6

KBDLED_FB

NC If LOW, keyboard backlight present KB_BL

If HIGH, keyboard backlight not present

1

R5853 always stuffed, R5854 only

R5755

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.25 MM

MIC2292

2

SMC_SYS_KBDLED

To detect Keyboard backlight, SMC will tristate and read SMC_SYS_KBDLED:

NC

U5750

10%

10V

EN

6

FB

5

NC

KB_BL

GND

2

4 8

F-RT-SM 5

1

J5815 pin 1 is grounded

2

on keyboard backlight flex

3

SW 7

CRITICAL

OUT 1

4 6

KBDLED_ANODE MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

NC

THRM

PAD

6

518S0793

9

OMIT_TABLE

C5755 1

4.7

grounded when KB BL flex connected.

J5715

VIN

1UF X5R 402-1

CRITICAL

FF14A-4C-R11DL-B-3H

2

C5750 1

B

KB_BL

KBDLED_SW MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

1098AS-SM

0.33UF

5% 1/16W MF-LF 402

10% 50V X5R 2 0603

OMIT_TABLE 1

C5756 0.33UF

10% 50V 2 X5R 0603

C5756 SYMBOL NOT READY FOR 0.22UF A

SYNC_MASTER=K78_MLB


PAGE TITLE

IPD / KBD Backlight PART NUMBER 138S0704

QTY 2

DESCRIPTION CAP,CER,0.22UF,10%,50V,X5R,0603

REFERENCE DES C5755,C5756

CRITICAL

DRAWING NUMBER

BOM OPTION

Apple Inc.

KB_BL

051-8870 REVISION

R

3.13.0


BRANCH


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SIZE

D

A

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6

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4

3

2

1

D

D

C

C 7

=PP3V3_S5_ROM

1

R6101 3.3K

2

70 43

8

C6100 1

5% 1/20W MF 201

0.1UF

VDD

CRITICAL

U6100

10% 16V X5R 2 402

64MBIT WSON

IN

SPI_MLB_CLK

6

IN

SPI_MLB_CS_L

1

SI/SIO0

SCK

5

SPI_MLB_MOSI

IN

43 70

2

SPI_MLB_MISO

OUT

43 70

SST25VF064C 70 43

43 19 6

IN

SPI_WP_L

3

SPIROM_USE_MLB

7

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

CE*

OMIT_TABLE SO/SOI1

WP*

RST*/HOLD* VSS THRM_PAD 4

9

B

B

A


S YN C_ DA TE =0 1/ 10 /2 01 1

PAGE TITLE

SPI ROM DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

61 OF 109

A

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6

5

4

3

2

1

SPEAKER AMPLIFIERS APN:353S2888

D

ALIAS OF

7

SPEAKER LOWPASS

80 HZ < FC < 132 HZ

GAIN

6DB

PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25M M

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

R6214

=PP5V_S3_AUDIO_AMP

1

0

D

PP5V_S3_U6210

2

5% 1/20W MF 201

C6207 1

NOSTUFF

0.1UF 10% 6.3V X5R 201

CRITICAL

1 A

IN

SPKRAMP_INR_P

74 40 6

IN

SPKRAMP_INR_N

40 6

IN

1

CRITICAL

C6211 0.1UF

C

1

2 10% 6.3V X5R 201

R6211 100K

2

WLP

74

MAX98300_R_P

A3

IN+

OUT+

B1

74

MAX98300_R_N

B3

IN-

OUT-

C1

C2

SHDN*

GAIN

C3

B2

0 5% 1/20W MF 201

1

2 2

C6201


47UF

MIN_NECK_WIDTH=0.10 MM

20% 6.3V POLY-TANT 2012-LLP

SPKRAMP_R_P_OUT

6 52 74

MIN_LINE_WIDTH=0.10 mm MIN_NECK_WIDTH=0.10 MM

SPKRAMP_R_N_OUT

6 52 74

R_AMP_GAIN

NC 1

R6210 1

1

R_SPKRAMP_SHDN

2 10% 6.3V X5R 201

AUD_GPIO_3

5% 1/20W MF 201

MAX98300

0.1UF

CRITICAL

1

100K

U6210

C6210

74 40 6

R6213

PVDD

2

R6212 100K

PGND

2 2 A

2

C

5% 1/20W MF 201

5% 1/20W MF 201

B

B

A


S YN C_ DA TE =0 1/ 10 /2 01 1

PAGE TITLE

AUDI0: SPEAKER AMP DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


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62 OF 109

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MLB to LIO Power Cable Connector CRITICAL

J6900

CRITICAL

WTB-PWR-M82 M-RT-SM

=PP18V5_DCIN_CONN

R6920

6 7

1

7 6

PPBUS_G3H

1

2

D

3 4

53

5

=PP5V_S3_LIO_CONN

518S0508

1

C6905 1 20% 50V CERM 603

C6906

10

2

2

3.425V "G3Hot" Supply

D6905 PPBUS_G3H_R

5% 1/8W MF-LF 805

PPDCIN_G3H_OR_PBUS_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

BAT30CWFILM

Supply needs to guarantee 3.31V delivered to SMC VRef generator

SOT-323 1

3

2

D

PPVIN_G3H_P3V42G3H MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

P3V42G3H_BOOST DIDT=TRUE

C6990

6

1

3

VIN

2.2UF 10% 25V X5R-CERM 603

10% 16V 2 CERM 402

2

R6905 5% 1/8W MF-LF 805

0.01UF

0.01UF

PPDCIN_G3H_OR_PBUS

1

6 7

6

4.7

C6994

BOOST

0.22UF 10% 10V CERM 402

U6990

2

1

LT3470A

CRITICAL

L6995

2

33UH-20%-0.39A-0.435OHM

=PP3V42_G3H_REG

DFN 8

NC

7

SHDN* NC

SW

CRITICAL

BIAS

FB GND 5

4 2

1

P3V42G3H_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

Vout = 3.425V 60MA MAX OUTPUT

1

THRM PAD

1

9

7

2 DP418C-SM

C6995 22PF

2

5% 50V CERM 201

R6995

(Switcher limit)

1

348K 1% 1/20W MF 201

CRITICAL 2

1

C6999 22UF

P3V42G3H_FB

1 R6996

20% 6.3V 2 X5R-CERM-1 603

200K 1% 1/20W MF 201

Debug LEDs

2

(For development only) 7

Vout = 1.25V * (1 + Ra / Rb)

=PP3V3_S3_DBGLEDS

C

S3_S0_LED

1

1K

5% 1/20W MF 201

C

S3_S0_LED

R69401

R6941 1K

2

2

5% 1/16W MF-LF 402

DBGLED_S3 DBGLED_S0 S3_S0_LED

D6910

A

A

K

K

GREEN-3.6MCD 2.0X1.25MM-SM

S3_S0_LED

D6920 GREEN-3.6MCD 2.0X1.25MM-SM

DBGLED_S0_D

S3_S0_LED

Q6940 3

D

SSM3K15FV SOD-VESM-HF

2

62 41 25 23

IN

B

S

G

1

ALL_SYS_PWRGD

B

Right Speaker Connector CRITICAL

J6903 78171-0002 M-RT-SM 3

K16-Specific Battery Connector PPVBAT_G3H_CONN

74 51 6

IN

74 51 6

IN

SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT

1 2

4

6 53

518S0519 CRITICAL

C6951 1

1

1UF

J6950

10% 16V X5R 402

WTB-PWR-M82 M-RT-SM

C6950 0.1UF

2

2

10% 25V X5R 402

1 2 3 4 5

A

6

6

=SMBUS_BATT_SCL

IN

=SMBUS_BATT_SDA

BI

6 44 6 44

SYS_DETECT_L SYNC_MASTER=JACK_K90I

7 8 9

518S0540

R6950

1

1

2


PAGE TITLE

DC-In & Battery Connectors

NO STUFF

10K 5% 1/20W MF 201

CRITICAL

D6950

DRAWING NUMBER

RCLAMP2402B 2 3

Apple Inc.

SC-75

051-8870

SIZE

D

REVISION

3.13.0

R


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69 OF 109

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This node is powered through body diodes:

Reverse-Current Protection

Inrush Limiter

* DCIN through Q7080. * PBUS through Q7085,

CRITICAL

Charger TOP FETs and

Q7080 SI5419DU

FROM ADAPTER 7

CRITICAL

Q7085

Q7055.

SI5419DU

PPDCIN_G3H_OR_PBUS

POWERPAK

52

POWERPAK

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WI DTH=0.25 mm VOLTAGE=18.5V

=PPDCIN_S5_CHGR

PPDCIN_G3H_INRUSH

A 5

D

1

MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.4 VOLTAGE=18.5V

A 5

D

D S

5

R7080

G

1

1

C7085 1

100K 5% 1/20W MF 201

4

2

2 2

1

1% 1/20W MF 201

4

CHGR_SGATE_DIV

CHGR_AGATE_DIV MIN_LINE_WIDTH=0.3 mm MIN_NECK_WID TH=0.25 mm

R7081

D7005

2

332K

5% 1/20W MF 201

1% 1/20W MF 201

BAT30CWFILM

(CHGR_SGATE)

SOT-323 1

CHGR_DCIN_D_R

20

1

2

R7021

(CHGR_DCIN)

5% 1/20W MF 201

2

2

30mA max load

10% 16V X7R 402

MIN_LINE_WI DTH=0.2 mm

4.7

1

FIXME: C7001 SAME AS C7000? PP5V1_CHGR_VDDP

2

MIN_LINE_WIDTH=0.2 MIN_NECK_WIDTH=0.2

5% 1/16W MF-LF 402

=PP3V42_G3H_CHGR

C

R7010

2

R7002

1% 1/20W MF 201

mm mm

C7001 1

5% 1/20W MF 201

R7000 43 42 41 6

SMC_RESET_L

IN

0

1

5% 1/20W MF 201

R7013 1% 1/20W MF 201

R7015

12

VHST

13

SMB_RST_N

=SMBUS_CHGR_SCL

11

SCL

44

BI

=SMBUS_CHGR_SDA

U7000

10

SDA

TQFN

IN

CHGR_VFRQ

4

VFRQ

CHGR_CELL

6

CELL

CHGR_ACIN

3

ACIN

CHGR_ICOMP

5

ICOMP

CHGR_VCOMP

7

VCOMP

CHGR_VNEG

8

VNEG CSOP

73

255K

2

73

1% 1/20W MF 2 201

R7011

CHGR_CSO_P CHGR_CSO_N

18 17

CHGR_VCOMP_R

1% 1/20W MF 201

Z T R H 9 5 2 6 L S I

C7022 1

2

10% 25V X5R 402

2

2

CHGR_DCIN

SGATE

26

CHGR_SGATE

AGATE

1

CHGR_AGATE

CSIP

28 73

CHGR_CSI_P

CSIN

27 73

CHGR_CSI_N

BOOT

25

CHGR_BOOT

9 2

2

2

0.5% 1W MF-LF 0612

PPDCIN_G3H_CHGR MIN_LINE_WI DTH=0.6 mm

20% 25V POLY-TANT CASE-D3L

CRITICAL 1

C7031

PLACE_NEAR=Q7030.5:1.5mm 1

1

20% 25V POLY-TANT CASE-D3L

C7035

C7036

1

1UF

33UF-0.06OHM 2

2

2

1

C7037

1UF

10% 25V X5R 603-1

0.001UF

10% 25V X5R 603-1

2

10% 50V X7R 402

2

C

CRITICAL

24

CHGR_UGATE

PHASE

23

CHGR_PHASE

LGATE

21

CHGR_LGATE

16

CHGR_BGATE

4

2

G

FDMS0355S POWER56

10% 10V CERM 402

CRITICAL 3

AMON

9

CHGR_AMON

OUT

46

36V/V

BMON

15

CHGR_BMON

OUT

46

(OD)

ACOK

14

=CHGR_ACOK

OUT

42 45

CRITICAL

L7030

F7040

4.7UH-13.1A

DIDT=TRUE

8AMP-24V

2 MIN_LINE_WID TH=0.6 mm MIN_NECK_WID TH=0.2 mm SWITCH_NODE=TRUE

20V/V

TO SYSTEM

f = 400 kHz

S 1 2 3

DIDT=TRUE

GATE_NODE=TRUE

Max Current = 8A

Q7030

PLACE_NEAR=U7000.25:2mm

C7025

1

2

=PPBUS_G3H

7

FDA1240F-SM 1206

DIDT=TRUE

DIDT= TRUE

1

PPVBAT_G3H_CHGR_REG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.4V

5

CRITICAL

CRITICAL

C7040 1

CRITICAL

D

20% 11V ELEC CASE-B2

Q7035

G

CRITICAL

C7041 1

62UF

2 2


PLACE_NEAR=L7030.2:1.5mm

C7043 1

62UF 2

1

C7045 1000PF

62UF 20% 11V ELEC CASE-B2

2

2

2

10% 16V X7R 201

FDMS0349 POWER56

1

C7002 10% 10V X5R 402

CRITICAL

XW7000

1 2 3

SM 1

(GND)

2

R7050

Q7055

0.01

SI7615DN

0.5%

PWRPK-1212-8

1W

TO/FROM BATTERY

MF


2

B

S

1UF 2

220

0612-3

CHGR_VNEG_R

C7016

R7051

(CHGR_CSO_P)

10% 16V X5R-X7R 201

2.2

1

2

74 46

5%

470PF 2

C7030 33UF-0.06OHM

10% 25V X5R 402

2

R70161

1

CRITICAL

MIN_NECK_WI DTH=0.4 mm VOLTAGE=18.5V

C7021

0.22UF

4

B 1% 1/20W MF 201

1

0.1UF

1

470PF 10% 16V X5R-X7R 201

3

D

UGATE

D N G P

T

C7015 1

CRITICAL

R7020

5

BGATE

) P D _ N M G A R ( H

10% 10V X5R 402

1

0.1UF

G A T EN _O D E = TRUE

CSON

C7050

2

OMIT_TABLE

DCIN

D A

1

0.47UF

10.5K

0 2

CHGR_RST_L

1

1

2

4

2

VDDP

IN

100

2

10% 10V X5R 402

CRITICAL 9 1

VDD

44

2

62

Float CELL for 1S

1

1

100K

CHGR_CSI_R_N

VOLTAGE=5.1V

NO STUFF

30.1K

CHGR_CSI_R_P

74

5% 1/20W MF 201

1UF 1

10

1

74

0.020

R7022

R7001

MIN_NECK_WI DTH=0.1 mm VOLTAGE=5.1V

7

2

5% 1/20W MF 201

C7020 0.047UF

DIVIDER SETS ACIN THRESHOLD AT 12.18V

PP5V1_CHGR_VDD

10

1

1

ACIN pin threshold is 3.2V, +/- 50mV

sparkitecture requirements

2

(CHGR_AGATE)

R7005 3

Input impedance of ~40K meets

1

R7086

62K

CRITICAL

D

G

MIN_LINE_WI DTH=0.3 mm MIN_NECK_WID TH=0.25 mm

1

mm mm

S

470K

0.1UF 10% 25V X5R 402

5

R7085

R7052

(CHGR_CSO_N)

0

1

2

1

4

3

S

PPVBAT_G3H_CHGR_R

MF

PPVBAT_G3H_CONN

3

MIN_LINE_WID TH=0.6 mm MIN_NECK_WID TH=0.25 MM VOLTAGE=8.4V

D

2

CHGR_CSO_R_P 1/20W

74 46

5%

(PPVBAT_G3H_CHGR_R)

2

5

6 52

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.4 mm VOLTAGE=8.4V

1

201

G

201

4

CHGR_CSO_R_N 1/20W

MF

(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)

1

C7042 0.1UF

2

10% 6.3V X5R 201

C7011 1

1

10% 10V X5R 201

C7000 1UF

0.01UF 2

2

10% 10V X5R 402-1

C7005 1

C7026 1

0.22UF 20% 25V X5R 603

1000PF 10% 16V X7R 201

2

GND_CHGR_AGND MIN_LINE_WIDTH=0.2 MIN_NECK_WIDTH=0.2 VOLTAGE=0V

A

mm mm

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

2

C7017 1

1

10% 25V X5R 805

C7014

1

1UF

10UF 2

2

10% 25V X5R 603-1

C7013

1

0.1UF 2

10% 25V X5R 402

C7012 0.01UF

2

10% 25V X7R 402

SYNC_MASTER=K78_MLB


PAGE TITLE

PBus Supply & Battery Charger DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

70 OF 109

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D

7

=PPVIN_S0_VCCSAS0

7

=PP5V_S0_VCCSA PLACE_NEAR=Q7100.2:1.5mm

VCCSAS0_BOOT_RC CRITICAL 1

R7101

1

2

20% 10V X5R 603

R7130

2

9 1

0 2

PVCC

IN

=PVCCSA_EN

IN

R7147 113K

2

1% 1/20W MF 201

62

OUT

7

UTQFN

CRITICAL

BOOT

18

UGATE

17

SREF

PHASE

16

12

VO

LGATE

1

11

OCSET

PVCCSA_PGOOD

14

VCCSAS0_RTN

4

VCCSAS0_FSEL

0.022UF

13

VCCSAS0_SET0

8

VCCSAS0_SET1

9

10% 16V X7R-CERM 402

C7122 1 1000PF

0.1UF

2

2

5% 25V NP0-C0G 402

C7123 1 62UF 20%

11V ELEC CASE-B2

2

2

2

2

3

7

CRITICAL

SIZ710DT

POWERPAK-6X3.7

1

R7140

CRITICAL

0.001

L7100

1% 1W MF-1 0612

1.0UH-7.7A 8

VCCSAS0_LL

C

CRITICAL

Q7100

VCCSAS0_DRVH MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

1

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

2

PPVCCSA_S0_REG_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

FDV0630H-SM

=PPVCCSA_S0_REG

1

2

3

4

6A Max Output 1

6

7

f = 300 kHz

C7141 270UF

PGOOD

2

RTN

VCCSAS0_DRVL

FSEL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

4


5

SET0 SET1

2 2

1

R7148

C7105 47PF

5% 25V 2 NP0-C0G 201

2

1% 1/20W MF 201

6

XW7101

VID0

SM

140K 1

FB

VCCSAS0_OCSET

C7103 1 10% 16V CERM-X5R 402

EN

10

VCCSAS0_VO

VCCSAS0_SREF

1

15

10% 16V X5R-CERM 0805

2

10% 10V CERM 402

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

ISL95870AH 62

CPU_VCCSASENSE

2

C7121 1

C7120 1 10UF

VCCSAS0_VBST

U7100

12

10% 16V X5R-CERM 0805

C7130 0.22UF

0 5% 1/10W MF-LF 603

VCC

C

1

CRITICAL

CRITICAL

C7119 1 10UF 1

PP5V_S0_VCCSAS0_VCC MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

CRITICAL


10UF

2.2 5% 1/16W MF-LF 402

C7101

1 1

C7102 2.2UF

2

10% 16V X5R 603

R7103 1

5

VID1

GND 2

3

PGND

R7141

2

1

1

IN

VCCSAS0_CS_P

74

VCCSAS0_CS_N

1K

PLACE_NEAR=C1763.2:3mm

1% 1/20W MF 201

2

C7140 1000PF 2

B

12

74

0 5% 1/20W MF 201

1

5% 25V NP0-C0G 402

CPU_VCCSA_VID<1>

R7149

1

2

1% 1/20W MF 201

(VCCSAS0_OCSET)

2

B

R7142 1K

47.5K

1% 1/20W MF 201

OCP = R7141 x 8.5uA / R7140 OCP = 8.5A

(VCCSAS0_VO)

XW7100 SM

VCCSAS0_AGND

1

2



VID1

A

VID0

Voltage

0

0

0.9V

1

0

0.8V


S YN C_ DA TE =0 1/ 16 /2 01 1

PAGE TITLE

System Agent Supply DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


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71 OF 109

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6

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D

D

7

=PPVIN_S5_P5VP3V3

PLACE_NEAR=Q7220.5.2:1.5mm

CRITICAL

CRITICAL 1 C7242

C7240

62UF

62UF

20%


11V 2 ELEC

CASE-B2

7 =PP5V_S5_LDO 1

1

2

2

C7270

1

1000PF 2

CRITICAL 1 C7284

C7241 1UF

10% 16V X7R 201

55 7

10% 16V X5R 402

=PP5V_S3_REG 55

P5VP3V3_VREG3

62UF 20% 11V ELEC CASE-B2

ELEC

CASE-B2

55

C7282

20%

11V 2

C7200 1

CRITICAL

62UF

PLACE_NEAR=Q7260.2:1.5mm 1

1

2

2

1

C7281

C7283 1000PF

1UF 10% 16V X5R 402

10% 16V X7R 201

2

P5VP3V3_VREF2

1UF

P5VS3_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

5

CRITICAL

D

Q7220

F=400KHZ

1

G

RJK03E0DNS

C

55 7

4

25V X5R 402

L7220

3

1.5UH-20%-18A-15MOHM

2

1

62UF 20% 6.3V ELEC CASE-B2S

2

2

150UF 20% 6.3V POLY-TANT CASE-B2-SM

C7250

C7253 20% 6.3V POLY-TANT CASE-B2-SM


PLACE_NEAR=L7220.2:3mm

SM

2

10V X5R 603

1

2

DID T=T RUE

P5VS3_DRVH GAT E_NODE =TR UE

DID T=T RUE

P5VS3_LL SWI TCH_NO DE= TRU E

SM

1

CRITICAL

1

RJK03E0DNS

C7271

SM

3

2

1

1

1

1.33K

2

1

R7220

1% 1/20W MF 201

41.2K

2

1% 1/20W MF 201

B

1

7.5K

0.22UF

1

1UF 10% 6.3V CERM 402

10% 10V CERM

2

402

C7205 10UF

2

2

P3V3S5_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

20% 10V X5R 0603

SW1

30

DRVL1

EN

12

=P5V3V3_REG_EN

IN

0 8 9 1 5 S P T

MF

C7237 1 10% 16V X7R-CERM 0201

2

P3V3S5_LL SWITCH_NODE=TRUE

27

P3V3S5_DRVL GA TE _ NO DE =T R UE

VFB2

16

COMP2

15

EN2

21

PGOOD2

20

COMP1 EN1 PGOOD1

3

3 3

R7249

X5R

7

CRITICAL

Q7260

=PP3V3_S5_REG

SIZ710DT

2

402

D ID T= TR UE

CRITICAL 2.5UH-14A 1

1

CRITICAL 150UF-0.018OHM-1.8A

2

5

1 C7290

2

20%

SM

PLACE_NEAR=L7260.1:3mm 1

2 1

2

P3V3S5_VFB2

2

1

2

2

C7272 1000PF 10% 16V X7R 201

PLACE_NEAR=L7260.2:3mm 10% 16V X5R 402

P3V3S5_COMP2 P3V3S5_EN_R

2

R7246 1

353S2678

1

1/20W

1/20W

MF

MF

201

2

10% 10V X7R

2

XW7262

2

SM

1

1

201

C7239 1 220PF

2

201

R7216


4.42K

MF 2

4700PF

201

1.54K

P3V3S5_COMP2_R

C7238 1


1/20W

201

1

1% 1/20W MF 201

1%

MF 2

NO STUFF

R7239 20K

1/20W

1%

5%

201

1

1%

249K 2

R7238 7.5K

R7206

10% 25V X7R-CERM

2

P3V3S5_VFB2_R

1% 1/20W MF 201

1

R7260 23.2K

P3V3S5_CSP2_R 2

2

201

1% 1/20W MF 201

P5VS3_CSP1_R P5VP3V3_VREF2

55

B

P5VP3V3_VREF2 1

10K

MF 201

20% 6.3V TANT CASE-B2-SM


R7221 1% 1/20W

10V X5R 603

1

C7292

10UF

XW7261

SM

4

0.1UF

P3V3S5_RF

F=400KHZ 2

PCMC063T-SM

6

MI N_ LI NE _W ID TH =0 . 6 mm MIN_NECK_WIDTH=0.2 mm

C7288

C

6.5A MAX OUTPUT

L7260

8


7

Vout = 3.3V

POWERPAK-6X3.7


DIDT=TRUE DI DT =T RU E

P3V3S5_CSN2

SM 1

25V

XW7260

THRM_PAD XW7200

3

10%


P3V3S5_CSP2

17

VFB1

270PF

4700PF 10% 10V X7R

2

25

9

0

201

SW2 DRVL2

P5VS3_VFB1

8 2

MF 2

P3V3S5_DRVH G AT E_ NO DE =T RU E

18

2

0.1UF

1

24

CSN2

5

C7264 1

5% 1/16W MF-LF 402

P3V3S5_VBST

DRVH2

CSP2

GND

1/20W

201

26

DIDT=TRUE

CSN1

NO STUFF

1

VBST2

CSP1

4

62

1

RF

10

R7264 0

U7201

DRVH1

R7237 1%

1/20W

P5VS3_COMP1_R

2

C7203 1

C7201 1

MODE

201

20K

1%

55

1

R7236

C7236 1

4.22K

2 F E R V

11

P5VS3_EN_R

2

R7256

3 G E R V

P5VS3_FUNC

P5VS3_COMP1

1% 1/20W MF 201

1

3 1

CRITICAL

VBST1

32

8

R7247

P5VS3_VFB1-R

1

1/20W

10% 16V X5R 402

S

XW7222

PLACE_NEAR=L7220.1.2:1.5mm

5%

2

MF

HWSON-8

2

0

1

P5VP3V3_VREG3

4


10% 16V X7R 201

OCSEL

7

P5VS3_CSN1

NO STUFF

55

2

SKIPSEL2

14

R7248

0.1UF

G

19

1

P5VS3_CSP1

C7218

D

SKIPSEL1

31

P5VS3_DRVL GATE_NODE=TRUE

D ID T= TR UE

5

Q7225

1000PF 2

1

M IN _L IN E_ WI DT H= 0. 6 m m MIN_NECK_WIDTH=0.2 mm

XW7221

20%

150UF

2

XW7220

10UF

2

CRITICAL

1

1

6

DIDT=TRUE

152S1424

1

C7252

5 G E R V

2 2

QFN


2 PCMC063T-SM

CRITICAL

N I V

2


1

9 2

2

P5VS3_VBST


C7254

W S 5 V

CRITICAL

7.2A MAX OUTPUT

1

2

2

3 2

1

0 5% 1/16W MF-LF 402

10% 2

S

CRITICAL

R7245

C7224 0.1UF

HWSON-8

=PP5V_S3_REG

Vout = 5.0V

10% 16V X5R 402

R7261 10K

62

62

OUT OUT

P5VS3_PGOOD

1% 1/20W

P3V3S5_PGOOD

2

MF 201

GND_P5VP3V3_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V



R7251

R7252

1

1

0

2

62

A

IN

=P5VS3_EN

0

5% 1/20W MF 201

2

62

IN

5% 1/20W MF 201

=P3V3S5_EN

SYNC_MASTER=K78_MLB


PAGE TITLE

5V / 3.3V Power Supply DRAWING NUMBER

Apple Inc.

051-8870 REVISION

R

3.13.0


BRANCH


PAGE

72 OF 109

SIZE

D

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D

7

=PPVIN_S3_DDRREG

CRITICAL

1

CRITICAL

1

C7330 62UF

7

7

1

62UF 20%

2 11V

ELEC CASE-B2

=PPVIN_S0_DDRREG_LDO

=PP5V_S3_DDRREG

CRITICAL

C7331

20%

2 11V

1

C7332 1UF

2

ELEC CASE-B2

1

C7333

2

C7334 62UF

0.001UF

10% 25V X5R 603-1

10% 50V X7R 402

20%

2 11V

ELEC CASE-B2

C7301 1 10UF 20% 10V X5R 603

C7300 1 20% 10V X5R 603

5

2


10UF

D 2


4

(DDRREG_DRVH) 2

G

PQFN3.3X3.3

MIN_NECK_WIDTH=0.17 mm

C

DDRREG_VBST

26 8

IN

=DDRVTT_EN

62

IN

=DDRREG_EN

VTT Enable VDDQ/VTTREF

Enable

DDRREG_1V8_VREF

12

V5IN

17

S3

16

S5

6

C7315 1

DDRREG_FB

8

20K

0.1UF 10% 16V X5R 402

31

R7315 1% MF

14

DDRREG_DRVH

SW

13

DDRREG_LL

DRVL

11

DDRREG_DRVL

PGOOD

20

DDRREG_PGOOD

5%

1

0

MF-LF

DDRREG_VBST_RC

VDDQSNS

REFIN

19

MODE

DDRREG_TRIP

18

TRIP

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

VTT

3

VTTSNS

1

VTTREF

5 31 7

7

R7316

MF

2

1

10% 16V CERM 402

R7317 200K

XW7360

D 2

4

PLACE _ N E A= RU 7 3 0 . 8 : 1 mm

1/20W MF 2

201


7

4

2

3

2

=PPDDR_S3_REG

7

4

ISNS_1V5_S3_P

1

2

Q7335

46 74

OUT

ISNS_1V5_S3_N

330UF 2

S

20% 6.3V X5R 603

1 2 3

C7346 1

2.0V POLY-TANT B2-SM

0.001UF 10% 50V X7R 402

CRITICAL

C7341

C7361 10UF

2


C7340 20%

CRITICAL

PQFN3.3X3.3

CRITICAL

20% 6.3V X5R 603

1 2

68K

OUT

IRFHM830DPBF


C7360 1

1% 1/20W MF 201

G


load

R7318

1

(DDRREG_DRVL)

SM 1

=PPVTT_S3_DDR_BUF

1

1%

PPDDR_S3_REG_R

1 74 46


0 1

C7316 0.01UF

1% 1/20W

2 MPCG1040LR88-SM

CRITICAL

10UF 1

100K

1

8

5

VTT THRM GND PAD

0.002 MF-LF 1/4W 1206 1%


OUT

=PPVTT_S0_DDR_LDO

max

R7350

0.88UH-20%-19A-2.3MOHM


CRITICAL

201 2 P L A C_ EN E A R =U730 .8:5 mm

CRITICAL

L7330

1 2 3

DDRREG_VDDQSNS

9

10mA

PGND GND

CRITICAL

2

10% 25V X5R 402 (DDRREG_LL)

GATE_NODE=TRUE

DDRREG_VTTSNS

201 2 PLACE_NEAR=U7300.8:5mm

1

1

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm

S

0.1UF

1/16W

2

DIDT=TRUE

SWITCH_NODE=TRUE

C

C7325

R7325

402

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm DIDT=TRUE

GATE_NODE=TRUE

QFN

DDRREG_MODE

1/20W 2


15

DRVH

TPS51916

VREF CRITICAL

1

VBST U7300

CRITICAL

Q7330

IRFHM831PBF


VLDOIN

2

1 1

330UF 20% 2.0V POLY-TANT B2-SM

C7345 20% 10UF

2 2

6.3V X5R 603


2

XW7301 SM

Vout = 1.5V 14.1A max output

1

PLACE_NEAR=C7340.1:1mm (Q7335 limit) C7360, C7361 close to memory 2


XW7300

C7350 1

f = 400 kHz (DDRREG_VDDQSNS)

0.22UF

SM

1

10% 10V CERM 402


2


GND_DDRREG_SGND MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.17

B

A

mm mm

B

VOLTAGE=0V

SYNC_MASTER=K78_MLB


PAGE TITLE

1.5V DDR3 Supply DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

73 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

=PP5V_S0_CPUIMVP

2

1

7

D

D R7401 P5V_S0_CPUIMVP_VDD

10

1

5% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V 7

2

=PPVCCIO_S0_CPUIMVP

=PPVIN_S0_CPUIMVP

C7401 1

1

2.2UF

R7479

1

1

20% 10V X5R-CERM 402

R7480

2

2

2

2


1% 1/20W MF 201

0 4


4 2

2.2UF

20% 10V X5R-CERM 402

20% 10V X5R-CERM 402

2


5 1

C A C D V D

B D D V

V

R7406 1

U7400

R7402

MAX15092GTL NC

QFN

31

OUT

BSTA1

CSPA3

5

CPU_PROCHOT_L

TON

DRVPWMA CRITICAL

39 67 42 10

25

C

62

IN

67 12

IN

67 12

IN

67 12

IN

OUT OUT

CPUIMVP_PGOOD CPUIMVP_AXG_PGOOD

CPU_VIDSOUT CPU_VIDSCLK CPU_VIDALERT_L

R7468 5.76K

1% 1/20W MF 2 201

R7466

NO STUFF

1

5.76K

1

R7464

1

R7462 215K

200K

1% 1/20W MF 2 201

1% 1/20W MF 201

2

2

1% 1/20W MF 201

DLA1

POKA

10

CSPA1

POKB

1

CPUIMVP_VR_ON

CPUIMVP_NTC CPUIMVP_NTCG

1

19

EN

CPUIMVP_BOOT1 CPUIMVP_UGATE1_R CPUIMVP_PHASE1 CPUIMVP_LGATE1 CPUIMVP_ISUM1_P

CSPAAVE

21 23 36 35

18

CLK

17

ALERT* CSPA2

38

33

THERMA

BSTA2

28

34

THERMB

DHA2

CSNA FBA

4

26

LXA2

27

CPUIMVP_SLEW

32

SR

DLA2

25

CPUIMVP_IMAXA CPUIMVP_IMAXB

29

IMAXA

BSTB

11

30

IMAXB

DHB

R7460

LXB

215K

DLB

1% 1/20W MF 201

CPUIMVP_ISUM CPUIMVP_ISUM_N CPUIMVP_FBA

37

VDIO

FBB

1

B

1

1

CRITICAL

R7467 100KOHM-1%-100MW

0603

1

R7465 10K

0603 2

2

C7444 47PF

CRITICAL

R7469 100KOHM-1%-100MW

2

1% 1/20W MF 201

1

R7463 137K

2

1% 1/20W MF 201

1

R7461

2

137K

2

5% 25V NP0-C0G 201

3

B S D N G 7

58

OUT

58

OUT

58

1

5%

2

2.2 CPUIMVP_UGATE1

OUT

12 14

45 58 74

NO STUFF

C7408

1

1

C

2200PF

10% 10V 2 X7R-CERM 0201

57

CPUIMVP_ISUM_R

2

10% 10V X5R-CERM 0402

C7404

C7409

R7410

470PF 2

OUT

58

OUT

58

OUT

58

OUT

58

OUT

1

1

2

5% 1/20W MF 201

58

57

1

OUT

58 74

OUT

58 74

C7407

0.0022UF

M D R A H P T

10% 50V 2 CERM 402

1 4

NO STUFF 1

XW7400

1% 1/20W MF 201

IN

0.039UF 58

5% 50V NP0-C0G 402

CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N CPUIMVP_FBB

6

CPUIMVP_ISNS1_P

58

OUT

CPUIMVP_BOOT1G CPUIMVP_UGATE1G CPUIMVP_PHASE1G CPUIMVP_LGATE1G

13

2

R7403

1/16WMF-LF402

1

CSNB

A S D N G

OUT

NC NC NC NC

CSPB1 8 9

NO STUFF

1

1% 1/16W MF-LF 402

300 5% 1/20W MF 201

90.9K2

CPUIMVP_TON

20

16

1

2

2

DHA1 22

VRHOT*

LXA1

62

7 58

C7403

1

2.2UF

130

54.9 1% 1/20W MF 201

C7402

NO STUFF 1

100PF

SM 2

C7418

1

2

5% 25V CERM 201

C7419 100PF

2

5% 25V CERM 201

NO STUFF

NO STUFF 1

C7414

1

100PF 2

C7415 100PF

5% 25V CERM 201

2

5% 25V CERM 201

B

GND_CPUIMVP_SGND MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

1

C7440 1000PF

2

10% 16V X7R 201

1

R7440

CPU_AXG_SENSE_R

10

1

VOLTAGE=0V 1

1000PF 2

10% 16V X7R 201

12 67

R7412 57

CPUIMVP_FBA

6.34K

1

1

VOLTAGE=0V

NO STUFF 1

2

C7442

NO STUFF 1

C7443

0.01UF

0.01UF

10% 10V X5R 201

10% 10V X5R 201

2

10

2

2

2

10% 16V X7R 201

R7413

CPUIMVP_FBA_R

1

1% 1/20W MF 201

R7441 CPU_VCCSENSE_R

A

IN

5% 1/20W MF 201

C7441

C7412 1000PF

CPU_AXG_SENSE_N

2

CPU_VCCSENSE_N

IN

10

2

CPU_VCCSENSE_P

IN

12 67

CPU_AXG_SENSE_P

IN

12 67

5% 1/20W MF 201

12 67

C7422 1

5% 1/20W MF 201

1000PF

R7422 57

CPUIMVP_FBB

8.25K

1

2

10% 16V X7R 201

2

R7423

CPUIMVP_FBB_R

1% 1/20W MF 201

1

10

2

5% 1/20W MF 201

SYNC_MASTER=K78_MLB


PAGE TITLE

CPU IMVP7 & AXG VCore Regulator DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

74 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

CPU=Sandy Bridge ULV, AXG=GT2

D

D

57 7

=PPVIN_S0_CPUIMVP CRITICAL

THESE TWO CAPS ARE FOR EMC

CRITICAL CRITICAL

1

2

CPUIMVP_BOOT1_RC

C7513

1

C7514

62UF

62UF

20%

20%

11V ELEC CASE-B2

2

1

2

11V ELEC CASE-B2

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

1

C7515

10UF

20%

20%

25V

2

X5R-CERM 0603

1

C7516

10UF

25V

2

X5R-CERM 0603

1

C7517

1

C7518 0.001UF

0.001UF

10% 16V X5R 402

10% 50V X7R 402

10% 50V X7R 402

2

2

1

C7519

1UF

1

C7540 62UF

C7541

2

62UF 20%

2

11V ELEC CASE-B2

1

C7510

20%

2

11V ELEC CASE-B2

1

62UF

20%

C7520 62UF 20%

2

11V ELEC CASE-B2

11V ELEC CASE-B2


PHASE 1

376S0984

DIDT=TRUE

CRITICAL

Q7510

R7511

IRF6811STRPBF

1 1

0 5% 1/16W MF-LF 402

SQ

C7511 0.22UF

2 2

IN

57

IN

CRITICAL

6

G

CPUIMVP_BOOT1 MIN_LINE_WIDTH=0.7 MIN_NECK_WIDTH=0.2

2 5

4 57

1

D

10% 10V CERM 402

S

3

DIDT=TRUE

MIN_LINE_WIDTH=0.7

MM MM

C

1


57

IN

PPVCORE_S0_CPU_PH1

2 PIMB104T-SM

CPUIMVP_PHASE1

IN

1% 1W MF 0612

0.36UH-20%-30A-1.2MOHM

DIDT=TRUE GATE_NODE=TRUE

57

0.00075

L7510

CPUIMVP_UGATE1 MIN_NECK_WIDTH=0.2

R7510

CRITICAL

MM MM

1


DIDT=TRUE

=PPVCORE_S0_CPU_REG

2

3

VOLTAGE=1.25V

7

C

4

CPUIMVP_ISNS1_N

74 45

152S1323

SWITCH_NODE=TRUE

CPUIMVP_ISNS1_P

OUT

45 57 74

CPUIMVP_LGATE1 MIN_LINE_WIDTH=0.7 MIN_NECK_WIDTH=0.2


MM MM

R7513

1

1

2

2

46.4

1

376S0985

2

6

1% 1/20W MF 201

CPUIMVP_ISUM_N

CRITICAL

D 5

R7514 10

1% 1/20W MF 201

7

Q7520

IRF6894MTRPBF

G

IN

57

NO STUFF

1

DIRECTFET-MX

C7571

S

2200PF

3

10% 10V X7R-CERM 0201

2

4

CPUIMVP_ISUM1_P

IN

57

B

B

7

=PPVIN_S0_CPUAXG CRITICAL

THESE TWO CAPS ARE FOR EMC

CRITICAL CRITICAL

1

MIN_NECK_WIDTH=0.25 MIN_LINE_WIDTH=0.5

MM

2


MM

376S0906


C7551

10

5% 1/16W MF-LF 402

10% 10V CERM 402

IN

TG

4

TGR

IN

MM MM

MIN_NECK_WIDTH=0.2

1 DIDT=TRUE GATE_NODE=TRUE

MM MM

57

IN

57

IN

1

VSW

6

2

25V

2

X5R-CERM 0603

1

25V

2

X5R-CERM 0603

C7557

1

CRITICAL 1

C7558

C7559

1UF

0.001UF

0.001UF

10% 16V X5R 402

10% 50V X7R 402

10% 50V X7R 402

2

2

1

CRITICAL

1

C7560 62UF

2

C7561 62UF


2


R7550 0.00075

L7550

1

CPUIMVP_VSWG

7


8

SWITCH_NODE=TRUE DIDT=TRUE

2 PIMB104T-SM

NOSTUFF 1

2

1% 1W MF 0612

2

1


=PPVCORE_S0_AXG_REG

2

3 74 45

CPUIMVP_ISNS1G_P

7

4

CPUIMVP_ISNS1G_N

74 45

R7553

5% 1/10W MF-LF

BG

PPVCORE_S0_AXG_R VOLTAGE=1.05V

152S1323

R7552 2.2

1

1

2

2

46.4

603

9

CPUIMVP_AXG_SNUB

1/16W MF-LF

MM MM

DIDT=TRUE SWITCH_NODE=TRUE

402

NOSTUFF 1

1% 1/20W MF 201

R7554 10 1% 1/20W MF

MM MM


C7552

201 SYNC_MASTER=K78_MLB

2


PAGE TITLE

DIDT=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

CPU IMVP7 & AXG VCore Output

VOLTAGE=1.25V

CPUIMVP_ISUMG_N

0.001UF

CPUIMVP_LGATE1G MIN_LINE_WIDTH=0.7 MIN_NECK_WIDTH=0.2

20%

CRITICAL

VIN

PGND 2

10UF

20%

5%

CPUIMVP_PHASE1G MIN_LINE_WIDTH=0.7 MIN_NECK_WIDTH=0.2

4.7

1 C7556

10UF

0.36UH-20%-30A-1.2MOHM

R7555

DIDT=TRUE

CPUIMVP_UGATE1G MIN_LINE_WIDTH=0.7

SON5X6

CPUIMVP_BOOT1G MIN_LINE_WIDTH=0.7 MIN_NECK_WIDTH=0.2

57

2


CRITICAL

1 C7555

62UF

CSD58864Q5D 3

1

0.22UF

2

C7554

Q7550

5 57

A

1

CRITICAL

MM MM

DIDT=TRUE

R75511


CRITICAL

CPUIMVP_BOOT1G_RC

AXG PHASE

C7553 62UF

CPUIMVP_UGATE1G_R

10% 50V CERM 402

IN

DRAWING NUMBER

57 74

Apple Inc. NO STUFF

1

C7574 1000PF

2

10% 16V X7R 201

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

75 OF 109

A

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6

5

4

3

2

1

D

D

CPU VCCIO (1.05V S0) Regulator

7

=PPVIN_S0_CPUVCCIOS0

7

=PP5V_S0_CPUVCCIOS0 CPUVCCIOS0_BOOT_RC CRITICAL

R7601

1

1

5% 1/20W MF 201

C 67 12

CPU_VCCIOSENSE_P

67 12

CPU_VCCIOSENSE_N

C7601

2

20% 10V X5R 603

R7630

2

1

1

603 4 1

2

=CPUVCCIOS0_EN

IN

CPUVCCIOS0_FB CPUVCCIOS0_SREF CPUVCCIOS0_VO CPUVCCIOS0_OCSET 62

R7605

1

1

2.74K 1% 1/20W MF 201

B

OUT

2

1

1% 1/20W MF 201

C7602 1

5% 25V NP0-C0G 402

1

C7619 62UF

2

2


C

PLACE_NEAR=Q7630.1:1.5mm

EN

6

FB

4 8 7

UTQFN

CRITICAL

SREF

UGATE

LGATE

11

0

CPUVCCIOS0_DRVH 1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

10

CPUVCCIOS0_LL

15

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

PGOOD

2

RTN

CPUVCCIOS0_FSEL

5

2

3 TG

SON5X6

VIN

R7640

1

0.001

L7630

VSW

MF-LF 402

CRITICAL

CSD58864Q5D CPUVCCIOS0_R

5% 1/16W

4 TGR

0.68UH-22A-2.7MOHM

6 7

PPCPUVCCIO_S0_REG1

8

PIMB104T-SM

CRITICAL

2 PPCPUVCCIO_S0_REG_R

2


4

1% 1W MF 0612

=PPCPUVCCIO_S0_REG 1

CRITICAL C7649 20% 2V TANT CASE-B2-SM

C7623 1

PGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

1000PF

9

5% 25V 2 NP0-C0G 402

FSEL

10% 16V X5R 603

C7604 1

1

47PF 2

2

C7605

1

0.047UF

5% 25V NP0-C0G 201

10% 16V X7R 402

2 2

R7641

C7648

1

74 45

CPUVCCIOS0_CS_P

74 45

CPUVCCIOS0_CS_N


B

3.01K

SM 1

f = 300 kHz 2

270UF 2

XW7600 CPUVCCIOS0_AGND

21A Max Output

CRITICAL 1

6 1

5% 1/20W MF 201

C7603

47PF 2

1

R7603

1

270UF


CPUVCCIOS0_DRVL

7

Vout = 1.05V

3

5 BG

OCSET

9

CPUVCCIOS0_RTN

Q7630

R7631 BOOT 12

PHASE

VO

2

0

2.2UF

5% 25V NP0-C0G 201

C7622 1 1000PF

2

GND PGND

2.74K

2

3

CPUVCCIOS0_PGOOD

R7645


10% 16V X5R 402


ISL95870 62

2

CRITICAL 1

62UF

CPUVCCIOS0_VBST

U7600

3.01K

2

C7621

2

MF-LF

3 1

R7644 1% 1/20W MF 201

CRITICAL 1


C7630 1UF

0

VCC PVCC

1% 1/20W MF 201

1

1

5% 1/10W


3.01K

C7620 62UF

PP5V_S0_CPUVCCIOS0_VCC

R7604

CRITICAL


10UF

2.2

1% 1/20W MF 201

2


2

C7640 1000PF 2


1

5% 25V NP0-C0G 402

(CPUVCCIOS0_OCSET)

1

R7642 3.01K

2

1% 1/20W MF 201

(CPUVCCIOS0_VO)

OCP = R7641 x 8.5uA / R7640 OCP = 25.6A Vout = 0.5V * (1 + Ra / Rb)

A

SYNC_MASTER=K78_MLB


PAGE TITLE

CPU VCCIO (1.05V) Power Supply DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

76 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

1.05V SUS LDO D

D

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups.

Alternative is strong voltage

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states. CRITICAL XDP_PCH

U7740

7

C7720 1

1000PF

22UF

10% 16V X7R 201

20% 6.3V X5R-CERM-1 603

1

2

N I V

2

C7740 1

3

1UF

D D V

10% 6.3V CERM 402

152S1302

L7720

U7720

62

BIAS

6

IN

3

EN

IN

=P1V8S0_EN

5

OUT

P1V8S0_PGOOD

7

PG

4

SYNCH

EN

=PP1V8_S0_REG LX

14

LX

15

P1V8S0_SW

1

SWITCH_NODE=TRUE DIDT=TRUE

2

D N G P

9 0 1

1 2 1 1

2

NC

2

THRM PAD

7

Vout = 1.05V Max Current = 0.020A NC XDP_PCH 1

C7741 2.2UF

7 2

10% 6.3V X5R 402

D A P _ M R H T

CRITICAL

P1V8S0_FB

8 16

NC

13

C7723

1

47PF

R7720

NC NC NC

6

7

Vout = 1.794V

CRITICAL 1

D N G S

5

1

PIMB042T-SM

QFN

CRITICAL

VFB

C

GND

=PP1V05_SUS_LDO OUT

1.0UH-20%-4.5A-24MOHM

ISL8014A 62

4

XDP_PCH

CRITICAL

2

SON

1.8V S0 Regulator

=PP3V3_S0_P1V8S0

C7724 1

TPS720105

=PP3V3_SUS_P1V05SUSLDO

7

1

113K 1% 1/20W MF 201

2

Max Current = 1.8A

C7721 22UF

5% 25V NP0-C0G 201

2

Freq = 1 MHz

20% 6.3V X5R-CERM-1 603

C

2

7 1

R7721

CRITICAL

1

C7722 1

90.9K 1% 1/20W MF 201

22UF 20% 6.3V X5R-CERM-1 603

2

2

Vout = 0.8V * (1 + Ra / Rb)

B

B

1.05V S0 LDO

1.5V S0 LDO

CRITICAL

CRITICAL

U7780

U7770

TPS720105

TPS72015

SON

SON 7

7

62

IN IN

=PP3V3_S0_P1V5S0

4 BIAS

=PP1V8_S0_P1V5S0

6 IN

C7771 1

1UF

1UF

10% 6.3V CERM 402

10% 6.3V CERM 402

2

2

NC 2 GND 5

THRM PAD 7

7

Vout = 1.5V

OUT 1

3 EN

=P1V5S0_EN

C7770 1

A

=PP1V5_S0_REG

Max Current = 0.02A

NC 1

C7772 2.2UF

2

10% 6.3V X5R 402

=PP1V05_S0_LDO

7


4

BIAS

7


6

IN

OUT

1

=1V05_S0_LDO_EN

3

EN

NC

2

62

C7782 1

C7780 1

1UF

1UF

10% 6.3V CERM 402

10% 6.3V CERM 402

2

GND 5

2

THRM PAD

7

Vout = 1.05V Max Current = 0.35A NC 1

C7781 2.2UF

7 2

10% 6.3V X5R 402


S YN C_ DA TE =0 1/ 16 /2 01 1

PAGE TITLE


Misc Power Supplies


DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

77 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

3.3V S0 FET

1

CRITICAL

Q7830 SIA427DJ SC70-6L

7

=PP3V3_S0_FET

7

=PP3V3_S0_P3V3S0FET

S

4

D

7

1

3.3V S0 FET 1

R7832

D

Q7812

C7831 1

10K

D 3

SSM6N37FEAPE SOT563

2

10% 16V X5R 402

IN

5

=P3V3S0_EN

G

3

2

C7830

R7830

P3V3S0_EN_L 62

G

0.033UF

5% 1/20W MF 201

91K

1

S 4

P3V3S0_SS

2

1

D

MOSFET

SiA427

CHANNEL

P-TYPE 8V/5V

RDS(ON)

0.01UF

26 mOhm @1.8V

2

LOADING

5% 1/20W MF 201

3.2 A (EDP)

10% 10V X5R 201

3.3V_SUS FET Q7820 CRITICAL

SIA427DJ SC70-6L 7

=PP3V3_S5_P3V3SUSFET

7

S

4

R7822

C7821 1

1

Q7822

D 6

100K 5%

SSM6N37FEAPE SOT563

3.3V S3 FET

2

CRITICAL

Q7810 2 G

SIA427DJ 62 61

SC70-6L 7

4

R7812 100K

1

Q7812

D 6

SOT563

2 IN

G

47K

1

=P3V3S3_EN

1

=PP3V3_S3_FET

G

0.033UF 10% 16V X5R 402

D

S 1

R7820 12K 1

=PP3V3_SUS_FET

7

3.3V SUS FET

3

C7820 0.01UF

P3V3SUS_SS

1

5% 1/20W MF 201

2

MOSFET

SiA427

CHANNEL

P-TYPE 8V/5V

RDS(ON)

10% 10V X5R 201

5V_SUS FET

3.3V S3 FET

26 mOhm @1.8V 100? mA (EDP)

LOADING

C

CRITICAL

Q7840 SIA413DJ

0.01UF

P3V3S3_SS

1

5% 1/20W MF 201

1

7

MOSFET

C7810

2

2

3

2

R7810

P3V3S3_EN_L

S 1

S

C7811 1

5% 1/20W MF 2201

SSM6N37FEAPE

62

P3V3SUS_EN_L

7

=PP3V3_S3_P3V3S3FET

C

IN

=P5V_3V3_SUS_EN

10% 16V 2 X5R 402

1/20W MF 201

D

G

0.033UF

SiA427

CHANNEL

2

7

P-TYPE 8V/5V

RDS(ON)

10% 10V X5R 201

SC70-6L

=PP5V_S5_P5VSUSFET

7

S

4

31 mOhm @1.8V

LOADING

C7841 1

R7842

1

1.608 A (EDP)

Q7822

D 3

220K

SSM6N37FEAPE SOT563

5 G 62 61

IN

=P5V_3V3_SUS_EN

10% 16V 2 X5R 402

5% 1/20W MF 2 201

P5VSUS_EN_L

S 4

R7840 3.3K 1

2

D

1

=PP5V_SUS_FET

7

5V SUS FET

G

0.033UF

3

C7840 0.01UF

P5VSUS_SS

1

5% 1/20W MF 201

2

MOSFET

SiA427

CHANNEL

P-TYPE 12V/8V 29 mOhm @4.5V

RDS(ON)

10% 16V CERM 402

LOADING

100? mA (EDP)

1.5V S3/S0 FET 7 7

5.0V S0 FET

=PP1V5_S3_P1V5S3RS0_FET

=PP5V_S5_P1V5DDRFET

CRITICAL

Q7860

TPCP8102

C7801 1

23V1K-SM

0.1UF 20% 10V CERM 402

B

1

2

7

VCC

IN

P1V5CPU_EN

2 3

TDFN

ON

CRITICAL

SHDN*

D

C7802 1 4.7UF

10% 6.3V X5R-CERM 2 603

GND 4

D G

NO STUFF

APN 376S0928

5

U7801

SLG5AP020 26

5 7

S

6

PG

8

1

P1V5S0FET_GATE

0

4

P1V5S0FET_GATE_R 5% 1/16W MF-LF 402

FDMC2514SDC

G

POWER33

S

P5V0S0_EN_L 1 2

PAD

1

0

2

7

5.0V S0 FET

6 5

16V X5R

R7860 1

10K

2

B

MOSFET

TPCP8102

CHANNEL

P-TYPE

RDS(ON)

18 MOHM @4.5V

LOADING

1.678 A (EDP)

4

10% 2

C7860

402

0.01UF

P5V0S0_SS

1

2

5% 1/20W

=PP1V5_S3RS0_FET

MF 201

7

10% 16V CERM 402

5% 1/4W MF-LF 1206

9

D

G

1

0.033UF

CRITICAL

R7850

3

PP1V5_S3RS0_FET_R

THRM

C7861

220K

5% 1/20W MF 2201

S

1

R7862

Q7801

2

7 2

1 CRITICAL

R7801

=PP5V_S0_FET 8

3

=PP5V_S3_P5VS0FET

Q7802

D 3

SSM6N37FEAPE SOT563

P1V5S3RS0_RAMP_DONE OUT

5 G 8 62

IN

=P5VS0_EN

S 4

1.5V S3/S0 FET

A

MOSFET

PQFN2X2

CHANNEL

N-TYPE

RDS(ON)

9.4 mOhm @4.5V

LOADING

5 A (EDP) SYNC_MASTER=K78_MLB PAGE TITLE


Power FETs DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

78 OF 109

A

8

7

www.laptopblue.vn

6

5

S5 Rail Enables & PGOOD

4

6.3V 2 X5R 201

1

CRITICAL

R7941

VDD

343S0497

1

U7941

SLG4AP012

SMC_PM_G2_EN

2

MAKE_BASE=TRUE 62 7

=PP3V3_S5_PWRCTL 6 Threshold: ?? DLY > 10 ms S5PGOOD_DLY 7 1

OUT_A*

IN_A (IPD)

4

(OD,IPU)

OUT_A

IN_B

3

(OD,IPU)

2:1 +

1

MAKE_BASE=TRUE

C7942

=P3V3S5_ENOUT

0.033UF

10% 2 16V X5R 402

OUT_B

DLY

S5_PWRGD

8

0

1

1

0

5

0

0

0

0

0

0

0

PAD

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

9

SMC-->PM_DSW_PWRGD

OUT

5% 1/20W MF 201

100

1

0

1

CPUVCCIOS0_PGOOD

R7956 15K

PM_PECI_PWRGD OUT

62 7

1K

1K

5% 1/20W MF 201

2

6

4

Q1

5

Q2

SSM3K15FV

B

A

62 7

R7960 S0PGOOD_ISL 1 6.04K R7970 1% 1/20W MF 201

2

4

=P5V_3V3_SUS_EN OUT

MAKE_BASE=TRUE

1/20W MF 2012

0

62 7

=PP3V3_S5_PWRCTL

R79571 100

C7930

P5V_DIV_VMON

S0PGOOD_ISL

1

R7961 S0PGOOD_ISL 15K R79711 1% 1/20W MF 201

2

10K

1% 1/20W MF 2012

P1V5_DIV_VMON P1V05_DIV_VMON S0PGOOD_ISL

1

5 SENSE

=PP3V3_SUS_PWRCTL

R7973 15K

1% 1/20W MF 201

S0PGOOD_ISL

V4MON

RST*

1 8

R7967 10K

NO STUFF

57

IN

CPUIMVP_AXG_PGOOD

60

IN

P1V8S0_PGOOD

100

1

5% 1/20W MF 201

100

P3V3S5_PGOOD 1

55

IN

P5VS3_PGOOD

62 59

IN

CPUVCCIOS0_PGOOD

54

IN

PVCCSA_PGOOD

5% 1/20W MF 201

C7986 0.47UF

2

10% 6.3V CERM-X5R 402

B

5% 1/20W MF 2012

6

U7930 RESET*

1

SOT23-6 MR* 3 (90K IPU)

PM_RSMRST_L

OUT

C7931

2

WLAN Enable Generation

10% 16V

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

201

2

NO STUFF

R7966 1

2

100

PM_WLAN_EN_L

100

5% 1/20W MF 201

2

IN

2

AP_PWR_EN

G

NC

DP S4 Power Enable

5% 1/20W MF 201

42 41

IN

SMC_S4_WAKESRC_EN =DPAPWRSW_EN MAKE_BASE=TRUE

SOT-363

65

ALL_SYS_PWRGD

S YN C_ MA ST ER =K 78 _M LB 3

NO STUFF

Q7920

D

SMC_ADAPTER_EN

2

G

S

OUT

23 25 41 52 62

5% 1/20W MF 201 2

Power Control 1/ENABLE DRAWING NUMBER

2N7002DW-X-G

0

IN

SY NC _D AT E= 01 /1 0/2 01 1

PAGE TITLE

R79291

D

42 41 17

S

NC

AC_EN_L

Q7920

PSOC USB Power Enable

S0PGOOD_ISL 2

(AC_EN_L)

2N7002DW-X-G 6 OUT

G

4

R7964 2

5

S 1

100

Unused fet

SOT-363

SOT-363

37 18

D

2N7002DW-X-G

D

2N7002DW-X-G

3

Q7925

6

Q7925

2

1

NC

37

OUT

2

R7901 1

17

PM_RSMRST_L goes to U1800.C21

NC

1000PF

R7962 330

2

100K

1

1

10% 6.3V CERM-X5R 402

61

2 X7R

5% 1/20W MF 201

ALL_SYS_PWRGD_R

9353S2310

0.47UF

2

1

C7988

10% 6.3V CERM-X5R 402

1

10% 6.3V 2 X5R 201

5% 1/20W MF 201

100

1

1

5% 1/20W MF 201 2

GND THRM_PAD

4


1

0.47UF

GND

1

IN

NC

S4_PGOOD_CT 4 CT

=PP3V3_S0_PWRCTL

R7963

V3MON

C7981

10% 6.3V CERM-X5R 402

VDD

VDD

3 5 6

1

0.47UF

R7933

0.1UF

CRITICAL

5% 1/20W MF 2012

2 7

ISL88042IRTEZ TDFN (IPU) V2MONCRITICAL MR*


C7987

=PP3V3_SUS_PWRCTL

PLACE_NEAR=U7930.6:2.3mm 1

R7968

U7960

C

3.3V SUS Detect

U7930 Sense input threhold is 3.07V

R7965

10% 6.3V 2 X5R 201

54

OUT

VFRQ High: Variable Frequency

No stuff C7931, 12ms Min delay time

C7960 1

1

59

=PVCCSA_EN

2

353S2809

=PP3V3_S0_VMON

1% 1/20W MF 201 2

60

=CPUVCCIOS0_EN OUT

R7917

S0PGD_BJT_GND_R

6.04K

60

=1V05_S0_LDO_ENOUT

NO STUFF

Worst-Case Thresholds:

S0PGOOD_ISL

R7972

60

OUT

VFRQ Low: Fix Frequency

5% 1/20W MF 201

P1V5S0_PGOOD from U7710

S0PGOOD_ISL

10K

OUT

=P1V5S0_EN

CHGR VFRQ Generation

Q4

3

PM_SUS_EN

S 2

2

1

VMON_Q4_BASE

=P1V8S0_EN


GND

CRITICAL

=PP1V05_S0_VMON 0.1UF

1% 1/20W MF 2012

45

C

DFN2015H4-8

55

=PP1V5_S3RS0_VMON

61

OUT

MAKE_BASE=TRUE


1

G

1

100K Delete R when5%pull-down added to PCH page

S0 Rail PGOOD Circuitry

1

61

OUT

=PBUSVSENS_EN

53

D 3

SOD-VESM-HF

6

PM_SLP_SUS_L

IN

Q3

2

NC

3

R7918

ASMCC0179

8

NC

VMON_Q3_BASE 7

2

MAKE_BASE=TRUE

PVCCSA_EN

A

PLACE_NEAR=U1800.A15:5mm 1

Q7950 2

1

23 25 41 52 62

(ISL Version in development)

62 7

OUT

=P3V3S0_EN


CPUVCCIOS0_EN

SOT891

Y

7

=PP5V_S0_VMON


=P5VS0_EN

MAKE_BASE=TRUE

5% 1/20W MF 201

CHGR_VFRQ OUT

Q7931

VCC

U7940 74AUP1G3208

TPS3808G33DBVRG4

7

5% 1/20W MF 201

1

201

R7931

1

SMC_BATLOW_L

IN

62 7

S0PGOOD_ISL

5% 1/20W

1 MF

P1V5S0_EN

2

ALL_SYS_PWRGD

Q2: 0.XXXV Q3: 0.640V 3.3V w/Divider: 2.345V Q4: 0.660V

62 7

5.1K

=PP3V42_G3H_PWRCTL

5

10% 6.3V X5R 2 201

17

5% 1/20W MF 201

=PP1V05_S0_VMON 1

R7986

39K

5% 1/20W MF 201

1

2

R7988

20K

5% 1/20W MF 201

1

R7981

2

10K

0.1UF

S0PGD_C

R7954

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

R7987

33K

2

C7943

42 41

1

62 7

PM_SLP_S3_R_L MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

R7955

B

10% 6.3V CERM-X5R 402

2

2 2

3.3V/5.0V Sus ENABLE

41

SMC_BATLOW_L:100K pull up on SMC page

V MO N_ Q2 _B AS E

2

5% 1/20W MF 201

1

6 39 40

0.47UF

P1V8S0_EN

2

1

R7953

PP1V5_S3RS0

56

OUT

MAKE_BASE=TRUE 7

1% 1/20W MF 201 2

R7951

=PP1V5_S3RS0_VMON

61

OUT

=USB_PWR_EN

62

150K

1

62 7

(PM_SLP_S3_R_L)

2

5% 1/20W MF 201

PLACE_NEAR=U1800.D4:5mm

=PP3V3_S5_VMON

7.15K

OUT

=DDRREG_EN


=PP3V3_S0_VMON

R7952

=P3V3S3_EN

R7978

57

5% 1/20W MF 201

1

D

C7912

NO STUFF

1K

10% 10V CERM 402

PLACE_NEAR=Q7812.2:6mm 1

10% 6.3V CERM-X5R 402


62 59

1% 1/20W MF 2 201

5% 1/20W MF

C7910

2

S0 ENABLE IN

R7975

1

0.068UF

2

9.1K 1 201


V MO N_ 3V 3_ DI V

55

OUT

NO STUFF

1 C7913

2

0.47UF

100K CPUIMVP_VR_ON

2

1% 1/20W MF 2 201

MAKE_BASE=TRUE

R7912

5.1K

R7915

S0 Rail PGOOD (BJT Version) 7

5% 1/20W MF 201

1

PLACE_NEAR=U7940.5:2.3mm 1

62 7

R7911

1


5% 1/20W MF 201

C

2

1

2

=P5VS3_EN

P5VS3_EN

P3V3S3_EN

Delete R when pull-down added to PCH page

R7976 0

2

MAKE_BASE=TRUE

CPUVCORE ENABLE


1


5% 1/20W MF 201


R79791

2

5% 1/20W MF 201

100K

PM_SLP_S5_L

IN

PM_SLP_S3_L

1

R7910

DDRREG_EN 41 17

62 41 26 17

ALL_SYS_PWRGD

0

5% 1/20W MF 201

1

41

2

62 52 41 25 23

MAKE_BASE=TRUE

PLACE_NEAR=Q7812.2:6mm

1/20W MF 201

0

1

PM_SLP_S4_L

55

100K Delete R when5%pull-down added to PCH page

R7974

IN

0

1

R7913

Delete R when pull-down added to PCH page 49 41 26 17

MAKE_BASE=TRUE OUT

MAKE_BASE=TRUE

(OD,IPU)

THRM

GND

220PF

1

1

3.3V S4 ENABLE

DLY_1C

10% 2 25V X7R-CERM 201

PM_SLP_S3_L

1

1

Battery Off (G3Hot)

1.3V -

C7941

PM_SLP_S4_L

1

1

Deep Sleep (S5)

P5V3V3_REG_EN MAKE_BASE=TRUE =P5V3V3_REG_EN OUT

PM_SLP_S5_L

1

Deep Sleep (S4)

55

NO STUFF

NC

SMC_PM_G2_ENABLE

Run (S0) Sleep (S3)

P3V3S5_EN

2

5% 1/20W MF 201

TDFN

IN

100

1

3.3V,5V S3 ENABLE State

C7940 1 0.1UF 10%

41

2

=PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20%

62 7

D

3

SOT-363

S

G

Apple Inc.

5

(PM_SLP_S3_L)

051-8870

SIZE

D

REVISION

3.13.0

R

4


BRANCH


PAGE

79 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

D

D

LCD Connector Internal DP Connector: 518S0787 CRITICAL

J9000 CABLINE-CA F-RT-SM

Pull-ups on panel side,

R9061 44

BI

0

1

=I2C_TCON_SDA

2

66 6

4.7 kOhm to 3.3V 6

31

PPVOUT_SW_LCDBKLT

1

I2C_TCON_SDA_R

5% 1/20W MF 201

NC

3 4

R9062 44

C

IN

0

1

=I2C_TCON_SCL

2

6

I2C_TCON_SCL_R

5% 1/20W MF 201

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

NC

=PP3V3_S5_LCD

U9000

LCD_IG_PWR_EN

MFET-2X2-8IN

9

OUT

DP_INT_HPD

1

FPF1009 8

IN

1

ON

2

VIN_1

3

FERR-120-OHM-1.5A

VIN_2

VOUT_1 VOUT_2

4

PP3V3_SW_LCD_UF

5


1

6

1 1

1K 5% 1/20W MF 201

C9009 0.1UF

2 2

10% 6.3V X5R 201

C9011 0.1UF 10% 6.3V X5R 201

C9012

70 9

BI

DP_INT_AUX_CH_N

1

1

1000PF

0.1UF 1

2

C9015 1 C9024

7 1

2

(DP_INT_AUX_CH_C_N)

10% 16V X7R 201

2

20% 6.3V X5R 603

10% 16V X5R-CERM 0201 70 9

BI

DP_INT_AUX_CH_P

2

0.1UF IN

DP_INT_ML_P<0>

1

LED_RETURN_6

66 6

OUT

LED_RETURN_5

66 6

OUT

LED_RETURN_4

66 6

OUT

LED_RETURN_3

9

66 6

OUT

LED_RETURN_2

10

66 6

OUT

LED_RETURN_1

11

7 8

NC

B

IN

2

DP_INT_HPD_CONN

6

PP3V3_SW_LCD

C

LED Backlight I/F

12 13 14 15 16

DisplayPort I/F

17 18


19 20

70 6

DP_INT_AUX_CH_C_N

21

70 6

DP_INT_AUX_CH_C_P

22

70 6

DP_INT_ML_F_P<0>

24

70 6

DP_INT_ML_F_N<0>

25

70 6

DP_INT_ML_F_P<1>

70 6

DP_INT_ML_F_N<1>

23

26

(DP_INT_AUX_CH_C_P)

10% 16V X5R-CERM 0201

27 28 29

PLACE_NEAR=J9000.25:1mm

R90171 1M

5% 1/20W MF 201 2

C9021 0.1UF 1

DP_INT_ML_N<0>

6

0.1UF

2

10% 16V X5R-CERM 0201 70 9

5% 1/20W MF 201

C9025 1

C9020 70 9

R9070 100K

2

10UF 2

2

0402-LF

GND THRM PAD

R9014

0

6

OUT

5% 1/20W MF 201

L9004

5

66 6

R9060 CRITICAL 7

2

2

1

R9018

30

1M

5% 1/20W MF 2 201

33 34

PLACE_NEAR=J9000.24:1mm

35

B

36

C9022 0.1UF 70 9

IN

DP_INT_ML_P<1>

1

10% 16V X5R-CERM 0201

37 38 39

2

40 10% 16V X5R-CERM 0201 70 9

IN

DP_INT_ML_N<1>

C9023 1

2 32

10% 16V X5R-CERM 0201

A

41

0.1UF

R9050

1

1

R9080

100K

100K

5% 1/20W MF 201

5% 1/20W MF 201

2

2

PLACE_NEAR=J9000.3:2mm 1

C9017

1000PF 5% 50V C0G-CERM 603

2


S YN C_ DA TE =0 2/ 10 /2 01 1

PAGE TITLE

Internal DisplayPort Connector DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

90 OF 109

A

8

7

www.laptopblue.vn

6

5

4

8

70 8

IN

DP_EXTA_ML_C_P<0>

C9300

70 8

IN

DP_EXTA_ML_C_N<0>

C9301

1

2

10% 16V X5R-CERM

0.1UF 1

70 8

IN

DP_EXTA_ML_C_P<1>

C9302

70 8

IN

DP_EXTA_ML_C_N<1>

C9303

1

64 70

72 34

OUT

T29_D2R_N<0>

72 34

OUT

T29_D2R_P<0>

C9370

(C9370/C9371)

(C9372.2)

DP_EXTA_ML_P<1>

64 70

0201

DP_EXTA_ML_N<1>

2

10% 16V X5R-CERM

64 70

72 34

IN

T29_R2D_C_N<0>

72 34

IN

T29_R2D_C_P<0>

0201

D

IN

DP_EXTA_ML_C_P<2>

IN

DP_EXTA_ML_C_N<2>

C9304

1

0.1UF 70 8

C9305

DP_EXTA_ML_P<2>

2

10% 16V X5R-CERM 1

DP_EXTA_ML_N<2>

2

IN

DP_EXTA_ML_C_P<3>

C9306

70 8

IN

DP_EXTA_ML_C_N<3>

C9307

1

IN

8

caps to improve layout.

2

1

DP_EXTA_ML_P<3>

64 70

DP_EXTA_ML_N<3>

64 70

0201

2

10% 16V X5R-CERM

0.1UF

1

IN

BI

DP_EXTA_AUXCH_C_P

C9308

70 8

BI

DP_EXTA_AUXCH_C_N

C9309

1

0.1UF

5% MF

DP_EXTA_AUXCH_P

2

10% 16V X5R-CERM

10% 16V X5R-CERM

1

0.1UF

72 34

OUT

T29_D2R_N<1>

72 34

OUT

T29_D2R_P<1>

(C9383.2)

64 70

72 34 72 34

DP_EXTA_AUXCH_N

If GPU uses common pins for AUX_CH

5% MF

1M

and DDC, alias nets together at GPU.

1/20W 201

R9354

T29_R2D_C_N<1>

IN

to prevent spikes when U9310 AUXDDC_OFF

5% MF

1

1/20W 201

8

R9353 5% 1/20W MF 201

DP A Super-Driver

R9355 5% 5% MF

C9310

1

C9311

1

2.2UF

C

20% 6.3V CERM 402-LF

PS8301 I2C Addresses: A1

A0

0

0

0x96/0x97

0

1

0xB6/0xB7

1

0.1UF 2

10% 16V X5R-CERM 0201

2

0

0x94/0x95

1

1

0xB4/0xB5

70 64

used for this part. NO STUFF

R9311

1

1

1K 5% 1/20W MF 201

1K

2

2

8

5% 1/20W MF 201

8

72

DP_SDRVA_ML_R_P<2>

72

DP_SDRVA_ML_R_N<2>

8

R9352

64 7

IN_D0N

OUT_D0N

29

72

DP_SDRVA_ML_C_N<0>

4

IN_D1P

OUT_D1P

28

72

DP_SDRVA_ML_C_P<1>

5

IN_D1N

OUT_D1N

27

72

DP_SDRVA_ML_C_N<1>

70 64

DP_EXTA_ML_P<2>

7

IN_D2P

OUT_D2P

25

72

DP_SDRVA_ML_C_P<2>

70 64

DP_EXTA_ML_N<2>

8

IN_D2N

OUT_D2N

24

72

DP_SDRVA_ML_C_N<2>

70 64

DP_EXTA_ML_P<3>

9

IN_D3P

OUT_D3P

23

72

DP_SDRVA_ML_C_P<3>

70 64

DP_EXTA_ML_N<3>

10

IN_D3N

OUT_D3N

22

72

DP_SDRVA_ML_C_N<3>

IN

DP_EXTA_DDC_CLK

14

IN_SCL

AC_AUXP

20

72

DP_SDRVA_AUXCH_C_P

BI

DP_EXTA_DDC_DATA

13

IN_SDA

AC_AUXN

19

72

DP_SDRVA_AUXCH_C_N

DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N

16

IN_AUXP

OUT_AUXP_SCL

18

(DP_SDRVA_AUXCH_P)

15

IN_AUXN

OUT_AUXN_SDA

17

(DP_SDRVA_AUXCH_N)

DP_EXTA_HPD

3

IN_HPD

(IPD)

DPSDRVA_I2C_CTL_EN

26

I2C_CTL_EN

DPSDRVA_I2C_ADDR0

36

I2C_ADDR0

DPSDRVA_I2C_ADDR1

35

IN

=I2C_DPSDRVA_SCL

38

BI

SDA_CTL

I2C_ADDR1

DP_A_CA_DET

CEXT

11

REXT

39

AUXDDC_OFF

34

PD

1

R9319 4.99K

2

1% 1/20W MF 201

64

1

U9330

10% 16V X5R-CERM 0201

2

44 44

=T29_WAKE_L:

Mobiles use S4 WAKE# OUT

OMIT 1

T29_LSEO<0>

7

PIO0_2/SSEL/CT16B0_CAP0

IN

=I2C_T29AMCU_SCL

8

PIO0_4/SCL

BI

=I2C_T29AMCU_SDA

9

T29_A_UC_ADDR

PIO0_5/SDA (OD)

65 64 8

OUT

T29DPA_HPD T29_A_BIAS

11

PIO0_7/CTS#

34

OUT

T29_LSOE<0>

12

PIO0_8/MISO/CT16B0_MAT0

34

OUT

T29_LSOE<1>

13

PIO0_9/MOSI/CT16B0_MAT1

OUT

T29_MCU_INT_L

IN

18

PIO0_6/SCK

1

1

2

1 2

65

T29_A_HV_EN_R T29_A_UC_ADDR

64

PIO1_4/AD5/WAKEUP

20

DP_A_EXT_HPD

42 64

PIO1_6/RXD

23

PIO1_7/TXD

24

T29_A_LSX_P2R T29_A_LSX_R2P

PAD

(OD)

XTALIN

4

SWDIO

1

5% 1/20W MF 201

2

5% 1/20W MF 201

5% MF

1/20W 201 1/20W 201

R9362

1

2

1.5K

1

2

1.5K

1

2

201

1.5K

1

VOLTAGE=3.3V

1/20W 201

5% MF

1/20W 201 8 DP_A_BIAS_N_0

51

2

DP_A_BIAS_P_2

5% MF

2 01

MF

2

1/20W 201

5% MF

1/20W 201

MF

2

5%

1/20W


1

5%

1 /2 0W

R9363


51

2

VOLTAGE=3.3V

5% MF

51

1

R9366 8

R9365

201

MF

5%

C

1 1/20W

R9367


2

DP_A_BIAS_P_0 201

51

1

MF

5%

1/20W

PP3V3_SW_DPAPWR

72

DP_SDRVA_ML_P<3>

30

D0-A

72

DP_SDRVA_ML_N<1>

27

D1+A

72

DP_SDRVA_ML_P<1>

26

D1-A

72

DP_SDRVA_AUXCH_P

19

AUX+A

72

DP_SDRVA_AUXCH_N

18

AUX-A HPD_A

1

10K

25

D0+B

T29_A_RSVD_P

24

D0-B

(T29_A_LSX_P2R)

23

D1+B

(T29_A_LSX_R2P)

22

D1-B

T29_D2R1_BIASP T29_D2R1_BIASN

15

AUX+B

14

AUX-B

13

HPD_B

NC 64 65 64 8

DP_A_PWRDWN T29_A_BIAS

2

TQFN

T29_A_RSVD_N

2

2

1

C9391 0.1UF

10% 16V X5R-CERM 0201

2

10% 16V X5R-CERM 0201

5% 1/20W MF 201

D0+ 1 D0- 2

T29DPA_ML_N<3>

OUT

T29DPA_ML_P<3>

BI

65 72 65 72

T29: Unused CRITICAL D1+ 4 D1- 5

T29DPA_ML_N<1>

BI

T29DPA_ML_P<1>

OUT

65 72

B

65 72

T29: LSX_A_R2P/P2R (P/N) AUX+ 6

DP_A_EXT_AUXCH_P

BI

65 72

AUX- 7

DP_A_EXT_AUXCH_N

BI

65 72

T29: RX_1 Bias Sink HPD 8

DP_A_EXT_HPD 1

IN

42 64

R9398 100K

10

SEL

32

AUX_SEL

11

HPD_SEL

LO=Port A HI=Port B

2

5% 1/20W MF 201

THMPAD GND 3 3

8 1 2 2

pin 10 for ML and pin 11 for HPD.

2

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C T29_A_HV_EN

2

OUT

36 65

pull-ups on ML<3>.

U9390

AUX defaults to DP mode

because 100-ohm pull-downs would defeat DP Sink’s detection of DP Source.

5% 1/20W MF 201

P2R = Plug to Receptacle R2P = Receptacle to Plug IN

U9390

DP_SDRVA_HPD

R9399 100K

PI3VEDP212

69 8

C9390 0.1UF

VDD

69 8

1K 5% 1/20W MF 201

D0+A

17

1

R9334

34

R9339


2

5% 1/20W MF 201

S YN C_ DA TE =1 2/ 13 /2 01 0

PAGE TITLE

DisplayPort/T29 A MUXing DRAWING NUMBER

1M

R9336 10K

1K

2 2

R9335

2

similar pinouts. NXP uses pin 10 for ML and HPD, Pericom uses

0x26/0x27 (Wr/Rd) 1

5 2

2

1

VOLTAGE=3.3V

footprint-compatible parts with

1

THRM

1

8 DP_A_BIAS_N_2

8

R9397

1

I2C Addr:

R/PIO0_11/AD0

VSS

65

IN

19

SWCLK/PIO0_10/SCK/CT16B0_MAT2

3

IN

T29DPA_CONFIG2_RC

18

15

(OD)

T29DPA_CONFIG1_RC

17

R/PIO1_2/AD3

14

1.5K

5% MF

R9360

DP_SDRVA_ML_N<3>

5% 1/20W MF 201

5% 1/20W MF 201

16

T29_LSEO<1>

1.5K

GND_VOID=TRUE

1.5K

31

51

2

10K

R/PIO1_1/AD2

6

GND_VOID=TRUE

R9385

DP_A_BIAS

4

R9393

R9338

R/PIO1_0/AD1

PIO1_8/CT16B1_CAP0

(D9361.2)

R9384

R9361

0201

SWDIO/PIO1_3/AD4

(IPU) (OD)

SWCLK

0 5% 1/20W MF 201

HVQFN25

IN

=T29_WAKE_L

R9330

PIO0_1/CLKOUT

10

65

Desktops use PCIe WAKE#

RESET#/PIO0_0

2

65 72

GND_VOID=TRUE

74LVC1G04DBDCK

0201

LPC1112A 1

65 72

OUT

(D9382/D9383)

TSLP-2-7

U9359

5

2

10% 16V X5R-CERM

C9331 0.1UF

OUT

T29DPA_ML_C_N<2> GND_VOID=TRUE

DP Path Biasing

CBTL04DP081 (353S3151) and PI3vEDP212 (353S3055) are 1

T29DPA_ML_C_P<2>

TSLP-2-7

CRITICAL 2

72

2

10% 16V X5R-CERM 0201

TSLP-2-7

1

5% 1/20W MF 201

0.1UF

2

DP/T29 A Low-Speed MUX

Must be 3.3V DP A port power

C9330

2

1

1

Port A MCU

1

1

VOLTAGE=3.3V

R9364

2

1K

OMIT_TABLE

65 72

T29: TX_1

CRITICAL

65 64

51

2

34

DP_SDRVA_ML_N<2>

2

2 2

65 72

IN

Must be 3.3V DP A port power

5% 1/20W MF 201

VDD

IN

(D9360.2)

0201

1 4

PP3V3_SW_DPAPWR

2

SIGNAL_MODEL=T29PIN

0201

THMPAD

5

DP_A_CA_DET

DP_SDRVA_ML_P<2>

72

DP_A_PWRDWN

R9396

Parade (pin is 5V-tolerant).

64

72

2

1/20W 201

T29_D2R_C_N<1>

(D9382/D9383)

6.3V 0201

1

pin. Okay to drive this pin even when VCC=0V per

DP_A_PWRDWN

6.3V 0201

2 20% X5R

1/20W 201

5% MF


0201

R9392

CRITICAL

17

20% X5R

5% MF

T29_D2R_C_P<1>

GND_VOID=TRUE

9 0 6 2 2 2 1 1 9 3

10% 16V X5R-CERM 1

0.1UF

1

BAR90-02LRH

high while Vcc = 0V.

10% 16V X5R-CERM

0.1UF

C9368

2

(D9360/D9361)

used by PS8301 during training.

C9369

2

1

SIGNAL_MODEL=EMPTY

IC supports input

64

1

1.5K

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

D9361

1/20W 201

2

0.1UF

1.5K

R9375

SC70

2

10% 16V X5R-CERM 1

R9374

3

10% 16V X5R-CERM

1

D

GND_VOID=TRUE

2

BAR90-02LRH

D9383 5% MF

6.3V 0201

2

(IPD)

3 3

D9382

AUXCH Snoop Port,

IN

20% 6.3V CERM 402-LF

65 64

DP_SDRVA_ML_N<0>

2

0.1UF

C9366

1

BAR90-02LRH

=PP3V3_S0_DPSDRVA

0201

65 72

(D9365.2)

2

1

~150K pull-down on PD

2

DP_SDRVA_ML_P<0>

72

2.2UF

GND

D9360

1/20W 201

C9359 1

PS8301 has internal

0

72

(IPD)

6

5% MF

2

C9319 1

DP_A_PWRDWN_R

A

1

5% 1/20W MF 201

10% 16V X5R-CERM 1

0.1UF

C9367

DPSDRVA_CEXT

SCL_CTL

12

SDRV_PD 1

1

PLACE_NEAR=U9310.11:2 mm

DPSDRVA_REXT

5% 1/20W MF 201

(DP_SDRVA_HPD)

32

(IPD)

=I2C_DPSDRVA_SDA

R9318

31

CA_DET

1

65 72

OUT

(D9372/D9373)

(All 4 D’s)

10% 6.3V X5R 201

0.1UF

C9362

(IPD)

DP_AUXCH_ISOL_R

5% 1/20W MF 201

OUT_HPD

(IPU)

C9363

OUT

T29DPA_ML_C_N<0>

GND_VOID=TRUE

CRITICAL

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

6.3V 0201

DP_SDRVA_ML_C_P<0>

72

2

1

2

30

DP_EXTA_ML_N<1>

R9390 0

OUT_D0P

DP_EXTA_ML_P<1>

37

44

DP_AUXCH_ISOL

CRITICAL

DP_EXTA_ML_N<0>

OUT

T29_R2D_N<1>

R9383

20% X5R

0.22UF 1

T29DPA_ML_C_P<0>

GND_VOID=TRUE TSLP-2-7

SIGNAL_MODEL=T29PIN

0.1UF

70 64

5% 1/20W MF 201

44

IN_D0P

T29_R2D_P<1>

72

1.5K

2

0.22UF

2

1/20W 201

2

D9364/D9365:

GND_VOID=TRUE

20% X5R 1

C9361

65 72

TSLP-2-7 1

2

0.22UF

2

70 64

70 64

R9312

B

1

DP_EXTA_ML_P<0>

R9310

1K

64

1

C9360

270

70 64

70 64

IN

1

2

72

2

20% 4V CERM-X5R-1 201

0.22UF

C9365

65 72

IN

(D9364.2) T29: TX_0

TSLP-2-7

D9372/D9373:

SIGNAL_MODEL=EMPTY

20% 4V CERM-X5R-1 201

1

1

GND_VOID=TRUE

C9364

2

(All 4 D’s)

R9382

1.5K

2

QFN

so only 94/B4 are

23 16

5% MF

VDD

30

DP_SDRVA_ML_R_N<0>

2

1

BAR90-02LRH

201

PS8301TQFN40GTR-A2

devices use 96/B6,

2

2

U9310

Note: Other Parade

1

2 MF

1

1/20W 201

R9351

1 0 2 4

10% 16V X5R-CERM 0201

Addr (W/R)

1

1

30

DP_SDRVA_ML_R_P<0>

72

2

C9312 0.1UF

2

30

1/20W

R9350

D9365

1/20W 201

GND_VOID=TRUE

20% 4V CERM-X5R-1 201

T29_A_BIAS_R2DN1

IN

5% MF

1

72

1

BAR90-02LRH

2

IN

T29_D2R_C_N<0>

TSLP-2-7

20% 4V CERM-X5R-1 201

1

C9383 (C9383.2)

2

transitions from high to low.

=PP3V3_S0_DPSDRVA

D9373

1

T29_D2R_C_P<0>

GND_VOID=TRUE

2

0.47UF

T29_R2D_C_P<1>

IN

30

270

64 7

BAR90-02LRH

T29_R2D_N<0> GND_VOID=TRUE

GND_VOID=TRUE

0.47UF R9308/R9309 maintain bias on C9308/C9309

2

D9372

T29_R2D_P<0>

2

2

1

C9382

64 70

1

1

1

BAR90-02LRH

SIGNAL_MODEL=EMPTY

1.5K

R9373

0.47UF

C9381

0201

R9308

C9380

1/20W 201

72

T29 Path Biasing

(C9380/C9381)

5% MF

72

2

20% 4V CERM-X5R-1 201 GND_VOID=TRUE

0.47UF

0.47UF

0201

2

2

T29_A_BIAS_R2DP1

7 64

1/20W 201

1

SIGNAL_MODEL=EMPTY

2

1M 70 8

=PP3V3_S0_DPSDRVA

0201

R9309

2

20% 4V CERM-X5R-1 201

1

R9372

1.5K

P/N-swapped after AC

64 70

0201

10% 16V X5R-CERM

0.1UF

1

D9364

GND_VOID=TRUE

20% 4V CERM-X5R-1 201

T29_A_BIAS_R2DN0

GND_VOID=TRUE 70 8

20% 4V CERM-X5R-1 201

0.47UF

8

1

2

GND_VOID=TRUE

C9373

T29 signals are

64 70

0201

10% 16V X5R-CERM

0.1UF

2

T29 A High-Speed Signals

2

1

C9372

(C9373.2) 70 8

1

0.47UF

C9371

0.47UF

10% 16V X5R-CERM 1

0.1UF

DP_EXTA_ML_N<0> 0201

2

0.1UF

64 70

0201

2

10% 16V X5R-CERM

0.1UF

3

T29_A_BIAS_R2DP0

IN

GND_VOID=TRUE

DP_EXTA_ML_P<0>

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

93 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

3.3V/HV Power MUX 64

7

=PPHV_SW_DPAPWRSW 20V Max

CRITICAL

R9416

C9410 1

470K 5% 1/20W MF 201

10% 50V X7R 603-1

11

VOUT

18.3ms

13.4ms

26.7ms

470ms

235ms

724ms


1

U9410

2

935mA

TFLT

QFN

16 EN*

1A (*)

2

FLT* 15

C9411 10% 50V X7R 603-1

MM MM

SM 1

R9427

2

1% 1/20W MF 201

TP_DPAPWRSW_FLT_L

DPAPWRSW_ILIM DPAPWRSW_IFLT

5% 1/20W MF 201

R9428

1

1

2

1% 1/20W MF 2 201

R9411

1% 1/20W MF 201

R9424

1

5% 1/20W MF 201

G

1

S

5

OUT

5 2

ZXRE060A

2

2


1

1

OUT OUT

2

5% 1/20W MF 201

1

2

2

1K 5% 1/20W MF 201

T29_A_BIAS_R

OUT

VOLTAGE=3.3V

8

8

IN

T29_A_BIAS_D2RP1

8

IN

T29_A_BIAS_D2RN1

72 64 72 64

BI

T29DPA_ML_P<3>

BI

T29DPA_ML_N<3>

R9498

2

2

2.2K 5% 1/20W MF 201

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE 72 64

OUT

72 64

OUT

R9499 2.2K

1

2

BAR90-02LRH

D9499 BAR90-02LRH

1

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

2

10% 50V X7R 402

OUT

T29DPA_HPD

OUT

T29DPA_CONFIG1_RC

64

OUT

T29DPA_CONFIG2_RC 1

1

R9451 1M

2

2

5% 1/20W MF 201

2

10K 5% 1/20W MF 201

T29_A_HV_EN

DP Dir

DP Dir

CRITICAL

16 20

1

C9405 1

2

12

GND_DPA1_R1

2

72

HOT_PLUG_DETECT

GND

CONFIG1

ML_LANE0P

CONFIG2

ML_LANE0N

GND

GND

ML_LANE3P

ML_LANE1P

ML_LANE3N

ML_LANE1N

GND

GND

AUX_CHP AUX_CHN DP_PWR

ML_LANE2P ML_LANE2N RETURN

1 3 5

GND_VOID=TRUE

GND_VOID=TRUE

C9470

7 9

1

C9471

12

2

1

12 5% 1/20W MF 201

10% 6.3V X5R 201

2

2

C9499

C9495 10% 16V X7R 201

C9402 1

High: 2.0 - 5.0V Low:

0 - 0.8V

1

0.01UF 10% 50V X7R 402

64 72

IN

64 72

T29DPA_ML_P<1>

IN

64 72

T29DPA_ML_N<1>

BI

T29DPA_ML_C_P<2>

IN

64 72

T29DPA_ML_C_N<2>

IN

64 72

R9471 470K

5% 1/20W MF 201

2

5% 1/20W MF 201

B

64 72

T29: LSX_R2P/P2R (P/N)

15 17 19

(Both C’s)

C9472

C9401 0.01UF

2

2

10% 50V X7R 402

1

2

20% 4V CERM-X5R-1 201

0.47UF

T29DPA_ML_P<2> T29DPA_ML_N<2>

C9473

1

2

20% 4V CERM-X5R-1 201

0.47UF GND_VOID=TRUE

L9408

1

FERR-120-OHM-3A

R9401 1

12 5% 1/20W MF 201

2

GND_DPACONN_19

1


GND_VOID=TRUE 1

R9472 470K

2 0603 2

R9473 470K

5% 1/20W MF 201

2

5% 1/20W MF 201

R9408 1

12 5% 1/20W MF 201

2

470k R’s for ESD protection on AC-coupled signals.

SYNC_MASTER=K78_MLB 1

R9441 100K

2

Sink HPD range:

1

R9470

T29: TX_1


5% 50V CERM 402

IN

T29DPA_ML_C_N<0>

GND_VOID=TRUE

470K

2

T29DPA_ML_C_P<0>

8

T29DPA_HPD_R

5% 1/20W MF 201

GND_VOID=TRUE

to 100K (DPv1.1a). 1

330PF 2

2

20% 4V CERM-X5R-1 201

11

R9402 1

1

DPACONN_20_RC

10% 16V X7R 201

2

20% 4V CERM-X5R-1 201

1

0.47UF

R9406

2GND_DPA7_R 1

72

SIGNAL_MODEL=EMPTY

330PF

1

0.47UF

T29DPA_ML_P<0> T29DPA_ML_N<0>

0.1UF

GND_DPACONN_7 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

72

30PF

2

(Both C’s)

5% 1/20W MF 201

10% 6.3V

X5R T29201 Dir

SHIELD PINS

L9499

2

C

R9405

0.1UF

72

T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N

2

1

2

DPAPWR_FB_DIV

GND_VOID=TRUE

GND_VOID=TRUE

650NH-5%-0.430MA-0.052OHM

C9494 1

36 64 65

Circuit threshold range: 2.877-2.941V (2.903V nominal)


CRITICAL

2

1

24.9K

GND_VOID=TRUE

L9498

greater than or equal

1M

2

1% 1/20W MF 201

R9432

R9436

GND_DPACONN_1

18

down HPD input with

5% 1/20W MF 201

1

1


0603

CRITICAL

DP Source must pull

R9452

2

100K 1

8 7 6 5 4 3 2 1 2 2 2 2 2 2 2 2

30PF

2

R9435

5% 1/20W MF 201

DPAPWRSW_HV_DET

2

2

6

72

GND

5% 1/20W

0603

C9498 1

64

1

R9437

4

C9406

0603

64

PGND

2

1

2

PP3V3RHV_SW_DPAPWR

4

10% 16V X5R-CERM 0201

FB

MF

2

5% 50V CERM 402

4

201

5% 1/20W MF 201

CRITICAL

DP_A_EXT_AUXCH_N

1

G

GND_VOID=TRUE

GND_VOID=TRUE SIGNAL_MODEL=T29PIN

DP_A_EXT_AUXCH_P

4

S

T29: TX_0

(Both L’s)

A

1K

R9495

TSLP-2-7

BI

SOT563

S

F-RT-TH

72

BI

10% 10V X5R 402

SOT353

DisplayPort/T29 A Connector

12

72 64

ZXRE060A

5% 1/20W MF 201

10

72 64

1UF

Q9430 SSM6N37FEAPE

G

220

SIGNAL_MODEL=EMPTY

TSLP-2-7

D

C9435 0.1UF

2

NO STUFF

0.01UF

2

T29_D2R_C_P<1> T29_D2R_C_N<1>

3

R9433

650NH-5%-0.430MA-0.052OHM

2

1

10% 16V X5R-CERM 0201

14

1

6

MF 201

L9400

C9400 1

S

SIGNAL_MODEL=T29PIN

D9498

GND_VOID=TRUE

1

3

IN

OUT

DPAPWRSW_NPN_E

FERR-120-OHM-3A

PP3V3RHV_SW_DPAPWR_UF

SIGNAL_MODEL=EMPTY

5% 1/20W MF 201

5

DPAPWRSW_ON_C

C9429

SIGNAL_MODEL=EMPTY 1

3

SOT563

5

6

T29: Unused

1

D

SSM6N37FEAPE

5

1K

SIGNAL_MODEL=EMPTY

T29_A_BIAS

82

13

B

2

SOT363

GND_VOID=TRUE 1

20% 6.3V POLY-TANT CASE-B2-SM

CRITICAL

Q9426

J9400

R9494

2

65 64 8

MDP-K21-K78

51

2

C9487 100UF

20% 6.3V X5R-CERM-1 603

MMDT3946XG

5% 1/20W MF 201

Q9419

1

GND_VOID=TRUE

2

D

CRITICAL 1

22UF

5% 1/20W MF 201

Q9430

R9429

T29_D2R_C_P<0> T29_D2R_C_N<0>

R9490

C9480

U9435

0.595-0.605V (0.600V nominal)

T29 Dir 72 64

2

1

DPAPWRSW_P3V3_ON

1

10% 6.3V X5R 201 72 64

2

10% 16V X5R-CERM 0201

4.7K

2

0.1UF

DMB53D0UV

HIGH and T29_A_HV_EN


0.1UF

10% 16V X5R-CERM 0201

1% 1/20W

D

is LOW.

2

62

R9430

R9418

DPAPWRSW_HV_DET is

0.1UF

C9481 1

0.1UF

NO STUFF

1

G

2

C9490

IN

6

T29_A_HV_EN

T29_A_BIAS

IN

C9485

CERM-X5R 10% 6.3V

Circuit threshold range: 3.363-3.439V (3.395V nominal)

DPAPWR_BLDR_E

1

4 1

7

=DPAPWRSW_EN

DPAPWRSW_HV_DET_L

SOT353

FB GND PGND

ZXRE060A REF range:

Note: Bleeder active when 65 64 8

2

0.47UF

2

5% 1/20W MF 201

DPAPWRSW_HV_DET_R_L

SOT-563

IN

1

DPAPWR_BLDR_B

4

1% 1/20W MF 201

65 64 36

C9424

1

R9426 1K

SOT-563

R9419 2

1

4.7K

2

P = ~27mW 249

1

DMB53D0UV

3

2.5V / 249 ohm = 10mA

1

or HV_EN high.

CRITICAL

3

Q9419

Bleeder Resistor

2

20% 6.3V X5R 603

3.3V Always

G

DPAPWRSW_P3V3_ON_L

402

U9426

C

4

CRITICAL

C9486 1

2

2

1 2

10% 16V X5R-CERM 0201

= CCT * 100000

EN

C9436 1

0.1UF

TFLT = CCT * 38900

=PP3V3_S4_DPAPWRSW 5

GND 2

D

1

C9426 1

ILIM = 201k / RLIM = 935mA

TSD

3 OC*

T29_A_HV_EN

when Source >3.4V

2

2

3

SOD-VESM-HF

S

Blocking FET, off

1

4.7K

1

22 5% 1/20W MF 201

IN

IFLT = 200k / RFLT = 885mA D

65 64 36

IN

3

21.5K

210K

100K

Q9415

Q9425

SOT23

BGA

DPAPWRSW_VREF

R9410

7 1

2 402

SSM3K15FV

CRITICAL SI8409DB

DPAPWR_ON_L_C

PAD

5 3 4 1 1

5% 1/16W MF-LF

3.7A @ 70C

100K

IFLT 8 THRM

0

Id(max):

R9425

D9410

ILIM 7

R9412

65mOhm @ 2.5V Vgs

4

STPS2L30AF

9 CT

1

Rds(on):

1 OUT

10UF

VOLTAGE=15V

6 RTRY*

GND

-1.4V

3.3V/HV MUXed

(IPU-Weak!)

DPAPWRSW_CT

Vgs(th):

CRITICAL

0.1UF

SN1010017

DPAPWRSW_HVEN_L_R

925mA

PPHV_SW_DPAPWR

12

4

0.1UF

2

VIN

3

1

894mA (*)

wake from T29 devices.

TPS2065DBV

DFLS1100

(*) U9410 tolerance unknown

10

2

876mA

ILIM TSD

SN1010017 1

Max

DP_PWR must be S4/S5 to support

1

U9480

Vgs(max): +/-12V Min

885mA

2

Vds(max): -30V

Nominal IFLT

CRITICAL

POWERDI-123

SI8409DB:

Port A HV Power Switch

D

Port A 3.3V Power Switch

CRITICAL D9425

PP3V3_SW_DPAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

1

5% 1/20W MF 201


PAGE TITLE

DisplayPort/T29 A Connector DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

94 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

PPBUS S0 LCDBkLT FET

MOSFET

FDC638APZ

CHANNEL

P-TYPE

RDS(ON)

43 mOhm @4.5V

LOADING

0.65 A (EDP)

CRITICAL Q9706 FDC638APZ_SBMS001 SSOT6-HF

F9700

D

1

=PPBUS_S0_LCDBKLT


5

2

1

1

7

3

10%

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

=PP5V_S0_BKL


16V

1/20W

X5R

MF

CRITICAL

2

CRITICAL

L9701

402

201

D9701

15UH-2.8A LCDBKLT_EN_DIV 8

=PPBUS_SW_BKL

1

C9712 1

1

10% 25V X5R 805

1/20W MF 201

PIMB053T-SM

C9713 0.1UF

10UF

1%

SOD-123 2

CRITICAL

R9789 147K

2

D

FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

ON THE SENSOR PAGE

0.1UF

1%

1

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE

AND PPBUS_SW_BKL

C9782 1

R9788 301K

2


2

mm

MIN_NECK_WIDT H=0.25 mm VOLTAGE=12.6V

603-HF

BOTTOM

THERE IS A SENSE RESISTOR BETWEEN

4

PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4

8 66


6

3AMP-32V-467 7

2

2


10% 25V X5R 402

PPBUS_SW_LCDBKLT_PWR_SW

1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.37 5 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE

2

PLACE_NEAR=U9701.A5:3mm

PPVOUT_SW_LCDBKLT CRITICAL

RB160M-60G

1

C9796

1

220PF 2


10% 50V X7R-CERM 402

CRITICAL

C9797

1

10UF 2

C9799

6 63


10UF

10% 50V X5R 1210-1

2

10% 50V X5R 1210-1

PLACE_NEAR=D9701.2:5mm

LCDBKLT_EN_L

PLACE_NEAR=D9701.2:3mm PLACE_NEAR=U9701.D1:5mm

Q9707

D

8

IN

G

C9714

1UF 10% 25V X5R 603-1

SOT563

5

PLACE_NEAR=U9701.D1:3mm

1

C9710 1

3

SSM6N15FEAPE

S

7

4

10%

XW9720 SM

201 PPVOUT_SW_LCDBKLT_FB VOLTAGE=50V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM

=PP3V3_S0_BKL_VDDIO

LCD_BKLT_EN

PLACE_NEAR=U9701.C4:4mm

LCDBKLT_DISABLE

Q9707

0.01UF 2 10V X5R

2

1

2


C9711 1 D

0.1UF 6

10% 6.3V 2 X5R 201

SSM6N15FEAPE SOT563

C

C 2

25

IN

G

S

1

BKLT_PLT_RST_L

4 C

1 D

1 C

VDDIO VLDO

VIN

U9701 25-BUMP-MICRO

R9741 R9753 44

IN

1

=I2C_BKL_1_SCL

44

BI

=I2C_BKL_1_SDA

1

Addr: 0x58(Wr)/0x59(Rd)

2

1

R9731 1% 1/20W MF 201

R9704 8

IN

LCD_BKLT_PWM

1

33

FILTER

BKL_ISET

B3

BKL_SCL

R9715

D3

1

FSET

B2

FB

A5

BKLT:PROD

R9717 PLACE_NEAR=U9701.E5:10mm

SCLK

OUT1

E5

BKL_ISEN1

D4

SDA

OUT2

D5

BKL_ISEN2

BKL_PWM

A4

PWM

OUT3

C5

BKL_ISEN3

A3

EN

OUT4

E3

BKL_ISEN4

OUT5

E2

BKL_ISEN5

OUT6

E1

BKL_ISEN6

C3

1% 1/20W MF

FAULT

S _ D N G 5 B

Fpwm=9.62kHz

L _ D N G 4 E

R9716

R9755

1

2

1% 1/20W MF 201

5% 1/20W MF 201

1

2

OUT

6 63

0

LED_RETURN_2

2


OUT

6 63

OUT

6 63

OUT

6 63

OUT

6 63

OUT

6 63

BKLT:PROD

W W S S _ _ D D N N G G

B

R9719 PLACE_NEAR=U9701.C5:10mm

1


1 2 A A

0

LED_RETURN_3

2


5% 1/16W MF-LF 402

BKLT:PROD

1

R9714

R9720

18.2K

2


5% 1/16W MF-LF 402

BOTTOM

BOTTOM

90.9K

10K

LED_RETURN_1

2

R9718 PLACE_NEAR=U9701.D5:10mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

I_LED=20.3mA 1

0 5% 1/16W MF-LF 402

BKLT:PROD

see spec for others

5% 25V NP0-C0G 201

1

BOTTOM

100K

C9704

B1

SW_1


PLACE_SIDE=BOTTOM

33PF 2

ISET

SW_0 0 5 5 8 P L

BKL_EN

TP_BKL_FAULT

1

B4

2 201

2

5% 1/20W MF 201

VSYNC

C2

BKL_FSET

2

200K

B

D2

BKL_FLTR

BKL_SDA

5% 1/20W MF 201


66 8

2

5% 1/20W MF 201

2

5% 1/20W MF 201

R9757 0

0

10K

1

BKL_VSYNC_R

PLACE_NEAR=U9701.E3:10mm

1% 1/20W MF 201

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

XW9710 SM

GND_BKL_SGND

1

1


0

LED_RETURN_4

2


5% 1/16W MF-LF 402

BOTTOM 2

BKLT:PROD



I_LED=369/Riset

1


(EEPROM should set EN_I_RES=1)

0

LED_RETURN_5

2


5% 1/16W MF-LF 402

BOTTOM

BKLT:PROD


1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BOTTOM

A

PART NUMBER

QTY

DESCRIPTION

103S0198

3

RES,THIN

FLIM,1/16W,10.2

OHM,0.1,0402,SM

103S0198

3

RES,THIN

FLIM,1/16W,10.2

OHM,0.1,0402,SM

REFERENCE DES

R9717,R9718,R9719

R9720,R9721,R9722

CRITICAL

BOM OPTION

0

LED_RETURN_6

2


5% 1/16W MF-LF 402


BKLT:ENG

10.2 ohm resistors for current

BKLT:ENG

measurement on LED strings.

S YN C_ DA TE =0 1/ 16 /2 01 1

PAGE TITLE

LCD Backlight Driver DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

97 OF 109

A

8

7

www.laptopblue.vn

6

5

CPU Signal Constraints

4

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

CPU_50S

*

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD TABLE_PHYSICAL_RULE_ITEM

*

CPU_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD


*

CPU_27P4S

3

2

1

CPU Net Properties

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

7 MIL

7 MIL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

P HY SI C AL

S PA CI NG

DMI_S2N_P<3:0> DMI_S2N_N<3:0> DMI_N2S_P<3:0> DMI_N2S_N<3:0>

D MI _S 2N

P CIE _8 5D

PCIE

D MI _S 2N

P CIE _8 5D

PCIE

D MI _N 2S

P CIE _8 5D

PCIE

D MI _N 2S

P CIE _8 5D

PCIE

FDI_DATA

PCIE_85D

PCIE

FDI_DATA

PCIE_85D

PCIE

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

FDI_DATA_P<7:0> FDI_DATA_N<7:0> FDI_FSYNC<1..0> FDI_LSYNC<1..0>

CPU_50S

CPU_AGTL

FDI_INT

9 17

PCIE

CPU_PECI

10 19 41

CPU_AGTL

PM_SYNC PM_MEM_PWRGD

9 17 9 17 9 17 9 17

TABLE_PHYSICAL_RULE_ITEM

CPU_XDP_BPM

TOP,BOTTOM

100 MIL

100 MIL

100 MIL

100 MIL

=CPU_50S

=CPU_50S

=CPU_50S

=CPU_50S

=STANDARD


*

CPU_XDP_BPM

=CPU_50S

=CPU_50S

NOTE: CPU_XDP_BPM physical constraint is to prevent routing on outer layers.

D

NOTE: 7 mil gap is

for VCCSense pair, which Intel says to route with

LAYER

LINE-TO-LINE

9 17 9 17

D

9 17

7 mil spacing without specifying a target impedance. TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

9 17

SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

CPU_AGTL

*

=STANDARD

?

CPU_8MIL

*

8 MIL

?

CPU_COMP

*

20 MIL

?

CPU_ITP

*

=2:1_SPACING

?


CPU_AGTL

TOP,BOTTOM

=2x_DIELECTRIC

CPU_PECI

CPU_50S

PM_SYNC

CPU_50S

PM_MEM_PWRGD

CPU_50S

CPU_AGTL

CPU_50S

CPU_ITP

XDP_DBRESET_L

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

?



10 17 10 17 26



CPU_VCCSENSE

*

Some signals require 27.4-ohm single-ended impedance. SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG

v1.0 Section 2.7

PCI-Express

CPU_SM_RCOMP

CPU_27P4S

CPU_SM_RCOMP

CPU_27P4S

CPU_SM_RCOMP

CPU_27P4S

CPU_COMP CPU_COMP


PHYSICAL_RULE_SET

LAYER


PCIE_85D

*

=85_OHM_DIFF

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

CPU_CATERR_L

CPU_COMP

CPU_50S

CPU_ITP

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL


CLK_PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

CPU_PROCHOT_L TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

*

=3X_DIELECTRIC

?

CPU_PWRGD

PM_EXT_TS_L<0> PM_EXT_TS_L<1> CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2> CPU_CFG<11..0> CPU_CATERR_L CPU_VCCIO_SEL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_PROCHOT_L CPU_PWRGD

CPU_50S

CPU_8MIL

PM_THRMTRIP_L

CLK_PCIE

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N DPLL_REF_CLKP DPLL_REF_CLKN ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N



PCIE

10 23 25

?

25 MIL

Most CPU signals with impedance requirements are 50-ohm single-ended.

10 23 10 23

10 10 10

9 23 10 12

10 42 57 10 19 23


PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

PM_THRMTRIP_L

10 19


C

CLK_PCIE

*

20 MIL

?

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG

v1.0 Section 2.7

DMI_CLK100M

CLK_PCIE_90D

DMI_CLK100M

CLK_PCIE_90D

DPLL_REF_CLK120M

CLK_PCIE_90D

DPLL_REF_CLK120M

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

I TP CP U_ CL K1 00 M

CLK_PCIE_90D

C LK _PC IE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

CPU_27P4S CPU_27P4S

XDP_TDI

B

CLK_PCIE CLK_PCIE

CPU_COMP

CPU_COMP

CPU_50S

CPU_ITP

XDP_TDO

CPU_50S

CPU_ITP

XDP_TMS

CPU_50S

CPU_ITP

XDP_TCK

CPU_50S

CPU_ITP

XDP_TRST_L

CPU_50S

CPU_ITP

XDP_BPM_L

XDP_BPM_R_L

CPU_XDP_BPM CPU_50S

CPU_ITP CPU_ITP

(FSB_CPURST_L)

CPU_50S

CPU_ITP

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

C PU _V CC AX G_ SE NS E

C PU _V CC SE NS E

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VALSENSE CPU_VALSENSE

CPU_27P4S

CPU_27P4S

CPU_VCCSENSE CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCAXG_SENSE

CPU_VCCSENSE

CPU_27P4S

CPU_VCCAXG_SENSE

CPU_VCCSENSE

CPU_VCCSENSE

C PU _S VI DA LER T_ L

CPU_50S

C PU _CO MP

CPU_SVIDSCLK

CPU_50S

CPU_COMP

CPU_SVIDSOUT

CPU_50S

CPU_COMP

EDP_COMP CPU_PEG_COMP

XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TCK XDP_CPU_TRST_L XDP_BPM_L<7..0> CPU_CFG<15..12> XDP_CPURST_L

CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N CPU_AXG_SENSE_P CPU_AXG_SENSE_N CPU_VDDQ_SENSE_P CPU_VDDQ_SENSE_N CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

C

10 16 10 16 10 16 10 16 10 16 10 16 16 23 16 23 23 23

9 9

10 23 10 23 10 23 10 23 10 23 10 23

9 23 23

12 57

B

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

12 57 12 59 12 59

12 57 12 57

12 12

9 9 9 9

CPU_VIDALERT_L CPU_VIDSCLK CPU_VIDSOUT

12 57 12 57 12 57

A

SYNC_MASTER=K21_CONSTRAINTS


PAGE TITLE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PEG_R2D_P<15..0> PEG_R2D_N<15..0> PEG_R2D_C_P<15..0> PEG_R2D_C_N<15..0> PEG_D2R_P<15..0> PEG_D2R_N<15..0> PEG_D2R_C_P<15..0> PEG_D2R_C_N<15..0>

CPU Constraints DRAWING NUMBER

Apple Inc.

8 8 8 8

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

100 OF 109

A

8

7

www.laptopblue.vn

6

5

Memory Bus Constraints

4


PHYSICAL_RULE_SET

LAYER


MEM_37S

*

=37_OHM_SE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



=37_OHM_SE

=37_OHM_SE

=37_OHM_SE

=STANDARD

=STANDARD

*

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD

PHYSICAL

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=55_OHM_SE


*

MEM_72D

1

SPACING

MEM_A_CLK

MEM_72D

MEM_CLK

MEM_A_CLK

MEM_72D

MEM_CLK

MEM_A_CTRL

MEM_55S

MEM_CTRL


MEM_55S

2

NET_TYPE



MEM_40S

3

Memory Net Properties

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

Y

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

M EM _A _C TR L

M EM _5 5S

MEM_CTRL

M EM _A _C TR L

M EM _5 5S

MEM_CTRL

MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0> MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0>

8 11 27 28 32 8 11 27 28 32

8 11 27 28 32 8 11 27 28 32 8 11 27 28 32


MEM_50S

TOP,BOTTOM

MEM_A_CMD

MEM_55S

MEM_CMD

MEM_A_CMD

MEM_55S

MEM_CMD


D

MEM_85D

TOP,BOTTOM

Y

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

MEM_50S

ISL3,ISL4,ISL9,ISL10

Y

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM

=STANDARD

MEM_A_CMD

MEM_55S

MEM_CMD

MEM_A_CMD

MEM_55S

MEM_CMD

MEM_A_CMD

MEM_55S

MEM_CMD


MEM_85D

ISL3,ISL4,ISL9,ISL10

Y

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

MEM_A_DQ_BYTE0

Memory to Power Spacing TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

C

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

MEM_PWR

*

MEM_2PWR

MEM_CTRL

MEM_PWR

*

MEM_2PWR

TABLE_SPACING_ASSIGNMENT_ITEM

Spacing Rule Sets TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE

*

MEM_2PWR

MEM_PWR

*

MEM_2PWR

MEM_PWR

*

MEM_2PWR

MEM_CMD

MEM_PWR

MEM_DATA

MEM_DQS


MEM_CLK2CLK

*

0.6 MM

?

*

0.2 MM

?



MEM_CTRL2CTRL



MEM_CMD2CTRL

*

0.2 MM

?

MEM_CMD2CMD

*

0.2 MM

?


Memory to GND Spacing


MEM_DATA2DATA

*

0.14 MM

?

*

0.4 MM

?

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

*

MEM_2GND


MEM_DQS2DQS

*

GND

MEM_CTRL

*

GND

*


?

=PWR_P2MM

MEM_CMD

*

GND

MEM_2GND


*

MEM_2GND

=GND_P2MM

*

?

MEM_DATA

*

GND

MEM_2GND TABLE_SPACING_ASSIGNMENT_ITEM

?

0.6 MM

MEM_DQS

*

GND

MEM_2GND

Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE


MEM_CLK

*

MEM_CLK

MEM_CLK2CLK

B

*

MEM_CTRL

MEM_CMD

*

MEM_CLK

MEM_CMD

*

MEM_CTRL


MEM_CMD

*

MEM_MEM2OTHERMEM

MEM_CLK

MEM_DATA

*

MEM_MEM2OTHERMEM

MEM_CMD

MEM_CMD

*

MEM_CMD2CMD

MEM_CMD

MEM_DATA

*

MEM_MEM2OTHERMEM



*

MEM_DQS


MEM_MEM2OTHERMEM

MEM_CMD

*

MEM_DQS


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

*

MEM_MEM2OTHERMEM

MEM_CLK

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

*

MEM_MEM2OTHERMEM


MEM_DATA

MEM_CLK


MEM_CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CMD

*


MEM_CTRL2CTRL

MEM_DATA

MEM_CTRL

*

MEM_MEM2OTHERMEM

MEM_DATA

MEM_CMD

*

MEM_MEM2OTHERMEM



MEM_CMD2CTRL TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_DATA

*

MEM_MEM2OTHERMEM

MEM_CTRL

MEM_DQS

*

MEM_MEM2OTHERMEM


MEM_DATA

MEM_DATA

*

MEM_DATA

MEM_DQS

*


NET_SPACING_TYPE2 MEM_CLK

AREA_TYPE

SPACING_RULE_SET

*

MEM_MEM2OTHERMEM

NET_SPACING_TYPE1

MEM_CTRL

*

NET_SPACING_TYPE2

AREA_TYPE

*

*

MEM_CTRL

*

*


MEM_CMD

*

MEM_MEM2OTHERMEM

MEM_DQS

MEM_DATA

*

MEM_MEM2OTHERMEM

MEM_DQS

MEM_DQS

*

MEM_DQS2DQS

MEM_A_DQ_BYTE5

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE7

MEM_50S

MEM_DATA

MEM_A_DQS0

MEM_85D

MEM_DQS

MEM_A_DQS0

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_85D

MEM_DQS

MEM_A_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS5

MEM_85D

MEM_DQS

MEM_A_DQS5

MEM_85D

MEM_DQS

MEM_A_DQS6

MEM_85D

MEM_DQS

MEM_A_DQS6 MEM_A_DQS7

MEM_85D MEM_85D

MEM_DQS MEM_DQS

MEM_A_DQS7

MEM_85D

MEM_DQS

MEM_B_CLK

MEM_72D

MEM_CLK

MEM_B_CLK

MEM_72D

MEM_CLK

MEM_B_CTRL

MEM_55S

MEM_CTRL

MEM_B_CTRL

MEM_55S

MEM_CTRL

MEM_B_CTRL

MEM_55S

MEM_CTRL

MEM_B_CMD

MEM_55S

MEM_CMD

MEM_B_CMD

MEM_55S

MEM_CMD

MEM_B_CMD

MEM_55S

MEM_CMD

MEM_55S

MEM_CMD

MEM_B_CMD

MEM_55S

MEM_CMD

M EM _B _D Q_ BY TE 0 MEM_B_DQ_BYTE1

MEM_50S MEM_50S

M EM _DA TA MEM_DATA

M EM _B _D Q_ BY TE 2

MEM_50S

M EM _DA TA


MEM_50S

M EM _DA TA


MEM_50S

M EM _DA TA


MEM_50S

M EM _DA TA

MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7

MEM_50S MEM_50S

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS1

MEM_85D

MEM_DQS

MEM_B_DQS1

MEM_85D

MEM_DQS

MEM_B_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

11 27 28 32

11 27 11 27 11 27 11 27 11 28 11 28 11 28 11 28

11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 27 11 28 11 28 11 28 11 28 11 28 11 28

C

11 28

MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0>

11 28

MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0> MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

8 11 29 30 32 8 11 29 30 32

8 11 29 30 32 8 11 29 30 32 8 11 29 30 32

8 11 29 30 32 11 29 30 32 11 29 30 32

M EM _B _D QS 2 MEM_B_DQS3

M EM _8 5D MEM_85D

M EM _B _D QS 3

M EM _8 5D

M EM _B _D QS 4

M EM _8 5D

MEM_B_DQS4 M EM _B _D QS 5

MEM_85D M EM _8 5D

MEM_DATA MEM_DATA

MEM_DQS MEM_DQS MEM_DQS M EM _D QS MEM_DQS M EM _D QS

MEM_B_DQS5

MEM_85D

M EM _B _D QS 6 MEM_B_DQS6

M EM _8 5D MEM_85D

MEM_DQS MEM_DQS

M EM _B _D QS 7

M EM _8 5D

MEM_DQS

MEM_B_DQS7

MEM_85D

MEM_DQS

MEM_DQS

MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56>

11 29 30 32 11 29 30 32

MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

11 29 11 29 11 29 11 29 11 30 11 30 11 30 11 30

11 29 11 29 11 29

B

11 29 11 29 11 29 11 29 11 29 11 30 11 30 11 30 11 30 11 30 11 30 11 30

MEM_2OTHER

MEM_PWR MEM_PWR MEM_PWR MEM_PWR

PP1V5_S3RS0 PP1V5_S3 PP0V75_S3_MEM_VREFCA_A PP0V75_S3_MEM_VREFDQ_A

11 30

7 7 27 28 29 30 31

9 27 28 29 30 31

MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

*

*

MEM_2OTHER

MEM_DATA

MEM_DQS

*

*

MEM_2OTHER

*

*

MEM_2OTHER



TABLE_SPACING_ASSIGNMENT_ ITEM

A

SPACING_RULE_SET


MEM_MEM2OTHERMEM

MEM_DQS

MEM_DATA

11 27 28 32

MEM_MEM2OTHERMEM


MEM_CLK


MEM_DQS

MEM_DATA2DATA



MEM_DQS

MEM_50S

11 27 28 32



NET_SPACING_TYPE1

MEM_MEM2OTHERMEM


NET_SPACING_TYPE1


MEM_CTRL

MEM_CMD2CTRL TABLE_SPACING_ASSIGNMENT_ITEM


MEM_CLK

MEM_MEM2OTHERMEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_MEM2OTHERMEM

MEM_CLK



MEM_CLK

MEM_A_DQ_BYTE4



MEM_2OTHER

MEM_DATA

D

11 27 28 32

MEM_2GND


MEM_2PWR

MEM_DATA

MEM_50S

MEM_B_CMD TABLE_SPACING_ASSIGNMENT_ITEM

?

0.4 MM

MEM_DATA

MEM_50S

MEM_A_DQ_BYTE3


MEM_CLK TABLE_SPACING_RULE_ITEM

MEM_MEM2OTHERMEM

MEM_DATA

MEM_50S

MEM_A_DQ_BYTE2

MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56>

8 11 27 28 32


WEIGHT

SPACING

MEM_50S

MEM_A_DQ_BYTE1

MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L


Need to support MEM_*-style wildcards!

DDR3:

Sandybridge SFF 2C when routed on Type-3 (Through hole)

should follow rPGA guidelines SYNC_MASTER=K21_CONSTRAINTS

per Huron River SFF DG rev1.0 (#438297).

DQ to DQS matching per byte lane


PAGE TITLE

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

Memory Constraints

should be within 0.127mm.

DRAWING NUMBER

DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].

Apple Inc.

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm. CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs. each other should match within 5.08mm.

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric. Maximum length of any signal from die pad

to SODIMM pad is 119.83mm, from procesor ball

SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5

051-8870

to SODIMM pad is 88.9mm.

SIZE

D

REVISION

3.13.0

R

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to


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6

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Digital Video Signal Constraints

4

3

2

1

PCH Net Properties TABLE_PHYSICAL_RULE_HEAD


PHYSICAL_RULE_SET

LAYER

DP_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

LVDS_90D

*

=90_OHM_DIFF

MINIMUM LINE WIDTH

=90_OHM_DIFF

MINIMUM NECK WIDTH

=90_OHM_DIFF

MAXIMUM NECK

=90_OHM_DIFF

LENGTH



=85_OHM_DIFF


=90_OHM_DIFF


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT


DISPLAYPORT

*

D I S P LA Y P O R T

TO P , B OT T O M

=4 x _ D I E LE C T R I C

?


LVDS

D

*

LVDS intra-pair matching should be 5 mils.


?

=3x_DIELECTRIC

P HY SI C AL

S PA CI NG

DP_ML

DP_85D

DISPLAYPORT

DP_ML

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

LVDS_IG_A_CLK

LVDS_90D

LVDS

LVDS_IG_A_CLK

LVDS_90D

LVDS

LVDS_IG_A_DATA

LVDS_90D

LVDS

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

?

Pairs should be within 100 mils of clock length.

LVDS_IG_A_DATA

LVDS_90D

LVDS

LVDS_90D

LVDS

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

LVDS_90D

LVDS

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

LVDS_90D

LVDS

LVDS_90D

LVDS

LVDS_90D

LVDS

LVDS_90D

LVDS

SATA_90D

SATA

DisplayPort/TMDS intra-pair match ing should be 5 ps.

DP_IG_ML_P<3..0> DP_IG_ML_N<3..0> DP_IG_AUX_CH_P DP_IG_AUX_CH_N

8 8 8 8


?

=3x_DIELECTRIC

NET_TYPE


=85_OHM_DIFF

=90_OHM_DIFF

Inter-pair matching should be within 150 ps.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_DATA_P<3..0> LVDS_IG_B_DATA_N<3..0> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N

D

8 8 8 8 8 8


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



SATA_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

SATA

*

LAYER

LINE-TO-LINE

SPACING

WEIGHT

SATA_ICOMP

*


?

=4x_DIELECTRIC

SATA

TOP,BOTTOM

=3x_DIELECTRIC

?

SATA

SATA_90D

SATA

SATA_HDD_R2D

SATA_90D

SATA

SATA_90D

SATA

SATA_HDD_D2R


SATA_HDD_D2R

?

8 MIL

SATA_90D SATA_HDD_R2D


SPACING_RULE_SET


SATA_90D SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_D2R

SATA_90D

SATA

SATA_ODD_D2R

SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

SATA_90D SATA_90D

SATA SATA

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_EXTA

USB_85D

USB

USB_EXTA

USB_85D

USB

USB_EXTB

USB_85D

USB

USB_85D

USB

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


PCH_USB_RBIAS

*

=STANDARD

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



8 MIL

8 MIL

=STANDARD

=STANDARD


USB_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT


C

USB

*

=2x_DIELECTRIC

?


USB

TOP,BOTTOM

=4x_DIELECTRIC

SATA

?

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_HDD_R2D_RC_P SATA_HDD_R2D_RC_N SATA_HDD_D2R_RC_P SATA_HDD_D2R_RC_N

16 38 16 38

6 38 6 38 16 38 16 38

6 38 6 38 8 16 8 16

8 16 8 16

C

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

PCH_SATA_ICOMP USB_HUB1_UP USB_HUB2_UP

USB_EXTC

USB_85D

USB_EXTD USB_EXTD

USB_CAMERA USB_CAMERA

B

USB_BT USB_BT

USB_TPAD USB_IR

USB_SDCARD USB_BRCRYPT

A

SATA_ICOMP

USB

USB_85D

USB

USB_85D USB_85D

USB

USB_85D

USB

USB_85D USB_85D

USB USB

USB_85D

USB

USB_85D USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB

USB

PCH_SATAICOMP USB_HUB1_UP_P USB_HUB1_UP_N USB_HUB2_UP_P USB_HUB2_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_T29A_P USB_T29A_N T29_A_RSVD_P T29_A_RSVD_N USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_SDCARD_P USB_SDCARD_N USB_BRCRYPT_P USB_BRCRYPT_N PCH_USB_RBIAS

PCH_USB_RBIAS

PCH_USB_RBIAS

PCH_DIFFCLK_UNUSED_ PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

CPU_50S

CLK_PCIE

LPC_CLK33M

CPU_50S

CLK_PCIE

GFX_CLK_DPLLSS

CLK_PCIE_90D

CLK_PCIE

GFX_CLK_DPLLSS

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N FSB_CLK133M_PCH_P FSB_CLK133M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN GFX_CLK120M_DPLLSS_P GFX_CLK120M_DPLLSS_N

16 18 24 18 24 18 24 18 24 24 39 24 39

6 24 40 6 24 40 8 24 8 24 8 64 8 64 6 18 40 6 18 40

B

6 24 37 6 24 37 49 49

24 33 24 33

18

16 25 16 25

8 8 16 25 16 25 16 25 16 25 16 25 16 25



PAGE TITLE

PCH Constraints 1 DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


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LPC Bus Constraints

4


PHYSICAL_RULE_SET

LAYER

LPC_50S

*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

CLK_LPC_50S

*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH




LAYER

LINE-TO-LINE

SPACING

WEIGHT TABLE_SPACING_RULE_ITEM

LPC

*

?

6 MIL


CLK_LPC

D

*

SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



SMB_50S

*

SPACING_RULE_SET

LAYER


=50_OHM_SE

SPACING

LPC_50S

LPC

LPC_FRAME_L

LPC_50S

LPC

LPC_RESET_L

LPC_50S

LPC_CLK33M

CLK_LPC_50S

CLK_LPC

LPC_CLK33M

CLK_LPC_50S

CLK_LPC

LPC_CLK33M

CLK_LPC_50S

CLK_LPC

LPC

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

SMBUS_PCH_CLK

SMB_50S

SMB

SMBUS_PCH_DATA

SMB_50S

SMB

SMBUS_PCH_0_CLK

SMB_50S

SMB

SMBUS_PCH_0_DATA

SPACING

SMB

SMB_50S

SMBUS_PCH_1_CLK

SMB_50S

SMBUS_PCH_1_DATA

SMB_50S

SMB

HDA_BIT_CLK

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

SMB

WEIGHT

HDA_SYNC


SMB

*

?

=2x_DIELECTRIC

HDA_RST_L HDA_SDIN0

HD Audio Interface Constraints


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

HDA_SDOUT


HDA_50S

*

LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS

6 16 41 43 6 16 41 43

LAYER

=50_OHM_SE

LINE-TO-LINE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R

PM_SUS_CLK

CLK_SLOW_55S

CLK_SLOW

SPACING

WEIGHT

SPI_CLK

SPI_55S

SPI

*

SPI_55S

SPI

?

=2x_DIELECTRIC

SPI_55S

SPI

SPI_55S

SPI

SPI_MISO

SPI_55S

SPI

SPI_CS0

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S SPI_55S

SPI

PCIE_85D

PCIE

SPI_MOSI


SIO Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



C

CLK_SLOW_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


CLK_SLOW

*

?

8 MIL

PCIE_ENET_R2D

SPI Interface Constraints

PCIE_ENET_D2R TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

SPI

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE


SPI_55S

*

SPACING_RULE_SET

LAYER

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_FW_R2D

PCIE_85D

PCIE

PCIE_FW_D2R

PCIE_85D PCIE_85D

PCIE PCIE


LINE-TO-LINE

SPACING

WEIGHT

PCIE_AP_R2D


SPI

*

?

8 MIL

PCIE_AP_D2R

DisplayPort Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

DP_85D

*


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

B

=85_OHM_DIFF

=85_OHM_DIFF


LINE-TO-LINE

SPACING

WEIGHT


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT


DISPLAYPORT

*

?

=3x_DIELECTRIC

PCIE_AP_R2D

PCIE

PCIE_85D

PCIE PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE


DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

CLK_PCIE_90D

PCI-Express Signal Constraints

CLK_PCIE_90D TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

PCIE_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

CLK_PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF


LINE-TO-LINE

SPACING

WEIGHT

C LK _P CI E

MCP_PE1_REFCLK


CLK_PCIE CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

*

?

=3X_DIELECTRIC

MCP_PE2_REFCLK

LAYER

LINE-TO-LINE

SPACING


PCIE

TOP,BOTTOM

=4X_DIELECTRIC

*

?

20 MIL

System Clock Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

*

=55_OHM_SE

=55_OHM_SE

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

=55_OHM_SE

=55_OHM_SE

=STANDARD

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S


CLK_25M_55S

*

=55_OHM_SE

=55_OHM_SE

CLK_PCIE CLK_PCIE

CLK_PCIE_90D


CLK_SLOW_55S

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

CPU_27P4S

CPU_COMP

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP


A

SPACING_RULE_SET

LAYER

LINE-TO-LINE

DISPLAYPORT

SPACING


CLK_SLOW

*

=2x_DIELECTRIC

?

CLK_25M

*

=5x_DIELECTRIC

?


NOTE: 25MHz system clocks very sensitive to noise.

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

6 25 43

D P_ EXT A_ AU XCH

DP_85D

D ISP LA YP OR T

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

16 44 16 44 16 44

D P_ INT _ML

DP _85 D

DISPLAYPORT

D P_ INT _ML

DP _85 D

DISPLAYPORT

16 44 16 44 16 44

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

16

DP_INT_AUXCH

DP_85D

DISPLAYPORT

6 16 40

DP_INT_AUXCH

DP_85D

6 16 40

DISPLAYPORT

16

DP_85D

DISPLAYPORT

16

DP_85D

DISPLAYPORT

6 16 40 6 16 40

6 16 40

P CI E_ PE G_ D2 R_ LA NE 3

16

PCIE_PEG_D2R_LANE2

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

P CI E


PCIE_85D

P CI E

16 43

PCIE_PEG_D2R_LANE3

PCIE_85D

PCIE

43

PCIE_PEG_D2R_LANE2

PCIE_85D

PCIE

16 43


PCIE_85D

P CI E

43

PCIE_PEG_D2R_LANE0

PCIE_85D

PCIE

16 43

PCIE_PEG_R2D_LANE3

PCIE_85D

PCIE

16 43

PCIE_PEG_R2D_LANE2

PCIE_85D

PCIE

43

PCIE_PEG_R2D_LANE1

PCIE_85D

PCIE

43 50

PCIE_PEG_R2D_LANE0

PCIE_85D

PCIE

43 50

PCIE_PEG_R2D_LANE3

PCIE_85D

PCIE

43 50 43 50

PCIE_PEG_R2D_LANE2 PCIE_PEG_R2D_LANE1

PCIE_85D PCIE_85D

PCIE PCIE

PCIE_PEG_R2D_LANE0

PCIE_85D

PCIE

PCIE_CLK100M_T29 PCIE_CLK100M_T29

PCIE_T29_D2R_P<3> PCIE_T29_D2R_P<2> PCIE_T29_D2R_P<1> PCIE_T29_D2R_P<0> PCIE_T29_D2R_N<3> PCIE_T29_D2R_N<2> PCIE_T29_D2R_N<1> PCIE_T29_D2R_N<0> PCIE_T29_R2D_P<3> PCIE_T29_R2D_P<2> PCIE_T29_R2D_P<1> PCIE_T29_R2D_P<0> PCIE_T29_R2D_N<3> PCIE_T29_R2D_N<2> PCIE_T29_R2D_N<1> PCIE_T29_R2D_N<0>

PCIE

PCIE_85D

DP_EXTA_ML_C_P<3..0> DP_EXTA_ML_C_N<3..0> DP_EXTA_ML_P<3..0> DP_EXTA_ML_N<3..0> DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N DP_INT_ML_C_P<3..0> DP_INT_ML_C_N<3..0> DP_INT_ML_P<3..0> DP_INT_ML_N<3..0> DP_INT_ML_F_P<3..0> DP_INT_ML_F_N<3..0> DP_INT_AUX_CH_C_P DP_INT_AUX_CH_C_N DP_INT_AUX_CH_P DP_INT_AUX_CH_N PCIE_T29_R2D_C_P<3..0> PCIE_T29_R2D_C_N<3..0>

P CI E

PCIE_85D


PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N

DP_85D

PCIE

PCIE_85D

PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

8 64 64 64

8 64 8 64 64

D

64 63 63

9 63 9 63 6 63 6 63 6 63 6 63 9 63 9 63

8 34 8 34

8 34 8 8 34 8 8 34 8 34 8 34 8 34 34 34 34 34 34

C

34 34 34

PCIE_T29_D2R_C_P<3..0> PCIE_T29_D2R_C_N<3..0>

PCIE_85D

8 64

PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N

34 34

16 34 16 34

Clock Net Properties NET_TYPE

6 37


P HY SI CA L

S PA CI NG

6 37 16 37 16 37

SYSCLK_CLK32K_RTC

CLK_SLOW_55S

CLK_SLOW

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

CLK_25M_55S CLK_25M_55S

CLK_25M CLK_25M

CLK_25M_55S

CLK_25M

CLK_25M_55S

CLK_25M

CLK_25M_55S

CLK_25M

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB_R SYSCLK_CLK25M_ENET SYSCLK_CLK25M_ENET_R SYSCLK_CLK25M_T29 SYSCLK_CLK25M_T29_R

6 16 37 6 16 37

PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N

SYSCLK_CLK25M_T29

16 25

16 25 16

25 34 34

B

CONN_PCIE_AP_D2R_P CONN_PCIE_AP_D2R_N CONN_PCIE_AP_R2D_P CONN_PCIE_AP_R2D_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N

8 16 8 16

6 16 37 6 16 37

8 16 8 16

?


CLK_PCIE



SPACING_RULE_SET


PCIE

CLK_PCIE

CLK_PCIE_90D


LAYER

CLK_PCIE

P CI E_ CL K1 00 M_ EN ET


SPACING_RULE_SET

DP_85D

=85_OHM_DIFF

PCIE_AP_D2R LAYER

PCIE_85D PCIE_85D


SPACING_RULE_SET

DISPLAYPORT

DP_EXTA_ML

25 41

PM_CLK32K_SUSCLK SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L

S PA CI NG

DP_85D

18 25

=STANDARD


HDA

P HY SI CA L

DP_EXTA_ML

25


SPACING_RULE_SET

1 NET_TYPE

LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L

=STANDARD


LINE-TO-LINE

PHYSICAL

LPC_AD

?

8 MIL


PHYSICAL_RULE_SET

2 Chipset Net Properties

NET_TYPE

ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET

3

PCH Net Properties TABLE_PHYSICAL_RULE_HEAD

PCH_VSS_NCTF<1> PCH_VSS_NCTF<2> PCH_VSS_NCTF<5> TP_PCH_VSS_NCTF<7> PCH_VSS_NCTF<9> PCH_VSS_NCTF<9> PCH_VSS_NCTF<11> PCH_VSS_NCTF<12> PCH_VSS_NCTF<15> PCH_VSS_NCTF<17> PCH_VSS_NCTF<19> PCH_VSS_NCTF<21> PCH_VSS_NCTF<22> PCH_VSS_NCTF<25> PCH_VSS_NCTF<27> PCH_VSS_NCTF<29>

6 6 6

6 70 6 70 6 6 6 6 6 6 SYNC_MASTER=K21_CONSTRAINTS


PAGE TITLE 6

PCH Constraints 2

6

DRAWING NUMBER

6

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

103 OF 109

A

8

7

www.laptopblue.vn

6

5

CAESAR IV (Ethernet) Constraints

4


PHYSICAL_RULE_SET

LAYER

ENET_50S

*


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

LAYER

LINE-TO-LINE

2

1

NET_TYPE


=STANDARD


SPACING_RULE_SET

3

Ethernet Net Properties

SPACING

WEIGHT

PHYSICAL

SPACING

ENET_50S

ENET_3X

ENET_50S

ENET_3X

ENET_50S

ENET_3X

BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO ENET_RESET_L


ENET_3X

*

ENET_MDI

?

=3:1_SPACING

ENET_100D

ENET_100D

ENET_MDI ENET_MDI

ENET_MDI_P<3..0> ENET_MDI_N<3..0>

SOURCE: Broadcom 5764-DS04-RDS Page 38 TABLE_SPACING_RULE_HEAD

D

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

I166

CR_DATA

ENET_50S

ENET_CR_DATA

I167

CR_DATA

ENET_50S

ENET_CR_DATA

I168

CR_CLK

ENET_50S

ENET_CR_DATA

I169

CR_DATA

ENET_50S

ENET_CR_DATA

I170

CR_DATA

ENET_50S

ENET_CR_DATA

I171

CR_CLK

ENET_50S

ENET_CR_DATA


ENET_CR_DATA

*

?

8MIL

CAESAR IV (Ethernet PHY) Constraints

ENET_CR_DATA<7..0> ENET_CR_CMD ENET_CR_CLK SDCONN_DATA<7..0> SDCONN_CMD SDCONN_CLK

D


PHYSICAL_RULE_SET

LAYER

ENET_100D

*

SPACING_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF


LINE-TO-LINE

SPACING


ENET_MDI

*

?

0.6 MM

SOURCE: Broadcom 5764-DS04-RDS Page 38

C

FireWire Interface Constraints LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



FW_110D

*

SPACING_RULE_SET

LAYER

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF


LINE-TO-LINE

SPACING

WEIGHT

=110_OHM_DIFF

=110_OHM_DIFF

NET_TYPE


=110_OHM_DIFF

*

=3:1_SPACING

?

PHYSICAL

SPACING

I158

FW_P0_TPA

FW_110D

FW_TP

I159

FW_P0_TPA

FW_110D

FW_TP

I160

FW_P0_TPB

FW_110D

FW_TP

I161

FW_P0_TPB

FW_110D

FW_TP

I162

FW_P1_TPA

FW_110D

FW_TP

I163

FW_P1_TPA

FW_110D

FW_TP

I164

FW_P1_TPB

FW_110D

FW_TP

I165

FW_P1_TPB

FW_110D

FW_TP


FW_TP

C

FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N

Port 2 Not Used

B

B

A



PAGE TITLE

Ethernet/FW Constraints DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

104 OF 109

A

8

7

www.laptopblue.vn

6

5

DisplayPort Signal Constraints

4

3

2

1

T29 Net Properties

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

NET_TYPE


T29 I2C Signal Constraints PHYSICAL_RULE_SET

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



T29_I2C_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=55_OHM_SE

=STANDARD


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


T29_I2C

D

*

?

=2x_DIELECTRIC

T29 SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



T29_SPI_55S

*

SPACING_RULE_SET

LAYER

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD


LINE-TO-LINE

SPACING


T29_SPI

*

?

=2x_DIELECTRIC

DP/T29 Connector Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


T29DP_80D

*

=80_OHM_DIFF

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

DISPLAYPORT

I262

DP_85D

DISPLAYPORT

*

=5x_DIELECTRIC

?

C I

LAYER

LINE-TO-LINE

SPACING


T29DP

TOP,BOTTOM

=7x_DIELECTRIC

?

C

s e i t r e p o r P t e N P D / 9 2 T

A

DP_T29SNK0_ML

DP_85D

DISPLAYPORT

I265

DP_T29SNK0_ML

DP_85D

DISPLAYPORT

I266

DP_85D

DISPLAYPORT

I267

DP_85D

DISPLAYPORT

I268

DP_T29SNK0_AUXCH

DP_85D

DISPLAYPORT

I269

DP_T29SNK0_AUXCH

DP_85D

DISPLAYPORT

I270

DP_85D

DISPLAYPORT

I271

DP_85D

DISPLAYPORT

I272

DP_T29SNK1_ML

DP_85D

DISPLAYPORT

I273

DP_T29SNK1_ML

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

I276

DP_T29SNK1_AUXCH

DP_85D

DISPLAYPORT

I277

DP_T29SNK1_AUXCH

DP_85D

DISPLAYPORT

I274 I275

I282

T29_I2C_55S

T29_I2C

I283

T29_I2C_55S

T29_I2C

I284

T29_SPI_CLK

T29_SPI_55S

T29_SPI

I285

T29_SPI_MOSI

T29_SPI_55S

T29_SPI

I286

T29_SPI_MISO

T29_SPI_55S

T29_SPI

I287

T29_SPI_CS_L

T29_SPI_55S

T29_SPI

9 2 T

SOURCE: Bill Cornelius’s T29 Routing Notes

B

I264

DP_T29SNK0_ML_C_P<3..0> DP_T29SNK0_ML_C_N<3..0> DP_T29SNK0_ML_P<3..0> DP_T29SNK0_ML_N<3..0> DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N

8 34 8 34 34 34

8 34 8 34 34

D

34

DP_T29SNK1_ML_C_P<3..0> DP_T29SNK1_ML_C_N<3..0> DP_T29SNK1_ML_P<3..0> DP_T29SNK1_ML_N<3..0> DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N

I2C_T29_SCL I2C_T29_SDA T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L

34 44 34 44

34 34 34 34


SPACING_RULE_SET


T29DP

t e N

SPACING

DP_85D

=80_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM

T29DP_100D

s e i t r e p o r P

PHYSICAL

I263



I288

T29DP_80D

I289

T29DP_80D

T29DP

I290

T 2 9D P _8 0 D

T 2 9D P

T29DP

I291

T 2 9D P _8 0 D

T 2 9D P

I292

T29_R2D0

T 2 9D P _8 0 D

T2 9 DP

I293

T29_R2D0

T 2 9D P _8 0 D

T 2 9D P

I294

T29_R2D1

T 2 9D P _8 0 D

T 2 9D P

I295

T29_R2D1

T 2 9D P _8 0 D

T 2 9D P

I322

T 2 9D P _8 0 D

T 2 9D P

I323

T 2 9D P _8 0 D

T 2 9D P

I296

T29_D2R0

T 2 9D P _8 0 D

T 2 9D P

I298

T29_D2R0

T 2 9D P _8 0 D

T 2 9D P

I297

T29_D2R1

T 2 9D P _8 0 D

T 2 9D P

I299

T29_D2R1

T 2 9D P _8 0 D

T 2 9D P

I300

T 2 9D P _8 0 D

T 2 9D P

I301

T29DP_80D

T29DP

I302

T 2 9D P _8 0 D

T 2 9D P

I303

T 2 9D P _8 0 D

T 2 9D P

I320

T 2 9D P _8 0 D

T 2 9D P

I321

T 2 9D P _8 0 D

T 2 9D P

T 2 9D P _8 0 D

T 2 9D P

I305

DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN

I306

DP_SDRVA_ML_ODD

T 2 9D P _8 0 D

T 2 9D P

T 2 9D P _8 0 D

T 2 9D P

I307

DP_SDRVA_ML_ODD DP_SDRVA_ML_EVEN

I309

I304

I308

T 2 9D P

T 2 9 D P_ 8 0D

T 2 9D P

DP_SDRVA_ML_EVEN

T29DP_80D

T29DP

I310

DP_SDRVA_ML_ODD

T 2 9D P _8 0 D

T 2 9D P

I311

DP_SDRVA_ML_ODD

T 2 9D P _8 0 D

T 2 9D P

I312

DP_SDRVA_AUXCH

T 2 9D P _8 0 D

T 2 9D P

I313

DP_SDRVA_AUXCH

T 2 9D P _8 0 D

T 2 9D P

I314

T 2 9D P _8 0 D

T 2 9D P

I315

T29DP_80D

T29DP

I326

T29DPA_ML_ODD

I327

T29DPA_ML_ODD

I328 I329

T 2 9 D P_ 8 0D

T29_R2D_C_P<3..0> T29_R2D_C_N<3..0> T29_D2R_P<3..0> T29_D2R_N<3..0>

T29_R2D_P<0> T29_R2D_N<0> T29_R2D_P<1> T29_R2D_N<1> T29_R2D_C_F_P<1..0> T29_R2D_C_F_N<1..0> T29_D2R_C_P<0> T29_D2R_C_N<0> T29_D2R_C_P<1> T29_D2R_C_N<1> T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N DP_SDRVA_ML_C_P<3..0> DP_SDRVA_ML_C_N<3..0> DP_SDRVA_ML_R_P<3..0> DP_SDRVA_ML_R_N<3..0> DP_SDRVA_ML_P<0> DP_SDRVA_ML_N<0> DP_SDRVA_ML_P<1> DP_SDRVA_ML_N<1> DP_SDRVA_ML_P<2> DP_SDRVA_ML_N<2> DP_SDRVA_ML_P<3> DP_SDRVA_ML_N<3> DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N T29DPA_ML_P<1> T29DPA_ML_N<1> T29DPA_ML_P<3> T29DPA_ML_N<3>

T29DPA_ML_ODD T29DPA_ML_ODD

I316

T 2 9D P _8 0 D

T 2 9D P

I317

T29DP_80D

T29DP

I324

T29DP_80D

T29DP

I325

T29DP_80D

T29DP

I318

DP_A_EXT_AUXCH

T 2 9D P _8 0 D

T 2 9D P

I319

DP_A_EXT_AUXCH

T 2 9D P _8 0 D

T 2 9D P

T29DPA_ML_P<3..0> T29DPA_ML_N<3..0> T29DPA_ML_C_P<3..0> T29DPA_ML_C_N<3..0> DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N

8 34 64 8 34 64 8 34 64 8 34 64

C

64 64 64 64 64 64 64 65 64 65 64 65 64 65 65 65

64 64 64 64

64 64 64 64 64 64 64

B

64 64 64 64 64

64 65 64 64 65 64

64 65 64 65 64 65 64 65 64 65 64 65



PAGE TITLE

T29 Constraints DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

105 OF 109

A

8

7

www.laptopblue.vn

6

5

4

3

2

1

SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


1TO1_DIFFPAIR

*

=STANDARD

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH



D

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.1 MM

NET_TYPE


PHYSICAL

SPACING

SMBUS_SMC_A_S3_SCL

SMB_50S

SMB

SMBUS_SMC_A_S3_SDA

SMB_50S

SMB

SMBUS_SMC_B_S0_SCL

SMB_50S

SMB

SMBUS_SMC_B_S0_SDA

SMB_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_50S

SMB

SMBUS_SMC_0_S0_SDA

SMB_50S

SMB

SMBUS_SMC_BSA_SCL

SMB_50S

SMB

SMBUS_SMC_BSA_SDA

SMB_50S

SMB

SMBUS_SMC_MGMT_SCL

SMB_50S

SMB

SMBUS_SMC_MGMT_SDA

SMB_50S

SMB

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

44 44 44 44 44 44

6 44

D

6 44 44 44

SMBus Charger Net Properties NET_TYPE

ELECTRICAL_CONSTRAINT_SET CHGR_CSI

P HY SI C AL

1TO1_DIFFPAIR 1TO1_DIFFPAIR

CHGR_CSO


S PA CI NG

CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N

53 53

53 53

C

C

B

B

A



PAGE TITLE

SMC Constraints DRAWING NUMBER

Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

106 OF 109

A

8

7

www.laptopblue.vn

6

5


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

4

3

K21/K78 Specific Net Properties

2

1

K21/K78 Specific Net Properties NET_TYPE

NET_TYPE


SENSE_1TO1_55S

*

=1:1_DIFFPAIR

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

THERM_1TO1_55S

*

=1:1_DIFFPAIR

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=1:1_DIFFPAIR


=1:1_DIFFPAIR

PHYSICAL

ENETCONN

ENET_100D

ENETCONN

SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

SATA_90D

SATA

I295

SATA_90D

SATA

I298

SATA_90D

SATA

I297

SATA_90D

SATA

I296

SATA_90D

SATA

=1:1_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR

*

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR



SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE



D

SENSE

*

=2:1_SPACING

?

THERM

*

=2:1_SPACING

?

CPU_COMP

GND

*

GND_P2MM

CPU_VCCSENSE

GND

*

GND_P2MM




AUDIO

*

?

=2:1_SPACING

SENSE_DIFFPAIR LAYER

LINE-TO-LINE

SPACING

WEIGHT

I287



ENETCONN

*

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

*

GND_P2MM

GND

AREA_TYPE

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

SENSE_DIFFPAIR


GND

*

NET_SPACING_TYPE2

THERM_1TO1_55S THERM THERM_1TO1_55S THERM


NET_SPACING_TYPE1

?

=STANDARD



SPACING_RULE_SET


SENSE_DIFFPAIR


ENET_MDI

CPU_THERMD

I288

?

25 MILS

THERM THERM_1TO1_55S

THERM_1TO1_55S THERM


SPACING_RULE_SET


CLK_PCIE

GND

*

GND_P2MM

PCIE

GND

*

GND_P2MM

SATA

GND

*

GND_P2MM

SENSE_DIFFPAIR

LAYER

LINE-TO-LINE

SPACING

WEIGHT

SENSE_DIFFPAIR


*

0.20 MM

SENSE_DIFFPAIR


1000 USB

*

GND

GND_P2MM

*

0.20 MM

SENSE

SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE


PWR_P2MM

SENSE_1TO1_55S

SENSE_1TO1_55S SENSE


GND_P2MM

SENSE SENSE_1TO1_55S




SPACING_RULE_SET

CLK_PCIE

SB_POWER

*

PWR_P2MM

SATA

SB_POWER

*

PWR_P2MM

SENSE_DIFFPAIR



NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

SENSE_1TO1_55S SENSE SENSE_DIFFPAIR



MEM_CLK

GND

*

GND_P2MM

MEM_CMD

GND

*

GND_P2MM

USB

*

SB_POWER

PWR_P2MM

SENSE_DIFFPAIR


SENSE_DIFFPAIR

SENSE_1TO1_55S SENSE SENSE SENSE_1TO1_55S


C

GND

*

GND_P2MM

MEM_DATA

GND

*

GND_P2MM

MEM_DQS

GND

*

GND_P2MM




NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE



MEM_CTRL

SENSE_DIFFPAIR

SPACING_RULE_SET

SENSE_1TO1_55S

SENSE




LVDS

GND

*

GND_P2MM

SENSE_DIFFPAIR


SENSE_1TO1_55S SENSE TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



MEM_40S

OV ERRIDE

0.09 MM

*

OVER RIDE

OVER RIDE

OVERRI DE

OVERRI DE

400 MIL

MEM_72D

0.09 MM

*

OVER RIDE

OVER RIDE

OVERRI DE

OVERRI DE

O VERRID E

400 MIL

O VERRID E

OV ERRIDE

0.09 MM

*

OVER RIDE

OVER RIDE

OVERRI DE

OVERRI DE

O VERRID E

MEM_85D

OV ERRIDE

0.09 MM

*

OVER RIDE

OVER RIDE

OVERRI DE

OVERRI DE

400 MIL

O VERRID E

PCIE_85D

OV ERRIDE

0.076 MM

*

OVER RIDE

OVER RIDE

OVERRI DE

OVERRI DE

OVER RIDE

OVERRI DE

OVERRI DE

10 mm

TOP

OVER RIDE

0.1 MM

O VERRID E

OV ERRIDE

O VERRID E

OV ERRIDE

500 MIL


CPU_27P4S

TOP

OV ERRIDE

OVER RIDE

0.09 MM

TOP

OV ERRIDE

OVER RIDE

OVER RIDE

OVERRI DE

OVERRI DE

OVER RIDE

OVERRI DE

OVERRI DE

0.09 MM

OV ERRIDE

O VERRID E

OV ERRIDE

O VERRID E

OV ERRIDE

400 MIL

OV ERRIDE

SENSE_DIFFPAIR





SENSE_DIFFPAIR

SENSE_1TO1_55S SENSE SENSE SENSE_1TO1_55S SENSE_1TO1_55S SENSE

I292

SENSE_DIFFPAIR

I335


I291

B


SENSE_1TO1_55S SENSE SENSE SENSE_1TO1_55S


CLK_PCIE_90D

SENSE


I286

400 MIL

SENSE_1TO1_55S

SENSE_DIFFPAIR

I284

I285

OV ERRIDE

SENSE


I282

I283

OV ERRIDE


USB_85D

OV ERRIDE

SENSE_DIFFPAIR

OV ERRIDE TABLE_PHYSICAL_RULE_ITEM

SENSE_1TO1_55S


I255

I281

OV ERRIDE

SENSE_DIFFPAIR

OV ERRIDE TABLE_PHYSICAL_RULE_ITEM

SENSE


I254

I256

OV ERRIDE

SENSE_DIFFPAIR

OV ERRIDE

400 MIL

SENSE_1TO1_55S


I251

I253

OV ERRIDE

SENSE_DIFFPAIR

I250

OV ERRIDE


MEM_37S

I249

I252

OV ERRIDE


OV ERRIDE

ENETCONN_P<3..0> ENETCONN_N<3..0> SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_RDRVR_OUT_P SATA_HDD_D2R_RDRVR_OUT_N SATA_HDD_R2D_RDRVR_IN_P SATA_HDD_R2D_RDRVR_IN_N SATA_HDD_D2R_RDRVR_IN_P SATA_HDD_D2R_RDRVR_IN_N SATA_HDD_R2D_RDRVR_OUT_P SATA_HDD_R2D_RDRVR_OUT_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N T29_THERMD_P T29_THERMD_N T29_MLBBOT_THMSNS_P T29_MLBBOT_THMSNS_N ISNS_HS_COMPUTING_N ISNS_HS_COMPUTING_P ISNS_HS_OTHER_N ISNS_HS_OTHER_P CPUVCCIOS0_CS_N CPUVCCIOS0_CS_P

PCIE_CLK100M_AP

SPACING

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR (USB_EXTA)

USB_85D

USB

(USB_EXTA)

USB_85D

USB

47

(USB_EXTA)

USB_85D

USB

47

(USB_EXTA)

USB_85D

USB

46 47

USB_85D

USB

46 47

USB_85D

USB

USB_85D

USB

USB_85D

USB

SENSE_DIFFPAIR


I336


I293

L VD S_ 90 D

L VD S

I294

L VD S_ 90 D

L VD S

CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N CPUIMVP_ISNS2_P CPUIMVP_ISNS2_N CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISUM_R_P CPUIMVP_ISUM_R_N CPUIMVP_ISUMG_R_P CPUIMVP_ISUMG_R_N CPUIMVP_ISNS_P CPUIMVP_ISNS_N VCCSAS0_CS_P VCCSAS0_CS_N CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N ISNS_CPU_N ISNS_CPU_P ISNS_HDD_N ISNS_HDD_P ISNS_HDD_R_N ISNS_HDD_R_P ISNS_LCDBKLT_N ISNS_LCDBKLT_P ISNS_ODD_N ISNS_ODD_P ISNS_ODD_R_N ISNS_ODD_R_P ISNS_1V5_S3_N ISNS_1V5_S3_P ISNS_P1V8GPU_R_N ISNS_P1V8GPU_R_P ISNS_AIRPORT_N ISNS_AIRPORT_P LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P

SPKRAMP_INR

I332 I334 I333

Memory Constraint Relaxations

M AX 98 30 0_ R

PHYSICAL

AUDIO

DIFFPAIR

AUDIO

D IF FP AI R DIFFPAIR

AUDIO AUDIO

SPKRAMP_INR_P SPKRAMP_INR_N MAX98300_R_P MAX98300_R_N

46 53

39 39 39 39

47

46 46

DP_85D DP_85D

DISPLAYPORT

45 59

SPK_OUT

DIFFPAIR

AUDIO

45 59

SPK_OUT

DIFFPAIR

AUDIO

SPK_OUT

DIFFPAIR

AUDIO

SPK_OUT

DIFFPAIR

AUDIO

SPK_OUT

DIFFPAIR

SPK_OUT

DIFFPAIR

AUDIO

AUD_DIFF


AUDIO

AUD_DIFF

I302

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

I301

AUD_DIFF AUD_DIFF


AUDIO

I304 I303

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

I305

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_DIFF AUD_DIFF

1TO1_DIFFPAIR

AUDIO

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

AUD_DIFF AUD_DIFF

1TO1_DIFFPAIR AUDIO

AUD_DIFF

1TO1_DIFFPAIR

AUD_DIFF SPKRAMP_INR

1TO1_DIFFPAIR

AUDIO

DIFFPAIR

AUDIO

AUD_DIFF

DIFFPAIR

AUDIO

AUD_DIFF AUD_DIFF

1TO1_DIFFPAIR

AUDIO

1TO1_DIFFPAIR

AUDIO

USB_85D USB_85D

USB

45 57 58 45 58

I299

45 58 45 58

I300

45 45 45 45

I307

54

I306 I310

54 I308

57 58 57 58

I309 I311 I312

38 46

I313 I314

38 46 I315 I316

8 46 8 46

DISPLAYPORT

AUDIO

AUDIO

AUDIO

AUDIO

1TO1_DIFFPAIR

AUDIO

USB

SB_POWER SB_POWER 46 56

GND

CONN_USB2_BT_P CONN_USB2_BT_N USB_LT2_P USB_LT2_N DP_IG_AUX_CH_C_P DP_IG_AUX_CH_C_N SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT SPKRAMP_SUB_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT SSM2315_SUB_N SSM2315_SUB_P SSM2315_L_N SSM2315_L_P SSM2315_R_N SSM2315_R_P AUD_LO2_N_R AUD_LO2_P_R AUD_LO1_N_R AUD_LO1_P_R AUD_LO2_N_L AUD_LO2_P_L SPKRAMP_INL_P SPKRAMP_INL_N SPKRAMP_INR_P SPKRAMP_INR_N SPKRAMP_INSUB_P SPKRAMP_INSUB_N

6 51 52 6 51 52

C

6 40 51 74 6 40 51 74

USB_TPAD_R_P USB_TPAD_R_N PP3V3_S5 PP3V3_S0

6 7 6 7

GND

46 56

B

37 46 37 46

Misc Net Properties NET_TYPE

SPACING

DIFFPAIR

D

53

46 53

47

NET_TYPE

I331

53

9 47

Audio Net Properties ELECTRICAL_CONSTRAINT_SET

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_LT1_P USB2_LT1_N

9 47


A

PHYSICAL


1000


NET_SPACING_TYPE1


SPACING

ENET_100D


=1:1_DIFFPAIR

6 40 51 74 6 40 51 74

51 51

PHYSICAL

SPACING

I317

(USB_EXTA)

USB_85D

USB

I318

(USB_EXTA)

USB_85D

USB

I319

(USB_EXTA)

USB_85D

USB

I320

(USB_EXTA)

USB_85D

I322

(USB_TPAD) (USB_TPAD)

USB_85D USB_85D

USB

I324 I326

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

I325

SMBUS_SMC_MGMT_SCL

SMB_55S

SMB

I328

SMB_55S

SMB

I327

SMB_55S

SMB

I330

SMB_55S

SMB

I329

SMB_55S

SMB

USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_LT1_P USB_LT1_N USB_TPAD_CONN_P USB_TPAD_CONN_N

USB USB

6 49 6 49

I2C_SMC_SMS_SDA_R I2C_SMC_SMS_SCL_R I2C_TCON_SCL I2C_TCON_SDA I2C_TCON_SCL_CONN I2C_TCON_SDA_CONN



PAGE TITLE Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

Project Specific Constraints



PHYSICAL_RULE_SET

LAYER

MEM_72D

BOTTOM

0.127 MM

6.35 MM

MEM_85D

TOP

0.1 MM

6.35 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK

LENGTH


DIFFPAIR NECK GAP

DRAWING NUMBER



Apple Inc.

051-8870

SIZE

D

REVISION

3.13.0

R


BRANCH


PAGE

108 OF 109

A

apple-macbook-air-a1369-1-8203023a-schematics.pdf

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