ABSTRACT
ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 spe specifi cif ications cations which include ncludes Adva Advan nced ced eX ten tensiable I nte nterfa rface (AX (A X I ) 4.0. AM AMBA bus bus protocol protocol has become the de facto standard standard SoC SoC bus. Tha T hatt means more ore and more ore existi xisting ng IP IPs must must be abl able e to communicate with with AM AM BA 4.0 bus. bus. Ba Based on AM AMBA 4.0 bus, bus, we designe designed d an an Inte Intellectual ctual Property Property (IP) (I P) core of Adva A dvan nced ced Peri Periph phe eral Bus Bus (APB (A PB)) Bri Bridg dge e, which trans transllates tes the the AX I 4.0-lite 4.0-l ite tran transacti sactions ons into into AP APB 4.0 transacti transactions. ons. The T he bridge bridge provi provides des an inter nterfaces between the the hi highperform rforman ance ce AXI AX I bus bus and and lowlow-powe power AP A PB domain. We We then interf interfa ace this bridge bridge to an an UAR UA RT transmitter and receiver. A MBA bus is wide widelly use used in the high-perform rforma ance nce SoC designs. signs. The T he A MBA specification defines an on-chip communication standard for designing high-performance embedded microcontrollers.
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1. INTRODUCTI INTRODUCTION ON The There are many companies ies that develop lop core IP fo for SoC products. The The int interfaces to these cores cores can dif differ from from com company to company and can can sometim etimes be propri proprieta etary ry in in natur nature e. The SoC SoC developer developer the then n must expen expend d tim time, effor effort, t, and money money to cre create “bridge “bridge” ” or or “glue “glue”” logic ogic that allows allows all all of the cores inside inside the SoC to comm communicate properl properly y wit with h ea each other. other. I ncompati patible ble inter nterfaces are thus barri rriers to both IP IP devel developers opers and and SoC develo develope pers. rs. SoC SoC integrate ntegrated d circui circuits ts envi envisi sioned oned by this this subcomm subcommittee span a wide wide breadth breadth of appli applications, cations, targe targett system costs, and and levels of performance and integration. I ntegrate ntegrated circui circuits ts have have entere entered d the era of System System-on-a-C on-a-Chip hip (SoC (SoC), ), which which refe refers to integrati ntegrating ng all compone components nts of a compute computerr or or other other electronic electronic system into a singl single e chip. I t may contain digital, analog, mixed-signal, and often radio-frequency functions – all on a single chip subs substrate trate. Wi With the the increasing increasing design design size size,, I P is an inevitable ch choi oice ce for SoC SoC design. And A nd the wide widespre spread ad use of all all kinds ki nds of I Ps has has change changed the nature of the desi design gn fl flow, making aking On-C On-Chip hip Buses (OCB) essential to the design. Of all OCB OCBs exi existi sting ng in the market, the A MBA bus system systemis wide widelly used as as the the de de facto standa ndard SoC bus. bus. On Ma March 8, 2010 2010,, ARM A RM announ nnounce ced d ava avaiilabi ability ity of the the AM AMBA 4.0 spe specif cifications. As As the the de facto stand standa ard SoC bus, bus, AM A MBA bus bus is wide wi delly used in in the the hi highperform rforman ance ce SoC designs. The T he A MBA spe specif cificati cation on defines an onon-chip com communication stand standa ard for designing high-performance embedded microcontrollers. ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 spe specifi cif ications cations in Ma M arch 201 2010, 0, which includ include es Adva Advan nced ced exte exten nsible sible Int Inte erfa rface (AX (A XI ) 4.0. AM AMBA bus protocol protocol has becom become e the de facto standard standard SoC SoC bus. Tha Thatt mea means ns more ore and more ore existi existing ng IP IPs must ust be abl able to comm communicate with with AM AM BA 4.0 bus. bus. Ba Based on AM AM BA 4.0 bus, bus, This This desi design gn is an I nte ntellectual ctual Prope Property (IP) (I P) core core of AXI (Adva (A dvanc nce ed exte exten nsible sible I nte nterfa rface) ce) L ite to to APB APB(A (Adva dvanc nce ed Periph riphe eral Bus Bus)) Bridg ridge e, which which transl translates tes the AX I 4.0-li 4.0-l ite transa transactions ctions into AP APB 4.0 trans transactions. actions. The The bri brid dge pr provide ides int interfac faces be between th the hig high h-pe -perfo rformance AXI bus an and low low-po -power APB domain.
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1. INTRODUCTI INTRODUCTION ON The There are many companies ies that develop lop core IP fo for SoC products. The The int interfaces to these cores cores can dif differ from from com company to company and can can sometim etimes be propri proprieta etary ry in in natur nature e. The SoC SoC developer developer the then n must expen expend d tim time, effor effort, t, and money money to cre create “bridge “bridge” ” or or “glue “glue”” logic ogic that allows allows all all of the cores inside inside the SoC to comm communicate properl properly y wit with h ea each other. other. I ncompati patible ble inter nterfaces are thus barri rriers to both IP IP devel developers opers and and SoC develo develope pers. rs. SoC SoC integrate ntegrated d circui circuits ts envi envisi sioned oned by this this subcomm subcommittee span a wide wide breadth breadth of appli applications, cations, targe targett system costs, and and levels of performance and integration. I ntegrate ntegrated circui circuits ts have have entere entered d the era of System System-on-a-C on-a-Chip hip (SoC (SoC), ), which which refe refers to integrati ntegrating ng all compone components nts of a compute computerr or or other other electronic electronic system into a singl single e chip. I t may contain digital, analog, mixed-signal, and often radio-frequency functions – all on a single chip subs substrate trate. Wi With the the increasing increasing design design size size,, I P is an inevitable ch choi oice ce for SoC SoC design. And A nd the wide widespre spread ad use of all all kinds ki nds of I Ps has has change changed the nature of the desi design gn fl flow, making aking On-C On-Chip hip Buses (OCB) essential to the design. Of all OCB OCBs exi existi sting ng in the market, the A MBA bus system systemis wide widelly used as as the the de de facto standa ndard SoC bus. bus. On Ma March 8, 2010 2010,, ARM A RM announ nnounce ced d ava avaiilabi ability ity of the the AM AMBA 4.0 spe specif cifications. As As the the de facto stand standa ard SoC bus, bus, AM A MBA bus bus is wide wi delly used in in the the hi highperform rforman ance ce SoC designs. The T he A MBA spe specif cificati cation on defines an onon-chip com communication stand standa ard for designing high-performance embedded microcontrollers. ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 spe specifi cif ications cations in Ma M arch 201 2010, 0, which includ include es Adva Advan nced ced exte exten nsible sible Int Inte erfa rface (AX (A XI ) 4.0. AM AMBA bus protocol protocol has becom become e the de facto standard standard SoC SoC bus. Tha Thatt mea means ns more ore and more ore existi existing ng IP IPs must ust be abl able to comm communicate with with AM AM BA 4.0 bus. bus. Ba Based on AM AM BA 4.0 bus, bus, This This desi design gn is an I nte ntellectual ctual Prope Property (IP) (I P) core core of AXI (Adva (A dvanc nce ed exte exten nsible sible I nte nterfa rface) ce) L ite to to APB APB(A (Adva dvanc nce ed Periph riphe eral Bus Bus)) Bridg ridge e, which which transl translates tes the AX I 4.0-li 4.0-l ite transa transactions ctions into AP APB 4.0 trans transactions. actions. The The bri brid dge pr provide ides int interfac faces be between th the hig high h-pe -perfo rformance AXI bus an and low low-po -power APB domain.
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2.LITERATURE REVIEW The The Adv Advanced Mic M icrrocontroller Bu Bus s Arch Archite itecture (AMBA) (AMBA) is is us used as as th the on on-ch -chip bu bus in system-on-a-chip (SoC) designs. Since its inception, the scope of AMBA has gone far beyond microcontroll crocontroller devices, and and is is now wide widelly used on a range range of ASI ASIC C and and SoC parts parts includi including ng appl appliications cations processor processors s used in in modern odern portab portablle mobil obile device vices s li like sma smart phone phones. s. The The AMBA protocol is an an op open st standard, on-ch -chip int interconnect specifica ification ion for for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates rightfirst-time development of multi-processor designs with large numbers of controllers and peripherals.
2.1 About System on Chip (SoC) SOC is a device which integrates all the computer devices on to one chip, which runs with with desktop operating system systems li like wind windows, ows, L inux nux etc. The T he contras contrastt with with a microcontroll crocontroller is is one one of degre degree e. Mi M icrocontroll crocontrolle ers typically typicall y have have unde under 100 KB KB of RAM (ofte (often n just a few few kilo kilobyte bytes) and often reall really y are are si singl ngle-chip-sys chip-system tems, whereas the term term SoC is typicall typically used used with with more powerful processors, capable of running software such as the desktop versions of Wind Windows ows and and L inux, which which ne need exte externa rnall memory chips chips (fl (flash, ash, RA RA M) to be use useful ful,, and which which are use used d with with various various external external per peripherals. rals. I n short, for larger system systems system system on a chip chip is hyperbole, indicating technical direction more than reality: increasing chip integration to reduce manufacturi anufacturing costs and and to enable ble smal smalller systems. Many M any interesting interesting systems are are too compl complex ex to fit on just just one chip chip bui buillt with with a process optim optimized for just one of the system system's tasks. tasks. When it is not feasible to construct an SoC for a particular application, an alternative is a system system in package (Si (SiP) comprisi prising ng a num number ber of chips chips in in a single single package package. I n large large volumes, SoC is believed to be more cost-effective than SiP since it increases the yield of the fabrication and and because its packagi packaging ng is sim simpler. pler.
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2.1.1 Structure of SoC A typical SoC consists of:
A microcontroller, microprocessor or DSP core(s). Some SoCs—called multiprocessor system on chip (MPSoC)—include more than one processor core.
Memory blocks including a selection of ROM, RAM, EEPROM and flash memory. Timing sources including oscillators and phase-locked loops.
Peripherals including counter-timers, real-time timers and power-on reset generators.
External interfaces including
industry
standards
such
as USB, FireWire, Ethernet, USART, SPI.
Analog interfaces including ADCs and DACs.
Voltage regulators and power management circuits. These blocks are connected by either a proprietary or industry standard bus such as
the AMBA bus
from ARM
Holdings. DMA controllers
route data
directly
between
external interfaces and memory, bypassing the processor core and thereby increasing the data throughput of the SoC.
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AXI -
AXI APB -
Figure 2.0 ARM-SoC Block Diagram
2.2 About Advanced Microcontroller Bus Architecture (AMBA) Advanced Microcontroller Bus Architecture (AMBA) specification defines an on chip communications standard for designing high-performance embedded microcontrollers. The de facto standard for on-chip communication. The AMBA protocol is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates rightfirst-time development of multi-processor designs with large numbers of controllers and peripherals. AMBA promotes design re-use by defining a common backbone for SoC modules using specifications for ACE, AXI, AHB, APB and ATB. 5
AMBA 4 is the latest addition to the AMBA family adding five new interface protocols: ACE for full cache coherency between processors; ACE-Lite for I/O coherency; AXI4 to maximize performance and power efficiency; AXI4-Lite and AXI4-Stream ideal for implementation in FPGA. Another family of buses that the Power.org Bus Architectures TSC decided to investigate is the ARM AMBA (Advanced Microcontroller Bus Architecture) set of buses: APB, AHB and AXI. The APB (Advanced Peripheral Bus) is considered a low-performance, peripheral level bus. The AHB (Advanced High-performance Bus) is considered (despite the bus name) a midperformance bus and the AXI (Advanced eXtensible Interface) bus is considered a highperformance bus. The AMBA family of buses was chosen for consideration because of their widespread acceptance in the industry and large amount of existing IP cores. We note in passing that the APB bus is not always used as a standalone bus. Some AMBA based IP cores will use a higher performing bus like AHB or AXI for the primary function, but use an APB port for access to configuration registers.
2.2.1 AMBA Specifications AMBA enables IP re-use IP re-use is an essential component in reducing SoC development costs and timescales. AMBA specifications provide the interface standard that enables IP re-use meeting the essential requirements of: 1. Flexibility IP re-use requires a common standard while supporting a wide variety of SoCs with different power, performance and area requirements. With its ACE, AXI, AHB and APB interface protocols; AMBA 4 has the flexibility to match every requirement. 2. Multi-Layer
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The Multi-layer architecture acts as a crossbar switch between masters and slaves in an AMBA 3 AXI or AHB system. The parallel links allow the bandwidth of the interconnect to support the peak bandwidth of the masters without increasing the frequency of the interconnect. 3. Compatibility It is a standard interface specification that ensures compatibility between IP components from different design teams or vendors. The AMBA specification is available as both a written specification as well as a set of assertions that unambiguously define the interface protocol, thus ensuring this level of compatibility. 4. Support The wide adoption of AMBA specifications throughout the semiconductor industry has driven a comprehensive market in third party IP products and tools to support the development of AMBA based systems. Theavailability of AMBA assertions promotes this industry wide participation.
2.2.2Design principles of AMBA The important aspect of a SoC is not only which components or blocks it houses, but also how they are interconnected. AMBA is a solution for the blocks to interface with each other. The objective of the AMBA is to: 1. facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors, 2. be technology independent, to allow reuse of IP cores, peripheral and system microcells across diverse IC processes, 3. encourage modular system design to improve processor independence, and the development of reusable peripheral and systemIP libraries Minimize silicon infrastructure while supporting high performance and low power on-chip communication.
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2.2.3AMBA Versions 1.VER1.0(ASB&APB) 2.VER2.0(AHB) 3.VER3.0(AXI,ATB) 4. VER 4.0 (AXI 4,AXI LITE,AXI STREAM (AXI))
2.2.4 AMBA 4.0 specification buses/interfaces o Advanced eXtensible Interface (AXI)
AXI4
AXI4-Lite
AXI-4 Stream
o Advanced High-performance Bus (AHB) o Advanced System Bus (ASB) o Advanced Peripheral Bus (APB) o Advanced Trace Bus (ATB) In this project these are to be used Advanced eXtensible Interface (AXI4-Lite)& Advanced Peripheral Bus (APB) because these are high bandwidth data transfer between high performance devices like processor, DMA, RAM etc..,. and Peripheral devices.
2.3 About Advanced eXtensible Interface (AXI) In previous SOC design a lot of buses are used which are introduced by ARM. ARM introduced ASB the first High data transfer between modules, then again ARM introduced AHB and AXI in followed version of AMBA. ARM AMBA (Advanced Microcontroller Bus Architecture) set of buses: ASB, AHB and AXI. The AHB (Advanced High-performance Bus) is considered (despite the bus name) a mid-performance bus and the AXI (Advanced eXtensible Interface) bus is considered a high-performance bus. The AMBA family of buses was chosen for consideration because of their widespread acceptance in the industry and large amount of existing IP cores. History of High-Performance Buses 8
1. ASB (Advanced System Bus) 2. AHB (Advanced High-performance Bus) 3. AXI (Advanced eXtensible Interface) 1. AXI4 2. AXI4-Lite 3. AXI4-Stream 1. ASB (Advanced System Bus) The Advanced System Bus (ASB) specification defines a high-performance bus that can be used in the design of high performance 16 and 32-bit embedded microcontrollers. AMBA ASB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral microcell functions. The bus also provides the test infrastructure for modular macro cell test and diagnostic access. The features of ASB are; 1. High performance 2. Pipelined operation 3. Burst transfers 4. Multiple bus masters
2. AHB (Advanced High-performance Bus) AHB is the mid-performance bus in the AMBA family. The protocol defines a 32-bit address bus (HADDR), but this has been extended in some implementations. The read and write data buses (HRDATA and HWDATA) may be defined under the specification as 2n bits wide, from 8-bit to 1024-bit, but the most common implementation has been 32-bit. With 27 additional control signals, and assuming the most common address and data bus width of 32-bit, AHB can have up to 123 I/O for each AHB master.
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Up to 16 AHB masters may be connected to a central interconnect which arbitrates between master requests, and multiplexes the winning request and corresponding transfer qualifiers to the slaves. Slave read data is multiplexed back to the masters. In addition to previous release, it has the following features: 1. single edge clock protocol 2. split transactions 3. several bus masters 4. burst transfers 5. pipelined operations 6. single-cycle bus master handover 7. non-tristate implementation 8. Large bus-widths (64/128 bit). A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX (non-tristate), thereby admitting bus-access to one bus-master at a time.
3. AXI (Advanced eXtensible Interface) AXI is the high-performance bus in the AMBA family. The architecture defines three write channels and two read channels. The write channels are address, write data, and response. The read channels are address and read data. The address channels include 32-bit address buses, AWADDR and ARADDR, but this could be extended in some implementations. The write and read data buses (WDATA and RDATA) may be defined under the specification as any 2n number, from 8-bit to 1024-bit. With the assumption that both the address and data buses are 32bit, and that the data buses are 128-bit, the write address, write data, and write response channels would require 56, 139, and 8 I/O, respectively. The read address and read data channels would 10
require 56 and 137 I/O, respectively. Thus, each 128-bit AXI master has 396 I/O total. AXI masters and slaves are connected together through a central interconnect, which routes master requests and write data to the proper slave, and returning read data to the requesting master. The interconnect also maintains ordering based on tags if, for example, a single master pipelines read requests to different slaves. AXI uses a handshake between VALID and READY signals. VALID is driven by the source, and READY is driven by the destination. Transfer of information, either address and control or data, occurs when both VALID and READY are sampled high. AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micrometer interconnect. 1. separate address/control and data phases 2. support for unaligned data transfers using byte strobes 3. burst based transactions with only start address issued 4. issuing of multiple outstanding addresses 5. Easy addition of register stages to provide timing closure.
The AXI Revisions (Advanced eXtensible Interface) 1. AXI4 2. AXI4-Lite 3. AXI4-Stream The table shows the differences between Interface parameters for above revisions.
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Table 2.0 Interface parameters for AXI4 and AXI4-Lite
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Table 2.1 Interface parameters for AXI4-Stream
1. AXI4 signals modified in AXI4-Lite The AXI4-Lite interface does not fully support the following signals: RRESP, BRESP 2. AXI4 signals not supported in AXI4-Lite The AXI4-Lite interface does not support the following signals: a) AWLEN, ARLEN The burst length is defined to be 1, equivalent to an AxLEN value of zero. b) AWSIZE, ARSIZE All accesses are defined to be the width of thedata bus. c) AWBURST, ARBURST Theburst type has no meaning because the burst length is 1. d) AWLOCK, ARLOCK All accesses are defined as Normal accesses, equivalent to an AxLOCK value of zero. e) AWCACHE, ARCACHE All accesses are defined as Non-modifiable, Non-buffer able, equivalent to an Ax CACHE value of 0b0000. Note:-AXI4-Lite requires a fixed data bus width of either 32-bits or 64-bits 13
2.4 About the Advanced Peripheral Bus (APB) The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB protocol is not pipelined, use it to connect to low-bandwidth peripherals that do not require the high performance of the AXI protocol. The APB protocol relates a signal transition to the rising edge of the clock, to simplify the integration of APB peripherals into any design flow. Every transfer takes at least two cycles. The APB can interface with: 1. AMBA Advanced High-performance Bus (AHB) 2. AMBA Advanced High-performance Bus Lite (AHB-L ite) 3. AMBA Advanced Extensible Interface (AXI) 4. AMBA Advanced Extensible Interface Lite (AXI4-Lite) Y ou can use it to access the programmable control registers of peripheral devices. 2.4.1APB revisions The APB Specification Rev E, released in 1998, is now obsolete and is superseded by the following three revisions: 1. AMBA 2 APB Specification 2. AMBA 3 APB Protocol Specification v1.0 3. AMBA APB Protocol Specification v2.0.
Out of these AMBA APB Protocol Specification v2.0 is used in this project. AMBA 2 APB Specification 14
This specification defines the interface signals; the basic read and write transfers and the two APB components the APB Bridge and the APB slave. This version of the specification is referred to as APB2. AMBA 3 APB Protocol Specification v1.0 The AMBA 3 APB Protocol Specification v1.0 defines the following additional functionality: •
Wait states.
•
Error reporting.
The following interface signals support this functionality: PREADY A ready signal to indicate completion of an APB transfer. PSLVERR An error signal to indicatethe failure of a transfer. This version of the specification is referred to as APB3. AMBA APB Protocol Specification v2.0 The AMBA APB Protocol Specification v2.0 defines the following additional functionality: •
Transaction protection.
•
Sparse data transfer.
The following interface signals support this functionality: PPROTA protection signal to support both non-secure and secure transactions on APB. PSTRBA write strobe signal to enable sparse data transfer on the write data bus. This version of the specification is referred to as APB4. 2.5Different types of Bridges
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1. ASB to APB Bridge 2. AHB to APB Bridge 3. AXI4-Lite to APB Bridge Out of these AXI4-Lite to APB Bridge is used for this project. This is the latest bridge. 1. ASB to APB Bridge The APB Bridge provides an interface between the ASB and the Advanced Peripheral Bus (APB). It continues the pipelining of the ASB by inserting wait cycles on the ASB only when they are needed. It inserts them for burst transfers or read transfers when the ASB must wait for the APB.
Fig. 2.1 ASB to APB Bridge Block Diagram
The implementation of this block contains: 1. a state machine, which is independent of the device memory map 16
2. ASB address, and data bus latching 3. Combinatorial address decoding logic to producePSELxsignals. To add new peripherals, or alter the system memory map only the address decode section needs to be modified 2. AHB to APB Bridge The AHB2APB interfaces the AHB to the APB. It buffers address, control and data from the AHB, drives the APB peripherals and returns data and response signals to the AHB. It decodes the address using an internal address map to select the peripheral. The AHB2APBis designed to operate when the APB and AHB clocks have the same frequency and phase. In addition to supporting all basic requirements for AMBA compliance, the AHB2APB provides enhancements to the APB protocol. With AHB2APB, an APB peripheral can insert wait states by holding its pready signal low for the required number of cycles. In the AMBA specification, APB accesses are word-wide (32 bits). The AHB2APB provides the signal pbyte_enable[3:0] to allow byte and half-word accesses. These can be used by the APB peripheral as necessary. The AHB2APB does not perform any alignment of the data, but transfers data from the AHB to the APB for write cycles and from the APB to the AHB for read cycles. The AHB2APB does not support burst transfers and converts any burst transfers into a series of APB accesses. The AHB slave interface supplied by the AHB2APB does not make use of the split response protocol.
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Fig. 2.2 AHB to APB Bridge Block Diagram
3. AXI4-Lite to APB Bridge In this study, we focused mainly on the implementation aspect of an AXI4-Lite to APB Bridge. The AXI4-Lite to APB Bridge provides an interface between the high-performance AXI domain and the low power APB domain. It appears as a slave on AXI bus but as a master on APB that can access up to sixteen slave peripherals. Read and write transfers on the AXI bus are converted into corresponding transfers on the APB. The AXI4-Lite to APB bridge Block diagram is shown in Figure. (2.3)
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Fig. 2.3 AXI to APB Bridge Block Diagram
Features of bridge The Xilinx AXI to APB Bridge is a soft IP core with these features: 1. AXI interface is based on the AXI4-Lite specification 2. APB interface is based on the APB3 specification, supports optional APB4 selection 3. Supports 1:1 (AXI:APB) synchronous clock ratio 4. Connects as a 32-bit slave on 32-bit AXI4-Lite 5. Connects as a 32-bit master on 32-bit APB3/APB4 6. Supports optional data phase time out
2.6 Connections of an Asynchronous FIFO The Asynchronous FIFO is a First-In-First-Out memory queue with control logic that performs management of the read and write pointers, generation of status flags, and optional handshake signals for interfacing with the user logic. Almost Full Flag: Generates an Almost Full signal, indicating that one additional write can be performed before the FIFO is full.
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Almost Empty Flag: Generates an Almost Empty signal, indicating that one additional read can be performed before theFIFO is empty. The optional handshaking control signals (acknowledge and/or error) can be enabled via the Handshaking Options . • Read Acknowledge Flag: Asserted active on the clock cycle after a successful read has occurred. This signal, when selected, can be made active high or low through the GUI. • Read Error Flag: Asserted active on the clock cycle after a read from the FIFO was attempted, but not successful. This signal, when selected, can be made active high or low through the GUI. • Write Acknowledge Flag: Asserted active on the clock cycle after a successful write has occurred. This signal, when selected, can be made active high or low through the GUI. • Write Error Flag: Asserted active on the clock cycle after a write to the FIFO was attempted, but not successful. This signal, when selected, can be made active high or low through the GUI.
Fig 2.4Connections of an Asynchronous FIFO
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3. DESIGN BACKGROUND Integrated circuits have entered the era of System-on-a-Chip (SoC), which refers to integrating all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on a single chip substrate. With the increasing design size, IP is an inevitable choice for SoC design. And the widespread use of all kinds of IPs has changed the nature of the design flow, making On-Chip Buses (OCB) essential to the design. The main criteria used to select buses for consideration were: 1. The level of acceptance and penetration in the industry: It would hinder acceptance of the bus hierarchy if an obscure set of buses were chosen that did not have an existing industry support structure and library of useful available IP. 2. Thetechnical ability to support the wide range of applications found in typical SoCs: It would be a mistake to specify a set of buses that lacked the features or sufficient bandwidth to support common SoC applications. 3. The ease of interfacing to Power Architecture processors: Given that the main goal of Power.org is to promote Power Architecture processors, it would make little sense for the Power.org Bus 4. Architectures to specify a set of buses that were difficult or cumbersome to attach to Embedded Power Processors or would add unnecessary bridges in the main transaction paths. 5. The ability to easily obtain a license for the bus architecture to create verification and core IP. Buses that have been restricted to internal development only were not considered in this report. Of all OCBs existing in the market, the AMBA bus systemis widely used as the de facto standard SoC bus. On March 8, 2010, ARM announced availability of the AMBA 4.0 specifications. As the de facto standard SoC bus, AMBA bus is widely used in the high21
performance SoC designs. The AMBA specification defines an on-chip communication standard for designing high-performance embedded microcontrollers. ARM introduced the Advanced Microcontroller Bus Architecture (AMBA) 4.0 specifications in March 2010, which includes advanced extensible Interface (AXI) 4.0. AMBA bus protocol has become the de facto standard SoC bus. That means more and more existing IPs must be able to communicate with AMBA 4.0 bus. Based on AMBA 4.0 bus, we designed an Intellectual Property (IP) core of AXI (Advanced extensible Interface) Lite to APB (Advanced Peripheral Bus) Bridge, which translates the AXI4.0-lite transactions into APB 4.0 transactions. The bridge provide Interfaces between the high-performance AXI bus and low-power APB domain. Advanced Microcontroller Bus Architecture (AMBA) specification defines an on chip communications standard for designing high-performance embedded microcontrollers. AMBA Versions 1.VER1.0(ASB&APB) 2.VER2.0(AHB) 3.VER3.0(AXI,ATB) 4.VER 4.0 (AXI 4,AXI LITE,AXI STREAM (AXI)) AMBA 4.0 specification buses/interfaces 1.AdvancedeXtensible Interface (AXI) AXI4 AXI4-Lite AXI-4 Stream Advanced High-performance Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB) Advanced Trace Bus (ATB)
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In this project these are to be used Advanced eXtensible Interface (AXI4-L ite)& Advanced Peripheral Bus (APB)because these are high bandwidth data transfer between high performance devices like processor, DMA, RAM etc..,. and Peripheral devices.
4.PROJECT AIM An Intellectual Property (IP) core of AXI4(Advanced eXtensible Interface) Lite to APB(Advanced Peripheral Bus) Bridge, which translates the AXI4.0-lite transactions into APB 4.0 transactions. The bridge provides interfaces between the high-performance AXI bus and lowpower APB domain.
4.1 Existing Model Overview: The AXI to APB Bridge translatesAXI4-Lite transactions into APB transactions. The bridge functions as a slave on the AXI4-Liteinterfaceandasa master on the APB interface. The AXI to APB Bridge main use model is to connect the APB slaves with AXI masters. Both AXI4Lite and APB transactions are happened during rising edge of the clock. The AXI to APB Bridge block diagram is shown in Figure (4.1) and described in subsequent sections.
Fig. 4.1. AXI to APB Bridge Block Diagram
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AXI4-L ite SlaveInterface The AXI4-Lite Slave Interface module provides a bidirectional slave interface to the AXI. The AXI address and data bus widths are always fixed to 32-bits and 1024bits. When both write and read transfers are simultaneously requested on AXI4-Lite, the read request is given more priority than the write request. This module also contains the data phase time out logic for generating OK response on AXI interface when APB slave does not respond. APB Master Interface The APB Master module provides the APB master interface on the APB. This interface can be APB3 or APB4, which can be selected by setting the generic C_M_APB_PROTOCOL. When C_M_APB_PROTOCOL=apb4, the M_APB_PSTRB, and M_APB_PPROT signals are driven at the APB Interface. The APB address and data bus widths are fixed to 32-bits.
4.2 Features of the project We provide an implementation of AXI4-L ite to APB Bridgewhich has the following features: 1. 32-bit AXI slave and APB master interfaces. 2. PCLK clock domain completely independent of ACL K clock domain. 3. Support up to 16 APB peripherals. 4. Support the PREADY signal which translates to wait states on AXI. 5. An error on any transfer results in SLVERR as the AXI read/write response.
4.3 Proposed Model In the proposed model we try to interface the APB bridge to UART transmitter and a receiver. AXI4-LITE to APB bridge we interface it to an UART Transmitter and receiver to send and receive bits from high performance AXI4-LITE bus to UART as axi_uart interface. For transmitting and receiving data bits from or to UART transmitter and receiver we append start bit as of to show the initialization of sequence and stop bit to show completion of 24
sequence. Apart from the start and stop bits we also have parity bit which shows the odd/even parity of the sequence. So we have each one bit of a start bit, stop bit and parity bit, and also 8 bits of data. In UART instead of using the normal clock cycle we use the baud clock which is 8 clock cycles, which means for every 8 clock cycles or for every one baud clock cycle the data sequence gets transmitted/ received . When the write address is selected the data sent (WDATA) of 8 bits along with start , stop and parity bit gets transmitted on to the uart transmitter. similarly during the receiving when the read register is selected the data from RDATA is read onto the uart receiver . For AXI-UART the AWADDR(write address) gives the address of the UART register and gets selected whether it is to read, write or control. When the address on AWADDR is 00 the write data is stored in WADDR, when the address on AWADDR is 02 the data bits stored on WDATA is transmitted into UART_tx. When the read address (ARADDR) is 01 the data bits present on the UART_rx is read onto the RDATA ( read data). UART A Universal Asynchronous Receiver/Transmitter, abbreviated UART is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA, RS-232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such as differential signaling etc.) typically are handled by a special driver circuit external to the UART. A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. 25
Transmitting and receiving serial data `
The Universal Asynchronous Receiver/Transmitter (UART) takes bytes of data and
transmits the individual bits in a sequential fashion. [1] At the destination, a second UART reassembles the bits into complete bytes. Each UART contains a shift register, which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels. External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically, current (in current loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC-LIN for power line communication. Communication may be simplex (in one direction only, with no provision for the receiving device to send information back to the transmitting device), full duplex (both devices send and receive at the same time) or half duplex (devices take turns transmitting and receiving).
Character framing
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The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy, in which the line is held high to show that the line and transmitter are not damaged. Each character is sent as a logic low start bit, a configurable number of data bits (usually 8, but legacy systems can use 5, 6, 7 or 9), an optional parity bit, and one or more logic high stop bits. The start bit signals the receiver that a new character is coming. The next five to eight bits, depending on the code set employed, represent the character. Following the data bits may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters. Obviously a problem exists if a receiver detects a line that is low for more than one character time. This is called a "break." It is normal to detect breaks to disable a UART or switch to an alternative channel. Sometimes remote equipment is designed to reset or shut down when it receives a break. Premium UARTs can detect and create breaks.
Receiver All operations of the UART hardware are controlled by a clock signal which runs at a multiple of the data rate. For example, each data bit may be as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register is made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. The best UARTs "resynchronize" on each change of the data line that is more than a half-bit wide. I n this way, they reliably receive when the transmitter is sending at a slightly different speed than the receiver. (This is the normal case, because communicating units usually have no 27
shared timing system apart from the communication signal.) Simplistic UARTs may merely detect the falling edge of the start bit, and then read the center of each expected data bit. A simple UART can work well if the data rates are close enough that the stop bits are sampled reliably. It is a standard feature for a UART to store the most recent character while receiving the next. This "double buffering" gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-out FIFO buffer memory between the receiver shift register and the host systeminterface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.
Transmitter Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line, generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since fullduplex operation requires characters to be sent and received at the same time, practical UARTs use two different shift register
Application Transmitting and receiving UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system.
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Typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ASCII characters per second equals the bit rate divided by 10. Some very low-cost home computers or embedded systems dispensed with a UART and used the CPU to sample the state of an input port or directly manipulate an output port for data transmission. While very CPU-intensive, since the CPU timing was critical, these schemes avoided thepurchase of a UART chip that was costly in the 1970's. The technique was known as a bit-banging serial port.
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5. PROJECT OVERVIEW An AMBA-based microcontroller typically consists of a high-performance system backbone bus (AMBA AXI Lite), able to sustain the external memory bandwidth, on which the CPU, on-chip memory and other Direct Memory Access (DMA) devices reside. This bus provides a high-bandwidth interface between the elements that are involved in the majority of transfers. Also located on the high performance bus is a bridge to the lower bandwidth APB, where most of the peripheral devices in the system are located see Figure (5.1).
Fig. 5.1 Overview of AXI Lite to APB Bridge
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5.1 About the Advanced eXtensible Interface (AXI) Protocol: The AMBA AXI protocol supports high-performance, high-frequency systemdesigns. The AXI protocol: 1. is suitable for high-bandwidth and low-latency designs 2. provides high-frequency operation without using complex bridges 3. meets the interface requirements of a wide rangeof components 4. is suitable for memory controllers with high initial access latency 5. Provides flexibility in the implementation of interconnect architectures is backwardcompatible with existing AHB and APB interfaces. The key features of the AXI protocol are: 1. Separate address/control and data phases 2. Support for unaligned data transfers, using byte strobes 3. uses burst-based transactions with only the start address issued 4. separate read and write data channels that can provide low-cost DMA 5. Support for issuing multiple outstanding addresses 6. Support for out-of-order transaction completion 7. Permits easy addition of register stages to provide timing closure. The AXI protocol includes the optional extensions that cover signaling for low-power operation AXI Revisions 1. AXI4 31
2. AXI4-Lite 3. AXI4-stream Note: Out of these AXI4-Lite is used. 1. AXI4: The AXI4 protocol is an update to AXI3 to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements: 1. Support for burst lengths up to 256 beats 2. Quality of Service signaling 3. Support for multiple region interfaces 2. AXI4-Lite: The AXI4-Lite protocol is a subset of the AXI4 protocol intended for communication with simpler, smaller control register style interfaces in components. The key features of the AXI4Lite interface are: 1. All transactions are burst length of one 2. All data accesses are the same size as the width of the data bus 3. Exclusive accesses are not supported 3. AXI4-Stream: The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features are 1. Supports single and multiple data streams using the same set of shared wires 2. Support for multiple data widths within the same interconnect 3. Ideal for implementation in FPGA 32
5.1.1AXI strengths: AXI offers several features that allow for high performance. However, achieving the highest performance at a system level requires that all of the AXI masters and slaves are designed to a high performance target, since,. AXI can use the higher frequency along with a data bus that can be defined to 128-bit and above to achieve the band 1. Data Pipelining: Buses that do not pipeline cannot achieve full bus utilization and peak bandwidth given that there will be transfer latency to and from the slaves. AXI supports 16 deep read and 16 deep write data pipelining. This allows for full bus utilization, even with interfaces with extremely long latency. 2. Multiple Data Beats per Burst Request: AXI address and data phases are independent from one another, so a burst request that is accepted by a slave when READY and VALID are active must consist of the number of data beats the master requested, with no further interaction with the address and control signals. The driver of the burst data also sends a LAST signal to mark the last beat of burst data. width required for mid- and some high-performance bus applications 3. Write Strobes: AXI defines write strobes to enable the transfer of some or all of the bytes on the write data bus in a single beat. Given a128-bit AXI, this allows any number of bytes between 1 and 16 to be transferred in a single beat on the write data bus. Buses that do not support write strobes can require that multiple transfers be made for bytes inside a single quad word. Having write strobes also enables AXI masters to limit propagation of write data with errors. If the master discovers there are errors in write data that has yet to be sent to AXI, it is allowed to complete the burst from a data beat standpoint, but without enabling any of the write strobes. 4. Out-of-order Reads: 33
AXI uses the ARID [3:0] bus on the read address channel to allow slaves to return read data out-of-order with respect to the order of the read requests. Reads made with the same ARID[3:0] must remain in order, but reads made with different ARID[3:0] may be returned outof-order. This improves read data channel utilization by allowing slaves with shorter latencies to return data as soon as it is available, rather than forcing them to return in the request order, potentially behind a slave with much longer read latency. This is a better mechanism than performing delayed reads, since they require communication between the master and slave once the read data is available, and then a subsequent repeat of the read request from the master. Simple slaves may not choose to implement out-of-order read data, so system integrators must be careful when selecting IP to be placed on the same AXI interconnect. Simple slaves with long latency will negate the benefit of the other slaves performing reads out-of-order, since the interconnect must guaranteethat reads with the same ARID from different slaves return read data in the same order in which the requests were made. 5. Write Data Interleaving: Multiple AXI masters may attempt to write data to a single slave at the same time. Some master’s buffer all of the write data before making the request, but others assemble data to send after the request is made. AXI slaves that support write data interleaving can accept write data from both types of masters in what looks like a single data tenure, with the AWID value switching between the masters sending write data. This allows interconnect to avoid stalling the write data bus to the slave, waiting for writes data to be assembled. Instead, the interconnect sends write data from a “buffered write” master in between beats of write data from the “assemble write” master. 6. Separate Data Buses: AXI doubles the peak bandwidth at a given frequency by using separate buses for read and write data. These buses are used in conjunction with data pipelining to increaseperformance. 7. Handshaking: The VALID and READY handshaking mechanism in AXI allows both masters and slaves to control the flow of data. This can be problematic if, for example, a poorly designed 34
master makes a write request while still assembling write data that is coming in from a slower or narrower interface. One real benefit of having the handshake mechanism is that slaves with long latencies can accept more requests than they have buffer space for. So, for example, an AXI PCIe slave may queue eight reads, but only have enough buffer space for four. The slave can do this if the masters are guaranteed to accept the read data when the slave drives it back. This is an area and cost savings, but requires knowledge of specific AXI master capabilities, and should therefore beimplemented as a configuration option in a general purpose AXI slave. 8. Exclusive Access: AXI supports an exclusive access mechanism that enables semaphore types of operations without requiring the bus to be locked. The process is 1)A master requests an exclusive read from an address location, 2)The same master, sometime later, attempts to complete the exclusive operation by attempting an exclusive write to the same address. The exclusive write is only able to complete successfully if no other master has written to that location between the exclusive read and writeand this mechanism could be used to improve the performance of Power processors attached to AXI. 9. No Slave Burst Termination: Once an AXI slave acknowledges a burst transfer, it is responsible for accepting all of the write data or generating all the read data associated with that burst. This simplifies master designs, since the master does not have to prepare to make a subsequent request if the slave terminated the original request before all of its data was transferred. Giving slaves the ability to terminate bursts is not required when the burst length is declared with the request, and is reasonably short. AXI bursts are 16 beats or fewer. 10. Excellent Verification Support: AXI offers a large selection of verification IP from several different suppliers. The solutions offered support several different languages and run in a choice of environments. 11. Flexible Complexity: 35
AXI masters and slaves are more difficult to design than AHB masters and slaves. However, there are several optional features that may be left unimplemented in order to reduce the increase in complexity. And may be somewhat offset with the availability of more sophisticated verification support. 12. Data Bus Width: AXI is defined with a choice of several bus widths, in 2n increments from 8-bit to 1024bit. The ability to select the data bus width at the time of synthesis improves the scalability (in peak bandwidth) of the core IP. However, supporting even a few bus widths does add to the complexity of the design, and choices need to interlock with other core IP to maintain interoperability. 13. Error Reporting: AXI defines errors in the read and write response channels. The slave can respond with SLVERR if it detects a problem, and the interconnect can respond with DECERR if no slave accepts thetransfer. Interrupts from masters are handled outside the AXI architecture. 14. IP Core Portability: The vast majority of the IP cores designed with an AXI interface are available as “synthesizable” cores. The source Verilog or VHDL is provided and synthesized into the target technology.
5.2AXI Architecture The AXI protocol is burst-based and defines the following independent transaction channels: 1. read address 2. read data 3. write address 4. write data 36
5. Write response. An address channel carries control information that describes the nature of the data to be transferred. The data is transferred between master and slave using either: 1. A write data channel to transfer data from the master to the slave. In a write transaction, the slave uses the write response channel to signal the completion of the transfer to the master. 2. A read data channel to transfer data from the slave to the master. The AXI protocol: 1. Permits address information to be issued ahead of the actual data transfer 2. supports multiple outstanding transactions 3. Supports out-of-order completion of transactions. Figure (5.2) shows how a read transaction uses the read address and read data channels.
Fig 5.2 Channel architecture of reads
Figure 5.3 shows how a write transaction uses the write address, write data, and write response channels. 37
Fig 5.3 Channel architecture of writes
Channel definition for AXI Architecture Each of the independent channels consists of a set of information signals, inthese VALID and READY signals that provide a two-way handshake mechanism. Transfer occurs only when both the VALID and READY signals are HIGH. All five transaction channels use the same VALID/READY
handshake process to transfer address, dataand controlinformation.
The information source uses the VALID signal to show when valid address, data or control information is available on the channel. The destination uses the READY signal to show when it can accept the information. Both the read data channel and the write data channel also include a LAST signal to indicate the transfer of the final data itemin a transaction. 1.Readandwriteaddresschannels. Read and write transactions each have their own address channel which carries all of the required address and control information for a transaction. 2. Read data channel. The read data channel conveys both the read data and read response information from the slave back to the master. It includes:
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1. The data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide (RDATA) 2. A 3.
read response indicating the completion status of
the read transaction.
Data and response group signals are maintained until the RReady signal is asserted
3. Write data channel. The write data channel conveys the write data from the master to the slave and includes 1. The data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide (WDATA) 2. One byte lane strobe for every byte, indicating which bytes of the data bus are valid (WSTRB) 3. The last transfer inside a burst must be signaled through the WL AST signal data, strobe and WL ast information are maintained until the WReady signal is asserted. 4. Write Response channel. The write response channel provides a way for the slave to respond to write transactions. 1. All write transactions usecompletion signaling. 2. The completion signal occurs once for each burst, not for each individual data transfer within the burst. 3. Response group signals are maintained until the BReady signal is asserted. 5.3About the Advanced Peripheral Bus (APB) Protocol The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. APB revisions The APB Specification Rev E, released in 1998, is now obsolete and is superseded by the following three revisions: 1. AMBA 2 APB Specification 2. AMBA 3 APB Protocol Specification v1.0 39
3. AMBA APB Protocol Specification v2.0. Out of these using AMBA APB Protocol Specification v2.0. The APB Bus is the lowest performance bus in the AMBA family. There are separate address (PADDR), write data (PWDATA), and read data (PRDATA) buses, up to 32-bits each. With 7 additional control signals, there can be up to 103 I/O for each APB slave. There is one APB master, usually the bridge from a higher performance bus that begins a transfer by asserting the appropriatePSELn signal with PADDR. PWRITE is active for a write and inactive on a read. PENABLE is asserted in the second clock, and is held active until PREADY is returned by the slave. The minimum transfer, read or write, is two clocks. APB slaves also have the option of inserting wait states for reads or writes by withholding PREADY . There is an optional PSLVERR signal used by the slave to report an error on a read or write with PREADY . Assuming a frequency of 133MHz, (which should be achievable in a 90nm or smaller process) and the maximum data bus widths of 32-bits, the overall APB bandwidth could be as high as 267MB/s, but that assumes that none of the APB slaves would insert any wait states. Also, the total APB bandwidth must be shared between all of the APB slaves.
5.3.1APB strengths The APB offers a very low cost (based on area), very low power (based on I/O), and the least amount of complexity. It is intended for use with simple slaves that do not require much bandwidth. 1. Interface Simplicity: The APB interface and protocol are very simple and easy to learn. Relatively little effort needs to be spent on APB design and verification, leaving more time to focus on the device logic. 2. Core IP: There are more than 75 APB cores available from at least 20 different companies. The cores cover a broad range of small bandwidth applications. There is also verification enablement in models and checkers/monitors available from at least 6 different companies with support for 5 different languages.
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3. Verification IP: There is verification enablement for APB in models and checkers/monitors available from at least 6 different companies with support for 5 different languages 4.Bridges Exist: APB cores are accessed by the AHB-to-APB or AXI-to-APB Bridge. 5. IP Core Portability: Most of the IP cores designed with an APB interface are available as “synthesizable” cores. The source code, written in Verilog or VHDL, is provided and synthesized into the target technology. This I P delivery method typically presents few timing challenges at the 66-133MHz range expected for APB. 6. Error Reporting: APB defines an optional signal, PSLVERR, driven by APB slaves on reads or writes with PREADY to indicate an error with the transfer.
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6.SIGNAL CONNECTIONS Figure (6.1) shows the component signal connections. The bridge uses: • AMBA AXI-L ite and APB signals as described in the AMBAAXI-Lite 4.0 protocol specification.
Fig 6.1 Signal connections 42
INPUT
/
OUTPUT
signal
descriptionsXI4-Lite
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Signals
list:-
Table 6.1 signal connections for AXI4-Lite
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APB Signals list:-
Table 6.2 signal connections for APB
6.1 Handshake mechanisms of AXI & APB In AXI 4.0 specification, each channel has VALID and READY signals for handshaking. The source asserts VALI D when the control information or data is available. The destination asserts READY when it can accept the control information or data. Transfer occurs only when both the VALID and READY are asserted. Figure 6.2 Shows all possible cases of 45
VALID/READY handshaking. Note that when source asserts VALID, the corresponding control information or data must also be available at the same time. The arrows in Figure. Indicate when the transfer occurs. A transfer takes place at the positive edge of clock. Therefore, the source needs a register input to sample the READY signal. In the same way, the destination needs a register input to sample the VALID signal. Considering the situation of Figure(c), we assume the source and destination use output registers instead of combination circuit, they need one cycle to pull low VALID/READY and sample the VALID/READY again at T4 cycle. When they sample the VALID/READY again at T4, there should be another transfer which is an error. Therefore source and destination should use combinational circuit as output. In short, AXI protocol is suitable register input and combinational output circuit. The APB Bridge buffers address, control and data from AXI4-Lite, drives the APB peripherals and returns data and response signal to the AXI4-Lite. It decodes the address using an internal address map to select the peripheral. The bridge is designed to operate when the APB and AXI4-L ite have independent clock frequency and phase. For every AXI channel, invalid commands are not forwarded and an error response generated. That is once a peripheral accessed does not exist, the APB Bridge will generate DE CERR as response through the response channel (read or write). And if the target peripheral exists, but asserts PSLVERR, it will give a SLVERR response.
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Fig. 6.2. Waveforms for handshaking mechanism
6.2 Asynchronous FIFO An asynchronous FIFO refers to a FI FO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from 47
another clock domain, where the two clock domains are asynchronous to each other. Asynchronous FIFOs are used to safely pass data from one clock domain to another clock domain. There are many ways to do asynchronous FIFO design, including many wrong ways. Most incorrectly implemented FIFO designs still function properly 90% of the time. Most almost-correct FIFO designs function properly 99%+ of the time. Unfortunately, FIFOs that work properly 99%+of the time have design flaws that are usually the most Difficult to detect and debug (if you are lucky enough to notice the bug before shipping the product), or the most costly to diagnose and recall. 6.2.1 Passing multiple asynchronous signals: Attempting to synchronize multiple changing signals from one clock domain into a new clock domain and insuring that all changing signals are synchronized to the same clock cycle in the new clock domain has been shown to be problematic. FIFOs are used in designs to safely pass multi-bit data words fromone clock domain to another. Data words are placed into a FIFO buffer memory array by control signals in one clock domain, and the data word sare removed from another port of the same FIFO buffer memory array by control signals froma second clock domain. Conceptually, the task of designing a FIFO with these assumptions seems to be easy. 6.2.2 Asynchronous FI FO pointers: In order to understand FIFO design, one needs to understand how the FIFO pointers work. The write pointer always points to the next word to be written; therefore, on reset, both pointers are set to zero, which also happens to bethe next FIFO word location to be written. On a FIFO-write operation, the memory location that is pointed to by the write pointer is written, and then the write pointer is incremented to point to the next location to be written. Similarly, the read pointer always points to the current FIFO word to be read. Again on reset, both pointers are reset to zero, the FIFO is empty and theread pointer is pointing to invalid data (because the FIFO is empty and the empty flag is asserted). As soon as the first data word is written to the FIFO, the write pointer increments, the empty flag is cleared, and the read pointer that is still addressing the contents of the first FIFO memory word, immediately drives that first 48
valid word onto the FIFO data output port, to be read by the receiver logic. The fact that the read pointer is always pointing to the next FIFO word to be read means that the receiver logic does not have to use two clock periods to read the data word. If the receiver first had to increment the read pointer before reading a FIFO data word, the receiver would clock once to output the data word from the FIFO, and clock a second time to capture the data word into the receiver. That would be needlessly inefficient. The FIFO is empty when the read and write pointers are both equal. This condition happens when both pointers are reset to zero during a reset operation, or when the read pointer catches up to the write pointer, having read the last word fromthe FIFO. A FIFO is full when the pointers are again equal, that is, when the write pointer has wrapped around and caught up to the read pointer. This is a problem. The FIFO is either empty or full when the pointers are equal, but which? One design technique used to distinguish between full and empty is to add an extra bit to each pointer. When the write pointer increments past the final FIFO address, the write pointer will increment the unused MSB while setting the rest of the bits back to zero as shown in Figure 1 (the FIFO has wrapped and toggled thepointer MSB). The same is done with the read pointer. If the MSBs of the two pointers are different, it means that the write pointer has wrapped one more time that the read pointer. If the MSBs of the two pointers are the same, it means that both Pointers have wrapped the same number of times. Using n-bit pointers where (n-1) is the number of address bits required to access the entire FIFO memory buffer, the FIFO is empty when both pointers, including the MSBs are equal. And the FIFO is full when both pointers, except the MSBs are equal. The FIFO design in this paper uses n-bit pointers for a FIFO with 2(n-1) write-able locations to help handle full and empty conditions. More design details related to the full and empty logic.
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Fig. 6.3 FIFO full and empty conditions
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7. MECHANISM OF AXI & APB
7.1 Finite state machine A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition. A particular FSM is defined by a list of the possible transition states fromeach current state, and the triggering condition for each transition. Finite-state machines can model a large number of problems, among which are electronic design automation, communication protocol design, parsing and other
engineering applications.
In biology and artificial intelligence research, state machines or hierarchies of state machines are sometimes used to describe neurological systems, and in linguistics they can be used to describe the grammars of natural languages.
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7.2 State DiagramOf APB 7.2.1 Operating states
Figure 7.1 shows the operational activity of the APB.
The state machine operates through the following states: IDLE: This is the default state of the APB. SETUP: When a transfer is required the bus moves into the SETUP state, where the appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock.
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ACCESS: The enable signal, PENABLE, is asserted in the ACCESS state. The address, writes, select, and write data signals must remain stable during the transition from the SETUP to ACCESS state. Exit fromthe ACCESS state is controlled by thePREADY signal fromthe slave: •If PREADY is held LOW by the slave then the peripheral bus remains in the ACCESS state. • If PREADY is driven HIGH by the slave then the ACCESS state is exited and the bus returns to theIDLE state if no more transfers are required. Alternatively, the bus moves directly to theSETUP state if another transfer follows. 7.2.2 Write transfer
Fig: 7.2 waveform for Write transfer
The write transfer starts with the address, write data, write signal and select signal all changing after the rising edge of the clock. The first clock cycle of the transfer is called the SETUP cycle. After the following clock edge the enable signal PENABLE is asserted and this 53
indicates that the ENABLE cycle is taking place. Theaddress, data and control signals all remain valid throughout theENABLE cycle. Thetransfer completes at the end of this cycle. The enable signal, PENABLE, will be disserted at the end of the transfer. The select signal will also go LOW, unless the transfer is to be immediately followed by another transfer to the same peripheral. In order to reduce power consumption the address signal and the write signal will not change after a transfer until the next access occurs. The protocol only requires a clean transition on the enable signal. It is possible that in the case of back to back transfers the select and write signals may glitch. 7.2.3 Read transfer
Fig: 7.3 wave form for Read transfer
The timing of the address, write, select and strobe signals are all the same as for the write transfer. I n the case of a read, the slave must provide the data during the ENABLE cycle. The data is sampled on the rising edge of clock at the end of the ENABLE cycle. 7.2.4 Protection unit support
54
To support complex system designs, it is often necessary for both the interconnect and other devices in the system to provide protection against illegal transactions. For the APB interface, this protection is provided by the PPROT [2:0] signals. The three levels of access protection are: 1. Normal or privileged, PPROT [0] •LOW indicates a normal access •HIGH indicates a privileged access. This is used by some masters to indicate their processing mode. A privileged processing mode typically has a greater level of access within a system. 2. Secure or non-secure, PPROT [1] •LOW indicates a secure access •HIGH indicates a non-secure access. This is used in systems where a greater degree of differentiation between Processing modes is required. Note: This bit is configured so that when it is HIGH then the transaction is considered nonsecure and when LOW, the transaction is considered as secure. 3. Data or Instruction, PPROT [2] •LOW indicates a data access •HIGH indicates an instruction access. This bit gives an indication if the transaction is a data or instruction access. Note: This indication is provided as a hint and is not accurate in all cases. For example, where a transaction contains a mix of instruction and data items. It is recommended that, by default, an access is marked as a data access unless it is specifically known to be an instruction access. 55
Table 7.1 Protection encoding
Note: The primary use of PPROT is as an identifier for Secure or Non-secure transactions. It is acceptable to use different interpretations of the PPROT [0] and PPROT [2] identifiers.
7.3 AXI4-Lite 7.3.1 Definition of AXI4-Lite This section defines the functionality and signal requirements of AXI4-Lite components. The key functionality of AXI4-Lite operation is: 1. All transactions are of burst length 1 2. All data accesses use the full width of the data bus. 3. AXI4_L ite supports adata bus width of 32-bit or 64-bit. 4. All accesses are Non-modifiable, Non-bufferable 5. Exclusive accesses are not supported. 56
Signal list: Shows the required signals on an AXI4-Lite interface.
Table 7.2 AXI4-Lite interface signals
7.3.2 Bus width
AXI4-Lite has a fixed data bus width and all transactions are the same width as the data bus. The data bus width must be, either 32-bits or 64-bits. ARM expects that: •The majority of components use a 32-bit interface •Only components requiring 64-bit atomic accesses use a 64-bit interface. A 64-bit component can be designed for access by 32-bit masters, but the implementation must ensure that the component sees all transactions as 64-bit transactions. 7.3.3Write strobes
The AXI4-Lite protocol supports write strobes. This means multi-sized registers can be implemented and also supports memory structures that require support for 8-bit and 16-bit accesses. 57
All master interfaces and interconnect components must provide correct write strobes. Any slave component can choose whether to use the write strobes. The options permitted are: •To make full use of the write strobes • To ignore the write strobes and treat all write accesses as being the full data bus width •To detect write strobe combinations that are not supported and provide an error response. A slave that provides memory access must fully support write strobes. Other slaves in the memory map might support a more limited write strobe option. 7.3.4 Conversion, protection, and detection
Connection of an AXI4-L ite slave to an AXI4 master requires some form of adaptation if it cannot be ensured that the master only issues transactions that meet the AXI4-Lite requirements. This section describes techniques that can be adopted in a system design to aid with the interoperability of components and the debugging of system design problems. These techniques are: 1. Conversion: This requires the conversion of all transactions to a format that is compatible
with the AXI4-Lite requirements. 2. Protection: This requires the detection of any non-compliant transaction. The non-compliant
transaction is discarded, and an error response is returned to the master that generated the transaction. 3. Detection: This requires observing any transaction that falls outside the AXI4-Lite
requirements • notifying the controlling software of the unexpected access •permitting the access to proceed at the hardware interface level.
58
7.3.5 Address structure
The AXI protocol is burst-based. The master begins each burst by driving control information and the address of the first byte in the transaction to the slave. As the burst progresses, the slave must calculate the addresses of subsequent transfers in the burst. A burst must not cross a 4KB address boundary. Note: This prevents a burst from crossing a boundary between two slaves. It also limits the
number of address increments that a slave must support. 1. Burst length
The burst length is specified by: ARLEN [7:0], for read transfers AWL EN [7:0], for write transfers.
In this specification, AxLEN indicates ARLEN or AWLEN. AXI3 supports burst lengths of 1 to 16 transfers, for all burst types. AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in AXI4 remains at 1 to 16 transfers. The burst length for AXI3 is defined as, Burst Length =AxL EN[3:0] +1 The burst length for AXI4 is defined as, Burst Length =AxL EN [7:0] +1, to accommodate the extended burst length of the INCR burst type in AXI4. AXI has the following rules governing the use of bursts: •For wrapping bursts, the burst length must be 2, 4, 8, or 16 •A burst must not cross a 4KB address boundary 59
• Early termination of bursts it not supported. No component can terminate a burst early. However, to reduce the number of data transfers in a write burst, the master can disable further writing by deserting all the write strobes. In this case, the master must complete the remaining transfers in the burst. In a read burst, the master can discard read data, but it must complete all transfers in the burst. Note: Discarding read data that is not required can result in lost data when accessing a read-
sensitive device such as a FIFO. When accessing such a device, a master must use a burst length that exactly matches the size of the required data transfer. In AXI4, transactions with INCR burst type and length greater than 16 can be converted to multiple smaller bursts, 2. Burst size
The maximum number of bytes to transfer in each data transfer, or beat, in a burst, is specified by: ARSIZE [2:0], for read transfers AWSIZE [2:0], for write transfers.
Table 7.3 Burst sizeencoding 60
3. Burst type
The AXI protocol defines three burst types: 1. FIXED: In a fixed burst, the address is the same for every transfer in theburst.
This burst type is used for repeated accesses to the same location such as when loading or emptying a FIFO. 2. INCR: In an incrementing burst, the address for each transfer in the burst is an increment of
the address for the previous transfer. The increment value depends on the size of the transfer. For example, the address for each transfer in a burst with a size of four bytes is the previous address plus four. This burst type is used for accesses to normal sequential memory. 3. WRAP: A wrapping burst is similar to an incrementing burst, except that the address wraps
around to a lower address if an upper address limit is reached. The following restrictions apply to wrapping bursts: •The start address must be aligned to the size of each transfer •The length of the burst must be 2, 4, 8, or 16 transfers. The burst type is specified by: •ARBURST [1:0], for read transfers. •AWBURST [1:0], for write transfers. In this specification, Ax BURST indicates ARBURST or AWBURST
61
Table 7.4Burst type encoding
62
8.VERILOG CODING Apb Br i dge `t i mescal e 1ns / 1ps modul e apb_br i dge_cha( i nput Acl k, i nput Pcl k, i nput Rst , i nput Awval i d, i nput [ 31: 0] Awaddr , i nput Wval i d, i nput [ 31: 0] Wdat a, i nput [ 3: 0] Wst r b, i nput Br eady, i nput Ar val i d, i nput [ 31: 0] Ar addr , i nput Rr eady, i nput Pr eady, i nput [ 31: 0] Pr dat a, i nput Psl ver r , out put r eg Awr eady, out put r eg Wr eady, out put r eg Bval i d, out put r eg Br esp, out put r eg Ar r eady, out put r eg Rval i d, out put r eg[ 31: 0] Rdat a, out put r eg Rr esp, out put r eg [ 31: 0] Paddr , out put r eg Psel , out put r eg Penabl e, 63
out put r eg Pwr i t e, out put r eg [ 31: 0] Pwdat a, out put reg [ 3: 0]
/ / / * * * * * * * ** * * * * * * ** * * * * * * ** * * * * * * *Si gnal s I nt er nal * * * * * * * ** * * * * * * ** * * * * * * ** * * * * * *
Of
Pst r b) ;
t he
/ / / I NTERNAL SI GNALS / / / I NTERCONNCTES SI GNALS
r eg [1: 0] awval i d_s, wval i d_s, ar val i d_s; r eg bval i d_s; r eg awval i d_ i ni t i al , ar val i d_ i ni t i al ; r eg [ 31: 0] awaddr _s, ar addr _s; r eg pr eady_s, psl ver r _s; r eg r r eady_s; r eg [ 31: 0] pr dat a_s, wdat a_s; r eg a_wr _s, a_r d_s, p_wr _s, p_r d_s; wi r e [ 31: 0] pwdat a_s_ w, r dat a_s_ w; r eg r d_addr , wr _addr ; r eg [ 31: 0] paddr _s; wi r e [ 31: 0] paddr _s2; r eg bval i d1, bval i d2; r eg r r eady_s1, r r eady_s2, r r eady_s3;
- - - - Addr es s l ogi c f or t he i nt er f ac e - - - - - Addr es s s Sel ec t i on - - - - - Assgi ni ng t he si gnal AXI Si gnal t o a Si gnal - - - - - Lat er t he si gnal i s connct ed t o t he FI FO I nput Si gnal ---------------------------------------------------------------------------------*/
64
al ways@( Ar val i d, ar addr _s, awaddr _s, Awval i d) begi n i f ( Ar val i d) paddr _ s<= ar addr _s; el s e paddr _s <= awaddr _ s; end / * - - - - - - - - - - - - - - - - Compl et ed The Addr ess L ogi c Si gnal s- - - - - - - - - - - - - - - - - - - - - - - -----------*/ A r ead and wr i t e r equest si gnal
ar e asser t ed on same t i me t hen gi ve a pr i or i t y
- - - f or t he r ead si gnal t han wr i t e si gnal . al ways@( Awval i d, Ar val i d) begi n i f ( ( Awval i d == 1' b1) &( Ar val i d==1' b1) ) begi n awval i d_i ni t i al = 1' b0; ar val i d_ i ni t i al = 1' b1; end el se i f ( ( Awval i d == 1' b1) &( Ar val i d==1' b0) ) begi n awval i d_i ni t i al = 1' b1; ar val i d_ i ni t i al = 1' b0; end el se i f ( ( Awval i d == 1' b0) &( Ar val i d==1' b1) ) begi n awval i d_i ni t i al = 1' b0; ar val i d_ i ni t i al = 1' b1; end el s e begi n 65
awval i d_i ni t i al = 1' b0; ar val i d_ i ni t i al = 1' b0; end end / * - - - - - - - - - - - - - - - - - - - - - - Pr i or i t y Of t he si gnal s i s compl et ed- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Wr i t e Si gnal s For AW si gnal s- - - - - - - - - - - - - - - - - - - - - - Awval i d Shoul d be Hi gh For The Addr ess Tr ansf er - - - Awr eady Shoul d get Hi gh For t he Pr eady i s Hi gh si gnal - - - I f Pr eady i s l ow and Awval i d i s hi gn si gnal t hen t he si gnal s - - - i nci dact e t hat r ecevi ce.
t he AXI ( Mast er )
i s r eady but
Apb( Sl ave)
i s not
r eady to
- - - I f Pr eady i s Hi gh and Awval i d i s Low si gnal s t hen t he si gnal s t hat - - - i nci dacet t hat t he AXI ( Mast er ) i s not r eady but ABP( Sl vae) i s r eady. - - - I f Pr eady i s hi gh t han Awr eady si gnal wi l l be Hi gh. - - - When Pr eady and Awval i d i s Bot h ar e Hi gh, We make one enabl e si gnal wi l l be HI gh - - - when both si gnal s wi l l be hi gh. al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n awval i d_s <= 2' b0; Awr eady <= 1' b0; awaddr _s <= 32' h0; end el se i f ( ( awval i d_i ni t i al ==1' b1) &( pr eady_s==1' b1) ) begi n awval i d_s <= 2' b11; awaddr _ s <= Awaddr ; Awr eady <= 1' b1; end 66
t hat
el se i f ( ( awval i d_i ni t i al ==1' b0) &( pr eady_s==1' b1) ) begi n awval i d_s <= 2' b01; Awr eady <= 1' b1; //
awaddr _ s <= 32' h0; end
el se i f ( ( awval i d_i ni t i al ==1' b1) &( pr eady_s==1' b0) ) begi n awaddr _ s <= Awaddr ; awval i d_s <= 2' b10; Awr eady <= 1' b0; end el s e begi n //
awaddr _s <= 32' h0; awval i d_s <= 2' b0; Awr eady <= 1' b0; end
end //-------------------------------------------------------------------- - - I n t hi s pr ocess Wdata t r anf t er Takes Pl ace Her e - - - Wdat a si gnal & Wr eady si gnal s Pr eady. - - - Wdat a i s t ake f r om when Wval i d i s Hi gh. - - - Wr eady i s hi gh i f Pr eady Si gnal i s Hi gh i f not i t wi l l be Low. - - - I have t ake One Enabl e si gnal . The enabl e Si gnal wi l l be Hi gh both - - - Si gnal ( Wval i d, Pr eady, AWenabl e) shoul d be hi gh. - - - Wr eady wi l l be Hi gh i f Pr eady i s Hi gh. - - - Wval i d i s hi gh t hen onl y my Data wi l l Taken f r om i nput ---------------------------------------------------------------------al ways@( posedge Acl k) 67
begi n i f ( ~( Rs t ) ) begi n wval i d_s <= 2' b0; wdat a_s <= 32' h0; Wr eady <= 1' b0; Pst r b <= 4' h0; end el se i f ( awval i d_s==2' b11) begi n i f ( ( Wval i d==1' b1) &( pr eady_s ==1' b1) ) begi n wdat a_ s <= Wdat a; wval i d_s <= 2' b11; Wr eady <= 1' b1; Pst r b <= Wst r b; end el se i f ( ( Wval i d==1' b0) &( pr eady_s==1' b1) ) begi n wval i d_s <=2' b01; Wr eady <= 1' b1; Pst r b <= 4' h0; end el se i f ( ( Wval i d==1' b1) &( pr eady_s==1' b0) ) begi n wdat a_ s <= Wdat a; wval i d_s <= 2' b10; Wr eady <= 1' b0; Pst r b <= Wst r b; end 68
el s e begi n wval i d_s <= 2' b00; Wr eady <= 1' b0; Pst r b <= 4' h0; end end el se i f ( ( awval i d_s==2' b01) | ( awval i d_s==2' b10) | ( awval i d_s==2' b0) ) begi n wdat a_ s <= 32' h0; wval i d_s <= 2' b0; Wr eady <=0; Pst r b <= 0; end end ** ** ** ** ** ** ** ** ** ** ** Response si de********************* *******
Si gnal s
on
t he
AXI
- - - Bval i d, Ps l ver r - - - Bval i d i s Resopse si gnal Of Axi Data . - - - I t wi l l r espond That when sl ave have r ecevi ced the data f r om Mast er
reg p_rd_ss; / / / I have made Regt er s Logi c when we ar e Changi ng f r om One cl ock Domai n t o Ot her Cl ock Domai n
al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n Bval i d<= 1' b0; bval i d1<=1' b0; 69
bval i d2<= 1' b0; end el s e i f ( p_ r d_ s s) begi n bval i d1 <=bval i d_s ; bval i d2 <=bval i d1; Bval i d <= bval i d2; end el s e begi n bval i d1<=bval i d_s ; bval i d2 <=bval i d1; Bval i d <= bval i d2; end end al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n bval i d_s<= 1' b0; end el se i f ( ( awval i d_s==2' b11) &( psl ver r _s==1' b0) ) begi n i f ( ( wval i d_s==2' b11) &( pr eady_s==1' b1) ) begi n bval i d_s<= 1' b1; end el s e begi n bval i d_s<= 1' b0; 70
end end el s e begi n bval i d_s<= 1' b0; end end - - - Br esp f r om t o AXI si gnal s f r om APB . - - - I Nt i al l y We have Bval i d si gnal t hen Axi wi l l Send Br eady si gnal t o Abp - - - I f Br eady i s HI gh t han Br esp wi l l be Hi gh. al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n Br esp <= 1' b0; end el s e i f ( bval i d_ s) begi n i f ( Br eady) begi n Br esp <= 1' b1; end el s e begi n Br esp <= 1' b0; end end el s e begi n Br esp <= 1' b0; 71
end end ***** ***** ***** ***** ***** ***** ********************
- - - Ar val i d Shoul d be Hi gh
Read
Si gnal s
on
t he
AXI
si de
For The Addr ess Tr ansf er
- - - Ar r eady Shoul d get Hi gh For t he Pr eady i s Hi gh si gnal - - - I f Pr eady i s l ow and Ar val i d i s hi gn si gnal t hen t he si gnal s - - - i nci dact e t hat r ecevi ce.
t he AXI ( Mast er )
i s r eady but
Apb( Sl ave)
i s not
r eady to
- - - I f Pr eady i s Hi gh and Ar val i d i s Low si gnal s t hen t he si gnal s t hat - - - i nci dacet t hat t he AXI ( Mast er ) i s not r eady but ABP( Sl vae) i s r eady. - - - I f Pr eady i s hi gh t han Ar r eady si gnal wi l l be Hi gh. - - - When Pr eady and Ar val i d i s Bot h ar e Hi gh, We make one enabl e si gnal wi l l be HI gh - - - when both si gnal s wi l l be hi gh. ---------------------------------------------------------------------al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n Ar r eady <=1' b0; ar val i d_s <= 2' b00; ar addr _s <= 32' h0; end el se i f ( ( ar val i d_i ni t i al ==1' b1) &( pr eady_s==1' b1) ) begi n ar val i d_s <= 2' b11; ar addr _s
<= Ar addr ;
Ar r eady
<= 1' b1;
end el se i f ( ( ar val i d_i ni t i al ==1' b1) &( pr eady_s==1' b0) ) 72
t hat
begi n ar val i d_s <= 2' b10; ar addr _s
<= Ar addr ; Ar r eady
<= 1' b0;
end el se i f ( ( ar val i d_i ni t i al ==1' b0) &( pr eady_s==1' b1) ) begi n ar val i d_s <= 2' b01; ar addr _s <= 32' h0; Ar r eady
<= 1' b1;
end el s e begi n ar val i d_s <= 2' b00; ar addr _s Ar r eady
<= 32' h0; <= 1' b0;
end
end - - Read Dat a Si gnal . - - - I n The pr ocess Sl ave wi l l be sendi ng t he Dat a f or par t i cul ar Addr esss - - - whi ch i s send by AXI ( Mast er ) . - - - I n t hi s pr ocess we wi l l be wr i t i ng Onl y the enabl e si gnal s. al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n Rval i d <= 1' b0; r r eady_s<=1' b0; end 73
el se i f ( ar val i d_s == 2' b11) begi n i f ( ( pr eady_s ==1' b1) &( Rr eady==1' b1) ) begi n Rval i d <= 1' b1; r r eady_s <= 1' b1; end el se i f ( ( pr eady_s ==1' b0) &( Rr eady==1' b1) ) begi n Rval i d <= 1' b0; r r eady_s <= 1' b1; end el se i f ( ( pr eady_s ==1' b1) &( Rr eady==1' b0) ) begi n Rval i d <= 1' b1; r r eady_s <= 1' b0; end el s e begi n Rval i d <= 1' b0; r r eady_s <= 1' b0; end end el s e begi n Rval i d <= 1' b0; r r eady_s <= 1' b0;
end end 74
- - - Read Resopse Si ngal al ways@( posedge Acl k ) begi n i f ( ~Rst ) begi n Rr esp <= 1' b0; end el se i f ( ( psl ver r _s==1' b0) &( r r eady_s1==1' b1) ) begi n Rr esp <= 1' b1; end el s e begi n Rr esp <= 1' b0; end end - - - I t i nt er nal Si gna f or t he Enabl i ng - - - a_r d_s : I nci dat es t hat AXI READ SI GNAL FOR THE FI FO - - - LOGI C THAT WHEN FI FO SHOULD READ THE DATA FROM FI FO OUT . al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n a_r d_s <= 1' b0; end el se i f ( ( pr eady_s==1' b1) &( ar val i d_s==2' b11) ) begi n i f ( ( r r eady_ s) ) begi n a_r d_s <= 1' b1; 75
end el s e begi n a_r d_s <= 1' b0; end end end - - - I NTERNAL SI GNAL PURPOSE - - - PREADY SI GNAL : I T REPRESENT THAT SLAVE I S READY NOT TO RECEVI CE THE DATA SI GNAL - - - ANY CONTROL SI GNALS al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n pr eady_s <= 1' b0; end el se i f ( Pr eady) begi n pr eady_s <= 1' b1; end el s e begi n pr eady_s <= 1' b0; end end - - - PLSVERR SI GNAL - - - THI S I S SHOWS ERROR I NCI DATI ON - - - I F THERE I S ERROR I T I S HI GH I F NOT LOW al ways@( posedge Pcl k) 76
begi n i f ( ~Rst ) begi n psl ver r _s <= 1' b0; end el s e begi n i f ( Psl ver r ) begi n psl ver r _s <= 1' b1; end el s e begi n psl ver r _s <= 1' b0; end end end - - - I N THI S PRO0ESS - - - WHEN SHOULD READ DATA SHOULD BE TAKEN I N al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n pr dat a_s <= 32' h0; end el se i f ( ( arval i d_i ni t i al ==1' b1) &( Pr eady==1' b1) &( Rr eady==1' b1) ) begi n pr dat a_s <= Pr dat a; end el se i f ( ( arval i d_i ni t i al ==1' b1) &( Pr eady==1' b0) &( Rr eady==1' b1) ) 77
begi n pr dat a_s <= Pr dat a; end el se i f ( ( arval i d_i ni t i al ==1' b0) &( Pr eady==1' b1) &( Rr eady==1' b0) ) begi n pr dat a_s <= 32' h0; end el s e begi n pr dat a_s <= 32' h0; end end - - - P_WR_S: I NCI DATES THAT ABP SI DE WRI TE SI GNAL FOR THE READ FI FO al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n p_wr _s <= 1' b0; end el se i f ( ( r r eady_s==1' b1) &( pr eady_s==1' b1) ) begi n p_wr _s <= 1' b1; end el s e begi n p_wr _s <= 1' b0; end end - - - PENABLE SI GNAL r eg penabl e1, penabl e2, penabl e3, penabl e4; 78
al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n Penabl e <= 1' b0; penabl e1<= 1' b0; penabl e2<= 1' b0; penabl e3<= 1' b0; penabl e4<= 1' b0; end el se i f ( ( Wr eady) ) begi n penabl e1<= 1' b1; penabl e2 <=penabl e1; penabl e3<= penabl e2; penabl e4<= penabl e3; Penabl e <= penabl e4; end el s e begi n penabl e1<= 1' b0; penabl e2<= penabl e1; penabl e3<= penabl e2; penabl e4<= penabl e3; Penabl e <= penabl e4;
end end - - - PWDATA : I T I S SOUTPUT SI GNAL 79
- - - TAKI NG DATA FROM WRI TE FI FO al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n Pwdat a<= 32' h0; end el se i f ( ( Penabl e==1' b1) | ( pr eady_s==1' b1) ) begi n Pwdat a <= pwdat a_ s_ w; end el s e begi n Pwdat a <= 32' h0; end
end - - - RDATA SI GNAL ON AXI SI DE - - - THI S SI GNAL TAKE DATA FROM ABP SLAVE GI VE I T TO AXI al ways@( posedge Acl k) begi n i f ( ~Rst ) Rdat a <= 32' h0; el s e i f ( a _r d_ s) Rdat a <= r dat a_s_ w; el s e Rdat a <= 32' h0; end
80
/ * * * * * * * ** * * * * * * * ** * * * * * * ** * FI FO Logi c*********************************** **********/
/ / ENABLE SI GNAL FOR FI FO SI GNAL
r eg wr eady_s;
al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n wr eady_s <= 1' b0; end el se i f ( Wr eady) begi n wr eady_s <= 1' b1; end el s e begi n wr eady_s <= 1' b0; end end
r eg p_r d_en;
al ways@( posedge Acl k) begi n i f ( ~Rst ) begi n 81
I nt er f ac i ng
a_wr _s <=1' b0; p_r d_en <=1' b0; end el se i f ( ( psl ver r _s==1' b0) &( Wr eady==1' b1) ) begi n p_r d_en <= 1' b1; a_wr _s <= 1' b1; end el s e begi n a_wr _s <=1' b0; p_r d_en <=1' b0; end end r eg r d_a; al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n p_r d_s <= 1' b0; end el se i f ( ( p_r d_en==1' b1) | ( r d_a==1' b1) ) begi n p_r d_s <= 1' b1; end el s e p_r d_s <= 1' b0;
end
82
r eg p_r d_ss1, p_r d_ss2;
al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n p_r d_ss <= 1' b0; p_r d_ss1 <= 1' b0; p_r d_ss2 <= 1' b0;
end
el s e begi n p_r d_ss <= p_r d_s; p_r d_ss 1 <= p_r d_ss ; p_r d_ss 2 <=p_r d_ss 1; end end / / - - - WRI TE FI FO I NTERFACI NG MODULE
f i f o_code wr _f i f o( . Dat a_i n( wdat a_s) , . RCl k( Pc l k) , . ReadEn_i n( p_r d_ss2), . Cl ear _ i n( Rs t ) , . WCl k( Acl k) , . Wr i t eEn_i n( a_wr _s) , . Dat a_out ( pwdat a_s_ w) //
empt y, 83
/ / f ul ul l );
/ / - - - READ EAD FI FO I NTERFAC TERFACII NG MODULE
f i f o_ c od ode r d_ f i f o( . Dat a_ i n( pr d at at a_ s ) , . RCl k( Acl k) , . ReadEn_i n( a_r d_s) , . Cl ear _ i n( Rs t ) , . WCl k(Pcl k), . Wr i t eEn_i n( p_wr _wr _s) , . Dat a_ou a_out ( r dat a_s_w) a_s_w) / / empt y, / / f ul ul l );
/ / - - - - - - - - - - - - - - Pwr i t e Sognal For t he r eg pw pwr i t e1, pwr i t e2;
al ways@( posedge posedge Pcl k) begi egi n i f ( ~Rst ) begi n Pwr i t e <= 1' b0; b0; pwr i t e1< e1<= 1' b0; b0; pwr i t e2< e2<= 1' b0; b0; end el se i f ( ( wr eady_s) ) / / | ( Wr eady==1' b1) ) begi n pwr i t e1< e1<= 1' b1; b1; 84
pwr i t e2 <=pwr i t e1; e1; Pwr i t e <= pwr i t e2; e2; end el s e begi n pwr i t e1< e1<= 1' b0; b0; pwr i t e2< e2<= pwr i t e1; e1; Pwr i t e <= pwr i t e2; e2; end end / *The Addr ddr ess f i f o have ave t ochan ochange ge*/ */ r eg r d_en d_en;
al ways@( posedge posedge Acl k) begi egi n i f ( ~Rst ) begi n wr _ addr addr = 1' b0; b0; r d_en =1' b0; b0; end el s e i f ( ( ( Awr ead eady==1' b1) b1) | ( Ar r ead eady==1' b1) b1) ) &( psl ver ver r _s ==1' b0) &( pr ead eady_s== y_s==1' b1) &( ( awv al i d_s== _s==2' b11) | ( arval arval i d_s== _s==2' b11) ) ) begi n wr _ addr addr = 1' b1; b1; r d_en =1' b1; b1; end el s e begi n r d_en =1' b0; b0; 85
wr _ addr addr = 1' b0; b0; end end
al ways@( posedge posedge Pcl k) begi egi n i f ( ~Rst ) r d_addr d_addr <= 1' b0; b0; el se i f ( ( r d_en= _en==1' b1) ) r d_addr d_addr <= 1' b1; b1; el s e r d_addr d_addr <= 1' b0; b0; end
al ways@( posedge posedge Pcl k) begi egi n i f ( ~Rst ) r d_a <= <= 1' b0; b0; el se i f ( ( r d_add _addr ==1' b1) ) r d_a <= <= 1' b1; b1; el s e r d_a <= <= 1' b0; end
f i f o_cod _code addr ( . Dat a_i n( paddr _s) , . RCl k( Pc l k) , . ReadEn_i n( r d_add _addr ) , . Cl ear _ i n( Rs t ) , . WCl k( Acl k) , . Wr i t eEn_i n( wr _add _addr ) , 86
. Dat a_out ( paddr _s2) );
- - - SLECTI ON OF SLAVE al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n Psel <= 1' b0; end el se i f ( ( r d_addr ==1' b1) &( psl ver r _s==1' b0) ) begi n i f ( pr eady_s==1' b1) begi n Psel <= 1' b1; end el s e begi n Psel <= 1' b0; end end end
/ / - - - ADDRESS ON ABP SI DE
al ways@( posedge Pcl k) begi n i f ( ~Rst ) Paddr <= 32' h0; el s e 87
Paddr <= paddr _s2; end / / ENABLE FOR READ READY SI GNAL
al ways@( posedge Acl k) begi n i f ( ~Rst ) r r eady_s1 <=1' b0; el s e r r eady_s 1 <=r r eady_ s3; end
al ways@( posedge Acl k) begi n i f ( ~Rst ) r r eady_s 2 <= 1' b0; el se begi n r r eady_s 2 <= r r eady_ s; r r eady_s 3 <= r r eady_ s2; end end //------------------------------------------------------------------------------endmodul e
/ / - - - - - - - - - - - - - - Compl et ed Code For t he ------// 88
Apb Br i dge- - - - - - - - - - - - - - - - - - - - - - - - - - -
`t i mescal e 1ns / 1ps
//----------------------------------------------------------------------------modul e apb_uar t _t op (
/ / APB I nt er f ace i nput PCLK, i nput PRESETn, i nput PSEL, i nput PENABLE, i nput PWRI TE, i nput [ 31: 0] PWDATA, i nput [ 31: 0] PADDR, out put [ 31: 0] PRDATA, / / / UART out put t x, i nput r x ); wi r e [ 7: 0] uar t _r x_dat a, uar t _t x_dat a; wi r e uar t _r d, uar t _wr ; wi r e t xr dy, r xr dy;
//---------------------------------------------------------------------------/ / I nput / Out put Decl ar at i on //----------------------------------------------------------------------------
89
/ / I nst ant i at i on of UART Cont r ol l er Regi st er modul e
APB I nt er f ace apb_i nt er f ace APB_I F( . PCLK( PCLK) , . PRESETn( PRESETn) , . PSEL( PSEL) , . PENABLE( PENABLE) , . PWRI TE( PWRI TE) , . PWDATA( PWDATA) , . PADDR( PADDR) , . PRDATA( PRDATA) , . uar t _r x_dat a( uar t _r x_dat a) , . uar t _t x_dat a( uar t _t x_dat a) , . r xr dy( r xr dy) , . t xr dy( t xr dy) , . uar t _ r d( uar t _ r d ) , . uar t _wr ( uar t _wr ) ) ; uar t UART_TOP( . cl k( PCLK) , . r st ( PRESETn) , . wr ( uar t _wr ) , . r d( uar t _ r d) , . r x( r x) , . t x( t x) , . di n( uar t _ t x_ dat a) , . r dat a_out ( uar t _r x_dat a) , . t xr dy( t xr dy) , . r xr dy( r xr dy) );
90
endmodul e / / <>
FI FO MODULE modul e f i f o_code #( par amet er
DATA_WI DTH
= 32,
ADDRESS_WI DTH = 7) / / FI FO_ DEPTH
= ( 1 << ADDRESS_WI DTH) )
/ / Readi ng por t ( out put r eg
[ 31: 0]
Data_out ,
out put r eg
Empt y_out ,
i nput wi r e
ReadEn_i n,
i nput wi r e
RCl k,
/ / Wr i t i ng por t . i nput wi r e
[ 31: 0]
Data_i n,
out put r eg
Ful l _out ,
i nput wi r e
Wr i t eEn_i n,
i nput wi r e
WCl k,
i nput wi r e
Cl ear _i n) ;
/ / / / / I nt er nal connect i ons & var i abl es / / / / / / r eg
[ 31: 0]
wi r e
[ 7: 0]
Mem [ 0: 255] ; pNext Wor dToWr i t e, pNext Wor dToRead;
wi r e
Equal Addr esses;
wi r e Next ReadAddr ess En;
Next Wr i t eAddr essEn,
wi r e
Set _Stat us, Rst _Stat us;
r eg
St at us;
wi r e
Preset Ful l , Pr eset Empt y;
91
/ / / / / / / / / / / / / / Code/ / / / / / / / / / / / / / / / / Dat a por t s l ogi c: / / ( Uses a dual - por t RAM) . / / ' Dat a_ out ' l ogi c : al ways @ ( posedge RCl k, negedge Cl ear _i n) begi n i f ( ~Cl ear _ i n) Dat a_out <= 32' h0; el se i f ( ReadEn_i n && ! Empt y_out ) Dat a_ out <= Mem[ pNext Wor dToRead] ; end r eg pt ; / / ' Dat a_ i n' l ogi c: al ways @ ( posedge WCl k, negedge Cl ear _ i n) begi n i f ( ~Cl ear _ i n) pt <= 1' b0; el se i f ( Wr i t eEn_i n & ! Ful l _out ) Mem[ pNext Wor dToWr i t e] <= Dat a_ i n; end / / Fi f o addr esses suppor t l ogi c: / / ' Next Addr esses' enabl e l ogi c: assi gn Next Wr i t eAddr essEn = Wr i t eEn_i n & ~Ful l _out ; ass i gn Next ReadAddr ess En
= ReadEn_i n
/ / Addr eses ( Gr ay count er s) l ogi c: Gr ayCount er Gr ayCount er _pWr ( . Gr ayCount _out ( pNext Wor dToWr i t e) ,
. Enabl e_i n( Next Wr i t eAddr essEn) , 92
& ~Empt y_ out ;
. Cl ear _ i n( Cl ear _ i n) ,
. Cl k( WCl k) );
Gr ayCount er Gr ayCount er _pRd ( . Gr ayCount _ out ( pNext Wor dToRead) , . Enabl e_i n( Next ReadAddr essEn) , . Cl ear _ i n( Cl ear _ i n) , . Cl k( RCl k) );
/ / ' Equal Addr esses' l ogi c: ass i gn Equal Addr ess es = ( pNext Wor dToWr i t e[ ADDRESS_WI DTH: 0] pNext Wor dToRead[ ADDRESS_WI DTH: 0] ) ?1' b1: 1' b0;
==
/ / ' Quadr ant s el ec t or s ' l ogi c : ass i gn Set _St at us = pNext Wor dToRead[ ADDRESS_WI DTH] ) &
( pNext Wor dToWr i t e[ ADDRESS_WI DTH- 1]
~^
( pNext Wor dToWr i t e[ ADDRESS_WI DTH] pNext Wor dToRead[ ADDRESS_WI DTH- 1] ) ?1' b1: 1' b0;
^
ass i gn Rst _St at us = pNext Wor dToRead[ ADDRESS_WI DTH] ) &
^
( ( pNext Wor dToWr i t e[ ADDRESS_WI DTH- 1]
( pNext Wor dToWr i t e[ ADDRESS_WI DTH] pNext Wor dToRead[ ADDRESS_WI DTH- 1] ) ) ?1' b1: 1' b0;
~^
/ / ' St a t us ' l at ch l ogi c: al ways @ ( Set _St at us, Cl ear & Pr eset .
Rst _Stat us,
begi n 93
Cl ear _i n)
/ / D Lat ch w/
Asynchr onous
i f ( Rs t _ St at us | ! Cl ear _ i n) St at us = 0;
/ / Goi ng ' Empt y' .
el s e i f ( Set _ St at us ) St at us = 1;
/ / Goi ng ' Ful l ' .
end / / ' Ful l _ out ' l ogi c f or t he wr i t i ng por t : assi gn Pr eset Ful l = St at us & Equal Addr esses;
/ / ' Ful l ' Fi f o.
al ways @ ( posedge WCl k, posedge Pr eset Ful l ) / / D Fl i p- Fl op w/ Asynchr onous Pr eset . begi n //
i f ( ~Cl ear _ i n)
//
Ful l _out <= 1' b0;
//
el se i f ( Pr es et Ful l ) Ful l _out <= 1; el s e Ful l _out <= 0; end / / ' Empt y_out ' l ogi c f or t he r eadi ng por t : assi gn Pr eset Empt y = ~St at us & Equal Addr esses;
al ways @ ( posedge Asynchr onous Pr eset .
RCl k,
posedge
begi n i f ( Preset Empt y) Empt y_ out <= 1; el s e Empt y_ out <= 0; end endmodul e 94
/ / ' Empt y' Fi f o.
Preset Empt y)
//D
Fl i p- Fl op
w/
GRAY COUNTER MODULE modul e Gr ayCount er #( par amet er ( out put r eg out put .
COUNTER_ WI DTH =8)
[ COUNTER_WI DTH- 1: 0]
Gr ayCount _out ,
/ / ' Gr ay'
i nput wi r e
Enabl e_i n,
/ / Count enabl e.
i nput wi r e
Cl ear _i n,
/ / Count r eset .
i nput wi r e
Cl k);
code count
/ / / / / / / / / I nt er nal connect i ons & var i abl es / / / / / / / r eg
[ COUNTER_WI DTH- 1: 0]
Bi nar yCount ;
/ / / / / / / / / Code/ / / / / / / / / / / / / / / / / / / / / / /
al ways @ ( posedge Cl k, negedge Cl ear _i n) begi n i f ( ~Cl ear _i n) begi n Bi nar yCount
<= {COUNTER_WI DTH{1' b 0}} + 1;
/ / Gr ay count begi ns
@ ' 1' wi t h Gr ayCount _out
<=
{COUNTER_ WI DTH{1' b
0}};
//
f i r st
' Enabl e_ i n' . end el se i f ( Enabl e_i n) begi n Bi nar yCount
<= Bi nar yCount + 1;
Gr ayCount _out <= {Bi nar yCount [ COUNTER_ WI DTH- 1] , Bi nar yCount [ COUNTER_WI DTH- 2: 0] Bi nar yCount [ COUNTER_WI DTH- 1: 1] }; end end 95
^
endmodul e
UART modul e uar t ( i nput cl k, r st , wr , r d, r x, out put t x, i nput [ 7: 0] di n, out put
[ 7: 0] r dat a_out ,
out put
t xr dy, r xr dy) ;
wi r e par i t yer r ; wi r e r xrdy1, t xrdy1;
assi gn r xrdy=( r st ==1' b1) ?( r xrdy1) : 1' bZ; assi gn t xrdy=( r st ==1' b1) ?( t xrdy1) : 1' bZ; uar t _ t r ans mi t t er u4( . c l k( c l k) , .rst_n(rst), . wr ( wr ) , . dat a( di n) , . t xr dy( t xr dy1) , .tx(tx)); uar t _ r ec ei ver u5(
. c l k( c l k) , .rst_n(rst), . r d( r d) , .rx(rx), . par i t yer r ( par i t y er r ) , . r xr dy( r xr dy1) , . det _ r x( det _ r x ) , . r d_ cl k( r d_ cl k) , . f l ag( f l ag) , . dat a( r dat a_out ) ) ;
endmodul e 96
UART_ RECEI VER modul e uar t _r ecei ver ( i nput cl k, r st _n, r d, r x, out put r eg
par i t yer r , out put r eg r xr dy, out put r eg det _r x, out put r eg
r d_cl k,
out put r eg f l ag, out put r eg [ 7: 0] dat a) ;
i nt eger count , count r x; / / r eg [ 7: 0] t emp_r hr ; r eg
r baud_cl k;
r eg [ 10: 0] r sr ; r eg [ 7: 0] r hr ;
/ / Thi s modul e i s t o det ec t t he r ec ei vi ng bi t i . e. , s t a r t bi t al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) begi n det _r x <=1' b0;
/ / On r eset , we assume t hat , det _r x
i s not acti vat ed. count r x <=1' b0; end el se i f ( r x ==1' b0) begi n det _r x <=1' b1; det _r x cont r ol si gnal i s enabl ed. 97
///
If
a st ar t
bi t
i s r ecei ved,
count r x <= count r x+1; end
el se i f ( f l ag ==1' b1)
/ / / and ( count r x < 100) )
det _r x <=1' b0; / / / I f st ar t bi t f i r s t bi t of RSR i . e. , al l t he bi t s ar e r ec ei ved i nt o r ec ei ver
occupi es
t he
end
/ / / Thi s modul e i s t o keep t r ack of t he count , whi ch wi l l be hel pf ul l i n gener at i ng baud cl ocks al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) count <= 0; el se i f ( ( det _r x ==1' b1) &&( count == 9) ) count <= 0; el se i f ( det _r x ==1' b1) count <= count +1; el s e count <= 0; end
/ / / Thi s modul e i s f or gener at i on of baud cl k al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) r baud_cl k <=1' b0; el se i f ( count == 1) r baud_cl k <=1' b1; el s e 98
r baud_cl k <=1' b0;
end
/ / Thi s modul e i s f or r ecei vi ng dat a f r om t r ansmi t t er l i ne t o r ecei ver i . e, t o RSR al ways@( posedge r baud_cl k ) begi n i f ( r st _n ==1' b0) r sr <=11' b11111111111; el s e begi n r sr[ 9: 0] <= r sr [ 10: 1] ;
/ / Recei vi ng bi t s bi t by bi t
r sr [ 10] <= r x;
i f ( f l ag ==1' b1) f i r s t pos i t i on, t hen, i t i s r es et
/ / I f s t a r t bi t r eac hes t he
r sr <= 11' b11111111111;
end
end
/ / Thi s modul e i s t o assi gn val ue t o the f l ag al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) f l ag <=1' b0; el s e 99
begi n i f ( r sr [ 0] ==1' b0) f l ag <=1' b1; el se i f ( det _r x ==1' b1) f l ag <=1' b0; end end
/ / / Thi s modul e i s t o recei ve data f r om RSR t o RHR al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) r hr <= 8' b11111111; el s e r hr <= r sr [ 8: 1] ;
end
al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) r d_cl k <=1' b0; el s e begi n i f ( f l ag ==1' b1) r d_cl k <=1' b1; el s e r d_cl k <=1' b0; 100
end end
/ / Thi s modul e i s t o shi f t dat a f r om RHR t o Dat al i ne wi t h t he hel p of r ead r d si gnal al ways@( posedge f l ag) begi n i f ( r st _n ==1' b0) dat a <= 8' b0; el s e dat a <= r hr ; end
/ / / Thi s modul e i s t o moni t or, whet her Recei ver i s r eady or not al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) r xr dy <=1' b0; el se
i f ( f l ag ==1' b1) r xr dy <=1' b1;
el se i f ( r d ==1' b1) r xr dy <=1' b0; end
/ / / Thi s modul e i s f or par i t y er r or al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) pari t yer r <=1' b0; 101
el se i f ( r d ==1' b1) pari t yer r <=1' b0; el se i f ( r sr[ 0] ==1' b0) begi n i f ( ( ( r s r [ 8] ^ r s r [ 7] r sr [ 3] ^ r sr [ 2] ^ r sr [ 1] ) &( r sr [ 9] ) ) ==1' b1)
^ r s r [ 6]
pari t yer r <=1' b0; el s e pari t yer r <= 1' b1; end
end
endmodul e
102
^ r s r [ 5]
^ r s r [ 4]
^
UART_ TRANSMI TTER modul e uar t _t r ansmi t t er ( i nput cl k, r st _n, wr , i nput [ 7: 0] dat a, out put r eg t xr dy, out put r eg t x);
i nt eger
count ;
r eg[ 7: 0] t br ; r eg [ 10: 0] t sr; r eg baud_cl k; reg
tx_sts;
/ *Thi s modul e i s t o keep t x_stat us t o be 1 or not - i . e, busy or not
t o moni t or t x i s
- - t x_st s i ndi cat es t r ansmi t t er st at us, t x_st s = 1 means t r ansmi t t er i s busy; t x_st s = 0 means t r ansmi t t er i s f r ee*/ al ways@( posedge cl k) begi n i f ( r st _n == 1' b0) t x_st s <= 1' b0;
/ / Tr ansmi t t er i s f r ee
el se i f ( ( wr == 1' b1) &( t xr dy ==1' b1) ) t x_st s <= 1' b1;
/ / Transmi t t er i s busy
el se i f ( t xrdy ==1' b1) t x_st s <= 1' b0; end
/ / / Thi s modul e i s t o l oad dat a f r om dat al i ne t o tbr al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) 103
/ / Tr ansmi t t er i s f r ee
t br <= 8' b0; el se i f ( t xr dy ==1' b1) / / I f t r ansmi t t er i s r eady, t hen we need t o l oad dat a f r om dat al i ne t o data buf f er r egi st er t br <= dat a; end / / / Thi s modul e i s t o gener at e baud cl ock al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) count <= 0; el se i f ( ( t x_st s== 1' b1) &( count ==9) ) count <= 0; el se i f ( t x_sts ==1' b1) count <= count +1; el s e count <=0; end / / / Thi s modul e i s used, t o tr i gger t he baud cl ock al ways@( posedge cl k) begi n i f ( r st _n ==1' b0) baud_c l k <=1' b0; el se i f ( count == 1) baud_cl k <=1' b1; el s e baud_c l k <=1' b0; end
/ / / Thi s modul e i s f or s hi f i ng bi t by bi t al ways@( posedge cl k) 104
begi n i f ( r st _n ==1' b0) begi n t x<=1; t sr <= 10' b0; t xr dy <=1' b1; end el se i f ( ( wr ==1' b1) & ( t xr dy ==1' b1) ) / / / and ( ( t br ( 0) or t br ( 1) or t br ( 2) or t br ( 3) or t br ( 4) or t br ( 5) or t br ( 6) ) = ' 1' ) / / / Thi s pi ece of code i s t o l oad dat a f r om TBR t o TSR( wi t h St ar t , St op and Par i t y) begi n t sr [ 10] <=1' b1; t s r [ 9] <= ( t br [ 0] ^ t br [ 4] ^ t br [ 5] ^ t br [ 6] ^ t br [ 7] ) ;
t br [ 1]
^
t br [ 2]
^
t br [ 3] ^
t sr [ 8: 1] <= t br ; t sr [ 0] <=1' b0; end i f ( ( t s r [ 0] | t s r [ 1] | t s r [ 2] | t s r [ 3] | t s r [ 4] | t s r [ 5] | t s r [ 6] | t s r [ 7] | t s r [ 8] | t s r [ 9] | t s r [ 10] ) ==1' b0) t xr dy <=1' b1;
/ / t xr dy
t xr dy <=1' b0;
/ / t xr dy i s 0,
is
1,
when TSR has
f i ni shed sendi ng dat a. el s e be sent i f ( ( t xr dy ==1' b0) &( baud_cl k ==1' b1) ) begi n t x <= t sr [ 0] ; t sr <={1' b0 , t sr [ 10: 1] }; end end endmodul e 105
when TSR has dat a t o
AXI _I NTERFACI NG_UART modul e axi _i nt er f aci ng_uar t (
i nput Acl k, i nput Pcl k, i nput Rst , i nput Awval i d, i nput [ 31: 0] Awaddr , i nput Wval i d, i nput [ 31: 0] Wdat a, i nput [ 3: 0] Wst r b, i nput Br eady, i nput Ar val i d, i nput [ 31: 0] Ar addr , i nput Rr eady, out put
Awr eady,
out put
Wr eady,
out put
Bval i d,
out put
Br esp,
out put
Ar r eady,
out put
Rval i d,
out put [ 31: 0] Rdat a, out put
Rr esp,
i nput uar t _r x, out put
uar t _t x ) ;
wi r e[ 31: 0] pr dat a_f r om_uart ; wi r e[ 31: 0] paddr _f r om_apb; wi r e[ 31: 0] pwdat a_f r om_apb; wi r e psel _f r om_apb; wi r e penabl e_f r om_apb; wi r e pwr i t e_f r om_apb; 106
wi r e[ 3: 0] pst r b_s; / / / I nt er nal Si gnal s r eg psel _s; r eg pwr i t e_s; r eg penabl e_s; al ways@( posedge Pcl k) begi n i f ( ~Rst ) psel _s <= 1' b0; el s e psel _s <= psel _f r om_ apb; end r eg pwr i t e_s1, pwr i t e_s2, pwr i t e_s3, pwr i t e_s4; al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n pwr i t e_s <= 1' b0; pwr i t e_s 1 <= 1' b0; pwr i t e_s 2 <= 1' b0; pwr i t e_s 3 <= 1' b0; pwr i t e_s 4 <= 1' b0; end el se i f ( pwr i t e_f r om_apb) begi n pwr i t e_s 1 <= 1' b1; pwr i t e_s2 <= pwr i t e_s1; pwr i t e_s3 <= pwr i t e_s2; pwr i t e_s <= pwr i t e_s3; end 107
el s e begi n pwr i t e_s 1 <= 1' b0; pwr i t e_s2 <= pwr i t e_s1; pwr i t e_s3 <= pwr i t e_s2; pwr i t e_s <= pwr i t e_s3; end end r eg penabl e_s1, penabl e_s2, penabl e_s3;
al ways@( posedge Pcl k) begi n i f ( ~Rst ) begi n penabl e_s 1 <= 1' b0; penabl e_s2 <= 1' b0; penabl e_s 3 <= 1' b0; penabl e_s
<= 1' b0;
end el se i f ( penabl e_f r om_apb) begi n penabl e_s1 <= 1' b1; penabl e_s2 <= penabl e_s1; penabl e_s3 <= penabl e_s2; penabl e_s <= penabl e_s 3; end el s e begi n penabl e_s 1 <= 1' b0; penabl e_s2 <= penabl e_s1; 108
penabl e_s3 <= penabl e_s2; penabl e_s <= penabl e_s 3; end
end apb_br i dge_cha axi _2_apb( . Acl k( Acl k) , . Pcl k( Pcl k) , . Rs t ( Rs t ) , . Awval i d( Awval i d) , . Awaddr ( Awaddr ) , . Wval i d( Wval i d) , . Wdat a( Wdat a) , . Wst r b( Wst r b) , . Br eady( Br eady) , . Ar v al i d( Ar val i d) , . Ar addr ( Ar addr ) , . Rr eady( Rr eady) , . Pr eady( 1' b1) , . Pr dat a( pr dat a_f r om_uar t ) , . Ps l ver r ( 1' b0) , . Awr eady( Awr eady) , . Wr eady( Wr eady) , . Bval i d( Bval i d) , . Br esp( Br esp) , . Ar r eady( Ar r eady), . Rval i d( Rval i d) , . Rdat a( Rdat a) , . Rr esp( Rr esp) , . Paddr ( paddr _f r om_apb) , . Psel ( psel _f r om_apb) , 109
. Penabl e( penabl e_f r om_apb) , . Pwr i t e( pwr i t e_f r om_apb) , . Pwdat a( pwdat a_f r om_apb) , . Ps t r b( ps t r b_ s ) );
apb_uart _t op apb_2_uart ( . PCLK( Pcl k) , . PRESETn( Rst ) , . PSEL(psel _s) , . PENABLE( penabl e_s) , . PWRI TE( pwr i t e_s) , . PWDATA( pwdat a_f r om_ apb) , . PADDR( paddr _f r om_apb) , . PRDATA( pr dat a_f r om_uar t ) , . t x ( uar t _ t x) , . r x ( uar t _ r x) ); endmodul e
110
APB_Bridge:
APB_Interfacing_UART:
113
AXI_Interfacing_uart;
114
UART_Receiver:
UART_transmitter
115
