Analog Guide Raja Reddy P, Indian Institute of Science July 26, 2007 1. Calculate Vout(s)/V Vout(s)/Vin(s). in(s). plot Vo(t). Vo(t). calculate time constant and pole frequency frequency. R
Vi(t) V Vi(t)
C Vout(t)
R
0
2. In the following following circuit circuit plot iL(t), VL(t) R
Vi(t)
L
V Vi(t)
R
Vout(t)
3k
0.4sin(wt)
0
3. Find Vo(t) Vo(t) in the circuit below. below. Vo(t) 8k 1k
4k
4k
0.6sin(wt) 2k
2k
2k
1p
4. A system has has an SNR of 60 dB. If an uncorrelated uncorrelated noise noise of 1 mV is added added in a 1V of signal to it, then what is the SNR? 1
5. Both ckts are equivalent. equivalent. Express Rp and Cp interms interms of Rs and Cs. Find ω range range for which these both are equivalent. Assume high quality factor.
Rs
Rp
Cp
Cs
6. Calculate the maximum maximum clock frequency frequency..
D
Tcq = 1ns
Q
Tpd = 100ps
Clk
Tsetup = 200ps Thold = 300ps
7. Plot Vout. Vout.
10sin(wt)
Vout(t)
8. Plot Vout Vout with respect to the given input waveforms. waveforms. Vout
Vin2 3V
5V
1pF
1pF
Vin1 0
t Vin1
Vin2
3V
5V 0 t1
t
2
5. Both ckts are equivalent. equivalent. Express Rp and Cp interms interms of Rs and Cs. Find ω range range for which these both are equivalent. Assume high quality factor.
Rs
Rp
Cp
Cs
6. Calculate the maximum maximum clock frequency frequency..
D
Tcq = 1ns
Q
Tpd = 100ps
Clk
Tsetup = 200ps Thold = 300ps
7. Plot Vout. Vout.
10sin(wt)
Vout(t)
8. Plot Vout Vout with respect to the given input waveforms. waveforms. Vout
Vin2 3V
5V
1pF
1pF
Vin1 0
t Vin1
Vin2
3V
5V 0 t1
t
2
9. Design a divide-by-3 divide-by-3 counter using using D-flipflops. The duty cycle cycle of the divided clock clock should be 2/3. 10. What is the function function of the following following circuit?
A
A’
E’
E Y
A
A’
E
E’
11. Plot the output Vout. R
R
R
10R Vin = 0.1sin(wt) Vout
R
12. Calculate the frequency frequency of oscillation. oscillation. What is the minimum required required Gm for osciloscillation?
Gm
Gm R
C
Gm R
C
Gm R
3
C
R
C
13. Calculate the output impedance.
1M Rout 500k
gm = 2uA/V Rds=1M
500k
14. Both transistors are biased in saturation. Calculate “VA/Vin”. Neglect the body effect.
Rd
Vin A
15. Calculate the output if (i) gain Av = infinity (ii) gain Av = 10 Vin Av
Vout 1k
1k
4
1mA
16. If the following inverter biased in the middle of Vdd, what is the small signal gain? (Answer: gm r o ) Vdd
Vin
Vout
17. Crossection diagram of the inverter (be able to draw the contact of power supply and ground) 18. From the crossection of the diagram, be able to draw the parasitic BJT leads to latchup. 19. How to prevent latch-up (do not forget guard ring, clampping circuits!) 20. Draw the layout of an inverter or NOR/NAND gate. 21. For the following source follower, what is its -3dB bandwidth? How about it stability?
Vo Vi
22. For the following circuits, Vdd=5v, tell me what are Vo1 and Vo2 when Vin is 5V, 3V, 2.5V and 0V.
Vdd Vin
Vin Vo1
5
Vo2
23. What are the effective resistance from source to drain of the following two transistors? (The value of the resistance is R). Answer: both of them are 1/gm. R
(a)
(b)
24. In the following figure, if the two resisters are equal, what is its -3dB bandwidth? Compare its stability with that of a source follower. R2 R1 Vi Vo
25. For the following circuit, if the input is a rail-to-rail square wave, plot the wave after the inverter and vo. Vdd
Vi
Vo
26. For the following circuits, What is the gain? Using what technology to improve the matching of the input transistors? If the bias current increase, what happens to the gain? (Hit: Decrease!!!) What happens to the bandwidth? Replace the NMOS with npn BJT and PMOS with pnp BJT, answer the above questions.(Now gain remains constant with increasing biasing current!) 6
Vdd
Vb1 Vo−
Vo+
Vin+
Vin
Vb2
27. For the following circuits, answer the questions again. What are the advantages and disadvantages of these two amplifiers? Vdd
Vo−
Vo+
Vin+
Vin
Vb
28. You are porbing a square wave pulse in the lab that has a ris etime of 5 ns and fall time of 2 ns. What is the minimum bandwidth of the oscilloscope to view the signal? Answer: The time thay it takes an RC circuit to go from 10% to 90% of its final value is t=ln9*RC. The bandwidth of the oscilloscope larger than BW = ln9/(2*pi*2ns) = 174MHz. Choose a 200MHz or faster oscilloscope. To reduce error, choose a oscolloscope 3 time faster than the calculated value, or 600MHz. 29. What is the low frequency gain of the following circuits? The input is the input current Iin. Where does the dominant pole locate? How about the pole at node 1?
7
1
Iin
Vo R
C
30. For the following circuit, the threshold voltage of the transistor is 0.7V. Vb1=1v, Vb2=2v, When Vin change from 5V to 0V, draw the current flow through the transistors VS Vin. (This question was supplied by Wang Ge) Vin Vb2
M2
Vb1
M1
31. For the following circuit, what is the gain of Vout/Vin? Where is the Feedback and what is the function of feedback?
Vin
Vout
Ib1
Ib2
8
32. For the following circuits, the small signal input is Iin, the small signal output is vout, what is the small signaloutput? What is the gain?
Vout
33. Plot the Vout wave form of the following circuits:
C
R
Vin
Vout
Vin
Vout
R
C
C1, 1u Vin
R1, 9k Vout
R 1k
Vin
Vout
C2 9u
C 1u
R2 1k
34. For the following circuit, at time 0, the switch switches from A to B, figure out the voltage wave form at B.
1V
C1
9
C2
35. For the following circuit, what is the voltage value at A and B? (The Vt of the transistor is 1V). 5V
5V
C1
C2
36. The capacitor of the following figure is connected with two ideal MOS switches. Switches T1 and T2 are alternately turned on with a frequency ffc. What is the average current flowing from node 1 to node 2? What is the equivalent impedance from node 1 to node 2?
T1
T2
V1
V2 C1
37. Plot the output of the following RC circuit
Vin
Vout
10
38. How the following two circuits differ in their functionality and which one is a better reference?
M3
M4
M3
M4
M1
M2
M1
M2
R
R
(a) bandgap1
(b) bandgap2
39. Draw Vo. Initially Vo is at +5V. Vosat = 5V 1k 1k Vin +4V
Vout t Vin
−4V
40. what is the output Y in the figure shown below. 1
2
21
’1’ Y
X
41. Draw the output waveform. 11
Vdd
Vout Vdd
42. what is the minimum value of V1. V1
43. How the diode should be doped for faster electron-hole collection at terminals.
P N
12
44. In which region the capacitance C gs is maximum. G
S
45. How a pn-diode should be doped for maximum capacitance? 46. How to reduce the crowbar (short circuit current) in an inverter? 47. How the latchup and ESD robustness are affected with increased substrate doping? 48. I have not remembered this qestion exactly. Two different MOS structures are given and asked to find about the sidewall and bottom capacitance.
49. How I 1 and I 2 changes with temperature
I1
I2
50. Decreased drian doping results in (choose from the options below) (a) High gate oxide reliability
13
(b) Hot carrier reliability (c) Decreases drain contact resistance
51. what is the output voltage 3V
3V
3V
Vout
52. what is the slew rate of output voltage
Vout C= 1pF
Vin 3V 2V
100 uA
53. For an NMOS in saturation, the drain current depends on (choose from the options below) (a) Surface mobility (b) Bulk mobility (c) Both (d) None
14
54. what is the output voltage after 5 seconds Vdd
3V 0V
Vout 5uA
0.1pF
Vdd
55. plot the output voltage
I(t)
I(t)
t Vo
R C 20C
56. what is Vout in the final state?
Vout 2V
Vout
1V
2.5V
Initial State
Final State
15
57. Frequency spectrum of ideal squrewave (choose from the options below) (a) Only C 0 = 0 (b) Odd terms are zero (c) Even terms are zero
58. Initially V1 = V2 = 1V and Vin = 0.7V. If Vin changes to 1.5V what are the final states? Vdd
Vdd
Vin
Vin V1
V2
10 uA
1pF
1pF
59. what is the steady state output voltage, Threshold voltage is 0.5V V
Vout
2V
1V
3V
60. Plot the output voltage 3V Vin 3V
Vin
0
Vout
t
61. If Vth of NMOS increases,for an inverter N M L and NM H will (a) both increase
16
(b) both decrease (c) NM L increase N M H decrease (d) NM L decrease NM H increase
62. What is the equivalent value of resistance. S1
S2
Vin
Vout C
63. Impulse response of interpolation filter is. Amp
Amp
Amp
1
Amp
1 1/2
1/2 −T
(a)
+T
f
−T /2
(b)
f
+T/2
−T/2 +T/2 (c)
f
−T
+T
(d)
64. plot the output voltage
2V
Vin
Vin
Vout C R
1V t
65. What is the transfer function
R
G1
G1
H1
H1
17
C
f
66. A planar metal is used for an interconnect.Neglecting the fringing capacitance the RC time constant will be RC
RC
W
(a)
RC
RC
W
(b)
W
(c)
(d)
67. Relationship between the time constants of figures 1,2,3 3R
1.5R
1.5R
3C
1.5C
(1)
1.5C
(2) R
R
R
C
C
C
(3)
68. In NMOS at weak inversion, the current is dominated by (a) drift current (b) diffusion current (c) both (d) none of the above
69. In MOS, channel is inverted when the surface potential reaches (a) (b) (c) (d)
70. Band-to-band tunneling occurs when 18
W
(a) both dopings are high (b) both dopings are low (c) one is high and other is low (d) independent of doping
71. One question on n p = n2i 72. Logic expression [(a + b′ )(a′ + b)]′ (a) XOR (b) NOR (c) XNOR (d) NAND
73. For real discrete signal magnitude will be even/odd?—————–, Phase will be even/odd?——————– 74. plot the ouput voltage Vin
Vin
Vout R
t
R
75. Logic of the gate shown is
b a
c Y a
b
c
76. The following logic implements a (R is asynchronus reset) (a) MOD-15 counter
19
’1’
D
Q
D
R
Q
D
R
Q
R
D
Q
R
Clk
(b) MOD-8 counter (c) MOD-11 counter (d) None
77. Determine Vout. Give a possible application of the circuit.
Vdd
Vout
78. Plot Vout.
Vin
Vout t
Vin
79. What is the equation of FIFO when it is empty? 80. Two clock domains 10MHz and 100MHz. One full period pulse is produced at 5th clock cycle of 100MHz of pulse width equal to 1/100MHz. The pulse should be received by 10MHz clock. Rig up the circuit. 20
81. There is a set of 5 bits a5, a4, a3, a2, a1. Set for mod 8 counter is (a) a1 (b) a2, a1 (c) a3, a2, a1 (d) a4, a3, a2, a1 (e) a5, a4, a3, a2, a1
82. Which of the following circuits has higher output impedance? Rout1
Rout2
83. Determine i b ic ie and V b with β = 100 and V be = 0.7V for the circuit below. ,
,
Vdd
5k
0.1k
Vb
5k
0.1k
21
84. Determine gain of following circuita. Assume µ n = 2 µ p
4/1
4/1 Vout
Vin
2/1
Vout Vin
2/1
85. Determine Vout R
Vin Vout
86. Determine the gain for the circuit below.
Vdd
Vb1 Vo−
Vo+
Vin+
Vin
Vb2
22
87. Frequency response for an Open loop Opamp was given and the opamp was operated as an inverting amplifier with gain -2. Plot the closed loop frequency response. 88. Number of Boolean equation for an ’n’ input variable. 89. Find equation for the circuit below.
B
D A’
C
E Y
D
E
B
C
A’
90. Size the remaining 4 transistors for the circuit below so that Iout = In.
Iin Iout
Iin
1/1
91. Calculate R. The network is fully resistive. 23
R1
R2
I1
I1
R=?
I1+I2
92. What is the time constant 10c Vin
Vout R
R
C
93. Compute the gain at low and high frequency.
gmp
C
gmp
Iout gmn
gmn
Vin Ibias
94. The open-loop gain bandwidth product of an opamp is 200 MHz. If it is operating in negative feedback mode with a closed loop gain of 2, then what is the bandwidth? 95. A signal x(t) = 0.4sin(2.π .75Hz.t) + 0.6sin(2. π .25Hz.t) is sampled with a sampling frequency of 100 Hz. What will be the frequency spectrum of sampled signal? 24
96. Calculate the current I through resistor.
1k I 1V
97. Calculate Iout(Vin, gmn, gmp, ∆ V)
∆V
Iout
Vin
Ibias
98. What is the frquency of oscillation of output voltage? R
C
Vout R1
R2
25
99. Calculate Vout.
Vs R C Vout C
R
100. What is the minimum value of resistor Rmin?. Rmin R
R C
R
C
101. Two identical opamps having 3dB frequency f o are in cascade. Find the overall 3dB frequency.
102. Find the maximum frequency of operation of the following circuit. 26
Td = 1ns min 2ns max
Tcq = 0
Tcq = 0
Combinational D
D
Q
Clk
D
logic
Q
Td = 1ns min 2ns max Combinational logic
103. Maximum power is dissipated in an inverter when (a) Input is 1 (b) Input is 0 (c) Input is toggling
104. In a D Flip-Flop, Q bar is connected to D. Find its function. 105. In a ring oscillator frequency depends on
1
2
3
n
(a) No of stages n (b) Supply voltage (c)
W ratio L
of the inverters
106. Plot V c (t ).
I(t)
I(t)
R
Io
Vc(t) C t to
27
107. Draw the bode plots for gain and phase. 1k
10k
A=10db
A=10db 1p
10p
108. Plot the Gate Capacitance versus Gate voltage curves for MOSFETs at DC and high frequencies. 109. Which of these is equivalent to the given RC circuit. R Vin
Vout C
Ans:
A=10dB
Vout
R Vin C
110. The following circuit is a
0 Q D
1 Clk
28
(a) level 0 transparent latch (b) level 1 transparent latch
111. Find Rin for the following circuit.
Rd
Vg
Rin
112. Find Vout. Vin 0.4 0.3 0.2 0.1
Vout t
Vin
113. Find i1, i2, Va and Vb. i1
1k Va 1k
2V
Vb i2 1mA
29
1k
