Proceedings of National Conference on Recent advancement in Science, Technology & Management-2011
An Efficient Approach to Design Low Power Digital Systems Pradeep Singla
[email protected]
Naveen Kr. Malik
[email protected]
Department of Electronics & Communication Hindu College of Engineering, Sonipat-131001 Haryana.
Abstract – Programming logic array(PLA) plays a important role in the reconfigurable computing. In the recent years, Electronics applications demands for a low power design logics having application in low power CMOS, quantum computing, nanotechnology, optical computing and space applications. In this paper, we proposed revrssible PLA (RPLA) architecture.The reversible logic system recycles their energy and emits very little heat. It has been shown that the proposed RPLA needs fewer garbage outputs and constant inputs due to which design of low power digital system is possible. In order to demonstrate the design of reversible PLA, a 3-input reversible PLA is designed which can perform any functions using the combination of 8 min terms. Keywords- Reversible logic, Garbage outputs, Constant inputs, Programmable logic array. I.
INTRODUCTION
In the designing of digital systems, the power dissipation is one of the greatest concerns in this era. In the digital systems, a part of energy loss is due to switches and materials. Another part of energy is lost due to conventional approach of designing digital system. In 1961, Researcher like Rolf Landauer proposed that the systems designed by conventional approach results in energy dissipation due to information loss [1]. Each bit of information lost generates KTln2 joules of energy. Where K= 1.3806505× (joules ) is the Boltzmann‟s Constant and T is the absolute temperature at which the computation is performed [2]. Reversible computing, a new paradigm in computing, that helps in saving this energy which has been lost due to irreversibility. This energy is saved by charge recovery process [10]. Actually, Reversible circuits are those circuits that do not lost information [1]. When a computer performs a logical operation, the unwanted bits after the operation are thrown away
with sudden change of voltage from positive to negative and dissipated as heat [3][9]. Even ever wondered why computer processors become so hot on use? They need to be cooled aggressively to improve the performance. The processor thrown away unwanted bits after computation in the form of heat. This heat dissipation increasingly becomes a limiting factor on performance [6]. For computer speed to keep on increasing, we need to „uncompute „the unwanted bits. On applying reversible computing we can move charges one point to other with the help of oscillators and switches. Hence saving of power in designing of digital systems. II. BACKGROUND A reversible gate that implements one to one mapping between n inputs and n outputs is called an n×n reversible logic gate that can be represented as: ( , ,……., ) ( , ,……., ) In the design of reversible systems two conditions are permitted [4]. Fan- Out is not permitted. Feedback from gate outputs to inputs is not permitted. A Reversible system should be designed using minimum numbers of reversible logic gates. From the point of view of reversible system design, there are many parameters for determining the complexity and performance of the system [5]. The number of reversible gates: The number of reversible gates used in the system. The number of garbage outputs (GO): This refers to the numbers of unused outputs present in a reversible
Proceedings of National Conference on Recent advancement in Science, Technology & Management-2011 logic circuit. One cannot avoid the garbage outputs as these are very essential to achieve reversibility. Several reversible logic gates have been proposed in the litrature including 2×2 Feynman gate (FG), 3×3 Toffoli gate (TG), 3×3 Fredkin gate (FRG), 3×3 Peres gate (PG) and 3×3 New gate(NG)[5].The following gates are used for design of reversible digital system.
Fig. 3. Fredkin Gate Fig. 4(a) and Fig.4 (b) shows that the implementation of the Fredkin gate as OR and AND function respectively. X Y 1
FRG FRG
X+Y
X Y 0
FRG XY
A. Feynman Gate Feynman gate is a 2×2 one through reversible gate shown in fig. 1. It is called 2×2 gate because it has 2 inputs and 2 outputs. One through hate means that one input variable is also the output. The inputs double ( ) associates with its output double ( ) as follows. = ; = XOR
FG XOR
Fig.1 Feynman Gate Fig. 2(a) shows the implementation of Fynman gate for copying the input and fig. 2(b) shows the implantation of it for generating the complement of the inputs. X
FG
0
X
X
X XOR 0 = X
1
FG
X X‟
Fig 2(a)
OR Function
III.
AND Function
MOTIVATION FOR WORK
We proposed the architecture of RPLA. As we know, the programming logic Arrays (PLA‟s) are standard parts that offer customers a wide range of logic capacity, speed and voltage characteristics.The PLA‟s are used in number of medical & industrials applications like ultrasonic flaw detection etc.The PLAs are faster than high end DSP‟s[7]. Thus, we proposed a efficient approach to design a low power digital system by combining the effect of PLA‟s and reversible computing called RPLA.This approach can be utilized to design various logic systems like half adder, Multipliter etc. IV. PROPOSED IMPLEMENTATION The reversible PLA consist of reversible AND array designed from reversible Fredkin gate and Fynman gate is shown in fig 4.
N Inputs
Reversible
Reversible
AND
OR
Array
K Product
Array
Fig. 2(b) M output
B. Fredkin Gate Fredkin gate is a 3×3 conservative reversible gate. It is called 3×3 gate because it has three inputs and three outputs. The inputs triple ( , associates with its outputs triple ( , ).
FRG
= = =
XOR
Fig. 4 Proposed Reversible PLA In proposed reversible PLA, we used Fredkin gate and Fynman gate is shown in fig. 5.Among the existing reversible gates Fredkin gate is most suitable to generate AND or OR function with minimum gates and garbage outputs.
Proceedings of National Conference on Recent advancement in Science, Technology & Management-2011
Fig 5.2 General Reversible PLA-OR Array
Fig.5.1
General Reversible PLA- AND Array
Proceedings of National Conference on Recent advancement in Science, Technology & Management-2011 The PLA-AND Array is shown in fig. 5.1 using fredkin & Fynman gates(Reversible gates). The PLA-OR Array is shown in fig. 5.2 using fredkin gate(Reversible gate).The two revrsible functions are used to implement AND & OR array. In the AND array, the complement of the inputs are required and moreover fan-out is not allowed in reversible logic, thus Feynman gates are used to complement and replicate the signals when required. The designed 3-inputs reversible AND array will generate 8 product term as outputs, which are combined using the reversible OR array designed using the Fredkin gate, to generate the required output function. V. RESULT & CONCLUSION In this paper we emphasis on an efficient approach to design low power digital system using RPLA. The application of RPLA is in designing of low power digital systems like adder, Subtractor, Multiplier etc. The design of RPLA is proposed using Fredkin & Fynman gates(Reversible gates).This approach provides low power consumption design of digital system.This design approach will definitly resolve the power problem or heat generation problem in design of digital system.The proposed RPLA will provide a new approach to the arena of low power reconfigurable computing. REFRENCES [1] Marek Perkowski, Pawel Kerntopf, Andrezej Buller, Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits. [2] Ahsan raja chowdhary, Rumana nazmul, Hafiz md. Hasan babu, “A new Approach to synthesis Multiple- Output Functions Using Reversible Programable Logic Array”,IEEE Proceeding of the 19th Internatinal conferences on VLSI design 2006. [3] Maryam Ehsanpour, Payman Moallem, Abbas Vafaei, “ Design Of a Naval Reversible Multiplier Circuit Using Modified Full Adder”, IEEE 2010 International conferences on computer design and application, V3-230 – V3-234. [4] Matthew Morrison, Nagaajan Ranganathan,” Design of a Reversible ALU based on a Noval Programmable Reversible Logic gate Structure”, 2011 IEEE computer society annual symposium on VLSI,P126-P131 [5] H.R. Bhagyalakshmi, M.K. Venkatesha,” An Improved Design of a Multiplier using Reversible Logic gates”, International Journel of Engineerin Science & Technology, Vol. 2(8), 2010. [6] Vivek V. Shende, Aditya K.Prasad, Igor L. Markov and P. Hayes,” Reversible Logic Synthesis”, ICCAD 2002 Nov 10-14, 2002, san jose, california, USA. [7] Saleh Abdel-Hafeez, Shadi M harb & Willian R. Eisenstadt*,” High Speed. Digital CMOS Divide by N Frequency Divider”, 2008IEEE, P592-P595. [8] Himashu Thapliyal, M.B. Srinivas,” Noval Reversible ‘TSG’ gate and its Application for Designing of Primitive Reversible / Quantum ALU”. [9] R. Landuar, “Irreversibility and Heat Generation in the computation Process”, IBM Jounral of Research and Development, 5,pp.183-191,1961.
[10] T.Toffoli., “Reversible Computing”, Tech memo MIT/LCS/TM-151,MIT Lab for computer science (1980).
