AMBA 2 AHB - General --------------------
1. The specifcaton recommends ha only 16 wai saes are used. ha should you do i! more han 16 cycles are needed" For some slaves it is acceptable acce ptable to insert more than 16 wait states. Forexample, Forexample, a serial boot ROM which is only ever accessed at inial power upcould insert a larer number o! wait states and it would not a"ect the calculaon o! the system per!ormance and latency once system power up has been completed. For other slaves a number o! opons exist. # $%&'( or R)(R* response could be used to indicate that the slave is not yet able to per!orm the re+uested data trans!er trans!er,, or the slave could be accessed either in response to interrupts or aer pollin a status reister, reister, in either case indican that the slave is now able to respond in an acceptable number o! cycles.
2. hy is a #urs no allowed o cross a 1 $ilo#ye #oundary" '! an # slave samples $)&x at the start o! a burst transacon, it /nows it will be selected !or the duraon o! the burst. #lso, a slave which isnot selected at the start o! a burst will /now that it will not become selected unl a new burst is started. 1 /ilobyte is the smallest area an # slave may occupy in the memory map. (here!ore, i! a burst did cross a 1 /ilobyte boundary, the access could start accessin one slave at the beinnin o! the burst and then switch to another on the boundary, boundary, which must not happen !or the above reason. (he 1 /ilobyte boundary has been chosen as it is lare enouh to allow reasonable lenth bursts, but small enouh that peripherals can be alined to the 1 /ilobyte boundary without usin up too much o! the available memory map.
0. %an an AHB maser #e conneced direcly o an AHB sla&e" #ny slave which does not use $%&'( responses can be connected directly to an # master. master. '! the slave does use $%&'( responses then a simplied version o! the arbiter is also re+uired. '! an # master is connected directly to an # slave it is important to ensure that the slave drives R)#2* hih durin reset and that the select sinal $)& !or the slave is ed e d permanently hih.
'. ha is he sae o! he AHB si(nals durin( rese"
(he specicaon states that durin reset the bus sinals should be at valid levels. (his simply means that the sinals should be loic 343 or 313, but not i-5. (he actual loic levels driven are le up to the desiner. (R#$ is the only sinal specied durin reset, with a mandatory value o! '2&). 't is important that R)#2* is hih durin reset. ' ! all slaves in the system drive R)#2* hih durin reset then this will ensure that this is the case. owever, i! slaves are used which do not drive R)#2* hih durin reset it should be ensured that a slave which does drive R)#2* hih is selected at reset.
). %an a B*+, rans!er occur a he end o! a #urs" # 7$* trans!er can only occur at the end o! an undened lenth burst 8'9R:. # 7$* trans!er cannot occur at the end o! a xed lenth burst 8$';&), '9R<, =R#%<, '9R>, =R#%>, ' 9R16, =R#%16:.
6. ha is a de!aul sla&e" '! the memory map o! a system does not dene the !ull < iabyte address space then a de!ault slave is re+uired, which is selected when an access is a?empted to the empty areas o! the memory map. (he de!ault slave should use an O@#* response !or '2&)A7$* trans!ers and an )RROR response se+uence !or O$)BA$)B trans!ers.
. s a de!aul sla&e really necessary" '! the enre < iabyte address space is dened then a de!ault slave is not re+uired. '!, however, there are undened areas in the memory map then it is important to ensure that a spurious access to a nonexistent address locaon will not loc/ up the system. (he !unconality o! the de!ault slave is extremely simple and it will oen ma/e sense to implement this within the decoder.
>. s a dummy maser really necessary" # dummy master is necessary in any system which has a slave that can ive $%&'( trans!er responses. (he dummy master is re+uired so that somethin can be ranted the bus i! all the other masters have received a $%&'( response. o loic is re+uired !or the dummy master and it can be implemented by simply tyin o" the inputs to the master addressAcontrol mulplexer !or the dummy master posion. (he re+uirements !or a dummy master are that (R#$ is driven to '2&), &O9@ is driven low, and all other master outputs are driven to leal values.
/. s i specifed ha H0T3 H+45 and HT5 remain consan hrou(hou a #urs" *es, the control sinals must remain constant throuhout the duraon o! a burst.
1. ha de!aul sae should #e used !or he H5A7, and H5+0 oupus !rom a sla&e" 't is recommended that the de!ault value !or R)#2* is hih and the de!ault value !or R)$% is O@#*. (his combinaon ensures that the slave will respond correctly to '2&) t rans!ers to the slave, even i! the slave is in some !orm o! power savin mode.
11. s H5A7, an inpu or an oupu !rom sla&es" #n # slave must have the R)#2* sinal as both an input and an output. R)#2* is re+uired as an output !rom a slave so that the slave can extend the data phase o! a trans!er. R)#2* is also re+uired as an input so that the slave can determine when the previously selected slave has completed its nal trans!er and the rst data phase trans!er !or this slave is about to commence. )ach # $lave should have an R)#2* output sinal 8convenonally named R)#2*O7(: which is connected to the $lave-to-Master Mulplexer. (he output o! this mulplexer is the lobal R)#2* sinal which is routed to all masters on the # and is also !ed bac/ to all slaves as the R)#2* input.
12. How many masers can here #e in an AHB sysem" (he # specicaon caters !or up to 16 masters. owever, allowin !or a dummy bus master means the maximum number o! real bus masters is actually 1C. y convenon bus master number 4 is allocated to the dummy bus master.
18. %an a maser chan(e he address9conrol si(nals durin( a waied rans!er" *es. '! the addressAcontrol sinals are indican an '2&) trans!er then the master can chane to a real trans!er 8O$)B: when R)#2* is low. owever, i! a master is indican a real trans!er 8O$)B or $)B: then it cannot cancel this durin a waited trans!er unless it receives a $%&'(, R)(R* or )RROR response.
1<. hen a maser re#uilds a #urs which has #een erminaed early are here any limiatons on how
i re#uilds he #urs" (he only limitaon is that the master uses leal burst combinaons to rebuild the burst. For example, i! a master was per!ormin an > beat burst,but had only completed 0 trans!ers be!ore losin control o! the bus, then the remainin C trans!ers could be per!ormed either by usin a 1 beat $';&) burst !ollowed by a < beat '9R< burst, or it could be per!ormed usin a C beat undened lenth '9R burst. For simplicity it is recommended that masters use '9R bursts to rebuild the remainin trans!ers.
1). ha is he recommended de!aul &alue !or H0T D Many bus masters will not be able to enerate accurate protecon in!ormaon and !or these bus masters it is recommended that the %RO( encodin shows, on-cacheable, on-bu"erable, %rivileed, 2ata #ccesses which corresponds to %RO(E04G H <3b4411.
16. 7o all sla&es ha&e o suppor he B*+, rans!er ype" *es. #ll slaves must support the 7$* trans!er type to ensure they are compable with any bus master.
1. ha sysem suppor is re:uired i! a sla&e can #e powered down or ha&e is cloc$ sopped" '! a slave access is a?empted while that slave is in a power down state or has had its cloc/ stopped, you must ensure that an access will cause the powerAcloc/ to be restored, or else conure the # decoder up to redirect any such accesses to the dummy slave so that the system does not han !orever when an access to the device is made when it is disabled. Redirecn the access in this way will ensure that random I'2&)I addresses are treated with the R)#2* hih and R)$%HO@#* de!ault response, but real accesses 8O$)B or $)B: w ill be detected with an )RROR response.
1;. hen can 5arly Burs Terminaton occur ursts can be early terminated either as a result o! the #rbiter removin the ;R#( to a master part way throuh a burst, or aer a slave returns a non-O@#* response to any beat o! a burst. ote however that a master cannot decide to terminate a dened lenth burst unless prompted to do so by the #rbiter or $lave responses. #ll # Masters, $laves and #rbiters must be desined to support )arly urst (erminaon.
1/. 7oes he address ha&e o #e ali(ned3 e&en !or 7<5 rans!ers" *es. (he address should be alined accordin to the trans!er siJe 8$'5): even !or '2&) trans!ers. (his will prevent spurious warnins !rom bus monitors used durin simulaon.
2. ha is he di=erence #eween a dummy #us maser and a de!aul #us maser" (he term de!ault bus master is used to describe the master that is ranted when none o! the masters in the system are re+uesn access to the bus. 7sually the bus master which is most li/ely to re+uest the bus is made the de!ault master. (he dummy bus master is a master which only per!orms '2&) trans!ers. 't is re+uired in a system so the arbiter can rant a master which is uaranteed not to per!orm any real trans!ers. (he two cases when the arbiter would need to do this are when a $%&'( response is iven to a loc/ed trans!er and when a $%&'( response is iven and all other masters have already been $%&'(.
21. s i le(al !or a maser o chan(e HA77 when a rans!er is e>ended" '! a master is indican that it wants to do a O$)B, $)B or 7$* trans!er then it cannot chane the address durin an extended trans!er 8when R)#2* is low: unless it receives an )RROR, R)(R* or $%&'( response. '! the master is indican that it wants to do an ' 2&) trans!er then it may chane the address.
22. %an HTA?+ chan(e whils H5A7, is low D 'n eneral, an # master should not chane control sinals whilst R)#2* is low. owever it is allowable to chane (R#$ in the !ollowin condions K (R#$ H '2&) (he # master is per!ormin internal operaons and has not yet commi?ed to a bus trans!er. owever durin the # wait states 8R)#2* low: the master may determine that a bus trans!er is re+uired and chane (R#$ on the next cycle to O$)B. K (R#$ H 7$* (R#$ is bein used to ive the master me to complete internal operaons, which may be enrely independent o! R)#2* 8i.e. wait states on the #:. (here!ore (R#$ can chane on the next cycle to any leal value, i.e. $)B i! the burst is to connue, '2&) i! the burst has completed, O$)B i! a separate burst is to bein.
K R)$% H $%&'(AR)(R* #s stated in the # specicaon, a master must assert '2&) on (R#$ durin the second cycle o! the two-cycle $%&'( or R)(R* slave response so (R#$ will c hane value !rom the rst cycle to the second cycle o! the response. K R)$% H )RROR (he master is permi?ed to chane (R#$ in reacon to an )RROR response in the same way as in reacon to a $%&'(AR)(R* response and cancel any !urther beats in the current burst 8even i! 7R$( is indican a dened-lenth burst:. 'n this case (R#$ chanes to '2&) on the second cycle o! the response. #lternavely, the master is permi?ed to connue with the current trans!ers.
28. ha are he di=eren #urss used !or" (ypically a master would use wrappin bursts !or cache line lls where the master wants to access the data it re+uires rst and then it completes the burst to !etch the remainin data it re+uires !or the cache line ll. 'ncremenn bursts are used by masters, such as 2M# controllers, that are llin a bu"er in memory which may not be alined to a parcular address boundary.
2'. ha se:uences o! rans!ers ypes @HTA?+ can occur on he #us" (he !ollowin examples show some o! the se+uences o! (R#$ that can occur on the bus # normal burst o! !our trans!ers !ollowed by an '2&). -$-$-$-' # normal burst o! !our trans!ers which includes 7$* trans!ers. -$--$--$-' # burst o! !our trans!ers !ollowed by another burst. -$-$-$--$-$-$-' # sinle trans!er !ollowed by a burst o! !our trans!ers. --$-$-$-' # sinle trans!er !ollowed by an '2&) -'
#n undened lenth burst which concludes with a 7$* trans!er. --$--$--' #n undened lenth burst which concludes with a 7$* t rans!er and is !ollowed immediately by another burst. --$--$---$
2). How should AHB o A0B #rid(es handle accesses ha are no 82-#is" (he bride should simply pass the enre 0L-bit data bus throuh the bride. %lease note that when trans!ers less than 0L-bits are per!ormed to an #% slave it is important to ensure that the peripheral is located on the appropriate bits o! the #% data bus.
AMBA AHB - Ar#iraton 1.hen should a maser asser and deasser he H<% si(nal !or a loc$ed rans!er" (he &O9@ sinal must be asserted at least one cycle be!ore the start o! the address phase o! a loc/ed trans!er. (his is re+uired so that the arbiter can sample the &O9@ sinal as hih at the start o! the address phase. (he master should deassert the &O9@ sinal when the address phase o! the last trans!er in the loc/ed se+uence has started.
2. %an an ar#ier #e desi(ned o always allow #urss o complee" # $%&'(, R)(R* or )RROR response !rom a slave can always cause a burst to be early terminated. (his is outwith the control o! the #rbiter and so must be supported. 7ndened lenth '9R bursts cannot have their end point predicted, so there is no eNcient way that an #rbiter desin can allow the burst to complete be!ore rann another master. '9R bursts must be arbitrated on a cycle by cycle basis. 2ened lenth '9Rx and =R#%x bursts can have their beats counted, and so allowed to complete by the #rbiter. owever because o! the # arbitraon synchronous min, there is no way to avoid possibly terminan a burst immediately aer the rst trans!er o! the burst has been indicated. (he #rbiter only /nows that a dened lenth burst is in proress by samplin the 7R$( bus. owever
the rst point at which 7R$( can be sampled is aer the rst cloc/ cycle o! the rst burst beat, by which me the #rbiter may already have decided to rant another master and will have chaned the ;R#( outputs accordinly. Only a combinatorial path !rom 7R$( to ;R#( would allow the burst to be detected in me to avoid early terminaon in this scenario, but combinatorial paths in the # bus are not allowed. as/ #RM
0. hy is HA77 sometmes shown as an inpu o he ar#ier D (he address bus, #22R, is not re+uired as an input to the arbiter but in some system desins it may be use!ul to use the address bus to determine a ood point to chane over between bus masters. For example, the arbiter could be desined to chane bus ownership when a burst o! trans!ers reaches a +uad word boundary.
'. hen can he HGA?T si(nal chan(e" (he ;R#( sinal can chane in any cycle and the !ollowin cases are possible K 't is possible that the ;R#( sinal may be asserted and then removed be!ore the current trans!er completes. (his is acceptable because the ;R#( sinal is only sampled by masters when R)#2* is hih. K # master can be ranted the bus without re+uesn it. K (he above point also means that it is possible to be ranted the bus in the same cycle that it is re+uested. (his can occur i! the master is coincidentally ranted the bus in the same cycle that it re+uests it.
). ha is he relatonship #eween he H<% si(nal and he HMA+T<% si(nal" #t the start o! the address phase o! every trans!er the arbiter will sample the &O9@ sinal o! the master that is about to start drivin the address bus and i! &O9@ is asserted at this point then M#$(&O9@ will be asserted by the arbiter !or the duraon o! the address phase o! the trans!er.
6. hen should a maser deasser is HB*+5C si(nal" For an undened lenth burst 8'9R: a master must /eep its 7$R)B sinal asserted unl it has started the address phase o! the last trans!er in the burst. (his will mean that i! the penulmate trans!er in the burst is Jero wait state then the master may be ranted the bus !or an addional trans!er at the end o! an undened lenth burst.
For a dened lenth burst the master can deassert the 7$R)B sinal once the master has been ranted the bus !or the rst trans!er. (his can be done because the arbiter is able to count the trans!ers in the burst and /eep the master ranted unl the burst completes. owever it is not a mandatory re+uirement !or an #rbiter to allow a burst to complete, so the master will have to re-assert 7$R)B i! the #rbiter removes ;R#( be!ore the burst has been completed.
. hen will he ar#ier (ran anoher maser aDer a loc$ed rans!er" (he arbiter will always rant the master an extra trans!er at the end o! a loc/ed se+uence, so the master is uaranteed to per!orm one trans!er with the M#$(&O9@ sinal low at the end o! the loc/ed se+uence. (his coincides with the data phase o! the last trans!er in the loc/ed se+uence. 2urin this me the arbiter can chane the ;R#( sinals to a new bus master, but i! the data phase o! the last loc/ed trans!er receives either a $%&'( or R)(R* response then the arbiter will drive the ;R#( sinals to ensure that either the master per!ormin the loc/ed se+uence remains ranted on the bus !or a R)(R* response, or the 2ummy master is ranted the bus !or the $%&'( response.
>. %an a maser deasser H<% durin( a #urs" (he # specicaon re+uires that all address phase med control sinals 8other than #22R and (R#$: remain constant !or the duraon o! a burst. #lthouh &O9@ is not an address phase med sinal, it does directly control the M#$(&O9@ sinal which is address phase med. (here!ore &O9@ must remain hih !or the duraon o! a burst, and can only be deasserted such that the !ollowin M#$(&O9@ sinal chanes aer the nal address phase o! the burst.
/. ! a maser is currenly (raned he #us #y de!aul3 how many cycles #e!ore sartn( an non-7<5 rans!er does i ha&e o asser HB*+5C" one. 't can start a non '2&) trans!er immediately.
1. %an a maser per!orm rans!ers oher han 7<5 when he #us was (raned o i3 #u no re:uesed #y he maser" *es. # master can per!orm trans!ers other than '2&) when it had not re+uested the bus. %lease note that in this case it is sll recommended that the master asserts its re+uest sinal so that the arbiter does not
chane ownership o! the bus to a lower priority master while the trans!ers are in proress.
AMBA 2 A0B - General -------------------1. hy is here no wai si(nal on he A0B" (he #% has been desined to implement as simple an inter!ace as possible. avin this simple desin ma/es it much easier to connect new #% peripherals and ma/es the analysis o! the system per!ormance easier to calculate. #lthouh many #% peripherals are slow devices, such as 7#R(s, they are normally accessed via control reisters. (ypically the driver soware will rst access a status reister to determine that data is available and only then access the data reister. oth o! these accesses are possible without the addion o! wait states and there!ore the peripheral can easily be accessed as an #% device. %eripherals which do re+uire wait states can be desined as # slaves and in the rare case that a desin does include a lare number o! these peripherals then a secondary stub # can be used to reduce the
loadin on the main system bus.
2. How should AHB o A0B #rid(es handle accesses ha are no 82-#is" (he bride should simply pass the enre 0L-bit data bus throuh the bride. %lease note that when trans!ers less than 0L-bits are per!ormed to an #% slave it is important to ensure that the peripheral is located on the appropriate bits o! the #% data bus
