A1502 820-3476-A

8

7

6

5

4

3

2

1 CK

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

R EV

EC N

< RE RE V> V>

DESCRIPTION OF REVISION

APPD APPD

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DATE

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D

J44 MLB-4GB SCHEMATIC 08/20/2013 (.csa)

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TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM















C


















B













1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 18 19 20 22 23 25 27 28 29 30 32 33 34 35 37 39 40 46 48 49 50 51 52 53 54 55 56 58 60 61

Date

Contents Table of Contents BOM Configuration BOM Configuration PD Parts CPU GFX/NCTF/RSVD CPU Misc/JTAG/CFG/RSVD Misc/JTAG/CFG/RSVD CPU DDR3/LPDDR3 Interfaces CPU/PCH POWER CPU/PCH GROUNDS CPU Decoupling PCH Decoupling PCH Audio/JTAG/SATA/CLK Audio/JTAG/SATA/CLK PCH PM/PCI/GFX PCH PCIe/USB/LPC/SPI/SMBus PCIe/USB/LPC/SPI/SMBus PCH GPIO/MISC/LPIO GPIO/MISC/LPIO CPU/PCH Merged XDP Chipset Support Project Chipset Support DDR3 VREF MARGINING DDR3 SDRAM Bank A (Rank 0) DDR3 SDRAM BANK B (RANK 0) DDR3 Termination Thunderbolt Host (1 of 2) Thunderbolt Host (2 of 2) Thunderbolt Mobile Support Thunderbolt Connector A Thunderbolt Connector B DDC Crossbar WIRELESS SUPPORT SSD Connector Camera 1 of 2 Camera 2 of 2 External A USB3 Connector KEYBOARD/TRACKPAD KEYBOARD/TRACKPAD (1 OF 2) KEYBOARD/TRACKPAD KEYBOARD/TRACKPAD (2 OF 2) SMC SMC Shared Support SMC Project Support SMBus Connections Power Sensors: High Side Power Sensors: Load Side Power Sensors: Extended Thermal Sensors Fan LPC+SPI Debug Connector

Sync D2_KEPLER J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 MASTER MASTER

01/13/2012 08/20/2013 01/03/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 MASTER MASTER

04/02/2013 J44_YONAS-4GB 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44 08/12/2013 J44

( .c sa)

Page 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

TABLE_TABLEOFCONTENTS_HEAD

































62 63 64 65 66 70 71 72 73 74 75 76 77 78 80 81 83 95 97 100 102 103 104 110 111 112 113 114 115 116 117 118 120

< EC EC O_ O_ DE DE SC SC RI RI PT PT IO IO N> N>

D

Date

Contents AUDIO: AUDIO:COD CODEC, EC, ANALOG ANALOG AUDIO: AUDIO:COD CODEC, EC, DIGITA DIGITAL L AUDI AUDIO: O: SPEA SPEAKE KER R AMP AMP A UD UD IO IO : J AC AC K AUDIO: AUDIO: JACK JACK TRANSL TRANSLATO ATORS RS DC-In DC-In & Batter Battery y Connec Connector tors s PBus PBus Supply Supply & Batter Battery y Charge Charger r CPU VR12.6 VR12.6 VCC Regula Regulator tor IC CPU VR12.5 VR12.5 VCC Power Power Stage Stage 1.35 1.35V V DDR3 DDR3 SUPP SUPPLY LY 5V / 3.3V 3.3V Power Power Supply Supply 1.05V 1.05V S0 Power Power Supply Supply LCD AND KBD BKLT BKLT DRIVER DRIVER Misc Misc Power Power Suppli Supplies es P ow ow er er F ET ET s Powe Power r Cont Contro rol l eDP Displa Display y Connec Connector tor RIO RIO Conn Connec ecto tor r Displa Display y Mux: Mux: HDMI HDMI vs DP Powe Power r Alia Aliase ses s Sign Signal al Alia Aliase ses s Memory Memory Bit/By Bit/Byte te Swizzl Swizzle e Functi Functiona onal l / ICT Test Test PCB Rule Rule Defini Definitio tions ns CPU & PCIe Constraints USB Constraints PCH Constraints Memory Constraints TBT,DP TBT,DP,HD ,HDMI MI Constr Constrain aints ts Camera Camera Constr Constrain aints ts SMC SMC Cons Constr trai aint nts s Project Project Specific Specific Constrain Constraints ts R ef ef er er en en ce ce

Sync J44 J44 J44 J44 J44

J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 J44 MASTER J44 J44 J44 J44 J44 J44 J44 J44 J44

J44 J44 J44

08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013

C

08/12/2013 08/12/2013 08/12/2013 08/12/2013 MASTER 01/03/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 01/03/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013 08/12/2013

B



ALIASES ALIASES RESOL RESOLVED VED

A

A

DRAWING TITLE

DRAWING NUMBER

Apple Inc. R

Schematic / PCB #’s

PART NUMBER 051-0052

QTY 1

DESCRIPTION

REFERENCE DES

CRITICAL

SCHEM,MLB-4GB,J44

SCH

CRITICAL

BOM OPTION

SIZE

D

REVISION

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

PAGE

1 OF 120

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2

1

BOM Groups TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS TABLE_BOMGROUP_ITEM

J44_COMMON

ALTERNATE,COMMON,J44_ COMMON1,J44_COMMON2,J 44_COMMON3,J44_COMMON 4,J44_PROGPARTS TABLE_BOMGROUP_ITEM

J44_COMMON1

J44_COMMON2

EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,MEM_ODT:PU,VCORE_FETS

J44_COMMON3

XDP,LPCPLUS,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO

TBTHV:P15V,SKIP_5V3V3:AUDIBLE,SPI:DUAL_IO TABLE_BOMGROUP_ITEM

D

D

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

J44_PROGPARTS

SMC_PROG:PVT,BOOTROM:PVT,TBTROM:PVT,TPAD_PSOC:PROG TABLE_BOMGROUP_ITEM

ENGISNS

LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS

Programmables (All Builds) TBT PART NUMBER

QTY

3 4 1S 3 91 8

1

EPROM,FALCON RIDGE (V13.7) J44

D E S C R IP T I ON

REFERENCE DES U2890

1

IC,SMC-B1,EXT(V2.16F39),PVT,J44

1

1

B OM OP T I O N

CRITICAL

C RITI CAL

TBTROM:PVT

U5000

C RITI CAL

SMC_PROG:PVT

IC,EFI ROM (V0116),PVT,J44

U6100

C RITI CAL

BOOTROM:PVT

IC,TRKPD/KYBD PSOC,CU ONLY(V224) J44

U4801

CR ITI CAL

TPAD_PSOC:PROG

SMC 3 4 1S 3 92 2

Module Parts P A RT N U M B ER

C

REFERENCE DES

CRITICAL

B OM OP T I O N

3 37 37 S4 59 59 6

1

HSWULT,SR18A,PRQ,C0,2.4,28W,2+3,3M,BGA

U 05 00

C RI TI TI CA L

CPU_HSW:2.4G

3 37 37 S4 59 59 7

QTY 1

HSWULT,SR189,PRQ,C0,2.6,28W,2+3,3M,BGA

U 05 00

C RI TI TI CA L

CPU_HSW:2.6G

3 37 37 S4 59 59 8

1

HSWULT,SR188,PRQ,C0,2.8,28W,2+3,4M,BGA

U0500

CRITICAL

CPU_HSW:2.8G

338S1247

1

3 3 8 S 1 1 86

1

3 7 6 S 1 1 94

2

3 7 6 S 1 1 93

D E SC R I P T ION

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288 IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR

U 28 28 00 U 3 9 00

EFI ROM 3 4 1S 3 92 4

C

C RI TI TI CA L C R I T I CA L C R I TI C A L

PSOC

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

Q7 3 1 0 , Q 73 20

2

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

Q7 3 1 1 ,Q 7 3 21

CRITICAL

V C O R E_ F E T : V S H Y

V C OR E _ F E T :V S H Y

3 7 6 S 09 64

2


Q7310,Q7320

CRITICAL

V C O R E_ F E T :R E N

376S1104

2


Q7311,Q Q7311,Q7321

CRITICAL

V C OR E _ F E T: R E N

341S3862

Alternate Parts TABLE_ALT_HEAD

P AR T N UM BE R ALTERNATE FOR PART NUMBER

B OM O PT IO N

REF DES COMMENTS: TABLE_ALT_ITEM

3 76 S1 S1 05 3 3 76 S0 S0 60 4

A LL

128 S031 1 128S0329

A LL

Diodes alt to Fairchild TABLE_ALT_ITEM

NEC a lt to S a n y o TABLE_ALT_ITEM

1 3 8 S 07 3 9

1 38 S0 7 0 6

ALL

197 S048 1 197S0480

ALL

152S0461

ALL

S a m s u n g a l t to M u r a t a TABLE_ALT_ITEM

Epson alt to NDK TABLE_ALT_ITEM

B

15 2 S 1 6 4 5

Cyntec alt to Vishay

B

TABLE_ALT_ITEM

376 S108 0 376S0820

D i o d es a l t t o O n S e m i

ALL TABLE_ALT_ITEM

155S0667

155S0583

ALL

138S0725

138S0724

ALL

Panasonic alt to TDK TABLE_ALT_ITEM

Samsung alt to Murata TABLE_ALT_ITEM

376 S103 2 376S0855

Toshiba alt for Diodes Dual

ALL TABLE_ALT_ITEM

376S1129

376S0855

ALL

376 S108 9 376S1128

ALL

NXP Alt for Diodes Dua l TABLE_ALT_ITEM

NXP Alt for Diodes Single TABLE_ALT_ITEM

353S3452

35 3 S 1 2 8 6

ALL

376S1180 376S0761

ALL

M a x im a lt to M i c r o c h i p TABLE_ALT_ITEM

Renesas alt to Vishay TABLE_ALT_ITEM

128S0364

12 8 S 0 2 6 4

ALL

107 S025 4 107S0241

ALL

1 3 8 S 08 4 3 13 8 S 0 6 7 4

ALL

Sanyo 2nd Factory alt TABLE_ALT_ITEM

Cyntec alt to TFT TABLE_ALT_ITEM

S a m s un g a l t to M u r a ta ( B KL T ) TABLE_ALT_ITEM

138S0803 138S0639

ALL

138S0846 138S0811

ALL

Samsung alt to Murata (BKLT) TABLE_ALT_ITEM

Samsung alt to Murata (BKLT) TABLE_ALT_ITEM

1 97 S0 S0 54 2 1 97 S0 S0 54 4

A LL

NDK alt to TXC TABLE_ALT_ITEM

197S0545 197S0544

ALL

152 S187 6 152S1804

ALL

Epson alt to TXC TABLE_ALT_ITEM

TDK alt to Toko TABLE_ALT_ITEM

A

107 S025 5 107S0240

ALL

Cyntec alt to TFT

A

TABLE_ALT_ITEM

107S0250

107S0248

ALL

127S0164

12 7 S 0 1 6 2

ALL

Cyntec alt to TFT TABLE_ALT_ITEM

Rohm alt to Vishay TABLE_ALT_ITEM

3 5 3 S 40 7 0

3 53 S4 0 6 9

ALL

P e r i c o m a l t to T I D P M u x U 9 7 5 0

SYNC_MASTER=J44

PAGE TITLE

SYNC_DATE=08/20/2013

BOM Configuration DRAWING NUMBER

Apple Inc.

TABLE_ALT_ITEM

3 5 3 S 40 6 8 35 3 S 4 0 6 9

ALL

N XP al t to TI DP M ux U 9 7 50 TABLE_ALT_ITEM

353S3814

35 3 S 3 8 1 2

ALL

T I a lt t o N X P TABLE_ALT_ITEM

311S0649 311S0541

ALL

ONsemi alt to Toshiba TABLE_ALT_ITEM

128 S043 6 128S0392

ALL

K e m et a lt t o S a n yo

R

SIZE

D

REVISION


BRANCH


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2

1

BOM Variants DEVELOPMENT/BASE BOM

TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

BOM OPTIONS

PART NUMBER

TABLE_BOMGROUP_ITEM

6 85 85 -0 05 05 4

C OM MO MO N, ML ML B- 4G 4G B, J4 J4 4

9 85-0 053

DEV ,MLB -4G B,J4 4

J44_COMMON TABLE_BOMGROUP_ITEM

XDP_CONN TABLE_BOMGROUP_ITEM

639-4878

PCBA,MLB-4GB,2.4G,4GB-HYNIX,J44

QTY

DE S C R IP T I ON

6 8 5 - 0 0 54

1

J44 MLB COMMON BOM

BASE

C R I TI CA L

B AS E_ B O M

9 8 5 - 0 0 53

1

J 44 44 M LB LB D EV EV EL EL B OM OM

R E F E R EN CE DES DEVEL

C R I T I CA L CRITICAL

B OM O P T I ON D E V EL _ B O M

QTY

DE S C R IP T I ON

R E F E R EN CE DES

C R I T I CA L

B OM O P T I ON

1

VCORE,FET,VSHY,J44

VCOREFETS

C R I T I CA L

VCORE_FETS

BASE_BOM,CPU_HSW:2.4G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H TABLE_BOMGROUP_ITEM

639-4879

PCBA,MLB-4GB,2.4G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.4G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA TABLE_BOMGROUP_ITEM

D

639-4880

PCBA,MLB-4GB,2.4G,4GB-MICRON,J44

639-5272

PCBA,MLB-4GB,2.6G,4GB-HYNIX,J44

BASE_BOM,CPU_HSW:2.4G,RAM_4G_MICRON,CAMDRAM:MICRON

SUB-BOMS TABLE_BOMGROUP_ITEM

PART NUMBER

BASE_BOM,CPU_HSW:2.6G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H

D

TABLE_BOMGROUP_ITEM

639-5273

PCBA,ML PCBA,MLB-4GB,2 B-4GB,2.6G, .6G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.6G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

639-5274

PCBA,ML PCBA,MLB-4GB,2 B-4GB,2.6G, .6G,4GB-MICRON,J44


639-5275

PCBA,MLB-4GB,2. -4GB,2.8G,4 8G,4GB-HYNIX,J44

639-5276

PCBA,ML PCBA,MLB-4GB,2 B-4GB,2.8G, .8G,4GB-ELPIDA,J44

BASE_BOM,CPU_HSW:2.8G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA

639-5277

PCBA,ML PCBA,MLB-4GB,2 B-4GB,2.8G, .8G,4GB-MICRON,J44


6 8 5 - 0 0 74 TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BASE_BOM,CPU_HSW:2.8G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H

Alternate Parts TABLE_BOMGROUP_ITEM

TABLE_ALT_HEAD

P AR T N UM BE R ALTERNATE FOR PART NUMBER

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

685-0074

VCORE,FET,VSHY,J44

6 85 85 -0 07 07 5

V CO RE RE ,F ET ET ,R EN EN ,J 44 44

B OM O PT IO N

REF DES COMMENTS: TABLE_ALT_ITEM

685 -007 5 685-0074

AL L

RENESAS ALT TO VISHAY

VCORE_FET:VSHY TABLE_BOMGROUP_ITEM

VCORE_FET:REN

DRAM PARTS

C

3 33 33 S0 70 70 4

8

IC,SDRAM,4G BIT,256MX16, DDR3-1600,F DIE,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

3 33 33 S0 70 70 0

8

IC,SDRAM,4GBI T,256MX16,DDR 3-1600,HUMA, 96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

3 33 33 S0 69 69 8

8

IC,SDRAM,4G BIT,256MX16, V E,96FBGA DDR3-1600,RE

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

333S0715

8

IC,SDRAM,4G BIT,256MX16, DDR3-1866,F DIE,96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_ELPIDA_1866

333S0717

8

IC,SDRAM,4GBI T,256MX16,DDR 3-1866,HUMA, 96FBGA

U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560

CRITICAL

4G_HYNIX_H_1866

333S0720

8

IC,SDRAM,4G BIT,256MX16, DDR3-1866,RE V E,96FBGA

CRITICAL

4G_MICRON_1866

U2300,U2320,U2340,U2360, U2500,U2520,U2540,U2560 U2500,U2520,U2540,U2560

4G_ELPIDA 4G_HYNIX_H 4G_MICRON

C

DRAM SPD Straps TABLE_BOMGROUP_HEAD

BOM GROUP


RAM_4G_ELPIDA

4G_ELPIDA,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V35 TABLE_BOMGROUP_ITEM

RAM_4G_HYNIX_H

4G_HYNIX_H,RAMCFG3:L,RA G3:L,RAMCFG MCFG2:L,RAM 2:L,RAMCFG1 CFG1:L, :L,RAMC RAMCFG0 FG0:H,P :H,PPDDR:1V PDDR:1V35 35

R AM AM _4 _4 G _M I CR ON ON

4 G _M IC IC R ON , RA M CF G 3: L, L, R AM C FG 2 :L ,R ,R A MC F G1 : H, R AM CF CF G 0: L ,P P DD R :1 V3 V3 5

RAM_4G_ELPIDA_1 LPIDA_1866

4G_ELPIDA_1 LPIDA_1866, 866,RAM RAMCFG3 CFG3:L, :L,RAMC RAMCFG2 FG2:L,R :L,RAMC AMCFG1: FG1:L,R L,RAMCF AMCFG0:L G0:L,PPDDR:1V5

RAM_4G_ RAM_4G_HYNIX_H_1866

4G_HYNIX_H_1866 _H_1866,RAM ,RAMCFG CFG3:L, 3:L,RAM RAMCFG2 CFG2:L, :L,RAMC RAMCFG1 FG1:L,R :L,RAMC AMCFG0: FG0:H,P H,PPDDR PDDR:1V :1V5 5

RAM_4G_MICRON_1 ICRON_1866

4G_MICRON_1 ICRON_1866, 866,RAM RAMCFG3 CFG3:L, :L,RAMC RAMCFG2 FG2:L,R :L,RAMC AMCFG1: FG1:H,R H,RAMCF AMCFG0:L G0:L,PPDDR:1V5

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

NOTE: 1866 PARTS BEING STRAPPED TO RUN AT 1600

13" MBP VARIABLE BOM GROUPS

B

B

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

J44_COMMON4

SMCBOARDID:8

TABLE_BOMGROUP_ITEM

DRAM SPD Straps TABLE_BOMGROUP_HEAD

BOM GROUP CAMDRAM:HYNIX_H

BOM OPTIONS CAMDRAM_TYPE:HYNIX_H

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CAMDRAM:ELPIDA

CAMDRAM_TYPE:ELPIDA

CAMDRAM:MICRON

CAMDRAM_TYPE:MICRON

TABLE_BOMGROUP_ITEM

A

P A RT N U M B ER 333S0700

QTY 1

A

SYNC_MASTER=J44

DRAM Parts


PAGE TITLE

DE S C R IP T I ON IC,SDRAM,4GBIT,DDR3L-1600,HUMA,96B

FBGA

333S0704

1

IC,SDRAM,4GBIT,DDR3L-1 600,DIE

F,96B FBGA

333S0698

1

IC,SDRAM,4GBIT,DDR3L-1 600,REV

E,96B FBGA

R E F E R EN CE DES U4000

C R IT I C A L C R I T I CA L

CRITICAL

CAMDRAM_TYPE:ELPIDA

CRITICAL

CAMDRAM_TYPE:MICRON

U4000 U 4 00 0

BOM Configuration Configuration

BOM OPTION

DRAWING NUMBER

CAMDRAM_TYPE:HYNIX_H

Apple Inc. R

SIZE

D

REVISION


BRANCH


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Shield Cans 1

1

SH0451

SH0450

SM

SM

SHLD-J44-MLB

SHLD-J44-MLB-T29

USB Cage

D

TBT Cage

D

Mounting Holes & Slots OMIT

ZT0411

4P5R2P3-3P5B 1

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD (998-1195)

OMIT

ZT0413

6.19X4.60-SNOWMAN 1

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK (998-5879)

OMIT

ZT0414

6.19X4.60-SNOWMAN 1

TH0400 TH-NSP 1

SL-1.1X0.5-1.4x0.8

C

TH0403 TH-NSP 1

SL-1.1X0.5-1.4x0.8

TH0404 TH-NSP 1

SL-1.1X0.45-1.4x0.75

TH0405 TH-NSP 1

SL-1.1X0.45-1.4x0.75

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK (998-5879)

Upper TBT can Ground slot (862-0118)

C

Lower TBT can Ground slot (862-0118)

USB can Ground slot (998-3975)

USB can Ground slot (998-3975)

Rubber Mount Standoffs (860-1448) SH0460

2.9OD1.2ID-1.35H-SM

SH0461

2.9OD1.2ID-1.35H-SM

1

1

2

2

B

B SH0462

2.9OD1.2ID-1.35H-SM

SH0465

2.9OD1.2ID-1.35H-SM

1

1

2

2

THERMAL MODULE STANDOFF (860-1645) SH0464

2.9OD1.2ID-1.35H-SM

SH0463

2.9OD1.2ID-1.35H-SM

1

1

2

2

SH0466

2.9OD1.2ID-1.35H-SM

SH0467

SH0420

THERMAL-4.50-J44-SM

1

2

2

THERMAL-4.50-J44-SM

1

SH0426

THERMAL-4.50-J44-SM

2.9OD1.2ID-1.35H-SM

1

SH0421

SSD STANDOFF (806-5375)

FAN STANDOFF (806-5376)

SH0440

SH0441

5.0OD2.0H-SM

STDOFF-4.5OD1.73H-SM-1.33-3.2

1

1

1

SH0427

POGO PINS (870-2451)

THERMAL-4.50-J44-SM

1

SH0435 & SH0436 removed.

1

SH0432

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0433

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM 1

A

RIO FLEX BRACKET BOSSES (860-2354) SH0443

3.5OD2.0H-SM 1

SM 1

A

SYNC_MASTER=J44 PAGE TITLE


PD Parts

SH0444

DRAWING NUMBER

3.5OD2.0H-SM

Apple Inc.

1 R

SIZE

D

REVISION


BRANCH


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CRITICAL OMIT_TABLE

U0500

HASWELL-ULT 2C+GT2 BGA-TSP

DDI Port Assignments:

SYM 1 OF 19

D

74 23

OUT

74 23

OUT

74 23

OUT OUT

74 23

TBT Sink 0

74 23

OUT

74 23

OUT OUT

74 23 74 23

TBT Sink 1 (MUXed with HDMI if necessary)

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

C54

DP_TBTSNK0_ML_C_N<0> DP_TBTSNK0_ML_C_P<0> DP_TBTSNK0_ML_C_N<1> DP_TBTSNK0_ML_C_P<1> DP_TBTSNK0_ML_C_N<2> DP_TBTSNK0_ML_C_P<2> DP_TBTSNK0_ML_C_N<3> DP_TBTSNK0_ML_C_P<3>

C55 B58 C58 B55 A55 A57 B57 C51

=DP_TBTSNK1_ML_C_N<0> =DP_TBTSNK1_ML_C_P<0> =DP_TBTSNK1_ML_C_N<1> =DP_TBTSNK1_ML_C_P<1> =DP_TBTSNK1_ML_C_N<2> =DP_TBTSNK1_ML_C_P<2> =DP_TBTSNK1_ML_C_N<3> =DP_TBTSNK1_ML_C_P<3>

C50 C53 B54 C49 B50 A53 B53

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

eDP Port Assignment: EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

I P D D D E

C45

DP_INT_ML_C_N<0> DP_INT_ML_C_P<0> DP_INT_ML_C_N<1> DP_INT_ML_C_P<1>

B46 A47 B47 C47

DP_INT_ML_C_N<2> DP_INT_ML_C_P<2> DP_INT_ML_C_N<3> DP_INT_ML_C_P<3>

C46 A49 B49

EDP_AUXN EDP_AUXP

A45

EDP_RCOMP EDP_DISP_UTIL

D20

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

B45

OUT

62 74

OUT

62 74

OUT OUT

62 74

D

62 74

OUT

62 74

OUT

62 74

OUT

62 74

OUT

62 74

Internal panel

PPVCOMP_S0_CPU 1

BI

62 74

BI

62 74

24.9

2 70

A43

8

R0530 1% 1/20W MF 201

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

MCP Daisy-Chain Strategy: CRITICAL OMIT_TABLE

Each corner of CPU has two testpoints. Other corner test signals connected in daisy-chain fashion. Continuity should exist between both TP’s on each corner.

U0500

C

HASWELL-ULT 2C+GT2

C

BGA-TSP

NO_TEST 5 5

TP0531

TP

1

TP-P6

5 5

TP0501

TP

1

TP-P6

5 5

MCP_DC_AW2_AY2 MCP_DC_AW3_AY3 MCP_DC_AY60 MCP_DC_AW61_AY61 MCP_DC_AW62_AY62 MCP_DC_B2 MCP_DC_A3_B3 MCP_DC_A61_B61 MCP_DC_B62_B63

TRUE TRUE

AY2 AY3 AY60

TRUE TRUE

AY61 AY62

B2 TRUE TRUE TRUE

B3 B61 B62 B63

MCP_DC_C1_C2

TRUE

C1 C2

SYM 17 OF 19 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A3 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A4 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A60 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A61 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A62 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AV1 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW1 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW2 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW3 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW61 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW62 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW63

NO_TEST TRUE

TRUE

TRUE TRUE TRUE TRUE

MCP_DC_A3_B3 MCP_DC_A4 MCP_DC_A60 MCP_DC_A61_B61 MCP_DC_A62 MCP_DC_AV1 MCP_DC_AW1 MCP_DC_AW2_AY2 MCP_DC_AW3_AY3 MCP_DC_AW61_AY61 MCP_DC_AW62_AY62 MCP_DC_AW63

5

1

TP

TP-P6 1

TP

5

TP-P6 1

TP

TP-P6 1

TP

TP-P6 1 5

TP

TP-P6

TP0500 TP0510 TP0511 TP0520 TP0521

5 5 5

1

TP

TP-P6

TP0530

CRITICAL OMIT_TABLE

U0500

B

BGA-TSP

NC NC NC NC NC NC NC

A

B

HASWELL-ULT 2C+GT2 AT2 AU44 AV44 D15 F22 H22 J21

SYM 18 OF 19 RSVD SPARE RSVD RSVD RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD

N23 R23 T23 U10

RSVD AL1 RSVD AM11 RSVD AP7 RSVD AU10 RSVD AU15 RSVD AW14 RSVD AY14

NC NC NC NC NC NC NC NC NC NC NC

A

SYNC_MASTER=J44


PAGE TITLE

CPU GFX/NCTF/RSVD DRAWING NUMBER

Apple Inc. R

REVISION


BRANCH


PAGE

5 OF 120

SIZE

D

8

7

6

5

4

3

2

1

CRITICAL OMIT_TABLE

D

U0500

D

HASWELL-ULT 2C+GT2 61 60 57 53 37 17 16 15 11 8 68 65

BGA-TSP

PP1V05_S0

NC

R0610

1

62

5% 1/20W MF 201 70 53 37 36

BI

2

CPU_PROCHOT_L

R0611 2

56

OUT

CPU_CATERR_L

K61

CATERR*

70 37

BI

CPU_PECI

N62

PECI

CPU_PROCHOT_R_L

K63

PROCHOT*

70

CPU_PWRGD

70 70

R0650

200

1% 1/20W MF 201

R0651

121

2

1% 1/20W MF 201

R0652

1

100

2

1% 1/20W MF 201

SYM 2 OF 19

R0620

1

66 22

OUT

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

(IPD) (IPU)

MEM_RESET_HSW_L

AU60

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

AV15

SM_DRAMRST*

G A T R J W P

(IPU)

2

E60

PROC_TDI PROC_TDO

F63

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

J60

(IPU) (IPU) (IPU) 3 R D D

(IPU) (IPU)

10K

5% 1/20W MF 201

PROC_TCK PROC_TMS PROC_TRST*

(IPU) 17

OUT

CPU_MEMVTT_PWR_EN_LSVDDQ

AV61

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

K62

XDP_CPU_TCK XDP_CPU_TMS XDP_CPUPCH_TRST_L

E61 E59

OUT IN

16 70 16 70

IN

16 70

IN

16 70

IN

12 16 70

IN

16 70

OUT

16 70

THERMAL

PROCPWRGD

AU61

J62

(IPU)

C S I M

C61

AV60

PRDY* PREQ*

(IPU)

(IPU) 1

70

1

PROC_DETECT*

70 36

5% 1/20W MF 201

1

D61

SM_PG_CNTL1

(IPU) (IPU)

2

XDP_CPU_TDI XDP_CPU_TDO

F62

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

H60 H61 H62 K59 H63 K60 J61

BI

16 70

BI

16 70

BI

16 70

BI BI

16 70

BI

16 70

BI BI

16 70

16 70

16 70

PLACE_NEAR=U0500.AU60:12.7mm PLACE_NEAR=U0500.AV60:12.7mm PLACE_NEAR=U0500.AU61:12.7mm PLACE_NEAR=U0500.C61:12.7mm

C

C

CRITICAL OMIT_TABLE

U0500 HASWELL-ULT 2C+GT2 BGA-TSP

B

70 16 6

BI

70 16 6

BI

70 16

BI

70 16

BI

70 16 6

BI

70 16

BI

70 16

BI

70 16

BI

70 16 6

BI

70 16 6

BI

70 16 6

CFG<10>:SAFE MODE BOOT CFG<9> :NO SVID-CAPABLE VR CFG<8> :ALLOW NOA ON LOCKED UNITS CFG<4> :eDP ENABLE/DISABLE CFG<1> :PCH-LESS MODE CFG<0> :RESET SEQUENCE STALL

1 1 1 1 1 1

= = = = = =

NORMAL OPERATION VR SUPPORTS SVID NORMAL OPERATION DISABLED NORMAL OPERATION NORMAL OPERATION

0 0 0 0 0 0

= = = = = =

POWER FEATURES NOT ACTIVE VR DOES NOT SUPPORT SVID NOA ALWAYS UNLOCKED ENABLED PCH-LESS MODE STALL AFTER PCU PLL LOCK

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

70 16

BI

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

AC60

CPU_CFG<16> CPU_CFG<18> CPU_CFG<17> CPU_CFG<19>

AA62

HSW_PRE_ES2

R0640 1

1

1K

A

NOSTUFF

R0638 1

R0639 1K

5% 1/20W MF 201 2

1K

5% 1/20W MF 2 201

5% 1/20W MF 201 2

AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

U63 AA61 U62

CPU_CFG_RCOMP

NC

These can be placed close to J1800 and are only for debug access

NOSTUFF

AC62

NOSTUFF 1

R0631 1K

5% 1/20W MF 2 201

CPU_CFG<10> CPU_CFG<9> CPU_CFG<8> CPU_CFG<1> CPU_CFG<0> NOSTUFF 1

6 16 70 6 16 70 6 16 70

PCH_TD_IREF

6 16 70 6 16 70

R0630 1K

5% 1/20W MF 2 201

R0680 1

1

49.9 1% 1/20W MF 201

NC NC NC NC

CFG0 (IPU) CFG1 (IPU) CFG2 (IPU) CFG3 (IPU) CFG4 (IPU) CFG5 (IPU) CFG6 (IPU) CFG7 (IPU) CFG8 (IPU) CFG9 (IPU) CFG10 (IPU) CFG11 (IPU) CFG12 (IPU) CFG13 (IPU) CFG14 (IPU) CFG15 (IPU) CFG16 CFG18 CFG17 CFG19

(IPU) (IPU) (IPU)

CFG_RCOMP

A5

RSVD

D1 J20 H18 B12

RSVD_TP AV63 RSVD_TP AU63 RSVD_TP RSVD_TP

C63

EDP_SPARE

B43

RSVD RSVD RSVD RSVD TD_IREF

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63 TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

C62

NC TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

RSVD_TP A51 RSVD_TP B51 RSVD_TP

L60

RSVD

N60

RSVD RSVD

W23 Y22

(IPU)

V63

E1

SYM 19 OF 19 RESERVED

NC NC

PROC_OPI_COMP AY15 RSVD AV62 RSVD D58 VSS VSS

P22

RSVD RSVD

P20

70

NC NC

CPU_OPI_RCOMP 1

R0690 49.9

2

N21

R20

B

TP_MCP_RSVD_L60

NC

1% 1/20W MF 201

NC NC

R0685 8.25K

2

2

1% 1/20W MF 201

A

S YNC _MA ST ER =J 44

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

CPU Misc/JTAG/CFG/RSVD DRAWING NUMBER

CPU_CFG<4> EDP 1

R0634 1K

5% 1/20W MF 2 201

Apple Inc.

6 16 70 R

REVISION


BRANCH


PAGE

6 OF 120

SIZE

D

8

7

6

5

4

3

CRITICAL OMIT_TABLE 73 68 67 73 68 67

BI

73 68 67

BI

73 68 67 73 68 67 73 68 67 73 68 67

D

73 68 67

BI BI BI

73 68 67

BI BI

73 68 67

BI

73 68 67

BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67 73 68 67

BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI BI

73 68 67 73 68 67

BI

73 68 67

BI BI

73 68 67 20 73 68 67 73 68 67 73 68 67 73 68 67 73 68 67

BI BI BI BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI BI

73 68 67 73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67 73 68 67 73 68 67 73 68 67 73 68 67 73 68 67

BI BI BI BI BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

A

BI

BI

73 68 67

B

BI

73 68 67

73 68 67

C

BI

BI

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

2

1

CRITICAL OMIT_TABLE

U0500

SA_CLK0* AU37 SA_CLK0 AV37 SA_CLK1* AW36 SA_CLK1 AY36


SYM 3 OF 19

MEM_A_CLK_N<0> MEM_A_CLK_P<0> NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1>

73 68 67

20 22 73

OUT

20 22 73

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67 73 68 67

AU43

SA_CKE0 SA_CKE1 AW43 SA_CKE2 AY42 SA_CKE3 AY43

A L E N N A H C Y R O M E M

MEM_A_CKE<0> NC_MEM_A_CKE1 MEM_A_CKE<2> NC_MEM_A_CKE<3>

CAB2 CAB1

CAB6 CAA5

CAB9 CAB8 CAB5 RSVD1 RSVD2 CAA0 CAA2 CAA4 CAA3 CAA1 CAB7 CAA7 CAA6 CAB0 CAA9 CAA8

BI

20 22 73

OUT OUT

22

73 68 67

66

73 68 67

OUT

66

73 68 67

BI

73 68 67

BI BI

73 68 67

BI BI BI

SA_CS0* AP33 SA_CS1* AR32

MEM_A_CS_L<0> NC_MEM_A_CS_L1

OUT

20 22 73

73 68 67

OUT

22

73 68 67

BI

73 68 67

SA_ODT0 AP32

MEM_A_ODT_CPU0

OUT

22 66

BI BI

73 68 67

SA_RAS* AY34 SA_WE* AW34 SA_CAS* AU34

BI

MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L

OUT

20 22 66 73

73 68 67

BI

OUT

20 22 66 73

73 68 67

BI

OUT

20 22 66 73

73 68 67

BI

73 68 67

73 68 67

CAB4

BI

OUT

LPDDR3 CAB3

BI

OUT

SA_BA0 AU35 SA_BA1 AV35 SA_BA2 AY41 SA_MA0 AU36 SA_MA1 AY37 SA_MA2 AR38 SA_MA3 AP36 SA_MA4 AU39 SA_MA5 AR36 SA_MA6 AV40 SA_MA7 AW39 SA_MA8 AY39 SA_MA9 AU40 SA_MA10 AP35 SA_MA11 AW41 SA_MA12 AU41 SA_MA13 AR35 SA_MA14 AV42 SA_MA15 AU42 SA_DQSN0 AJ61 SA_DQSN1 AN62 SA_DQSN2 AM58 SA_DQSN3 AM55 SA_DQSN4 AV57 SA_DQSN5 AV53 SA_DQSN6 AL43 SA_DQSN7 AL48

=MEM_A_BA<0> MEM_A_BA<1> =MEM_A_BA<2> =MEM_A_A<0> =MEM_A_A<1> =MEM_A_A<2> =MEM_A_A<3> =MEM_A_A<4> =MEM_A_A<5> MEM_A_A<6> =MEM_A_A<7> =MEM_A_A<8> =MEM_A_A<9> =MEM_A_A<10> =MEM_A_A<11> =MEM_A_A<12> =MEM_A_A<13> =MEM_A_A<14> NC_MEM_A_A15 MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

OUT OUT

20 22 66 73

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

OUT

66

OUT

66

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

OUT

20 22 66 73

73 68 67

BI BI

OUT

66

73 68 67

BI

OUT

66

73 68 67

OUT

66

73 68 67 21

BI BI

OUT

66

73 68 67

OUT

66

73 68 67

OUT

66

73 68 67

OUT

66

73 68 67

OUT

66

73 68 67

OUT

22

73 68 67

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

BI

73 68 67

BI

73 68 67

BI BI BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

67 73 67 73

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

BI

20 67 73

73 68 67

BI

BI

67 73

73 68 67

BI BI

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

BI

67 73

73 68 67

BI

67 73

73 68 67

BI

20 67 73

73 68 67

BI

67 73

73 68 67

SM_VREF_CA AP49

CPU_DIMM_VREFCA

OUT

19 73

SM_VREF_DQ0 AR51

CPU_DIMMA_VREFDQ

OUT

19 73

OUT

19 73

CPU_DIMMB_VREFDQ

BI

BI

73 68 67

SM_VREF_DQ1

BI

BI

73 68 67

AP51

BI

73 68 67

73 68 67

SA_DQSP0 AJ62 SA_DQSP1 AN61 SA_DQSP2 AN58 SA_DQSP3 AN55 SA_DQSP4 AW57 SA_DQSP5 AW53 SA_DQSP6 AL42 SA_DQSP7 AL49

BI

66

BI BI BI BI BI BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

73 68 67

BI

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63


SYM 4 OF 19 B L E N N A H C Y R O M E M

SB_CK0* AM38 SB_CK0 AN38 SB_CK1* AK38 SB_CK1 AL38

MEM_B_CLK_N<0> MEM_B_CLK_P<0> NC_MEM_B_CLKN<1> NC_MEM_B_CLKP<1>

OUT

21 22 73

OUT

21 22 73

OUT

66

OUT

66

OUT

21 22 73

OUT OUT

22

OUT

66

MEM_B_CS_L<0> NC_MEM_B_CS_L1

OUT

21 22 73

OUT

22

OUT

22 66

OUT

21 22 66 73

OUT

21 22 66 73

OUT

21 22 66 73

OUT

66

OUT

21 22 66 73

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

21 22 66 73

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

66

OUT

22

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

AY49

SB_CS0* SB_CS1*

AM32

SB_ODT0

AL32

MEM_B_ODT_CPU0

SB_RAS* SB_WE* SB_CAS*

AM35

MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L

SB_BA0 SB_BA1 SB_BA2

AL35

AU50 AW49 AV50

AK32

MEM_B_CKE<0> NC_MEM_B_CKE1 MEM_B_CKE<2> NC_MEM_B_CKE<3>

D

66

LPDDR3 CAB3 CAB2 CAB1

CAB4 CAB6

CAA5

CAB9 CAB8 CAB5 RSVD3 RSVD4 CAA0 CAA2 CAA4 CAA3 CAA1 CAB7 CAA7 CAA6 CAB0 CAA9 CAA8

AK35 AM33

AM36 AU49

SB_MA0 AP40 SB_MA1 AR40 SB_MA2 AP42 SB_MA3 AR42 SB_MA4 AR45 SB_MA5 AP45 SB_MA6 AW46 SB_MA7 AY46 SB_MA8 AY47 SB_MA9 AU46 SB_MA10 AK36 SB_MA11 AV47 SB_MA12 AU47 SB_MA13 AK33 SB_MA14 AR46 SB_MA15 AP46 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

AW30

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AV30

AV26 AN28 AN25 AW22 AV18 AN21 AN18

AW26 AM28 AM25 AV22 AW18 AM21 AM18

=MEM_B_BA<0> MEM_B_BA<1> =MEM_B_BA<2> =MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> =MEM_B_A<3> =MEM_B_A<4> =MEM_B_A<5> MEM_B_A<6> =MEM_B_A<7> =MEM_B_A<8> =MEM_B_A<9> =MEM_B_A<10> =MEM_B_A<11> =MEM_B_A<12> =MEM_B_A<13> =MEM_B_A<14> NC_MEM_B_A15 MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7> MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

21 67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

67 73

BI

21 67 73

BI

67 73

C

B

A

SYNC_MASTER=J44


PAGE TITLE

CPU DDR3/LPDDR3 Interfaces DRAWING NUMBER

Apple Inc. R

REVISION


BRANCH


PAGE

7 OF 120

SIZE

D

8

7

6

5

4

3

2

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9. LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

CRITICAL OMIT_TABLE

PP1V35_S3_CPUDDR 1.4A Max (DDR3: 1.5-1.35V) 1.1A Max (LPDDR3: 1.2V)

73 65 41 10

NC NC

L59 J58

AH26 AJ31

AJ37 AN33

D

AP43 AR48 AY35 68 65 54 42 10 8

AY40

PPVCC_S0_CPU

AY44 AY50

R0860 1 PLACE_NEAR=U0500.C50:50.8mm 60 57 53 37 17 16 15 11 8 6 68 65 61

R0800 1

1

1% 1/20W MF 201

IN

2

CPU_VIDALERT_L

R0810 1

OUT

CPU_VIDSCLK

1

0

BI

2

2

CPU_VCCSENSE_P TP_PPVCCIO_S0_CPU

5

Max load: 300mA

NC

PPVCOMP_S0_CPU MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

70

CPU_VIDSOUT

70 70

R0812 1

0

R0802.2: R0810.2:

2

R0800.2:

5% 1/20W MF 0201

C

PLACE_NEAR=U0500.L63:2.54mm

70 17 16

PLACE_NEAR=U0500.L62:38.1mm

53 17

PLACE_NEAR=R0810.1:2.54mm

53 17

IN OUT IN

IN

L10

1838mA Max

M9

57 53 37 17 16 15 11 8 6 68 65 61 60

14 11

B

12 11

11

PP1V05_S0

N8

29mA Max[1]

P9

B18

PP1V05_S0SW_PCH_VCCUSB3PLL 41mA Max PP1V05_S0SW_PCH_VCCSATA3PLL 42mA Max WF: RSVD on Sawtooth Peak rev 1.0 PP1V05_S0_PCH_VCCAPLL_OPI

NC

NC 60 17 11

I P O

DCPSUS3

3 B S U

AA21

J13

77 68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30

11

PP3V3_SUS

AC9

59mA Max[1]

AA9

AH10

PP3V3_S5 114mA Max PP3V3_S0

V8 W9

40mA Max[1]

J18

PP1V05_S0_PCH_VCC_ICC

K19

VCCCLK: 200mA Max

A

12 11

57 53 37 17 16 15 11 8 6 68 65 61 60

AH13

VCC1P05 J11 VCC1P05 H11 VCC1P05 H15 VCC1P05 AE8 VCC1P05 AF22

A20

PP1V05_S0_PCH_VCCACLKPLL 31mA Max PP1V05_S0 VCCCLK: 200mA Max

J17 R21 T21

WF: RSVD on Sawtooth Peak rev 1.0

65 61 60 59 45 14 11 8

PP3V3_SUS 3.3mA Max[1]

DCPSUSBYP AG19 DCPSUSBYP AG20

NC NC NC

K18 M20 V21

AE20 AE21

VRM/USB2/AZALIA DCPSUS2

VCCDSW3_3 VCC3 VCC3

C C L / O I P G

VCCASW AE9 VCCASW AF9 VCCASW AG8 DCPSUS1 AD10 DCPSUS1 AD8

THERMAL SENSOR VCCTS1_5 VCC3 VCC3

VCC1P05 VCC1P05 VCCACLKPLL VCCCLK VCCCLK VCCCLK VCCCLK VCCCLK VCCCLK VCCSUS3 VCCSUS3

Y8

VCCASW VCCASW AG13

AZALIA/HDA E R VCCHDA O

VCCSUS3 VCCSUS3

8 11 14 45 59 60 61 65

PPVRTC_G3H

J15

K14

AA23 AE59

N63 L63 B59 F60 C59

H59

12 13 17 65

P60 P61 N59 N61

NC NC NC NC NC NC NC NC NC

T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59

AC22 AE22 AE23

BYPASS=U0500.AE7:6.35mm

PPVOUT_S0_PCH_DCPRTC MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP3V3_SUS

8 11 14 45 59 60 61 65

C0891 1

0.1UF

0.1UF

0.1UF

PP1V05_S0 185mA Max[1]

6 8 11 15 16 17 37 53 57 60 61 65 68

PP1V05_S0

6 8 11 15 16 17 37 53 57 60 65 68

20% 10V CERM 402

2

20% 10V CERM 402

2

1499mA Max[1]

C0892 1 C0895

1

18mA Max

C

NC

56 29 27 26 18 17 16 15 13 11 77 68 65 61 60 59

VCCSPI

AG14

11mA Max

65 61 60 59 45 14 11 8

DCPRTC AE7

O I I P S S H

VCCAPLL VCCAPLL VCCAPLL

AH14

PP1V5_S0SW_AUDIO_HDA

C T R

Y20

PP3V3_SUS

PP1V05_S0 ???mA Max

VCCRTC AG10

SYM 13 OF 19

VCCSATA3PLL

60 57 53 37 17 16 15 11 8 6 68 65 61

0.3mA Max[1]

BGA-TSP

B11

W21

57mA Max

HASWELL-ULT 2C+GT2

VCCIO VCCIO VCCUSB3PLL

VCCSUS3 AH11

AD23

L62

CPU_VIDALERT_R_L CPU_VIDSCLK_R CPU_VIDSOUT_R CPU_VCCST_PWRGD CPU_VR_EN CPU_VR_READY

TP_CPU_RSVD_P60 TP_CPU_RSVDP61 TP_CPU_RSVD_N59 TP_CPU_RSVDN61

CRITICAL OMIT_TABLE

U0500

A59

P62

18

VCCHSIO VCCHSIO VCCHSIO

NC NC NC

CPU_PWR_DEBUG

18

K9

AB23

D63 16

PP1V05_S0SW_PCH_HSIO

AC58

E20

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

2

N58

E63

2

5% 1/20W MF 0201 70 53

43

1% 1/20W MF 201

NC NC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

Max load: 300mA

5% 1/20W MF 201

R0811 70 53

R0802

OUT

130

75

70 53

5% 1/20W MF 201

PP1V05_S0 70 53

F59

100

20% 10V CERM 402

2

1

C0890

AB57

1UF

2

AD57

10% 6.3V CERM 402

AG57 C24

BYPASS=U0500.AG10:6.35mm BYPASS=U0500.AG10:6.35mm BYPASS=U0500.AG10:6.35mm

U0500

RSVD RSVD


AJ33

65 60 11

1

C28 C32

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

SYM 12 OF 19 HSW ULT POWER

VCC RSVD RSVD VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD VIDALERT* VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY VSS PWR_DEBUG* VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCST VCCST VCCST VCC VCC VCC VCC VCC VCC

PPVCC_S0_CPU VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36

8 10 42 54 65 68

32A Max

C40 C44 C48 C52 C56 E23 E25

D

E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23

C

G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

B

61

PLACE_NEAR=U0500.AG19:2.54mm

R0899 PPVOUT_S5_PCH_DCPSUSBYP_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1

Powered in DeepSx

PP1V05_S0 473mA Max[1]

5.11 1% 1/20W MF-LF 201

6 8 11 15 16 17 37 53 57 60 65 68

2

PPVOUT_S5_PCH_DCPSUSBYP MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1

C0899 1UF

61

2

10% 6.3V CERM 402

BYPASS=R0899:U0500:2.54mm

NC NC PP1V5_S0 3mA Max PP3V3_S0

K16

1mA Max[1]

U8

PP3V3_S0

T9

17mA Max

47 59 60 61 63 65 68

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

SERIAL IO VCCSDIO VCCSDIO C C SUS I

OSCILLATOR DCPSUS4 AB8

2 B S U

LPT LP POWER

VCCAPLL AC20 VCCIO AG16 VCCIO AG17

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

CPU/PCH POWER DRAWING NUMBER

NC

Apple Inc. R

NC WF: RSVD on Sawtooth Peak rev 1.0 PP1V05_S0 213mA Max[1]

6 8 11 15 16 17 37 53 57 60 65 68

61

REVISION


BRANCH


PAGE

8 OF 120

SIZE

D

8

7

6

5

4

CRITICAL OMIT_TABLE

CRITICAL OMIT_TABLE

U0500

U0500

HASWELL-ULT 2C+GT2

HASWELL-ULT 2C+GT2

BGA-TSP

A18 A24

D

A28 A32 A36 A40 A44 A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17

C

AF18 AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55

B

AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

A

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS AJ35 VSS AJ39 VSS AJ41 VSS AJ43 VSS AJ45 VSS AJ47 VSS AJ50 VSS AJ52 VSS AJ54 VSS AJ56 VSS AJ58 VSS AJ60 VSS AJ63 VSS AK23 VSS AK3 VSS AK52 VSS AL10 VSS AL13 VSS AL17 VSS AL20 VSS AL22 VSS AL23 VSS AL26 VSS AL29 VSS AL31 VSS AL33 VSS AL36 VSS AL39 VSS AL40 VSS AL45 VSS AL46 VSS AL51 VSS AL52 VSS AL54 VSS AL57 VSS AL60 VSS AL61 VSS AM1 VSS AM17 VSS AM23 VSS AM31 VSS AM52 VSS AN17 VSS AN23 VSS AN31 VSS AN32 VSS AN35 VSS AN36 VSS AN39 VSS AN40 VSS AN42 VSS AN43 VSS AN45 VSS AN46 VSS AN48 VSS AN49 VSS AN51 VSS AN52 VSS AN60 VSS AN63 VSS AN7 VSS AP10 VSS AP17 VSS AP20

AP22 AP23 AP26 AP29 AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49 AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63 AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

SYM 15 OF 19 VSS VSS AV59 VSS VSS AV8 VSS VSS AW16 VSS VSS AW24 VSS VSS AW33 VSS VSS AW35 VSS VSS AW37 VSS VSS AW4 VSS VSS AW40 VSS VSS AW42 VSS VSS AW44 VSS VSS AW47 VSS VSS AW50 VSS VSS AW51 VSS VSS AW59 VSS VSS AW60 VSS VSS AY11 VSS VSS AY16 VSS VSS AY18 VSS VSS AY22 VSS VSS AY24 VSS VSS AY26 VSS VSS AY30 VSS VSS AY33 VSS VSS AY4 VSS VSS AY51 VSS VSS AY53 VSS VSS AY57 VSS VSS AY59 VSS VSS AY6 VSS VSS B20 VSS VSS B24 VSS VSS B26 VSS VSS B28 VSS VSS B32 VSS VSS B36 VSS VSS B4 VSS VSS B40 VSS VSS B44 VSS VSS B48 VSS VSS B52 VSS VSS B56 VSS VSS B60 VSS VSS C11 VSS VSS C14 VSS VSS C18 VSS VSS C20 VSS VSS C25 VSS VSS C27 VSS VSS C38 VSS VSS C39 VSS VSS C57 VSS VSS D12 VSS VSS D14 VSS VSS D18 VSS VSS D2 VSS VSS D21 VSS VSS D23 VSS VSS D25 VSS VSS D26 VSS VSS D27 VSS VSS D29 VSS VSS D30 VSS VSS D31

1

CRITICAL OMIT_TABLE

U0500 BGA-TSP

A14

2

HASWELL-ULT 2C+GT2 SYM 14 OF 19 A11

3

BGA-TSP

SYM 16 OF 19 D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

G3 G5 G6 G8 H13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_SENSE VSS

H17 H57 J10 J22

D

J59 J63

K1 K12 L13 L15 L17 L18 L20 L58 L61

L7 M22 N10

N3 P59 P63 R10 R22

R8 T1 T58 U20 U22 U61

U9 V10

C

V3 V7 W20 W22 Y10 Y59 Y63 V58 AH46 V23

CPU_VCCSENSE_N

E62 AH16 1

100

2

OUT

53 70

R0960 5% 1/20W MF 201

PLACE_NEAR=U0500.E62:50.8mm

B

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

CPU/PCH GROUNDS DRAWING NUMBER

Apple Inc. R

REVISION


BRANCH


PAGE

9 OF 120

SIZE

D

8

7

6

5

4

3

2

1

All Intel recommenda tions from Intel doc # 503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

CPU VCC Decoupling 68 65 54 42 8

PPVCC_S0_CPU

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff CRITICAL 1

CRITICAL

C1000

1

10UF 2

D

CRITICAL

C1001

1

10UF

20% 4V X6S 0402

2

CRITICAL

C1002

1

10UF

20% 4V X6S 0402

2

2

NO STUFF

NO STUFF

CRITICAL

C1003

1

10UF

20% 4V X6S 0402

2

NO STUFF

CRITICAL 1

CRITICAL

C1070

1

10UF 2

1

2

C1085

2

20% 4V X6S 0402

CRITICAL 1

10UF

NO STUFF

1

1

2

NO STUFF 1

1

2

NO STUFF 1

1

2

1

10UF 2

1

2

2

1

2

1

2

1

1

2

2

1

2

CRITICAL 1

C1009

CRITICAL 1

10UF 2

20% 4V X6S 0402

2

1

2

1

1

2

2

1

1

2

2

C1063 20% 4V X6S 0402

1

C108A

2

20% 4V X6S 0402

CRITICAL 1

C1081 20% 4V X6S 0402

CRITICAL

C1093

CRITICAL 1

10UF 2

20% 4V X6S 0402

NO STUFF

C1032 20% 4V X6S 0402

CRITICAL 1

C1033 20% 4V X6S 0402

20% 4V X6S 0402

CRITICAL 1

C1034 20% 4V X6S 0402

C1035 20% 4V X6S 0402

20% 4V X6S 0402

CRITICAL 1

CRITICAL

C105C

C105D

1

10UF 2

NO STUFF

20% 4V X6S 0402

2

CRITICAL

2

20% 4V X6S 0402

2

10UF

C1083

CRITICAL 1

C105F 10UF

2

NO STUFF

20% 4V X6S 0402

D

10UF

20% 4V X6S 0402

20% 4V X6S 0402

2

NO STUFF

CRITICAL 1

10UF 20% 4V X6S 0402

20% 4V X6S 0402

C106E

1

10UF

CRITICAL

2

C105E 10UF

2

CRITICAL

C106D

NO STUFF

1

CRITICAL 1

10UF

20% 4V X6S 0402

C1084 10UF

2

NO STUFF

20% 4V X6S 0402

NO STUFF

C1097 10UF

2

20% 4V X6S 0402

NO STUFF

NO STUFF 1

10UF 2

C105B 10UF

2

CRITICAL 1

NO STUFF 1

10UF 2

20% 4V X6S 0402

NO STUFF

CRITICAL 1

C1096 10UF

2

NO STUFF

10UF 2

C1095 10UF

2

NO STUFF 1

10UF 2

20% 4V X6S 0402

NO STUFF

NO STUFF 1

C1094 10UF

2

20% 4V X6S 0402

CRITICAL 1

1

NO STUFF

NO STUFF

1

C1082

20% 4V X6S 0402

C104F

10UF 2

C105A 10UF

2

CRITICAL

CRITICAL 1

10UF 2

10UF 20% 4V X6S 0402

20% 4V X6S 0402

CRITICAL 1

1

NO STUFF

20% 4V X6S 0402

C1029

C104E 10UF

NO STUFF

2

C1036

NO STUFF 1

C1037

2

20% 4V X6S 0402

10UF 2

20% 4V X6S 0402

NO STUFF 1

10UF

C

C1038 10UF

2

20% 4V X6S 0402

C1049 20% 4V X6S 0402

NO STUFF 1

C1064

CRITICAL 1

10UF 2

20% 4V X6S 0402

C108B

2

20% 4V X6S 0402

NO STUFF 1

C108C

2

20% 4V X6S 0402

NO STUFF 1

C108D

2

20% 4V X6S 0402

NO STUFF 1

C108E

2

20% 4V X6S 0402

NO STUFF 1

C108F

2

20% 4V X6S 0402

NO STUFF 1

C107A

2

20% 4V X6S 0402

NO STUFF 1

C1099

NO STUFF 1

10UF 2

20% 4V X6S 0402

C109A 10UF

2

20% 4V X6S 0402

NO STUFF 1

10UF 20% 4V X6S 0402

C1098 10UF

2

NO STUFF 1

10UF 20% 4V X6S 0402

C1069 10UF

2

NO STUFF 1

10UF 20% 4V X6S 0402

C1068 10UF

2

NO STUFF 1

10UF 20% 4V X6S 0402

C1067 10UF

2

NO STUFF 1

10UF 20% 4V X6S 0402

C1066 10UF

2

NO STUFF 1

10UF 20% 4V X6S 0402

C1065 10UF

2

NO STUFF 1

10UF

20% 4V X6S 0402

NO STUFF

2

NO STUFF

1

20% 4V X6S 0402

10UF 2

NO STUFF

C109F

20% 4V X6S 0402

C1014 10UF

2

CRITICAL

C1077

20% 4V X6S 0402

1

20% 4V X6S 0402

NO STUFF

20% 4V X6S

C1092

CRITICAL

C1012 10UF

2

NO STUFF 1

10UF

20% 4V X6S 0402

10UF

20% 4V X6S 0402

20% 4V X6S 0402

NO STUFF

C1062

NO STUFF

C109E

C1048

C1028

CRITICAL 1

1

10UF 2

10UF 2

20% 4V X6S 0402

C1030

CRITICAL 1

NO STUFF 1

10UF

20% 4V X6S 0402

10UF

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

NO STUFF

NO STUFF

C1047

NO STUFF

C1059

C1027

C1091 10UF

10UF 2

10UF

20% 4V X6S 0402

CRITICAL

2

NO STUFF 1

20% 4V X6S 0402

NO STUFF

NO STUFF

1

C1011 10UF

2

10UF 2

NO STUFF

C1026

CRITICAL 1

10UF

1

20% 4V X6S 0402

20% 4V X6S 0402

20% 4V X6S 0402

CRITICAL

C1075

C1090

C1010 10UF

2

0402 NO STUFF

NO STUFF

10UF

20% 4V X6S 0402

NO STUFF

C1046

10UF

20% 4V X6S 0402

20% 4V X6S 0402

10UF

2

CRITICAL

C1089

10UF

20% 4V X6S 0402

NO STUFF

C109D 10UF

20% 4V X6S 0402

20% 4V X6S 0402

1

10UF 2

CRITICAL

C1025

10UF

20% 4V X6S 0402

NO STUFF

C109C 10UF

20% 4V X6S 0402

1

20% 4V X6S 0402

NO STUFF

NO STUFF

C1058

20% 4V X6S 0402

CRITICAL

C1021

CRITICAL

C1074

10UF 2

10UF 2

10UF

20% 4V X6S 0402

NO STUFF

C109B

1

20% 4V X6S 0402

NO STUFF

C1057

1

20% 4V X6S 0402

NO STUFF

C1045

CRITICAL 1

10UF

CRITICAL

C1088

10UF 2

10UF 2

10UF

20% 4V X6S 0402

NO STUFF 1

1

20% 4V X6S 0402

NO STUFF

C1056 10UF

2

1

20% 4V X6S 0402

C1020

NO STUFF

NO STUFF

C1024

NO STUFF

C1044 10UF

20% 4V X6S 0402

2

10UF 2

NO STUFF

10UF 2

NO STUFF

C1039 10UF

2

1

20% 4V X6S 0402

1

20% 4V X6S 0402

10UF 2

NO STUFF

C1023 10UF

20% 4V X6S 0402

1

20% 4V X6S 0402

NO STUFF

NO STUFF

C1022 10UF

2

20% 4V X6S 0402

CRITICAL

C1073

CRITICAL

C1087 10UF

2

NO STUFF

CRITICAL

C

1

20% 4V X6S 0402

1

NO STUFF

CRITICAL

C1086 10UF

2

2

10UF 2

NO STUFF

CRITICAL 1

1

20% 4V X6S 0402

CRITICAL

C1019 10UF

20% 4V X6S 0402

CRITICAL

C1072 10UF

20% 4V X6S 0402

C1008 10UF

2

CRITICAL

C1018 10UF

2

1

20% 4V X6S 0402

NO STUFF

CRITICAL 1

CRITICAL

C1004 10UF

20% 4V X6S 0402

C107B 10UF

2

20% 4V X6S 0402

B

B CRITICAL 1

C1031

470UF-0.0045OHM

3

2

20% 2.5V POLY-TANT SM

CPU VDDQ DECOUPLING 73 65 41 8

PP1V35_S3_CPUDDR

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603 Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

1

C1040

1

2.2UF 2

1

20% 6.3V CERM 402-LF

2

C1050 20% 6.3V CERM-X5R 0402-1

1

2.2UF 2

1

10UF

A

C1041

C1051

2

1

10UF 2

20% 6.3V CERM-X5R 0402-1

C1042

1

2.2UF

20% 6.3V CERM 402-LF

C1052

2

1

10UF 2

20% 6.3V CERM-X5R 0402-1

CPU VCC Decoupling

C1043 2.2UF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

C1053

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

1

10UF 2

20% 6.3V CERM-X5R 0402-1

C1054

1

10UF 2

20% 6.3V CERM-X5R 0402-1

C1055 10UF

2

20% 6.3V CERM-X5R 0402-1

A

SYNC_MASTER=J44


PAGE TITLE

CPU Decoupling DRAWING NUMBER

Apple Inc.

NO STUFF 1

C1060

1

270UF

2

20% 2V TANT CASE-B2-SM

C1061 270UF

2

20% 2V TANT CASE-B2-SM

R

1x Bulk nostuff, Harris Beach has 2x nostuff

REVISION


BRANCH


PAGE

10 OF 120

SIZE

D

8

7

56 29 27 26 18 17 16 15 13 8 77 68 65 61 60 59

6

PCH VCCDSW3_3 BYPASS (PCH 3.3V DSW PWR) PP3V3_S5 NO STUFF

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

5

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR) PP3V3_S0

65 61 60 59 45 14 11 8

60 57 53 37 17 16 15 11 8 6 68 65 61

C1200 1

C1212 1

10% 6.3V CERM 2 402

20% 6.3V X5R-CERM-1 2 603

BYPASS=U0500.AH10:6.35mm

BYPASS=U0500.V8:12.7mm

PCH VCCSPI BYPASS (PCH 3.3V SPI PWR) PP3V3_SUS NO STUFF

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

PCH VCCIO BYPASS (PCH 1.05V USB2 PWR) PP1V05_S0

C1251

C1264 1

1UF

2

2

1UF

10% 6.3V CERM 402

10% 6.3V CERM 402

60 57 53 37 17 16 15 11 8 6 68 65 61

2

BYPASS=U0500.AG16:6.35mm

BYPASS=U0500.AE9:12.7mm BYPASS=U0500.AE9:6.35mm

C1214 1

0.1UF

1

22UF

20% 6.3V X5R-CERM-1 603

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR) PP3V3_S0

PCH VCC BYPASS (PCH 1.05V CORE PWR) PP1V05_S0

60 57 53 37 17 16 15 11 8 6 68 65 61

D

PCH VCCCLK BYPASS (PCH 1.05V CLK PWR) PP1V05_S0

0.1UF

20% 10V CERM 2 402

20% 10V CERM 2 402

BYPASS=U0500.Y8:6.35mm

C1255 1

1

10UF

20% 6.3V X5R 603

BYPASS=U0500.K14:6.35mm

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR) PP3V3_SUS

C1256

1

1UF

2

2

C1257

C1266 1

1UF

10% 6.3V CERM 402

1UF

10% 6.3V CERM 402

2

10% 6.3V CERM 2 402

BYPASS=U0500.J11:12.7mm BYPASS=U0500.J11:6.35mm BYPASS=U0500.AE8:6.35mm

C1204 1 22UF

65 60 11 8

20% 6.3V X5R-CERM-1 2 603

C1267 1 1UF

10% 6.3V CERM 402

2

BYPASS=U0500.J17:6.35mm BYPASS=U0500.R21:6.35mm

PCH VCCHSIO BYPASS (PCH 1.05V PCIe/SATA/USB3 PWR) PP1V05_S0SW_PCH_HSIO

BYPASS=U0500.AC9:12.7mm

C1260 1

C1261 1

1UF

65 61 60 59 45 14 11 8

2

60 57 53 37 17 16 15 11 8 6 68 65 61

C1250 1

22UF

C1202 1

65 61 60 59 45 14 11 8

3

NO STUFF

1UF

D

4 PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR) PP1V05_S0

10% 6.3V CERM 402

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND RTC PWR) PP3V3_SUS

1

1UF

10% 6.3V CERM 402

2

C1262 10UF

2

20% 6.3V CERM-X5R 0402-1

2

BYPASS=U0500.K9:6.35mm BYPASS=U0500.L10:6.35mm BYPASS=U0500.M9:6.35mm

C1206 1 1UF

10% 6.3V CERM 2 402

C


C

CRITICAL PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR) 50 PP3V3_S0 8

60 57 53 37 17 16 15 11 8 6 68 65 61

77 68 65 64 62 61 30 28 24 18 17 15 13 12 11 47 46 44 43 42 41 40 39 38 37

PP1V05_S0 ??mA Max

1

0

2.2UH-240MA-0.221OHM

2

PP1V05_S0_PCH_VCCACLKPLL_R

1

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

5%

1/16W MF-LF 402

C1208 1


2 0603

C1270 1

C1271 1

47UF

47UF

1UF

20% 4V CERM-X5R 0805-1

10% 6.3V CERM 2 402

2

20% 4V CERM-X5R 0805-1

1

8 12

31mA Max

C1272 1UF

2

2

10% 10V X5R 402

BYPASS=U0500.A20:12.7mm BYPASS=U0500.A20:12.7mm BYPASS=U0500.A20:6.35mm

BYPASS=U0500.U8:6.35mm

60 17 8

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR) PP1V05_S0_PCH_VCCACLKPLL

L1270

R1270

CRITICAL

PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR) PP1V5_S0SW_AUDIO_HDA

0

2.2UH-240MA-0.221OHM

2

1/16W MF-LF 402

1UF

10% 6.3V CERM 2 402

PP1V05_S0_PCH_VCC_ICC_R

1


5%

C1210 1

1

0

0603

C1275 1 47UF

20% 4V CERM-X5R 0805-1

C1276 1

1

1UF

47UF

2

20% 4V CERM-X5R 0805-1

8

??mA Max

C1277

2

2

10% 10V X5R 402

BYPASS=U0500.J18:12.7mm BYPASS=U0500.J18:12.7mm BYPASS=U0500.J18:6.35mm

2

5% 1/16W MF-LF 402

B


2

R1280


PCH VCCCLK FILTER/BYPASS (PCH 1.05V VCCCLK PWR) PP1V05_S0_PCH_VCC_ICC

L1275

R1275 1

CRITICAL NO STUFF

1

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.07 5 MM VOLTAGE=1.05V

2 0603

NO STUFF

8

57mA Max

NO STUFF

C1280 1 47UF

20% 4V CERM-X5R 0805-1

B

PCH OPI VCCAPLL FILTER/BYPASS (PCH 1.05V OPI PLL PWR) PP1V05_S0_PCH_VCCAPLL_OPI

L1280

2.2UH-240MA-0.221OHM

C1281 1

1

20% 4V CERM-X5R 0805-1

2

C1282 1UF

47UF

2

2

10% 10V X5R 402

BYPASS=U0500.AA21:12.7mm BYPASS=U0500.AA21:12.7mm BYPASS=U0500.AA21:6.35mm

CRITICAL

PCH VCCSATA3PLL FILTER/BYPASS (PCH 1.05V SATA3 PLL PWR) PP1V05_S0SW_PCH_VCCSATA3PLL

L1290

65 60 11 8

PP1V05_S0SW_PCH_HSIO 83mA Max

2.2UH-240MA-0.221OHM 1

2

NO STUFF

0603

C1290 1 47UF

20% 4V CERM-X5R 0805-1

C1291 1


1

1UF

47UF

2

20% 4V CERM-X5R 0805-1

2

8 12

42mA Max

C1292

2

10% 10V X5R 402

BYPASS=U0500.B11:12.7mm BYPASS=U0500.B11:12.7mm BYPASS=U0500.B11:6.35mm

A

CRITICAL

PCH VCCUSB3PLL FILTER/BYPASS (PCH 1.05V USB3 PLL PWR) PP1V05_S0SW_PCH_VCCUSB3PLL

L1295

2.2UH-240MA-0.221OHM 1

2 0603

C1295 1 47UF

20% 4V CERM-X5R 0805-1

NO STUFF

C1296 1


1

20% 4V CERM-X5R 0805-1

BYPASS=U0500.B18:12.7mm BYPASS=U0500.B18:12.7mm

2

C1297 1UF

47UF

2

2

10% 10V X5R 402

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

PCH Decoupling

8 14

41mA Max

DRAWING NUMBER

Apple Inc. R

REVISION


BRANCH


PAGE

12 OF 120

SIZE

D

8 65 17 13 8

7

6

5

4

3

2

1

PPVRTC_G3H

R1300

1

1

20K

R1302

R1301 1M

1/20W

MF

201

72

D 1

1UF

C1303 1UF

10% 10V X5R 2 402

2

AW5

PCH_CLK32K_RTCX1 NC_RTC_CLK32K_RTCX2

IN OUT

AY5

U0500

RTCX1 RTCX2


SYM 5 OF 19

PCH_INTRUDER_L

AU6

INTRUDER*

PCH_INTVRMEN

AV7

INTVRMEN

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 C T R

72

PCH_SRTCRST_L

AV6

SRTCRST*

72

RTC_RESET_L

AU7

RTCRST*

AW8

HDA_BCLK/I2S0_SCLK

R1310

33

OUT

HDA_BIT_CLK

72 47

OUT

HDA_SYNC

R1311

33

1

2

72 47

OUT

HDA_RST_L

R1312

33

1

2

72 47

10% 10V X5R 402

17

MF 2 201

2 72

C1300 1

72 17

5%

1/20W

MF 2 201

2

CRITICAL OMIT_TABLE

1

5%

1/20W

MF

1

330K

5%

1/20W

201

R1303 20K

5%

1

2

72

HDA_BIT_CLK_R

5%

1/20W 201 MF PLACE_NEAR=U0500.AW8:1.27mm 72

AV11

HDA_SYNC_R

1/20W 201 5% MF PLACE_NEAR=U0500.AV11:1.27mm 72

MF 1/20W 201 PLACE_NEAR=U0500.AU8:1.27mm 72 68 47

IN 66

OUT

R1313

HDA_SDOUT

33

1

2

72 17

HDA_RST*/I2S_MCLK O I D U A

HDA_SDIN0 NC_HDA_SDIN1

AY10

HDA_SDOUT_R

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

AU12

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

1/20W 201 5% MF PLACE_NEAR=U0500.AU11:1.27mm

AV10

TP_PCH_I2S1_SCLK

AY8

IN

XDP_CPUPCH_TRST_L

AU62

PCH_TRST*

70 16

IN

XDP_PCH_TCK

AE62

PCH_TCK

(IPD)

70 16

IN

XDP_PCH_TDI

AD61

PCH_TDI

(IPU)

70 16

OUT

XDP_PCH_TDO

AE61

PCH_TDO

C

IN

AD62

XDP_PCH_TMS

NC NC 70 16

BI

NC

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

PCH_JTAGX

AV2

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

J8

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

A17


J6


B14


F5


C17

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

B17


C15

IN IN

30 68 70

OUT


D17

30 68 70 30 68 70

30 68 70

IN

30 68 70

OUT

30 68 70

OUT

30 68 70

IN

30 68 70

IN

30 68 70

OUT

SATA Port assignments:

SSD Lane 3

Primary HDD/SSD

SSD Lane 2

Reserved: ODD

SSD Lane 1

Unused

SSD Lane 0

Secondary HDD/SSD

D

30 68 70

IN

OUT

PCIe Port assignments:

30 68 70

OUT

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

E5

30 68 70

30 68 70


H6

30 68 70

IN OUT OUT


H8

IN

30 68 70 30 68 70

I2S1_SCLK

70 16 6

70 16

A T A S

(IPD-PLTRST#)

TP_PCH_I2S1_TXD TP_PCH_I2S1_SFRM


SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 A15

HDA_SYNC/I2S0_SFRM

(IPD) 72 47


H5 B15

(IPD-PLTRST#)

AU8

HDA_RST_R_L

5%

J5

SATA0GP/GPIO34 V1 SATA1GP/GPIO35 U1 SATA2GP/GPIO36 V6 SATA3GP/GPIO37 AC1

XDP_SSD_PCIE3_SEL_L XDP_SSD_PCIE2_SEL_L XDP_SSD_PCIE1_SEL_L XDP_SSD_PCIE0_SEL_L

(IPU)

SATA_IREF G A T J

(IPU)

RSVD

JTAGX

L11

RSVD

K10

C12

SATALED*

IN IN

16

IN

16

A12

SATA_RCOMP

RSVD

IN

16

U3

16

PP1V05_S0SW_PCH_VCCSATA3PLL

8 11

1

R1370

NC

3.01K

C

1%

NC

1/20W

MF 2 201 PLACE_NEAR=U0500.C12:2.54mm 72

PCH_SATA_RCOMP PCH_SATALED_L

12

CRITICAL OMIT_TABLE


SYM 6 OF 19 66 66

68 12

70 68 32 70 68 32

31 12

B

OUT IN

CAMERA_CLKREQ_L

OUT

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

OUT

70 68 63

OUT IN

70 68 23

23 12

70 68 30 70 68 30

30 12

A

AP_CLKREQ_L

66

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

12

FW_CLKREQ_L

66

70 68 23

ENETSD_CLKREQ_L PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

70 68 63

63 12

NC_PCIE_CLK100M_ENETSDN NC_PCIE_CLK100M_ENETSDP

OUT

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

IN

TBT_CLKREQ_L

OUT OUT

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

IN

SSD_CLKREQ_L

OUT

C43 C42

U2

B41 A41

Y5

C41 B42 AD1

B38 C37

N1

A39 B39

U5

B37 A37

T2

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0*/GPIO18

S L A N G I S

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

K C O L C

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT

XTAL24_IN A25 XTAL24_OUT B25

PCIECLKRQ2*/GPIO20 CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

17 72 17 72

PP1V05_S0_PCH_VCCACLKPLL RSVD RSVD

K21

DIFFCLK_BIASREF

C26

M21

R1380

NC NC

3.01K 1%

1/20W

MF 2 201 PLACE_NEAR=U0500.C26:2.54mm

TESTLOW C35 TESTLOW C34 TESTLOW AK8 TESTLOW AL8


CLKOUT_LPC_0

AN15

PCH_TESTLOW_C35 PCH_TESTLOW_C34 PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

R1390 R1391 R1392 R1393

CLKOUT_LPC_1 AP15

LPC_CLK24M_SMC_R

OUT

17 72

LPC_CLK24M_LPCPLUS_R

OUT

17 72

(IPD-PWROK)

CLKOUT_ITPXDP_N B35 CLKOUT_ITPXDP_P A35

B

PCH_DIFFCLK_BIASREF


8 11

1


IN OUT

10K 10K 10K 10K

1

2

1

2

1

2

1

2

5%

1/20W

MF

201

5% 5% 5%

1/20W

MF

201

1/20W

MF

201

1/20W

MF

201

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

PCIECLKRQ5*/GPIO23

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

PCH Audio/JTAG/SATA/CLK

62 64 65 68 77 8 11 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61

PP3V3_S0

R1375

100K

1

2

R1340 R1341 R1342 R1343 R1344

100K 100K 100K 100K 100K

1

2

1

2

1

2

1

2

1

2

PCH_SATALED_L 5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

ENETSD_CLKREQ_L CAMERA_CLKREQ_L AP_CLKREQ_L FW_CLKREQ_L TBT_CLKREQ_L

DRAWING NUMBER

Apple Inc.

12

R

REVISION

12 68 12 31 12 63 12


BRANCH


PAGE

13 OF 120

SIZE

D

8

7

6

5

4

3

2

CRITICAL OMIT_TABLE

PPVRTC_G3H

U0500

330K

NO STUFF

SLP_S0# Isolation 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

R14001 5% 1/20W MF 0201 2

0

PP3V3_S0

1

IN

C1420 38

74LVC1G08 6 SOT891 36 18 13

OUT

PM_SLP_S0_L

4

IN IN

PM_PCH_SYS_PWROK

AG2

SYS_PWROK

IN

PM_PCH_PWROK

AY7

PCH_PWROK

72 17 13

IN

PM_PCH_PWROK

AB5 APWROK

18 16 15

OUT

PLT_RESET_L

AG7

PLTRST*

SUSCLK/GPIO62 AE6

IN

PM_RSMRST_L

AW6

RSMRST*

SLP_S5*/GPIO63 AP5

PCH_SUSWARN_L

AV4

SUSWARN*/SUSPWRDNACK/GPIO30 PWRBTN* (IPU)

(IPD-DeepSx) WAKE* AJ5 CLKRUN*/GPIO32 V5 SUS_STAT*/GPIO61 AG4

72

PCH_DSWVRMEN PM_DSW_PWRGD IN

PM_CLKRUN_L

BI

13 29 31 72

13 36 45 68

LPC_PWRDWN_L

OUT

36 45 68

PM_CLK32K_SUSCLK_R

OUT

37

PM_SLP_S5_L

OUT

13 36 61

SLP_S4* AJ6

PM_SLP_S4_L

OUT

13 18 29 36 61 63

SLP_S3* AT4

PM_SLP_S3_L

OUT

13 17 18 36 61 63 68

IN

PM_PWRBTN_L

AL7

37 36

IN

SMC_ADAPTER_EN

36 25 13

IN

PM_BATLOW_L

AJ8 ACPRESENT/GPIO31 (IPD-DeepSx) AN4 BATLOW*/GPIO72

SLP_SUS* AP4

PM_SLP_SUS_L

PCH_PM_SLP_S0_L

AF3

SLP_S0*

SLP_LAN* AJ7

TP_PCH_SLP_LAN_L

TP_PCH_SLP_WLAN_L

AM5

SLP_WLAN*/GPIO29

5

IN

PCIE_WAKE_L

72 36 16 13

NC

3

SYS_RESET*

DPWROK AV5

72 17 13

2

U1420 08 1

AC3

72 36 17 16

OUT

CRITICAL

SYSTEM POWER MANAGEMENT SUSACK* (IPU) DSWVRMEN AW7

72 68 36 17

0.1UF 10% 10V 0201

AK2

PM_SYSRST_L

72 61

2 X5R-CERM

PCH_SUSACK_L

SLP_A* AL5

D

5% 1/20W MF 2 201

BGA-TSP

SYM 8 OF 19

R1400 kept for debug purposes. 38

8 12 17 65

R1450

1

HASWELL-ULT 2C+GT2

D

1

NC_PM_SLP_A_L

36 72

R1451

1

100K

5% 1/20W MF 2 201

68

OUT

13 40 61

NC SLP_S0# can be driven high outside of S0 U1420 ensures signal will only be high in S0.

CRITICAL OMIT_TABLE

U0500

C

C

HASWELL-ULT 2C+GT2 BGA-TSP SYM 9 OF 19

68 62

OUT

EDP_BKLT_PWM

62 13

OUT

EDP_BKLT_EN

62 13

OUT

EDP_PANEL_PWR

24 13

IN

36 13

IN

68 13

IN

68 13

IN 66

68 13 66 64 13 68 13 61 13 68 13

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L NC_PCI_PME_L

ODD_PWR_EN_L OUT HDMITBTMUX_LATCH OUT ENET_LOW_PWR OUT AUD_PWR_EN OUT AUD_IPHS_SWITCH_EN OUT

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6 P4 N4 N2 AD4 U7 L1 L3 R5 L4

S

Y A L P S I D

PIRQA*/GPIO77 PIRQB*/GPIO78 PIRQC*/GPIO79 PIRQD*/GPIO80 PME* (IPU) GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

DDPB_CTRLCLK B9 DDPB_CTRLDATA C9 (IPD-PLTRST#) DDPC_CTRLCLK D9 DDPC_CTRLDATA D11 (IPD-PLTRST#)

D N A P B D E e D I

I C P

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

OUT

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA

OUT

BI

28 28

64 66

BI

64 66

DDPB_AUXN C5 DDPC_AUXN B6

DP_TBTSNK0_AUXCH_C_N DP_HDMI_TBT_AUX_N

BI

23 74

BI

64 66 74

DDPB_AUXP B5 DDPC_AUXP A6

DP_TBTSNK0_AUXCH_C_P DP_HDMI_TBT_AUX_P

BI

23 74

BI

64 66 74

DDPB_HPD C8

DP_TBTSNK0_HPD

IN

23

DDPC_HPD A8

DPMUX_HPD_OUT

IN

64 66

DP_INT_HPD

IN

62

EDP_HPD D6

B

B

PP3V3_S5 PP3V3_S0

A

R1405 R1410 R1452 R1455 R1460 R1461 R1462 R1463 R1464 R1430 R1431 R1440 R1441 R1442 R1443 R1445 R1446 R1447 R1448 R1449

8 11 15 16 17 18 26 27 29 60 61 65 68 77

56 59

61 62 64 65 68 30 37 46 47 50

8 11 12 13 15 17 18 24 28

1K

38 39 40 41 42 43 44 77

1

2

10K

1

2

10K

1

2

10K

1

2

1

2

1

2

1

2

1

2

1

2

100K 100K 100K 100K 100K 100K 100K

1/20W

MF

201

5%

1/20W

MF

201

5% 5%

1

2

1

2

100K 1

10K

5%

100K 100K

1 1 1

100K 100K 100K 100K 100K

1 1 1 1 1

1/20W 1/20W

MF MF

201 201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5% 5%

2 2 5% 5% 2 5% 2 5% 2 5% 2 5% 2 5% 2 5% 2 5%

1/20W

MF

1/20W

MF

201 201

PM_PWRBTN_L

13 16 36 72

PM_BATLOW_L

13 25 36

PCIE_WAKE_L

13 29 31 72

PM_CLKRUN_L

13 36 45 68

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L PM_SLP_SUS_L EDP_BKLT_EN EDP_PANEL_PWR TBT_PWR_REQ_L

1/20W MF 1/20W MF 1/20W MF 1/20W MF

201 SMC_RUNTIME_SCI_L 201 AUD_IP_PERIPHERAL_DET 201 AUD_I2C_INT_L 201

1/20W 1/20W 1/20W 1/20W 1/20W

201 HDMITBTMUX_LATCH 201 ENET_LOW_PWR 201 AUD_PWR_EN 201 AUD_IPHS_SWITCH_EN 201

MF MF MF MF MF

ODD_PWR_EN_L

13 36 61 13 18 29 36 61 63 13 17 18 36 61 63 68 13 18 36 13 40 61

13 62

A

13 62

13 24

S YN C_ MA ST ER =J 44 PAGE TITLE

13 68

DRAWING NUMBER

13 68

Apple Inc.

13 68

R 13 64 66 13 68 13 61 13 68

S YN C_ DA TE =0 8/ 12 /2 01 3

PCH PM/PCI/GFX

13 36

SIZE

D

REVISION


BRANCH


PAGE

14 OF 120

8

7

6

5

4 CRITICAL OMIT_TABLE

PCIe Port Assignments:

70 68 23

IN

Thunderbolt lane 0 70 68 23

OUT

70 68 23

OUT

70 68 23

IN

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

IN

70 68 23

OUT

70 68 23

OUT

Thunderbolt lane 1

70 68 23

IN

70 68 23

OUT

70 68 23

OUT

Thunderbolt lane 2

IN

70 68 23

IN

70 68 23

OUT

70 68 23

OUT

70 68 63

IN

70 68 63

OUT

70 68 63

OUT 66 66

Reserved: FireWire 66 66

C

71 68 63

SD Card Reader (& Ethernet if combo)

IN

71 63

OUT

71 63

OUT

Camera 70 32 70 32

11 8

H10


B21

G10

C21

E6 F6 B22 A21

PCIE_AP_D2R_N PCIE_AP_D2R_P

G11

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

C29

NC_PCIE_FW_D2RN NC_PCIE_FW_D2RP

F13

NC_PCIE_FW_R2D_CN NC_PCIE_FW_R2D_CP

B29

F11

B30

G13

A29

G17 F17 C30 C31

F15 G15 B31

PCIE_CAMERA_R2D_C_N PCIE_CAMERA_R2D_C_P

OUT OUT

P P 1V 0 5_ S 0S W _P C H_ V CC U SB 3 PL L

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_P

IN

70 68 32

B23 A23

USB3RPCIE_SD_R2D_C_N USB3RPCIE_SD_R2D_C_P

IN

70 68 32

E8

USB3RPCIE_SD_D2R_N USB3RPCIE_SD_D2R_P

IN

71 68 63

F8


IN

70 68 63

C22


Thunderbolt lane 3

AirPort

C23


IN

70 68 23

E10


70 68 23

70 68 23

F10


IN

70 68 23

D

3

72

P C H_ P CI E _R C OM P

A31

NC NC

E15 E13 A27 B27

1

USB Port Assignments:

U0500

PERN5_L0 PERP5_L0

2

HASWELL-ULT 2C+GT2

USB2N0 AN8 USB2P0 AM8

USB_EXTA_N USB_EXTA_P

BI

33 71

BI

33 71

USB2N1 AR7 USB2P1 AT7

USB_EXTB_N USB_EXTB_P

BI

63 71

BI

63 71

USB2N2 AR8 USB2P2 AP8

USB_BT_N USB_BT_P

BI BI

29 71

USB2N3 AR10 USB2P3 AT10

NC_USB_IRN NC_USB_IRP

BI BI

66 71

USB2N4 AM15 USB2P4 AL15

USB_TPAD_N USB_TPAD_P

BI BI

34 71

USB2N5 AM13 USB2P5 AN13

TP_USB_5N TP_USB_5P

USB2N6 AP11 USB2P6 AN11

NC_USB_CAMERAN NC_USB_CAMERAP

USB2N7 AR13 USB2P7 AP13

NC_USB_SDN NC_USB_SDP

Ext A (LS/FS/HS)

BGA-TSP

PETN5_L0 PETP5_L0

SYM 11 OF 19

PERN5_L1 PERP5_L1 PETN5_L1 PETP5_L1 PERN5_L2 PERP5_L2 PETN5_L2 PETP5_L2 PERN5_L3 PERP5_L3 PETN5_L3 PETP5_L3 PERN3 PERP3

66 71

BT

D

IR Trackpad

34 71

71

Unused

71

66 71

Reserved: Camera

66 71

66 71

Reserved: SD (HS)

66 71

(IPD)

E - B I S C U P

PETN3 PETP3

29 71

Ext B (LS/FS/HS)

USB3 Port Assignments:

PERN4 PERP4 PETN4 PETP4 PERN1/USB3RN2 PERP1/USB3RP2

USB3RN0 USB3RP0

G20

USB3TN0 USB3TP0

C33

USB3RN1 USB3RP1

E18

USB3_EXTA_D2R_N USB3_EXTA_D2R_P

H20

USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

B34

USB3_EXTB_D2R_N USB3_EXTB_D2R_P

F18

USB3TN1 B33 USB3TP1 A33

USB3_EXTB_R2D_C_N USB3_EXTB_R2D_C_P

IN

33 68 71

IN

33 68 71

OUT

33 68 71

OUT

33 68 71

Ext A (SS)

IN IN

63 68 71

OUT

63 68 71

OUT

63 68 71

63 68 71

Ext B (SS)

C

PETN1/USB3TN2 PETP1/USB3TP2 USBRBIAS* AJ10 USBRBIAS AJ11

PERN2/USB3RN3 PERP2/USB3RP3

71

PCH_USB_RBIAS PLACE_NEAR=U0500.AJ10:2.54mm

1

RSVD AN10 RSVD AM10

PETN2/USB3TN3 PETP2/USB3TP3

OC0*/GPIO40 AL3 OC1*/GPIO41 AT1 OC2*/GPIO42 AH2 OC3*/GPIO43 AV3

RSVD RSVD PCIE_RCOMP PCIE_IREF

R1570 22.6

NC NC

1%

1/20W

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

MF 2 201

IN

14 16 33

IN

14 16 63

IN

14 16

IN

14 16

R1500 1 3.01K 1% 1/20W MF 201 2 PLACE_NEAR=U0500.A27:2.54mm

CRITICAL OMIT_TABLE


B

BI

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

OUT

LPC_FRAME_L

72 68 45 36

BI

72 68 45 36

BI

72 68 45 36 72 68 45 36

72 68 45 36

BI

R1540 R1541 R1542 R1543 R1544

33 33 33 33 33

1

2

1

2

1

2

1 1

2

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

2 5%

1/20W

MF

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

AU14

LPC_FRAME_R_L

AV12

AW12 AY12 AW11

SYM 7 OF 19

(IPU)

L AD 0 LAD1 LAD2 LAD3

S MB ALE RT */ GP IO1 1 AN2

LFRAME*

S U B M S

201 AA3

72 45

OUT

SPI_CLK_R

72 45

OUT

SPI_CS0_R_L

Y7

SPI_CS0*

TP_SPI_CS1_L

Y4

SPI_CS1* SPI_CS2*

SMBCLK AP2 SMBDATA AH1

C P L

SPI_CLK

(IPU)

TP_SPI_CS2_L

AC2

72 45

BI

SPI_MOSI_R

AA2

SPI_MOSI

72 45

BI

SPI_MISO

AA4

SPI_MISO

72 45 14

BI

SPI_IO<2>

Y6

SPI_IO2

72 45 14

BI

SPI_IO<3>

AF1

SPI_IO3

(IPU)

PP3V3_SUS PP3V3_SUS

WOL_EN SML_PCH_0_CLK SML_PCH_0_DATA

SML1ALERT*/PCHHOT*/GPIO73 AU4

PCH_SML1ALERT_L

AU3

SML1CLK_GPIO75 SML1DATA/GPIO74 AH3

I P S

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML0CLK AN1 SML0DATA AK1

(IPU)

(IPU)

A

SML0ALERT*/GPIO60 AL2

PCH_SMBALERT_L

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

14

OUT BI

16 19 39 63 68 72

14 68

OUT

39 72

BI

39 72

OUT

38

OUT

32 36 39 43 68 72 76

BI

B

16 19 39 63 68 72

OUT

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals. Otherwise, 100k pull-up to 3.3V SUS required.

32 36 39 43 68 72 76

(IPU/IPD)

(IPU)

(IPU) (IPU)

K N I L C

(IPU/IPD) (IPU/IPD)

CL_CLK AF2

NC_CLINK_CLK

66

CL_DATA AD2

NC_CLINK_DATA

66

CL_RST* AF4

NC_CLINK_RESET_L

66

8 11 14 45 59 60 61 65

A

8 11 14 45 59 60 61 65

SYNC_MASTER=J44

R1580 R1581 R1582 R1583

100K 100K 100K 100K

1

2

1

2

1

2

1

2

R1548 R1549

1K 1K

1

2

1

2

R1590 R1591

100K 100K

1

2

1

2

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

201

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L SPI_IO<2> SPI_IO<3> PCH_SMBALERT_L WOL_EN

14 16 33 14 16 63


PAGE TITLE

PCH PCIe/USB/LPC/SPI/SMBus DRAWING NUMBER

14 16

Apple Inc.

14 16

14 45 72 14 45 72

14 14 68

R

REVISION


BRANCH


PAGE

15 OF 120

SIZE

D

8

7

6

5

4

3

2

1

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

61 60 57 53 37 17 16 11 8 6 68 65

TABLE_BOMGROUP_ITEM

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

PP3V3_S0 RAMCFG3:H

1

R1631 100K

5% 1/20W MF 2012

R16501 1K

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

RAMCFG2:H

RAMCFG1:H

1

1

R1636

R1635

100K

100K

5% 1/20W MF 2201

5% 1/20W MF 2012

RAMCFG0:H

1

R1611

U0500

15 16 18

IN

XDP_PCH_GPIO76

18 16 15

BI

XDP_MLB_RAMCFG0

AU2

GPIO8

66 64 23

BI

HDMITBTMUX_SEL_TBT

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

15 16 18 15 16 18

GPIO16

GSPI0_CS*/GPIO83 R6

PCH_GSPI0_CS_L

15

GPIO17

GSPI0_CLK/GPIO84 L6

PCH_GSPI0_CLK

15

63 15

OUT

SD_RESET_L

15

IN

GSPI0_MISO/GPIO85 N6 (IPD) GSPI0_MOSI/GPIO86 L8 (IPD-PLTRST#)

PCH_GSPI0_MISO

36 15

PCH_GSPI0_MOSI

15

AD5

GPIO24

SMC_WAKE_SCI_L

AN5

GPIO27 (IPD-DeepSx)

15

TPAD_SPI_INT_L

AD7

GPIO28

TPAD_SPI_CS_L

15

TPAD_USB_IF_EN

AN3

GSPI1_CS*/GPIO87 R7

15

GPIO26

TPAD_SPI_CLK

15

SSD_PWR_EN

AG6

GSPI1_CLK/GPIO88 L5

GPIO56

TPAD_SPI_MISO

15

PCH_TBT_PCIE_RESET_L

AP1

GPIO57

TPAD_SPI_MOSI

15

OUT

HDD_PWR_EN

AL4

GSPI1_MISO/GPIO89 N7 (IPD) GSPI_MOSI/GPIO90 K2

GPIO58

BI

XDP_SDCONN_STATE_CHANGE_L

AT5

GPIO59

63 15

OUT

SD_PWR_EN

AK4

GPIO44

23 15

OUT

TBT_PWR_EN

AB6

GPIO47

16 15

OUT

XDP_JTAG_ISP_TCK

U4

GPIO48 GPIO49

OUT

XDP_JTAG_ISP_TDI

Y3

18 15

OUT

JTAG_TBT_TMS_PCH

P3

GPIO50

60 15

OUT

PCH_HSIO_PWR_EN

Y2

16 15

15

B

A

R1610 R1614 R1615

100K

R1616 R1617 R1618 R1619 R1620 R1622 R1623 R1624 R1625 R1626 R1627 R1628 R1629 R1630 R1632 R1633 R1634 R1637 R1638 R1640 R1652 R1670 R1691 R1693 R1694 R1695

100K 100K 100K 100K 100K

1 1 1 1 1

2 2 2 2 2

100K 100K 100K 100K 100K 100K 100K 100K 100K

1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2

100K 100K

1 1 1

2

5%

2 2 5% 5%

1K

2

5%

5% 5% 5% 5% 5% 5% 5% 5% 5%

1 1

100K

1

10K

1

100K

1

100K

1

100K

1 1

10K

5% 2 2 5% 5% 2 5% 2 5% 2 5% 2 5% 2 2 5% 5%

15 29

IN

15 64

JTAG_ISP_TDO

IN

15 18

15

PCH_UART1_TXD

15

HSIOPC/GPIO71

UART1_RST*/GPIO2 J3

PCH_UART1_RTS_L

15

TPAD_SPI_IF_EN

AT3

GPIO13

UART1_CTS*/GPIO3 J4

PCH_UART1_CTS_L

15

XDP_MLB_RAMCFG3

AH4

GPIO14

PCH_I2C0_SDA

15

AM4

I2C0_SDA/GPIO4 F2

SPIROM_USE_MLB

GPIO25

PCH_I2C0_SCL

15

AG5

I2C0_SCL/GPIO5 F3

CAMERA_PWR_EN_PCH

GPIO45

FW_PWR_EN

I2C1_SDA/GPIO6 G4

PCH_I2C1_SDA

15

OUT

AG3

GPIO9

15

BI

AM3

PCH_I2C1_SCL

18 16 15

XDP_MLB_RAMCFG1

I2C1_SCL/GPIO7 F1

18 16 15

BI

XDP_MLB_RAMCFG2

AM2

30 15

OUT

SSD_DEVSLP

29 15

OUT

68 15

IN

1/20W MF

63

C

GPIO10

SDIO_CLK/GPIO64 E3

TBT_POC_RESET_L

OUT

P2

DEVSLP0*/GPIO33

SDIO_CMD/GPIO65 F4

BT_PWRRST_L

OUT

C4

SDIO_POWER_EN/GPIO70

PCH_STRP_TOPBLK_SWP_L

IN

38

SSD_RESET_L

L2

DEVSLP1*/GPIO38

SDIO_D0/GPIO66 D3 (IPD-PLTRST#) SDIO_D1/GPIO67 E4

ENET_MEDIA_SENSE

IN

15 68

FW_PME_L

N5

DEVSLP2*/GPIO39

SDIO_D2/GPIO68 C3

LCD_IRQ_L

IN

15 62 68

PCH_TCO_TIMER_DISABLE

V2

SPKR/GPIO81 (IPD-PLTRST#)

SDIO_D3/GPIO69 E2

LCD_PSR_EN

AP_S0IX_WAKE_SEL

201

GPIO46

5% 1/20W MF 2 201

OUT

PCH_UART1_RXD

UART1_TXD/GPIO1 G2

13 15 16 18

100K

AP_RESET_L

UART1_RXD/GPIO0 K4

IN

R1671

1

OUT

24

Pull-up on TBT page

15 68

Requires connection to SMC via 1K series R

15 62

56 59

15 18 19 39 42 60 65 68 15 18 19 39 42 60 65 68 15 18 19 39 42 60 65 68 31 42 77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

15 15

1/20W

MF

201

1/20W 1 /2 0W

MF MF

201 2 01

1/20W 1/20W 1/20W 1/20W 1 /2 0W

MF MF MF MF MF

201 201 201 201 2 01

XDP_PCH_GPIO76 XDP_LPCPLUS_GPIO XDP_PCH_GPIO17

15 16

15 15

1/20W 1/20W 1 /2 0W 1/20W 1/20W 1/20W 1 /2 0W 1/20W 1/20W

1/20W

MF MF MF MF MF MF MF MF MF MF MF MF

201 201 2 01 201 201 201 2 01 201 201

15 16

201

SSD_DEVSLP 201 AP_S0IX_WAKE_SEL

MF MF

1/20W

MF

1/20W

MF

201

1/20W

MF

201

1/20W 1/20W

MF MF MF

201

201

201

15 36

15

R1616 should also be stuffed if platform does not use SD card

15 15

15

29 15

15

64 15

15 30 60 61

15 68

15

15 16 18

15

15 63

15

15 23 15 15 16 15

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI AP_S0IX_WAKE_L HDMITBTMUX_FLAG_L PCH_UART1_RXD PCH_UART1_TXD PCH_UART1_RTS_L PCH_UART1_CTS_L PCH_I2C0_SDA PCH_I2C0_SCL

15 16 15 18

15

15 60

15

PCH_I2C1_SDA PCH_I2C1_SCL

R1660 R1661 R1662 R1663 R1664 R1665 R1666 R1667 R1668 R1669 R1672 R1673 R1674 R1675 R1676 R1677 R1678 R1679

100K 100K 100K 100K

1 1 1 1

47K 47K 47K 47K

1 1 1 1

PP3V3_S0

100K 1 100K 1 100K 100K 100K 100K

1 1 1 1

100K 1 100K 1 100K 1 100K 1

2 5% 1/20W 2 5% 1/20W 2 5% 1/20W 2 5% 1/20W 2 5% 1/20W 2 2 5% 1/20W 5% 1/20W 2 5% 1/20W 2 5% 1/20W 2 5% 1/20W 2 2 5% 1/20W 5% 1/20W 2 5% 1/20W 2 5% 1/20W 2 2 5% 1/20W 5% 1/20W 2 5% 1/20W 2 5% 1/20W

B MF MF MF MF

201 201 201 201

MF MF MF MF

201 201 201 201

MF MF

201 201

MF MF MF MF

201 201 201 201

MF MF

201 201

MF MF

201 201

15

15 45 68 72 15 18 15 68

15 30 15 29

FW_PME_L

15 68

LPC_SERIRQ

15 36 45 68

JTAG_ISP_TDO

15 18

BT_PWRRST_L

15 68

ENET_MEDIA_SENSE 201 LCD_IRQ_L

201

15 63

15

HDD_PWR_EN XDP_SDCONN_STATE_CHANGE_L SD_PWR_EN TBT_PWR_EN XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI JTAG_TBT_TMS_PCH PCH_HSIO_PWR_EN TPAD_SPI_IF_EN

SPIROM_USE_MLB 201 CAMERA_PWR_EN_PCH 201 FW_PWR_EN

1/20W 1/20W

1/20W

SD_RESET_L SMC_WAKE_SCI_L TPAD_SPI_INT_L TPAD_USB_IF_EN SSD_PWR_EN

PCH_GSPI0_CS_L PCH_GSPI0_CLK PCH_GSPI0_MISO PCH_GSPI0_MOSI

15 16 45 68

15

100K NO 1 STUFF 2 100K 1 2 5% 1/20W 100K 1 2 5% 1/20W 100K 100K

O O I I P P G L

PLT_RESET_L IN

OUT

SD_ON_MLB 5% 5% 5% 5% 5%

UART0_CTS*/GPIO94 G1

1% 1/20W MF 2 201

HDMITBTMUX_FLAG_L

BI

OUT

1

UART0_RTS*/GPIO93 J2

AP_S0IX_WAKE_L

BI

100K

R1641

UART0_TXD/GPIO92 K3

18 16 15

68 15

60 61 65 68 77

UART0_RXD/GPIO91 J1

72 68 45 15

18 15

8 11 13 16 17 18 26 27 29

49.9

T3

18 16 15

PP3V3_S0

R1655

Y1

OUT

D PLACE_NEAR=U0500.AW15:2.54mm 1

XDP_PCH_GPIO17

OUT

Pull-up/down on chipset support page (depends on TBT controller) Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

15 36 45 68

PCH_OPI_COMP

XDP_LPCPLUS_GPIO

GPIO15 (IPD-RSMRST#)

37 72

18 23 72

NC NC

IN

68 15

30

72

BI

BI

61 60 30 15

5% 1/20W MF 201 2

RSVD AF20 RSVD AB21

IN

LPC_SERIRQ

OUT

100K

R16391

PCH_OPI_COMP AW15

OUT

TBT_CIO_PLUG_EVENT_L

16 15

R1621

C

SERIRQ T4

68 45 16 15

1

23 18

PM_THRMTRIP_L

RCIN*/GPIO82 V4

MEM_VDD_SEL_1V5_L

PLT_RESET_L

5% 1/20W MF 201 2

C S I M / U P C

BI

55

18 16 15 13

P1

BGA-TSP SYM 10 OF 19 BMBUSY*/GPIO76

16 15 15 16 18

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

PP3V3_S5 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3RS0_CAMERA PP3V3_S0 PP3V3_S0 TBTLC for CR, S0 for RR

THRMTRIP* D60

HASWELL-ULT 2C+GT2

100K

5% 1/20W MF 2 201

GPIO12:

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

5% 1/20W MF 2012

CRITICAL OMIT_TABLE

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3

D

PP1V05_S0

15 68 15 62 68

S YN C_ MA ST ER =J 44 PAGE TITLE

A

S YN C_ DA TE =0 8/ 12 /2 01 3

PCH GPIO/MISC/LPIO DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

16 OF 120

8

7

6

Extra BPM Testpoints

D

70 6

IN

XDP_BPM_L<2>

70 6

IN

XDP_BPM_L<3>

70 6

IN

XDP_BPM_L<4>

70 6

IN

XDP_BPM_L<5>

70 6

IN

XDP_BPM_L<6>

70 6

IN

XDP_BPM_L<7>

70 17 8

TP1802 TP1803 TP1804 TP1805 TP1806 TP1807

150

2

XDP 2

OUT

PM_PWRBTN_L

R1802

72 36 17 13

OUT

PM_PCH_SYS_PWROK

R1804

0 1 PLACE_NEAR=U5000.J3:2.54mm 0

5%

1 / 20 W

MF

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

70 6

IN

5%

1 / 20 W

0201

5%

1/16W MF-LF 402

XDP 1

8

2

72 68 63 39 19 14 72 68 63 39 19 14 70 16 12

C

70 16 6

70 16 12

OUT

XDP_CPU_TCK

OUT

PCH_JTAGX

R1835

0

CPU_CFG<0> CPU_CFG<1>

OBSDATA_A0 OBSDATA_A1


OBSDATA_A2 OBSDATA_A3

XDP_BPM_L<0> XDP_BPM_L<1>

OBSFN_B0 OBSFN_B1


OBSDATA_B0 OBSDATA_B1


OBSDATA_B2 OBSDATA_B3

72

XDP_CPU_VCCST_PWRGD XDP_CPU_PWRBTN_L

72

CPU_PWR_DEBUG XDP_SYS_PWROK

70

MF

OBSFN_A0 OBSFN_A1

201

XDP 2

5% 1/16W MF-LF 402

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

BI

OUT

BI IN OUT

PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3

SDA SCL

SMBUS_PCH_DATA SMBUS_PCH_CLK XDP_PCH_TCK

TCK1 TCK0

XDP 1

2

XDP

5% 1 / 20 W MF 0201 PLACE_NEAR=J1800.58:28mm

XDP

C1804 1 0.1UF

1K

10% 6.3V CERM-X5R 2 0201

5% 1/16W MF-LF 2402

62

61

70 16 6

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

64

10% 6.3V CERM-X5R 2 0201

70 16 6

OBSFN_C0 OBSFN_C1


IN

6 70

IN

6 70

OBSDATA_C0 OBSDATA_C1


IN

6 70

IN

6 70

OBSDATA_C2 OBSDATA_C3


IN

6 70

IN

6 70

OBSFN_D0 OBSFN_D1


IN

6 70

IN

6 70

OBSDATA_D0 OBSDATA_D1


IN

6 70

IN

6 70

OBSDATA_D2 OBSDATA_D3


IN

6 70

IN

6 70

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7

NC NC

TDO TRSTn

70

TDI TMS XDP_PRESENT# 1

63

XDP

C1801

1

0.1UF

518S0847

XDP

C1806 0.1UF

10% 2 6.3V CERM-X5R 0201

10% 2 6.3V CERM-X5R 0201

Q1840

DMN5L06VK-7 SOT-563 D

S

Q1842

DMN5L06VK-7

63 16 14

14

XDP_USB_EXTB_OC_L

OUT

XDP_USB_EXTC_OC_L

TP1870

SOT-563

XDP_USB_EXTD_OC_L XDP_SDCONN_STATE_CHANGE_L

18 15

BI

XDP_MLB_RAMCFG1

18 15

BI

XDP_MLB_RAMCFG2

BI

XDP_MLB_RAMCFG3

15

IN

XDP_JTAG_ISP_TCK

12

OUT

XDP_SSD_PCIE3_SEL_L

12

OUT

XDP_SSD_PCIE2_SEL_L

12

OUT

XDP_SSD_PCIE1_SEL_L

12

OUT

XDP_SSD_PCIE0_SEL_L

BI

XDP_LPCPLUS_GPIO

15

OUT

XDP_PCH_GPIO17

15

BI

XDP_PCH_GPIO76

15

IN

XDP_JTAG_ISP_TDI

68 45 16 15

CPU JTAG Isolation

XDP_USB_EXTB_OC_L

56 29 27 26 18 17 15 13 11 8 77 68 65 61 60 59

PP5V_S0 PP3V3_S5

TP1873 TP1874

1 TP TP-P6

14 16 33

IN

14 16 63

1 TP TP-P6 1 TP TP-P6 1 TP TP-P6

TP1876 TP1877 TP1878

R1881 R1882 R1883 R1884

1

2

1K

1

2

1K

1

2

1K

1

2

5%

1/20W MF

S 1

1/20W MF

201

5%

1/20W MF

201

5%

1/20W MF

201

IN

XDP_LPCPLUS_GPIO

BI

12 16 70

C

12 16 70

IN

6 16 70

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

6 12 16 70

OUT

6 12 16 70

OUT

6 12 16 70

XDP_CPU_TDI

OUT

6 70

XDP_CPU_TMS

OUT

6 70

G

S 4

U1845

74LVC1G07GF SOT891

ALL_SYS_PWRGD

2 A

NC

5% 1/20W MF 2 201

NC 5

D

PLACE_NEAR=J1800.57:28mm 6

B

2

G

S 1

65 59

XDP_JTAG_CPU_ISOL_L

Y 4

1 NC

SOT-563

PP1V05_SUS

NO STUFF

NC

R1899 1K 2 PLACE_NEAR=U0500.AE63:28mm

70 16 12

PCH_JTAGX

70 16 12

XDP_PCH_TDO

R1890

51

1

R1891

51

2

70 16 12

XDP_PCH_TMS

R1892

51

2

70 16 12

XDP_PCH_TCK

R1896

51

1

PLACE_NEAR=U0500.AD61:28mm

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

5%

1/20W

MF

201

XDP

PLACE_NEAR=U0500.AD62:28mm

1

NO STUFF 2

PLACE_NEAR=U0500.AE62:28mm

R1897 51 XDP_CPUPCH_TRST_L

5%

XDP

XDP_PCH_TDI

70 16 12 6

1

XDP 2

PLACE_NEAR=U0500.AE61:28mm

70 16 12

30

15 16 45 68

12 16 70

5

NOTE: Must not short XDP pins together!

SSD_PCIE_SEL_L

XDP_CPU_TDO

XDP_CPUPCH_TRST_L XDP_CPUPCH_TRST_L

18 23

201

5%

MAKE_BASE=TRUE

OUT

13 15 18

2

3

JTAG_ISP_TCK

1K

330K

VCC

0.1UF

IN

R1845

1

6

GND

MAKE_BASE=TRUE

201

XDP

Q1842

C1845 1

61 36 17 15 16 18

201

MF

CRITICAL

10% 16V X5R-CERM 2 0201

XDP_SDCONN_STATE_CHANGE_L IN

MAKE_BASE=TRUE

D


DMN5L06VK-7 IN

1 TP TP-P6

IN

18 15

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

OUT

14

18 16 15

A

OUT

1 TP TP-P6

MAKE_BASE=TRUE

MF

1/20W

G

XDP

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

XDP_USB_EXTA_OC_L

1/20W

5%

XDP

PCH XDP Signals

XDP_MLB_RAMCFG0

5%

G

CRITICAL

OUT

1

5

4


BI

2

XDP

PLACE_NEAR=U0500.E60:28mm

CRITICAL

D

18 15

R1813

XDP

XDP

SOT-563

33 16 14

XDP_CPU_TCK

51 2

CRITICAL

Q1840

B

51 1

XDP

DMN5L06VK-7

61 60 58 54 53 45 44 41 32 17 68 65

R1810

PLACE_NEAR=U0500.F62:28mm

2 R1805 1K 1 XDP_CPURST_L PLT_RESET_L IN 5% 1/20W MF 201 XDP_DBRESET_L PLACE_NEAR=U0500.AG7:2.54mm OUT 17 72 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page XDP_PCH_TDO IN XDP_TRST_L XDP_PCH_TDI OUT XDP_PCH_TMS OUT

XDP_CPU_PRESENT_L

Non-XDP Signals

XDP_CPU_TDO

D


PCH/XDP Signals

PP1V05_S0

TDI and TMS are terminated in CPU.

XDP

1 R1831 C1800 0.1UF

1

1 60 57 53 37 17 16 15 11 8 6 68 65 61

M-ST-SM1

R1830

70 6

2

DF40RC-60DP-0.4V

1

70 6

3

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

J1800

R1800 1K 1 PLACE_NEAR=U0500.C61:2.54mm

72 36 13

4 Merged (CPU/PCH) Micro2-XDP CRITICAL XDP_CONN

1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6 1 TP TP-P6

CPU_VCCST_PWRGD

IN

5 PP1V05_S0

60 57 53 37 17 16 15 11 8 6 68 65 61

1

NO STUFF 2

PLACE_NEAR=U0500.AU62:28mm

1

1 TP TP-P6

TP1886 TP1887

1 TP TP-P6

MAKE_BASE=TRUE

JTAG_ISP_TDI

OUT

18 23

Unused & MLB_RAMCFGx GPIOs have TPs. USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.


DRAWING NUMBER

Apple Inc.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug. JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug. NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals. SSD_PCIEx_SEL_L straps are connected via 1K to common net.

A


CPU/PCH Merged XDP R

SIZE

D

REVISION


BRANCH


PAGE

18 OF 120

8

7

6

5

4

3

2

1

System RTC Power Source & 32kHz / 25MHz Clock Generator PCH Reset Button

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal PP3V42_G3H Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

51 45 39 38 37 36 34 33 30 17 68 65 61 52

This looks a little ugly to support new and old parts. With GreenCLK Rev C pin 5 must receive S5 power (Stuff60R2042) 59 56 29 27 26

D

73 65 55 41 22 21 20 19

31

PP1V2_CAM_XTALPCIEVDD PP3V3_TBTLC

2

C1922 1

1

10% 16V X5R-CERM 2 0201

10% 16V X5R-CERM 2 0201

20% 6.3V 2 X5R 0201

0.1UF

R1996 72 16

C1902

2

1

71

0201 5 %

25V

1

NP0-C0G-CERM

NC NC

C1906

2 3

2

Y1905

BI

6

0

1M

NC

5% 1/20W MF 2 201

U1970

74AUP1G07GF SOT891

CPU_MEMVTT_PWR_EN_LSVDDQ

2 A

Y 4

1 NC

NC

NC 5

MEMVTT_PWR_EN

17 55

MEMVTT_PWR_EN

OUT

MAKE_BASE=TRUE

NC

GND THRM PAD

0

1

PCH_CLK24M_XTALOUT_R CRITICAL

OUT

1

61 60 58 54 53 45 44 41 32 16 68 65

12 72

PP5V_S0 1

R1920

PCH ME Disable Strap

32 71 23 71

100K

5% 1/20W MF 2201

Q1920

DMN5L06VK-7 SOT-563

C1910

60 11 8

1UF

SPI_DESCRIPTOR_OVERRIDE_LS5V

5

G

PP1V5_S0SW_AUDIO_HDA D

20% 2 6.3V X5R 0201

S

3

SPI_DESCRIPTOR_OVERRIDE

4

1

NC_RTC_CLK32K_RTCX2

NC_RTC_CLK32K_RTCX2

R1921

D 6

1K

5% 1/20W MF 2 201

NO_TEST=TRUE

IN

12 17

2 G 36

2

PCH_CLK24M_XTALOUT

5% 1/20W MF

Y1915 NC 24.000MHZ-20PPM-6PF 0201 2 NC 3.20X2.50MM-SM1 4

12 72

OUT

12 72

R1916 1M

5% 1/20W MF 2 201

3

2

PCH_CLK24M_XTALIN

IN

72 12

IN

LPC_CLK24M_LPCPLUS_R

22

1 PLACE_NEAR=U0500.AN15:5.1mm

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

LPC_CLK24M_SMC

R1927 LPC_CLK24M_SMC_R

5% 1/20W MF 201 1 PLACE_NEAR=U0500.AP15:5.1mm

PP3V3_S5

17 36 68 72

MAKE_BASE=TRUE

2

LPC_CLK24M_SMC

OUT

17 36 68 72

2

LPC_CLK24M_LPCPLUS

OUT

45 68 72

PP1V05_S0

C1930 1

12 72

0.1UF

61 36 17 16

5% 1/20W MF 201

68 63 61 36 18 13

6

IN

2 A

PM_SLP_S3_L

65

U1930 74AUP1G09

5% 1/20W MF 2 201

SOT891

CPU_VCCST_PWRGD

Y 4

OUT

8 16 70

1 B

NC

B

68

10K

VCC

ALL_SYS_PWRGD

6 8 11 15 16 37 53 57 60 61

R1931

1

CRITICAL

10% 16V X5R-CERM 2 0201

R1926 22

C OUT

VCCST (1.05V S0) PWRGD

PCH 24MHz Outputs

72 12

IN

HDA_SDOUT_R IPD = 9-50k

S 1

SPI_DESCRIPTOR_OVERRIDE_L

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

1

6.8PF

+/-0.1PF 25V C0G 0201

IN

17 55

GND

Q1920

MAKE_BASE=TRUE

D

3

SILK_PART=SYS RESET

SYSCLK_CLK25M_CAMERA OUT SYSCLK_CLK25M_TBT OUT PPVRTC_G3H 8 12 13 65 For SB RTC Power

0 6 7 7 1 1 1

17 12

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V 33uW when driven-low

SOT-563

72

1

IN

5% 1/16W MF-LF 2 402

R1915

2

10% 16V X5R-CERM 2 0201

13 36 68 72

R1997

330K

VCC

0.1UF

PM_SYSRST_L NO STUFF

1

R1970

1

6

DMN5L06VK-7

6.8PF

1

PCH_CLK32K_RTCX1

NC

VOUT 1

R1906

PCH 24MHz Crystal

+/-0.1PF 25V C0G 0201 NC

C1916

25M_A 9 25M_B 8 25M_C 15

X2 X1

5% 1/20W MF 2201

OMIT

C1915 1

3 4

32.768K 12

1

25.000MHZ-12PF-20PPM

C1970 1

CRITICAL

11 VIOE_25M_A 6 VIOE_25M_B 14 VIOE_25M_C

71

5% 1/20W MF 0201

2

5% 1/20W MF 2201

+V3.3A should be first available ~3.3V power to reduce VBAT draw.

TQFN

SYSCLK_CLK25M_X2_R NO STUFF

2

0

1

VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.

T O H 3 G V

71 SYSCLK_CLK25M_X1 NOTE: 30 PPM or better required for RTC accuracy

5% 25V NP0-C0G-CERM 0201

C

0

1

SM-3.2X2.5MM

4

12PF 1

SYSCLK_CLK25M_X2 CRITICAL

D D V

U1900

R1905

12PF

XDP_DBRESET_L

1/20W 0201 MF 5%

SLG3NB148CV

CKPLUS_WAIVE=PwrTerm2Gnd

C1905

IN

3 1

5

1UF

0.1UF

PP3V3_S0

10K

XDP

C N

C1924 1

PP1V35_S3

R1995

77 68 65 61 15 13 11 8 18 17 16

18 GreenCLK 25MHz Power Must be powered if any VDDIO is powered.

65 24 23 18

PP3V3_S0 1

PP3V3_S5 Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5 No bypass necessary PP3V3_S5RS3RS0_SYSCLKGEN

CAM XTAL Power TBT XTAL Power

Memory VTT Enable Level-Shifter CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

5 NC

B

GND 3

IN

53 17 8

CPU_VR_READY OUT MAKE_BASE=TRUE

53 17 8

IN

CPU_VR_READY

R1951 1

0

2

61 36 17 16

IN

13 17 72

R19632 0

ALL_SYS_PWRGD

1

CPUVR_PGOOD_R

2

5% 1/20W MF 0201

C1950

10% 16V 2 X5R-CERM 0201

10K

NO STUFF

13 17 72

OUT

0.1UF

5% 1/20W MF 201 2

10K

A

1

R19501

R19551

OUT

BYPASS=U1950:5MM

PP3V3_S0

CPU_VR_EN

5% 1/20W MF 201 2

PM_PCH_PWROK PM_PCH_PWROK MAKE_BASE=TRUE

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

53 8

PCH PWROK Generation

PP3V42_G3H

51 45 39 38 37 36 34 33 30 17 68 65 61 52

8 74LVC2G08GT/S505

SOT833

A

U1950Y 7 B

08 4

72

5% 1/20W MF 0201 1

PM_S0_PGOOD NO STUFF

R19611

PART NUMBER

R1960 0

5% 1/20W MF 1 0201 5 6

197S0480

CKPLUS_WAIVE=UNCONNECTED_PINS 8 74LVC2G08GT/S505

SOT833

A

U1950 Y 3 B

72

SYS_PWROK_R

08

100K

5% 1/20W MF 201 2

SMC_DELAYED_PWRGD

NO STUFF WF: Do we need this? 2

4

R1962 1

1K

5% 1/20W MF 201

2

QTY 1

DESCRIPTION

REFERENCE DES

XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

CRITICAL

S YN C_ MA ST ER =J 44 PM_PCH_SYS_PWROK

PAGE TITLE OUT

13 16 36 72

BOM OPTION

Y1905

A

S YN C_ DA TE =0 8/ 12 /2 01 3

Chipset Support DRAWING NUMBER

Apple Inc.

CKPLUS_WAIVE=UNCONNECTED_PINS R

SIZE

D

REVISION


BRANCH


PAGE

19 OF 120

8

7

6

5

4

Platform Reset Connections

16 15 13

IN

1

33

R2040 PP3V3_S3

68 65 60 42 39 19 18 15

2

LPCPLUS_RESET_L

OUT

45 68

0

1

PCA9557D_RESET_L

OUT

19

R2041 PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

0

1

17 18

PP3V3_S5RS3RS0_SYSCLKGEN

17 18

R2015 1 100K 5%

1/20W

PP3V3_S5

77 68 65 47 46 44 43 38 37 30 28 13 12 11 8 24 18 17 15 42 41 40 39 64 62 61 50

0

1

MAKE_BASE

2 72 23 18 15

5% 1/20W MF 0201

SC70-HF

U2071

2

1

PLT_RST_BUF_L

4

C2071

1

0

OUT

68 65 64 63 60 42 38 37 34 29


R2032

R2089 1

0

CAM_PCIE_RESET_L OUT

2

R20311

31

5% 1/20W MF 201

MF

0201


PCH_TBT_PCIE_RESET_LOUT

Q2030

15 18 23

C

DMN5L06VK-7

SMC_PME_S4_DARK_L

37 36 23 18

SOT-563

SOT-563

To SMC

68 65 60 42 39 19 18 15

100K

5% 1/20W MF 201 2

D

R2062 100K

0.1UF

20% 10V 2 CERM 402

5% 1/20W MF 2 201

5

VCC

U2060

74LVC2G07 From RR

S

6

1

From PCH

S0 pull-up on PCH page To PCH

SOT891

23

IN

15

IN

S

3

15 18 23 72

1

C2060

1

G

2

G

D

SMC_PME_S4_DARK_L

37 36 23 18

R20611

2

SMC_PME_SDCONN

5

470K

5% 1/20W MF 2 201

Q2030

DMN5L06VK-7

470K

5% 1/20W

MAKE_BASE=TRUE

IN

PP3V3_TBTLC

1

1/20W

IN

TBTLC can be on when S0 is off, and vice-versa Isolation ensures no leakage to RR or PCH 65 24 23 17

5%

MF 2 201

23 18 15

TRUE

PP3V3_S4

MF

0201

100K

10% 16V X5R-CERM 0201


36

1/20W

R2070

OUT

Redwood Ridge JTAG Isolation

SDCONN_STATE_CHANGE Isolation SMC_LRESET_L

2

5% 1

3

0.1UF

2

Buffered R2072

CRITICAL MC74VHC1G08

5

1

2

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)

Scrub for Layout Optimization

PP3V3_S0

D

MF

201

THUNDERBOLT PULL-UP

R2042 should be stuffed for GreenCLK C

R2042 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

R2041/2 should be stuffed for GreekCLK A or B depending on S2 rail

2

5% 1/20W MF 0201

MF

0201

PP3V3_S5RS3RS0_SYSCLKGEN MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

NO STUFF

2

5% 1/20W

D

1

I1608

2

5% 1/20W MF 0201

R2071

MF

201

0

1

5% 1/20W

2

NO STUFF

Unbuffered R2081 PLT_RESET_L

3

GreenCLK 25MHz Power

JTAG_TBT_TDO JTAG_TBT_TMS_PCH S0 pull-up on PCH page

1 1A

1Y 6

JTAG_ISP_TDO

OUT

15

3 2A

2Y 4

JTAG_TBT_TMS

OUT

23

To RR

C

GND 2

4

PP3V3_S3 CRITICAL

U2031

6

OUT

16 15

XDP_SDCONN_STATE_CHANGE_L

4 Y

0.1UF 0201

2

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs different isolation techniques will likely be necessary. Multi-router designs also require different circuitry.

B 1

C2031 1 10% 6.3V CERM-X5R

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK and TDI as well for PCH glitch-prevention.

A 2

BYPASS=U2030.5:5MM

To PCH

74AUP1G09 SOT891

VCC

NC 5

NC

GND 3

Power State Debug LEDs DBGLED 65 61 60 27 26 18 13 11 8 17 16 15 59 56 29 77 68

PP3V3_S5

0

2

DBGLED

DBGLED

DBGLED

DBGLED

DBGLED

R2090 1

R2091 1

R2092 1

R2093 1

R2095 1

5% 1/20W MF 201

20K

5% 1/20W MF 201

2

DBGLED_S5 A

20K

5% 1/20W MF 201

2

DBGLED_S4

DBGLED

A

D2090 GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

63

JTAG_ISP_TCK

JTAG_ISP_TCK

OUT

16 18 23

JTAG_ISP_TDI

JTAG_ISP_TDI

OUT

16 18 23

23 18 16

IN

MAKE_BASE=TRUE

23 18 16

IN

MAKE_BASE=TRUE


20K

B

IN

PP3V3_S5_DBGLED

1

5% 1/16W MF-LF 402

PLACE_SIDE=BOTTOM

SDCONN_STATE_CHANGE_RIO

(For development only)

R2094

5% 1/20W MF 201

2

DBGLED_S3

DBGLED

A


K

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

20K

A


K

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

DBGLED_S4_D

Q2090

D

6

SOT-563

2

G

Q2090

D

3

1

A

D2093

5

G

4

D2095 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

61 60 27 26

IN

63 61 36 29 18 13

IN

68 63 61 36 17 13

IN

36 13

IN

TP_CPU_RSVDP61

TP_CPU_RSVDN61 MAKE_BASE=TRUE TP_CPU_RSVDP61 MAKE_BASE=TRUE

8 18

B

8 18

NOSTUFF


BYPASS=U2030:3mm

C2030 1

Q2091

D

DBGLED 6

2

G

Q2091

RAM Configuration Straps

0.1UF

D

10% 10V X5R-CERM 2 0201

3

DMN5L06VK-7

Pull-downs for chip-down RAM systems

NOSTUFF CRITICAL

SOT-563

S

1

5

G

S

63 61 36 29 18 13

IN IN

16 15 16 15

6 74LVC1G08 SOT891

PM_SLP_S4_L

2

CAMERA_PWR_EN_PCH

4 U2030 1 08

4 15

S4_PWR_EN PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

TP_CPU_RSVDN61

18 8

PP3V3_S5

DBGLED_S0_D

SOT-563

S

18 8

DBGLED GREEN-56MCD-2MA-2.65V LTQH9G-SM

K

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DMN5L06VK-7

SOT-563

S

DBGLED

DBGLED

DMN5L06VK-7

2

DBGLED_S0

DBGLED_S0I3_D DBGLED

DMN5L06VK-7

2

GREEN-56MCD-2MA-2.65V LTQH9G-SM K


DBGLED_S3_D

DBGLED

5% 1/20W MF 201

DBGLED_S0I3

DBGLED

Pin N61 needs a TP for Power to perform iFDIM test Renaming the pins N61 and P61 to remove automatic diffpari property

20K

OUT

31

OUT

16 15

OUT

16 15

OUT

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 XDP_MLB_RAMCFG2 XDP_MLB_RAMCFG3 RAMCFG3:L

R2050

NC

5

CAMERA_PWR_EN

OUT

3

RAMCFG2:L

1

R2051

10K 201

201

1

R2053 5%

1/20W

MF

2

201

1

10K

1/20W

MF

2

RAMCFG0:L

R2052 5%

1/20W

MF

RAMCFG1:L 10K

5%

1/20W

NC

1

10K

5%

MF

201

2

2

R2030 1

A

0

2

5% 1/20W MF 0201

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Project Chipset Support DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

20 OF 120

8

7

6

Page Notes

5

4

CPU-Based Margining

Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PPDDR_S3_MEMVREF

73

FETs for CPU isolation during DAC margining

DDRVREF_DAC

G

73 7

IN

Q2220 DDRVREF_DAC

SOT-563

S

CPU_DIMMA_VREFDQ

1

DMN5L06VK-7

100K

D

5% 1/20W MF 201

6

1

100K

CPU_DIMMA_VREFDQ_A_ISOL

VREFMRGN_DQ_A_EN_RC

2

G

10% 6.3V CERM-X5R 0201

1K

SOT-563

R2223 D

1

R2245 IN

73 7

S

CPU_DIMMB_VREFDQ

DDRVREF_DAC

Q2220

R2215

DMN5L06VK-7

1

5% 1/20W MF 201

D

20% 6.3V CERM 402-LF

1

100K 5% 1/20W MF 201

10% 6.3V CERM-X5R 0201

63 39 19 16 14 72 68

BI

6 SCL

SMBUS_PCH_DATA

PP0V675_S3_MEM_VREFCA_A

MSOP 4 7 5 5 C A D

7 SDA

10 A1

2

VREFMRGN_CA_B_EN_RC

5

DDRVREF_DAC

1K

1% 1/20W MF 201

Q2225

G

DMN5L06VK-7

S

D

332

1

VOUTB 2

VREFMRGN_DQ_B

R2246

332

1

2

VOUTC 4

VREFMRGN_CA_AB

R2266

332

1

2

VOUTD 5

VREFMRGN_MEMVREG

R2286

332

1

2

1/20W

MF

PP0V675_S3_MEM_VREFCA_B

1K 1% 1/20W MF 201 2

C2280

PLACE_NEAR=Q2225.1:2.54mm

VREFMRGN_DQ_B_RDIV 1%

1/20W

MF

201


VREFMRGN_CA_A_RDIV 1%

1/20W

MF

1/20W

MF

R2280

MEM_VREFCA_B_RC

1


201

24.9

2

1% 1/20W MF 201


VREFMRGN_CA_B_RDIV 1%

10% 6.3V X5R-CERM 0201

2

21 65 73

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

R2282 1

0.022UF

R22x6 pin 2:

201

1% 1/20W MF 201 2 PLACE_NEAR=Q2220.3:4mm

PLACE_NEAR=R2281.2:1mm

PLACE_NEAR=Q2220.3:2mm

1%

R2281 1K

2

5% 1/20W MF 201

1

VREFMRGN_DQ_A_RDIV

2

1

2

3

4

2

2

R2226

2

1

24.9 1% 1/20W MF 201

SOT-563

R2283

0.1UF

10% 6.3V CERM-X5R 0201

1

C

2

R2260

MEM_VREFCA_A_RC

(All 4 R’s) DDRVREF_DAC VREFMRGN_DQ_A

10% 6.3V X5R-CERM 0201

C2285 1

20 65 73


R2262

0.022UF 2

CRITICAL DDRVREF_DAC

5% 1/20W MF 201


U2200 VOUTA 1

9 A0

Addr=0x98(WR)/0x99(RD)

100K

1K

PLACE_NEAR=R2261.2:1mm 1

C2260

CPU_DIMM_VREFCA_B_ISOL

R2261


2

5% 1/20W MF 201

R2285

SMBUS_PCH_CLK

1

1

2

6

1

2

PLACE_NEAR=Q2260.6:2mm

8

IN

D

2

24.9 1% 1/20W MF 201

SOT-563

1

VDD 63 39 19 16 14 72 68

1

DMN5L06VK-7

S

0.1UF

73

C2201

2

R2240

MEM_VREFDQ_B_RC

Q2265

R2263

DDRVREF_DAC

0.1UF 2

G

C2265 1 10% 6.3V CERM-X5R 0201

R2207 1 2.2UF

1% 1/20W MF 201 2


DDRVREF_DAC

C2200 1

2

DDRVREF_DAC

21 65 73

1K

10% 6.3V X5R-CERM 0201

2

DDRVREF_DAC

DDRVREF_DAC

VREFMRGN_CA_A_EN_RC

2

3

1 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP0V675_S3_MEM_VREFDQ_B MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

R2242 1

0.022UF 2


5% 1/20W MF 201

100K

SOT-563

100K

1K

PLACE_NEAR=R2241.2:1mm

C2240

CPU_DIMM_VREFCA_A_ISOL

R2241


2

5% 1/20W MF 201 PLACE_NEAR=Q2260.3:2mm

73

PP3V3_S3_VREFMRGN_DAC

2

NONE NONE NONE 402

1

1

2

3

4

2

DDRVREF_DAC

R2218 SHORT

D

2

24.9 1% 1/20W MF 201

SOT-563

1

D

4

1

DMN5L06VK-7

S

0.1UF

R2265

G

MEM_VREFDQ_A_RC

Q2265

D 2

R2220

R2243

C2245 1 10% 6.3V CERM-X5R 0201

1

DAC-Based Margining

1

G

6

CRITICAL 5

1% 1/20W MF 201

10% 6.3V X5R-CERM 0201

2

DAC sets voltage level, PCA9557 & FETs enable outputs and disables margining after platform reset. OMIT PP3V3_S3

5

DDRVREF_DAC

SOT-563

S

42 39 19 18 15 68 65 60

VREFMRGN_DQ_B_EN_RC

2

DMN5L06VK-7

1

NOTE: CPU has single output for VREFCA. Split into two signals for independent DAC margining support. When DAC margining VREFCA ensure VREFMRGN_CPU_EN is low to remove short due to CPU.

C

5% 1/20W MF 201

Q2260

S

CPU_DIMM_VREFCA

100K 5% 1/20W MF 201

100K

CRITICAL 2

G

IN

1

DDRVREF_DAC

R2202 1

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step LPDDR3 (1.2V) ?.??mV per step

73 7

D 3

4

1K

0.022UF 2


20 65 73


R2222

C2220

CPU_DIMMB_VREFDQ_B_ISOL

DDRVREF_DAC

SOT-563

PLACE_NEAR=R2221.2:1mm 1

PLACE_NEAR=Q2220.6:2mm 1

73

DMN5L06VK-7

PP0V675_S3_MEM_VREFDQ_A

2

5% 1/20W MF 201

2

2

Q2260

2

6

1

17 20 21 22 41 55 65 73

R2221


DMN5L06VK-7

CRITICAL G

1

Q2225

S

0.1UF


5

1 PP1V35_S3

Always used, regardless of margining option.

C2225 1

BOM options provided by this page: - DDRVREF_DAC - Stuffs DAC margining circuit.

D

CRITICAL DDRVREF_DAC 2

DDRVREF_DAC

5% 1/20W MF 201

R2201 1

2 VRef Dividers

EN RC’s to avoid drain glitches May not be necessary due to C22x0

R2225

CRITICAL 2

Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA

3

201

GND 3

NOTE: MEMVREG and SPARE share a DAC output, cannot enable both at the same time! PP3V3_S3

B

DDRVREF_DAC 6 1

C2202 1

5% 1/20W MF 201

PCA9557 QFN (OD) 3

A0

Addr=0x30(WR)/0x31(RD)

4 A1 5

A2

72 68 63 39 19 16 14 72 68 63 39 19 16 14

IN BI


1 2

SCL SDA THRM

PAD

7 1

RST* on ’platform reset’ so that system watchdog will disable margining.

GND

10% 6.3V CERM-X5R 0201

100K

U2201

2

P0 P1 P2 P3 P4 P5 P6 P7

RESET*

7 9 10 11 12 13 14

IN

B1 C2

V+

C3

68

B

V-

DDRVREF_DAC

U2204 MAX4253 UCSP C1

R2214 VREFMRGN_MEMVREG_BUF

1

R2213

8

B1 A2

V+ 2 A3

V-

55

VREFMRGN_SPARE_BUF

A4

DDRVREF_DAC 1

DDRVREF_DAC

R2217 1M

Pins B1 & B4: CKPLUS_WAIVE=unconnected_pins

R2212

OUT

U2204 MAX4253 UCSP A1

B4

PCA9557D_RESET_L

DDRREG_FB PLACE_NEAR=R7415.2:1mm

1

100K

5% 1/20W MF 201

2


DDRVREF_DAC

NC

15

33.2K 1% 1/20W MF 201

C4

B4

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles. 18

2

2

VREFMRGN_CPU_EN VREFMRGN_DQ_A_EN VREFMRGN_DQ_B_EN VREFMRGN_CA_A_EN VREFMRGN_CA_B_EN VREFMRGN_MEMVREG_EN VREFMRGN_SPARE_EN

6

1

0.1UF

R2200 1

VCC

0.1UF

10% 6.3V CERM-X5R 0201

C2205


15 18 19 39 42 60 65


DDRVREF_DAC

2

5% 1/20W MF 201

1

100K

A

MEM A VREF DQ DAC Channel: PCA9557D Pin:

MEM B VREF DQ

MEM B VREF CA

B

C

C

D

1

2

3

4

5

0.600V (DAC: 0x2E.5)

5% 1/20W MF 201

MEM VREG

A

LPDDR3 (1.2V) Nominal value

MEM A VREF CA

DDR3L (1.35V)

DDR3L (1.35V)

1.200V (DAC: 0x5D)

1.343V (DAC: 0x68)

0.300V - 0.900V (+/- 300mV)

0.337V - 1.013V (+/- 337.5mV)

0.800V - 1.600V (+/- 400mV)

0.972V - 1.714V (+/- 371mV)

DAC range:

0.000V - 1.199V (0x00 - 0x5D)

0.000V - 1.354V (0x00 - 0x69)

0.000V - 2.397V (0x00 - 0xBA)

0.000V - 2.694V (0x00 - 0xD1)

VRef current:

+73uA - -73uA

+82uA - -82uA

+21uA -

+25uA -

(- = sourced)

-21uA (- = sourced)


DDR3 VREF MARGINING

Margined target:

(- = sourced)

A


LPDDR3 (1.2V)

0.675V (DAC: 0x34)

2

-25uA (- = sourced)

DRAWING NUMBER

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

Apple Inc. R

REVISION


BRANCH


PAGE

22 OF 120

SIZE

D

8 73 65 55 41 22 21 20 19 17

7

PP1V35_S3

73 65 20 19 73 65 20 19

6

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_A

5 73 65 55 41 22 21 20 19 17

20%

1 8 1 9 2 9 1 2 9 2 9 7 2 8 1 9 1 9 8 1 A A C C D E F H H B D G K K N N R R M H

4V CERM-X5R-1 2

201

VDD

VDDQ

73 66 22 20

D

73 66 22 20

MEM_A_A<2>

73 66 22 20

MEM_A_A<3>

73 66 22 20

MEM_A_A<4> MEM_A_A<5>

73 66 22 20 7

MEM_A_A<6>

73 66 22 20

MEM_A_A<7>

73 66 22 20

MEM_A_A<8>

73 66 22 20

MEM_A_A<9>

73 66 22 20

MEM_A_A<10>

73 66 22 20

MEM_A_A<11>

73 66 22 20

MEM_A_A<12>

73 66 22 20

73 66 22 20 73 66 22 20

73 66 22 20 73 66 22 20 7 73 66 22 20

73 66 22 20 7 73 66 22 20 7 73 66 22 20 7

U2300

A C F E R V

Q D F E R V

0.47UF

C2308 10%

6.3V 2 X5R

201

N3 A0 P7 A14GB-DDR3L-1600-256MX16 P3 A2 FBGA NC MT41K256M16HA-125:E N2 A3 P8 A4 OMIT_TABLE P2 A5 R8 A6 DQ0 R2 A7 DQ1 T8 A8 DQ2 R3 A9 DQ3 L7 A10/AP DQ4 R7 A11 DQ5 N7 A12/BC* DQ6 T3 A13 DQ7 T7 A14 DQ8

MEM_A_BA<0>M2 MEM_A_BA<1>N8 MEM_A_BA<2>M3 MEM_A_RAS_LJ3 MEM_A_CAS_LK3 MEM_A_WE_L L3

BA0 BA1 BA2 RAS* CAS*

WE* LDQS

LDQS*

UDQS*

73 22 20 7

73 22 20

K1 MEM_A_ODT<0>

ODT

L8 MEM_A_ZQ<0>

LDM UDM

ZQ

UDQS

C2309

240


4V CERM-X5R-1 2

0.047UF

201

10%

VDD

VDDQ

201

73 66 22 20 73 66 22 20

MEM_A_A<2>

73 66 22 20

MEM_A_A<3>

73 66 22 20


73 66 22 20 7

MEM_A_A<6>

73 66 22 20

MEM_A_A<7>

73 66 22 20

MEM_A_A<8>

73 66 22 20

MEM_A_A<9>

73 66 22 20

MEM_A_A<10>

73 66 22 20

MEM_A_A<11>

73 66 22 20

MEM_A_A<12>

73 66 22 20 73 66 22 20

73 66 22 20 73 66 22 20 7 73 66 22 20

73 66 22 20 7 73 66 22 20 7 73 66 22 20 7

F3 =MEM_A_DQS_P<0> G3 =MEM_A_DQS_N<0>

67

C7 =MEM_A_DQS_P<1> B7 =MEM_A_DQS_N<1>

67

67

E7 D3


U2320

A C F E R V

Q D F E R V

C2328 1 10%

6.3V 2 X5R



201

0.047UF 10% 201

T2 MEM_RESET_L

BA0 BA1 BA2 RAS* CAS*

WE* LDQS

LDQS*

UDQS*

73 22 20 7

CKE CS*

73 22 20

K1 MEM_A_ODT<0>

ODT

MEM_A_ZQ<1>L8

LDM UDM

ZQ

R2320

RESET*

240

VSS

VSSQ

1%

1/20W MF 201

UDQS

2

22 21 20 70

2.2UF

2.2UF

20% 10V X5R-CERM 2 402

67 67

73 65 20 19


67

67

0.47UF

20%

4V CERM-X5R-1 2

1 8 1 9 2 9 1 2 9 2 9 7 2 8 1 9 1 9 8 1 A A C C D E F H H B D G K K N N R R M H VDDQ

MEM_A_A<1>

73 66 22 20

B

73 66 22 20

MEM_A_A<2>

73 66 22 20

MEM_A_A<3>

73 66 22 20


73 66 22 20 7

MEM_A_A<6>

73 66 22 20

MEM_A_A<7>

73 66 22 20

73 66 22 20


73 66 22 20

MEM_A_A<10>

73 66 22 20

MEM_A_A<11>

73 66 22 20

MEM_A_A<12>

73 66 22 20

MEM_A_A<13>

73 66 22 20

MEM_A_A<14>

73 66 22 20

73 66 22 20 73 66 22 20 7 73 66 22 20

73 66 22 20 7 73 66 22 20 7 73 66 22 20 7

73 22 20 7 73 22 20 7

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

10V X5R-CERM 2

10V X5R-CERM 2

10V X5R-CERM 2

10V X5R-CERM 2

10V X5R-CERM 2

10V X5R-CERM 2

10V X5R-CERM 2

20%

402

VDD

U2340

MEM_A_BA<0>M2 MEM_A_BA<1>N8 MEM_A_BA<2>M3

A C F E R V

Q D F E R V

MEM_A_RAS_LJ3 MEM_A_CAS_LK3 MEM_A_WE_L L3

RAS* CAS*

WE* LDQS

J7 CK MEM_A_CLK_P<0> K7 CK* MEM_A_CLK_N<0>

LDQS* UDQS

73 22 20

K1 MEM_A_ODT<0>

ODT

L8 MEM_A_ZQ<2>

ZQ

CKE CS*

UDQS*

LDM UDM

1

240 1%

1/20W MF 201 2

C2348 1

0.047UF 10%

6.3V 2 X5R

201

J1 NC J9 NC L1 NC L9 NC M7 NC

1

73 65 20 19

C2349

4V CERM-X5R-1 2

0.047UF

20%

402

20%

402

20%

402

20%

402

402

67 67 67

1

C2303 10%

2 6.3V CERM-X5R

67

1

0.1UF

67 68 73 67

0201

C2304

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2305

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2313

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2314

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2315

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2323

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2324 0.1UF 10%

2 6.3V CERM-X5R 0201

67


67


67

67

1

C2343 10%

E7 D3

1

0.1UF

2 6.3V CERM-X5R 0201

67

1

C2325

C2344

1

0.1UF 10%

2 6.3V CERM-X5R 0201

1

0.1UF

1

C2365 0.1UF

1 8 1 9 2 9 1 2 9 2 9 7 2 8 1 9 1 9 8 1 A A C C D E F H H B D G K K N N R R M H VDDQ

201

73 66 22 20


73 66 22 20 73 66 22 20

MEM_A_A<2>

73 66 22 20

MEM_A_A<3>

73 66 22 20


67

73 66 22 20 7

MEM_A_A<6>

67

73 66 22 20

MEM_A_A<7>

67

73 66 22 20

67

73 66 22 20


67

73 66 22 20

MEM_A_A<10>

67

73 66 22 20

MEM_A_A<11>

67

73 66 22 20

MEM_A_A<12>

67

73 66 22 20

MEM_A_A<13>

67

73 66 22 20

MEM_A_A<14>

73 66 22 20

67 67

73 66 22 20

67

73 66 22 20 7

67

73 66 22 20

67 67

73 66 22 20 7

67

73 66 22 20 7


73 66 22 20 7 67 67

73 22 20 7 73 22 20 7

67 67

U2360

A C F E R V

Q D F E R V

T2 MEM_RESET_L


RAS* CAS*

WE* LDQS


LDQS* UDQS

73 22 20

K1 MEM_A_ODT<0>

ODT

MEM_A_ZQ<3>L8

ZQ

VSSQ

VSS

240 1%

1/20W MF 201 2

22 21 20 70

10%

6.3V 2 X5R

201


1

C2333

2 6.3V CERM-X5R 0201

1

0.1UF 10%

0201

1

0.1UF 10%

C2345

2 6.3V CERM-X5R

C2334

0.1UF 10%

0201

1

0.1UF 10%

2 6.3V CERM-X5R 0201

C2353

2 6.3V CERM-X5R

1

C2354 0.1UF 10%

2 6.3V CERM-X5R 0201

1

C2355 0.1UF 10%

2 6.3V CERM-X5R 0201

1

C2363 0.1UF 10%

2 6.3V CERM-X5R 0201

1

C2364 0.1UF 10%

2 6.3V CERM-X5R 0201

C

C2335 0.1UF 10%

2 6.3V CERM-X5R 0201

1

C2373 0.1UF 10%

2 6.3V CERM-X5R 0201

1

C2374 0.1UF 10%

2 6.3V CERM-X5R 0201

1

C2375 0.1UF 10%

2 6.3V CERM-X5R 0201

C2369

0.047UF 10%

2 6.3V X5R

201

E3 =MEM_A_DQ<48> F7 =MEM_A_DQ<49> F2 =MEM_A_DQ<50> F8 =MEM_A_DQ<51> H3 =MEM_A_DQ<52> H8 =MEM_A_DQ<53> G2 =MEM_A_DQ<54> H7 =MEM_A_DQ<55> D7 =MEM_A_DQ<56> DQ9 C3 =MEM_A_DQ<57> DQ10 C8 =MEM_A_DQ<58> DQ11 C2 =MEM_A_DQ<59> DQ12 A7 =MEM_A_DQ<60> DQ13 A2 =MEM_A_DQ<61> DQ14 B8 =MEM_A_DQ<62> DQ15 A3 =MEM_A_DQ<63>

BA0 BA1 BA2

73 22 20 7

R2360

RESET*

1 9 1 8 2 8 9 1 9 9 3 1 8 2 8 1 9 1 9 1 9 B B D D E E F G G A B E G J J M M P P T T

C2368 1

0.047UF


K9 MEM_A_CKE<0> L2 MEM_A_CS_L<0>

73 22 20 7

VDD

CKE CS*

UDQS*

LDM UDM

F3 MEM_A_DQS_P<6> G3 MEM_A_DQS_N<6>

B 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67

7 67 73 7 67 73

C7 =MEM_A_DQS_P<7> B7 =MEM_A_DQS_N<7> E7 D3

67 67

SYNC_MASTER=MASTER PAGE TITLE

A

SYNC_DATE=MASTER

DDR3 SDRAM Bank A (Rank 0)

1 22 21 20 70

20%

402


201

10%


E7 D3

20%

2 6.3V X5R

E3 =MEM_A_DQ<32> F7 =MEM_A_DQ<33> F2 =MEM_A_DQ<34> F8 =MEM_A_DQ<35> H3 =MEM_A_DQ<36> H8 =MEM_A_DQ<37> G2 =MEM_A_DQ<38> H7 =MEM_A_DQ<39> D7 =MEM_A_DQ<40> DQ9 C3 =MEM_A_DQ<41> DQ10 C8 =MEM_A_DQ<42> DQ11 C2 =MEM_A_DQ<43> DQ12 A7 =MEM_A_DQ<44> DQ13 A2 =MEM_A_DQ<45> DQ14 B8 =MEM_A_DQ<46> DQ15 A3 =MEM_A_DQ<47>

BA0 BA1 BA2

73 22 20 7

R2340

20%

402

VSS

73 65 20 19

0.47UF



73 22 20 7

A

MEM_A_A<0>

20% 10V X5R-CERM 2 402

C2367 1

201

73 66 22 20

2.2UF

20% 10V X5R-CERM 2 402

2.2UF

10%

C2347 1

2.2UF

20% 10V X5R-CERM 2 402

67

2 6.3V CERM-X5R 0201

PP1V35_S3

2.2UF

20% 10V X5R-CERM 2 402

10V X5R-CERM 2

20%

67

10%

VSSQ

73 65 55 41 22 21 20 19 17

2.2UF

20% 10V X5R-CERM 2 402

C2340 1 C2341 1 C2350 1 C2351 1 C2360 1 C2361 1 C2370 1 C2371 1

67

0201

73 65 20 19

D 2.2UF

20% 10V X5R-CERM 2 402

67

2 6.3V CERM-X5R

PP1V35_S3

2.2UF

20% 10V X5R-CERM 2 402

67


2

17 19 20 21 22 41 55 65 73

C2300 1 C2301 1 C2310 1 C2311 1 C2320 1 C2321 1 C2330 1 C2331 1

T2 RESET* MEM_RESET_L

1%

1/20W MF 201


73 65 55 41 22 21 20 19 17

1

SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP) PP1V35_S3

1 22 21 20 70

2

C2329

2 6.3V X5R


E3 =MEM_A_DQ<16> F7 =MEM_A_DQ<17> F2 =MEM_A_DQ<18> F8 =MEM_A_DQ<19> H3 =MEM_A_DQ<20> H8 =MEM_A_DQ<21> G2 =MEM_A_DQ<22> H7 =MEM_A_DQ<23> D7 =MEM_A_DQ<24> DQ9 C3 =MEM_A_DQ<25> DQ10 C8 =MEM_A_DQ<26> DQ11 C2 =MEM_A_DQ<27> DQ12 A7 MEM_A_DQ<32> 7 DQ13 A2 =MEM_A_DQ<29> DQ14 B8 =MEM_A_DQ<30> DQ15 A3 =MEM_A_DQ<31>


73 22 20 7

1

0.047UF


73 22 20 7 73 22 20 7

67


73 66 22 20

73 66 22 20

1

R2300

20%

2 6.3V X5R

E3 =MEM_A_DQ<0> 67 F7 =MEM_A_DQ<1> 67 F2 =MEM_A_DQ<2> 67 F8 =MEM_A_DQ<3> 67 H3 =MEM_A_DQ<4> 67 H8 =MEM_A_DQ<5> 67 G2 =MEM_A_DQ<6> 67 H7 =MEM_A_DQ<7> 67 D7 =MEM_A_DQ<8> 67 DQ9 C3 =MEM_A_DQ<9> 67 DQ10 C8 =MEM_A_DQ<10> 67 DQ11 C2 =MEM_A_DQ<11> 67 DQ12 A7 =MEM_A_DQ<12> 67 DQ13 A2 =MEM_A_DQ<13> 67 DQ14 B8 =MEM_A_DQ<14> 67 DQ15 A3 =MEM_A_DQ<15> 67

CKE CS*

73 22 20 7

1



73 22 20 7

1

0.047UF


73 22 20 7

C


73 65 20 19

3


C2327 1

0.47UF


4 73 65 20 19

C2307 1

73 66 22 20

PP1V35_S3

DRAWING NUMBER

T2 RESET* MEM_RESET_L VSSQ

Apple Inc.

VSS R


NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

SIZE

D

REVISION

BRANCH

PAGE

23 OF 120

SHEET

8 73 65 55 41 22 21 20 19 17

7

PP1V35_S3

73 65 21 19 73 65 21 19

6

5

PP0V675_S3_MEM_VREFCA_B PP0V675_S3_MEM_VREFDQ_B

73 65 55 41 22 21 20 19 17

0.47UF


VDDQ

73 66 22 21

D

73 66 22 21

MEM_B_A<2>

73 66 22 21

MEM_B_A<3>

73 66 22 21

MEM_B_A<4> MEM_B_A<5>

73 66 22 21 7

MEM_B_A<6>

73 66 22 21

MEM_B_A<7>

73 66 22 21

MEM_B_A<8>

73 66 22 21

73 66 22 21


73 66 22 21

MEM_B_A<11>

73 66 22 21

MEM_B_A<12>

73 66 22 21

73 66 22 21 73 66 22 21

73 66 22 21 73 66 22 21 7 73 66 22 21

73 66 22 21 7 73 66 22 21 7 73 66 22 21 7

73 22 21 7 73 22 21 7

VDD

U2500

A C F E R V

Q D F E R V

0.47UF

C2508 1

MEM_B_BA<0>M2 MEM_B_BA<1>N8 MEM_B_BA<2>M3

BA0 BA1 BA2

MEM_B_RAS_LJ3 MEM_B_CAS_LK3 MEM_B_WE_L L3

RAS* CAS* WE*

73 22 21 7

73 22 21

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<0>L8

10% 6.3V 2 X5R 201

20% 4V CERM-X5R-1 2 201

C2509

0.047UF 10%

VDDQ

201


73 66 22 21 73 66 22 21

240

MEM_B_A<3>

73 66 22 21


73 66 22 21 7

MEM_B_A<6>

73 66 22 21

MEM_B_A<7>

73 66 22 21

MEM_B_A<8>

73 66 22 21


73 66 22 21

MEM_B_A<11>

73 66 22 21

MEM_B_A<12>

73 66 22 21 73 66 22 21

73 66 22 21 73 66 22 21 7 73 66 22 21

73 66 22 21 7 73 66 22 21 7 73 66 22 21 7

F3 =MEM_B_DQS_P<0> G3 =MEM_B_DQS_N<0>

67

UDQS UDQS*

C7 =MEM_B_DQS_P<1> B7 =MEM_B_DQS_N<1>

67

LDM UDM

MEM_B_A<2>

73 66 22 21

73 66 22 21

LDQS LDQS*

67

73 22 21 7 73 22 21 7

67


U2520


BA0 BA1 BA2


RAS* CAS* WE*

A C F E R V

Q D F E R V

C2528 1

73 22 21 7

73 22 21

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<1>L8

1

0.047UF

10% 6.3V 2 X5R 201

0.047UF 10% 201


T2 MEM_RESET_L

R2520

RESET* VSSQ

1% 1/20W MF

240

VSS


201 2

22 21 20 70

T2 MEM_RESET_L

2.2UF

67 67

2

73 65 21 19 73 65 21 19


2.2UF

67

2.2UF

20% 10V X5R-CERM 2 402

67 67

0.47UF

20% 4V CERM-X5R-1 2 201

73 66 22 21


73 66 22 21

MEM_B_A<3>

73 66 22 21

MEM_B_A<4>

73 66 22 21

MEM_B_A<5>

73 66 22 21

B

73 66 22 21


73 66 22 21

MEM_B_A<8>

73 66 22 21

MEM_B_A<9>

73 66 22 21 7

73 66 22 21


73 66 22 21

MEM_B_A<12>

73 66 22 21

MEM_B_A<13>

73 66 22 21

MEM_B_A<14>

73 66 22 21

73 66 22 21 73 66 22 21 7 73 66 22 21

73 66 22 21 7 73 66 22 21 7 73 66 22 21 7

73 22 21 7 73 22 21 7

VDD

U2540


A C F E R V

Q D F E R V


RAS* CAS* WE*

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0>

73 22 21 7

73 22 21

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<2>L8

ZQ

240 1%

2

10% 6.3V 2 X5R 201


1

20% 10V X5R-CERM 2 402

2.2UF

20% 10V X5R-CERM 2 402

2.2UF

20% 10V X5R-CERM 2 402

2.2UF

20% 10V X5R-CERM 2 402

2.2UF

20% 10V X5R-CERM 2 402

2.2UF

20% 10V X5R-CERM 2 402

20% 10V X5R-CERM 2 402

67 67 67

1

C2503

1

0.1UF

67

10%

2 6.3V CERM-X5R

67

0201

67

C2504

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2505

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2513

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2514

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2515

1

0.1UF 10%

2 6.3V CERM-X5R

0201

1

0.1UF 10%

0201


67

UDQS UDQS*


67

67

1

C2543 0.1UF 10%

2 6.3V CERM-X5R

0201

67

E7 D3

1

C2544

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2545

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2553

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2554 0.1UF 10%

2 6.3V CERM-X5R

0201

1

C2555

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2563 0.1UF 10%

2 6.3V CERM-X5R

0201

C2524 0.1UF 10%

2 6.3V CERM-X5R

0201

1

C2564 0.1UF 10%

2 6.3V CERM-X5R

0201

C 1

C2525

1

0.1UF 10%

C2533

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2534

1

0.1UF 10%

2 6.3V CERM-X5R

0201

C2535 0.1UF 10%

2 6.3V CERM-X5R

0201

VSS 1

C2565 0.1UF

73 65 21 19

1

C2573 0.1UF 10%

2 6.3V CERM-X5R

0201

1

C2574 0.1UF 10%

2 6.3V CERM-X5R

0201

1

C2575 0.1UF 10%

2 6.3V CERM-X5R

0201


C2549

0.047UF 10%

73 66 22 21

MEM_B_A<0>

73 66 22 21


73 66 22 21

MEM_B_A<3>

73 66 22 21

MEM_B_A<4>

73 66 22 21

MEM_B_A<5>

73 66 22 21

67

73 66 22 21 7

67

73 66 22 21


67

73 66 22 21

MEM_B_A<8>

67

73 66 22 21

MEM_B_A<9>

67

73 66 22 21

67

73 66 22 21


73 66 22 21

MEM_B_A<12>

73 66 22 21

MEM_B_A<13>

73 66 22 21

MEM_B_A<14>

67 67 67 67 67

73 66 22 21

67

73 66 22 21 7

67 68 73

73 66 22 21

67 67

73 66 22 21 7

67

73 66 22 21 7 73 66 22 21 7

UDQS UDQS*

C7 =MEM_B_DQS_P<5> B7 =MEM_B_DQS_N<5> E7 D3


VDDQ

201

F3 MEM_B_DQS_P<6> G3 MEM_B_DQS_N<6>

LDM UDM

20% 4V CERM-X5R-1 2 201

7 67 73 7 67 73

73 22 21 7 73 22 21 7

67 67

U2560

A C F E R V

Q D F E R V

C2568 1

0.047UF



BA0 BA1 BA2


RAS* CAS* WE*

73 22 21 7

CKE CS*

73 22 21

K1 MEM_B_ODT<0>

ODT

MEM_B_ZQ<3>L8

ZQ

10% 6.3V 2 X5R 201


1

C2569

0.047UF 10%

2 6.3V X5R

201

E3 =MEM_B_DQ<48> F7 =MEM_B_DQ<49> F2 =MEM_B_DQ<50> F8 =MEM_B_DQ<51> H3 =MEM_B_DQ<52> H8 =MEM_B_DQ<53> G2 =MEM_B_DQ<54> H7 =MEM_B_DQ<55> D7 =MEM_B_DQ<56> DQ9 C3 =MEM_B_DQ<57> DQ10 C8 =MEM_B_DQ<58> DQ11 C2 =MEM_B_DQ<59> DQ12 A7 =MEM_B_DQ<60> DQ13 A2 =MEM_B_DQ<61> DQ14 B8 =MEM_B_DQ<62> DQ15 A3 =MEM_B_DQ<63>

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0> K9 MEM_B_CKE<0> L2 MEM_B_CS_L<0>

73 22 21 7

VDD

B 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67 67

LDQS LDQS*


UDQS UDQS*


LDM UDM

E7 D3

67 67

67 67

SYNC_MASTER=MASTER

T2 MEM_RESET_L

R2560

RESET* VSSQ

VSS


240 1%

1/20W MF 201 2

22 21 20 70

T2 MEM_RESET_L

A

SYNC_DATE=MASTER

PAGE TITLE

DDR3 SDRAM BANK B (RANK 0)

1 22 21 20 70

C2523

2 6.3V CERM-X5R

67

0201

2 6.3V X5R

LDQS LDQS*

1

1/20W MF 201

C2548

0.047UF

1

E3 =MEM_B_DQ<32> F7 =MEM_B_DQ<33> F2 =MEM_B_DQ<34> F8 =MEM_B_DQ<35> H3 =MEM_B_DQ<36> H8 =MEM_B_DQ<37> G2 =MEM_B_DQ<38> H7 =MEM_B_DQ<39> D7 =MEM_B_DQ<40> DQ9 C3 =MEM_B_DQ<41> DQ10 C8 =MEM_B_DQ<42> DQ11 C2 =MEM_B_DQ<43> DQ12 A7 MEM_B_DQ<32> 7 DQ13 A2 =MEM_B_DQ<45> DQ14 B8 =MEM_B_DQ<46> DQ15 A3 =MEM_B_DQ<47>

BA0 BA1 BA2

CKE CS*

R2540

2.2UF

20% 10V X5R-CERM 2 402

2 6.3V CERM-X5R

PP1V35_S3

0.47UF


K9 MEM_B_CKE<0> L2 MEM_B_CS_L<0>

73 22 21 7

A

MEM_B_A<0>

2.2UF

20% 10V X5R-CERM 2 402

C2567 1 1 8 1 9 2 9 1 2 9 2 9 7 2 8 1 9 1 9 8 1 A A C C D E F H H B D G K K N N R R M H

VDDQ 73 66 22 21

2.2UF

20% 10V X5R-CERM 2 402

RESET*

73 65 21 19

C2547 1

2.2UF

20% 10V X5R-CERM 2 402

67

10%

73 65 55 41 22 21 20 19 17

2.2UF

20% 10V X5R-CERM 2 402

C2540 1 C2541 1 C2550 1 C2551 1 C2560 1 C2561 1 C2570 1 C2571 1

67

0201

PP1V35_S3

2.2UF

20% 10V X5R-CERM 2 402

67

2 6.3V CERM-X5R

73 65 55 41 22 21 20 19 17

2.2UF

20% 10V X5R-CERM 2 402

67


201

2.2UF

20% 10V X5R-CERM 2 402

ZQ

VSSQ

1% 1/20W MF

D

17 19 20 21 22 41 55 65 73

C2500 1 C2501 1 C2510 1 C2511 1 C2520 1 C2521 1 C2530 1 C2531 1

LDQS LDQS*

LDM UDM

SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP) PP1V35_S3

1 22 21 20 70

1

C2529

2 6.3V X5R

E3 =MEM_B_DQ<16> F7 =MEM_B_DQ<17> F2 =MEM_B_DQ<18> F8 =MEM_B_DQ<19> H3 =MEM_B_DQ<20> H8 =MEM_B_DQ<21> G2 =MEM_B_DQ<22> H7 =MEM_B_DQ<23> D7 =MEM_B_DQ<24> DQ9 C3 =MEM_B_DQ<25> DQ10 C8 =MEM_B_DQ<26> DQ11 C2 =MEM_B_DQ<27> DQ12 A7 =MEM_B_DQ<28> DQ13 A2 =MEM_B_DQ<29> DQ14 B8 =MEM_B_DQ<30> DQ15 A3 =MEM_B_DQ<31>

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0> CKE CS*

ZQ

VDD



73 22 21 7

E7 D3


73 66 22 21

73 66 22 21

1

R2500

2



2 6.3V X5R

E3 =MEM_B_DQ<0> 67 F7 =MEM_B_DQ<1> 67 F2 =MEM_B_DQ<2> 67 F8 =MEM_B_DQ<3> 67 H3 =MEM_B_DQ<4> 67 H8 =MEM_B_DQ<5> 67 G2 =MEM_B_DQ<6> 67 H7 =MEM_B_DQ<7> 67 D7 =MEM_B_DQ<8> 67 DQ9 C3 =MEM_B_DQ<9> 67 DQ10 C8 =MEM_B_DQ<10> 67 DQ11 C2 =MEM_B_DQ<11> 67 DQ12 A7 =MEM_B_DQ<12> 67 DQ13 A2 =MEM_B_DQ<13> 67 DQ14 B8 =MEM_B_DQ<14> 67 DQ15 A3 =MEM_B_DQ<15> 67

J7 CK MEM_B_CLK_P<0> K7 CK* MEM_B_CLK_N<0> CKE CS*

1

0.047UF



73 22 21 7

C


3

C2527 1

20% 4V CERM-X5R-1 2 201


73 65 21 19 73 65 21 19

C2507 1

73 66 22 21

PP1V35_S3

4

DRAWING NUMBER

RESET* VSSQ

VSS


Apple Inc. R

NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

SIZE

D

REVISION

BRANCH

PAGE

25 OF 120

SHEET

8

7

6

5

4

3

2

Memory CMD/CTL Termination - Channel A Memory ODT Option

73 68 65 55 22

MEM_ODT:CPU drives ODT from CPU, terminated to 0.675V VTT. MEM_ODT:PU disconnect ODT from CPU, ODT pins on DRAM pulled up to 1.35V VDDQ. 73 68 65 55 22

D

73 65 55 41 22 21 20 19 17

PP0V675_S0_DDRVTT PP1V35_S3

73 66 20 7

IN

73 66 20 7

IN

73 66 20 7

IN IN

73 66 20 73 66 20

MEM_ODT:PU

73 66 20

R2782 73 20

IN

MEM_A_ODT<0> (Connects to DRAM)

66 7

IN

36

1

MEM_ODT:CPU

MAKE_BASE=TRUE

MEM_A_ODT_CPU0 (Connects to CPU)

MEM_ODT:CPU

R2780

R2781

1

1

PLACE_NEAR=U0500.AP32:8MM

0.00 2 1% 1/20W MF 0201

36

73 66 20

2

5% 1/20W MF 201

2

73 66 20

IN

IN

MEM_ODT:PU

R2792 IN

MEM_B_ODT<0> (Connects to DRAM)

MEM_ODT:CPU

MAKE_BASE=TRUE

66 7

IN

36

1

73 66 20 7

IN

73 66 20

IN

73 66 20

IN

MEM_A_A<10>

MEM_B_ODT_CPU0 (Connects to CPU)

R2790

R2791

1

1

0.00 2 1% 1/20W MF 0201

PLACE_NEAR=U0500.AL32:8MM

36

IN

IN

73 66 20

IN

73 66 20

IN

73 66 20

IN

MEM_A_A<12> MEM_A_A<1> MEM_A_A<11> MEM_A_A<14>

RP2702 RP2702 RP2702 RP2702 RP2703 RP2703 RP2703 RP2703

36 36 36 36 36 36 36 36

1

8

2

7

3

6

4

5

1

8

2

RP2705 RP2706 RP2706 RP2706

36 36 36 36

RP2705

36

RP2705 RP2707 RP2707 RP2707

36 36 36 36

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

7

5%

1/32W

4X0201

3

6

5%

1/32W

4X0201

4

5

5%

1/32W

4X0201

5%

1/32W

4X0201

1

8

2

7

3

6

4

5

2

7

4

5

2

7

3

6

4

5

1

RP2704

C2700 20%

2

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

RP2704 1

C2702

1

2

4V

CERM-X5R-1 201

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

73 20 7 73 66 20

2

IN

73 66 20

IN IN

73 66 20

C

IN IN

73 66 20

73 20 7

IN

MEM_A_CS_L<0> MEM_A_BA<0> MEM_A_A<3> MEM_A_A<5> MEM_A_A<7>

MEM_A_CKE<0>

RP2701 RP2701 RP2701 RP2707 RP2706 RP2704

36

2

7

3

6

4

5

1

8

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

36

4

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

2

C2704

1

1/32W

8

NC

5% 1/32W 4X0201

4V

CERM-X5R-1 201

2

4V

CERM-X5R-1 201

C2705

36

1

NC

0.47UF

20%

2

8

NC

5% 1/32W 4X0201

20%

4V

CERM-X5R-1 201

RP2704 1

C2706

1

0.47UF

1

4V

CERM-X5R-1 201

36

3

NC

C2707 20%

2

6

NC

5% 1/32W 4X0201

0.47UF 4V

CERM-X5R-1 201

C2708

22 7

IN

22 7

IN

22 7

0.47UF

MAKE_BASE=TRUE MAKE_BASE=TRUE

NC_MEM_A_CKE1 MAKE_BASE=TRUE

NC_MEM_A_A15

IN

NO_TEST=TRUE 7 22 NO_TEST=TRUE 7 22

NC_MEM_A_CS_L1

NC_MEM_A_CS_L1 NC_MEM_A_CKE1

NO_TEST=TRUE 7 22

NC_MEM_A_A15

20%

2

5 5%

36

1

NC

20%

RP2701 1

2

36 36 36 36

C2703 0.47UF

0.47UF

5%

D

NC

1/32W 4X0201

CERM-X5R-1 201

20%

1/32W

7

5%

4V

0.47UF

5%

36

2

NC

0.47UF

20%

5% 1/20W MF 201

MEMORY RPACK SPARES

PP0V675_S0_DDRVTT

2

5% 1/20W MF 201

MEM_ODT:CPU

MEM_A_A<0> MEM_A_A<2> MEM_A_A<9> MEM_A_A<13> MEM_A_BA<1> MEM_A_A<4> MEM_A_A<6> MEM_A_A<8>

73 66 20

73 21

IN IN

73 66 20 7 73 66 20

5% 1/20W MF 201

IN

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_BA<2>

1

4V

CERM-X5R-1 201

1

36

3

NC

C2710

6

NC

5% 1/32W 4X0201

0.47UF 20%

2

C

RP2705

4X0201

4V

CERM-X5R-1 201

Memory Reset Pull Up Reset is an open drain in Haswell ULT and needs pull up PP1V35_S3

17 19 20 21 22 41 55 65

Memory CMD/CTL Termination - Channel B

73

R2710

1

73 68 65 55 22

470

2

1% 1/20W MF 201

R2711 MEM_RESET_HSW_L

66 6

1

0

MEM_RESET_L

2

5% 1/20W MF 0201

1

20 21 70

NO STUFF

C2711

IN

73 66 21 7

IN

73 66 21 7

IN

73 66 21

IN

73 66 21

0.47UF

2

73 66 21 7

20%

73 66 21

IN

CERM-X5R-1 201

73 66 21

IN

73 66 21

IN

73 66 21

IN

4V

B

73 66 21

Memory Clock Near-End Termination

Memory Clock Far-End Termination

Place Source C termination before first DRAM

Place RC end termination after last DRAM

C2751

R2750 IN

MEM_A_CLK_N<0>

73 22 20 7

IN

MEM_A_CLK_N<0>

1

30

2

0.1UF

MEM_A_CLK0_TERM_R

5% MF

201

3.3PF 5%

25V CERM 2 201 73 22 20 7

IN

MEM_A_CLK_P<0>

1

2

10% 6.3V CERM-X5R 0201

1/20W

C2750 1

R2751 73 22 20 7

IN

MEM_A_CLK_P<0>

1

30

2

5% 1/20W

MF

201

IN

73 66 21

IN

IN

MEM_B_CLK_N<0>

73 22 21 7

IN

MEM_B_CLK_N<0>

1

30

2

5%

C2760 1

A

MF

201

3.3PF 5%

25V CERM 2 201 73 22 21 7

IN

MEM_B_CLK_P<0>

R2761 73 22 21 7

IN

MEM_B_CLK_P<0>

1

30

0.1UF

MEM_B_CLK0_TERM_R

1

2

10% 6.3V CERM-X5R 0201

1/20W

73 66 21 7 73 66 21

IN IN IN

73 66 21

IN

73 66 21

IN

4

5

3

6

2

7

1

8 5

MEM_B_A<2> MEM_B_A<9> MEM_B_A<13>

36 36 36 36 36 36 36 36

MEM_B_A<10> MEM_B_A<4> MEM_B_A<6> MEM_B_A<8>

RP2725 RP2724 RP2724 RP2724 RP2725 RP2725 RP2726 RP2726 RP2726

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_BA<2> MEM_B_A<0>

MEM_B_A<12> MEM_B_BA<1> MEM_B_A<1> MEM_B_A<11> MEM_B_A<14>

4

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

3

6

2

7

1

8

36 36 36 36

4

5

3

6

2

7

5%

1/32W

4X0201

1

8

5%

1/32W

4X0201

5%

1/32W

4X0201

36 36 36 36 36

2

7

1

8

5%

1/32W

4X0201

3

6

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1

C2720

RP2725

0.47UF 20%

2

1

NC

4V

CERM-X5R-1 201

C2722

1

1

CERM-X5R-1 201

C2724

1

2

7

1

8

4V

CERM-X5R-1 201

73 21 7

IN

73 66 21

IN

73 66 21

IN

73 66 21

IN

73 66 21

IN

73 21 7

IN

MEM_B_CS_L<0> MEM_B_BA<0> MEM_B_A<3> MEM_B_A<5> MEM_B_A<7>

MEM_B_CKE<0>

RP2720

1

RP2720 RP2720 RP2726 RP2724

36 36 36 36

7

1

8

5%

1/32W

4X0201

4

5

5%

1/32W

4X0201

4

5

5%

1/32W

4X0201

36

1

1/32W

4X0201

C2726 4V

CERM-X5R-1 201

1/32W

NC

RP2728 36

C2725 NC

4V

4

5

NC

5%

CERM-X5R-1 201

1/32W 4X0201

1

C2727

NC

0.47UF

4

36

CERM-X5R-1 201

NC

C2728

2

7

NC

5% 1/32W 4X0201

20%

4V

CERM-X5R-1 201

4X0201

1

NC

1/32W 4X0201

4V

0.47UF

2

5

5%

20%

2

RP2728 36

1

8 5%

6 5%

4X0201

2

5%

RP2728

1/32W

3

1/32W 4X0201

20%

2

0.47UF

6 5%

CERM-X5R-1 201

RP2720

2

36 3

NC

4V

0.47UF

20%

B

36

20%

2

0.47UF

2

NC

RP2728

C2723 0.47UF

20%

4V

6

5%

0.47UF

2

36

3

1/32W 4X0201

20%

C2761

R2760 73 22 21 7

IN

73 66 21 7

73 66 21

73 22 20 7

IN

PP0V675_S0_DDRVTT

RP2722 RP2722 RP2722 RP2722 RP2730 RP2730 RP2730 RP2730

C2730 0.47UF

22 7

IN

22 7

IN

22 7

IN

NC_MEM_B_A15 NC_MEM_B_CS_L1 NC_MEM_B_CKE1

MAKE_BASE=TRUE

NC_MEM_B_A15 MAKE_BASE=TRUE

NO_TEST=TRUE 7 22 NO_TEST=TRUE 7 22 NO_TEST=TRUE 7 22

NC_MEM_B_CS_L1 MAKE_BASE=TRUE

NC_MEM_B_CKE1

20%

2

A

4V

CERM-X5R-1 201

SYNC_MASTER=J44_YONAS-4GB PAGE TITLE


DDR3 Termination

2

DRAWING NUMBER

5% 1/20W

Apple Inc.

MF

201 R

SIZE

D

REVISION


BRANCH


PAGE

27 OF 120

8

7

6

5

4

3

2

1

CRITICAL OMIT_TABLE 70 68 14

IN

PCIE_TBT_R2D_C_P<0>

C2800

1

70 68 14

IN

PCIE_TBT_R2D_C_N<0>

C2801

1

IN

PCIE_TBT_R2D_C_P<1>

C2802

1

70 68 14

C2803

1

PCIE_TBT_R2D_C_P<2>

C2804

1

IN

PCIE_TBT_R2D_C_N<2>

C2805

1

70 68 14

IN

PCIE_TBT_R2D_C_P<3>

C2806

1

70 68 14

IN

PCIE_TBT_R2D_C_N<3>

C2807

1

70 68 14

IN

D

70 68 14

X5R-CERM 0201 X5R-CERM 0201

2

16V

X5R-CERM 0201

16V X5R-CERM 10%

2

0.1UF

16V

X5R-CERM 0201

2

16V

16V

X5R-CERM 0201

PP3V3_TBTLC

R28901 3.3K 5% 1/20W MF 201

2

1

R2891 3.3K

5% 1/20W MF 2201

C2890

R2892

1UF

3.3K

10% 6.3V 2 CERM 402

5% 1/20W MF 2012

CRITICAL OMIT_TABLE

8

R2815

R2893

NOSTUFF

NONE NONE NONE 0201 2

3.3K

5% 1/20W MF 2 201

(TBT_SPI_CLK)

6 CLK 4MBIT 1 CS*W25X40CLXIG USON 3 WP*

TBTROM_WP_L TBTROM_HOLD_L

DO/IO1 2

U2890

1

R2829

5% 1/20W MF 2012

18 16

IN

18

IN

18 16 18

100

IN OUT

74 23

5% 1/20W MF 2 201

74 23

74 23 74 23

74 23 74 23

74 23 74 23

74 23

74 5

B

DP_TBTSNK0_ML_C_N<0>

C2821

1

0.1UF

74 5

IN

DP_TBTSNK0_ML_C_P<1>

C2822

1

74 5

IN


C2823

1

74 5

IN


C2824

1

IN


C2825

1

74 5

IN


C2826

1

74 5

IN


C2827

1

74 5

74 13

74 13

0.1UF 0.1UF 0.1UF 0.1UF

0.1UF

BI

DP_TBTSNK0_AUXCH_C_P

C2828

1

BI

DP_TBTSNK0_AUXCH_C_N

C2829

1

0.1UF 0.1UF


IN


C2831

1

74 64

IN


C2832

1

74 64

74 64

1

0.1UF 0.1UF 0.1UF


C2833

1

0.1UF

IN


IN


C2834

1

C2835

1

0.1UF 0.1UF

74 64

IN


C2836

1

74 64

IN


C2837

1

74 64

BI

2

10% 16V

X5R-CERM 2

10% 16V

X5R-CERM 2

10% 16V

X5R-CERM 2

10%

16V

X5R-CERM 2

0.1UF 0.1UF

DP_TBTSNK1_AUXCH_C_P

C2838

0201

DP_TBTSNK0_ML_N<0> 0201

13 23 74

23 74

DP_TBTSNK0_ML_P<1>

23 74

DP_TBTSNK0_ML_N<1>

23 74

DP_TBTSNK0_ML_P<2>

23 74

DP_TBTSNK0_ML_N<2>

23 74

0201 0201

R2830

0201

2

10% 16V

X5R-CERM 2

1

74 23

100K

74 23

5% 1/20W MF 201 2

74 23 74 23

74 23

74 23 74 23

1

0.1UF

DP_TBTSNK0_ML_P<3> 0201

DP_TBTSNK0_ML_N<3>

74 23

10% 16V 0201 X5R-CERM 2

10% 16V

X5R-CERM 2

X5R-CERM

2

23 74

0201

10% 16V

X5R-CERM 2

10% 16V

X5R-CERM 2

10% 16V

X5R-CERM 2

10% 16V

X5R-CERM 2

DP_TBTSNK1_ML_P<0>

23 74

DP_TBTSNK1_ML_N<0>

23 74

DP_TBTSNK1_ML_P<1>

23 74

0201

0201


DP_TBTSNK1_ML_P<2> 0201


10% 16V

X5R-CERM

5% 1/20W MF 201 2

OUT

74 68 26

OUT

74 68 26

IN

74 68 26

IN

26

IN IN

74 68 26

OUT

74 68 26

OUT

74 68 26

IN IN

26

OUT

26

IN

74 26

OUT

74 26

OUT

74 26

OUT

74 26

OUT

23 74

23 74

23 74

23 74

0201

1

C2841

1

C2842

1

C2843

1

C2844

1

C2845

1

C2846

1

C2847

1

0.1UF

68 70 68

PCIE_TBT_D2R_C_P<1> PCIE_TBT_D2R_C_N<1>

0.1UF

PETP_2 AD13 PETN_2 AD15

70 68 70 68


0.1UF 0.1UF

70 68 70 68


0.1UF

RSENSE U20

AA2 Y3 T5 U8

EE_DI EE_DO EE_CS_N EE_CLK

JTAG_ISP_TDI JTAG_TBT_TMS JTAG_ISP_TCK JTAG_TBT_TDO TBT_TEST_EN TBT_TEST_PWR_GOOD

W2 AB1 AA6 U6 R6 W8

TDI TMS TCK TDO TEST_EN TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3> DP_TBTSNK0_ML_N<3>

RBIAS W20

E16 DPSNK0_2_P D15 DPSNK0_2_N





DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N


C S I M




DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

H3 DPSNK1_AUX_P H1 DPSNK1_AUX_N

DP_TBTSNK1_HPD

U4 DPSNK1_HPD

14 68 70

OUT

2

14 68 70

PCIE_TBT_D2R_P<1>

OUT

14 68 70

PCIE_TBT_D2R_N<1>

OUT

14 68 70

PCIE_TBT_D2R_P<2>

OUT

14 68 70

PCIE_TBT_D2R_N<2>

OUT

14 68 70

PCIE_TBT_D2R_P<3>

OUT

14 68 70

PCIE_TBT_D2R_N<3>

OUT

14 68 70

10% 16V 2

10% 16V 2

10% 2

16V

10% 16V 2

10% 2

10%

16V 16V

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

X5R-CERM

0201

D

R2855

Used for straps in host mode TP_TBT_PCIE_RESET0_L TBT_DFT_STRAP_1 TBT_ROM_SECURITY_XOR TBT_DFT_STRAP_3

PCIE_RST_0_N W6 PCIE_RST_1_N AB3 PCIE_RST_2_N AD3 PCIE_RST_3_N V1

XTAL_25_IN AA24 XTAL_25_OUT AB23 TMU_CLK_OUT AA4

TBT_CLKREQ_L

OUT

Y A L P S I D

DPSRC_2_P A12 DPSRC_2_N B13

TP_DP_TBTSRC_ML_CP<2> TP_DP_TBTSRC_ML_CN<2>





DPSRC_AUX_P J4 DPSRC_AUX_N J2

TP_DP_TBTSRC_AUXCH_CP TP_DP_TBTSRC_AUXCH_CN

GPIO_2/TMU_CLK_IN/AC_PRESENT GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD GPIO_8/EN_CIO_PWR_OD* GPIO_9/SX_CTRL_OD* GPIO_14 GPIO_15

U2 L6 H5 Y7 Y1 T7 V7 M7 T1 T3

DP_TBTSRC_HPD TBT_GPIO2 TBT_PWR_EN SMC_PME_S4_DARK_L TBT_CIO_PLUG_EVENT_L HDMITBTMUX_SEL_TBT TBT_GPIO7 TBT_EN_CIO_PWR_L TBT_BATLOW_L TBTDP_AUXIO_EN TBT_DDC_XBAR_EN_L

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

G24 PA_CIO0_TX_P/DPSRC_0_P E24 PA_CIO0_TX_N/DPSRC_0_N

TBT_A_D2R_P<0> TBT_A_D2R_N<0>

G22 PA_CIO0_RX_P E22 PA_CIO0_RX_N

PB_CIO2_TX_P/DPSRC_0_P R24 PB_CIO2_TX_N/DPSRC_0_N N24 PB_CIO2_RX_P R22 PB_CIO2_RX_N N22

P1 PA_CONFIG1/CIO_0_LSEO K5 PA_CONFIG2/CIO_0_LSOE

PB_CONFIG1/CIO_2_LSEO D3 PB_CONFIG2/CIO_2_LSOE M1


L24 PA_CIO1_TX_P/DPSRC_2_P J24 PA_CIO1_TX_N/DPSRC_2_N

PB_CIO3_TX_P/DPSRC_2_P W24 PB_CIO3_TX_N/DPSRC_2_N U24


L22 PA_CIO1_RX_P J22 PA_CIO1_RX_N

TBT_A_CONFIG1_BUF TBT_A_CONFIG2_RC

TBT_A_LSTX TBT_A_LSRX

PB_CIO3_RX_P W22 PB_CIO3_RX_N U22

N8 PA_LSTX/CIO_1_LSEO J6 PA_LSRX/CIO_1_LSOE

PB_LSTX/CIO_3_LSEO M5 PB_LSRX/CIO_3_LSOE P7

TBT_B_R2D_C_P<0> TBT_B_R2D_C_N<0>

IN

12 68 70

IN

12 68 70

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1>

A16 PA_DPSRC_1_P B17 PA_DPSRC_1_N


A18 PA_DPSRC_3_P B19 PA_DPSRC_3_N

74 26

BI

74 26

BI

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N

L4 PA_AUX_P L2 PA_AUX_N

26

IN

DP_TBTPA_HPD

M3 PA_DPSRC_HPD

26 25 23

OUT

26

OUT

26 23

OUT

23 74

TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN

S T R O P

10K

5% 1/20W MF 2012

806

2

65 24 23 18 17 65 42 25 24 23

R2896

2

5% 1/20W MF 201

R8 GPIO_0/PA_HV_EN/BYP0 N2 GPIO_10/PA_CIO_SEL/BYP1 P3 GPIO_12/PA_DP_PWRDN/BYP2

PP3V3_TBTLC

100K

5% 1/20W MF 201 2

5% 1/20W MF 201 2

100K

18 36 37

OUT

15 18 72

5% 1/20W MF 201 2

100K 5% 1/20W MF

R2883

1

100K

5% 1/20W MF 2 201

2 201

PP3V3_S4_TBT NO STUFF

15 23 64 66

OUT

23 24

IN

23 25 23 26 27

OUT

23 28

OUT

27 68 74

26 25 23 28 27 23

27 68 74

27 68 74

IN

27 68 74

TBT_B_CONFIG1_BUF TBT_B_CONFIG2_RC

IN

27

IN

27

27 68 74

OUT

27 68 74

IN

27 68 74

IN

27 68 74

27 27

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

OUT

27 74

OUT

27 74

PB_DPSRC_3_P A22 PB_DPSRC_3_N B23


OUT

27 74

OUT

27 74

R28841

R28851

5% 1/20W MF 201 2

5% 1/20W MF 201 2

100K

OUT

OUT

100K

5% 1/20W MF 2 201

17 18 23 24 65

R2879

1

65 42 25 24 23

OUT IN

R2882

1

15

IN

10K

NO STUFF

R2886

1

BI

DP_TBTPB_HPD

IN

BI

5% 1/20W MF 2 201

TBT_BATLOW_L TBT_A_DP_PWRDN TBT_B_DP_PWRDN TBT_A_HV_EN TBT_B_HV_EN

25 23 26 23

R28881 10K

5% 1/20W MF 201 2

R2887

1

10K

5% 1/20W MF 2 201

NOTE: The following pins require testpoints: 0 - GPIO_13 8 - GPIO_15 1 - GPIO_1 9 - GPIO_11 2 - GPIO_2 10 - GPIO_14 3 - GPIO_3 11 - GPIO_0 4 - GPIO_5 12 - GPIO_12 5 - PCIE_RST_1_N 13 - GPIO_10 6 - PCIE_RST_2_N 14 - PB_LSTX 7 - PCIE_RST_3_N 15 - PB_LSRX

S YN C_ MA ST ER =J 44

A

S YN C_ DA TE =0 8/ 12 /2 01 3

PAGE TITLE

Thunderbolt Host (1 of 2)

27 74

Apple Inc.

27 74

R 27

OUT

23 27 28

OUT

27

OUT

23 27

B

10K

DRAWING NUMBER

DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N

TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN

R28801

5% 1/20W MF 201 2

100K

PB_DPSRC_1_P A20 PB_DPSRC_1_N B21

F1 R2 F3

R28811

R28321 R28781

IN

GPIO_1/PB_HV_EN/BYP0 GPIO_11/PB_CIO_SEL/BYP1 GPIO_13/PB_DP_PWRDN/BYP2

17 71

TBT_EN_CIO_PWR_L TBT_DDC_XBAR_EN_L HDMITBTMUX_SEL_TBT TBTDP_AUXIO_EN DP_TBTSRC_HPD

28 23

OUT

PB_AUX_P K3 PB_AUX_N K1

IN

100K

1K

27 26 23

IN

10K

5% 1/20W MF 2 201

PP3V3_TBTLC PP3V3_S4_TBT

1

66 64 23 15

23

R2863

1

C

SYSCLK_CLK25M_TBT

24 23

TBT_B_LSTX TBT_B_LSRX

PB_DPSRC_HPD N6

5% 1/20W MF 2 201

R2895 1% 1/20W MF 201

OUT

TBT_B_D2R_P<1> TBT_B_D2R_N<1>

10K

Divides 3.3V to 1.8V 1



R2862

1

10K

23

DPSRC_HPD_OD AC2

10K

R2861

R28991 T R O P

R2867

5% 1/20W MF 2 201

1

12

TBT_TMU_CLK_OUT


NO STUFF 1

If strap != bit then security is enabled?

SYSCLK_CLK25M_TBT_R TP_TBT_XTAL25OUT


PP3V3_TBTLC

5% 1/20W MF 2 201

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N 71

65 24 23 18 17

Security strap setting is XORed with bit in the flash, so the active-level depends on the code in the flash.

NO STUFF



OUT

PCIE_TBT_D2R_N<0>

10% 16V

1

1% 1/20W MF 2 201

REFCLK_100_IN_P AB21 REFCLK_100_IN_N AD21

AB5 DPSNK0_HPD


TBT_RBIAS

AD1 L8

PCIE_CLKREQ_OD_N V3

G4 DPSNK0_AUX_P G2 DPSNK0_AUX_N


PCIE_TBT_D2R_P<0>

10% 16V 2

1K

RSVD



2

TBT_RSENSE

23 74

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

C2840

27 23 74 68 26

74 68 26

DP_TBTSNK1_ML_P<3>

10% 16V 0201 X5R-CERM 2

R2831

1

26

10% 16V 0201 X5R-CERM 2

OUT

100K

23 74

DP_TBTSNK0_AUXCH_N

10% 16V 0201 X5R-CERM 2

64

DP_TBTSNK0_AUXCH_P

10% 16V 0201 X5R-CERM

2

23 74

23 74

TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L TBT_SPI_CLK

DP_TBTSNK0_HPD

OUT

74 23

10% 16V 0201 X5R-CERM

SNK1 AC Coupling C2830 10% 16V

IN

74 64

IN

X5R-CERM

74 23

DP_TBTSNK0_ML_P<0>

74 23

0.1UF

74 64

74 64

A

IN

0.1UF

2


0.1UF


AD23 MONDC0 AC24 MONDC1 DEBUG: For monitoring current/voltage W18 MONOBSP TBT_MONOBSP W16 MONOBSN TBT_MONOBSN DEBUG: For monitoring clock AB7 THERMDA TBTTHMSNS_D1_P 77 43 Use AA8 GND ball for THERM_DN

9

1

E I C P

AA18 PERP_3 AB19 PERN_3

IN

74

SNK0 AC Coupling C2820 10% 16V

PCIE_TBT_R2D_P<3> PCIE_TBT_R2D_N<3>

R4 PWR_ON_POC_RSTN

74

10K


2 N E G

TP_TBT_MONDC0 TP_TBT_MONDC1

R2825

IN

70

0.1UF

PETP_1 AD9 70 PETN_1 AD11

AB15 PERP_2 AA16 PERN_2

P5 PERST_OD_N

1

74 5


TBT_PWR_ON_POC_RST_L

74

GND THRM_PAD 4

AA12 PERP_1 AB13 PERN_1


(TBT_SPI_MISO)

7 HOLD*

70

0.1UF

74

5 DI/IO0


IN

VCC

(TBT_SPI_MOSI)

(TBT_SPI_CS_L)

C

1

1

70 68

16V

OMIT 1


X5R-CERM 0201

24

BYPASS=U2890:2mm 1

70 68

70 68

2

10%

18 15

65 24 23 18 17

70 68

70 68

10%

0.1UF

U2800

REDWOOD-RIDGE

X5R-CERM 0201

2

0.1UF

AB9 PERP_0 AA10 PERN_0

0201

10% 10%

0.1UF


FCBGA (1 OF 2)

70 68

2

0.1UF

70 68

70 68

16V

10%

10%

0.1UF

PCIE_TBT_R2D_C_N<1>

16V

2

0.1UF

IN

70 68 14

2

10%

0.1UF

SIZE

D

REVISION


BRANCH


PAGE

28 OF 120

8

7

6

5

4

3

2

1

U2950

CRITICAL OMIT_TABLE

D

PP1V05_TBTRDV

C2900 1 1.0UF

C2901 1

C2902 1

C2903 1

C2904 1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 0201-1

20% 6.3V X5R 2 0201-1

1.0UF

2

1.0UF

2

1.0UF

2

1.0UF

2

C2905 1

C2906 1

20% 6.3V X5R 2 0201-1

20% 6.3V X5R 2 0201-1

1.0UF

G10


700 mA EDP

1.0UF

K11 L10

(2 OF 2)

G18

M11

H19

N10

H9

N14

J18

VCC1P0_CIO

K15

1.05V TBT "CIO" Switch Internal switch not functional on RR. PP1V05_TBT

PP1V05_TBTCIO

1.0UF

20% 6.3V X5R 0201-1

C2931 1

C2932 1

20% 6.3V X5R 2 0201-1

20% 6.3V X5R 2 0201-1

1.0UF

2

1.0UF

PP3V3_TBTLC

A1


B1

1

CSP

A2

VOUT

2

CRITICAL

1 D

K19

R14

1

C2940

T15

M19

U10

P19

U14

T19

6

D

1

S

1.0UF

2

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

Q2945 DMN5L06VK-7

20% 6.3V X5R 0201-1

SOT-563

T11

L16

5% 1/20W MF 201

TBT_EN_CIO_PWR

D2

ON

GND

D

100K

C2

1200 mA EDP

17 18 23 24 65

R2945

B2

VIN

C1

P15 R10

VCC1P0_RDV_DECAP

C2930 1

24

U2940

TPS22920

P11

K17

K7

8 mOhm Typ 11.5 mOhm Max

J12

FCBGA

G16

Load Switch

R(on) @ 1.05V

J10

REDWOOD-RIDGE

G14

TPS22920

Type

Max Current = 4A (85C)

U2800

G12

Part

G

2

PP3V3_S0 5

V11

G

SOT-563

U18

D1

C C V

V15 V17 W12

H11

VCC3P3

PP1V05_TBT J8

OUT

S

D

TBT_EN_CIO_PWR_L

3

4

150 mA EDP

IN

23

Q2945

Pull-up (S0) on PCH page

Isolated to reduce noise from SVR

DMN5L06VK-7

W4

PP3V3_TBTLC

K9

C2910 1 1.0UF

C

20% 6.3V X5R 0201-1

C2911 1

2

L14

1.0UF

M15

20% 6.3V X5R 2 0201-1

VCC3P3_LC

M17

H13

P17

H15

V19

H17

H7

L2920

1

C2922 1

C2921 1

C2920 1

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V CERM-X5R 2 0402-1

10UF

10UF

10UF

10UF

A6

P1V05TBT_SW

2

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM DIDT=TRUE SWITCH_NODE=TRUE

SM

C2923 1

VCC3P3_RDV_DECAP

A4

680NH-30%-3.6A-35MOHM

1900 mA EDP

CRITICAL

B3

B5

C2952 1

C2953 1

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V CERM-X5R 2 0402-1

20% 6.3V CERM-X5R 2 0402-1

10UF

2

10UF

10UF

23 24 25 42 65

3.1 W (Dual-Port) 2.4 W (Single-Port) EDP: 1.25 A

C

10UF

PLACE_NEAR=C2953.1:1mm 2

XW2960 SM

1

PP3V3_TBTRDV

PP3V3_S4_TBT_F


SVR_AMON G20

A24

G6

AA14

G8

AA20

H21

AA22

H23

AA8

J14

AB11

J16

AB17

J20

AC10

1

25 mA EDP

C2980

1

1.0UF

2

20% 6.3V X5R 0201-1

C2981 1.0UF

2

C2960 1

C2961 1

20% 6.3V X5R 2 0201-1

20% 6.3V X5R 2 0201-1

1.0UF

20% 6.3V X5R 0201-1


1.0UF

K13

AC12

K21

AC14

K23

D N G

AC16 AC18

L12 L20

AC20

M13

AC22

M21

AC4

M23

B

M9

AC6 AC8

N12

B1 B7

20% 6.3V X5R 0201-1

C2951 1

R18

A2

A

1.0UF

C2950 1

L18

W10

NC

100 mA EDP

C2970 1

N18

SVR_IND0

K

D2920 SOD-323 NSR1020MW2T1G

PP3V3_S4_TBT

17 18 23 24 65


Y5

SVR_VCC1P0

CRITICAL

A

N4

POC input to RR -

TBT_PWR_REQ_L

V5


B

13

E2

W14 24

SVR input to RR - 1100 mA EDP

65 42 25 24 23

N16

VSS

VSS

N20

C10

P13

C12

P21

C14

P23

C16

P9

C18

R12

C2

R16

C20

R20

C22

T13

C24

T17

C4

T21

C6

T23

C8

T9

72 37 36 25 17

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

IN

PP3V3_S4_TBT

PP3V3_S0

Q2995

R2995 1 100K 5% 1/20W MF 201 15

TBT "POC" Power-up Reset

SMC_DELAYED_PWRGD

IN

TBT_POC_RESET_L

1

DMN32D2LFB4

1

DFN1006H4-3

G

SYM_VER_3

2

2

S 2

D

R2990

100K

5% 1/20W MF 201

5% 1/20W MF 201

C2995 1

USON

TBTPOCRST_MR_L

1

ENABLE

TBTPOCRST_SENSE

3

SENSE

R2991

2

TPS3895ADRY 2

SENSE_OUT 4 CT 5

10% 25V X5R 402

Push-pull output TBT_PWR_ON_POC_RST_L

U16

E4

V13

F11

V21

F13

V23

F15

V9

F17

Y11

F19

Y13

F21

Y15

F23

Y17

F5

Y19


F7

Y21

PAGE TITLE

F9

Y23

2 2

23

C2991 1

2

24.9K

U12

D23

330PF

OUT

TBTPOCRST_CT

GND

D21

10% 16V X7R-CERM 0201

C2990 0.1UF

VCC

U2990

3

1

1

CRITICAL 6

R2992 1

100K

0.001UF

1% 1/20W MF 201

10% 50V X7R-CERM 0402

Vth = 2.508V nominal

2

Delay = 4.04ms nominal

A

S YNC _D AT E= 08 /1 2/ 20 13

Thunderbolt Host (2 of 2)

Y9

DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

29 OF 120

8 Page Notes

7

6

5

4

3

2

1

Power aliases required by this page: - =PPVIN_SW_TBTBST (8-13V Boost Input) - =PP15V_TBT_REG (15V Boost Output) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)

D

D

SI8409DB: Vds(max): Vgs(max): Vgs(th): Rds(on): Id(max):

CRITICAL

Q3080 68 65 58 52 51 40

SI8409DB

PPBUS_G3H

BGA

8-13V Input Changes required for 2S.

3 4

R3080

1

1

65

L3095

3.3UH-6.5A

PPVIN_SW_TBTBST

1

2

2

10% 25V X5R 402

C3090 1

C3091 1

10UF

10UF

20% 25V X5R-CERM 0603

R3091 1

1

20% 25V X5R-CERM 0603

2

TBTBST_SNS1 1

2 7 2

200K 1% 1/16W MF-LF 402

TBTBST_PWREN_DIV_L

8

TBTBST_EN_UVLO

R3081 1

25

EN/UVLO

5%

Q3005

D

3

C3085 1 20% 10V X5R-CERM 402

SYM_VER_2

1

TBT_A_HV_EN

G

1

2.2UF

DFN1006H4-3

IN

28

INTVCC

TBTBST_VC

30

VC

LT3957

SNS1

6

SNS2

3

2

3

S

C3086

1

2.2UF 2

2

C3087 68PF

20% 10V X5R-CERM 402

2

5% 50V COG-CERM 0402

49.9K

SM

TBTBST_RT

33

RT

TBTBST_SS

32

SS

R3092 73.2K

2

1% 1/16W MF-LF 402

C3092 1

1

2.2UF

20% 10V X5R-CERM 402

C3093 0.0033UF

2

2

10% 50V X7R-CERM 0402

10

R3094

1 1

26.7K 1% 1/16W MF-LF 402

NC

35

1

2 2

NO STUFF 1

SGND

10% 6.3V CERM-X5R 402

4

5% 50V C0G-CERM 0402

3 4 7 2 2 3

R3095 1 137K

PP15V_TBT

1%

1/16W MF-LF 402

C3089 100PF

GND 2

2 3 4 5 6 7 1 1 1 1 1 1

5% 50V CERM 402

GND_TBTBST_SGND

1

15.8K

SGND shorted to GND inside package, no XW necessary.

2

Max Current = 2A?

C3095

FREQ = 480KHZ

20% 25V POLY-TANT CASE-D3L

NO STUFF

1%

1/16W MF-LF 402

C3096 1 2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

1

33UF-0.06OHM

R3096

26 27 65

Vout = 15.47V

2

TBTBST_FBX

31

SYNC

C3094 0.33UF

C3088 10PF

2

FBX 34

1

PLACE_NEAR=C3095.1:2 mm

2

TBTBST_VC_RC

2

Second FET needed for dual-port designs.

1

TBTBST_VSNS

1

36

1% 1/16W MF-LF 402 2

PWRDI5

XW3095

QFN

NC

R3093 1

C

D3095 PDS540XF

TBTBST_SNS2

2

TBTBST_PWREN_L

DMN32D2LFB4

26 23

TBTBST_INTVCC

MF

2

28

CRITICAL

1/20W

0201

U3090

330K

2

1

0

5%

SW

CRITICAL

2

R3089

9 0 1 8 2 2 3

VIN

1/16W MF-LF 402

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

PIMB063T-SM

G

C3080

TBTBST_BOOST

2


2

0.1UF

5%

C

D

CRITICAL

Voltage not specified here, add property on another page.

470K

1/16W MF-LF 402

S

Thunderbolt 15V Boost Regulator

-30V +/-12V -1.4V 46mOhm @ 4.5V Vgs 3.7A @ 70C

1

10UF

10% 25V X5R 1206-2

C3097

1

10UF 2

2

10% 25V X5R 805

C3099 0.001UF

2

10% 50V X7R-CERM 0402

Vout = 1.6V * (1 + Ra / Rb)

B

B 6

D

Q3088 DMN5L06VK-7

1

SOT-563

R3088 330K

1

S

G

2

Max Vgs: 10V

2

5% 1/16W MF-LF 402

TBTBST_SHDN_DIV 1

R3087

3

D

4

S

Q3088

330K

2

DMN5L06VK-7

5% 1/16W MF-LF 402

SOT-563

G

5

SMC_DELAYED_PWRGD

IN

17 24 36 37 72

BATLOW# Isolation Q3000

A

DMN32D2LFB4

36 13

IN

PM_BATLOW_L

PP3V3_S4_TBT G

D

S

3

23 24 42 65

A

1

DFN1006H4-3

SYM_VER_3


2

TBT_BATLOW_L TBT_BATLOW_L

S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Pull-up on RR page OUT

23 25

Thunderbolt Mobile Support DRAWING NUMBER

23 25

Apple Inc.

MAKE_BASE=TRUE R

REVISION


BRANCH


PAGE

30 OF 120

SIZE

D

8

7

6

5

4

3

2

1

3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt devices. 29 27 18 17 16 15 13 11 8 77 68 65 61 60 59 56

26

PP3V3_S5

C3287 1

C3280 1

1

20% 6.3V 2 POLY-TANT CASE-B2-SM

20% 6.3V X5R-CERM-1 2 603

2

22UF

100UF

D

65 27 25

C3281 0.1UF

10% 16V X5R-CERM 0201

PP15V_TBT

19 20

C3215 1

1

10% 25V X5R-CERM 0603

2

4.7UF

2

V3P3

12 14

OUT

CRITICAL QFN

16 ENHVU

C3285 1

1

10% 16V X5R-CERM 0201

2

0.1UF

U3210

CD3211A0RGPR

C3286

1

20% 6.3V CERM-X5R 0402

2

10UF

2

68

TBTAPWRSW_ISET_V3P3

IN

TBT_A_HV_EN

11 HV_EN

ISET_S0 10

68

TBTAPWRSW_ISET_S0

61 46 27

IN

PM_SLP_S3_BUF_L

17 S0

ISET_S3 9

68

TBTAPWRSW_ISET_S3

OUT

C3277

TBT_A_D2R_N<1> TBT_A_D2R_P<1>

3 3 5 1 1

10% 25V X5R 402

74 23

BI

74 23

BI

1

TBTHV:P15V

1

1

2

MF 2 201

22.6K

1%

1/20W

MF

74 68 74 68

C3230

DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_C_P

1

2

74

10% 16V X5R-CERM 0201

74

1

2

22.6K

10% 16V X5R-CERM 0201

1/20W

201

201

1

C3233

1 AUX-

28

BI IN

DP_TBTPA_DDC_DATA DP_TBTPA_DDC_CLK

OUT

TBT_A_CONFIG1_BUF

1

0.22UF

74

6. 3V 02 01

74

2 20 % X5 R

8

4 5

(IPU) AUXIO-

23

AUXIO+ (IPD)

22

TBT_A_D2R1_AUXDDC_N TBT_A_D2R1_AUXDDC_P

CA_DET

18

TBT_A_CONFIG1_RC

DPMLO+ DPMLO-

19

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

DDC_DAT DDC_CLK CA_DETOUT

11

DP+ DP-

23

IN OUT

TBT_A_LSTX TBT_A_LSRX

14

23

23

OUT

DP_TBTPA_HPD

12

13

LSTX LSRX

IN

23

IN

23 27

IN

23

26 74 26 74

TBT: RX_1

16

10

TBT_A_CIO_SEL TBTDP_AUXIO_EN TBT_A_DP_PWRDN

(IPU)

20

26

26 74 26 74

TBT: LSX_A_R2P/P2R (P/N)

(IPD)

HPDOUT

HPD

17

TBT_A_HPD

26

GND THMPAD 9 1 2

5 2

ILIM = 40000 / RISET

C

For 12V systems: PART NUMBER

QTY

118S0145 118S0145 Nominal IHVS0/S3 1120mA

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

2

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

R3210,R3213

TBTHV:P12V

2


R3211,R3214

TBTHV:P12V

Thunderbolt Connector A

CRITICAL

L3200

Min Max 1090mA 1170mA (12W minimum)

FERR-120-OHM-3A 1

2 0603

C3200 1 0.01UF

10% 50V X7R-CERM 2 0402

PP3V3RHV_S4_TBTAPWR_F MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTACONN_20_RC 1

C3201

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

GND_VOID=TRUE

2

(Both C’s) 74 68 23

OUT

74 68 23

OUT


C3274

1

2

1

2

20% 201 4V CERM-X5R-1

0.47UF

C3275

74 68 74 68

GND_VOID=TRUE

GND_VOID=TRUE

R3294 1

1

1K

74 23

IN

74 23

IN


1

20 % X5 R

0.22UF

C3279

1

0.22UF

2 74

6. 3V 02 01

74

2 20 % X5 R

0.01UF

10% 25V X5R-CERM 0201

TBT Dir

MF 2

201

NO_XNET_CONNECTION=TRUE

DP_TBTPA_ML_P<3> DP_TBTPA_ML_N<3>

6. 3V 02 01

TBT: Unused

R3279

1

1

2

2

470K

5%

1/20W

MF

201

R3278 470K

5%

1/20W

DP Dir

74 68


J3200

MDP-J44

F-RT-TH GND0 HPD ML_LANE0P CONFIG1 ML_LANE0N CONFIG2 GND1 GND2 ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND3 GND4 ML_LANE2P AUX_CHP ML_LANE2N AUX_CHN RETURN DP_PWR

C3270 74 68

201

74 26

514-0876

TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

23

26

TBT_A_CONFIG1_RC

OUT

C3206 1

1

C3202 0.01UF

TBT_A_CONFIG2_RC 2

R3252 1

1

1M

5%

1/20W

1/20W

MF

201

R3251 1M

5%

MF 2

2

201

C3294 1

1

330PF

10% 16V X7R-CERM 0201

2

C3295

1

2

10% 16V X7R-CERM 0201

R3241 100K

330PF

5%

1/20W

MF 2

201

10% 16V X5R-CERM 0201

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a). Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

20% X5R 20% X5R

1

R3270

IN

23 68 74

IN

23 68 74

R3271 5%

1/20W

MF 2


6.3V 0201

470K

5%

1/20W

2

6.3V 0201

GND_VOID=TRUE

MF

201

2

201

B

DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1>

26 74 26 74

TBT: LSX_R2P/P2R (P/N)

GND_VOID=TRUE

(Both C’s)

C3272 74 68

TBT: TX_1

1

2

1

2

20% X5R

0.22UF

TBT_A_R2D_P<1> TBT_A_R2D_N<1>

C3273

20% X5R

0.22UF GND_VOID=TRUE

6.3V 0201


IN

23 68 74

IN

23 68 74

6.3V 0201

GND_VOID=TRUE

1

R3272 470K

R3273 470K

5%

5%

1/20W

1/20W

MF 2 201 1

2

470K

0.01UF

10% 25V X5R-CERM 0201

1

TBT: RX_1

2

1


74 68

TBT_A_HPD

C3271

GND_VOID=TRUE

(0-18.9V)

B1 B3 B5 B7 B9 B11 B13 B15 B17 B19

1

0.22UF

SHIELD PINS 4 2 1 0 9 8 7 2 2 2 2 1 1 1 S S S S S S S

26

TBT_A_R2D_P<0> TBT_A_R2D_N<0>

TBT: TX_0 TBTACONN_7_C

SHIELD PINS

B2 B4 B6 B8 B10 B12 B14 B16 B18 B20

TBT Dir

PORT B

MF

74 26

GND_VOID=TRUE

(Both C’s)

DP Dir

5%

2

2

CRITICAL

1/20W

MF

201

C3205 1

MF

TBT: RX_0

R3295

GND_VOID=TRUE

(0-18.9V)

1/20W

1K

5%

1/20W

C3278


2

5%

6 5 4 3 2 1 1 1 1 1 S S S S S


B

12

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

4V 20% 201 CERM-X5R-1

0.47UF

10% 50V X7R-CERM 0402

TBTACONN_1_C

R3201 1

201

0.01UF

A

TB_ENA 15 AUXIO_EN 24 DP_PD 6

TBTB+

2 AUX+

DP_TBTPA_ML_P<1> DP_TBTPA_ML_N<1>

6. 3V 02 01

MF 2

DP_TBTPA_AUXCH_N DP_TBTPA_AUXCH_P

28

2 20 % X5 R

0.22UF

1%

1/20W

MF 2

IN

C3232


36.5K

1%

2

74 23

R3212

IN

7

20% 201 4V CERM-X5R-1

0.1UF

C3231

D

HVQFN24-COMBO

TBT_A_D2R_C_N<1> TBT_A_D2R_C_P<1>

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

R3214 22.6K

1%

1/20W 201

TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R

1

R3211

1%

1/20W

MF

68

74 23

TBTHV:P15V

22.6K 201

R3213

4V 20% 201 CERM-X5R-1 2

23

R3210 1

12V: See below

1 2

TBTHV:P15V

2

1

0.47UF

0.1UF

SIGNAL_MODEL=TBT_MUX

U3220

CBTL05024

1

0.47UF

C3276

C3211

TBTHV:P15V

THRM PAD

GND

C

OUT

74 68 23

0.1UF

ISET_V3P3 8

S4_PWR_EN

1 2

74 68 23

FAULTZ 4

5 EN

IN

3

VDD CRITICAL

2

(Both C’s)

PP3V3RHV_S4_TBTAPWR

25 23

61 60 27 18

0.1UF

10% 16V X5R-CERM 0201

GND_VOID=TRUE

26


VHV

0.1UF 10% 25V X5R 402

C3220 1


V3P3OUT 18

C3210

PP3V3_S4_TBTAPWR

Min Max 1030mA 1200mA 830mA 930mA (assumes 15V, 12W minimum) 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) PP3V3_S4_TBTAPWR

6 7

15.75V Max

Nominal 1100mA 890mA 890mA

IV3P3 IHVS0 IHVS3

CRITICAL

MF 2 201

470k R’s for ESD protection on AC-coupled signals.

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Thunderbolt Connector A DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

32 OF 120

8

7

6

5

4

3

2

1

3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt devices. 29 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

27

PP3V3_S5

C3387 1

C3380 1

1

20% 6.3V 2 POLY-TANT CASE-B2-SM

20% 6.3V X5R-CERM-1 2 603

2

22UF

100UF

D

65 26 25

C3381 0.1UF

10% 16V X5R-CERM 0201

PP15V_TBT

19 20

C3315 1

1

10% 25V X5R-CERM 0603

2

4.7UF

2

V3P3 OUT

12 14

CRITICAL QFN

16 ENHVU

1

10% 16V X5R-CERM 0201

2

C3386

1

20% 6.3V CERM-X5R 0402

2

10UF

2

OUT

74 68 23

OUT

C3377

TBT_B_D2R_N<1> TBT_B_D2R_P<1>

C3311

IN

TBT_B_HV_EN

11 HV_EN

ISET_S0 10

61 46 26

IN

PM_SLP_S3_BUF_L

17 S0

ISET_S3 9

68

10% 25V X5R 402

68

74 23

BI

74 23

BI

TBTBPWRSW_ISET_S3 TBTHV:P15V

R3310 1

12V: See below

1

68

TBTHV:P15V

1

1

2

MF 2 201

22.6K

C3330

DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_C_P

1%

1/20W

MF

201

1

2

74

10% 16V X5R-CERM 0201

74

1

2

22.6K

1%

10% 16V X5R-CERM 0201

1/20W

201

201

2

IN

1

C3333

1 AUX-

28

BI IN

DP_TBTPB_DDC_DATA DP_TBTPB_DDC_CLK

OUT

TBT_B_CONFIG1_BUF

1

74

2 20 % X5 R

0.22UF

74

6. 3V 02 01

8

4 5

23

AUXIO+ (IPD)

22

TBT_B_D2R1_AUXDDC_N TBT_B_D2R1_AUXDDC_P

CA_DET

18

TBT_B_CONFIG1_RC

DPMLO+ DPMLO-

19

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

DDC_DAT DDC_CLK

11

DP+ DP-

23

IN

TBT_B_LSTX TBT_B_LSRX

14

OUT

23

OUT

DP_TBTPB_HPD

12

13

LSTX LSRX

IN

23

IN

23 26

IN

23

27 74 27 74

TBT: RX_1

CA_DETOUT

23

TBT_B_DP_PWRDN

(IPU) AUXIO-

16

10

TBT_B_CIO_SEL TBTDP_AUXIO_EN

(IPU)

20

27

27 74 27 74

TBT: LSX_A_R2P/P2R (P/N)

(IPD)

HPDOUT

HPD

17

TBT_B_HPD

27

GND THMPAD 9 1 2

5 2

ILIM = 40000 / RISET

C

For 12V systems: PART NUMBER

QTY

118S0145 118S0145 Nominal IHVS0/S3 1120mA

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

2


R3310,R3313

TBTHV:P12V

2


R3311,R3314

TBTHV:P12V

Thunderbolt Connector B

CRITICAL

L3300

Min Max 1090mA 1170mA (12W minimum)

FERR-120-OHM-3A 1

2 0603

C3300 1 0.01UF

10% 50V X7R-CERM 2 0402

PP3V3RHV_S4_TBTBPWR_F MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

TBTBCONN_20_RC 1

C3301


GND_VOID=TRUE

2

(Both C’s) 74 68 23

OUT

74 68 23

OUT


C3374

1

2

1

2

20% 201 4V CERM-X5R-1

0.47UF

C3375

74 68 74 68

GND_VOID=TRUE

GND_VOID=TRUE

R3394 1

1

1K

74 23

IN

74 23

IN


1

20% X5R

0.22UF

C3379

1

0.22UF

2 74

6.3V 0201

74

2 20% X5R

0.01UF

10% 25V X5R-CERM 0201

TBT Dir

MF 2

201


DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3>

6.3V 0201

TBT: Unused

R3379

1

1

2

2

470K

5%

1/20W

MF

201

R3378 470K

5%

1/20W

DP Dir

74 68


J3200

MDP-J44

F-RT-TH GND0 HPD ML_LANE0P CONFIG1 ML_LANE0N CONFIG2 GND1 GND2 ML_LANE3P ML_LANE1P ML_LANE3N ML_LANE1N GND3 GND4 ML_LANE2P AUX_CHP ML_LANE2N AUX_CHN RETURN DP_PWR

C3370 74 68

201

74 27

514-0876

TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N

23

27

TBT_B_CONFIG1_RC

OUT

C3306 1

1

C3302 0.01UF

TBT_B_CONFIG2_RC 2

R3352 1

1

1M

5%

1/20W

1/20W

MF

201

R3351 1M

5%

MF 2

2

201

C3394 1

1

330PF

10% 16V X7R-CERM 0201

2

C3395

1

2

10% 16V X7R-CERM 0201

R3341 100K

330PF

5%

1/20W

MF 2

201

10% 16V X5R-CERM 0201

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a). Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

20 % X5 R 20 % X5 R

1

R3370

IN

23 68 74

IN

23 68 74

R3371 5%

1/20W

MF 2


6 .3 V 0 20 1

470K

5%

1/20W

2

6 .3 V 0 20 1

GND_VOID=TRUE

MF

201

2

201

B

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

27 74 27 74

TBT: LSX_R2P/P2R (P/N)

GND_VOID=TRUE

(Both C’s)

C3372 74 68

TBT: TX_1

1

2

1

2

20 % X5 R

0.22UF

TBT_B_R2D_P<1> TBT_B_R2D_N<1>

C3373

20 % X5 R


6 .3 V 0 20 1


IN

23 68 74

IN

23 68 74

6 .3 V 0 20 1

GND_VOID=TRUE

1

R3372 470K

R3373 470K

5%

5%

1/20W

1/20W

MF 2 201 1

2

470K

0.01UF

10% 25V X5R-CERM 0201

1

TBT: RX_1

2

1


74 68

TBT_B_HPD

C3371

GND_VOID=TRUE

(0-18.9V)

A1 A3 A5 A7 A9 A11 A13 A15 A17 A19

1

0.22UF

SHIELD PINS 3 1 0 9 8 7 6 2 1 1 S S S S S S S

27

TBT_B_R2D_P<0> TBT_B_R2D_N<0>

TBT: TX_0 TBTBCONN_7_C

SHIELD PINS

A2 A4 A6 A8 A10 A12 A14 A16 A18 A20

TBT Dir

PORT A

MF

74 27

GND_VOID=TRUE

(Both C’s)

DP Dir

5%

2

2

CRITICAL

1/20W

MF

201

C3305 1

MF

TBT: RX_0

R3395

GND_VOID=TRUE

(0-18.9V)

1/20W

1K

5%

1/20W

C3378


2

5%

5 4 3 2 1 S S S S S


B

12

TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0>

4V 20% 201 CERM-X5R-1

0.47UF

10% 50V X7R-CERM 0402

TBTBCONN_1_C

R3301 1

201

0.01UF

A

TB_ENA 15 AUXIO_EN 24 DP_PD 6

TBTB+

2 AUX+

DP_TBTPB_ML_P<1> DP_TBTPB_ML_N<1>

6. 3V 02 01

MF 2

DP_TBTPB_AUXCH_N DP_TBTPB_AUXCH_P

28

2 20 % X5 R

0.22UF

1%

1/20W

MF 2

74 23

R3312

C3332


36.5K

1%

1/20W

IN

7

20% 201 4V CERM-X5R-1

0.1UF

C3331

D

HVQFN24-COMBO

TBT_B_D2R_C_N<1> TBT_B_D2R_C_P<1>

Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.

R3314 22.6K

1%

1/20W

1

R3311

22.6K

TBTBPWRSW_ISET_S3_R TBTBPWRSW_ISET_S0_R

74 23

TBTHV:P15V

MF

74 68

23

201

R3313

74 68

TBTBPWRSW_ISET_S0

1 2

TBTHV:P15V

4V 20% 201 CERM-X5R-1 2

TBTBPWRSW_ISET_V3P3

THRM PAD

3 3 5 1 1

2

1

0.47UF

0.1UF

SIGNAL_MODEL=TBT_MUX

U3320

CBTL05024

1

0.47UF

C3376

0.1UF

ISET_V3P3 8

S4_PWR_EN

GND

C

74 68 23

FAULTZ 4

5 EN

IN

1 2

C3385 1 0.1UF

U3310

3

VDD CRITICAL

2

(Both C’s)

PP3V3RHV_S4_TBTBPWR

CD3211A0RGPR

28 23

61 60 26 18

0.1UF

10% 16V X5R-CERM 0201

GND_VOID=TRUE

27


VHV

0.1UF 10% 25V X5R 402

C3320 1


V3P3OUT 18

C3310

PP3V3_S4_TBTBPWR

Min Max 1030mA 1200mA 830mA 930mA (assumes 15V, 12W minimum) 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) PP3V3_S4_TBTBPWR

6 7

15.75V Max

Nominal 1100mA 890mA 890mA

IV3P3 IHVS0 IHVS3

CRITICAL

MF 2 201

470k R’s for ESD protection on AC-coupled signals.

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Thunderbolt Connector B DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

33 OF 120

8

7

6

5

4

3

2

1

DDC Pull-Ups 2.2k pull-ups are required by PCH to indicate active display interface. DP++ spec violation, should remove! NOTE: Only DDC_DATA is sensed, so DDC_CLK pull-ups are unstuffed.

D 77 68 65 64 62 61 37 30 24 18 17 15 13 12 11 8 50 47 46 44 43 42 41 40 39 38

PP3V3_S0

DDC Crossbar Only necessary on dual-port hosts. On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC. NEVER SEND AUXCH THROUGH CROSSBAR!

3 1

R34851 5% 1/20W MF 201 2

26

OUT

26

BI

27

OUT

27

BI

1

2

U3400

DP_TBTPA_DDC_CLK DP_TBTPA_DDC_DATA

ENA

1

INA+ INA-

14

SAI

10

ENB

3

DP_TBTPB_DDC_CLK DP_TBTPB_DDC_DATA

4

Q3485

INB+ INB-

OUTA1+ OUTA1-

20

OUTA0+ OUTA0-

18

SAO

15

OUTB1+ OUTB1-

12 SBI

5

SAI/SBI = 1: INA == OUTA0, INB == OUTB0 SAI/SBI = 0: INA == OUTB0, INB == OUTA0

SOT-563

5 G 23

IN

D N G

D 3

DMN5L06VK-7

1%

1/20W

MF 2 201

R3453 1

2.2K 1%

1/20W

MF 2 201

R3454 1

2.2K 1%

1/20W

MF 2 201

2.2K 1%

1/20W

MF 2 201

C3480 20% 10V CERM 402

QFN

CRITICAL

OUTB0+ OUTB0-

TBT_DDC_XBAR_EN

R3452 1

2.2K

TS3DS10224

16

2

R3451 1

0.1UF

C C V

100K

C

D

M D R A H P T

SBO

C

19


17

IN

64

BI

64

6 7


8 9

IN BI

13 13

11

1 2

S 4

TBT_DDC_XBAR_EN_L

B

B

Second FET needed for dual-port designs. CONNECTS TO TBTBTS_PWREN_L ON PAGE 30.

TBTBST_PWREN_L

Q3485

OUT

25

D 6

DMN5L06VK-7 SOT-563

2 G 27 23

A

IN

S 1

TBT_B_HV_EN

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

DDC Crossbar DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

34 OF 120

8

7

6

5

4

3

2

1

D

D

C

C

PCIe Wake Muxing B

B 56 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59

PP3V3_S5

R3561

1

100K

5% 1/20W MF 2 201

SEL

C3560 1

VCC CRITICAL

U3560 VER-3

AP_PCIE_WAKE_L

S 6

PCIE_WAKE_L (B0) AP_S0IX_WAKE_L (B1)

AP_S0IX_WAKE_SEL

NC7SB3157P6XG SC70

72 63

L H

5

0.1UF

10% 6.3V CERM-X5R 2 0201

OUTPUT

4 A

B0 3 B1 1

PCIE_WAKE_L AP_S0IX_WAKE_L

GND

IN

15

OUT

13 31 72

OUT

15

2

NOSTUFF

BLUETOOTH

R3560 1

0

2

68 65 64 63 60 42 38 37 34 18

PP3V3_S4

5% 1/20W MF 0201

1

5

DFN

C3510

2

DP_2

6

DM_2

7

DP_1

2

DM_1

1

10% 6.3V CERM-X5R 0201

71 63

USB_BT_CONN_P

10

DP

71 63

USB_BT_CONN_N

9

DM

OE* SIGNAL_MODEL=BT_MUX

S GND 8

Q3510

D

3

34 36 38

S

2

DMN32D2LFB4

BI

14 71

USB_BT_N

BI

14 71

DFN1006H4-3

SYM_VER_2

NC

1

G

A

SYNC_MASTER=J44


PAGE TITLE

WIRELESS SUPPORT

BT_WAKE

DRAWING NUMBER

3 4

OUT


USB_BT_P

CRITICAL

A

SMC_PME_S4_WAKE_L

0.1UF

VDD

U3510

USB3740

1

PM_SLP_S4_L SEL

IN

1%

BT_WAKE (1) USB_BT (2)

Apple Inc. R

1/20W

MF 2

L H

R3512 15K

13 18 36 61 63

OUTPUT

201

SIZE

D

REVISION


BRANCH


PAGE

35 OF 120

8

7

6

5

4

3

2

1

OOB Isolation

D 65 41 30

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

BYPASS=U3710:5 mm

PP3V3_S0

1

CRITICAL

74LVC1G08 SOT891

FERR-26-OHM-6A 1

PP3V3_S0SW_SSD_FLT

2

C3701

1

10% 10V X5R-CERM 0201

2

0.1UF

2

4

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.15mm VOLTAGE=3.3V

0603

1

C3702

R37011 R3700

514S0449 CRITICAL

J3700 F-RT-SM

100K

100K

1/20W

1/20W

1% MF

C3710

PCIE_SSD_R2D_C_N<3>

1

70 68 12

IN

PCIE_SSD_R2D_C_P<3>

C3711

70 68 12

IN

PCIE_SSD_R2D_C_N<2>

C3712

GND_VOID=TRUE 10% 16V X 5R C ER M

1

2

1

2

GND_VOID=TRUE 10% 16V X5R-CERM GND_VOID=TRUE 10% 16V X 5R C ER M

0.1UF

IN

PCIE_SSD_R2D_C_P<2>

C3713

70 68 12

IN

PCIE_SSD_R2D_C_N<1>

C3714

70 68 12

IN

PCIE_SSD_R2D_C_P<1>

C3715

IN

PCIE_SSD_R2D_C_N<0>

C3716

1

2

1

2

1

2

1

2

1

2

GND_VOID=TRUE 10% 16V X5R-CERM

0.1UF


0.1UF


0.1UF 70 68 12


0.1UF 70 68 12

IN

C3717

PCIE_SSD_R2D_C_P<0>

0 20 1 70 68

0.1UF

70 68 12

PP3V3_S0 SSD_RESET_CONN_L NC_SSD_MFG_RSVD

2

53

2

52

3

51


0.1UF

70 68

70 68 70 68

5

50

6

49

7

48

8

47

201

50 47 46 44 43 42 41 18 17 15 13 12 11 8 40 39 38 37 30 28 24 77 68 65 64 62 61

2

45 TRUE

TRUE

12

44 TRUE

13

43

PCIE_SSD_R2D_N<2> PCIE_SSD_R2D_P<2>

TRUE

14

42 TRUE

TRUE

15

41 TRUE

16

40

17

39

0201

70 68 70 68

TRUE

18

38 TRUE

TRUE

19

37 TRUE

20

36

TRUE

21

35 TRUE

TRUE

22

34 TRUE

23

33


0 20 1 70 68

0201

0 20 1

70 68

PCIE_SSD_R2D_N<0> PCIE_SSD_R2D_P<0> SSD_CLKREQ_CONN_L

Supervisor & CLKREQ# Isolation Delay = 55ms

R3740

1

1

100K

1/20W

MF 2

2

201

P3V3SSD_VMON

1

17 33 34 36 37 38 39 61 65 68

2

SLG4AP016V

16

IN

15

IN

36

IN

15 30 60 61

2

CRITICAL 6

2

74LVC1G08 SOT891

U3711 08

4

C

NC

5


OUT

12 68 70

OUT

12 68 70


OUT

12 68 70

OUT

12 68 70


OUT

12 68 70

OUT

12 68 70


OUT

12 68 70

OUT

12 68 70

IN

12 68 70

IN

12 68 70

3

NC SMC_PWRFAIL_WARN_L: There is 10k pullup on the SSD, its OPEN drain on SMC.

32 31

27

30

28

29

54

59

55

60

56

61

57

62

58

63

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

B

45 51 52

C3740 0.1UF

VDD

U3740

1%

MF

CRITICAL

1

R3741 232K

5%

1/20W 201

PP3V42_G3H

36

0.1UF

10% 10V X5R-CERM 0201

OUT

24

26

30 41 65

SSD_PCIE_SEL_L SSD_DEVSLP SMC_PWRFAIL_WARN_L SSD_PWR_EN

0201

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

PP3V3_S0SW_SSD

OUT

C3719 1

1

46

11

25

B

SMC_OOB1_D2R_L

PP3V3_S0 BYPASS=U3711:5 mm

SMC_OOB1_R2D_CONN_L SMC_OOB1_D2R_CONN_L

9 10 TRUE

0201

0 20 1

36

NC

GND_VOID

1


2

0.1UF

IN

5

1

4

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

SMC_OOB1_R2D_L

1

1% MF

201

SSD-GS3

IN

2

3

10% 10V X5R-CERM 0201 PLACE_NEAR=L3700.1:1mm

GND_VOID

70 68 12

6

U3710 08 NC

0.1UF

PLACE_NEAR=L3700.1:1mm

C

10% 10V X5R-CERM 0201

CRITICAL

L3700

PP3V3_S0SW_SSD

C3718 0.1UF

2 PLACE_NEAR=J3700.1:3mm

65 41 30

D

PP3V3_S0SW_SSD

10% 6.3V CERM-X5R 0201

Gumstick3 Connector

TDFN

2 SENSE + 0.7V DLY 4 RESET*

7 IN 1

R3742

MR* 3

SSD_RESET_L

EN 6 OUT 8

SSD_PWR_EN SSD_CLKREQ_L

(OD)

THRM PAD 9

IN

15

IN

15 30 60 61

OUT

12

GND 5

100K 1%

1/20W

MF

A

2

201

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

SSD Connector DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

37 OF 120

8

7

6

5

4

3

2 PP1V8_CAM

L3902

75 32 31

BYPASS=U3900.K13:2.54MM

PP1V35_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.35V

1

L3906

1.0UF

22NH

PP1V35_DDR_CLK

1


U3900

D

N7 N8 N6 C10 C7

2

10% 2 6.3V CERM-X5R 0201

31

GND_CAM_PVSSC

GND_CAM_PVSSD

N13 P14 P15 R15 K15 L12 L13 L14 L15 A1 A6 B6 D1 D5 E5 G1 G6 G7 G8 G9 H5 H6 H7 H8 H9 J5 J6 J7 J8 J9 K1 K5 K6 K7 K8 K9 A14 M9 N1 P5 R1 R5 E9

C

B

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.675V 1

32 75

1

C3927

C3930

1

20% 6.3V 0201-1

20% 2 6.3V CERM-X5R 0402-1

1.0UF

2 X5R

10% 6.3V 2 CERM-X5R 0201

1


10UF

31

1

20% 6.3V 0201-1

20% 6.3V 2 CERM-X5R 0402-1

2 X5R

330K

1

10%

10% 2 16V X7R-CERM 0201

0201

2

C3971

1

1000PF

2 6.3V CERM-X5R

0603

SR_VDD_3P3C

SR_VDD_3P3D

VSSC SR_VLXC_O

SR_VLXD_O

H14 H15 J13 J14 J15

1

C3919

1

10% 6.3V 0201

10% 16V 2 X7R-CERM 0201

0.1UF

BYPASS=U3900.D7:2.54MM

2 CERM-X5R

C3938

C3972

1

0.1UF

C3973

1

1000PF

10% 2 6.3V CERM-X5R 0201

C3974 0.1UF

10% 2 16V X7R-CERM 0201

10% 2 6.3V CERM-X5R 0201

1

L3901

1.0UH-1.6A-55MOHM

C3975

1

10% 2 6.3V CERM-X5R 0201

31

C3914

4.7UF

20% 2 6.3V X5R 402

C3918

1

1000PF

C3916 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C3917 1000PF

10% 16V 2 X7R-CERM 0201

1

C3910 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C3951

GND_CAM_PVSSC

K13 K14

P1V35_CAM_SRVLXD_PHASE

B15 VDDO18

1

1

20% 2 6.3V X5R 402

XTAL_AVDD1P2 B13

C3926 GND_CAM_PVSSD

1

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.175MM VOLTAGE=0V

1

1

C3939

1K

5% 1/20W MF 201 1

20% 2 6.3V CERM 402-LF

20% 6.3V 2 X5R 402

C3940

1

10% 6.3V 0201

10% 16V 2 X7R-CERM 0201

0.1UF

2 CERM-X5R

C3934 1000PF

1

C3935 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

C3936 1000PF

10% 16V 2 X7R-CERM 0201

1

C3937 0.1UF

10% 6.3V 2 CERM-X5R 0201

OUT

PP1V2_CAM PP1V35_CAM

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32 17 31

OUT

31 31 32 75

PP1V2_CAM_XTALPCIEVDD MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V MAKE_BASE=TRUE

17 31

C3960

75 32

OUT

75 32

OUT

75 32

OUT

0.1UF

75 32

OUT

6.3V 2 CERM-X5R

75 32

OUT

75 32

OUT

75 32

OUT

R3976

1

51K

R3912 1

240

1% 1/20W MF 201

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

75 32

OUT

2 75 32

OUT

75 32

OUT

P8 MIPI_DP0 R8 MIPI_DM0

31

PLACE_NEAR=U3900.M13:2.54MM

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

IN

70 32

IN

70 32

IN

70 32

IN

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

72 29 13

OUT

32 31

70 32

OUT

70 32

OUT

PCIE_CAMERA_D2R_C_P PCIE_CAMERA_D2R_C_N

5% 1/20W MF 201

68 32

BI

71 32

OUT

71 32

IN

CLK25M_CAM_CLKP CLK25M_CAM_CLKN

2

31

NOSTUFF

PCIE_WAKE_L

2

31

R3990 100K

5% 1/20W MF 201 2

CRITICAL OMIT_TABLE

DDR_DQ00 C2 DDR_DQ01 E3 DDR_DQ02 E4 DDR_DQ03 D3 DDR_DQ04 F3 DDR_DQ05 F1 DDR_DQ06 F4 DDR_DQ07 F2 DDR_DQ08 B5 DDR_DQ09 C3 DDR_DQ10 B1 DDR_DQ11 B4 DDR_DQ12 A5 DDR_DQ13 C5 DDR_DQ14 B2 DDR_DQ15 B3

MEM_CAM_DQ<0> MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6> MEM_CAM_DQ<7> MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15>

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

BI

32 75

DDR_DQS_P0 E2 MEM_CAM_DQS_P<0> DDR_DQS_N0 D2 MEM_CAM_DQS_N<0>

BI

32 75

BI

32 75

MEM_CAM_CLK_P H2 DDR_CK_P0 MEM_CAM_CLK_N G2 DDR_CK_N0

DDR_DQS_P1 A2 MEM_CAM_DQS_P<1> DDR_DQS_N1 A3 MEM_CAM_DQS_N<1>

BI

32 75

BI

32 75

MEM_CAM_ZQ_S2 G3 DDR_ZQ J3 DDR_CKE MEM_CAM_CKE L4 DDR_CS* MEM_CAM_CS_L

0

5% 1/20W MF 0201

PP1V8_CAM

MEM_CAM_BA<0> K3 DDR_BA0 MEM_CAM_BA<1> L2 DDR_BA1 MEM_CAM_BA<2> K2 DDR_BA2

MEM_CAM_DM<0> C1 DDR_DM0 MEM_CAM_DM<1> C4 DDR_DM1

1

DDR_RAS* DDR_WE* DDR_CAS* DDR_RESET*

H3 J2 H4 R3

MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_CAS_L MEM_CAM_RESET_L

12

OUT

18

IN 72

D15 R10 C15 R9

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

TP_CAM_JTAG_TCK TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO TP_CAM_JTAG_TMS TP_CAM_JTAG_TRST_L CAM_JTAG_SRST_L

F13 E12 F12 D12 D11 C11

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST* JTAG_SRST*

CAMERA_CLKREQ_L CAM_PCIE_RESET_L CAM_PCIE_WAKE_L

P13 PCIE_CLKREQ* R14 PCIE_RST* N12 PCIE_WAKE*

CAM_PWR_SEL CAM_DEBUG_RESET_L

G12 E15 R13 H12

R3901

1

C3990

100K

0.1UF

5% 1/20W MF

10% 6.3V 0201

2 CERM-X5R

32 75 32 75

OUT

32 75

OUT

32

31

NOSTUFF

R39371 100K 5% 1/20W MF 201

NC

IN

B 31 31

STRAP_XTAL_FREQ C13 CAM_XTAL_FREQ

31

31

DDR_PWR_SEL RESET* SENSOR_WAKE* SHUTDOWN*

32 31

PP1V8_CAM 31

31

100K

IN

31

TEST_OUT J12 CAM_TEST_OUT TEST_MODE M10 CAM_TEST_MODE

R3915

18

2

31

UARTRXD E13 CAM_UARTRXD UARTTXD E14 TP_CAM_UARTTXD

CAM_A1

32

5% 1/20W MF 201 2

31

UARTCTS D13 CAM_UARTCTS UARTRTS D14 TP_CAM_UARTRTS

1

NO STUFF

R3910

31

A1 SILICON BUG

31 32

R3911

1

CAM_JTAG_SRST_L PP1V8_CAM

CAM_TEST_MODE

CAM_TEST_OUT

5% 1/20W MF 2 201

CAM_SENSOR_WAKE_L CAMERA_PWR_EN

PU on PCH page

1

100K

100K

5% 1/20W MF 2 201

5% 1/20W MF

2 201

CAM_XTAL:YES

R3904 100K

31

OUT

31

PD = 1.35V

2 201

1

OUT

100K

A13 XTAL_P A12 XTAL_N

I2C_CAM_SMBDBG_CLK I2C_CAM_SCK I2C_CAM_SMBDBG_DAT I2C_CAM_SDA

C

R3936

R12 CAM_RAMCFG0 P12 CAM_RAMCFG1 P11 CAM_RAMCFG2 P10 CAM_GPIO3 P9 NC N11 NC N10 NC N9

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

STRAP_XTAL_SEL C12 CAM_XTAL_SEL

NOSTUFF 1

A8 PCIE_TDP0 B8 PCIE_TDN0 B9 PCIE_TESTP NC C9 PCIE_TESTN NC

1

FBGA SYM 2 OF 3

DEBUG_00 B11 TP_CAM_TEST_MODE0 DEBUG_01 C14 TP_CAM_TEST_MODE1 DEBUG_02 B14 TP_CAM_TEST_MODE2 DEBUG_03 A15 TP_CAM_LV_JTAG_TCK DEBUG_04 E11 TP_CAM_LV_JTAG_TDI DEBUG_05 E10 TP_CAM_LV_JTAG_TDO DEBUG_06 F11 TP_CAM_LV_JTAG_TMS DEBUG_07 F10 TP_CAM_LV_JTAG_TRSTN DEBUG_08 G11NC DEBUG_09 G10NC DEBUG_10 H11NC DEBUG_11 H10NC DEBUG_12 J10NC DEBUG_13 K11NC DEBUG_14 K10NC PP1V8_CAM DEBUG_15 L11NC 32 31 DEBUG_16 L10NC NOSTUFF 1

CRITICAL OMIT_TABLE

PCIE_CLK100M_CAMERA_C_P B10 PCIE_REFCLKP PCIE_CLK100M_CAMERA_C_N A10 PCIE_REFCLKN

R3991

L3 M4 N3 M3 M1 M2 P4 N2 P3 P2 J4 R2 L1 P1 R4

FBGA SYM 1 OF 3

B7 PCIE_RDP0 A7 PCIE_RDN0

PCIE_CAMERA_R2D_P PCIE_CAMERA_R2D_N

70 32

1K

2

BYPASS=U3900:7mm BYPASS=U3900:3mm BYPASS=U3900:3mm BYPASS=U3900:5mm BYPASS=U3900:5mm BYPASS=U3900:5mm

U3900

OUT

MIPI_DATA_P MIPI_DATA_N

31 68 32

BCM15700 75 32

75 32

5% 1/20W MF 2 201

C3942

BYPASS=U3900.F15:2.54MM 1UF 10% 10V 2 X5R 402 BYPASS=U3900.G15:2.54MM

31

0201

5% 1/20W MF 2 201

C3941 2.2UF

1

P7 MIPI_CP_CLK R7 MIPI_CM_CLK

R39131 R39141

PP3V3_S3RS0_CAMERA 15 42

4.7UF

PP1V8_CAM

10%

51K

IN

MIPI_CLK_P MIPI_CLK_N

XW3901 SM

PP1V2_CAM_XTALPCIEVDD

1

R3975

75 68 32

PP1V8_CAM

32 31

20% 2 6.3V X5R 402

31


1

IN

2

31 32 75


20% 2 6.3V X5R 402

P1V2_CAM_SRVLXC_PHASE

PLACE_NEAR=U3900.M13:4MM

4.7UF

P6 MIPI_DP1 NC R6 MIPI_DM1 NC

4.7UF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

PP1V2_CAM

2 1008

C3915

GND_CAM_PVSSC

BYPASS=U3900.J1:2.54MM BYPASS=U3900.L7:2.54MM BYPASS=U3900.J1:2.54MM BYPASS=U3900.D6:2.54MM BYPASS=U3900.L7:2.54MM BYPASS=U3900.D6:2.54MM

R11

L3901:1 VSENSE_C M11 L3902:1 VSENSE_D K12

IN

75 68 32

PLACE_NEAR=U3900.M14:2.54MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM DIDT=TRUE

VDD1P2_O F15

VDDC

75 68 32

0.1UF

10% 6.3V 2 CERM-X5R 0201

VDD_3P3A J11

F6 F7 F8 F9 L6 L5 L8 L9

IN

(=PP3V3_S3RS0_CAMERA) P1V2_CAM_SRVLXC_PHASE 31

VDD1P8_O G15

75 68 32

XW3900 SM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.175MM VOLTAGE=0V

PP1V35_CAM

1

4.7UF

0.1UF

BYPASS=U3900.F6:2.54MM BYPASS=U3900.F9:2.54MM BYPASS=U3900.F6:2.54MM BYPASS=U3900.L9:2.54MM BYPASS=U3900.F9:2.54MM BYPASS=U3900.L9:2.54MM

1000PF

10% 16V 2 X7R-CERM 0201

C3928

M13 N14

VDD_1P35A F14

D

5% 1/20W MF 2 201

U3900

1

(=PP3V3_S3RS0_CAMERA)

1

31

330K

5% 1/20W MF 2 201

BCM15700


M14 M15 N15

31

R3935

1

C3970 0.1UF

10UF

31

1

330K

5% 1/20W MF 2 201

I2C_CAM_SMBDBG_CLK 31 I2C_CAM_SMBDBG_DAT 31

17 31

R3933

1

PP1V2_CAM 1

C3933

R3931

1

5% 1/20W MF 2 201

PP1V8_CAM

OTP_VDD3P3 D7

CAM_UARTRXD

5% 1/20W MF 2 201


PLL_VDD1P8 D6

5% 1/20W MF 2 201

CAM_RAMCFG2 CAM_RAMCFG1 CAM_RAMCFG0

100K

0603

C3931

C3932 1.0UF

PP1V2_CAM_PCIE_PVDD_FLT

DDR_AVDD1P8 J1

100K

5% 1/20W MF 2 201

MIPI_AVDD1P8 L7

SR_PVSSD

R3934

100K

5% 1/20W MF 201

PP1V8_CAM

100K

L3904

PP1V2_CAM_PCIE_VDD_FLT

PCIE_PVDD1P2 D9

2

1NOSTUFF

R3932

100K

R3920 1R3921


2

1

CAM_UARTCTS

32 31

1NOSTUFF

R3930

31

PLACE_NEAR=U3900.K13:4MM

20% 2 6.3V X5R 402

220-OHM-1.4A

PCIE_VDD1P2 C8 SR_PVSSC

31

C3913 4.7UF

20% 2 6.3V X5R 402

P1V35_CAM_SRVLXD_PHASE

2 1008

L3903

1

PP0V675_CAM_VREF

PMU_AVSS

31

10% 2 6.3V CERM-X5R 0201

1

220-OHM-1.4A

DDR_VDDIO_CK G5

B12 XTAL_AVSS

A

4.7UF

1NOSTUFF

1.0UH-1.6A-55MOHM

1

DDR_VREF_O N5 31

C3912

1

GND_CAM_PVSSD

31

CRITICAL

OMIT_TABLE PCIE_GND

C3924

1

0.1UF

20% 2 6.3V X5R 0201-1

10% 2 6.3V CERM-X5R 0201

A4 D4 G4 DDR_VDDIO K4 N4

1

1.0UF

0.1UF

FBGA SYM 3 OF 3

MIPI_AGND

C3923

C3900

0.1UF

G14 M12

C3922

1

0.1UF

20% 2 6.3V X5R 0201-1

0402

1

BCM15700

C3921

1

1

31 32

CAM_XTAL_FREQ PU = 25MHz

5% 1/20W MF 201 2

R3906

1

100K

2

5% 1/20W MF 201

CAM_XTAL_SEL CAM_XTAL:NO

SYNC_MASTER=J44 PAGE TITLE 31

DRAWING NUMBER

R3907

1

100K

5% 1/20W MF 201 2

Apple Inc. R

A


Camera 1 of 2

SIZE

D

REVISION


BRANCH


PAGE

39 OF 120

8

75 31

7

6

5

1

BYPASS=U4000.B2:4mm

C4002

1

10UF

PP0V675_CAM_VREF

1 0201

0

2

75

2

75

R40231

10% 6.3V CERM-X5R 2 0201

10% 2 6.3V CERM-X5R 0201

0.1UF

1K

BYPASS=U4000.D2:4mm 1

5% 1/20W MF 201

C4006 2.2UF

20% 10V 2 X5R-CERM 402

1

C4007 0.1UF

10% 6.3V 2 CERM-X5R 0201

BYPASS=U4000.K2:4mm 1

C4008 2.2UF

20% 10V 2 X5R-CERM 402

1

C4009 0.1UF

10% 6.3V 2 CERM-X5R 0201

1 8 1 9 2 9 1 2 9 A A C C D E F H H

2 9 7 2 8 1 9 1 9 B D G K K N N R R

VDDQ

2

75 31

IN

75 31

IN

75 31

IN

75 31

IN IN

75 31

1K

5% 1/20W MF 2012

75 31

IN

75 31

IN IN

75 31 75 31

IN

75 31

IN IN

75 31

C

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

75 31

IN

IN

R4020

1

84.5

1% 1/20W MF 2 201

NO STUFF

75 31

R4021

1

IN

82

75

1% 1/20W MF 2 201

MEM_CAM_CKE_R 31

NO STUFF

IN

70 14

IN

PCIE_CAMERA_R2D_C_P

C4033 1

70 14

IN

PCIE_CAMERA_R2D_C_N

C4032 1

IN

PCIE_CAMERA_D2R_C_P

IN

PCIE_CAMERA_D2R_C_N

70 68 12

IN

PCIE_CLK100M_CAMERA_P

C4061 1

70 68 12

IN

PCIE_CLK100M_CAMERA_N

C4062 1

70 31

BYPASS=U4000.R9:4mm

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5> MEM_CAM_A<6> MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>

N3 A0 P7 A1 P3 A2 N2 A3 P8 A4 P2 A5 R8 A6 R2 A7 T8 A8 R3 A9 L7 A10/AP R7 A11 N7 A12/BC* T3 A13 T7 A14

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

M2 BA0 N8 BA1 M3 BA2

MEM_CAM_RAS_L MEM_CAM_CAS_L MEM_CAM_WE_L

J3 RAS* K3 CAS* L3 WE*

MEM_CAM_CLK_P MEM_CAM_CLK_N

J7 CK K7 CK*

MEM_CAM_CKE MEM_CAM_CS_L

K9 CKE L2 CS*

MEM_CAM_ODT

K1 ODT

MEM_CAM_ZQ_DDR

L8 ZQ

MEM_CAM_RESET_L

T2 RESET*

R4006

VDD

U4000

1 H

A C F E R V

Q D F E R V

4GB-DDR3-256MX16 FBGA

NC

K4B4G1646B-HYK0

CRITICAL OMIT_TABLE

VSSQ

100PF

5% 2 25V NP0-CERM 0201

8 M

71 17

0.1UF

C4031 1 0.1UF

C4030 1

0.1UF

71

0201

1

NP0-C0G-CERM

NC NC

C4014

2 4

CLK25M_CAM_XTALP CRITICAL

Y4000

1

BI

31 75

BI BI

31 75

BI

31 75

BI

31 75

BI

31 75

DQSL F3 MEM_CAM_DQS_P<0> DQSL* G3 MEM_CAM_DQS_N<0>

BI

31 75

BI

31 75

DQSU C7 MEM_CAM_DQS_P<1> DQSU* B7 MEM_CAM_DQS_N<1>

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

BI

31 75

CAM_WAKE:NO

BI

31 75

R40311

DQU0 D7 DQU1 C3 DQU2 C8 DQU3 C2 DQU4 A7 DQU5 A2 DQU6 B8 DQU7 A3

MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15>

DML E7 DMU D3

MEM_CAM_DM<0> MEM_CAM_DM<1>

31 75

2

PCIE_CLK100M_CAMERA_C_N

OUT

31 70

IN

31 71

R4008 0

1

2

0201 5% 1/20W

CLK25M_CAM_XTALP_R NOSTUFF

5% 1/20W MF 0201

1M

1% 1/20W MF 2 201

0

1

R4012

71

CAM_XTAL:YES

31 70

10% 16V X5R-CERM 0201

1

2 5% 25V

D

OUT

10% 16V X5R-CERM 0201

CAM_XTAL:NO

71

5% 1/20W MF

CAM_XTAL:YES

12PF

31 75

MEM_CAM_DQ<0> MEM_CAM_DQ<1> MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6> MEM_CAM_DQ<7>

0

1 0201

25.000MHZ-12PF-20PPM

31 75

E3 F7 F2 F8 H3 H8 G2 H7

14 68 70

PCIE_CLK100M_CAMERA_C_P

CLK25M_CAM_CLKP

MF

R4009

SM-3.2X2.5MM 3

BI BI

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

14 68 70

2 PCIE_CAMERA_D2R_N OUT 10% 16V X5R-CERM 0201

R4007

2

25V 5%

31 70

2 PCIE_CAMERA_D2R_P OUT 10% 16V X5R-CERM 0201

2

0.1UF

12PF

CAM_XTAL:YES 1

NC NC NC NC NC

31 70

2 PCIE_CAMERA_R2D_N OUT 10% 16V X5R-CERM 0201

CAM_XTAL:YES

C4015 J1 J9 L1 L9 M7

2 PCIE_CAMERA_R2D_P OUT 10% 16V X5R-CERM 0201

2

0.1UF

SYSCLK_CLK25M_CAMERA

IN

1

0.1UF

0.1UF

1K

NOSTUFF

1

10% 6.3V 2 CERM-X5R 0201

C4011

R40021

R40031

IN

0.1UF


1

IN

20% 4V 2 CERM-X5R-1 201

C4005

PP0V675_MEM_CAM_VREFCA

C4010 1

75 31

20% 6.3V 2 CERM-X5R 0402-1

1

70 31

2

75 31

0.47UF


1K

75 31

C4004

PP0V675_MEM_CAM_VREFDQ

5% MF 1/20W

1% 1/20W MF 2012

1

BYPASS=U4000.H9:4mm

R40221 1% 1/20W MF 201

C4003 10UF

20% 6.3V 2 CERM-X5R 0402-1

R4000 75 31

3

PP1V35_CAM BYPASS=U4000.A1:4mm

D

4

2

CAM_XTAL:YES

R4010

CLK25M_CAM_XTALN

1

0

NP0-C0G-CERM

0201

CLK25M_CAM_CLKN OUT 31 71 CAM_XTAL:YES CAM_XTAL:NO

2

5% 1/20W MF 0201

NOTE: TBD PPM crystal required

1

C4016 100PF

5% 2 25V NP0-CERM 0201

PP1V8_CAM

C

31

R4005

1

100K 5% 1/20W MF

CAM_WAKE:YES

2 201

R4030 68 32

CAM_SENSOR_WAKE_L_CONN

1 0201

0

2

31

CAM_SENSOR_WAKE_L

5% 1/20W MF

0

IN

31 75

IN

31 75

5% 1/20W MF 0201

2

VSS

1 9 1 8 2 8 9 1 9 B B D D E E F G G

9 3 1 8 2 8 1 9 1 9 1 9 A B E G J J M M P P T T

R4004

1

B

B

240

1% 1/20W MF 2 201

CAMERA SENSOR

L4009

90-OHM-50MA TCM0605-1 SYM_VER-1

CRITICAL

J4002

CCR20-AK7100-1 F-RT-SM

14

1

4

MIPI_CLK_N

IN

31 68 75

2

3

MIPI_CLK_P

IN

31 68 75

PLACE_NEAR=J4002.2:2.54MM

CRITICAL

1 2

75 68

3

75 68

4 5

75 68

6

75 68

MIPI_CLK_CONN_N MIPI_CLK_CONN_P CAM_SENSOR_WAKE_L_CONN MIPI_DATA_CONN_N MIPI_DATA_CONN_P

L4007


32 68

7

A

ALS

8 9 10 11 12 13

68

SMBUS_SMC_1_S0_SDA 14 36 39 43 68 72 76 BI SMBUS_SMC_1_S0_SCL 14 36 39 43 68 72 76 IN I2C_CAM_SCK IN 31 68 I2C_CAM_SDA BI 31 68 PP5V_S3RS0_ALSCAM_F

4

MIPI_DATA_N

BI

31 68 75

2

3

MIPI_DATA_P

BI

31 68 75


2

PP5V_S0

1

0402-LF

PAGE TITLE 16 17 41 44 45 53 54 65 68

58 60 61

DRAWING NUMBER

Apple Inc.

L4011

R

FERR-120-OHM-1.5A 2

1

0402-LF

PP5V_S4

33 46 55 56 57 60 62 63 68

77.2 mA nominal max 96.2 mA peak

65 66

A


Camera 2 of 2

NOSTUFF

C4013 1 20% 10V CERM 2 402

SYNC_MASTER=J44

CRITICAL L4010 FERR-120-OHM-1.5A


0.1uF

518S0892

1

SIZE

D

REVISION


BRANCH


PAGE

40 OF 120

8

7

6

5

4

3

2

1

RIGHT USB PORT A

D

D

USB Port Power Switch CRITICAL

CRITICAL

L4605

U4600

FERR-120-OHM-3A

TPS2557DRB

PP5V_S3_LTUSB_A_ILIM

SON 66 65 63 62 60 57 56 55 46 32 68

16 14

OUT 61

PP5V_S4

2 3

XDP_USB_EXTA_OC_L USB_PWR_EN

1

10UF 20% 6.3V CERM-X5R 0402-2

1

C4691 0.1UF

2

2

8

FAULT*

4

EN

7 5

ILIM

C4696

1

2

68

PP5V_S3_LTUSB_A_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WI DTH=0.375 mm VOLTAGE=5V

0.01UF

USB_ILIM

10% 16V X5R-CERM 0201

CRITICAL

J4600

2

USB3.0-J44-ALT F-RT-TH

22.1K

1% 1/20W MF 201 2

9

USB_ILIM_L

20% 6.3V POLY-TANT CASE-B2-SM1

2 0603

C4605 1

R4600 1

220UF-35MOHM

10% 16V X5R-CERM 0201

MIN_LINE_WID TH=0.5 mm MIN_NECK_WID TH=0.15 mm VOLTAGE=5V

6

OUT1 OUT2

THRM GND PAD

CRITICAL

C4690 1

IN_0 IN_1

1

1

CRITICAL

R4601

90-OHM

10UF 20% 6.3V CERM-X5R 0402-2

DLP0NS

SYM_VER-1

2

22.1K

2

1 2 3 4 5 6 7 8 9 10

L4600

C4695 1

71

1% 1/20W MF 201

71

USB2_EXTA_MUXED_N USB2_EXTA_MUXED_P

4

3

1

2

71 71

CRITICAL

D4601

2

2

ESD0P2RF-02LS

Current limit per port (R4600+R4601): 2.19A min / 2.76A max

CRITICAL

D4600

ESD0P2RF-02LS

TSSLP-2-1

THE PI3USB102E CAN CLAMP VOLTAGE IN THE INTERNAL USB PINS PP3V42_G3H BYPASS=U4650.9:3:5mm

C4650 1

1

0.1UF

10% 10V X5R-CERM 0201

71 37 36

IN

71 37 36

OUT

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L

R4650 100K

9

2

VCC 5 M+ 4 M-

2

5% 1/20W MF 201

71 68 14

OUT

USB3_EXTA_D2R_N

71 68 14

OUT

USB3_EXTA_D2R_P

Y+ 1

U4650

BI

71 14

BI

USB_EXTA_P USB_EXTA_N

7 D+ 6 D-

GND_VOID=TRUE

D4621

2

2

ESD0P2RF-02LS

SEL 10 GND

SSRX-

GND

C

SMC_DEBUGPRT_EN_L SEL

IN

CRITICAL

D4620

ESD0P2RF-02LS

TSSLP-2-1

SIGNAL_MODEL=MOJO_MUX_SMSC

SXRX+

GND_VOID=TRUE

CRITICAL

TQFN CRITICAL

8 OE*

GND DD+ GND

Y- 2

PI3USB102EZLE

71 14

SSTX-

11 12 13 14 15 16 17 18 19 20 21 22 23

1

Mojo SMC Debug Mux 52 51 45 39 38 37 36 34 30 17 68 65 61

SSTX+

TSSLP-2-1 1

C

USB2_EXTA_MUXED_F_N USB2_EXTA_MUXED_F_P

VBUS

TSSLP-2-1

36

1

1

OUTPUT

3

L H

SMC (M) USB (D)

B

B GND_VOID=TRUE

C4620 0.1UF 71 68 14

IN

71 68 14

IN

USB3_EXTA_R2D_C_N

1

2

71 68

USB3_EXTA_R2D_N

71

USB3_EXTA_R2D_P

C4621 10%

6.3V

CERM-X5R0201

USB3_EXTA_R2D_C_P

0.1UF 1

2

10% 6.3V CERM-X5R0201

GND_VOID=TRUE

GND_VOID=TRUE CRITICAL

D4611

GND_VOID=TRUE 2

2

ESD0P2RF-02LS

ESD0P2RF-02LS

TSSLP-2-1

TSSLP-2-1 1

A

CRITICAL

D4610

1

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

External A USB3 Connector DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

46 OF 120

8

7

6

5

4

3

2

IPD Flex Connector

F-RT-SM

65 64 63 60 42 38 37 34 29 18 68

PP3V3_S4

0

1

20

518S0848

2

68

5% 1/20W MF 0201

PP3V42_G3H

NOSTUFF 1

0.1UF

PLACE_NEAR=J4800.4:3MM

68 34

68 34

(IPD)

1 IN_1 (IPD)

WS_LEFT_OPTION_KBD

2 IN_2 (IPD)

WS_CONTROL_KBD

1

68 34

2

68 34

0402-LF

OUT_1 9

WS_LEFT_SHIFT_KEY

34

OUT_2 8

WS_LEFT_OPTION_KEY

34

OUT_3 7

3 IN_3

WS_CONTROL_KEY

1

68 34

C4807

68 34

0.1UF

2

34

68 34

10% 10V X5R-CERM

68 34 68 34

0201

(IPD)

5

3

SMBUS_SMC_2_S3_SDA

5

D

6

PSOC_SCLK PSOC_MOSI Z2_SCLK PSOC_MISO Z2_MISO

7 8 9 10 11 12

Z2_MOSI PSOC_F_CS_L Z2_CS_L Z2_KEY_ACT_L PICKB_L Z2_HOST_INTN

13 14 15 16 17 18


Pull-up in U5110. OUT_ALL# 6

GND

36 68

68 34

L4807

PP5V_S5

68 65 56

2 4

VOLTAGE=5V MIN_NECK_WIDTH=0.20MM39 MIN_LINE_WIDTH=0.50MM76

FERR-120-OHM-1.5A

TQFN

Z2_CLKIN SMBUS_SMC_2_S3_SCL

PP5V_S4_CUMULUS

68 34

U4850

WS_LEFT_SHIFT_KBD

68

68 34

SLG4AP4103

68 34

34

68 34

4 OE

PP3V3_S4

VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM68 MIN_LINE_WIDTH=0.50MM

10% 16V X7R-CERM 2 0402

VDD

1

PP3V3_TPAD_CONN

76 68 39 36

0.1UF

C4850 1

65 64 63 60 42 38 37 34 29 18 68

C4808

10% 6.3V 2 CERM-X5R 0201

BYPASS=U4850.10:5:5 mm

0 1

J4800

R4808

Left shift, option & control keys combined with power button cause SMC RESET# assertion. Keys ANDed with PSoC power to isolate when PSoC is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).

D

CRITICAL

FF14-18C-R11DL

SMC Manual Reset & Isolation

51 45 39 38 37 36 34 33 30 17 68 65 61 52

1

SMC_TPAD_RST_L

OUT

37

19

R48001 51K

THRM PAD

5% 1/20W MF 2012

1 1

Keyboard Connector 518S0752 CRITICAL

C

J4813

PSOC USB CONTROLLER -

65 64 63 60 42 38 37 34 29 18 68 51 45 39 38 37 36 34 33 30 17 68 65 61 52

USB INTERFACES TO MLB SPI HOST TO Z2 TRACKPAD PICK BUTTONS KEYBOARD SCANNER

60 42 38 37 34 29 18 68 65 64 63

PP3V3_S4

R4804 2

1.5 1

5% 1/16W MF-LF 402

PP3V3_S3_PSOC

1

220K

5% 1/20W MF 2012

OUT 34 68 34 34 34

C4805

1

0.1UF

5% 25V 2 NP0-CERM 0201

R4803

68 34

1

100PF

1

38 36 29

C4804

68 34

C4806

34 68 34

61

IN

68 34 68 34 68 34 68 34 68 34 68 34 68 34 68 34

1 2 3 4 5 6 7 8 9 10 11 12 13 14

WS_CONTROL_KEY Z2_KEY_ACT_L

NC

TPAD_VBUS_EN

NC NC

PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK

68 68

38 37 36 34 68

IN

68

S 1

SMC_LID

68

THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V

R4814 34

WS_KBD15_C

34 68 34 68

337S4426

PAD

42 41 40 39 38 37 36 35 34 33 32 31 30 29

WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3

113

68 68

2

68

R4815

34 68 34 68

34

34 68

WS_KBD16N

1

D 3

Spare MOSFET symbol

34 68

OUT

SMC_ONOFF_L

1


34 34 68

5 G

S 4

NC

NC

68 68

2

68 68 68 68

R4810 68 37 36

34

0

5% 1/16W MF-LF 402

NC

SOT-563

P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 D _ _ _ _ _ _ THRML _ _ _ _ S S + - D 7 7 1 1 1 1

1

1% 1/16W MF-LF 402

DMN5L06VK-7

P2_3 CRITICAL P2_1 OMIT P4_7 P4_5 U4801 P4_3 CY8C24794 MLF-1 P4_1 (SYM-VER2) P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1 7 5 3 1 7 0 0 2 4 6 1 1 1 1 P P P P V D D V P P P P P P

68

SOT-563

Q4801

5 7 1 3 5 7 S D 6 4 2 0 6 4 _ _ _ _ _ _ S D _ _ _ _ _ _ 2 2 0 0 0 0 V V 0 0 0 0 2 2 P P P P P P P P P P P P

D 6

PLACE THESE COMPONENTS CLOSE TO J4800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

DMN5L06VK-7

6 5 4 3 2 1 0 9 8 7 6 5 4 3 5 5 5 5 5 5 5 4 4 4 4 4 4 4

B

68

Q4801

20% 2 6.3V X5R 402

WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18

68

BUTTON_DISABLE

2 G

SMC_PME_S4_WAKE_L PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY

68 34

TPAD Buttons Disable 34

4.7UF

10% 2 6.3V CERM-X5R 0201

WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 34 WS_KBD6 34 WS_KBD7 34 WS_KBD8 34 WS_KBD9 34 WS_KBD10 34 WS_KBD11 34 WS_KBD12 34 WS_KBD13 34 WS_KBD14 34 68 WS_KBD15_CAP 68 WS_KBD16_NUM WS_KBD17 34 WS_KBD18 34 WS_KBD19 34 WS_KBD20 34 WS_KBD21 34 WS_KBD22 34 WS_KBD23 34 68 WS_KBD_ONOFF_L

68 34

BYPASS=U4801.49:50:11 mm BYPASS=U4801.49:50:8 mm BYPASS=U4801.49:50:5 mm


30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

68 34

PLACE_SIDE=BOTTOM

C4810 1 0.1UF

1K

68

2

5% 1/16W MF-LF 402

68 34

20% 10V CERM 2 402

34 68

68 34 68 34

C

32

PP3V3_S4 PP3V42_G3H

WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

B

31

34 68 34 68 34 68

F-RT-SM

34 68

FF14A-30C-R11DL-B-3H

34 68 34 68 34 68 34 68 34 68

57

5 6 7 8 9 0 1 2 3 4 5 6 7 8 1 1 1 1 1 2 2 2 2 2 2 2 2 2

TP_PSOC_SCL TP_PSOC_SDA TP_PSOC_P1_3 TP_ISSP_SCLK_P1_1

WS_KBD4 WS_KBD5 WS_KBD6 TP_ISSP_SDATA_P1_0

ISSP SCLK/I2C SCL R4801

A 71 14

USB_TPAD_P

1

24

2

71

Z2_CLKIN TP_P7_7

USB_TPAD_R_P

1

24

5% 1/20W MF 201

34 68

34 68

2

1 71

USB_TPAD_R_N

C4802 100PF

5% 2 25V NP0-CERM 0201

1

C4803 0.1UF

10% 6.3V 2 CERM-X5R 0201

1

S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

IC

C4801 4.7UF

20% 2 6.3V X5R 402

BYPASS=U4801.22:19:5 mm BYPASS=U4801.22:19:8 mm BYPASS=U4801.22:19:11

A


(PP3V3_S3_PSOC)

R4802 USB_TPAD_N

34 68

ISSP SDATA/I2C SDA

5% 1/20W MF 201

71 14

34 68

TMP102

V+

3V3 LDO

VDD VOUT VDD

PSOC

mm

PIN NAME CURRENT R_SNS 10UA 80UA 60MA (MAX) 60MA (MAX) 8MA (TYP) 14MA (MAX)

2.55 KOHM 10 OHM 0.2 OHM 1.5 OHM

V_SNS 0.0255 0.204 0.6 0.012 0.012 0.021

V V V V V V

KEYBOARD/TRACKPAD (1 OF 2)

POWER 0.255E-6 16.32E-6 36E-3 0.72E-3 96E-6 294E-6

DRAWING NUMBER

W W W W W W

Apple Inc. R

REVISION


BRANCH


PAGE

48 OF 120

SIZE

D

8

7

6

5

4

3

2

1

D

D Keyboard Backlight Connector 516S0899 CRITICAL

J4915

AA07A-S010-VA1 F-ST-SM 12 11

68 58 68 58 35

NC PIN 6 WAS USED KEYBOARD BKLT NOT USED ANYMORE

2 KBDLED_CATHODE2 PPVOUT_S0_KBDBKLT 4 6 8 10 DETECTION

1 3 5 7 9

KBDLED_CATHODE1 58 68 PPVOUT_S0_KBDBKLT 35 58 68 J4915 PIN 5 IS GROUNDED ON KEYBOARD BACKLIGHT FLEX

13 14

C

C

B

B

OUT

A

SYNC_MASTER=J44

A


PAGE TITLE

KEYBOARD/TRACKPAD (2 OF 2) DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

49 OF 120

8

7

6

5

4

3

2

1

D

D U5000 LM4FSXAH5BB 72 68 45 14

BI

72 68 45 14

BI

72 68 45 14

BI

72 68 45 14

BI

72 68 17

IN

72 68 45 14

IN

18

IN

68 45 15

BI

68 45 13

OUT

68 45 13

IN

13

OUT

15

OUT

76 68 62 39

BI

76 68 62 39

BI BI

76 72 68 43 39 32 14 76 72 68 43 39 32 14

BI

76 68 39 34

BI BI

76 68 39 34 76 63 43 39

C

76 63 43 39 38 38 76 68 52 51 39 76 68 52 51 39

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

BI BI BI BI BI BI

44

OUT

44

IN

38

OUT

38

IN

38

OUT

60 40 38

OUT

58

OUT

38

OUT

38

B

51

IN

38

OUT

38

OUT

70 37

BI

70 37

OUT

38

IN

37

IN

38 34 29

IN

37 23 18

IN

61 37

OUT

38 37

IN 38

38 37 34

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK24M_SMC LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ PM_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L SMC_WAKE_SCI_L

IN

38

OUT

37

IN

52 51 37

IN

18 13

IN

68 63 61 18 17 13

IN

63 61 29 18 13

IN

61 13

IN

68 37 34

IN

68 45 37

IN

68 45 37

OUT

30

OUT

63 38

OUT

(OD) (OD)

(OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD)

B13 A13 C12 D11 H12 D12 C13 H13 G11 F13 F12 B12 E10 D13 M4 N2 N8 M8 L8 K8 N7 M7 N4 N3

BGA LPC0AD0 (1 OF 2) LPC0AD1 LPC0AD2 OMIT_TABLE LPC0AD3 LPC0CLK LPC0FRAME* LPC0RESET* LPC0SERIRQ LPC0CLKRUN* LPC0PD* LPC0SCI* PK5 I2C0SCL I2C0SDA I2C1SCL I2C1SDA I2C2SCL I2C2SDA I2C3SCL I2C3SDA I2C4SCL I2C4SDA I2C5SCL I2C5SDA

H11 L13 C11 A12 G3

SMC_FAN_0_CTL SMC_FAN_0_TACH NC_SMC_FAN_1_CTL NC_SMC_FAN_1_TACH SMC_TOPBLK_SWP_L SMC_SENSOR_PWR_EN

PM6/FAN0PWM0 PM7/FAN0TACH0 PK6/FAN0PWM1 PK7/FAN0TACH1 PN2/FAN0PWM2 D10 PN3/FAN0TACH2

SMC_SYS_KBDLED NC_SMC_ACTUATOR_DISABLE_L NC_SMC_5VSW_PWR_EN SYS_ONEWIRE NC_SMC_FAN_5_CTL SMC_PCH_SUSACK_L (OD)

L11 N12 N11 M11 J4 J2

PN4/FAN0PWM3 PN5/FAN0TACH3 PN6/FAN0PWM4 PN7/FAN0TACH4 PH2/FAN0PWM5 PH3/FAN0TACH5

C4 PECI0RX C6 PECI0TX

CPU_PECI_R SMC_PECI_L NC_SMC_BIL_BUTTON_L SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_S4_WAKESRC_EN SMC_SENSOR_ALERT_L NC_SMC_T101_COM_1 SMC_LID SMC_PCH_SUSWARN_L SMS_INT_L SMC_BC_ACOK PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L

M13 L12 M5 J12 (OD)

(OD)

J13 L5 D8 K6

PP0/IRQ116 PP1/IRQ117 PP2/IRQ118 PP3/IRQ119 PP4/IRQ120 PP5/IRQ121 PP6/IRQ122 PP7/IRQ123

D4 E4 F5 N5 N6 K5 M6 L6

PQ0/IRQ124 PQ1/IRQ125 PQ2/IRQ126 PQ3/IRQ127 PQ4/IRQ128 PQ5/IRQ129 PQ6/IRQ130 PQ7/IRQ131

L3 U0RX M1 U0TX

SMC_RX_L SMC_TX_L SMC_PWRFAIL_WARN_L SMC_WIFI_PWR_EN

(OD)

E13 USB0DM(PL7) E12 USB0DP (PL6)

AIN00 E2 AIN01 E1 AIN02 F2 AIN03 F1 AIN04 B3 AIN05 A3 AIN06 B4 AIN07 A4 AIN08 B5 AIN09 A5 AIN10 B6 AIN11 A6 AIN12 C1 AIN13 C2 AIN14 B1 AIN15 B2 AIN16 G2 AIN17 G1 AIN18 H1 AIN19 H2 AIN20 B7 AIN21 A7 AIN22 B8 AIN23 A8

C0C0+ C1PC5/C1+ T3CCP1/PJ5/C2T3CCP0/PJ4/C2+

K2 K1 L2 L1 C5 D5

SMC_CPU_HI_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_BMON_DISCRETE_ISENSE SMC_CPU_ISENSE SMC_OTHER5V_HI_ISENSE SMC_OTHER3V3_HI_ISENSE SMC_DDR_ISENSE SMC_LCDBKLT_ISENSE SMC_ADC11_PD SMC_ADC12_PD SMC_SSD_ISENSE SMC_PP3V3S0_ISENSE SMC_CAMERA_ISENSE SMC_ADC16_PD SMC_PP5VS0_ISENSE SMC_CPUDDR_ISENSE SMC_PCH_ISENSE SMC_CPU_VSENSE SMC_LCDPANEL_ISENSE SMC_CPU_IMON_ISENSE SMC_TBT_ISENSE

SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT

U1RX/B0 U1TX/PB1 T0CCP0/PB6 T0CCP1/PB7

F11 E11 F4 F3

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L NC_SMC_SYS_LED NC_SMC_GFX_THROTTLE_L

SSI1RX/PF0 SSI1TX/PF1 SSI1CLK/PF2 SSI1FSS/PF3 PF4 PF5

M9 N9 L10 K10 L9 K9

SPI_SMC_MISO SPI_SMC_MOSI SPI_SMC_CLK SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK

WT0CCP0/PG4 K7 WT0CCP1/PG5 L7 WT2CCP0/PH0 K3 WT2CCP1/PH1 K4

SMC_DEBUGPRT_EN_L NC_SMC_GFX_OVERTEMP ALL_SYS_PWRGD SMC_THRMTRIP

J3 H4 H3 G4

PM_PWRBTN_L PM_SYSRST_L NC_MEM_EVENT_L SMC_ADAPTER_EN

T1CCP0/PJ0 C9 T1CCP1/PJ1 B9 T2CCP0/PJ2 A9 T2CCP1/PJ3 C8

SMC_OOB1_D2R_L SMC_OOB1_R2D_L SMC_BOARDID NC_BDV_BKL_PWM

WT3CCP0/PH4 WT3CCP1/PH5 WT4CCP0/PH6 WT4CCP1/PH7

WT5CCP1/PM3 H10

38 40

IN

38 40

IN

38 40

IN

38 40

IN

38 40

IN

38 42

IN

38 41

IN

38 40

IN

38 40

IN

38 41

IN

38 40

IN

38

IN

38

IN

38 41

IN IN

38 41

IN

38

IN IN

38 41

IN

38 41

IN

38 42

IN

38 42

IN

38 42

IN

38 42

CPU_PROCHOT_L IN SMC_VCCIO_CPU_DIV2 IN SMC_S5_PWRGD_VIN IN SPI_DESCRIPTOR_OVERRIDE_LOUT CPU_CATERR_L IN CPU_THRMTRIP_3V3 IN

M2 M3 L4 N1

SSI0CLK/PA2 SSI0FSS/PA3 SSI0RX/PA4 SSI0TX/PA5

IN

PM_BATLOW_L

(OD)

38 42

C5002 1UF

20% 2 6.3V X5R 0201

1

C5003 0.1UF

10% 2 10V X5R-CERM 0201

1

C5004 0.1UF

10% 2 10V X5R-CERM 0201

1

C5005 0.1UF

10% 2 10V X5R-CERM 0201

1

R5002 1M

0.1UF

45 38 37 68 52

63

IN

1

C5007 0.1UF

10% 10V 2 X5R-CERM 0201

1

C5008 0.1UF

10% 10V 2 X5R-CERM 0201

1

BI

C5009 0.1UF

10% 10V 2 X5R-CERM 0201

37

IN

37

SMC_RESET_L WIFI_EVENT_L (OD) SMC_WAKE_L NC_SMC_HIB_L SMC_CLK32K NC_SMC_XOSC1 SMC_EXTAL SMC_XTAL

37

17 24 25 37 72 37

33 37 71

OUT

38

PP1V2_S5_SMC_VDDC

38

IN

45 72

OUT

45 72

OUT

45 72

OUT

45 72

IN

56 61

IN

13 16 17 72

OUT

33

IN

38

IN

16 17 61


37

OUT

13 16 72

OUT

13 17 68 72

0.1UF

BGA (2 OF 2) G10 RST* SWCLK/TCK C10 SWDIO/TMS A10 B11 PK4/RTCCLK SWO/TDO A11 N13 WAKE* TDI B10 M12 HIB* NC A2 NC M10 XOSC0 N10 XOSC1 VDDA D3 G12 OSC0 G13 OSC1 VREFA+ D2 VREFA- D1 K12 VBAT 42 41 40 C338 37 D7 GNDA E3 E6 OMIT_TABLE E8 A1 E9 C7 F10 D9 VDD J7 E5 J9 F9 J10 H5 H9 GND J1 J5 J6 J8 VDDC J11 K13 D6 K11

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

37 45 68 37 45 68 37 45 68

C

37 45 68

PP3V3_S5_AVREF_SMC

37 68

XW5000 SM 2

GND_SMC_AVSS

1

PLACE_NEAR=U5000.A1:4MM

1

C5020 0.01UF

10% 10V 2 X5R-CERM 0201

1

C5021 1UF

20% 6.3V 2 X5R 0201

BYPASS=U5000.D2:D1:1MM BYPASS=U5000.D2:D1:1MM

B

PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM PLACE_NEAR=U5000.J1:5MM PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM PLACE_NEAR=U5000.J1:5MM

1

C5010 1.0UF

OUT

C5001

10% 10V 2 X5R-CERM 0201

LM4FSXAH5BB

6 70

OUT

1

U5000

5% 1/20W MF 2 201

10% 2 10V X5R-CERM 0201

PP3V3_S5_SMC_VDDA MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

1

C5006

37

33 37 71

2 0402

1

17

IN

OUT

1

37

13 72

BI

L5001

30-OHM-1.7A

37

37 56 61

BI

45 51 52

6 37 53 70

OUT OUT

17 30 33 34 37 38 39 61 65 68

38 41

OUT OUT

PP3V42_G3H

20% 6.3V 2 X5R 0201-1

1

C5017 1.0UF

20% 6.3V 2 X5R 0201-1

1

C5015 0.1UF

10% 10V 2 X5R-CERM 0201

1

C5016 0.1UF

10% 10V 2 X5R-CERM 0201

1

C5014 1.0UF

20% 6.3V 2 X5R 0201-1

1

C5012 0.1UF

10% 10V 2 X5R-CERM 0201

1

C5013 0.1UF

10% 2 10V X5R-CERM 0201

1

C5011 0.1UF

10% 10V 2 X5R-CERM 0201

38 13 37

IN

30

OUT

30

OUT

38

OUT

38

OUT

13 25

NOTE: SMS INTERRUPT IS NOT USED, PULL UP TO SMC RAIL.

A

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

A

S YNC _MA ST ER =J 44 PAGE TITLE

S YNC _D AT E= 08 /1 2/ 20 13

SMC DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

50 OF 120

8

7

6

5

4

3

2

1

SMC Reset "Button", Supervisor & AVREF Supply 68 65 45 39 38 33 30 17 37 36 34 61 52 51

R5127 PP3V42_G3H

0

1

42 41 40 38 37 36

70 53 36 6

2

5% 1/16W MF-LF 402

1

BI

CPU_PROCHOT_L

PP3V42_G3H_SMC_SPVSR MIN_LINE_WIDTH=0.4 mm NOSTUFF MIN_NECK_WIDTH=0.1 mm

C5131 1

4.7UF

GND_SMC_AVSS PP3V42_G3H 17

Q5159

6 D

C5127 VOLTAGE=3.42V

DMN5L06VK-7

5% 25V NP0-C0G-CERM 2 0201 PLACE_NEAR=Q5159.6:5MM

PP1V05_S0

G 2

1 S

51 45 39 38 37 36 34 33 30 68 65 61 52

D

34

IN

68 37 36 34

IN

SMC_PROCHOT 1

Desktops: 5V Mobiles: 3.42V

C5120 1

V+

0.47UF

10% 6.3V CERM-X5R 2 402

DFN 6 MR1* (IPU) SN0903049 7 MR2* (IPU) 4 DELAY

SMC_MANUAL_RST_L OMIT

1

R5101

GND

C5101 1

0

2

1

20% 10V X5R-CERM 2 0402-1

10% 2 10V X5R-CERM 0201

10UF

SILK_PART=SMC_RST

C

DMN5L06VK-7

OUT

G 5 IN

1NOSTUFF

R5153

5% 1/20W MF 2201

36 37

37 36

CRITICAL

Q5158

52 51 37 36

SMC_BC_ACOK

SMC_BC_ACOK

MAKE_BASE=TRUE

43

1

70 36

DFN1006-3

R5158

2

3.3K 2 1 PM_THRMTRIP_R_L

34 36 37 68

5% 1/20W MF 201

OUT

To SMC

1

C5134

CPU_PECI

47PF

BI

6

70

From/To CPU/PCH

MF 201

5% 25V 2 NP0-C0G-CERM 0201 PLACE_NEAR=Q5150.2:5MM

PLACE_SIDE=TOP

C

SMC_XTAL_R CRITICAL

1% 1/20W MF 201

R5167 R5168

SMC_ONOFF_L SMC_SENSOR_ALERT_L SMC_LID SMC_TX_L SMC_RX_L SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK

R5170 R5172 R5171 R5173 R5174 R5175 R5176 R5177 R5178 R5179 R5180

1 1 100K 1 10K 1 100K 1 20K 1 20K 1 10K 1 10K 1 10K 1 10K 1

2 2 2 2 2 2 2 2 2 2 2

SMC_BC_ACOK SMC_S5_PWRGD_VIN SMS_INT_L

R5187 100K 1 R5192 100K 1 R5193 10K 1

2 2 2

37 36

CPU_THRMTRIP_3V3

R5117

2

68 45

SMC_ROMBOOT

68 37 36 34 38 36

Y5110

38 36 34

3.2X2.5MM-SM

68 45 36

12.000MHZ-30PPM-10PF-85C

SMC_EXTAL

1

68 45 36

3

71 36 33

2 4 1

C5110 12PF

5% 2 25V NP0-C0G-CERM 0201

NCNC

71 36 33

1

C5111

37 36 23 18

12PF

SMC_PME_S4_DARK_L

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

IN

18 23 36 37

68 45 36 68 45 36

5% 2 25V NP0-C0G-CERM 0201

60 57 53 37 17 16 15 11 8 6 68 65 61

R5112 22

13

IN

PM_CLK32K_SUSCLK_R 1 PLACE_NEAR=U0500.AE6:5.1mm

2

68 45 36

PP1V05_S0

68 45 36

1

R5197

SMC_CLK32K

5% 1 / 20 W MF 2 0 1

100K

OUT

36

36

SMC_VCCIO_CPU_DIV2

52 51 37 36

1% 1/20W MF 2201

36 36

1

R5196 100K

PP3V3_S4

PP3V3_S0

SMC_PME_S4_DARK_L SMC_DP_HPD_L

SMC_DP_HD_L IS NOT USED ANY MORE 36

2.49K2

1

PP3V42_G3H

51 45 39 38 37 36 34 33 30 17 68 65 61 52 68 65 64 63 60 42 38 34 29 18 77 68 65 64 62 61 30 28 24 18 17 15 13 12 11 8 50 47 46 44 43 42 41 40 39 38

37 36 23 18

1% 1/20W MF 2201

100K 1 100K 1

10K 10K

100K 1

2 2

5% 5%

1 /2 0W 1/20W

MF MF

2 01 201

5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%

1 /2 0W 1/20W 1 /2 0W 1 /2 0W 1 /2 0W 1 /2 0W 1 /2 0W 1 /2 0W 1 /2 0W 1 /2 0W 1 /2 0W

MF MF MF MF MF MF MF MF MF MF MF

2 01 201 2 01 2 01 2 01 2 01 2 01 2 01 2 01 2 01 2 01

5% 5% 5%

1 /2 0W 1 /2 0W 1 /2 0W

MF MF MF

2 01 2 01 2 01

5%

1 /2 0W

MF

2 01

5% 5% 5%

1 /2 0W 1 /2 0W 1 /2 0W

MF MF MF

2 01 2 01 2 01

5%

1 /2 0W

MF

2 01

5%

1 /2 0W

MF

2 01

B

1

R5188 1K

5% 1/20W MF 2 201

61 56 36 36 13 37 36

A

1 2 CPU_PECI_R 5% NOSTUFF 1/20W

PM_THRMTRIP_L IN 15 37 72

SILK_PART=PWR_BTN

R5110

B

330

R5134

3

MMBT3904LP-7

36 37 51 52

SMC USB Clock require these crystal values:5,6,8,10,12,16,18,20,24,25 MHz

36

R5151

5% 1/20W MF 2201

CPU_THRMTRIP_3V3

OUT

SMC Crystal Circuit

36

1

5% 1/10W MF-LF 2603

SILK_PART=PWR_BTN

SMC_XTAL

S 2

SMC_PECI_L_R

2

5% 1/20W MF 0201

36 37 38 40 41 42

R5115 0

0

1

1.6K

SMC_THRMTRIP

1

0

5% 1/10W MF-LF 6032

SMC_PECI_L

From SMC

72

SMC_ONOFF_L OMIT

IN

70 36

SOT-563

0.01UF

GND_SMC_AVSS

1 G

R5152

Q5159

3 D

36 38 45 52 68

36 68

C5126


Debug Power "Buttons" OMIT

OUT

SYM_VER_2

PM_THRMTRIP_L

4 S

C5125 1

PLACE_SIDE=BOTTOM

R51161

SMC_RESET_L MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

OUT

PAD

9

10% 10V X5R-CERM 2 0201

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.

PLACE_SIDE=BOTTOM

72 37 15

PP3V3_S5_AVREF_SMC

REFOUT 8 CRITICAL THRM

D

D 3

DFN1006H4-3

5% 1/20W MF 2201

RESET* 5

0.01UF

5% 1/10W MF-LF 2 603

Q5150

DMN32D2LFB4

100K

VREF-3.3V-VDET-3.0V

SMC_TPAD_RST_L SMC_ONOFF_L

IN

R5100

VIN

61 65 68 6 8 11 15 16 17 37 53 57 60

CRITICAL 36

1

3

U5110

SMC12 PECI Support

SOT-563

47PF

20% 6.3V 2 X5R 402

SMC_PM_G2_EN SMC_ADAPTER_EN SMC_THRMTRIP

72 36 25 24 17

SMC_DELAYED_PWRGD

61 36

SMC_S4_WAKESRC_EN

R5198 100K 1 R5185 10K 1 R5186 10K 1 R5191 100K 1 R5190 100K 1

2 2 2 2 2

A



SMC Shared Support DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

51 OF 120

8

7

6

5

SMC12 ADC Assignments

D

C

OUT

SMC_CPU_HI_ISENSE

SMC_CPU_HI_ISENSE

IN

36 38 40

40 38 36

OUT

SMC_PBUS_VSENSE

40 38 36

OUT

SMC_BMON_ISENSE

40 38 36

OUT

SMC_DCIN_ISENSE

SMC_PBUS_VSENSE

IN

36 38 40

SMC_BMON_ISENSE

IN

36 38 40

SMC_DCIN_ISENSE

IN

36 38 40

40 38 36

OUT

SMC_DCIN_VSENSE

42 38 36

OUT

SMC_BMON_DISCRETE_ISENSESMC_BMON_DISCRETE_ISENSE

SMC_DCIN_VSENSE

IN

36 38 40

IN

36 38 42

41 38 36

OUT

SMC_CPU_ISENSE

40 38 36

OUT

SMC_OTHER5V_HI_ISENSE

SMC_CPU_ISENSE

IN

36 38 41

SMC_OTHER5V_HI_ISENSE

IN

36 38 40

40 38 36

OUT

41 38 36

OUT

40 38 36

OUT

SMC_OTHER3V3_HI_ISENSE SMC_OTHER3V3_HI_ISENSE

IN

36 38 40

SMC_DDR_ISENSE SMC_LCDBKLT_ISENSE

SMC_DDR_ISENSE

IN

36 38 41

SMC_LCDBKLT_ISENSE

IN

36 38 40

38 36

OUT

SMC_ADC11_PD

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

SMC_ADC11_PD

36 38

SMC_ADC12_PD

36 38

MAKE_BASE=TRUE

OUT

SMC_ADC12_PD

OUT

SMC_SSD_ISENSE

41 38 36

OUT

SMC_PP3V3S0_ISENSE

42 38 36

OUT

SMC_CAMERA_ISENSE

38 36

OUT

SMC_ADC16_PD

41 38 36

OUT

SMC_PP5VS0_ISENSE

41 38 36

OUT

SMC_CPUDDR_ISENSE

41 38 36

OUT

SMC_PCH_ISENSE

42 38 36

OUT

SMC_CPU_VSENSE

42 38 36

OUT

SMC_LCDPANEL_ISENSE

42 38 36

OUT

SMC_CPU_IMON_ISENSE

42 38 36

OUT

SMC_TBT_ISENSE

R5215

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_PP3V3S0_ISENSE

MAKE_BASE=TRUE

SMC_CAMERA_ISENSE

MAKE_BASE=TRUE

SMC_ADC16_PD

IN

PCH_SML1ALERT_L

100

1

IN

36 38 41

IN

36 38 41

IN

36 38 42

IN

SMC_CPUHI_COMP_ALERT_L

IN

SMC_CPUDDR_ISENSE

IN

36 38 41

SMC_PCH_ISENSE

IN

36 38 41

SMC_CPU_VSENSE

IN

36 38 42

SMC_LCDPANEL_ISENSE

IN

36 38 42

SMC_CPU_IMON_ISENSE

IN

36 38 42

SMC_TBT_ISENSE

IN

36 38 42

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

100

IN

1

SMC_BMON_COMP_ALERT_L

100

NC

B

36 38

NC_SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA

36 38

MAKE_BASE=TRUE NO_TEST=TRUE

NC_SMC_SYS_LED NC_SMC_GFX_THROTTLE_L

38 36

NC_SMC_GFX_OVERTEMP

38 36

NC_SMC_FAN_1_CTL

38 36

NC_SMC_FAN_1_TACH

38 36

NC_SMC_5VSW_PWR_EN

38 36

NC_SMC_FAN_5_CTL

36 38

36 38

NC_SMC_GFX_THROTTLE_L

36 38

NC_SMC_GFX_OVERTEMP

36 38

MAKE_BASE=TRUE

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

NC_SMC_FAN_1_CTL

36 38

NC_SMC_FAN_1_TACH

36 38


NC_SMC_BIL_BUTTON_L NC_MEM_EVENT_L

38 36

NC_SMC_T101_COM_1

NC_SMC_FAN_5_CTL

36 38

NO_TEST=TRUE NO_TEST=TRUE

IN

CPUTHMSNS_THM_L

1

100

5% 1/20W MF 201 IN

2

36 38

NC_MEM_EVENT_L

36 38

NC_SMC_T101_COM_1

36 38

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1

CPUTHMSNS_ALERT_L

R5220 43

IN

1

TBTTHMSNS_THM_L

100

5% 1/20W MF 201 43

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

NC_SMC_ACTUATOR_DISABLE_LNC_SMC_ACTUATOR_DISABLE_L

IN

TBTTHMSNS_ALERT_L

SMC_PCH_SUSWARN_L

0

1

MAKE_BASE=TRUE

OUT

100

2

DESCRIPTION

REFERENCE DES

CRITICAL

1

SUBASSY,PCBA HALL EFFECT,J44

J5250

CRITICAL

BOM OPTION

CPUTHRM_ALRT:SMC

2

TBTTHRM_THRM:SMC

Specify one of these BOM GROUPs.

R5210 1

100

2

TABLE_BOMGROUP_HEAD

TBTTHRM_ALRT:SMC

BOM GROUP

BOM OPTIONS

CPUTHRM:BOTH

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC

CPUTHRM:THRM

CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PU

CPUTHRM:ALRT

CPUTHRM_THRM:PU,CPUTHRM_ALRT:SMC

CPUTHRM:NONE

CPUTHRM_THRM:PU,CPUTHRM_ALRT:PU

C

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

OUT

36 37

PP3V42_G3H

TABLE_BOMGROUP_HEAD

BOM GROUP


R5232

5% 1/20W MF 2201

SMC_BOARDID

38 36

TB TTHR M_T HRM: SMC ,TBT THR M_AL RT:S MC

TBTTHRM:THRM

TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU

TBT THRM :ALRT

T BTT HRM_ THRM :PU, TBTT HRM_ ALR T:SM C

TBTTHRM:NONE

TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

SMCBOARDID:16

SMC_BOARDID

TBT THRM :BOTH

TABLE_BOMGROUP_ITEM

10K

MAKE_BASE=TRUE

TABLE_BOMGROUP_ITEM

TBTTHRM:GONE

1

R5233 Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.

5% 1/20W MF 2201

SMCBOARDID:8

36 38

PCH_SUSWARN_L

2

1

MAKE_BASE=TRUE

63 38 36

0

2

18 29 34 37 38 42 60 63 68

B

64 65

1 OUT

PCH_SUSACK_L

IN

13

R5282

S4 SMC Wake Sources

13

5% 1/20W MF 0201

SMC_PCH_SUSACK_L

60 40 38 36

38 36 34 29

IN

SMC_PME_S4_WAKE_L

38 36 34 29

IN

SMC_PME_S4_WAKE_L

100K

5% 1/20W MF 2201

SMC_PME_S4_WAKE_L MAKE_BASE=TRUE

65 64 63 60 42 38 37 34 29 18 68

OUT

63 38 36

SMC_SENSOR_PWR_EN SMC_SENSOR_PWR_EN

SMC_SENSOR_PWR_EN MAKE_BASE=TRUE

PP3V3_S4

29 34 36 38

5% 1/20W MF 0201 36 38 40 60

60 40 38 36

SMC_WIFI_PWR_EN

R5295

10K

SMC_SENSOR_PWR_EN

R5294

10K

1

2

5%

1/20W

MF

201

5%

1/20W

MF

201

NOSTUFF 1

2

36 38 40 60

NOSTUFF

SMC_WIFI_PWR_EN

SMC_WIFI_PWR_EN

MAKE_BASE=TRUE

36 38 63

38 36 38 36 38 36

SMC_ADC16_PD SMC_ADC12_PD SMC_ADC11_PD

Top Block Swap

1

R5284 100K

PP3V3_S0

5% 1/20W MF 2201

62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 39 40 41 42 43 44 46 47 50 61

NOSTUFF

1

R5296

42 41 40 38 37 36

1K

5% 1/20W MF 2012 IN

QTY

677-0912

Specify one of these BOM GROUPs. 51 45 39 38 37 36 34 33 30 17 68 65 61 52

R5231

36

0.001UF


IN

A

C5250

5% 1/20W MF 201

PP3V3_S4

36

1

34 36 37

639-4502 (J44 HALL EFFECT BOARD) REPORTS TO 677-0912

5% 1/20W MF 201

R5230 36

5% 1/16W MF-LF 402

NC

SMC_LID

PART NUMBER CPUTHRM_THRM:SMC

R5214

10K

NC_SMC_BIL_BUTTON_L

MAKE_BASE=TRUE

2

2

R5216

38 36 36 38

MAKE_BASE=TRUE

38 36

NO_TEST=TRUE

NC_SMC_5VSW_PWR_EN

MAKE_BASE=TRUE

0

1

5% 1/20W MF 201

1


MAKE_BASE=TRUE

D R5250 SMC_LID_R

10% 2 50V X7R-CERM 0402

SMC_SENSOR_ALERT_L

NC_SMC_SYS_LED

MAKE_BASE=TRUE

38 36

38 36

NO_TEST=TRUE

NC_BDV_BKL_PWM MAKE_BASE=TRUE

NC

TABLE_BOMGROUP_ITEM

NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL

38 36

NC_BDV_BKL_PWM

8 7 6 5

TABLE_BOMGROUP_ITEM

38 36

38 36

39 45 51

SM

1 2 3 4

NC

2

5% 1/20W MF 201

SMC12 Pin Assignments

38 36

17 30 33 34 36 37 38 52 61 65 68

BMONHYS

43

MAKE_BASE=TRUE

1

PP3V42_G3H

J5250

R5217 41

43

36 38 41

MAKE_BASE=TRUE

OMIT_TABLE

HALL-EFFECT-SENSOR-MLB-D1

R5213

SMC_PP5VS0_ISENSE

MAKE_BASE=TRUE

APN: 998-4692 CPUHYS

36 38

MAKE_BASE=TRUE

38 36

1

2

5% 1/20W MF 201

42

MAKE_BASE=TRUE

MAKE_BASE=TRUE

2

Hall Effect Pads

NOSTUFF 14

MAKE_BASE=TRUE

38 36

3

Thermal Alerts

40 38 36

41 38 36

4

SMC_TOPBLK_SWP_L

R5283 1

1K

5% 1/20W MF

2

PCH_STRP_TOPBLK_SWP_L

OUT

15

GND_SMC_AVSS

1

R5285 100K

5% 1/20W MF 2201

NOSTUFF

1

R5286

SMC_RESET_L

100K

5% 1/20W MF 2201

NOSTUFF

A

36 37 45 52 68

PAGE TITLE

NOSTUFF

C5270 1

SMC Project Support DRAWING NUMBER

1000PF

10% 16V X7R-CERM 2 0201

Apple Inc. GND_SMC_AVSS

R 36 37 38 40 41 42

SIZE

D

REVISION


BRANCH


PAGE

52 OF 120

8

7

6

5

LYNX POINT LP S0 "SMBus 0" Connections 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

LYNX POINT LP

1K

U0500

5% 1/20W MF 2012

(MASTER)

D

39 19 16 14 72 68 63 39 19 16 14 72 68 63

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

R53001

1

R5301 HDMI Redriver (on RIO) 1K

5% 1/20W MF 2 201

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_DATA


3

2.0K

U5000

14 16 19 39 63 68 72

68 62 39 36 76

14 16 19 39 63 68 72

68 62 39 36 76

52 51 45 38 37 36 34 33 30 17 68 65 61

R53501 5% 1/20W MF 2012

(MASTER)

2

R5351

Internal DP

5% 1/20W MF 201

(See Table)

1

2.0K

2

R53801

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA 36

36 39 62 68 76 39 62 68 76

52 51 39 36 76 68 52 51 39 36 76 68

1

R5381

2.0K

U5000

2.0K

5% 1/20W MF 2012

(MASTER)

SMBUS_SMC_0_S0_SCL MAKE_BASE=TRUE

PP3V42_G3H

SMC

J8300

MAKE_BASE=TRUE

1

SMC SMBus "5" G3H Connections

PP3V3_S0

SMC

J9510

(WRITE: 0xCC READ: 0xCD)

SMBUS_PCH_CLK

4

SMC SMBus "0" S0 Connections

5% 1/20W MF 2 201

Battery Charger

ISL6259 - U7100 (Write: 0x12 Read: 0x13)

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SDA 36 39 51


52 68 76

Battery

VRef DACs

U2200

SMBUS_PCH_CLK

72 19 16 14 68 63 39

SMBUS_PCH_DATA

J7050

Battery Battery Manager - (Write: 0x16 Read: 0x17)

(Write: 0x98 Read: 0x99) 72 19 16 14 68 63 39

D

36 39 51 52 68 76

(See Table) SMBUS_SMC_5_G3_SCL

36 39 51 52 68 76

SMBUS_SMC_5_G3_SDA 36 39 51 52 68 76

Margin Control

SMC SMBus "3" S0

U2201

Connections

(Write: 0x30 Read: 0x31) 72 19 16 14 68 63 39

SMBUS_PCH_CLK

72 19 16 14 68 63 39

SMBUS_PCH_DATA

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

J44 Samsung

Internal DP Parade T-con

- (0x10-0x2F or 0x30-0x4F)

Y

LGD

SMC

Y

U5000

(MASTER)

XDP Connectors

J1800

C

63 43 39 36 76


(MASTER) 39 19 16 14 72 68 63 39 19 16 14 72 68 63

PP3V3_S0


68 65 60 42 19 18 15

R5391 2.0K

5% 1/20W MF 2012

5% 1/20W MF 2 201

SMBUS_SMC_3_SCL

C

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA MAKE_BASE=TRUE

X29 Temp (on RIO)

R53701 1K

U5000

5% 1/20W MF 201 2

(MASTER)

1

R5371 1K

5% 1/20W MF 2201

TMP105: J9510

Trackpad

(Write: 0x92 Read: 0x93)

J4800

SMBUS_SMC_3_SCL

(Write: 0x90 Read: 0x91)

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_2_S3_SDA 34 36 39

MAKE_BASE=TRUE

68 39 36 34 76

1

2.0K

PP3V3_S3

SMC

68 39 36 34 76

R53901

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

36 39 43 63 76 36 39 43 63 76

34 36 39 68 76

68 76

TBT & MLB Prox

EMC1412: U5850 (Write: 0xD8 Read: 0xD9) SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

B

36 39 43 63 76 36 39 43 63 76

B

LYNX POINT LP S0 "SMLink 0" Connections 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

LYNX POINT LP

U0500

(MASTER) 72 14

SML_PCH_0_CLK

72 14

SML_PCH_0_DATA


PP3V3_S0

R53101 8.2K

5% 1/20W MF 2012

1

PP3V3_S0

R5311

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

8.2K

5% 1/20W MF 2 201

SMC

U5000

MAKE_BASE=TRUE

(MASTER)

MAKE_BASE=TRUE

39 36 32 14 76 72 68 43 39 36 32 14 76 72 68 43

LYNX POINT LP S0 "SMLink 1" Connections

R53601 2.0K

5% 1/20W MF 2012

1

R5361 2.0K

5% 1/20W MF 2201

CPU, Mem, Airflow, Fixstack Prox

EMC1704-02: U5870 (Write: 0x98 Read: 0x99)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SCL

72 76 14 32 36 39 43 68

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SDA

72 76 14 32 36 39 43 68


ALS

J4002

(Write: 0x72 Read 0x73)

LYNX POINT LP

A

U0500 (Write: 0x88 Read: 0x89) 39 36 32 14 76 72 68 43 39 36 32 14 76 72 68 43

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

72 76 14 32 36 39 43 68

SMBUS_SMC_1_S0_SDA

72 76 14 32 36 39 43 68


DRAWING NUMBER

Apple Inc. R

SMLink 1 is slave port to access PCH.

A


SMBus Connections SIZE

D

REVISION


BRANCH


PAGE

53 OF 120

8

7

6

5

4

PCH 1.05V Current Sense (IC1C) Gain: 500x, EDP: 5 A Rsense: 0.001 (R7640) or Rsense SHORT PP3V3_S4SW_SNS 65 60 42 41 40 Vsense: 5 mV, Range: 6.6 A SMC ADC: 19

1

20% 10V 2 CERM 402

V+

D

77 57

77 57

IN

ISNS_1V05_S0_N

5 IN-

IN

ISNS_1V05_S0_P

4 IN+

PLACE_NEAR=R7640.3:5MM PLACE_NEAR=R7640.4:5MM

INA211 SC70

OUT 6

500x

REF 1

P1V05S0_IOUT

PLACE_NEAR=U5000.H2:5MM 77 54

R5569 4.53K2

1

1% 1/20W MF 201

1

R5565

2

LOADISNS

SMC_PCH_ISENSE 1

OUT

C5569

77 54

20% 2 6.3V X5R 0201

LOADRC:YES

PLACE_NEAR=U5560.6:5MM

77 54

GND_SMC_AVSS

36 37 38 40 41 42

LOADISNS

DDR 1.35V S3 (CPU & Memory) Current Sense (IM0C) Gain: 100x, EDP: 9 A Rsense: 0.002 (R7450) or XW7450 PP3V3_S4SW_SNS 41 40 Vsense: 21 mV, Range: 16.5 A 42 65 60 SMC ADC: 09

DDRISNS

BYPASS=U5570.3:5MM

1

20% 10V 2 CERM 402

V+

U5570

77 55

77 55

IN IN

NC_ISNS_DDR_S3N NC_ISNS_DDR_S3P

5 IN4 IN+

INA214 SC70

OUT 6

100x

ISNS_DDR_IOUT 1

R5575

REF 1

2

DDRISNS

SMC_DDR_ISENSE 1

OUT

36 38

C5579

65 30

1

OMIT Short Rsense

73 65 20 19 17 55 22 21

0

0 1 W MF 77 ISNS_CPUDDR_P 0612-SHORT 2 4 PLACE_NEAR=U5510.4:10MM

4 IN+

INA210 SC70

20% 2 10V CERM 402

OUT 6

200x

ISNS_CPUDDR_IOUT

PP3V3_S4SW_SNS

65 60 42 41 40

CRITICAL

36 37 38 40 41 42

1 3 77 ISNS_SSD_N

4.53K2

1

1% 1/20W MF 201

SMC_CPUDDR_ISENSE 1

OUT

36 38

C5519

OMIT Short Rsense

65 60


R5520 1

3 77 ISNS_PP3V3S0_N

0

0 1 W MF 77 ISNS_PP3V3S0_P 0612-SHORT 2 4 PLACE_NEAR=U5520.4:10MM

PP3V3_S0_FET

4 IN+

100x

4 IN+

6

PLACE_NEAR=U5000.C2:5MM

R5589 4.53K

ISNS_S0_SSD_IOUT

1

R5585 20K


1

OUT

36 38

C5589

C

0.22UF

20% 2 6.3V X5R 0201

5% 1/20W MF 2 201

GND 2

CRITICAL

SMC_SSD_ISENSE

2

1% 1/20W MF 201

1

REF 1

PLACE_NEAR=U5000.C2:5MM

36 37 38 40 41 42

0.1UF

INA211 SC70

OUT 6

500x

ISNS_PP3V3S0_IOUT

1% 1/20W MF 2 201

1% 1/20W MF 201

20K

SMC_PP3V3S0_ISENSE 1

2 1% 1/16W MF-LF 402 5 MCP6541T CPUHYS SC70-5 1 CPUHI_COMP_OUT

3

2

1% 1/20W MF 201

255K

B

4 2

R5555 84.5K

1% 1/20W MF 2 201 OUT

CPUHI_IOUT_R

C5529

1

NOSTUFF

R5557 0

5% 1/20W MF 2 0201

PLACE_NEAR=U5000.B1:5MM

OMIT 42

GND_SMC_AVSS

CPUHYS

NOSTUFF

1

36 38

0.22UF


12K

1

U5551

1

20% 2 6.3V X5R 0201

NOSTUFF

1

CPUHI_COMP_VREF CPUHYS

R5529 4.53K2

R5553 CPUHI_COMP_FB CPUHYS

R5556

294K

2

20% 6.3V X5R 0201

CPUHYS

R5554


5% 1/20W MF 2201

LOADISNS

1

LOADRC:YES

1

1

CPUHYS

C5551

10% 6.3V 2 CERM-X5R 0201 BYPASS=U5551:3MM

CPUHYS

36 37 38 40 41 42

Trip Target on CPU High current: 2.5 A Hysteresis Circuit: Vref = 0.737 V Vth = 0.616 V -> 2.054 A on CPU High current Vtl = 0.771 V -> 2.571 A on CPU High current Hysteresis Margin = 0.518 A

R5525

REF 1

0.22UF

LOADRC:YES

1

2

NOSTUFF

C5553

PP3V3_S0 0.1UF

C5520

20% 2 10V CERM 402

Gain: 100x Rsense: 0.003 (R5400)

1

LOADISNS

GND

CRITICAL

OUT

PLACE_NEAR=U5000.H1:5MM

BYPASS=U5520.3:5MM

1

U5520 5 IN-

SC70

20% 2 6.3V X5R 0201


V+

PP3V3_S0

5 IN-

1% 1W MF 77 ISNS_SSD_P 0612-2 2 4

PP3V3_S0SW_SSD_FET

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

0.22UF

NOSTUFF

3

13 30 42 61

0.1uF

U5580 INA214

C5580

20% 10V 2 CERM 402

CPU High Side Current (IC0R) Threshold Alert

R5519

20K

Gain: 500x, EDP: 1.0 A Rsense: 0.005 (R5520) or Rsense SHORT PP3V3_S4SW_SNS 41 40 Vsense: 21.5 mV, Range: 1.32 A 42 65 60 SMC ADC: 14

8



3.3V S0 Rail Current Sense (IR3C)

65 46 39 18

36 37 38 40 41 42

LOADISNS

NOSTUFF

GND_SMC_AVSS

68 47 40 24 11 15 37 43 62



GND_SMC_AVSS

0.1% 1/16W MF 402

BYPASS=U5580.3:5MM

1 3

0.005


5% 1/20W MF 2201

2

CRITICAL

77 50 41 28 12 17 38 44 64

0.22UF



107S0241

LOADRC:YES

R5515

LOADISNS

B

C5549 LOADRC:YES

NOSTUFF

715K 2

36 38

20% 2 6.3V X5R 0201

5% 1/20W MF 2201

GND_SMC_AVSS

1

REF 1

GND

PP1V35_S3

1

OUT

C5510 0.1UF

U5510 5 IN-

1

SMC_CPU_ISENSE

BYPASS=U5510.3:5MM

V+ PLACE_NEAR=U5510.5:10MM

3 77 ISNS_CPUDDR_N

20K

LOADISNS

3

R5510 1

R5540

R5541

LOADISNS


1% 1/20W MF 201

1

2

D

LOADRC:YES

R5549

SC70-5 4.53K2 4 CPUVR_ISUM_IOUT 1

V-

R5543

CPU DDR 1.35V S3 (CPU Only) Current Sense (IM1C)

PP1V35_S3_CPUDDR

3


PP3V3_S0SW_SSD

DDRRC:YES 65 60

65 10 8 73

ISL28133

V+

R5544

R5580

GND_SMC_AVSS

Gain: 200x, EDP: 2.5 A Rsense: 0.005 (R5510) or Rsense SHORT 65 PP3V3_S4SW_SNS 41 40 Vsense: 12.5 mV, Range: 6.6 A 60 42 SMC ADC: 18

1

11.05K2 77 CPUVR_ISNS_R_N 1% 1 1/20W MF 201 715K 0.1% 1/16W LOADISNS MF 2402

Gain: 100x, EDP: 5 A (16.5 W) Rsense: 0.005 (R5580) Vsense: 25 mV, Range: 6.6 A SMC ADC: 13



CPUVR_ISNS_R_P

V+

0.22UF

NOSTUFF

0.1UF

U5540

5 77

CPUVR_ISNS_N

14.42K2 0.1% 1/16W MF 0402

20% 2 6.3V X5R 0201

5% 1/20W MF 2201

GND

CRITICAL

2

1% 1/20W MF 201

20K

PLACE_NEAR=XW7450.1:10MM

C


4.53K

11.05K2 1% 1/20W MF 201

C5540

20% 2 10V CERM 402

SSD Current Sense (ISDC)

DDRRC:YES

R5579 1

77

R5548

CPUVR_ISNS2_N IN PLACE_NEAR=R7320.4:5MM NO_XNET_CONNECTION=TRUE

LOADISNS

C5570 0.1UF

3


77 54

BYPASS=U5540.5:3MM

R5542

14.42K2 77 CPUVR_ISNS_P 0.1% 1/16W MF 0402 14.42K2 0.1% 1/16W MF 0402

LOADISNS 1

LOADISNS CRITICAL

LOADISNS

R5547

CPUVR_ISNS1_N IN PLACE_NEAR=R7310.3:5MM NO_XNET_CONNECTION=TRUE

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

14.42K2 0.1% 1/16W MF 0402

R5546

CPUVR_ISNS2_P IN PLACE_NEAR=R7320.3:5MM NO_XNET_CONNECTION=TRUE

LOADISNS


NOSTUFF

CPUVR_ISNS1_P IN PLACE_NEAR=R7310.4:5MM NO_XNET_CONNECTION=TRUE

LOADISNS

36 38

0.22UF

5% 1/20W MF 2201

GND

R5545

LOADRC:YES

20K

CRITICAL

1

Gain: 219.33x, EDP: 40 A Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375 Vsense: 15 mV, Range: 40.12 A SMC ADC: 06

C5560 0.1uF

3

2

CPU Fixed Current Sense (IC0C) LOADISNS

BYPASS=U5560.3:5MM

U5560

3

1

CPUHYS

R5552 0

C5552 0.1UF

10% 25V 2 X5R 402

SMC_CPUHI_COMP_ALERT_L

U5552

OUT

38

D 3

DMN32D2LFB4 DFN1006H4-3

SYM_VER_2

5% 1/20W MF 2 0201

1 G

S 2

BMON_IOUT_D

36 37 38 40 41 42

NOSTUFF

A

5V S0 Rail Current Sense (IR5C) Gain: 500x, EDP: 1.0 A Rsense: 0.005 (R5530) or Rsense SHORT PP3V3_S4SW_SNS 60 42 41 40 Vsense: 23.5 mV, Range: 1.32 A 65 SMC ADC: 17

LOADISNS

BYPASS=U5530.3:5MM

1

20% 2 10V CERM 402

V+

PP5V_S0 OMIT Short Rsense

65 60

PP5V_S0_FET


R5530 1 0

3 77 ISNS_PP5VS0_N

0 1 W MF 77 ISNS_PP5VS0_P 0612-SHORT 2 4 PLACE_NEAR=U5530.4:10MM

U5530 5 IN4 IN+

CRITICAL

LOADISNS

INA211 SC70

500x

OUT 6 REF 1

ISNS_PP5VS0_IOUT 1

R5535 51K

GND 2

K

C5530 0.1UF

3

60 58 54 32 17 16 53 45 44 68 65 61

A

D5557 SM-201

RB521ZS-30

5% 1/20W MF 2201

LOADISNS


LOADRC:YES

PLACE_NEAR=U5000.G1:5MM

40

IN

CPUHI_IOUT

R5539 4.53K2

1

1% 1/20W MF 201

SMC_PP5VS0_ISENSE 1

SYNC_MASTER=J44 OUT

36 38

C5539 0.22UF

20% 2 6.3V X5R 0201

PLACE_NEAR=U5000.G1:5MM

LOADRC:YES GND_SMC_AVSS

36 37 38 40 41 42

PART NUMBER

QTY

117S0008

2

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

DESCRIPTION

117S0008

3


117S0008

1


REFERENCE DES

C5569,C5519

C5529,C5539,C5549

C5579

CRITICAL

BOM OPTION LOADRC:NO

Power Sensors: Load Side DRAWING NUMBER

LOADRC:NO DDRRC:NO

A


PAGE TITLE

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

55 OF 120

8

7

6

5

4

3

2

1

CPU High Side (IC0R) Peak Detection Support R5660 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

1

47

R5666

2

77

5% 1/20W MF 201

1K

C5660

1% 1/20W MF 2 201

0.1UF

10% 6.3V 2 CERM-X5R 0201 BYPASS=U5660.3:5MM

77

D

IN

77 42 40

1% 1/20W MF 2 201

CKPLUS_WAIVE=NdifPr_badTerm 77 42 40

Thunderbolt TBT Current/Voltage Sense (IHSC/VHSC) Gain: 200x. EDP: 2.8 A XW5640 SM Rsense: 0.005 (R5640) or Rsense SHORT 1 2 ISNS_TBT_IVIN Vsense: 14 mV, Range: 3.3 A PLACE_NEAR=R5640.1:10 MM SMC AD: 23 65 60 42 41 40

R5648 0

1

PP3V3_S4SW_SNS

1

OMIT Short Rsense 68 65 60 38 29 18 37 34 64 63

PP3V3_S4

1 3 77 ISNS_TBT_N

R5640 0

0 1 W 77 ISNS_TBT_P MF 0612-SHORT 2 4 PLACE_NEAR=U5640.4:10MM

ISNS_HS_COMPUTING_N

SC70

CKPLUS_WAIVE=NdifPr_badTerm

INA210 SC70

OUT

6

R5664 15K

2

NOSTUFF

C5640

R5647 1

0

R5649 14.53K2 1% 1/20W MF 201

2

5% 1/20W MF 0201

R5645 20K

2

TBTISNS

SMC_TBT_ISENSE 1

OUT

36 38

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

0.22UF

NOSTUFF

NOSTUFF

36 37 38 40 41 42

R5674

0.1UF

3

ISNS_LCDPANEL_N

5 IN-

ISNS_LCDPANEL_P

4 IN+

INA211 SC70

OUT

6


R5629

4.53K2 ISNS_LCDPANEL_IOUT 1

500x

1% 1/20W MF 201

1

R5625

REF 1

51K

2

LOADISNS

SMC_LCDPANEL_ISENSE 1

OUT

36 38

C5629 0.22UF

20% 2 6.3V X5R 0201

5% 1/20W MF 2 201

GND

CHGR_CSO_R_P/N are swapped on purpose to measure Battery discharge power into system.

LOADRC:YES

20% 2 10V CERM 402

V+

IN

LOADISNS

1% 1/20W MF 2201

41

65 60 42 41 40

1

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.175MM VOLTAGE=3.3V MAKE_BASE=TRUE

V+

77

NC_ISNS_CAMERAN 5 IN-

77

NC_ISNS_CAMERAP 4 IN+

2

A

65 50 43 39 28 15

8

12 18 37 41 46 62 77

65 60 18 15 39 19 68


R5611 1

PP3V3_S0

0

2

SC70

OUT

500x

6

REF 1

GND

PP3V3_S3RS0_CAMERA_R 68 61 44 40 30 17 11 13 24 38 42 47 64

INA211

LOADISNS

2

B

K

INA213 SC70

R5679

OUT 6

4.53K2

1

BMON_IOUT

CRITICAL REF 1 50x

1% 1/20W MF 201

1

R5671 15K


5% 1/20W MF 2201

1

R5615 20K

1

OUT

36 38


0.22UF

68 65 54 10 8

PPVCC_S0_CPU

XW5680 SM 1

2

4.53K2


SMC_CPU_VSENSE

1

1% 1/20W MF 201

1

PLACE_NEAR=U5000.B7:5MM 36 37 38 40 41 42

OUT

36 38

C5689 0.22UF

20% 6.3V 2 X5R 0201


GND_SMC_AVSS

36 37 38 40 41 42

R5612 1

0

2

36 37 38 40 41 42

R5689 CPUVSENSE_IN

PLACE_NEAR=R7310.2:5 MM

LOADRC:YES

GND_SMC_AVSS

20% 2 6.3V X5R 0201

CPU Core Voltage Sense (VC0C) SMC ADC: 20

C5619

20% 6.3V 2 X5R 0201

5% 1/20W MF 2 201

A


CAMERA_3V3:S3

Gain: 1 A / 28.273 mV, Range: 40 A. SMC ADC: 22 CPUVR_IMON 53

PART NUMBER

QTY

DESCRIPTION

117S0008

4

RES,MTL FILM,100K,1/16W,0201,SMD,LF

117S0008

1

FILM,100K,1/16W,0201,SMD,LF

REFERENCE DES C5619,C5629,C5649

C5679

CRITICAL

BOM OPTION

Power Sensors: Extended DRAWING NUMBER

R5699 1

0

5% 1/20W MF 0201

SMC_CPU_IMON_ISENSE OUT

2

With R7210 (Ri) set to 316 Ohm, PLACE_NEAR=U5000.B8:5MM R7310 (Rsen) set to 0.75 mOhm, R7230 set to 95.3 kOhm, Num Phases (N) is 2, and Io (ICCmax) is 40A,

S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

CPU Core IMON Current Sense (IC2C)

5% 1/16W MF-LF 402

36 38

0.22UF

GND_SMC_AVSS

R5619 SM C_ CA ME RA _I SE NS E

OUT

C5679


NOSTUFF

14.53K2 1% 1/20W MF 201

SMC_BMON_DISCRETE_ISENSE BMONRC:YES 1



I SNS _C AME RA _I OU T

S 2

BMONRC:YES

GND

5% 1/16W MF-LF 402

PP3V3_S3

1 G

A

LOADRC:YES

NOSTUFF

CAMERA_3V3:S0

SYM_VER_2

D5677 SM-201

2

BMONISNS

20% 2 10V CERM 402

U5610

PP3V3_S3RS0_CAMERA

5 IN-

CHGR_CSO_R_P

IN

C5610 0.1UF

3

IN

38

DFN1006H4-3

10% 2 25V X5R 402

BMON_IOUT_D

U5670

4 IN+ CHGR_CSO_R_N CKPLUS_WAIVE=NdifPr_badTerm

BYPASS=U5630.3:5MM

PP3V3_S4SW_SNS

PP3V3_S3RS0_CAMERA

SM

0

OUT

D 3

DMN32D2LFB4

0.1UF

5% 1/20W MF 20201

V+

LOADISNS

XW5610

R5672

SMC_BMON_COMP_ALERT_L

U5672

C5672

NOSTUFF

RB521ZS-30 3

PP3V3_S3RS0_CAMERA

1

1

R5677

10% 6.3V CERM-X5R 2 0201

CKPLUS_WAIVE=NdifPr_badTerm

31 15 42

BMONHYS

1

1

BMONHYS

NOSTUFF

NOSTUFF

0.1UF

42 31 15

2

BMON_IOUT_R

5% 1/20W MF 2 0201

C5670

77 52

4

1

BYPASS=U5670:3MM

77 52

5 MCP6541T BMONHYS SC70-5 1 BMON_COMP_OUT

69.8K

BMONISNS

Gain: 500x. EDP: 0.82 A Rsense: 0.005 (R5610) or XW5610 Vsense: 4.1 mV, Range: 1.32 A SMC AD: 15

1% 1/16W MF-LF 402

U5671

3

2

255K 2

R5675

0

36 37 38 40 41 42

10K

1% 1/20W MF 201

BMON_COMP_VREF BMONHYS


Camera (S2 Controller) Current Sense (ICMC)

31 15 42

1

1

1

Trip Target on Battery current: 3.5 A Hysteresis Circuit: Vref = 0.854 V Vth = 0.758 V -> 3.031 A on Battery current Vtl = 0.887 V -> 3.549 A on Battery current Hysteresis Margin = 0.518 A

LOADRC:YES


GND_SMC_AVSS

B

R5676

200K

C

R5673 BMON_COMP_FB BMONHYS

BMONHYS

1% 1/20W MF 2201

BYPASS=U5620.3:5MM

2

20% 6.3V X5R 0201

BYPASS=U5671:3MM

BMONHYS

LOADISNS

U5620

C5671

10% 2 6.3V CERM-X5R 0201


C5620

1

BMONHYS

0.1UF

LCD Panel Current Sense (ILDC) 1

2

5% 1/20W MF 0201

0.22UF

PP3V3_S0

1

Gain: 500x. EDP: 1 A RSENSE: 0.005 (R8320) or Rsense SHORT Vsense: 5 mV, Range: 1.32 A 65 60 42 41 40 PP3V3_S4SW_SNS SMC AD: 21

0

SENSE+ pins of EMC1704 sink 10-20uA current. This deviation has been designed in our Peak Detection circuit. With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV

NOSTUFF

1

GND_SMC_AVSS

IN

0.22UF

TBTRC:YES


D

R5669

C5673

C5649

20% 2 6.3V X5R 0201

5% 1/20W MF 2 201

43 77

NOSTUFF


Gain: 50x. EDP: 8 A Rsense: 0.005 (R7150) Vsense: 50 mV, Range: 13.2 A SMC AD: 05


TBTISNS

OUT

5% 1/20W MF 0201

ISNS_CPUHIGAIN_N

Battery BMON Discrete Current Sense (IP0R) & Threshold Alert

TBTRC:YES


2

5% 1/20W MF 0201

In battery discharge scenario negative voltage will be present on IN+/- pins with INA output voltage decreasing from 3.3V with increasing discharge current.

C5665


1

REF 1

GND

77 62

1

20% 6.3V 2 X5R 0201

5% 1/20W MF 2201

GND

43 77

2

2 ISNS_CPUHIGAIN_OUT_R

5% 1/20W MF 0201

1

TBTISNS

ISNS_TBT_IOUT

200x 4 IN+

77 62

0

ISNS_CPUHIGAIN_OUT 1

ISNS_TBT_IVOUT

0.1UF

U5640 5 IN-

R5665

OUT 6

CRITICAL 4 IN+ 200x REF 1

NOSTUFF

20% 2 10V CERM 402

V+ PLACE_NEAR=U5640.5:10MM

INA210

5 IN-

BYPASS=U5640.3:5MM

3

PP3V3_S4_TBT

24 23 65 25

IN

U5660

ISNS_HS_COMPUTING_P


2

5% 1/20W MF 0201

77 42 40

IN

0

ISNS_HS_COMPUTING_N 1

IN

77 42 40

0

1

OUT

NOSTUFF

R5667

R5668


16K

V+

ISNS_CPUHIGAIN_P


ISNS_CPUHIGAIN_R_N

R5661

3

2

5% 1/20W MF 0201

ISNS_HS_COMPUTING_P 1

1 PLACE_NEAR=R5400:10MM

C


R5662

1

0

1

ISNS_CPUHIGAIN_R_P 1

1

0.22UF

20% 2 6.3V X5R 0201

NOSTUFF

Apple Inc.

36 38

C5699 PLACE_NEAR=U5000.B8:5MM

R

SIZE

D

REVISION


BRANCH


PAGE

56 OF 120

8

7

6

5

4

3

2

1

Thermal Sensor A: Thunderbolt Die, MLB Proximity I2C Write: 0xD8, I2C Read: 0xD9

R5850 PP3V3_S0

1

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

D

77 43 23

BI

47

PP3V3_S0_TBTTHMSNS_R

2


5% 1/16W MF-LF 402 77 43 23

TBTTHMSNS_D1_P

MAKE_BASE=TRUE

C5851

2

77

TBTTHMSNS_D1_N

XW5851 SM

U5850

EMC1412-A

PLACE_NEAR=U2800.AA8:2MM

BI

76 63 39 36

BI

SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL

7 SMDATA 8 SMCLK

R5851 1R5852 15K

1% 1/20W MF 2 201

D

U5850 I2C Address: By setting R5851 to 15k, I2C address for U5850 is 0xD8/0xD9.

1

TBTTHRM_THRM:PU

TQFN

2 DP 3 DN


76 63 39 36

TBTTHRM_SNS

VDD

1

402

1

20% 10V 2 CERM 402

1

0.0022uF 10% 50V 2 TBTTHRM_SNS CERM

C5850 0.1uF

PLACE_NEAR=U5850.2:5MM NO_XNET_CONNECTION=TRUE

Thermal Diode: TBT Die (THSP) Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AA8.

1

TBTTHMSNS_D1_P

100K

1% 1/20W MF 2 201

TBTTHRM_ALRT:PU

THERM*/ADDR

4

TBTTHMSNS_THM_L

OUT

38

ALERT*

6

TBTTHMSNS_ALERT_L

OUT

38

THRM GND PAD

Note: Use GND pin AA8 on U2800 for N leg.

9

5

TBTTHRM_SNS

Thermal Diode: MLB Proximity (TMLB) Placement Note: Place U5850 on the TOP side, on the left portion of the board, 1" to the right of USB connector.

C

C Thermal Sensor B & CPU High Peak Detection: CPU Proximity, Memory Proximity, Airflow, Fin Stack Proximity I2C Write: 0x98, I2C Read: 0x99

R5870 PP3V3_S0

1

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

Thermal Diode: Airflow (TA0P) Placement Note: Place Q5871, Airflow thermal indicator, above the SSD, on the BOTTOM side.

77

Q5872

BC846BLP

DFN1006H4-3 1

B

2

3

Q5871 2

10% 50V CERM 2 402

CRITICAL


CPUTHMSNS_D1_N


Q5873

C5872 1

1

0.0022uF

10% 50V CERM 2 402

BC846BLP

DFN1006H4-3

2

CRITICAL


CPUTHMSNS_D2_N

Thermal Diode: Memory Proximity (TM0P) Placement Note: Place Q5872 between two rows of Memory devices, between channel A and B, on the BOTTOM side.

Thermal Diode: CPU Proximity (TC0P)

20% 10V 2 CERM 402

U5870

R5871 1R5872 100K

1% 1/20W MF 2 201

CPUTHRM_THRM:PU

EMC1704-2 QFN

1

CPUTHRM_ALRT:PU

DP1

3

DN1

4

DP2/DN3

SMDATA 11 SMBUS_SMC_1_S0_SDA

BI

14 32 36 39 68 72 76

5

DN2/DP3

SMCLK 12 SMBUS_SMC_1_S0_SCL

BI

14 32 36 39 68 72 76

16 15

SENSE+ SENSE-

13 14

THERM* 9

100K

1% 1/20W MF 2 201

2

CPUTHMSNS_THM_L

ALERT* 10 CPUTHMSNS_ALERT_L

ADDR_SEL 6 GPIO 7

DUR_SEL TH_SEL GND 8

Placement Note: Place Q5873 under the CPU, on the BOTTOM side.

C5870 0.1uF

CRITICAL

VDD

0.0022uF

BC846BLP

DFN1006H4-3

1

1

C5871 1

1

CPUTHMSNS_D2_P

CRITICAL

77


CPUTHMSNS_D1_P

3

3

PP3V3_S0_CPUTHMSNS_R

2


77

77

47

5% 1/16W MF-LF 402

OUT

38

OUT

38

CPUTHMSNS_ADDR_SEL 1

NC

R5875

B

0

5% 1/20W MF 2 0201

THRM_PAD 7 1

Thermal Sensor: Fin Stack Proximity (Th1H) Placement Note: Place U5870 at corner near Fan, on the TOP side.

77 42

IN

77 42

IN

ISNS_CPUHIGAIN_P ISNS_CPUHIGAIN_N

CPUTHMSNS_DUR_SEL CPUTHMSNS_TH_SEL 1

R5874 10K

A

5% 1/20W MF 2201

NOSTUFF

1

R5873 10K

5% 1/20W MF 2201

NOSTUFF

A


S YNC _D AT E= 08 /1 2/ 20 13

Thermal Sensors DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

58 OF 120

8

D

7

6

5

4

3

2

1

FAN CONNECTOR

D

KEEP THE 5 PIN CONNECTOR FROM D1

PP3V3_S0

62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 46 47 50 61

PP5V_S0

C

16 17 32 41 45 53 54 58 65 68

C

60 61

CRITICAL

R6060

FF14A-5C-R11DL-B-3H

5%

1/20W

MF

R6065 36

OUT

SMC_FAN_0_TACH

1

47K

201

J6050

1

47K 2

NC

FAN_RT_TACH

2

5% 1/20W

MF

201

NC NC

R6061 1 100K 5%

1

1/20W

MF

201

G 2 S

B

A

36

IN

SMC_FAN_0_CTL

2

F-RT-SM 6 1 2 3 4 5

5V DC MOTOR CONTROL GND

TACH

7

518S0769

Q6060

DMN32D2LFB4 DFN1006H4-3

SYM_VER_3 D

FAN_RT_PWM

3

B

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Fan DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

60 OF 120

8

7

6

5

4

3

2

1

LPC+SPI Connector (Matt Card Connector) LPCPLUS CRITICAL

SPI ROM

J6100

Dual-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC.

D

65 61 60 59 14 11 8

DF40C-30DP-0.4V

PP3V3_SUS 52 51 39 38 37 36 34 33 30 17 68 65 61 61 60 58 54 53 44 41 32 17 16 68 65

SPI:DUAL_IO

BYPASS=U6100:3mm 1

R61011 R6103

1

5% 1/20W MF 2012

5% 1/20W MF 2 201

U6100

10% 16V X5R-CERM 2 0201 72 45

72 45

WSON 6

SPI_MLB_CS_L SPIROM_WP_L SPIROM_HOLD_L

1 3 7

SI/SIO0

SCK

R6102

SPIROM_USE_MLB

5

SPI_MLB_MOSI

2

SPI_MLB_MISO

72 68 36 14

BI

72 68 36 14

BI

72 68 36 14

BI

45 72

OMIT_TABLE

CE* WP* RST*/HOLD*

SPI:DUAL_IO IN

72 68 36 14

1

IN BI

64MBIT

SPI_MLB_CLK

SST25VF064C 72 45

72 45

68 45 15 72

72 68 17

VDD

0.1UF

100K

CRITICAL

8

C6100

3.3K

SO/SOI1

72 45

IN

68 16 15

BI

68 18

IN

45 72

68 37 36

OUT

68 37 36

IN

66

VSS THRM_PAD 4 9

0

66

2 5% 1/20W MF 0201 PLACE_NEAR=U6100.7:12MM

NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and Dual-IO modes.

M-ST-SM 31 32

PP3V42_G3H PP5V_S0 LPC_CLK24M_LPCPLUS LPC_AD<0> LPC_AD<2> LPC_AD<1> LPC_AD<3> SPI_ALT_MOSI XDP_LPCPLUS_GPIO LPCPLUS_RESET_L SMC_TDO NC_SMC_TRST_L NC_SMC_MD1 SMC_TX_L

NOTE: Not all ROM APNs currently used support Quad-IO. Also not compatible with Matt card ROM override. Quad-IO support is for experimentation only.

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

33

34

D SPI_ALT_MISO LPC_FRAME_L SPIROM_USE_MLB PM_CLKRUN_L SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TMS

OUT IN BI OUT

45 72 14 36 68 72 15 45 68 72

13 36 68

IN

45 72

IN

45 72

BI

15 36 68

IN

13 36 68

OUT

36 37 68

OUT

36 37 68

OUT

36 37 38 52 68

OUT

37 68

OUT

36 37 68

OUT

36 37 68

516S1039

C

C SPI Bus Series Termination SPI_ALT_MISO

PLACE_NEAR=J6100.2:5MM SPI_ALT_MOSI PLACE_NEAR=J6100.15:5MM SPI_ALT_CLK PLACE_NEAR=J6100.12:5MM SPI_ALT_CS_L PLACE_NEAR=J6100.14:5MM

LPCPLUS

1

R6128 0

5% 1/20W MF 20201

R6110 72 14

IN

SPI_CS0_R_L

1

PLACE_NEAR=U0500.Y7:50MM

B

72 14

IN

SPI_CLK_R

72 14

BI

SPI_MOSI_R (SPI_IO<0>)

1


0

1


BI

SPI_MISO

1


BI

SPI_IO<2>

BI

SPI_IO<3>

SPI_CS0_L

1

72

SPI_CLK

72

SPI_MOSI

1

2

2

1% 1/20W MF 201

R6127 0

5% 1/20W MF 20201

1

R6126 0

5% 1/20W MF 2 0201

45 72

Matt Card ROM Slave

45 72

LPCPLUS

1

R6125 0

5% 1/20W MF 20201

72

SPI_MISO_R

1

2

1% 1/20W MF 201


SPI_MLB_CS_L

OUT

45 72

SPI_MLB_CLK

OUT

45 72

SPI ROM Slave

R6122 33

1% 1/20W MF 201

R6123 33

2


1

5% 1/20W MF 0201

2

33

33

1% 1/20W MF 201

R6121

5% 1/20W MF 0201

(SPI_IO<1>) 72 14

0

0

1

LPCPLUS

45 72

R6120 72

R6112

R6113 72 14

2

2

5% 1/20W MF 0201

CPU Master

0

5% 1/20W MF 0201

R6111

LPCPLUS

45 72

2



SPI_MLB_MOSI

BI

45 72

SPI_MLB_MISO

BI

45 72

B

SPI:QUAD_IO

R6130 1

33

2 PLACE_NEAR=U6100.3:12MM

1% 1/20W MF 201 2 PLACE_NEAR=U6100.7:12MM 1% 1/20W MF 201

SPIROM_WP_L

45 72

SPI:QUAD_IO

R6131

72 14

1

33

SPIROM_HOLD_L

45 72

R6114 72 36

OUT

SPI_SMC_MISO

1

0

5% 1/20W MF 0201 72 36

A

IN

SPI_SMC_MOSI

2

PLACE_NEAR=U5000.M9:12MM

R6115 1

0

5% 1/20W MF 0201

SMC12 Master 72 36

IN

SPI_SMC_CLK

2

PLACE_NEAR=U5000.N9:12MM

R6116 1

0

5% 1/20W MF 0201 72 36

IN

SPI_SMC_CS_L

2

SYNC_MASTER=J44

A


PAGE TITLE

PLACE_NEAR=U5000.L10:12MM

R6117 1

0

5% 1/20W MF 0201

2

LPC+SPI Debug Connector DRAWING NUMBER

Apple Inc.

PLACE_NEAR=U5000.K10:12MM R

SIZE

D

REVISION


BRANCH


PAGE

61 OF 120

8

7

6

5

4

3

2

AUDIO CODEC, ANALOG BLOCKS APPLE P/N 353S4080

1

CRITICAL

L6201

120-OHM-25%-1.3A PP3V3_S0_AUDIO_ANALOG

1

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

PP4V5_AUDIO_ANALOG BYPASS=U6201.H12:L10 :5 mm

D

C6218 1

C6216 1

1

10% 16V X7R-CERM 2 0402

10% 16V X7R-CERM 2 0402

20% 2 16V TANT-POLY 0805-LLP-1

0.1UF

CRITICAL

CRITICAL 1 10UF

15UF 1

20% 4V X5R 0402

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM VREF_DAC H13 VREF_DAC MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM VHP_FILTN A11 VHP_FILT-

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.07MM

CRITICAL

C6222

1

15UF

20% 4V X5R 2 0402

A8 B10 B11

CODEC_FLYN


TP_AUD_CODEC_MICBIAS1_L

CS4208-CRZR

FLYP FLYN FLYN

AUD_HSBIAS_IN AUD_HSBIAS AUD_HSBIAS_REF

2.21K

2

L12 L13 M13 N11

HS3 HS4 HS3_REF HS4_REF HSIN+ HSIN-

SYM 1 OF 2

SENSE_B1 SENSE_B2 SENSE_C SENSE_D

AUD_HP_PORT_L AUD_HP_PORT_R

MIN_NECK_WIDTH=0.07MM MIN_NECK_WIDTH=0.07MM

OUT

50

OUT

50

IN

50

IN

50

IN

50 77

IN

50 77

IN IN

50 77

HS_MIC_P

IN

49 77

MIN_LINE_WIDTH=0.3MM 2 MIN_NECK_WIDTH=0.07MM HS_MIC_N

IN

49 77

AUD_TIPDET_1 AUD_TIPDET_2

C13 AUD_US_HS_GND MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.07MM C12 AUD_CH_HS_GND MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.07MM B13 AUD_HP_PORT_REFUS MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.07MM B12 AUD_HP_PORT_REFCH MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.07MM N6 77 CODEC_HS_MIC_P MIN_LINE_WIDTH=0.3MM M6 77 CODEC_HS_MIC_N MIN_NECK_WIDTH=0.06MM MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM 1UF MIN_NECK_WIDTH=0.06MM MIN_NECK_WIDTH=0.07MM 1 2 10% 25V402 X5R

E11 D11 M3 L3

GND_AUDIO_CODEC

46 50

C6225 10% 25V X5R 402

AUD_TYPEDET NC_AUD_LO1_LP NC_AUD_LO1_LN

2

10% 25V X5R 402

1

C6221 4.7UF

D D D D N N N N G G G G A A A A

20% 2 10V X5R-CERM 0402

B

AUD_HSBIAS_FILT

D D D N N N G G G P P P H H H

D N G S H

50

NC_AUD_LO1_RP NC_AUD_LO1_RN AUD_LO2_L_P AUD_LO2_L_N

OUT

48 77

OUT

48 77

LINEOUT2_R+ G12 LINEOUT2_R- G13

AUD_LO2_R_P AUD_LO2_R_N

OUT

48 77

OUT

48 77

LINEOUT3_L+ H11 LINEOUT3_L- J11

AUD_LO3_L_P AUD_LO3_L_N

OUT

48 77

OUT

48 77

LINEOUT3_R+ J12 LINEOUT3_R- J13

AUD_LO3_R_P AUD_LO3_R_N

OUT

48 77

OUT

48 77

D N G L L P

VCOM M12 VREF_ADC N12

RT. SPKR AMP. SIG. SOURCE LFT SUBWOOFER AMP. SIG. SOURCE RT. SUBWOOFER AMP. SIG. SOURCE

NC_AUD_LO4_RP NC_AUD_LO4_RN CODEC_VCOM CODEC_VREF_ADC CRITICAL 1 C6210

1UF-10OHM

1 6 9 0 0 8 0 3 2 1 L L 1 1 C 1 1 A M L A C D

LFT. SPKR AMP. SIG. SOURCE

NC_AUD_LO4_LP NC_AUD_LO4_LN

LINEOUT4_R+ K13 LINEOUT4_R- L11

1UF

C

OUT

LINEOUT2_L+ F13 LINEOUT2_L- G11

LINEOUT4_L+ K11 LINEOUT4_L- K12

C6220

50 77

1UF

1

LINEOUT1_R+ F11 LINEOUT1_R- F12

HSBIAS_IN HSBIAS HSBIAS_REF HSBIAS_FILT

46 50

C6224

LINEOUT1_L+ E12 LINEOUT1_L- E13

1% 1/20W MF 201

1

MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM

SENSE_A1 C11 SENSE_A2 D12

VFBGA

ANALOG

N4 MICIN2_R+ M4 MICIN2_R-

CODEC_MICIN2

BYPASS=U6201.A1:A2:5 MM

GND_AUDIO_CODEC HPOUT_L A12 HPOUT_R A13

U6201

N5 MICIN2_L+ M5 MICIN2_L-

0.1UF

1

46 50

0.1UF

N7 MICIN1_R+ M7 MICIN1_R-

C6226

R6206

D 46 50

10% 16V X7R-CERM 2 0402

N8 MICIN1_L+ M8 MICIN1_L-

GND_AUDIO_CODEC

50 46

C6213

20% 2 10V X5R-CERM 0402-1

GND_AUDIO_CODEC

C6212 1

L5 MICBIAS2_L L4 MICBIAS2_R

TP_AUD_CODEC_MICBIAS2_R

10% 16V X5R-CERM 0201 2 GND_AUDIO_CODEC 1

GND_AUDIO_CODEC

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

CRITICAL 10UF

10% 16V X7R-CERM 2 0402

10UF

L L P _ A V

L8 MICBIAS1_L L7 MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

50 46

A V

N9 LINEIN_R+ M9 LINEIN_R-

TP_AUD_CODEC_MICBIAS1_R

C

P H _ A V

N10 LINEIN_L+ M10 LINEIN_L-

GND_AUDIO_CODEC

50 46

F E R _ A V

BYPASS=U6201.H12:H13 :5 mm

CODEC_FLYP

BYPASS=U6201.A8:B10:5 mm

1

0.1UF

C6217

2 3 1 9 1 1 H A N A

20% 16V TANT-POLY 2 0805-LLP-1

2

C6214

1

BYPASS=U6201.N13:M11:5 mm

C6215

C6219 GND_AUDIO_CODEC

50 46

0.1UF

PP3V3_S0

2 0402

46

20% 25V TANT 2 0603-LLP

CRITICAL 1

B

C6211 10UF

20% 2 16V TANT-POLY 0805-LLP-1

GND_AUDIO_CODEC

46 50

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456

PLACE XW6201 NEAR 5V SOURCE

L6200

XW6201 SM 62 60 57 56 55 33 32 68 66 65 63

1

PP5V_S4

R6200 PP3V3_S0

77 68 65 64 62 61 50 47 30 28 24 18 17 15 13 12 11 8 46 44 43 42 41 40 39 38 37

A

1

2.2K 2

5% NO STUFF 1/20W

PM_SLP_S3_BUF_L 61 27 26

MF 201

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.15MM FERR-22-OHM-1A-0.065-OHM VOLTAGE=5V

2 PP5V_S4_AUDIO_XW MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

1

2

SON

OUT

2

22K

5% 1/16W MF-LF 402

1

1

PP4V5_AUDIO_ANALOG

46

CRITICAL 4 EN

4V5_REG_EN

NR/FB 3

1

C6200 0.1UF

20% 10V 2 X7R-CERM 0402

4V5_NR

NC 5

GND

R6207


U6200

TPS71745

6 IN

4V5_REG_IN

0201

CRITICAL

2 1

C6201 1UF

10% 2 10V X5R 402

XW6200 SM 1

2

C6202 1 0.01UF

10% 25V X5R-CERM 2 0201

CRITICAL 1

C6203

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

A


1.0UF

20% 2 10V X5R-CERM 0201-1

S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

AUDIO:CODEC, ANALOG DRAWING NUMBER

GND_AUDIO_CODEC

Apple Inc.

46 50

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.15MM VOLTAGE=0V

R

SIZE

D

REVISION


BRANCH


PAGE

62 OF 120

8

7

6

5

1

PP1V5_S0

PP1V5_S0_AUDIO_DIG

PP3V3_S0

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.07MM VOLTAGE=1.5V

C6300 1

1

20% 4V X5R-1 402

10% 16V 2 X7R-CERM 0402

4.7UF

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

2

BYPASS=U6201.E1:F1:5

C6301

1

0.1UF

C6302

mm

BYPASS=U6201.G1:F1:5

0.1UF

BYPASS=U6201.J2:J1:5

1

10% 2 16V X7R-CERM 0402

mm

mm BYPASS=U6201.K1:K3:5

C6303 C6304 1

0.1UF

0.1UF

100K

NOSTUFF

R6322 1

100K 2

OUT IN

68 50

IN

49

72 12

C

100K

OUT

H3 H2 H1 C4 C5 C7

GPIO0_SPKR_SHUTDOWN PD_CS4208_GPIO1 SPKRCONN_L_ID SPKRCONN_R_ID DFET_OPENUS DFET_OPENCH

72 68 12

IN IN

HDA_BIT_CLK HDA_SYNC

OUT

HDA_SDIN0

72 47 12

IN

72 12

IN

HDA_SDOUT HDA_RST_L

D V

5% 1/20W MF 201

NC_CS4208_GPO0 NC_CS4208_GPO1 72 12

OUT

R6325

2 48

5% 1/20W MF 201

49

20% 10V 2 X5R-CERM 0402-1

OMIT 2 1 J E

1

R6331 1

22

5% 1/20W MF 201

2

72

CS4208_HDA_SDOUT0_R TP_CS4208_HDA_SDOUT1

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5

D H _ L V

C63061

F I _ L V

U6201 VFBGA

DIGITAL SYM 2 OF 2

C9 GPO0 B9 GPO1 F2 E2 D1 C1 D2 C2 C3 B1 D3 A5 B2 B4 A3 B3

MCLK_A SCLK_A LRCK_A SDOUT_A SDIN_A

NC_CS4208_MCLKB NC_CS4208_SCLKB NC_CS4208_LRCLKB NC_CS4208_SDOUTB

A6 B6 B5 B8 A4

MCLK_B SCLK_B LRCK_B SDOUT_B SDIN_B

1

C6307 0.1UF

10% 6.3V 2 CERM-X5R 0201

SPDIF_IN G3 SPDIF_OUT G2

R6330

CS4208_SPDIF_IN CS4208_SPDIF_OUT

1

33

2

SPDIF_OUT_JACK

OUT

50

5% 1/16W MF-LF 402

DMIC_SDA0 N3 DMIC_SCL0 N2 DMIC_SDA1 N1 DMIC_SCL1 M1

NC_DMIC_CLK0

DMIC_SDA2 M2 DMIC_SCL2 L1

BCLK SYNC SDI0 SDI1 SDO0 SDO1 SDO2 SDO3 RST*

NC_CS4208_MCLKA NC_CS4208_SCLKA NC_CS4208_LRCLKA NC_CS4208_SDOUTA

D

BYPASS=U6201.A7:E3:5 mm

1SHORT2 402

M D _ L V

CS4208-CRZR

20% 10V 2 X5R-CERM 0402-1

R6302

7 1 1 A G K P S _ L V

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

10UF

10UF

R6324

68 50

PP3V3_S0

1

PP3V3_S0

5% 1/20W MF 2 201

1 100K 2 5% 1/20W MF 201

1

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

mm

C6305

10% 10% 6.3V 2 6.3V CERM-X5R 2 CERM-X5R 0201 0201

1

R6323

2

APPLE P/N 353S4080

2 0201

D

3

AUDIO CODEC, DIGITAL BLOCKS

L6300

FERR-22-OHM-1A-0.065-OHM 65 63 61 60 59 8 68

4

DMIC_SDA3 K2 DMIC_SCL3 L2 NC NC NC NC NC NC NC NC NC

DMIC_CLK3_R

NC_DMIC_CLK1

F6 F7 F8 G6 G7 G8 H6 H7 H8

C

NC_DMIC_CLK2

R6332 1

75

2

DMIC_SDA3

IN

DMIC_CLK3

OUT

47 50 68

50 68

1% 1/16W MF-LF 402

C6 SDA B7 SCL D N G D

D D D D D N N N N N G G G G G L L L L L

PP6301 P3MM 68 50 47

DMIC_SDA3

1

SM

PP PLACE_NEAR=U6201.N3:5 mm

1 1 3 3 3 3 J F E F J K

B

B PP6304 P3MM 72 47 12

HDA_SDOUT

1

SM PP

PLACE_NEAR=U6201.D2:5 mm

A

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

AUDIO:CODEC, DIGITAL DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

63 OF 120

8

7

6

5

4

3 66 48

2

1

PP5V_S0_AUDIO_AMP_L CRITICAL

CRITICAL

CRITICAL

FERR-1000-OHM

C6413

L6410

77 46

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

77

0402

1

1 1 A

10% 50V X7R-CERM 0402 0.01UF 1 2 AUD_SPKRAMP_LIN 1_N 2 77 IN AUD_LO2_L_N NO_TEST=TRUE 0402 10% CRITICAL 50V 77 X7R-CERM 0402 48

BYPASS=U6410.A1:A2:5 mm

47UF

2

CRITICAL

L6411

77 46

C6412 1

0.01UF

2 AUD_SPKRAMP_LIN_P NO_TEST=TRUE

U6410 WLP

A3 IN+ SPKRAMP_LIN_P SPKRAMP_LIN_NB3 IN-

L6401

SPKRCONN_L_OUT_P

GAIN C3

R64001

SPKR_L_GAIN

SPKRCONN_L_OUT_N OUT 50 68 77

MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

R64101

100K

0402

100K

PGND

5% 1/16W MF-LF 4022

CRITICAL

D

50 68 77

OUT- C1

B2 NC

FERR-1000-OHM GPIO0_SPKR_SHUTDOWN 1 2

OUT


OUT+ B1

NO_TEST=TRUE

C2 SHDN*

IN

0.1UF

MAX98300

NO_TEST=TRUE

77

SPKR_SHUTDOWN

47

C6411

10% 2 16V X5R-CERM 0201

CRITICAL

PVDD

C6414

FERR-1000-OHM

APN: 353S2888 & 353S 2958 GAIN = +3 DB 1ST ORDER FC (L&R) = NOM 569 HZ 1ST ORDER FC (SUB) = NOM 9 HZ

D

1 IN AUD_LO2_L_P

20% 6.3V 2 TANT-POLY CASE-A4

5% 1/16W MF-LF 4022

2 A

PP5V_S0_AUDIO_AMP_R CRITICAL CRITICAL C6422 1 C6423 47UF 20% 0.01UF 6.3V 2 2 AUD_SPKRAMP_RIN 1 _P2 TANT-POLY CASE-A4 66 48

CRITICAL

L6420

BYPASS=U6420.A1:A2:5 mm

1

FERR-1000-OHM AUD_LO2_R_1 P

IN

77 46

77

0402

C6424X7R-CERM 0402

FERR-1000-OHM 77 46

1N AUD_LO2_R_

0.01UF

2 AUD_SPKRAMP_RIN 1 _N 2 NO_TEST=TRUE 0402 10% CRITICAL 50V X7R-CERM48 0402

IN

77

SPKRCONN_R_OUT_P

WLP

SPKR_SHUTDOWN

C2 SHDN*

GAIN C3

50 68 77

SPKRCONN_R_OUT_N MIN_LINE_WIDTH=0.40 MM OUT MIN_NECK_WIDTH=0.10 MM

OUT+ B1 OUT- C1

NO_TEST=TRUE

OUT


MAX98300 NO_TEST=TRUE

A3 IN+ SPKRAMP_RIN_P SPKRAMP_RIN_N B3 IN77

77

10% 16V 2 X5R-CERM 0201

U6420

10% CRITICAL 50V

C6421 0.1UF

CRITICAL

PVDD

NO_TEST=TRUE

L6421

C

1 A

C

50 68 77

SPKR_R_GAIN

B2 NC

R64201 66 48

PGND

PP5V_S0_AUDIO_AMP_R

2 A

CRITICAL

77 46

IN

NO_TEST=TRUE

0402

CRITICAL

IN

AUD_LO3_R_N

1

10% 16V CERM 402

0402

2

C6431

VDD

10% 2 16V X5R-CERM 0201

CRITICAL

WLCSP

SPKR_SHUTDOWN

A2 SD*

RSUB_GAIN

EDGE B2

1

50 68 77

SPKRCONN_SR_OUT_N

OUT

50 68 77


C6436 4700PF

GND

10% 16V CERM 402

OUT

OUT+ C3 OUT- B3 GAIN A3

RSUBIN_N

SPKRCONN_SR_OUT_P MIN_LINE_WIDTH=0.40 MM MIN_NECK_WIDTH=0.10 MM

U6430

SSM2375

48

0.22UF

5% 1/16W MF-LF 4022

0.1UF

2 C

B1 IN+ A1 IN-

NO_TEST=TRUE

C6434

2 AUD_SPKRAMP_RSUBIN_N 1 NO_TEST=TRUE

77

1

100UF

20% 6.3V 2 TANT CASE-AL1

NO_TEST=TRUE

CRITICAL

L6431

FERR-1000-OHM 77 46

C6432 1

CRITICAL CRITICAL L6430 C6433 FERR-1000-OHM 0.22UF 2 AUD_SPKRAMP_RSUBIN_P 1 2 RSUBIN_P AUD_LO3_R_P 1 77

100K

BYPASS=U6430.C2:C1:5 mm

10% 50V 2 X7R-CERM 0402

1 C

B

B 66 48

PP5V_S0_AUDIO_AMP_L BYPASS=U6440.C2:C1:5 mm

CRITICAL

L6440

77 46

IN

FERR-1000-OHM 2 AUD_SPKRAMP_LSUBIN_P AUD_LO3_L_P 1 77

A

77

2

LSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_N

NO_TEST=TRUE

10% 16V CERM 402

10% 16V 2 X5R-CERM 0201

CRITICAL

VDD

U6440

B1 IN+ A1 IN-

0.22UF

2 LSUBIN_N NO_TEST=TRUE

2 C

SPKRCONN_SL_OUT_P

OUT

50 68 77


SSM2375

C6444 1

C6441 0.1UF

20% 6.3V TANT 2 CASE-AL1

CRITICAL

FERR-1000-OHM AUD_LO3_L_N 1 2 0402

1

1

100UF

0.22UF 10% 16V CERM 402

L6441

IN

C6442 1

C6443

NO_TEST=TRUE

0402

CRITICAL

77 46

CRITICAL

CRITICAL

48

WLCSP

SPKR_SHUTDOWN A2 SD*

OUT+ C3 OUT- B3 GAIN A3 EDGE B2

GND 1 C

LSUB_GAIN 1

C6446

SPKRCONN_SL_OUT_N

MIN_LINE_WIDTH=0.40 MM OUT MIN_NECK_WIDTH=0.10 MM

50 68 77

4700PF

10% 50V 2 X7R-CERM 0402

A

SYNC_MASTER=J44


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AUDIO: SPEAKER AMP DRAWING NUMBER

Apple Inc. R

SIZE

D

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PAGE

64 OF 120

8

7

6

5

4

3

2

1

D

D 77 46

OUT

R6550

HS_MIC_P

1

R65561

1

100K

HS_MIC_N 77 46

2.2K

2

MIN_NECK_WIDTH=0.06MM MIN_LINE_WIDTH=0.2MM

AUD_HS_MIC_P

5% 1/16W MF-LF 402

CRITICAL

C6550

1

3300PF

5% 1/20W MF 2012

IN

50 77

CRITICAL

C6558 27PF

10% 10V 2 X7R-CERM 0201

5% 25V 2 NP0-C0G 0201

R6559 1 2.2K 2 5% 1/16W MF-LF 402

OUT

IN

AUD_HS_MIC_N

50 77


R/C6550 FILTER TO ADDRESS OUT-OF-BAND NOISE ISSUE SEEN ON EARLY HEADSETS (SEE RADAR # 6210118)

C

47

IN

BYPASS=U6500.B2:3MM

DFET_OPENCH

C

BYPASS=U6500.B2:3MM

1

C6560 1.0UF

1

R6520 10K

10% 2 35V CERM-X5R 0402

5% 1/16W MF-LF 2 402

1

C6562 0.1UF

10% 2 16V X5R-CERM 0201

1

C6563 0.01UF

10% 2 10V X5R-CERM 0201

2 B

VDD

U6500

DFET_CPO1

1

C6501 1000PF

5% 2 25V NP0-C0G 0402

47

IN

TAIC3027A0YFFR WCSP C2 PSEL OUT1 A1 AUD_CONN_SLEEVE_XW OUT2 A2 AUD_CONN_SLEEVE_XW C1 CP

OUT

49 50 77

OUT

49 50 77

GND 1 B

BYPASS=U6501.B2:3MM

DFET_OPENUS

BYPASS=U6501.B2:3MM

1

B

1

R6521 10K

5% 1/16W MF-LF 2 402

C6530 1.0UF

10% 35V 2 CERM-X5R 0402

1

C6542 0.1UF

10% 2 16V X5R-CERM 0201

1

C6543

B

0.01UF

10% 10V 2 X5R-CERM 0201

2 B

VDD

U6501

DFET_CPO2 1

C6502 1000PF

5% 2 25V NP0-C0G 0402

A

TAIC3027A0YFFR WCSP C2 PSEL OUT1 A1 OUT2 A2 C1 CP

AUD_CONN_RING2_XW AUD_CONN_RING2_XW

OUT

49 50 77

OUT

49 50 77

GND 1 B

A



AUDIO: JACK DRAWING NUMBER

Apple Inc. R

SIZE

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8

7

6

5

4

3

2

CODEC OUTPUT SIGNAL PATHS FUNCTION HP/HS OUT TWEETERS SUB SPDIF OUT

V OL UM E 0X02 (2) 0X03 (3) 0X04 (4) N/A

SPEAKER CONNECTOR

C ON VE RT ER 0X02 (2) 0X03 (3) 0X04 (4) 0X0E (14)

PIN COMPLEX 0X10 (16) 0X12 (18) 0X13 (19) 0X21 (33)

MUTE CONTROL N/A CODEC GPIO0 CODEC GPIO0 N/A

D

C O NV E RT ER 0X09 (9) 0X09 (9)

HEADSET MIC

P I N C O MP LE X 0X1C (28) 0X1C (28)

0X07 (7)

PP3V3_S0

68 47

OUT

J6601

FF14A-6C-R11DL-B-3H

DMIC_SDA3

2.7V

F-RT-SM 7

OMIT

R6680 GPIO2 INPUT GPIO3 INPUT GPIO4 OUTPUT

SHORT

1

68 47

1

IN

M-RT-SM 7

77 68 48

IN

68 47

IN

77 68 48

IN

77 68 48

IN

SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_L_ID

1 2 3 4 5 6

68

OUT

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

1 2 3 4 5 6

DMIC_SDA2

DMIC_CLK3

CRITICAL

J6603

78171-6006 M-RT-SM 7

77 68 48

IN

77 68 48

IN

68 47

IN

77 68 48

IN

77 68 48

IN

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_R_ID

1 2 3 4 5 6

PLACE_NEAR=J6600.5:5mm

XW6600 SM

AUD_CONN_SLEEVE

77

2

1


0402

D

8

8

L6611

120-OHM-25%-1.3A AUD_HP_PORT_REFCH

OUT

2

402

HIGH = FG, LOW = MERRY HIGH = FG, LOW = MERRY HIGH = DFETs OPEN

CRITICAL

77 46

77 68 48

CRITICAL

OTHER CODEC GPIO LINES LEFT SPEAKER ID RIGHT SPEAKER ID DFET CONTROL

78171-6006

APN: 518S0672

APN: 518S0818

VREF 3.3V 3.3V

0X18 (24)

CRITICAL

J6602

HP=80HZ

2-MIC CONNECTOR

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

CODEC INPUT SIGNAL PATHS FUNCTION DMIC 1 DMIC 2

1

2

SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N

8

CRITICAL

L6612

120-OHM-25%-1.3A OUT

77 46

C

77 49

OUT

AUD_CH_HS_GND

1

AUD_CONN_SLEEVE_XW

2

77 49

0402


XW6601 SM

AUD_HS_MIC_P

1

C

2

CRITICAL

L6613

PLACE_NEAR=J6600.6:5mm

XW6602 SM

120-OHM-25%-1.3A 77 46

OUT

1

AUD_CONN_RING2

77

2

1


0402

AUD_HP_PORT_REFUS

2

CRITICAL

L6614

120-OHM-25%-1.3A 77 46

OUT

AUD_US_HS_GND

1

AUD_CONN_RING2_XW

2

77 49

0402

77 49

OUT


XW6603 SM

AUD_HS_MIC_N

1

APN: 514-0875

2

J6600

CRITICAL

AUDIO-SPDIF-J44

L6604

120-OHM-25%-1.3A

AUD_HP_PORT_L 46

1

IN

L6608

2.2K

5% 1/16W MF-LF 402 2

46

OUT

FERR-470-OHM AUD_TIPDET_21 2 0201

GND_AUDIO_CODEC

2.2K

46

5% 1/16W MF-LF 402 2

46

NC CRITICAL

AUD_CONN_TIPDET_2

L6607

FERR-470-OHM

R66031

B

2 AUD_CONN_HP_LEFT MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.06MM

0402

CRITICAL

R66021

OUT

AUD_TIPDET_1

1

CRITICAL

L6605

2

AUDIO

AUD_CONN_TIPDET_1

9 10 11

0201

120-OHM-25%-1.3A 1 2 AUD_CONN_HP_RIGHT

IN

0402

AUD_HP_PORT_R


CRITICAL

C6600 1

L6606

46

47

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

IN

OUT

AUD_TYPEDET

1UF

FERR-470-OHM 1 2 AUD_CONN_TYPEDET

10% 10V 2 X5R 402-1

0201

C6601

1

0.1UF

10% 6.3V 2 CERM-X5R 0201

B

VIN VDD GND

OPERATING VOLTAGE 3.3 POF 12 13 14 15

SHELL PINS

SPDIF_OUT_JACK

PP3V3_S0

1

2 CRITICAL

R6601

5% 1/16W MF-LF 2 402

1

C6602 1 100PF

5% 25V NP0-CERM 2 0201

SOD882

CRITICAL 2

DZ6601 ESDALC5-1BM2 SOD882

C6605 1

C6604 1

5% 25V NP0-CERM 2 0201

2 CRITICAL

100PF

1

5% 25V NP0-CERM 2 0201

2 CRITICAL

DZ6602 1

ESDALC5-1BM2 SOD882

2 CRITICAL

DZ6603

100PF

5% 2 25V NP0-CERM 0201

ESDALC5-1BM2

10K

C6603 100PF

DZ6607

1

A

F-RT-TH 5 MIC 6 AUDIO GND 2 2RTN 1 DET2 8 DET1 7 1RTN 3 R.AUDIO 4 AUDIO GND

1

ESDALC5-1BM2 SOD882

C6606 1 100PF

5% 25V NP0-CERM 2 0201

1

1

5% 2 25V NP0-CERM 0201

SOD882

CRITICAL 2

SOD882

C6608 1

2 CRITICAL

DZ6604

100PF

DZ6605 ESDALC5-1BM2

C6607 100PF

DZ6606 ESDALC5-1BM2

1

5% 25V NP0-CERM 2 0201

ESDALC5-1BM2 1

SOD882

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

AUDIO: JACK TRANSLATORS DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


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PAGE

66 OF 120

8

7

6

5

4

3

2

1

MagSafe DC Power Jack CRITICAL F7005

6AMP-32V-0.0095OHM 1

PPDCIN_G3H

2

52 65 68

0603

PP3V42_G3H 1 68

CRITICAL

D

J7000

PP18V5_DCIN_FUSE 1

WTB-PWR-M82 M-RT-SM 1 2 3 4 5 6

0.1UF

U7001

NO STUFF

TC7SZ08FEAPE 5

C7005

SOT665 4

0.1UF

10% 50V 2 X7R 603-1

D


A

Y

2

SMC_BC_ACOK

IN

36 37 52

1

B

3

TP_TDM_ONEWIRE_MPM

SMC_BC_ACOK_VCC

65 52 40

C7000 1 20% 10V CERM 2 402

1

SBR0330CW

5% 1/16W MF-LF 2402

U7000 SC70-5

D7020

2.0K

VCC

5 EXT

ADAPTER_SENSE

BLEEDER CRITICAL

R7029

MAX9940 68

PPDCIN_G3H_ISOL

1

0.1UF

518S0508

17 30 33 34 36 37 3 8 39 45 51 52 61 65 68

C7008

20% 10V 2 CERM 402

CRITICAL


INT 4

SOT-323 1

3

SYS_ONEWIRE

BI

36

DCIN_ISOL_BLEEDER_PSRC MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.20MM 1

2

CRITICAL

C7020 0.1UF

10% BLEEDER 50V 2 X7R 603-1

NC GND

1-Wire OverVoltage Protection The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is connected.

3

BLEEDER

2

1

R7012

R7030 1K

NC

5% 1/16W MF-LF 2 402

S

1

G

BLEEDER

SI5419DU

Q7020

POWERPAK

AO3407A


Q7030

D

SOT23-HF1

S

5A

SOT23

BLEEDER

3

C

Q7010

2

DCIN_ISOL_BLEEDER_R

1

D

G

2

1

1

R7010

D

3

2N7002

S

5

C7012 1 4 0.047UF

DCIN_ISOL_BLEEDER_NGATE 1

BLEEDER

R7021 10K

DCIN_ISOL_GATE_R

When input voltage is 2V the FET will be off blocking the leakage path and 22.1K can be properly detected.

100K

5% 1/20W MF 2201

G


Input impedance of 68K meets sparkitecture requirements for both MPM4 and MPM5.

68K

1% 1/20W MF 2 201

1

10% 25V 2 X5R 0402

1

10K

2

1% 1/20W MF 201

5% 1/16W MF-LF 2 402

C

When input voltage is at 16V+, FET will conduct and power charger and 3.42V reg

R7011

DCIN_ISOL_GATE K

D7010

GDZT2R6.8

6.8V Zener

GDZ-0201

A

R7020 47

1

CRITICAL PP18V5_DCIN_CONN_R D7005 MIN_LINE_WIDTH=0.6 mm SBR0330CW

2

1% 1/3W MF 805

MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

SOT-323 1

3

R7005 68 65 58 52 40 25

10

PPBUS_G3H 1

2

5% 1/8W MF-LF 805

B

PPBUS_G3H_R


2

3.425V "G3Hot" Supply

PPVIN_G3H_P3V42G3H

P3V42G3H_BOOST

4.7UF

10% 25V X6S-CERM 2 0603

4.7UF

SW 4 BIAS 2

7 NC CRITICAL

1

R7080

10 11 12 13 14 15 16 17 18

GND

0

5% 1/20W MF 20201

PPVBAT_G3H_CONN

52 68

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L CRITICAL

D7050

C7060 1

10% 25V 2 X5R 402

10% 25V 2 X5R 603-1

1UF

BI

36 39 52 68 76

BI

36 39 52 68 76 68

1

1

C7050 1 0.1UF

A

DFN

8 SHDN*

NC

2

RCLAMP2402B

R7050 10K

5% 1/16W MF-LF 2402

SC-75

3

5

R7081 49.9K

1% 1/20W MF 2201

0.22UF

CRITICAL 10% 10V CERM 2 40210UH-20%-0.85A-0.46OHM 1 2 P3V42G3H_SW MIN_LINE_WIDTH=0.5 mm Vout 2520 MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

(Switcher limit)

1

9

1

C7095 R7095 348K 22PF

5% 2 50V NP0-C0G-CERM 0201

1% 1/20W MF 2012

CRITICAL 1

C7099 22UF

P3V42G3H_FB

NO STUFF

C7080

= 3.425V

300MA MAX OUTPUT

FB 1 THRM PAD

P3V42G3H_SHDN_L NO STUFF 1

C7094 1 L7095

LT3470AED

CRITICAL

NC NC

BOOST

U7090

10% 25V X6S-CERM 2 0603

518-0394

PWR PWR PWR SMBUSSCL SMBUSSDA SYSDETL GND GND GND

SWITCH_NODE=TRUE

3

VIN

J7050 1 2 3 4 5 6 7 8 9

B

DIDT=TRUE

10% 25V X6S-CERM 2 0603

F-ST-TH

65 68 17 30 33 34 36 37 38 39 45 51 52 61

NO_TEST=TRUE

6

C7092 1 C7091 1 C7090 1 4.7UF

BAT-J44

PP3V42_G3H

Supply needs to guarantee 3.31V delivered to SMC VRef generator


1

1

R7096

1000PF

20% 2 6.3V X5R 0603

200K

5% 25V CERM 2 0402

1% 1/20W MF 2012

Vout = 1.25V * (1 + Ra / Rb)

A

SYNC_MASTER=J44


PAGE TITLE

DC-In & Battery Connectors DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


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70 OF 120

8

7

6

5

4

3

2

1

Reverse-Current Protection

NOSTUFF

R7192

Inrush Limiter

52

CHGR_DCIN_D_R

0

1

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

FROM ADAPTER

9

4

1

C7185

1

2

S

D

D

NOSTUFF

1/16W MF-LF 402

G

3

1/16W MF-LF

6

D7105

2

CHGR_DCIN_D_R

20

1

(CHGR_DCIN)

2

1

5%

2

4.7

52

R7112 1%

1/16W MF-LF 402

1

R7110 68.1K

SMC_RESET_L

IN

0

1

2

5%

51 39 36

1/16W 76 68 MF-LF 51 39 36 76 68 402

1/16W MF-LF 402

61

IN BI IN

1%

1/16W MF-LF 402

1

R7115

77

100K

77

CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N

1/16W MF-LF 402

1

CHGR_LGATE

16

CHGR_BGATE CHGR_AMON CHGR_BMON SMC_BC_ACOK

CHGR_VCOMP_R 2 1

C7115

10% 16V X5R 402

D ) A D P N _ G M A R ( H T

BGATE 20V/V AMON 36V/V BMON (OD) ACOK

52

26 1 28

77

27

77

24

2 2

R7125 1

CHGR_SGATE CHGR_AGATE CHGR_CSI_P CHGR_CSI_N CHGR_BOOT CHGR_UGATE

25

77

CHGR_CSI_R_N 4

RL1632W

2

2

PPDCIN_G3H_CHGR MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

1

22UF

1

1

C7136

1

1.0UF

10% 50V X5R 0603

2

1

2

10% 10V CERM 402

Q7130 PLACE_NEAR=U7100.23:2MM


RJK03P0DPA

CRITICAL

WPAK

1

SWITCH_NODE=TRUE DIDT=TRUE

CRITICAL

2

CHGR_PHASE

7

1

SWITCH_NODE=TRUE

9 15 14


GATE_NODE=TRUE DIDT=TRUE

OUT

40

OUT

40

OUT

36 37 51

TO SYSTEM

CRITICAL

L7130

F7140

4.7UH-20%-8.5A-18.3MOHM

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

12AMP-32V

2

1

1/16W MF-LF 402

3

4

PPVBAT_G3H_CHGR_REG

5


CRITICAL 1

1

C7140

C7145

0.001UF

68UF 20%

2 16V

2

POLY-TANT CASE-D2E-SM

10% 50V X7R-CERM 0402

CRITICAL

Q7155

(GND)


C7116 470PF 10% 50V CERM 0402

(CHGR_CSO_P)

R7151

2.2

1

2

77 42

(CHGR_CSO_N)

R7152

0

1

2

77 42

(PPVBAT_G3H_CHGR_R)

5% 5%

TO/FROM BATTERY

SO-8 SYM-VER-2

2

1

4

3

PPVBAT_G3H_CHGR_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V

3

S D

2

C7155 1

C7156 1

C7157 1

10% 25V X5R 2 402

10% 25V X5R 2 402

10% 50V X7R-CERM 2 0402

1UF

2

B

SI7137DP

1% 1W MF

0612-2

2

25 40 51 58 65 68

1206

6

SM

1

PPBUS_G3H

2

PIME103T-4R7MS

DIDT=TRUE

XW7100

CHGR_VNEG_R

C

Max Current = 8.5A (L7130 limit) f = 400 kHz

C7125 0.22UF

2

0.005

3.01K

20% 50V CERM 0402

2

R7150

R7116 1

C7137

0.001UF

10% 50V X5R 0603

PLACE_NEAR=C7136.1:3mm


1%

2

2

POLY-TANT CASE-D2-SM

CRITICAL

1%

1

2 25V


C7135 1.0UF

20%

2 25V

PLACE_NEAR=Q7130.2:1MM

50V COG 402

1K 2

1

C7132 22UF

20%


R7142 1/16W MF-LF 402

CRITICAL 1

C7131 22UF

20%

5%

B

CRITICAL 1

C7130

2 25V

353S2929

330PF

2

CRITICAL

10% 25V X5R 402

2

0

5%

1/16W MF-LF 402

23

D N G P

9 2

0.5%

1W MF

SWITCH_NODE=TRUE

21

17

R7120

CHGR_BOOT_R

8

1UF

2

0.02


CHGR_DCIN

18

C7150

10

3 1

CHGR_CSI_R_P

0.1UF

10% 25V X5R 2 402

VDDP 2

1%

2

MF

201

CRITICAL 77

C7121

1

0.1UF

2

VHST CRITICAL DCIN SMB_RST_N SGATE 11 SCL U7100 AGATE 10 SDA TQFN CSIP 9 4 VFRQ 5 2 CSIN 6 CELL 6 L S BOOT 3 ACIN I UGATE 5 ICOMP PHASE 7 VCOMP LGATE VNEG CSOP CSON

Vout = 5.50V 250MA MAX OUTPUT (Switcher limit)

DIDT=TRUE

13

CHGR_ACIN

R7111

C7122 1

0 2

VDD

2

1%


12

21.5K

2

9 1

1/16W MF-LF 402

CHGR_RST_L SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA CHGR_VFRQ CHGR_CELL

2

Float CELL for 1S 1

R7102

R7100 68 38 36 37 45

1%

2

52

GND_CHGR_AGND

2

10% 10V X5R 402

5%

2

20% 25V X5R-CERM 0603

1/20W

1/16W MF-LF 402

NO_XNET_CONNECTION=TRUE 1UF

100K

10% 10V X5R 402

1K

D

10UF

200K

Vout = 1.25V * (1 + Ra / Rb)

5%

C7101 1

NO STUFF 1

52

C7199

MF

201

PP5V1_CHGR_VDDP

R7196 1

2

R7122

PP5V1_CHGR_VDDP


5% 1/16W MF-LF 402

1UF

10% 10V X5R-CERM 0402

1

2

10

1/16W MF-LF 402

C7120

R7101 1

2

1/20W

50V NP0-C0G-CERM 0201

1/16W MF-LF 402

5% 1

0.047UF

PP5V1_CHGR_VDD

1

20% 25V X5R-CERM 0603

2

1%

22PF 5%

2

C7198 10UF

681K

2

CRITICAL

R7121

1/16W MF-LF 402


52

(CHGR_SGATE)

R7105 52

C7195

0

P5V1_FB

2

30mA max load

1

9

1

R7195 1

P5V1_BIAS

1 1

CRITICAL

5%

2

C7102 1

5

DP418C-SM

62K

Divider sets ACIN threshold at 13.55V

PP3V42_G3H

FB THRM PAD

(CHGR_AGATE) 3

1

R7181

1

Input impedance of ~90K meets sparkitecture requirements

GND

CHGR_DCIN

MF-LF 5% 402 1/16W

MIN_NECK_WIDTH=0.25 mm

2 MIN_LINE_WIDTH=0.5 mm

1

SOT-323

ACIN pin th reshold is 3.2V, +/- 5 0mV

BIAS 2

2 402

CHGR_SGATE_DIV

L7195

1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE


1%

1/16W MF-LF 402

NC

7

CRITICAL

CRITICAL

P5V1_SW

4

2 402

R7191

33UH-20%-0.39A-0.435OHM SW

5%

G

CRITICAL

332K

SBR0330CW

C

R7180

R7186 1 CRITICAL

NC

1

SHDN*

100K


51 45 39 38 37 36 34 33 30 17 68 65 61


DIRECTFET-MC

CHGR_AGATE_DIV PPDCIN_G3H_ISOL

U7190

LT3470A 8

PPDCIN_G3H_INRUSH

10% 25V X6S-CERM 2 0603

S

IRF9395TRPBF

1%

10% 25V X5R 402

2

Q7180

R7185

470K

0.1UF

10% 10V CERM 2 402

BOOST

DFN

4.7UF

D

65 51 40

10% 25V X6S-CERM 2 0603

C7180 1

5

0

1/16W

0.22UF

3

VIN

4.7UF

NCNCNCNC 0 7 1 8

1 2

PPDCIN_G3H

68 65 51

C7194 1

SWITCH_NODE=TRUE 6

5%

MF-LF

DIDT=TRUE NO_TEST=TRUE

1

1

(P5V1_BIAS)

P5V1_BOOST

MF-LF 5% 402 1/16W

C7190

R7190

For Erp Lot6 spec


2

0.1UF

PPVBAT_G3H_CONN

51 68


1

0.01UF

5

G 4

CHGR_CSO_R_P

1/16W

MF-LF

402

CHGR_CSO_R_N

1/16W

MF-LF

402

(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)

CHGR_ICOMP_RC 1

C7142

C7111 1

1

10% 10V X5R-CERM 0402

10% 16V X7R-CERM 2 0402

2

0.068UF

2

0.01UF

C7100

C7105 1

10% 10V X5R 402-1

10% 50V X5R-CERM 2 0603-1

1UF

C7126 1

0.22UF

52

0.001UF

GND_CHGR_AGND

10% 50V X7R-CERM 2 0402


A

A

SYNC_MASTER=J44


PAGE TITLE

PBus Supply & Battery Charger DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

71 OF 120

8

7

6

5

4

3

PART NUMBER

QTY

REFERENCE DES

CRITICAL

U7200

CRITICAL

IC,ISL95826R6200,PWM,PGOOD,SCREN,32P,QFN

1

BOM OPTION

D

D

R7201 PP5V_S0

61 60 58 54 45 44 41 32 17 16 68 65

1

1

2

R7202 PP5V_S0_CPUVR_VDD

1

PLACE_NEAR=U7200.16:2mm

1

1

0201 2

PP1V05_S0

61 60 57 37 17 16 15 11 8 6 68 65

2

0.1UF

10% PLACE_NEAR=R7279.1:3mm 6.3V CERM-X5R 0201

R7279 1

2

1

54.9 1%

IN IN

CPUVR_ISUMP

BI OUT

70 8

54

54

IN IN

CPUVR_NTC CPU_PROCHOT_L

OUT

70 37 36 6

5

NTC

4

OMIT_TABLE VR_HOT*

1%

CPUVR_PROG1 CPUVR_PROG2 CPUVR_PROG3

28

PROG1 PROG2 PROG3

17 8

27 26 1

CPU_VR_EN

IN

30 31 32 6

CPUVR_COMP

C7215

R7215 845

1

1% 1 /2 0W

2

201 MF

1

R7210

CPUVR_ISUMN

1

316

1

0201 X7R-CERM

2

5% 25V

201 NP0-C0G

RTN

7

FB FB2

15 14 3

CPUVR_IMON

OUT

42

13

12

10

C7210

1

0.01UF 2

10% 10V X7R-CERM 0201

2

C7211

C7240 1

0.01UF

1.2NF

10% 10V X7R-CERM 0201

+/-10% 10V CERM 0201-1

18

CPUVR_FCCM

OUT

54

1

R7225

PWM3 PWM2 PWM1

23 22 20

NC

CPUVR_PWM2 CPUVR_PWM1

2

OUT

54

OUT

54

OUT

8 17

5% 1/20W MF 0201

R7224 DRSEL

25

CPUVR_DRSEL

PGOOD

2

CPU_VR_READY

9

NC NC NC NC

NC NC NC NC

19 21 24

1

0

C

2

5% 1/20W MF 0201

ISUMP ISUMN IMON ISEN1 ISEN2 ISEN3

M D R A H P T 3 3

C7241 1 39PF

R7240

C7213 1

5% 25V NP0-C0G 201

1

1% 1/20W MF 201

2

2

C7230 1

1

10% 10V X7R 0201

R7230 95.3K

1500PF


75K

0.1UF

B

NOSTUFF FCCM

2

CPUVR_COMP_RC

10% 6.3V CERM-X5R 0201

FCCM = 1: Forced CCM FCCM = 0: DCM FCCM = FLOATING: PS4

VR_ON

11

1

1/16W MF-LF 402 PLACE_NEAR=U7200.17:2mm

2

0

SDA ALERT* SCLK CRITICAL COMP

8

CPUVR_ISUMN_R

2

1% 1/20W MF 201

CPUVR_ISEN1 CPUVR_ISEN2

CPUVR_FB CPUVR_FB2 (CPUVR_ISUMP)

22PF

2

10% 25V

CPU_RTN

C7216

820PF

CPUVR_ISUMN_RC

2

C7202 1

LLP

SLOPE


10% 25V X7R-CERM 201

54

2

1% 1/20W MF 201

29

220PF

IN

2

1% 1/20W MF 201

ISL95826

CPUVR_SLOPE

C7214 1

40 54 55 57 65

7 1

U7200

6.04K

R7280


54

2

1% 1/20W MF 201

R7220

MF 2 201

2


CPU_VIDSOUT CPU_VIDALERT_L CPU_VIDSCLK

70 8 70 8

1% 1/20W MF 201

1

R7221 34K

9.31K

1/20W

MF

201

1

R7222

130

1/20W

PPBUS_S5_HS_COMPUTING

(GND)

1

R7223 16.9K

2

2

5%

10% 25V X7R 0402

VDD VIN

100KOHM

10

1

0.22UF

10% 10V X5R 402-1

R7237

95.3K

C7278 1

2

2

1% 1/20W MF 201

C7201

6 1

R7236 1 1% 1/20W MF 201

7.5K


1UF

R7235 CPUVR_NTC_R PLACE_NEAR=Q7310.3:3MM PLACE_NEAR=L7310.1:3MM 1

PPVIN_S0_CPUVR_VIN


5% 1/16W MF-LF 402

C

DESCRIPTION

1

353S4170

2

2 2

1% 1/20W MF 201

B

2


R7241 CPU_VCCSENSE_P_R


R7243 70 8

IN

CPU_VCCSENSE_P

1

0

C7242 2

1

CPU_VCCSENSE_N

CPU_VCCSENSE_P_RC

XW7261

NOSTUFF


R7242 2

1K

1% 1/20W MF 201

R7250 1

1

2K

1% 1/20W MF 201

2

CPUVR_FB_RC NOSTUFF 1

SM

1

2

1

C7260

1

330PF 2

10% 16V X7R-CERM 0201

C7250 330PF

2


A

2

100PF

5% 25V NP0-CERM 0201

IN

1.69K 1% 1/20W MF 201


2

5% 1/20W MF 0201

70 9

1

10% 16V X7R-CERM 0201

C7261 330PF

2

10% 16V X7R-CERM 0201

A

SYNC_MASTER=J44


PAGE TITLE

CPU VR12.6 VCC Regulator IC DRAWING NUMBER

Apple Inc. R

REVISION


BRANCH


PAGE

72 OF 120

SIZE

D

8

7

65 57 55 53 40

6

5

4

3

2

CRITICAL

1

NOSTUFF CRITICAL

CRITICAL

1

C7313 68UF

1

C7314 68UF

THESE TWO CAPS ARE FOR EMC

NOSTUFF CRITICAL

1

C7315 10UF

1

C7316 10UF

C7317 1.0UF

1

C7370 33UF

20% 2 16V

POLY-TANT CASED12-SM

CRITICAL

PP5V_S0

D

CPUVR_UGATE1 4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF

SISA18DN PWRPAK-SM

PILE063T-SM 152S1821

R73121

54 53

DFN

CPUVR_PWM1

3 PWM

IN

CPUVR_FCCM

7 FCCM

353S3942

4

9

4

CPUVR_BOOT1

2.2

1

C 60 58 54 53 45 44 41 32 17 16 68 65 61

1K

1% 1/20W MF 201

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

402

1

2

3 PWM

54 53

IN

CPUVR_FCCM

7 FCCM

DFN

CRITICAL

CRITICAL

68UF

68UF

NOSTUFF CRITICAL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE SWITCH_NODE=TRUE NOSTUFF

OMIT_TABLE CRITICAL

5% 1/10W MF-LF 6032

SISA18DN PWRPAK-SM

S

B

OUT

53

CPUVR_ISUMP

OUT

53 54

152S1821


77 41

OUT


1

CRITICAL

D

C7375 68UF

20% 2 16V


CPUVR_ISNS2_N

41 54 77


THESE TWO CAPS ARE FOR EMC

C

D 4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

2

CPUVR_BOOT2

C7321

G

OMIT_TABLE CRITICAL

Q7321

SISA12DN PWRPAK-SM

OUT

41 54 77

1.00

1% 1/20W MF-LF 20201

C7322

CPUVR_ISUMN

R73251 1K

1% 1/20W MF 2012

1


OMIT OUT

53 54

NONE NONE NONE 0201

200K

2

R7327

CPUVR_ISNS1_N NOSTUFF 1 2

R7326 1% 1/20W MF 201

CPUVR_ISEN2

OUT

53

CPUVR_ISUMP

OUT

53 54

41 54 77


S

R7321 MIN_LINE_WIDTH=0.25 MM 5% MIN_NECK_WIDTH=0.2 MM 1/16W DIDT=TRUE MF-LF

CPUVR_ISNS2_N

8 10 42 65 68

Vout = 1.85V max 40A MAX OUTPUT F = 800KHZ

2 4

R7324

0.001UF

5

PPVCC_S0_CPU

1

10% 2 50V X7R-CERM 0402

2.2

CPUVR_ISNS2_P

CPUVR_PH2_SNUB 1

1 2 3

CPUVR_LGATE2

1 3

1% 1W MF 0612

DIDT=TRUE NOSTUFF

UGATE 1

9

CPUVR_ISEN1

NOSTUFF CRITICAL

2.2

Q7320

G


PHASE 8

4

NONE NONE NONE 0201

R7320

PILE063T-SM

R73221

CRITICAL

353S3942

NOSTUFF 1 2

0.00075

0.4UH-20%-23A PPVCC_S0_CPU_PH2 1 2

CPUVR_PHASE2 5

BOOT 2

5 THRM LGATE GND PAD

20% 2 16V

CRITICAL

ISL6208D CPUVR_PWM2

CRITICAL

C7374 68UF

1 C7326 1 C7327 1 C7328 1 C7329 C7323 1 C7324 1 C7325 10UF 10UF 1.0UF 0.001UF 0.001UF

L7320

CPUVR_UGATE2 4

IN


1

20% 20% 10% 10% 10% 20% 20% 16V 35V 50V 50V 16V 16V 2 POLY-TANT 2 POLY-TANT 2 16V X6S-CERM 2 X6S-CERM 2 CERM-X6S 2 X7R-CERM 2 X7R-CERM 0603 0402 0402 0402 CASE-D2E-SMCASE-D2E-SM0603

D

53

20% 2 16V

CPUVR_BOOT1_RC

1UF

U7320

CRITICAL

C7373 68UF

R7317

53 54

200K

PWRPAK-SM

2

10% 16V X6S-CERM 2 0402

VCC

1

1 2 3

C7320 1

6


OMIT OUT


1% 1/20W MF 2201

2

CRITICAL

PHASE 2

CRITICAL

C7372 68UF POLY-TANT CASE-D2E-SM

41 54 77

R7316

SISA12DN

10% 16V CERM 402

PP5V_S0

C7380 33UF

20% 2 16V


Q7311

0.22UF 1

1

S

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM 5% 1/16W DIDT=TRUE MF-LF

C7311

CRITICAL

1

C7378 33UF

20% 2 16V


20% 2 16V

1% 1/20W MF-LF 2 0201

R73151

CRITICAL

G

R7311

OUT

CPUVR_ISUMN

C7312

10% 2 50V X7R-CERM 0402

OMIT_TABLE

D

CPUVR_LGATE1


CRITICAL

1

C7376 33UF

20% 2 16V

1.00

0.001UF

5

CRITICAL

1

R7314

1

PHASE 8 5 THRM LGATE PAD

CPUVR_ISNS1_N

CPUVR_PH1_SNUB

BOOT 2 UGATE 1


1

1 3

DIDT=TRUE NOSTUFF

CRITICAL

GND

1% 1W MF 0612

C7371 33UF

20% 2 16V

1

ISL6208D IN

2 4

CPUVR_ISNS1_P

OUT

77 41

5% 1/10W MF-LF 603 2

1 2 3

U7310 53


2.2

S

6

VCC

0.00075

0.4UH-20%-23A PPVCC_S0_CPU_PH1 1 2

CPUVR_PHASE1

Q7310

G


PHASE 1

OMIT_TABLE CRITICAL

D

1

Note: C7377, C7379, C7381 were removed. Area where the pads used t o reside was preserved .

R7310

CRITICAL

1UF

10% 16V X6S-CERM 2 0402

L7310

5

C7310 1

NOSTUFF CRITICAL

CRITICAL

1

1 C7319 C7318 0.001UF 0.001UF

20% 20% 10% 10% 10% 20% 20% 35V 50V 50V 2 16V 2 16V 2 16V 2 16V X6S-CERM 2 CERM-X6S 2 X7R-CERM 2 X7R-CERM POLY-TANT POLY-TANT X6S-CERM 0603 0402 0402 0402 CASE-D2E-SMCASE-D2E-SM0603 68 65 61 44 41 32 17 16 60 58 54 53 45

1

Additonal Input Bulk Caps


B

1 2 3

1 CPUVR_BOOT2_RC


402

0.22UF 1

2

10% 16V CERM 402

A

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

CPU VR12.5 VCC Power Stage DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

73 OF 120

8

7

6

5

4

3

2

1

D

D DDR3L (1V35 S3) REGULATOR


65 57 54 53 40


CRITICAL 1

CRITICAL 1

C7431 68UF

C7434 68UF

20%

20%

2 16V 73 65 55 41 22 21 20 19 17

C7400

VLDOIN 12

DDRREG_FB MEMVTT_PWR_EN DDRREG_EN

VTT Enable VDDQ/VTTREF Enable

17 16

DDRREG_1V8_VREF

6 1

C7415 1

R7415

8

19.6K

0.1UF

DDRREG_MODE DDRREG_TRIP

1%

10% 16V X7R-CERM 2 0402

1/16W MF-LF 2 402

19 18

V5IN

VBST DRVH SW

15

DRVL PGOOD VDDQSNS VTT VTTSNS

11

U7400

S3 S5

TPS51916

DDRREG_VBST DDRREG_DRVH DDRREG_LL

14 13

CRITICAL

REFIN MODE TRIP

OMIT_TABLE 1

R74191

R7416

150K

100K

1

C7416

0 1

0.01UF

1% 1/16W MF-LF

1% 1/16W MF-LF 402 2

PGND GND

2

2 402

10% 16V X7R-CERM 0402

1

200K 1%

PLACE_NEAR=U7400.8:5mm PLACE_NEAR=U7400.8:1MM

DDRREG_P1V35_L

R7417

D

7

4

3

DDRREG_VTTSNS 73 68 65

1/16W MF-LF

B

10% 25V X5R 402

FDMS3602S POWER56

1

C

CRITICAL

L7430

1.0UH-20%-15A-0.0066OHM PHASE

1

7

2 PIME063T-SM

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm 61

152S1822

6

XW7450 SM

PPDDR_S3_REG_R

1

2

VOLTAGE=1.35V

MIN_LINE_WIDTH=0.8 MIN_NECK_WIDTH=0.1

MM MM

20%

3

4

CRITICAL

5

(DDRREG_DRVL)

1

CRITICAL

C7460 1

1

20% 25V X5R-CERM 2 0603

2

10UF

POLY-TANT CASE-B2-SM1

10UF

20% 25V X5R-CERM 0603

C7441 1

2 1

C7445

10% 50V X7R-CERM 0402

10UF

330UF

20% 2.0V 2 POLY-TANT CASE-B2-SM1

C7446

0.001UF

CRITICAL

20% 2 2.0V POLY-TANT CASE-B2-SM1

C7461

1

2 2.0V

C7442 330UF


2

20% 25V X5R-CERM 0603


2

XW7401

C7460, C7461 close to memory 2

XW7400

C7450 1

(DDRREG_VDDQSNS)

77 41

0.22UF

10% 10V CERM 402

1

17 19 20 21 22 41 55 65 73

VOUT = 1.35V 9A MAX OUTPUT f = 400 kHz

C7440 330UF

2

CRITICAL

PP1V35_S3

CRITICAL 1

XW7460 1

1 2

SM

2

(DDRREG_LL)


10mA max load

1/16W MF-LF

2 402

OUT

SM

NC_ISNS_DDR_S3P PLACE_NEAR=C7442.1:2MM

2

77 41

OUT

1

NC_ISNS_DDR_S3N


GND_DDRREG_SGND

S



CRITICAL G

CRITICAL

Q7430

2

PPVTTDDR_S3

51.1K

SOD-VESM-HF

1


1

SM

1

R7418


3

DDRREG_VBST_RC

GATE_NODE=TRUE

9

5

2

C7425 0.1UF

2

DIDT=TRUE

VTT THRM GND PAD


OMIT_TABLE

0.001UF

1%

2 402

Q7419

SSM3K15FV

1

0

GATE_NODE=TRUE

DDRREG_DRVL DIDT=TRUE DDRREG_PGOOD OUT DDRREG_VDDQSNS PP0V675_S0_DDRVTT

20


OMIT_TABLE

5% 1


MF-LF 1/16W

DIDT=TRUE

VTTREF


NO_TEST=TRUE

402

SWITCH_NODE=TRUE

QFN

VREF

R7425

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm SWITCH_NODE=TRUE DIDT=TRUE

IN

C7433

(DDRREG_DRVH) 2


IN

1

1.0UF

2

C 61

C7435


20% 10V X5R-CERM 2 0402-1

17

1

10% 10% 20% 35V 35V 50V 2 CERM-X6S 2 CERM-X6S 2 CERM 0402 0402 0402 PLACE_NEAR=Q7430.5:3mm PLACE_NEAR=Q7430.5:3MM PLACE_NEAR=C7435.1:3MM

10UF

20% 10V X5R-CERM 0402-1

1

10UF

IN

1.0UF

C7401 1 CRITICAL

19


C7432

CRITICAL

PP5V_S4

66 65 63 62 60 57 56 46 33 32 68

2 16V


PP1V35_S3

1


MEM_VDD_SEL_1V5_L

IN

B 15

R7401 1 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

10 5%

1/20W

2

DDRREG_VDDQSNS_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

MF

201

PART NUMBER

A

QTY

114S0411

1

114S0391

1

376S0612

1

114S0428

1

DESCRIPTION

REFERENCE DES

CRITICAL

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

R7416

C RI TI CA L

RES,MTL FILM,1/16W,60.4K,1,0402,SM D,LF

R7416

CRITICAL

Q7419

C RI TI CA L

P PD DR :1 V5

R7419

CRITICAL

PPDDR:1V5

MOSFET,N-CH,30V,100MA,7.0OHM,SOT-723,HF RES, MTL FILM,1/16W,150k,0402,SMD,LF

BOM OPTION P PD DR :1 V5 PPDDR:1V35

A

SYNC_MASTER=J44

PAGE TITLE


1.35V DDR3 SUPPLY DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

74 OF 120

8

7

6

5

4

3

2

1

D

D

65 40

PPBUS_S5_HS_OTHER5V 65 40

CRITICAL

CRITICAL

C7543 1

C7540 1

C7542 1

20% 16V 2 POLY-TANT CASE-D2E-SM



68UF

PPBUS_S5_HS_OTHER3V3

PP5V_S4

65 63 62 60 57 56 55 46 33 32 68 66

CRITICAL

68UF

1

C7541

1

10% 25V X6S-CERM 0603

2

4.7UF

68UF

2

0.001UF

1UF

10% 25V X5R 603-1

PP5V_S4

1

10.8A MAX OUTPUT

152S0688

1

C

CRITICAL

1.0UH-21A-0.006OHM

1

C7553

0.001UF 10% 50V X7R-CERM 0402

20%

2

POLY-TANT CASE-D3L-SM

C7552

C7550

P5VS4_VSW MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

1

10UF

330UF

M M 3 : 1 . 3 5 5 7 C = R A E N _ E C A L P

20% 25V X5R-CERM 2 0603

20% 6.3V 2 POLY-TANT CASE-D3L-SM

M M 3 : 1 . 0 2 5 7 L = R A E N _ E C A L P

1

P5VS4_VFB1_R 2

5% 1/16W MF-LF 2 402

5VS4_VFB1_RR

BG

XW7520 SM

1

2

M M 3 : 2 . 0 2 5 7 L = R A E N _ E C A L P

5

PGND

1/10W MF-LF 603

9

P5VS4_DRVH


GATE_NODE=TRUE

DIDT=TRUE


SWITCH_NODE=TRUE

DIDT=TRUE


GATE_NODE=TRUE

DIDT=TRUE

P5VS4_DRVL P5VS4_CSP1 P5VS4_CSN1

1

NO STUFF

C7599 1

R7547

0.0033UF

10% 50V CERM 2 402

1

3.01K

XW7521

1/16W MF-LF 402

1

61

IN

61

OUT

41.2K 1%

2

P5VS4RS3_EN P5VS4RS3_PGOOD

4 5

1

MODE VFB1 COMP1

2

VBST2

26 24

SW2

25

DRVL2

27

1/16W MF-LF 402

1/16W MF-LF 402

2

2

EN1 PGOOD1

EN2 PGOOD2

3

15 21 20

IN

2

0


GATE_NODE=TRUE


P3V3S5_CSP2 P3V3S5_CSN2

R7506

3 3

2

5

2

1

1.82K

10K

2

1/16W MF-LF 402

NO STUFF

1

C7598

0.001UF

2

2 1

10% 50V X7R-CERM 0402

R7516

2

5.23K

XW7560

1%

2

2

P3V3S5_COMP2_R

M M 3 : 2 . 0 6 5 7 L = R A E N _ E C A L P

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE SWITCH_NODE=TRUE

1%

1/16W MF-LF 402

2

P3V3S5_SNUBR

2

10% 16V X7R-CERM 0402

1/16W MF-LF 402

R7539 1

12.1K

SM

4

1/10W MF-LF 603

SM

1/16W MF-LF 402

P3V3S5_CSP2_R

1

M M 3 : 1 . 0 6 5 7 L = R A E N _ E C A L P

CRITICAL

C7590

1

20% 25V X5R-CERM 0603

2 6.3V

10UF

M M 3 : 1 . 2 9 5 7 C = R A E N _ E C A L P

5%

1%

R7538

1

R7546

1%

1/16W MF-LF 402

7

R7598 1 3

C

2

CRITICAL

10

1

165K

36 61

10% 50V X7R-CERM 0402

2

NO STUFF

1

61

POWER56

PHASE

0.1UF

IN

C7572 1

0.001UF

FDMS3602S 1

6

P3V3S5_RF P3V3S5_VFB2 P3V3S5_COMP2

OUT

PCMC063T-SM

Q7560

C7588

S5_PWR_EN S5_PWRGD

2

C7537

1

50V CERM 402

2

2

1

C7536 4700PF

C7538

1

1

10% 100V CERM 402

2

2

4700PF

10% 100V CERM 402

(P5VP3V3_VREF2)

C7592 330UF 20%

POLY-TANT CASE-D3L-SM

2

XW7562 SM

1

P3V3S5_VFB2_R

2

XW7561

R7562

1

SM

10

1

5% 1/16W MF-LF 2 402

DIDT=TRUE

PLACE_NEAR=U7501.28:1MM 1

59 60 61 65 68 8 11 13 15 16 17 18 26 27 29 77

1.0UH-22A

CRITICAL

P3V3S5_TG

2

S WI T C H_ N O DE= TR U E

THRM_PAD

XW7500

20% 50V CERM 0402

F = 600 KHZ

L7560

376S0958

2

MIN_LINE_WIDTH=0.6 MM 5% MIN_NECK_WIDTH=0.2 MM 1/16W DIDT=TRUE MF-LF GATE_NODE=TRUE 402 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

1%

P5VS4_COMP1_R

0.001UF

10.5A MAX OUTPUT

CRITICAL

10% 50V X7R 2 603-1

R7563

36 37 61

P3V3S5_DRVL

1

C7583

VOUT = 3.3V

152S0754 C7564 1 0.1UF

P3V3S5_LL DIDT=TRUE

16

2

PP3V3_S5


P3V3S5_DRVH DI D T= T R UE

17

1

10% 25V X6S-CERM 0603

1

20% 10V X5R-CERM 402

SWITCH_NODE=TRUE

DIDT=TRUE

18

C7581 4.7UF

2

20% 6.3V X5R 603

2.2UF

P3V3S5_VBST DIDT=TRUE

DRVH2

1

68UF

C7503

SMC_PM_G2_EN

1%

1%

2

12

12.1K

10K

DIDT=TRUE

10% 10V CERM 402

RF VFB2 COMP2

R7536 1

R7537

1

0.22UF

CSP2 CSN2

GND

1/16W MF-LF 402

C7501 1

EN

C7582 1 20% 16V 2 POLY-TANT CASE-D2E-SM

68UF

10UF

1

CSP1 CSN1

8 2

5%

R7520

9

2

1%

SM

DRVL1

10

1%

R7556 1

2

2.49K

SW1

30

8

P5VS4_VFB1 P5VS4_COMP1

2 F E R V

QFN 0 8 9 1 5 S P T

DRVH1

32

11

2

10% 16V X7R-CERM 0402

3 G E R V

VBST1

7

0.1UF

P5VS4_SNUBR

5 G E R V

3 1

31 1

P5VS4_LL

N I V

2 2

14

19

SWITCH_NODE=TRUE

DIDT=TRUE

9 2

SKIPSEL1 CRITICAL SKIPSEL2 U7501 OCSEL

6

P5VS4_VBST

2

150PF

1

2

P5VP3V3_SKIPSEL

5%

1/16W MF-LF 402

C7518


SWITCH_NODE=TRUE

P5VS4_CSP1_R

2

1

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE

4

MF

0201

MF

0201

R7544 1

P5VS4_TG

3

8

R7599 5%

2

10

TG

TGR

7

1

SM

R7522

VSW

1/20W

0

1/20W

10% 50V X7R 603-1

NO STUFF 1

XW7522

1

6

2

CRITICAL

1

1

CSD58872Q5D VIN SON5X6

2

W S 5 V

5%

5%

C7524 0.1UF

Q7520

PCMB103T-1R0MS

C7571

330UF

2 6.3V

CRITICAL

B

1

L7520

CRITICAL

2

0

R7500 1


CRITICAL

F = 600 KHZ 1

R7501

SKIP_5V3V3:AUDIBLE

3 2

CRITICAL


C7505

2

P5VP3V3_VREF2 1

CRITICAL


68UF

CRITICAL

2

SKIP_5V3V3:INAUDIBLE

VOUT = 5.0V

34 65 68

VOUT = 5V 100MA MAX OUTPUT

C7500 1

20% 50V CERM 0402

P5VP3V3_VREG3 57 56 55 46 33 32 68 66 65 63 62 60

CRITICAL

PP5V_S5

C7570

C7539

P3V3S5_VFB2_RR

47PF

B

5%

50V CERM 402

R7560 1 23.2K

(P5VP3V3_VREF2)

1/16W MF-LF 402

0.5% 1/16W MF-LF 0402

2

GND_5V3V3_AGND 1

R7521


R7561 1

10.0K

10.0K

0.5% 1/16W

0.5% 1/16W

MF 2

A

MF

402

402

2

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

5V / 3.3V Power Supply DRAWING NUMBER

Apple Inc. R

REVISION


BRANCH


PAGE

75 OF 120

SIZE

D

8

7

6

5

4

3

2

1

D

D 1.05V S0 Regulator


65 55 54 53 40

1

C7622 1 60 57 53 37 17 16 15 11 8 6 68 65 61

1000PF

PP1V05_S0

5% 25V CERM 0402

P1V05S0_BOOT_RC

66 65 63 62 60 56 55 46 33 32 68

PP5V_S4

1

10UF

C

20% 10V X5R 603

C7600 1 10UF

20% 10V X5R 603

1

2

2.2

C7630

C

16V X7R-CERM 0402

CRITICAL

5%

2

Q7630

MF-LF

603

BYPASS=U7600.12:1mm

2

FDPC1012S

2

LLP

VLDOIN

61

P1V05S0_EN

P1V05_S0_VREF

16 6

MIN_LINE_WIDTH=0.2 MIN_NECK_WIDTH=0.1

C7615

1

1

0.1UF

10% 16V X7R-CERM 0402 BYPASS=U7600.6:1mm

R7611 35.7K

MIN_LINE_WI DTH=0.2 mm MIN_NECK_WI DTH=0.1 mm

1%

2

1/20W

MF 2

8

P1V05S0_MODE

19

P1V05S0_TRIP

18

TPS51916 QFN

VREF

CRITICAL

REFIN MODE TRIP

VTTREF


R7612

1

49.9K 1/20W

2 201

2 PLACE_NEAR=U7600.8:5mm

C7616 0.01UF

1% MF

DRVL PGOOD VDDQSNS VTT VTTSNS

0 1

1

10% 16V X7R-CERM 0402

R7610

1

1K

201

14 1

P1V05S0_DRVH

13

MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 GATE_NODE=TRUE DIDT=TRUE

11

mm mm

0

2

7

Short Rsense OMIT

P1V05S0_DRVH_R

HSG

MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

5%

1/16W

MF-LF

3

P1V05S0_VTT

R7640

1

SW

mm mm

0.003

L7630

1% 1w CYN 0612-SHORT

1.0UH-20%-11A-0.011OHM

2

402

MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 SWITCH_NODE=TRUE DIDT=TRUE

9

3

1

4

NOSTUFF 1

R7632

2 PP1V05_S0_REG_R FDSD0630-SM CRITICAL

MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 VOLTAGE=1.05V

mm mm

1 3

MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2 GATE_NODE=TRUE DIDT=TRUE

5

7

LSG

mm mm

2

Vout = 1.05V CRITICAL

C7649

5% 1/10W MF-LF 603

1 2

P1V05S0_PGOOD

R7614

OUT

D D D N N N G G G

61

ISNS_1V05_S0_P

OUT

ISNS_1V05_S0_N

NOSTUFF

C7632 1

77 41

5% 25V CERM 0402

10% 50V X7R-CERM 0402

F = 400 KHZ 2

2 CRITICAL 1

0.001UF 0 6 5 1

P1V05S0_VTTREF

5A MAX OUTPUT

POLY-TANT CASE-B2-SM1

1000PF

P1V05S0_LL_SNUB DIDT=TRUE

20% 2.0V

C7623 1 OUT

1

330UF

PLACE_NEAR=L7630.2:1.5mm

77 41

53 57 60 6 8 11 15 16 17 37 61 65 68

PP1V05_S0

2 4

2.2

1

VTT THRM GND PAD 4

V+ V+

P1V05S0_LL

20

C7648 330UF 20%

2

2

2


XW7610 SM

2.0V POLY-TANT CASE-B2-SM1

1

MF 2


201 PLACE_NEAR=U7600.18:3mm

2

XW7600

B

9

1/20W

MF 2

8

1%

1/20W

MF

201

mm mm

R7631

14.7K

1%

1/20W 2

1

47.5K

1%

BYPASS=U7600.8:1mm

R7613

MIN_LINE_WIDTH=0.5 MIN_NECK_WIDTH=0.2 DIDT=TRUE

15

P1V05S0_DRVL

201

PGND GND 1

VBST DRVH SW

U7600

S3 S5

mm mm

P1V05S0_FB

P1V05S0_VBST

V5IN

Scrub S3 & S5 pins connections! 17

10% 35V CERM-X6S 0402

CASE-D2E-SM

10%

R7630 1/10W

P1V05S3_EN

C7624

2

1.0UF

16V POLY-TANT

0.1UF 2

BYPASS=U7600.2:1mm

12

1

20%

2


MIN_LINE_WI DTH=0.5 mm MIN_NECK_WI DTH=0.2 mm DIDT=TRUE

C7601 1

C7619 68UF

2

C7650 1 0.22UF

SM

1

10% 10V CERM 402

B

2

P1V05S0_AGND MIN_LINE_WI DTH=0.6 mm MIN_NECK_WI DTH=0.2 mm VOLTAGE=0V


R7641 P1V05S0_VDDQSNS MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

A

1

10

5% 1/20W MF 201

2

P1V05S0_VDDQSNS_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

A

SYNC_MASTER=J44


PAGE TITLE

1.05V S0 Power Supply DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

76 OF 120

8

7

6

5

4

3

2

1

Page Notes Power aliases required by this page: - =PPVIN_S0SW_LCDBKLT FET

(9-12.6V LCD BA CKLIGHT INPUT)

- =PP5V_S0_BKLT

(5V BACKLIGHT DRIVER INPUT)

- =PP5V_S0SW_KBDLED

(5V KEYBOARD BACKLIGHT INPUT)

BOM options provided by this page: BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds BKLT:PROD - Stuffs 0 ohm series R for production

D

SENSOR ON PAGE 54 USES R7700 TO MEASURE THE POWER GOING TO LCD BACKLIGHT

740S0159 CRITICAL

PPBUS_G3H

1

2

58

PPVIN_S0SW_LCDBKLT_F 1 3

1% 1W MTL 0612

FDC638APZ_SBMS001 SSOT6-HF

2 4

0603

58

PPVIN_S0SW_LCDBKLT_R 1

1

77 40

OUT

OUT

5

4

PPVIN_S0SW_LCDBKLT MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V MAKE_BASE=TRUE


2

1

3

1% 1/16W MF-LF 402

NOSTUFF

152S1527 CRITICAL

C7701

L7710

10% 50V CERM 402

1

1

C7710

1

4.7UF

63.4K

PP5V_S0

65 61 60 58 41 32 17 16 54 53 45 44 68

R7744 0

1%

2

1

1/16W MF-LF 402

5%

1/16W MF-LF

402 2 58

C7740

1

10% 10V X5R 402-1

2

GND_BKLT_SGND

58

1UF

1

1UF

2

11

BKLT_SENSE_OUT

19 17

R7742 0

12

BKLT_EN_R NO STUFF

2

5% 1/20W

1

MF

0201

15 16

C7742 33PF 5%

2 58

GND_BKLT_SGND

25V NPO-C0G 0201

IN

SMC_SYS_KBDLED

0

1

1

MF

0201

B

10% 100V X7R 1210-1

2

2

C7716

1

58 62 68

10% 100V X7R 1210-1

2

2.2UF

C7717 1000PF 10% 100V X7R-CERM 0603

PLACEMENT_NOTE: SANDWICH C7713 AND C7714 SANDWICH C7715 AND C7716

PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM PLACE_NEAR=D7710.K:5MM

1% 1/16W MF-LF

SI7812DN

2 402

PWRPK-1212-8

C

1

R7732

0

1 2

5% 1/16W MF-LF

150K

3

1% 1/16W MF-LF

2 402


LCDBKLT_SW

1

4 58

LCDBKLT_FB LCDBKLT_FET_DRV

20

BKLT_ISET_KEYB

R7720

13

BKLT_KEYB1 BKLT_KEYB2

1

21

14

10.2 2

PART NUMBER

BKLT:ENG


QTY

1 16 S0 004

6

RES,MTL FILM,0 OHM,1A MAX,0402,SMD

KBDLED_CATHODE1

8

1

10.2 2

31.6K

CRITICAL

R7720,R7721

CRITICAL

BOM OPTION

BKLT:PROD

35 68


KBDLED_CATHODE2

35 68


0.1% 1/16W TF 402

R7741

REFERENCE DES


R7721 BKLT:ENG 1

DESCRIPTION

1

0.1% 1/16W TF 402

1% 1/20W MF 201 2 PLACE_NEAR=U7700.20:5MM

5 2

C7747 33PF 5%

2 58

C7715

1

2.2UF

10% 100V X7R 1210-1

2

13.3K

R7733

2 402 2 58

C7714

1

2.2UF

10% 100V X7R 1210-1

R7731

1

A D D V

4 3 7 3 2 2 2 2

BKLT_PWM_KEYB NO STUFF

2

5% 1/20W

2.2UF

2

SM

R W X _ B T _ T L K B D C1 L

4

LCDBKLT_FET_DRV_R

C7713

1

1

Q7701

2 W W W S S S _ _ _ D A D D D D D N N N N N THRM G G G G G PAD

R7747 36

2

XW7710

CRITICAL

58

LP8548B1SQ_-04 SD SW VSENSE_N SW VSENSE_P FB GD SENSE_OUT ISET_KEYB EN PWM_KEYB KEYB1 KEYB2 SCL (IPU) SDA (IPU) SW2 FB2 CRITICAL 353S4160

1

PLACE_NEAR=D7710.K:2MM

5

LLP

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW 1

PLACE_NEAR=L7710.1:5MM

8 1

D D D V

9

EDP_BKLT_PSR_EN

10% 25V X5R 402

U7700

5% 1/20W MF 201

10

IN

C7712

2


10% 10V X5R 402-1

R7740

BKLT_SD

62

1

0.1UF

10% 25V X6S-CERM 0603


1M

2

PPVOUT_S0_LCDBKLT

K

DFLS2100

C7741

5

C


PP5V_S0_BKLT_A PP5V_S0_BKLT_D

1

2

SANDWICH C7710 AND C7711

2 402 58

A

W S _ T L K B D C L _ W S _ N I V P 58 P

PLACEMENT_NOTE:

5%

1/16W MF-LF


R7745 0

C7711 4.7UF

10% 25V X6S-CERM 0603

2

1

D7710

POWERDI-123

2 DEM8030C-SM

LCDBKLT_EN_L

R7702

371S0704 CRITICAL

22UH-20%-2.4A-0.105OHM

0.001UF 2

ISNS_LCDBKLT_N 1


2

R7701 80.6K

10% 16V X7R-CERM 0201

2

ISNS_LCDBKLT_P

58

6

1

C7700 1000PF

77 40

D

Q7700

0.025

3AMP-32V 65 52 51 40 25 68

CRITICAL

R7700

F7700

GND_BKLT_SGND

XW7700

25V NPO-C0G 0201

58

SM

1

58

2

B

PPVOUT_BKLT_FB2 PP5V_S0_KBDBKLT_SW 2

58 60 58 54 53 45 44 41 32 17 16 68 65 61

XW7720

GND_BKLT_SGND

SM


PP5V_S0

1

R7752

1

2.4K

53 45 44 41 32 17 16 68 65 61 60 58 54

5%

1

MF 2

201

IN

1

I2C_BKLT_SCL

1

R7751 68 66 62

BI

I2C_BKLT_SDA

1

0

2

0

2

C7720

1

10% 25V X5R-CERM 603

2

2.2UF

BKLT_SCL

2

5%

0201

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

PPVIN_S0SW_LCDBKLT_F

1


0.1UF

C7723

1

1.0UF

10% 16V X5R-CERM 0201

2


10% 50V X7R 0805

C7724

1

10% 50V X7R 0805

2

1.0UF

2

C7725

1

10% 50V X7R-CERM 0402

2

0.001UF

C7726

1

1.0UF 10% 50V X7R 0805

C7727 1.0UF

2

10% 50V X7R 0805

LCDBKLT_SW

58

PPVIN_SW_LCDBKLT_SW


LCDBKLT_FET_DRV MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V 58


PPVOUT_BKLT_FB MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.25 MM




PP5V_S0_KBDBKLT_SW

58

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=40V DIDT=TRUE

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

LCD AND KBD BKLT DRIVER

SWITCH_NODE=TRUE

DRAWING NUMBER

58

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=53V DIDT=TRUE SWITCH_NODE=TRUE

PPVOUT_S0_LCDBKLT


KBD BKLT LINE WIDTHS

58

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=53V DIDT=TRUE SWITCH_NODE=TRUE

GATE_NODE=TRUE

PPVIN_S0SW_LCDBKLT_FET

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.9V

58

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V DIDT=TRUE 58


PPVIN_S0SW_LCDBKLT

LCDBKLT_FET_DRV_R

T-BONE C7726 AND C7727



LCD BKLT LINE WIDTHS

58


58

35 58 68

K

PLACEMENT_NOTE:



PPVIN_S0SW_LCDBKLT_R PP5V_S0_BKLT_D

2

PLACEMENT_NOTE:

MF

MIN_LINE_WIDTH=2 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

PPVOUT_S0_KBDBKLT

SOD-123

A

RB160M-60G

C7722

BKLT_SDA

1/20W

58

10% 25V X5R-CERM 603

2.2UF

PBUS LINE WIDTHS PP5V_S0_BKLT_A

1

MF

0201 PLACE_NEAR=U7700.16:10MM

A

C7721

1/20W

5%

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

D7720

2 PST041H-SM


R7750 68 66 62


371S0572 CRITICAL

10UH-20%-1.4A-0.17OHM

PP5V_S0

1/20W

MF

201

1

152S1701 CRITICAL

L7720

R7753 2.4K

5%

1/20W

2


PPVOUT_S0_KBDBKLT 58 62 68


Apple Inc.

35 58 68


PPVOUT_BKLT_FB2

R 58

SIZE

D

REVISION


BRANCH


PAGE

77 OF 120

8

7

6

5

4

1

1 VIN

CRITICAL

C7870

20% 2 6.3V X5R 0603

CRITICAL

61

IN

P1V5S0_EN

2 EN CRITICAL LX 8

OUT

P1V5S0_PGOOD

3 POR

VFB 6

4 SKIP

353S2535

CRITICAL XDP_CONN

L7870

2.2UH-2A-0.155-OHM

DFN

61

D

152S1051

22UF

U7870

ISL8009B

1

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

PP3V3_S5

D

2

1.05V SUS LDO

1.5V S0 Switcher 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 56

3

P1V5_S0_SW


1

PP1V5_S0

8 47 60 61 63 65 68

U7840

2 2512

Vout = 1.508V

1

R7882


10

RSI 5

GND THRM_PAD 7 9

2

65 61 60 45 14 11 8

TPS720105

PP3V3_SUS

4 BIAS

MAX CURRENT = 0.6A

5% 1/16W MF-LF 402

3 EN

NC 2

XDP

C7840 1

P1V5_S0_FB_R 1

C7876 10PF

1

5% 50V C0G-CERM 2 0402

P1V5_S0_FB

1

R7880 100K

1% 1/16W MF-LF 2 402

CRITICAL

C7873 22UF

20% 6.3V 2 X5R 0603

1

CRITICAL

C7874 22UF

20% 6.3V 2 X5R 0603

1UF

10% 6.3V CERM 2 402

PP1V05_SUS

SON

GND 5

THRM PAD 7

16 65

Vout = 1.05V Max Current = 0.35A

OUT 1

6 IN

Freq = 1.6MHZ

NC 1

XDP

C7841 2.2UF

10% 6.3V 2 X5R 402

1

R7881 113K

1% 1/16W MF-LF 2 402

C

C

Vout = 0.8V * (1 + Ra / Rb)

B

B

A

A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Misc Power Supplies DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

78 OF 120

8 7 1.5V S0 Audio Switch (BYPASSED) 0

1


2

MF

0201

R8040

TPS22924

5% MF

2

D

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

CSP A1 NOSTUFF VIN VOUT B1

A2 B2

61

IN

C8040

1

20% 6.3V X5R 0201-1

2

1.0UF

TPS22924C

Type

Load Switch

R(on) @ 1.8V

19.6 mOhm Typ 21.8 mOhm Max

Current

2A Max

CSP

VIN

VOUT

D2 ON

S4_PWR_EN

IN

2

3

4

NC

C8000 1 1.0UF

20% 6.3V X5R 2 0201-1

PP3V3_S4 EDP: 2.4A

NC

2

Part

TPS22934

Type

Load Switch

R(on) @ 3.6V

63 mOhm Typ 77 mOhm Max

Current

1A Max

18 29 34 37 38 42 63 64

Type

Load Switch

R(on) @ 3.6V

5.5 MOHM TYP 8.8 MOHM MAX

Current

4A MAX

C8071 1

30 15 61

IN

TDFN

2 ON

SSD_PWR_EN

CRITICAL

D

3

CSP

A1

VOUT

B1

S

5

IN

1

0

MF

R8011

0201

0612-SHORT

2

3

4

NC

PP3V3_S3 EDP: 1.02A

IN

9 ON

PCH_HSIO_PWR_EN

41 65

EDP: 5A Sense R on sensor page

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

CRITICAL

D

S S

2 3 5 7


Part

SLG5AP1453V

Type

Load Switch

C8005 1

U8005

10% 10V 2 X5R 402

R(on) @ 25C


Current

5.3A Max

C

8 11 65

EDP: 1.84A

GND 8

1UF

U8070

2

1/20W

1

TDFN

PP3V3_S0SW_SSD_FET

NOSTUFF P3V3S0_EN

OMIT

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

SLG5AP1471V D

8

2

5%

PP3V3_S3_FET_R

VDD

U8005

10% 6.3V CERM-X5R 0201

15

GND

1% 1W MF

TPS22924

PP1V05_S0

SLG5AP1453V 7 CAP

P3V3S0SW_SSD_FET_RAMP

0.002

VIN

PP5V_S0

0.1UF

R8070

B2

61 58 54 53 45 44 41 32 17 16 68 65

C8070

2

U8070

10% 10V X7R 201

A2

D

1

4700PF

PP3V3_S5

8 11 14 45 59 61 65

61 57 53 37 17 16 15 11 8 6 68 65

VDD

61 60

77 59 56 29 27 15 13 11 8 26 18 17 16 68 65 61 60

EDP: 167mA

PP3V3_S5 1

TPS22920

U8010

PP3V3_SUS

4

65 68

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

1

Part

3.3V S3 Switch

2

NC

U8020

1 B

U8000

GND 1 D

C

1


CRITICAL 61 27 26 18

0612-SHORT

PP3V3_S4_FET_R

NC

3.3V SSD Switch

0.002 1% 1W MF

A1 B1 C1

3

1.05V PCH HSIO Switch

OMIT

R8000

TPS22920 A2 B2 C2

1


1.0UF

20% 6.3V X5R 0201-1

0612-SHORT

PP3V3_SUS_FET_R

CRITICAL

C8020 1

Part

U8000

PP3V3_S5

B2 ON

P3V3SUS_EN

VOUT A1

GND

3.3V S4 Switch 77 59 56 29 27 15 13 11 8 26 18 17 16 68 65 61 60

IN

61

1% 1W MF

WCSP

A2 VIN

U8040

1 C

1

0.002

TPS22934

PP3V3_S5

GND

NOSTUFF

2

OMIT

U8020

EDP: 0.5A

CRITICAL C2 ON

P1V5S0SW_AUDIO_EN

3

R8020

U8040

1/20W

201

3.3V SUS Switch

1

10K

4

8 11 17 60

8 11 17 60

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

5% 1/20W

NOSTUFF

5

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e


R8042 PP1V5_S0

68 59 47 8 65 63 61

6

Part

SLG5AP1417V

Type

Load Switch

R(on) @ 4V Vgs

9.8 mOhm Typ TBD mOhm Max

Current

6A Max

15 18 19 39 42 65 68

NC

CRITICAL 61

IN

P3V3S3_EN

C2

ON

U8010

GND

C8010 1

1 C

Part

1.0UF

20% 6.3V X5R 2 0201-1

TPS22924C

Type

Load Switch

R(on) @ 2 .5 V

18.5 mOhm Typ 2 5. 8 m Oh m M ax

Current

2A Max

REMOVED THE ANALOG POWER GATE AS SLG5AP1471 SHOULD BE AVAILABLE BY THEN

B

B

3.3V S0 Switch 65 61 60 27 26 18 13 11 8 17 16 15 59 56 29 77 68

Sense R on sensor page

U8030

TPS22924

PP3V3_S5

CSP

A2 B2

VIN

PP3V3_S0_FET B1

U8030

CRITICAL 61 60

IN

P3V3S0_EN

C2

ON

C8030 1

41 65

EDP: 1A

A1

VOUT

GND

P ar t

TP S22 92 4C

1 C

Type

Load Switch

1.0UF

20% 6.3V X5R 2 0201-1

R(on) @ 2.5V


C ur re nt

2 A M ax

5V S0 Switch 66 65 63 62 57 56 55 46 33 32 68

PP5V_S4

3.3V Sensor Switch

1 1

A

U8050

TPS22934

PP3V3_S5

40 38 36

WCSP

A2 VIN IN

SMC_SENSOR_PWR_EN

B2 ON

PP3V3_S4SW_SNS_FET_R

VOUT A1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

5% 1/16W MF-LF 402

CRITICAL

2

PP3V3_S4SW_SNS

40 41 42 65

1 B

U8050

P5VS0_FET_RAMP

EDP: 50mA

C8081 1 4700PF

GND

C8050 1

0

1

2

U8080

R8050

10% 10V X7R 201

61

IN

P5VS0_EN

SLG5AP1443V TDFN

7

CAP

2

ON

CRITICAL GND

2

C8080 0.1UF

VDD 77 61 56 26 16 11 8 15 13 18 17 29 27 60 59 68 65

D

3

S

5

10% 16V X5R-CERM 0201

Power FETs DRAWING NUMBER

U8080

8


PAGE TITLE 41 65

EDP: 1.1A

Apple Inc.

D

TPS22934

Part

SLG5AP1443V

Type

Load Switch

Type

Load Switch


BRANCH

R(on) @ 3.6V


R(on)



PAGE

R

SIZE

REVISION

Part

1.0UF

20% 6.3V X5R 2 0201-1

A

SYNC_MASTER=J44

PP5V_S0_FET

80 OF 120

8

7

6

5

4

3

2

S5 Enables

S3 Enables

PLACE_NEAR=U7501.21:7mm 56 37 36 61

OUT

SMC_PM_G2_EN

56 37 36 61

IN

SMC_PM_G2_EN

100

1

2

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

S5_PWR_EN

61 56

S5_PWR_EN

PP3V3_S5

201

10% 6.3V CERM-X5R 0201

0.47UF 10% 6.3V CERM-X5R 402

2

2

IN

PM_SLP_S5_L

U8170

61 52 51 45 34 33 30 17 39 38 37 36 68 65

37 36

IN

SMC_S4_WAKESRC_EN

S4_PWR_EN

NC

5

OUT

18 26 27 60 61

S4_PWR_EN

OUT

18 26 27 60 61

NO STUFF

1

OUT

MAKE_BASE=TRUE

36 56 61

2

61 33

SSD_PWR_EN

55 61

D

10% 6.3V CERM-X5R 402

2

C8113 0.47UF

PLACE_NEAR=U8010.C2:6mm

10% 6.3V CERM-X5R 402


R8117 5% 1/20W MF 201

USB_PWR_EN

USB_PWR_EN

OUT

MAKE_BASE=TRUE

SSD_PWR_EN

OUT

MAKE_BASE=TRUE

1

0

1

P5VS4RS3_EN_RC

2

5% 1/20W MF 0201

15 30 60 61

33 61

NO STUFF

R8179 PM_SLP_S4_L

63 61 36 29 18 13

IN

1


SSD Enable 61 60 30 15

60 61

OUT

100

MF

S5_PWRGD

34

OUT

DDRREG_EN

NO STUFF

C8112 0.47UF

2


0201

SMC-->PM_DSW_PWRGD

2

1

20% 10V CERM 402

2

2

1/20W

S5_PWRGD-->SMC

MF

C8111

1

5%

5%

1/20W

S5_PWRGD

OUT

P3V3S3_EN

DDRREG_EN MAKE_BASE=TRUE

0.1UF

0

1

100K

201

S4_PWR_EN

R8115

R8141 1

TPAD_VBUS_EN

P3V3S3_EN

18 26 27 60 61

3

NC


5% 1/20W MF 201


61 55

MAKE_BASE=TRUE

1

PP3V42_G3H

61 56 36


MAKE_BASE=TRUE

OUT

SOT891

4

S5 Power Good

2

61 60

S4_PWR_EN

74LVC1G32

2

R8113 3.3K

5% 1/20W MF 0201

2

NOSTUFF 6

36 13

1

R8112 0

5% 1/20W MF 201


2

BYPASS=U8170.6:2.3mm


1

R8111 20K

0.1UF

C8142

D

1

C8170 1

NOSTUFF 1

PM_SLP_S4_L

Standby Enables

NOSTUFF

56 61

OUT

MAKE_BASE=TRUE

5% 1/20W

MF

IN

63 61 36 29 18 13

R8140

MAKE_BASE=TRUE

1

NO STUFF

1

D8175

0

5% 1/20W MF 0201

NO STUFF

2

R8176

P5VS4RS3_EN_D

1

5V needs to be held up so 1.05V can fall after 1.5V

240

10% 6.3V CERM-X5R 402

PM_SUS_EN

PM_SL P_S5 _L

Run(S0)

State

X

SMC_ADAPTER_EN

1

1

1

1

1

1

Sleep(S3AC)

1

1

1

1

1

1

0

Sleep(S3)

0

1

1

1

1

1

0

DeepSleep (S4AC)

1

1

1

0

0

0

0

DeepSlee p(S4)

0

1

1

0

0

0

DeepSleep (S5AC)

1

1

0

0

0

0

DeepSlee p(S5)

0

1

0

0

0

0

0

Battery Off (G3HotAC)

toggle 3Hz

0

0

0

0

0

0

Battery Off (G3Hot)

1

0

0

0

0

0

0


P5VS4RS3_EN NO STUFF

OUT

56

C8175

1


SMC_P M _ G 2E _N A B L E

SMC_S 4_WAK E S R CE _N

PM_S LP_S4 _L

PM_SLP_S3_L


2

5% 1/20W MF 201

C

2

R8175

SM-201

RB521ZS-30 K

Mobile System Power State Table

0.47UF


A

C8114

0 0

C

2.2UF 10% 6.3V X5R 402

2

29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP3V3_S5


BYPASS=U8180.6:3mm

1

C8180 0.1UF

S0 Rail PGOOD (BJT Version) 68 63 36 18 17 13 61 65 68 16 17 32 41 44 45 53 54 58 60 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

PP5V_S0 1

R8151

R8152

1

1K 5%

10% 10V X5R 402

2

S0PGD_C

ALL_SYS_PWRGD

PM_SLP_S3_BUF_L MAKE_BASE=TRUE NOSTUFF NO STUFF A

1

2

16 17 36 61

6

5

R8158

1

NC NC

MF

201

AUD_PWR_EN

IN

1

NOSTUFF K

100K

MF

1K 1%

1/20W

RB521ZS-30

OUT

VMON_3V3_DIV

SM-201

K

2

5% 1/20W MF 201


A

R8187 0

2

5% 1/20W MF 0201

D8183


P1V5S0_EN_D

A 61 59

RB521ZS-30

61 60

P5VS0_EN

61 60

P3V3S0_EN

P1V5S0_EN

P1V5S0_EN

OUT

59 61

P5VS0_EN

OUT

60 61

P3V3S0_EN

OUT

60 61

P1V05S0_EN OUT

57 61

MAKE_BASE=TRUE


MAKE_BASE=TRUE


NOSTUFF 1


SM-201

K


MAKE_BASE=TRUE

RB521ZS-30

5% 1/20W MF 2 201


60

2

0.1UF 10% 25V X5R 402

C8186

1

0.1UF

10% 10V CERM 402

2

20% 10V CERM 402


P1V05S0_EN MAKE_BASE=TRUE

NO STUFF 1

C8185 0.22UF

C8146

C8187

1

0.68UF 2

C8188 0.1UF

10% 6.3V CERM 402

2

20% 10V CERM 402

B




3.3V SUS Detect


29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

3

PP3V3_S5

S0PGD_BJT_GND_R

PP1V5_S0

68 65 63 61 60 59 47 8

1K

1

2

100

5% MF

201

MF

201

PM_SLP_S3_BUF_L

61 46 27 26

0.1UF

CRITICAL

2 1

65 61 60 59 45 14 11 8

5%

PP3V3_SUS

2

SENSE

3

CT

MF

R8169

S0 Rail PGOOD Circuitry

IN

1

P1V5S0_PGOOD

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP1V05_S0

56

S0PGOOD_ISL

IN

P5VS4RS3_PGOOD

1

PP1V5_S0

10% 6.3V CERM-X5R 0201

1

R8160

1

2

1% 1/20W MF 201

R8170

1

15K

6.04K 3.19V @ 4.5Vmin

S0PGOOD_ISL

2

1% 1/20W MF 201

R8172

0.718V @ 1.45Vmin S0PGOOD_ISL 1

R8161

S0PGOOD_ISL 1

15K

0.723V @ 1.02Vmin

2

1% 1/20W MF 201

R8171 15K

2

1% 1/20W MF 201

R8173 15K

2

1% 1/20W MF 201

2

57

IN

P1V05S0_PGOOD

TDFN

55

IN

DDRREG_PGOOD

3

V2MON

5

V3MON

6

V4MON

CRITICAL

(IPU)

MR*

1

NC

RST*

8

ALL_SYS_PWRGD_R

GND THRM_PAD 4

9

4

TP_SUS_PGOOD_MR_L

R8131 1 330K

OUT

THRM PAD

MR*

VFRQ Low: Fix Frequency

Q8131

7

S0PGOOD_ISL

R8162 1

330

2

100

1/20W

61 40 13

MF

201

IN

PM_SLP_SUS_L

PM_SLP_SUS_L

MAKE_BASE=TRUE 1

G

PM_SLP_S3_R_L

OUT

13 40 61

1/20W

MF

201 2

OUT

16 17 36 61

61 60

MAKE_BASE=TRUE

NO STUFF 1

C8190 0.1UF

2

10% 25V X5R


Power Control

5% 1/20W MF 0201

P3V3SUS_EN

A


R8190 0

5% 201

2

52

SUS Enables

2

5%

ALL_SYS_PWRGD

S

OUT

SYM_VER_2

1/20W

MF

3

DFN1006H4-3

1

2

CHGR_VFRQ

D

DMN32D2LFB4

R8164 100

2

VFRQ High: Variable Frequency

61

1

1

5% 1/20W MF 201

13 72

10% 16V X7R-CERM 0201

5%

353S2310

PP3V42_G3H

201

PM_RSMRST_L

2

R8168

ISL88042IRTEZ

1/20W

6

MF

VDD

U8160

1% 1/20W MF 201

S0PGOOD_ISL 1

7

51 45 39 38 37 36 34 33 30 17 68 65 61 52

MF

RESET*

QFN

5

1000PF

201

2

S0PGOOD_ISL

6.04K

2

P5V_DIV_VMON P1V5_DIV_VMON P1V05_DIV_VMON

1.5V Divider:

2

5%

2

U8130 GND

C8131

CHGR VFRQ Generation

100K

1/20W

0.1UF

5V Divider:

1

100

8 11 14 45 59 60 61 65

R8133

5%

C8160 1 S0PGOOD_ISL

NO STUFF

2

R8165

PP3V3_S0

PP5V_S0

S0PGOOD_ISL

SUS_PGOOD_CT

201

5% 1/20W MF 201

(ISL version used for development)

60 57 53 37 17 16 15 11 8 6 68 65

100

2

1

1 2

TPS3808G33

1/20W

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

10% 6.3V CERM-X5R 0201

VDD

R8167 10K

PP3V3_SUS

C8130 1

U8130 Sense input threhold is 3.07V

5%

1/20W

Vbe 0.7V max @ 2mA Vce(sat) 0.1V max @ 1mA Q1 Vth 0.7~1V @Id 250uA

BYPASS=U8130.6:2.3mm

No stuff C8131, 12ms Min delay time

R8157 1 VMON_Q4_BASE

1/20W

1.05V Divider:

D8184

NO STUFF

2

R8155

A

P3V3S0_EN_D

1

2

MF

R8159

68 65 63 61 60 59 47 8 68 60 58 45 44 17 16 41 32 54 53 65 61

R8186 39K

5% 1/20W MF 201

2

26 27 46 61

R8188 68K

5% 1/20W MF 2 201

61 57

201


7.15K

R8184 330

5% 1/20W MF 0201

2

R8146 1

Q4

1% 1/20W MF 2 201

820

1

R8185

1

NOSTUFF

1/20W

201 SM-201 A P1V5CODEC_EN_D

376S0854

Q3

2 1

P1V05_EN_D

2

1

PLACE_NEAR=U7600.16:6mm PLACE_NEAR=U8030.C2:6mm

5% 1/20W MF 201

P1V5S0SW_AUDIO_EN

2

1%

D8146

DFN2015H4-8

8 7

VMON_Q3_BASE

2

5% 1/20W

1% 1/20W MF 201

13

Q1 ASMCC0179

Q2

R8138

R8145

CRITICAL

1K

NO STUFF

NOSTUFF

Q8150

R8154



9ms RC delay

62 64 65 68 77 37 38 39 40 41 8 11 12 13 15 17 18 24 28 30 42 43 44 46 47 50 61

K

1

0

SM-201

RB521ZS-30

5% 1/20W MF 201

1

R8183 330

1

D8185

R8180

1.5V Codec Enable(BYPASSED NOW)

4

PM_SLP_S3_BUF_L OUT 1

4 46 27 61 26

3

MF

1UF

1% 1/20W MF 201

S0 Enables

SC70-HF

U8180

330K

2

3.3V Divider: 1.07V 1

2

10% 6.3V CERM-X5R 0201

MC74VHC1G08

1

MF

201

15K

2

P M_ SL P_ S3 _R _L

1%

201

VMON_Q2_BASE

1

5

2 61

1/20W

2

1/20W

C8159 1

PP3V3_S0

B

100

5% 1/20W MF 201

150K

R8153 VMON_5V_DIV

15K

2

1

R8156 1

1% 1/20W MF 201

5.0V Divider: 1.07V 1

P M_ SL P_ S3 _L

IN

PP3V3_S5

54.9K

2

2

R8178

DRAWING NUMBER

P3V3SUS_EN

OUT

Apple Inc.

60 61

R

REVISION


BRANCH


PAGE

81 OF 120

SIZE

D

8

7

6

5

4

3

2

1

LCD PANEL INTERFACE (eDP) NEEDS FINAL CHECK AGAINST UPDATE FOR NEW PANEL PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

C8330 1 0.1UF

8

VCC

D

LCD_PSR_EN

15

5 6

EDP_PANEL_PWR

13

SOT833 A Y B

1 2

EDP_BKLT_PSR_EN

7

Y = B 3

EDP_PANEL_PWR_OR_PSR_EN

GND 4

R8330 1 R8331 1

0 2

0 2

58

R83101

R83091

5% 1/16W MF-LF 4022

5% 1/16W MF-LF 4022

100K

NO STUFF 5%

1/20W

MF

1

R8340

62 68

100K

5% 1/16W MF-LF 4022

100K

5%

1/20W

OUT

0.1UF

1

74 5

BI

EDP_PANEL_PWR_OR_PSR_EN DP_INT_AUXCH_C_P

74 5

BI

DP_INT_AUXCH_C_N

74 5

IN

DP_INT_ML_C_P<0>

IN

DP_INT_ML_C_N<0>

74 5

IN

DP_INT_ML_C_P<1>

C8322 1

74 5

IN

DP_INT_ML_C_N<1>

C8323 1

74 5

IN

DP_INT_ML_C_P<2>

C8324 1

74 5

IN

DP_INT_ML_C_N<2>

C8325 1

68 62

10% 10V 2 X7R 201

10% 16V X7R-CERM 2 0402

SLG5AP1443V

Type

Load Switch

R(on)


Current

C8321 1 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

74 5

IN

DP_INT_ML_C_P<3>

C8326

74 5

IN

DP_INT_ML_C_N<3>

C8327 1

1

0.1UF

CAP

2

ON

TDFN

CRITICAL

3

S

5

C8328 1 C8329 1

0.1UF

EDP: 1 A

PP5VR3V3_SW_LCD_ISNS MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

2 0201 10% 16V X5R-CERM 2 0201 10% 16V X5R-CERM

+/-0.1PF COH 25V 2 0201

NC

I2C_BKLT_SCL I2C_BKLT_SDA LCD_IRQ_L 68 15 SMBUS_SMC_0_S0_SCL 39 36 76 SMBUS_SMC_0_S0_SDA 39 36 76 EDP_BKLT_PWM 68 13 68 62 LCD_HPD_CONN

1


C8311 0.1UF

10% 2 16V X7R-CERM 0402

1

74 68 62 74 68 62

2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM 2 16V 0201 10% X5R-CERM

R8320 0 1 W MF 0612-SHORT

1 3

2 4

OMIT Short Rsense

20% 2 6.3V X5R 603

ISNS_LCDPANEL_N ISNS_LCDPANEL_P

DP_INT_ML_P<0>

74 68 62

DP_INT_ML_N<0>

74 68 62

DP_INT_ML_P<1>

74 68 62

DP_INT_ML_N<1>

74 68 62

DP_INT_ML_P<2>

74 68 62

DP_INT_ML_N<2>

74 68 62

DP_INT_ML_P<3>

74 68 62

DP_INT_ML_N<3>

EDP_LS_CAP EDP_LS_CAP

1

C8356 9.1PF

+/-0.1PF COH 25V 2 0201

1

C8357 9.1PF

+/-0.1PF COH 25V 2 0201

EDP_LS_CAP

1

C8358 9.1PF

+/-0.1PF COH 25V 2 0201

EDP_LS_CAP

1

C8359 9.1PF

+/-0.1PF COH 25V 2 0201

D

1

2

C8302 1

10% 16V X5R-CERM 2 0201

10% 16V X5R-CERM 2 0201

OUT OUT

68

PP5VR3V3_SW_LCD


0805

C8301 1

0.1UF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

C

33 34 35 36 37 38 39 40 41

L8300

0.1UF

10UF

74 68 62

CRITICAL


C8312

DP_INT_AUX_P DP_INT_AUX_N

FERR-220-OHM

PP5VR3V3_SW_LCD_UF

32

C8303 1

C8300 1

10% 100V X7R-CERM 2 0603

10% 100V X7R-CERM 2 0603

1000PF

B

518S0829

1000PF

42 77 42 77


R8311 74 68 62 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

2.5A

1

R8303

LCD Panel HPD & AUX strapping LCD_HPD_CONN

74 68 62

DP_INT_AUX_N

74 68 62

DP_INT_AUX_P

1M

2 NO_XNET_CONNECTION=TRUE

R8312

DP_INT_ML_N<0>

DP_INT_ML_P<1>

1M

1

2

5% 1/20W MF 201 74 68 62


R8314

DP_INT_ML_N<1>

1


R8301 1M

5% 1/20W MF 2201

74 68 62

DP_INT_ML_P<2>

74 68 62

DP_INT_ML_N<2>

1

1

R8302 1M

5% 1/20W MF 2 201

1M

2

5% 1/20W MF 201


R8315 1

2

5% 1/20W MF 201

R8313 74 68 62

1M

1


1M

5% 1/20W MF 2 201

1

5% 1/20W MF 201


68 62

DP_INT_ML_P<0>

PP3V3_S0 74 68 62

A

9.1PF

PPVOUT_S0_LCDBKLT

68 58

0

D

U8300 Part

C8355

F-RT-SM

8

10% 6.3V 2 CERM 402

EDP_LS_CAP

1

J8300

0.1UF

C8320 1 0.1UF

GND

4700PF

+/-0.1PF COH 25V 2 0201

CRITICAL

0.1UF

SLG5AP1443V 7

5% 1/20W MF 201

C8310 1

9.1PF

+/-0.1PF COH 25V 2 0201

20525-130E-01

68

VDD

1UF

C8354

1

9.1PF

C 6

68

U8300

C8319 1

C8353

GND 2

DP_INT_HPD

0.1UF

B

1

B 1

0201

C8309 1

2 EDP_PANEL_PWR_EN_RC

EDP_LS_CAP

EDP_LS_CAP

BYPASS=U8340.5:3MM

PP5V_S4

EDP_PANEL_PWR_OR_PSR_EN 1

+/-0.1PF COH 25V 2 0201

68 66 58

74 5

68 62

C8352 9.1PF

+/-0.1PF COH 25V 2 0201

LCD_HPD_CONN IS A 2.5V SIGNAL NEEDS TO BE LEVEL SHIFTED TO 3.3V

0201

C

1K

1

9.1PF

68 66 58

MF

PP5V_S0_LCD_FETCAP

EDP_LS_CAP

C8351

A 3

C8340

10% 16V 2 X5R-CERM 0201

EDP_LS_CAP

1

31

PANEL USES EDP_PANEL_PWR_PSR_EN TO DISCHARGE THE LCD BEFORE POWER GOES AWAY

R8319

+/-0.1PF COH 25V 2 0201

NO STUFF

13

63 60 57 56 55 46 33 32 68 66 65

1

C8350 9.1PF

SOT891 5 VCC 4 Y

74LVC2G32GT A Y B

1

CRITICAL

U8340 74AUP1T97

NOSTUFF

U8330

EDP_BKLT_EN

13

EDP_LS_CAP

10% 6.3V CERM-X5R 2 0201 BYPASS=U8330.8:3MM

1M

2 5% 1/20W NO_XNET_CONNECTION=TRUE MF 201

R8316 1

R8317 DP_INT_ML_P<3>

1

1M

5% 1/20W MF 201 74 68 62

DP_INT_ML_N<3>

2

5% 1/20W MF 201


74 68 62

1M

A

SYNC_MASTER=J44


PAGE TITLE

eDP Display Connector DRAWING NUMBER

Apple Inc. R

2 TRUE

R8318 1

1M

2

SIZE

D

REVISION


BRANCH


PAGE

83 OF 120

8

7

6

5

4

3

2

1

RIO Power Connector PLACE_NEAR=J9510.1:2.54MM

518S0882

C9533 1 2

PCIE_AP_R2D_C_P

0.1UF

10% 16V X7R-CERM 0402 70 68 63

OUT

PCIE_AP_R2D_P

70 68 63

OUT

PCIE_AP_R2D_N

IN

J9500

14 68 70

504050-0491 M-RT-SM

5

1 10%

2 0.1UF 16V

PCIE_AP_R2D_C_N

1 IN

14 68 70

2

C9532 X7R-CERM

D

65 64 60 42 38 37 34 29 18 68

0402

65 62 60 57 56 55 46 33 32 68 66

PP3V3_S4 PP5V_S4

4 PLACE_NEAR=J9500.2:2.5MM

1

C9591

1

0.1UF

70 68 63 14

IN

70 68 63 14

IN

PCIE_AP_D2R_P PCIE_AP_D2R_N

OUT

6

C9592 0.1UF

10% 16V 2 X5R-CERM 0201

OUT

D

3


10% 16V 2 X5R-CERM 0201

CRITICAL


L9501


70 63

70 63

OUT

PCIE_CLK100M_AP_CONN_P

1

4

PCIE_CLK100M_AP_P

IN

12 68 70

OUT

PCIE_CLK100M_AP_CONN_N

2

3

PCIE_CLK100M_AP_N

IN

12 68 70

64 63

IN

HDMI_HPD

R9530

1

300K


5% 1/20W MF 2 201

68 65 63 61 60 59 47 8

C

PP1V5_S0

PP1V5_S0

C


RIO FLEX CONNECTOR

1

C9593 0.1UF

10% 16V 2 X5R-CERM 0201

J9510

DF40BG-70DP-0.4V M-ST-SM

516S1059 CRITICAL

74 68 64 63

OUT

74 68 64 63

OUT

63

OUT

63

OUT

74 68 64 63

B

74 68 64 63

OUT

63

OUT

63

OUT

71 63 29

BI

71 63 29

BI

71 68 14

OUT

71 68 14

OUT

64 63

71 68 14 71 68 14

A

OUT

IN

IN IN

71 14

BI

71 14

BI

70 68 63 14

IN

70 68 63 14

IN

70 63

OUT

70 63

OUT

HDMI_IG_CLK_C_N HDMI_IG_CLK_C_P =HDMI_DATA_C_N<0> =HDMI_DATA_C_P<0>

GND_VOID=TRUE GND_VOID=TRUE

HDMI_IG_DATA_C_N<1>GND_VOID=TRUE HDMI_IG_DATA_C_P<1>GND_VOID=TRUE =HDMI_DATA_C_N<2> =HDMI_DATA_C_P<2>


USB_BT_CONN_P USB_BT_CONN_N USB3_EXTB_R2D_C_P GND_VOID=TRUE USB3_EXTB_R2D_C_N GND_VOID=TRUE (USB3_EXTB_R2D caps on RIO) HDMI_HPD

USB3_EXTB_D2R_P USB3_EXTB_D2R_N


USB_EXTB_N USB_EXTB_P

PCIE_AP_D2R_N PCIE_AP_D2R_P


PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N

73

74

69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

71

72

1 TP 1 TP

PM_SLP_S3_L PM_SLP_S4_L XDP_USB_EXTB_OC_L AP_RESET_L SD_RESET_L

OUT

13 17 18 36 61 68

OUT

13 18 29 36 61

IN

1 TP 1 TP 1 TP 1 TP

14 16

OUT

15

OUT

15

1 TP 1 TP

BP9500 BEAD-PROBE BP9501 BEAD-PROBE BP9502 BEAD-PROBE BP9503 BEAD-PROBE BP9504 BEAD-PROBE BP9505 BEAD-PROBE BP9506 BEAD-PROBE BP9507 BEAD-PROBE

SM SM SM SM SM SM SM SM

MAKE BASE SMBUS_PCH_CLK SMBUS_PCH_DATA SMC_WIFI_PWR_EN HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

PP1V5_S0

OUT BI

14 16 19 39 63 68 72

36 38

OUT

63 64

BI

63

OUT

63

OUT

74 68 64 63

OUT

14 16 19 39 63 68 72

OUT

63 64 74 68 64 63

OUT

63

OUT

8 47 59 60 61 63 65 68

SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA WIFI_EVENT_L SD_PWR_EN SDCONN_STATE_CHANGE_RIO

AP_PCIE_WAKE_L AP_CLKREQ_L

OUT BI

36 39 43 63 76 36 39 43 63 76

63

OUT

74 68 64 63

OUT

74 68 64 63

OUT

OUT

36

OUT

15

71 63 29

BI

18 63

71 63 29

BI

IN

IN

29 63 72

IN

12

IN

14 63 68 71

IN

14 63 68 71

=HDMI_DATA_C_P<2> =HDMI_DATA_C_N<2>

TRUE TRUE

HDMI_IG_DATA_C_P<2> HDMI_IG_DATA_C_N<2>

IN

64 68 74

IN

64 68 74


TRUE TRUE


IN

63 64 68 74

IN

63 64 68 74

=HDMI_DATA_C_P<0> =HDMI_DATA_C_N<0>

TRUE TRUE


IN

64 68 74

IN

64 68 74

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N

TRUE TRUE


IN

63 64 68 74

IN

63 64 68 74

USB_BT_CONN_P USB_BT_CONN_N

TRUE TRUE

USB_BT_CONN_P USB_BT_CONN_N

BI

TRUE TRUE


IN

63 70

IN

63 70

14 16 19 39 63 68 72

BI

70 63

OUT

70 63

OUT


72 68 63 39 19 16 14

OUT

SMBUS_PCH_CLK

SMBUS_PCH_CLK

IN

SMBUS_PCH_DATA

SMBUS_PCH_DATA

BI

B

29 63 71 29 63 71

MAKE BASE FOR I2C IS ON I2C PAGE GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N

USB3RPCIE_SD_R2D_C_P OUT USB3RPCIE_SD_R2D_C_N OUT PCIE_AP_R2D_N PCIE_AP_R2D_P

72 68 63 39 19 16 14

OUT

63 68 70

OUT

63 68 70

TRUE TRUE

OUT

64 63

BI

HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA

OUT

SMBUS_SMC_3_SCL

76 63 43 39 36

BI

SMBUS_SMC_3_SDA

63 18

IN


TRUE


OUT

18 63

71 68 63 14

IN

TRUE TRUE


14 63 68 71

IN


OUT

71 68 63 14

OUT

14 63 68 71

USB3RPCIE_SD_R2D_C_P USB3RPCIE_SD_R2D_C_N

TRUE TRUE

76 63 43 39 36

71 63 14

NOTE: This connector is shielded 70P Hirose Plug APN 516S1059, mates with APN 516S1058.

OUT OUT

72 63 29

IN


IN

SMBUS_SMC_3_SCL

IN

14 16 19 39 63 68 72

64 63

14 63 71 14 63 71

BI

BI

63 64 63 64

36 39 43 63 76

MAKE BASE FOR I2C IS ON I2C PAGE

AP_PCIE_WAKE_L

SMBUS_SMC_3_SDA

TRUE

USB3RPCIE_SD_R2D_C_P USB3RPCIE_SD_R2D_C_N AP_PCIE_WAKE_L

BI

36 39 43 63 76

PAGE TITLE

IN

14 63 71

IN

14 63 71

OUT

SYNC_MASTER=J44

29 63 72

A


RIO Connector DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

95 OF 120

8

7

6

5

4

3

2

1

DISPLAY MUX: DP OR HDMI

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

D

PP3V3_S0

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

1

0.1UF

DP 1:2 ANALOG DEMUX

20% 10V 2 X7R-CERM 0402

2 4 A J

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

OUT

74 23

BI

74 23

BI

TOWARDS PORTS

C

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

74 68 63

OUT

A5 B6 A6 A8

DP_TBTSNK1_ML_C_P<3> DP_TBTSNK1_ML_C_N<3>

A9

64 28

OUT

64 28

BI

OUT

64 63

BI

PP3V3_S0

64 63

DDCCLK_A DDCDAT_A

J2

HPDA

B8

DB0(P) DB0(N)


D8

B9

D9


E8


F8

E9

F9

HDMI_IG_DDC_CLK HDMI_IG_DDC_DATA HDMI_HPD

IN

1

DISP_MUX_EN

64

100K 5% 1/20W MF 201

J8

DP_TBTSNK1_HPD

DISP_MUX_SEL_L

R9753

H8


NC NC

47 46 44 43 42 41 18 17 15 13 12 11 8 40 39 38 37 30 28 24 77 68 65 64 62 61 50

DA3(P) DA3(N)

DISP MUX SEL_L SEL_L 0 = DP SEL_L 1 = HDMI

2

DB1(P) DB1(N) DB2(P) DB2(N) DB3(P) DB3(N)

J5 H3

HPDB

A1 B7

D X_ SE L OE

5% 1/20W MF 2 201

PP3V3_S0

SYM_VER_2

23 15 66 64

R9755

DC0(P) B2 DC0(N) B1

DP_HDMI_TBT_ML_P<0> DP_HDMI_TBT_ML_N<0>

IN

66 74

IN

66 74

DC1(P) D2 DC1(N) D1


IN

66 74

IN

66 74

1

64 63

BI


5 M+ 4 M-


7 D+ 6 D-

2

64 28

BI

64 28

BI

NO STUFF

Y+ 1

U9725

Y- 2

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA

IN

66 74

IN

66 74

DC3(P) F2 DC3(N) F1


IN

66 74

IN

66 74

SEL 10

OE*

HDMITBTMUX_SEL_TBT

3

S 2

C

BI

13 66 74

BI

13 66 74

DISP_MUX_EN 77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

C9700 1 0.1UF

HPDC J1

DPMUX_HPD_OUT

OUT

10% 6.3V CERM-X5R 2 0201

13 66

OMIT_TABLE 1 DDCCLK_C J3 DDCDAT_C J7 A UX _S EL C2

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_AUX_DDC_SEL

IN BI

R9752 100K

13 64 66 13 64 66

2

64

U9700

5% 1/20W MF 201

SLG4APXXX TDFN

D D D D D D N N N N N N G G G G G G 3 8 8 4 7 2 B C G H H G

64 23

64 63

DP_TBTSNK1_HPD HDMI_HPD HDMITBTMUX_LATCH

1 VDD

IO_8 8

DISP_MUX_EN

2 IO_2

IO_7 7

HDMITBTMUX_SEL_TBT

3 IO_3

IO_6 6

4 IO_4

GND 5

68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30 77

5% 1/20W MF 201

1

B

64 63

HDMI_HPD

64 23

DP_TBTSNK1_HPD

NC 64

DISP_MUX_PRIORITY

1 2 3 4 5 6

VDD GPI(2) GPIO(3) GPIO(4) GPIO(5) GPIO(6)

GPIO(12) GPIO(11) GPIO(10) GPIO(9) GPIO(8) GND

THRM_PAD 1

510K

2

QTY

343S0666

1

DESCRIPTION IC, SAK,AP4179,DP MUX CTRLR,TDFN-8

REFERENCE DES

CRITICAL

U9700

CRITICAL

BOM OPTION

5% 1/20W MF 201

1

2

TDFN

DPMUX_AUX_DDC_SEL 64

5% 1/20W MF 201

PART NUMBER

100K

SLG46400V

2

R9704

R9754

NOSTUFF CRITICAL

U9775

A 5% 1/20W MF 201

15 64

PP3V3_S0

C9775 1

R9703

2

100K

15 23 64 66

9

510K

1

HDMITBTMUX_FLAG_L

THRM PAD

NOTE: HDMI ML SWIZZLED INTENTIONALLY AS PER TABLE 9-1 HASWELL-ULT PDG

DISP_MUX_PRIORITY 64

R9702

64

S 2

PP3V3_S0

1

15 23 64 66

SYM_VER_2

0.1UF

5% 1/20W MF 201

TOWARDS CPU

DISP MUX SEL SEL 0 = HDMI SEL 1 = DP

SIGNAL_MODEL=MOJO_MUX

D 3

DFN1006H4-3

1 G

77 68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30

100K

13 64 66

TOWARDS CPU

10% 6.3V CERM-X5R 2 0201

R9701

13 64 66

BI

CRITICAL

GND

64

DP_HDMI_TBT_AUX_P DP_HDMI_TBT_AUX_N

BI

TQFN

DMN32D2LFB4 DP_HDMI_TBT_ML_P<2> DP_HDMI_TBT_ML_N<2>

AUXC(P) H2 AUXC(N) H1

8

NO STUFF

Q9701

DC2(P) E2 DC2(N) E1

PP3V3_S4

NOSTUFF

5% 1/20W MF 2 201

PI3USB102ZLE

100K 5% 1/20W MF 201

BI

DISP_MUX_EN_L

68 65 63 60 42 38 37 34 29 18

PP3V3_S0

10K

5% 1/20W MF 2201

9

NO STUFF

HDMITBTMUX_SEL_TBT

68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30 77

R9727

10K

D 3

DFN1006H4-3

1 G

1

R9726

VCC

CRITICAL

64 63

DMN32D2LFB4

B

1

TOWARDS PORTS 68 65 64 62 61 50 47 46 28 24 18 17 15 13 12 11 8 44 43 42 41 40 39 38 37 30 77

BGA

66 64 13

Q9700

10K

20% 16V X6S-CERM 2 0201

AUXB(N) DDCCLK_B DDCDAT_B

R9725

0.1UF

20% 10V 2 X7R-CERM 0402

H6 AUXB(P) J6 H5

NO STUFF 1

C9725 1

0.1UF

HD3SS213ZQE

DA2(P) DA2(N)

D

PP3V3_S0

C9751

U9750

AUXA(N)


IN

64 63

DA1(P) DA1(N)

1

D D D D V V

DA0(P) DA0(N)

H9 AUXA(P) J9

DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N

OUT

74 68 63

B5


64 23

74 68 63

A4


OUT

74 23

B4


C9750

66 64 13

HDMITBTMUX_LATCH

3 1

12 11 10 9 8 7

NC NC

HDMITBTMUX_FLAG_L

15 64

DISP_MUX_EN 64 HDMITBTMUX_SEL_TBT 15

23 64 66

DISP MUX SEL SEL 0 = HDMI SEL 1 = DP

A

SYNC_MASTER=J44


PAGE TITLE

Display Mux: HDMI vs DP DRAWING NUMBER

Apple Inc.

2 R

PRIORITY 0 = HDMI WINS OVER DP PRIORITY 1 = DP WINS OVER HDMI

AUX_SEL 0 = AUX ONLY AUX_SEL 1 = DDC ONLY AUX_SEL Vdd/2 = AUX & DDC

SIZE

D

REVISION


BRANCH


PAGE

97 OF 120

8

7

6

"G3Hot" (Always-Present) Rails

PPBUS_G3H

68 51 40 25 65 58 52

PPBUS_G3H


PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H 54 53 40 65 57 55


D

65 56 40

PPBUS_S5_HS_OTHER5V


25 40 51 52 58 65 68 25 40 51 52 58 65 68 25 40 51 52 58 65 68 25 40 51 52 58 65 68


40 53 54 55 57 65

PPBUS_S5_HS_OTHER5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=8.6V MAKE_BASE=TRUE

4

40 53 54 55 57 65 40 53 54 55 57 65 40 53 54 55 57 65

40 56 65

40 56 65

PP3V3_S5

MIN_LINE_WIDTH=0.2 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

65 64 63 60 42 38 37 34 29 18 68

PPDCIN_G3H_ISOL

PPDCIN_G3H_ISOL PPDCIN_G3H_ISOL

C

52 51 68 65

PPDCIN_G3H

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE

PPDCIN_G3H 68 51 37 30 34 39 61

65 45 36 17 33 38 52

PP3V42_G3H

PP3V42_G3H


PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H

13 12 8 65 17

PPVRTC_G3H

B

PPVRTC_G3H

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE

PPVRTC_G3H

5V Rails 68 65 56 34

PP5V_S5

PP5V_S5


PP5V_S5 57 56 55 46 33 32 68 66 65 63 62 60

57 56 55 46 33 32 68 66 65 63 62 60

68 45 44 41 32 17 16 65 61 60 58 54 53

A

PP5V_S4

PP5V_S4

PP5V_S0

PP5V_S4


PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S4 PP5V_S0

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

8 11 13 15 16 17 18 26 59 60 61 65 68 77

27 29 56

27 29 56 65 41 30 27 29 56

59 60 61 65 68 77 59 60 61 65 68 77

8 11 13 15 16 17 18 26

27 29 56

8 11 13 15 16 17 18 26

27 29 56

59 60 61 65 68 77 59 60 61 65 68 77

8 11 13 15 16 17 18 26 27

PP3V3_S0SW_SSD_FET

59 60 61 65 68 77


18 29 34 37 38 42 60

63 64 65

18 29 34 37 38 42 60 68

63 64 65

18 29 34 37 38 42 60 68

63 64 65

18 29 34 37 38 42 60 68

63 64 65

18 29 34 37 38 42 60 68

63 64 65

VOLTAGE=3.3V 68 MAKE_BASE=TRUE

PP3V3_S0SW_SSD

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM

40 41 42 60 65 40 41 42 60 65

PP3V3_S0SW_SSD


PP3V3_SUS

51 52 65 68

51 52 65 68

17 30 33 34 36 37 38 39 52 61 65 68

73 65 55 41 22 21 20 19 17 8 11 14 45 59 60 61 65

PP3V3_S3

30 41 65

PP3V3_S4_TBT

23 24 25 42 65

PP3V3_S4_TBT

23 24 25 42 65

8 11 14 45 59 60 61 65 8 11 14 45 59 60 61 65 8 11 14 45 59 60 61 65 8 11 14 45 59 60 61 65

73 68 65 55 22 15 18 19 39 42 60 65 68

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

17 30 33 34 36 37 38 39 52 61 65 68

45 51

17 30 33 34 36 37 38 39 52 61 65 68

45 51

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37

PP3V3_S0

45 51

8 12 13 17 65

77 68 65 64 62 61 50 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37 30 28 24 18 17 15 13 12 11 8 47 46 44 43 42 41 40 39 38 37 77 68 65 64 62 61 50 39 38 37 8 30 28 24 18 17 15 13 12 11 61 50 47 46 44 43 42 41 40 77 68 65 64 62

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

34 56 65 68

34 56 65 68

62 63 65

PP3V3_S0


62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

32 33 46 55 56 57 60 66 68

62 63 65

16 17 32 41 44 45 53 61 65 68

54 58 60

PP5V_S0_FET

16 17 32 41 44 45 53 61 65 68

54 58 60

16 17 32 41 44 45 53 61 65 68

54 58 60

16 17 32 41 44 45 53 54 58 60 61 65

68

16 17 32 41 44 45 53 61 65 68

54 58 60

16 17 32 41 44 45 53 61 65 68

54 58 60

16 17 32 41 44 45 53 61 65 68

54 58 60

PP3V3_S0_FET

16 17 32 41 44 45 53 58 60 61 65 68

54

16 17 32 41 44 45 53 61 65 68

54 58 60

16 17 32 41 44 45 53 54 58 60 61 65 68

PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFDQ_B

15 18 19 39 42 60 65

68

15 18 19 39 42 60 65

68

15 18 19 39 42 60 65

68

15 18 19 39 42 60 65

68

15 18 19 39 42 60 65

68

15 18 19 39 42 60 65

68

15 18 19 39 42 60 65

68

PP0V675_S0_DDRVTT

PP1V35_S3_CPUDDR


PPVTTDDR_S3

65 55 73 68

65 59 16 47 50 61 62 64 65 68 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 77

PP1V05_SUS

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 62 64 65 68 77

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PP0V675_S0_DDRVTT


61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61 62 64 65 68 77 37 38 39 ? 8 4011 12 13 15 17 18 24 28 30 1240 41 42 43 44 46 47 50 61 8 62 64 65 68 77 11 64 65 68 77 13 15 17 18 24 28 30 37 38 39 41 42 43 44 46 47 50 61 62

PPVTTDDR_S3


25 26 27 65 25 26 27 65

17 18 23 24 65

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_TBTLC

17 18 23 24 65

8 10 41 65 73

8 10 41 65 73

17 19 20 21 22 41 55

65 73

C

PP1V05_S0 mA

77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 61 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50 68 62 64 65 68 77 37 38 39 40 41 42 8 4011 12 13 15 17 18 24 28 30 1243 44 46 47 50 61 62 64 65 8 77 11 64 65 68 77 13 15 17 18 24 28 30 37 38 39 41 42 43 44 46 47 50 61 62

41 60 65

PP3V3_S0_FET

41 60 65

73

17 19 20 21 22 41 55 65

73

17 19 20 21 22 41 55 65

73

17 19 20 21 22 41 55 65

73

17 19 20 21 22 41 55 65

73

17 19 20 21 22 41 55 65

73

22 55 65 68 73

CPU "VCORE" RAILS 22 55 65 68 73 22 55 65 68 73

68 65 54 42 10 8

PP1V05_SUS

16 59 65

PP1V5_S0

8 47 59 60 61 63 65 68



PP1V05_S0


PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

PPVCC_S0_CPU

PPVCC_S0_CPU

8 10 42 54 65 68


55 65 68 73

16 59 65

41 60 65

PP5V_S0_FET

17 19 20 21 22 41 55 65

PP1V05_SUS


77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PPVCC_S0_CPU

8 10 42 54 65 68

B

8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68 8 47 59 60 61 63 65 68

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60 65 68

61

6 8 11 15 16 17 37 53 57 60

61

6 8 11 15 16 17 37 53 57 60

61

6 8 11 15 16 17 37 53 57 60

61

6 8 11 15 16 17 37 53 57 60

61

6 8 11 15 16 17 37 53 57 60

61

6 8 11 15 16 17 37 53 57 60

61

Digital Ground GND

VOLTAGE=0V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM

65 68 65 68 65 68 65 68 65 68 65 68

A

SYNC_MASTER=J44


PAGE TITLE


65 60 11 8

VOLTAGE=0.6V

PP0V675_S3_MEM_VREFCA_A 19 20 65 73 VOLTAGE=0.6V

PP0V675_S3_MEM_VREFDQ_B VOLTAGE=0.6V

PP1V05_S0SW_PCH_HSIO 1.84A

41 60 65

PP0V675_S3_MEM_VREFDQ_A 19 20 65 73

MAKE_BASE=TRUE


PP1V5_S0

77 42 43 44 46 47 50 61 62 64 65 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 68 61 62 64 65 68 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PP5V_S0_FET

MAKE_BASE=TRUE

PP1V5_S0

68 65 63 61 60 59 47 8

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP1V35_S3

PP0V675_S0_DDRVTT PP0V675_S0_DDRVTT

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0_FET PP0V675_S3_MEM_VREFDQ_A

16 17 32 41 44 45 53 54 58 60 61 65 68

25 26 27 65

68


PP3V3_S0

32 33 46 55 56 57 60 66 68

PP15V_TBT

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=15V MAKE_BASE=TRUE

PP15V_TBT PP15V_TBT

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

PP1V35_S3 PP1V35_S3 PP1V35_S3 PP1V35_S3 PP1V35_S3 PP1V35_S3

8 11 14 45 59 60 61 65

MIN_LINE_WIDTH=0.20MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

PP3V3_S3

PP15V_TBT

8 11 14 45 59 60 61 65

15 18 19 39 42 60 65

45 51

32 33 46 55 56 57 60 66 68

8 11 14 45 59 60 61 65

PP3V3_S3

17 30 33 34 36 37 38 39 52 61 65 68

17 30 33 34 36 37 38 39 52 61 65 68

PP1V35_S3

45 51

68 65 60 42 39 19 18 15

30 41 65


PP3V3_S0SW_SSD

1.5V/1.35V/1.05V RAILS PP1V35_S3_CPUDDR

D

25

8 11 14 45 59 60 61 65


PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS

40 51 52 65

PPVIN_SW_TBTBST

PP3V3_TBTLC

18 29 34 37 38 42 60 63 64 65 68 73 65 41 10 8 18 29 34 37 38 42 60 63 64 65 68


41 60 65


PP1V35_S3_CPUDDR

PP3V3_SUS

65 61 60 59 45 14 11 8

40 51 52 65

TBT RAILS (OFF WHEN NO CABLE)

41 60 65


65 27 26 25

PP3V3_S4_TBT

40 51 52 65

65 60 41


PP3V3_S0SW_SSD_FET

1

29 56

65 42 25 24 23 18 26 27 29 56 59 60 61 65 68 77 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S4

2 40 41 42 60 65

PP3V3_S0SW_SSD_FET

8 11 13 15 16 17

PP3V3_S4 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=18.5V MAKE_BASE=TRUE

8 11 13 15 16 17 18 26 59 60 61 65 68 77

3 PP3V3_S4SW_SNS

PP3V3_S4SW_SNS PP3V3_S4SW_SNS

8 11 13 15 16 17 18 26

PP3V3_S4 PPDCIN_G3H_ISOL

27 29 56

8 11 13 15 16 17 18 26


51 40 65 52

8 11 13 15 16 17 18 26 59 60 61 65 68 77

8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77 65 60 41 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S5 PP3V3_S5

PP3V3_S4

PP3V3_S4SW_SNS

65 60 42 41 40 8 11 13 15 16 17 18 26 27 29 56 59 60 61 65 68 77

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

25 40 51 52 58 65 68



PP3V3_S5

25 40 51 52 58 65 68

PPBUS_S5_HS_COMPUTING PPBUS_S5_HS_COMPUTING PPBUS_S5_HS_COMPUTING 65 56 40

5 3.3V Rails

25 40 51 52 58 65 68 29 27 26 18 17 16 15 13 11 8 77 68 65 61 60 59 56

19 21 65 73



PP1V05_S0SW_PCH_HSIO PP1V05_S0SW_PCH_HSIO

Power Aliases

8 11 60 65

DRAWING NUMBER

Apple Inc. 8 11 60 65 8 11 60 65

R

SIZE

D

REVISION


BRANCH


PAGE

100 OF 120

8

7

6

MEMORY ADDRESS/CTRL

7 7 7 7 7

D

66 22 20 7 73

7 7 7 7 7 7 7 7

=MEM_A_A<0> =MEM_A_A<1> =MEM_A_A<2> =MEM_A_A<3> =MEM_A_A<4> =MEM_A_A<5> MEM_A_A<6> =MEM_A_A<7> =MEM_A_A<8> =MEM_A_A<9> =MEM_A_A<10> =MEM_A_A<11> =MEM_A_A<12> =MEM_A_A<13> =MEM_A_A<14>

TRUE

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14>

TRUE TRUE TRUE

TRUE

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

20 22 73

5

20 22 73

5

20 22 73

5

20 22 73

5

20 22 73

5

20 22 73

5

7 20 22 66 73

5

20 22 73

5

20 22 73

74 66 64 13

20 22 73

74 66 64 13

20 22 73

66 64 13

20 22 73

66 64 13

20 22 73

66 64 13

=DP_TBTSNK1_ML_C_P<0> =DP_TBTSNK1_ML_C_N<0> =DP_TBTSNK1_ML_C_P<1> =DP_TBTSNK1_ML_C_N<1> =DP_TBTSNK1_ML_C_P<2> =DP_TBTSNK1_ML_C_N<2> =DP_TBTSNK1_ML_C_P<3> =DP_TBTSNK1_ML_C_N<3> DP_HDMI_TBT_AUX_P DP_HDMI_TBT_AUX_N DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_HPD_OUT

TRUE

DP_HDMI_TBT_ML_P<0>

64 74

TRUE

DP_HDMI_TBT_ML_N<0>

64 74

TRUE

DP_HDMI_TBT_ML_P<1>

64 74

TRUE

DP_HDMI_TBT_ML_N<1>

64 74

TRUE

DP_HDMI_TBT_ML_P<2>

64 74

TRUE

DP_HDMI_TBT_ML_N<2>

64 74

TRUE

DP_HDMI_TBT_ML_P<3>

64 74

TRUE

DP_HDMI_TBT_ML_N<3>

64 74

TRUE

DP_HDMI_TBT_AUX_P

13 64 66 74

TRUE

DP_HDMI_TBT_AUX_N

13 64 66 74

TRUE TRUE TRUE

DP_HDMI_TBT_DDC_CLK DP_HDMI_TBT_DDC_DATA DPMUX_HPD_OUT

7 7 7 7 7 66 22 21 7 73

7 7 7 7 7 7 7 7

TRUE

TRUE TRUE TRUE

TRUE TRUE TRUE TRUE TRUE

D

13 64 66 13 64 66 13 64 66

HDMITBTMUX_SEL_TBT

HDMITBTMUX_SEL_TBT MAKE_BASE=TRUE

15 23 64 66

HDMITBTMUX_SEL_TBT MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14>

TRUE

TRUE

1

20 22 73

MAKE_BASE

=MEM_B_A<0> =MEM_B_A<1> =MEM_B_A<2> =MEM_B_A<3> =MEM_B_A<4> =MEM_B_A<5> MEM_B_A<6> =MEM_B_A<7> =MEM_B_A<8> =MEM_B_A<9> =MEM_B_A<10> =MEM_B_A<11> =MEM_B_A<12> =MEM_B_A<13> =MEM_B_A<14>

2

20 22 73

66 64 23 15

7

3

MAKE_BASE

TRUE

TRUE

4

HDMI VS TBT

MAKE_BASE 7

5

TRUE TRUE TRUE TRUE

21 22 73 66 64 13

H DM IT BT MU X_ LA TC H

H DM IT BT MU X_ LA TC H MAKE_BASE=TRUE

21 22 73

15 23 64 66

13 64 66

21 22 73 21 22 73

EPD PANEL

21 22 73 21 22 73

MAKE_BASE 7 21 22 66 73 68 66 62 58 21 22 73 68 66 62 58

I2C_BKLT_SCL I2C_BKLT_SDA

TRUE

I2C_BKLT_SCL

58 62 66 68

TRUE

I2C_BKLT_SDA

58 62 66 68

21 22 73 21 22 73 21 22 73 21 22 73 21 22 73 21 22 73 21 22 73

C

C MAKE_BASE 66 22 7 66 22 20 7 73 66 22 20 7 73 66 22 20 7 73

7 66 22 20 7 73

7

MEM_A_ODT_CPU0 MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L =MEM_A_BA<0> MEM_A_BA<1> =MEM_A_BA<2>

TRUE TRUE TRUE TRUE TRUE TRUE TRUE

MEM_A_ODT_CPU0 MEM_A_RAS_L MEM_A_WE_L MEM_A_CAS_L MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

7 22 66 7 20 22 66 73 7 20 22 66 73 7 20 22 66 73 20 22 73

7 20 22 66 73

UNUSED SIGNALS

20 22 73

MAKE_BASE 66 22 7 66 22 21 7 73 66 22 21 7 73 66 22 21 7 73

7 66 22 21 7 73

7

MEM_B_ODT_CPU0 MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L =MEM_B_BA<0> MEM_B_BA<1> =MEM_B_BA<2>

TRUE TRUE TRUE TRUE TRUE TRUE TRUE

MEM_B_ODT_CPU0 MEM_B_RAS_L MEM_B_WE_L MEM_B_CAS_L MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

7 22 66 7 21 22 66 73 7 21 22 66 73 7 21 22 66 73 21 22 73

7 21 22 66 73

MAKE_BASE

21 22 73

66 12 66 12 66 14 66 14

66 22 6

MEM_RESET_HSW_L

MAKE_BASE TRUE

66 14

MEM_RESET_HSW_L

6 22 66

66 14

B

NC_PCIE_CLK100M_FWP NC_PCIE_CLK100M_FWN NC_PCIE_FW_D2RP NC_PCIE_FW_D2RN

TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE

NC_PCIE_FW_R2D_CP NC_PCIE_FW_R2D_CN

TRUE TRUE

NC_PCIE_CLK100M_ENETSDP 66 12 NC_PCIE_CLK100M_ENETSDN NC_USB_IRP 71 66 14 NC_USB_IRN 71 66 14 NC_USB_CAMERAP 71 66 14 NC_USB_CAMERAN 71 66 14 NC_USB_SDP 71 66 14 NC_USB_SDN 71 66 14 66 12

UNUSED MEMORY SIGNALS 66 7 66 7

7 66 7 66 7 66 7

7 66 7

NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1> MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLKN<1> NC_MEM_B_CLKP<1> MEM_B_CKE<2> NC_MEM_B_CKE<3>

NO_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

66 12 66 13 66 14

NC_MEM_A_CLKN<1> NC_MEM_A_CLKP<1> NC_MEM_A_CKE<2> NC_MEM_A_CKE<3> NC_MEM_B_CLKN<1> NC_MEM_B_CLKP<1> NC_MEM_B_CKE<2> NC_MEM_B_CKE<3>

7 66

66 14

7 66

66 14

NC_HDA_SDIN1 NC_PCI_PME_L NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L


TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE TRUE NO_TEST=TRUE

NC_PCIE_CLK100M_FWP NC_PCIE_CLK100M_FWN NC_PCIE_FW_D2RP NC_PCIE_FW_D2RN NC_PCIE_FW_R2D_CP NC_PCIE_FW_R2D_CN

12 66 12 66 14 66 14 66 14 66 14 66

B

NC_PCIE_CLK100M_ENETSDP 12 66 NC_PCIE_CLK100M_ENETSDN 12 66 NC_USB_IRP 14 66 71 NC_USB_IRN 14 66 71 NC_USB_CAMERAP 14 66 71 NC_USB_CAMERAN 14 66 71 NC_USB_SDP 14 66 71 NC_USB_SDN 14 66 71

NC_HDA_SDIN1 NC_PCI_PME_L NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

12 66 13 66 14 66 14 66 14 66

7 66 7 66 7 66

7 66

66 45 66 45

NC_SMC_TRST_L NC_SMC_MD1

TRUE TRUE


NC_SMC_TRST_L NC_SMC_MD1

45 66 45 66

A

A

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PAGE TITLE 65 63 62 60 57 56 55 46 33 32 68

Signal Aliases

PP5V_S4

DRAWING NUMBER

GND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

SM

1

Digital Ground

Apple Inc.

XWA202 2

XWA203

R

PP5V_S0_AUDIO_AMP_L MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

SM

1

2

PP5V_S0_AUDIO_AMP_R

48

SIZE

D

REVISION


BRANCH


PAGE

102 OF 120

8

7

6

5

4

3

2

1

D

D Memory Bit/Byte Swizzle MAKE_BASE 73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 67 20 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

C

B

A

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 7

TRUE

73 67 20 7

TRUE

73 67 20 7

TRUE

73 7

TRUE

73 7

TRUE

MAKE_BASE

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> M E M_ A _D Q <2 0 > MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

=MEM_A_DQ<60> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<63> =MEM_A_DQ<44> =MEM_A_DQ<40> =MEM_A_DQ<45> =MEM_A_DQ<47> =MEM_A_DQ<46> =MEM_A_DQ<42> =MEM_A_DQ<41> =MEM_A_DQ<43> =MEM_A_DQ<20> =MEM_A_DQ<18> =MEM_A_DQ<23> =MEM_A_DQ<19> = M EM _ A_ D Q< 1 7> =MEM_A_DQ<21> =MEM_A_DQ<22> =MEM_A_DQ<16> =MEM_A_DQ<38> =MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<39> =MEM_A_DQ<34> =MEM_A_DQ<32> =MEM_A_DQ<35> =MEM_A_DQ<33> MEM_A_DQ<32> =MEM_A_DQ<24> =MEM_A_DQ<25> =MEM_A_DQ<29> =MEM_A_DQ<30> =MEM_A_DQ<26> =MEM_A_DQ<31> =MEM_A_DQ<27> =MEM_A_DQ<12> =MEM_A_DQ<8> =MEM_A_DQ<11> =MEM_A_DQ<15> =MEM_A_DQ<14> =MEM_A_DQ<10> =MEM_A_DQ<9> =MEM_A_DQ<13> =MEM_A_DQ<53> =MEM_A_DQ<55> =MEM_A_DQ<50> =MEM_A_DQ<54> =MEM_A_DQ<52> =MEM_A_DQ<48> =MEM_A_DQ<51> =MEM_A_DQ<49> =MEM_A_DQ<2> =MEM_A_DQ<1> =MEM_A_DQ<6> =MEM_A_DQ<4> =MEM_A_DQ<0> =MEM_A_DQ<3> =MEM_A_DQ<7> =MEM_A_DQ<5> =MEM_A_DQS_P<7> =MEM_A_DQS_N<7> =MEM_A_DQS_P<5> =MEM_A_DQS_N<5> =MEM_A_DQS_P<2> =MEM_A_DQS_N<2> =MEM_A_DQS_P<4> =MEM_A_DQS_N<4> =MEM_A_DQS_P<3> =MEM_A_DQS_N<3> =MEM_A_DQS_P<1> =MEM_A_DQS_N<1> MEM_A_DQS_P<6> MEM_A_DQS_N<6> =MEM_A_DQS_P<0> =MEM_A_DQS_N<0>

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

73 68 67 21 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

20

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

73 68 7

TRUE

7 20 67 68 73

20

20 20 20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

7 20 67 73

73 67 21 7

TRUE

7 20 67 73

20

73 67 21 7

TRUE

20

73 7

TRUE

20

73 7

TRUE

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> M E M_ B _D Q <1 0 > MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

=MEM_B_DQ<8> =MEM_B_DQ<14> =MEM_B_DQ<11> =MEM_B_DQ<9> =MEM_B_DQ<12> =MEM_B_DQ<10> =MEM_B_DQ<15> =MEM_B_DQ<13> =MEM_B_DQ<24> =MEM_B_DQ<30> = M EM _ B_ D Q< 2 9> =MEM_B_DQ<27> =MEM_B_DQ<28> =MEM_B_DQ<26> =MEM_B_DQ<25> =MEM_B_DQ<31> =MEM_B_DQ<5> =MEM_B_DQ<1> =MEM_B_DQ<6> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<7> =MEM_B_DQ<0> =MEM_B_DQ<2> =MEM_B_DQ<21> =MEM_B_DQ<17> =MEM_B_DQ<20> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<19> =MEM_B_DQ<18> =MEM_B_DQ<16> MEM_B_DQ<32> =MEM_B_DQ<40> =MEM_B_DQ<45> =MEM_B_DQ<43> =MEM_B_DQ<46> =MEM_B_DQ<42> =MEM_B_DQ<47> =MEM_B_DQ<41> =MEM_B_DQ<60> =MEM_B_DQ<56> =MEM_B_DQ<63> =MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<58> =MEM_B_DQ<59> =MEM_B_DQ<57> =MEM_B_DQ<38> =MEM_B_DQ<37> =MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQ<35> =MEM_B_DQ<36> =MEM_B_DQ<34> =MEM_B_DQ<39> =MEM_B_DQ<51> =MEM_B_DQ<53> =MEM_B_DQ<48> =MEM_B_DQ<55> =MEM_B_DQ<50> =MEM_B_DQ<49> =MEM_B_DQ<54> =MEM_B_DQ<52> =MEM_B_DQS_P<1> =MEM_B_DQS_N<1> =MEM_B_DQS_P<3> =MEM_B_DQS_N<3> =MEM_B_DQS_P<0> =MEM_B_DQS_N<0> =MEM_B_DQS_P<2> =MEM_B_DQS_N<2> =MEM_B_DQS_P<5> =MEM_B_DQS_N<5> =MEM_B_DQS_P<7> =MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> =MEM_B_DQS_P<6> =MEM_B_DQS_N<6>

21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

C

21 21 21 21 21 21 21 21 21 21 21 21 21

7 21 67 68 73 21 21 21 21 21 21 21 21 21 21 21 21

B

21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

21 21 21 21 21 21 21 21 21 21 21

Memory Bit/Byte Swizzle DRAWING NUMBER

Apple Inc.

7 21 67 73

21 21


PAGE TITLE

21

7 21 67 73

A

SYNC_MASTER=J44

R

SIZE

D

REVISION


BRANCH


PAGE

103 OF 120

8

7

TRUE

TRUE

1

SM

PP

P2MM

70 68 23 12

3 TPs per Fan

FAN_LT_PWM FAN_LT_TACH

SM 1P2MM PP SM 1

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

PP

P2MM

70 32 14 70 32 14

70 68 30 12

D

70 68 30 12

70 68 63 14

J4002 (ALS/CAMERA CONN)

70 68 63 14

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA PP5V_S3RS0_ALSCAM_F MIPI_CLK_CONN_N TRUE MIPI_CLK_CONN_P TRUE TRUE CAM_SENSOR_WAKE_L_CONN TRUE MIPI_DATA_CONN_N TRUE MIPI_DATA_CONN_P TRUE I2C_CAM_SCK TRUE I2C_CAM_SDA

14 32 36 39 43 72 76

TRUE

14 32 36 39 43 72 71 63 14 76 71 63 14 32

TRUE

SM 1P2MM PP SM 1

PCIE_CAMERA_D2R_P PCIE_CAMERA_D2R_N

PP

P2MM SM 1P2MM PP

PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0>

1

PP

P2MM SM 1P2MM PP


1

SM

PP

SM 1P2MM PP SM 1


PP

32 75 32 75

SM

PPA400 PPA401 PPA423 PPA424 PPA402 PPA403 PPA404 PPA405 PPA410 PPA411

P2MM

TRUE

PPA420 PPA421

P2MM 72 47 12

1

HDA_SDIN0

32

SM

PP

PPA408

PLACE_NEAR=U0500.AY10:6MM 32 75 32 75

75 32 31

31 32

SM

1P2MM PP SM 1

MIPI_CLK_N MIPI_CLK_P

PP P2MM SM 1P2MM PP

31 32 75 32 31

J9500 (RIO POWER PINS) PP3V3_S4 TRUE PP5V_S4 TRUE PP1V5_S0 TRUE

18 29 34 37 38 42 60 68

63 64 65

32 33 46 55 56 57 60 66 68

62 63 65

MIPI_DATA_N MIPI_DATA_P

1

SM

PP

PPA441 PPA442 PPA443 PPA444

U5000 CHARZ TPS 72 36 17

P2MM

LPC_CLK24M_SMC

1

PP

PPA419

J6601 (AUDIO 2-MIKE CONN)

TRUE

4

TRUE


14 16 19 39 63 72

TRUE 14 16 19 39 63 72

TRUE

DMIC_SDA3 DMIC_SDA2 DMIC_CLK3

45 51

TRUE

PM_SLP_S3_L PP0V675_S0_DDRVTT

TRUE

PP1V05_S0

TRUE

34

TRUE

J7715 (KBD BACKLIGHT CONN) TRUE PPVOUT_S0_KBDBKLT TRUE KBDLED_CATHODE1 KBDLED_CATHODE2 TRUE

TRUE 35 58

TRUE

35 58

TRUE

SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_L_ID SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N

2

1

ICT Test Points

FUNC_TEST

17 30 33 34 36 37 38 39 52 61 65 68

NC NO_TEST

13 17 18 36 61 63 22 55 65 73

34 34

6 8 11 15 16 17 37 53 57 60 61 65

34

High Speed NO_TEST

34 34

PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N

34 34 34

SMBUS_SMC_2_S3_SDA SMBUS_SMC_2_S3_SCL PP3V3_TPAD_CONN TRUE PP5V_S4_CUMULUS TRUE Z2_CLKIN TRUE PSOC_SCLK TRUE PSOC_MOSI TRUE Z2_SCLK TRUE PSOC_MISO TRUE Z2_MISO TRUE Z2_MOSI TRUE PSOC_F_CS_L TRUE Z2_CS_L TRUE Z2_KEY_ACT_L TRUE PICKB_L TRUE Z2_HOST_INTN TRUE

14 63 70

TRUE 14 63 70

TRUE 14 63 68 70

TRUE

PCIE_SSD_R2D_C_P<3..0> PCIE_SSD_R2D_C_N<3..0>

34 34

GND

TRUE

4 TPs

34

12 30 70

TRUE 12 30 70

TRUE

PCIE_SSD_R2D_P<3..0> PCIE_SSD_R2D_N<3..0>

34

30 70

TRUE

PCIE_SSD_D2R_P<3..0> PCIE_SSD_D2R_N<3..0>

34 34

TRUE

PP3V3_S0

TRUE

PP3V3_S3 PP3V3_S5

34 34 34

TRUE 34

TRUE

PP3V3_S5_AVREF_SMC PP3V42_G3H PP5V_S0 PP5V_S4 PP5V_S5 PPBUS_G3H PPDCIN_G3H

TRUE

PPVCC_S0_CPU

TRUE 34

TRUE 34

TRUE 34

TRUE 34

TRUE 34

TRUE 34

61 62 64 65 77 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

PCIE_TBT_R2D_C_P<3..0> PCIE_TBT_R2D_C_N<3..0> PCIE_TBT_R2D_P<3..0> PCIE_TBT_R2D_N<3..0> PCIE_TBT_D2R_P<3..1> PCIE_TBT_D2R_N<3..1> PCIE_TBT_D2R_C_P<3..1> PCIE_TBT_D2R_C_N<3..1>

15 18 19 39 42 60 65

8 11 13 15 16 17 18 26 59 60 61 65 77

27 29 56

36 37 17 30 33 34 36 37 38 52 61 65 68

39 45 51

16 17 32 41 44 45 53 61 65 68

54 58 60

32 33 46 55 56 57 60 66 68

62 63 65

12 30 68 70

TRUE

34 36 39 76

TRUE

34 56 65 25 40 51 52 58 65

14 23 70

TRUE 14 23 70

TRUE 23 70

TRUE TRUE

14 23 70

TRUE

23 70

USB3_EXTA_D2R_P USB3_EXTA_D2R_N

8 10 42 54 65

23 70

14 33 71

PPVTTDDR_S3

NC_PM_SLP_A_L

55 65 68 73

TRUE MAKE_BASE=TRUE

NC_PM_SLP_A_L

13 68

USB3_EXTA_R2D_C_P USB3_EXTA_R2D_C_N USB3_EXTA_R2D_N USB3_EXTA_R2D_N

TRUE

34

NO_TESTs

34

USB3_EXTB_D2R_P USB3_EXTB_D2R_N USB3_EXTB_R2D_C_P USB3_EXTB_R2D_C_N

34 34

TBTBPWRSW_ISET_V3P3

27

TRUE

34

33 68 71

TBTBPWRSW_ISET_S0_R TBTBPWRSW_ISET_S3

34 34

14 63 71

14 63 71

TRUE 14 63 71

TRUE

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

27

TRUE

12 30 70

TRUE 12 30 70

TRUE 34

TBTAPWRSW_ISET_V3P3

MEM_A_DQ<63..0>

26

TRUE

34

7 20 67 73

TRUE

PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

26

12 23 68 70

TRUE

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

J7000 (DC POWER CONN)

48 50 77

TDM_ONEWIRE_MPM ADAPTER_SENSE PP18V5_DCIN_FUSE

51

J6603 (AUDIO RIGHT SPEAKER CONN)

TBT_A_D2R_C_P<1> TBT_A_D2R_C_N<1> TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0>

PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_CAMERA_P PCIE_CLK100M_CAMERA_N

26

TRUE 26

PPVTTDDR_S3

TRUE

55 65 68 73

23 26 74

12 63 70

TRUE TRUE TRUE

TRUE

12 63 70 12 32 70 12 32 70

TRUE 23 26 74

TRUE 26 74

TRUE 26 74

TRUE 51

GND

12 23 68 70

TRUE

TRUE

TRUE

14 63 71

TRUE

27

TRUE

34

TBTAPWRSW_ISET_S3 TBTAPWRSW_ISET_S3_R

TRUE

C

33 68 71

TRUE

34

47 50

TRUE

14 33 71

TRUE

34

34

14 33 71

TRUE TRUE

50

48 50 77

14 33 71

TRUE

TRUE

48 50 77

14 23 70

TRUE

51 52 65

TBTAPWRSW_ISET_S0

35 58

23 70

TRUE

TRUE

34

47 50

TRUE

12 30 68 70

TRUE

TRUE 34 36 39 76

TRUE

47 50

30 70

TRUE

34

TRUE

48 50 77

D

14 63 68 70

TRUE

34

J6602 (AUDIO LEFT SPEAKER CONN) TRUE

3

POWER RAILS 18 29 34 37 38 42 60 63 64 65 68

J4800 (TPAD CONN)

SM

C

TRUE

5 J4813 (KEY BOARD CONN) PP3V3_S4 TRUE PP3V42_G3H TRUE WS_KBD1 TRUE WS_KBD2 TRUE TRUE WS_KBD3 TRUE WS_KBD4 TRUE WS_KBD5 TRUE WS_KBD6 TRUE WS_KBD7 TRUE WS_KBD8 TRUE WS_KBD9 TRUE WS_KBD10 WS_KBD11 TRUE WS_KBD12 TRUE WS_KBD13 TRUE WS_KBD14 TRUE WS_KBD15_CAP TRUE WS_KBD16_NUM TRUE TRUE WS_KBD17 TRUE WS_KBD18 WS_KBD19 TRUE WS_KBD20 TRUE WS_KBD21 TRUE WS_KBD22 TRUE WS_KBD23 TRUE WS_KBD_ONOFF_L TRUE WS_LEFT_SHIFT_KBD TRUE WS_LEFT_OPTION_KBD TRUE WS_CONTROL_KBD TRUE

8 47 59 60 61 63 65

GND

TRUE

P2MM SM 1P2MM PP

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_N<0>

70 23 14 70 23 14

J6050 (LEFT FAN CONN) FUNC_TEST PP5V_S0 TRUE

6 U0500 CHARZ TPS

Functional Test Points

MEM_B_DQ<63..0>

7 21 67 73

TRUE 26 74

TRUE

26 74

TRUE

26 74

TRUE 26 74

TRUE

B

TRUE

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_R_ID SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N

TRUE

GND

TRUE TRUE TRUE TRUE

48 50 77 48 50 77 47 50

TRUE

48 50 77

TRUE

TRUE

TRUE

TRUE TRUE

36 39 51 52 76

TRUE

A

TRUE TRUE

51

CON_DMIC_PWR CON_DMIC_SDA1 CON_DMIC_CLK

J4600 (LEFT USB CONN) PP5V_S3_LTUSB_A_F USB_LT1_N TRUE USB_LT1_P TRUE TRUE

FUNC_TEST TRUE

TRUE

PPVOUT_S0_LCDBKLT

58 62

36 39 51 52 76

SYS_DETECT_L

PCH_VSS_NCTF<19> PCH_VSS_NCTF<19>

62

68 68

33

I2C_BKLT_SCL I2C_BKLT_SDA LCD_HPD_CONN LCD_IRQ_L TRUE EDP_BKLT_PWM TRUE SMBUS_SMC_0_S0_SCL TRUE SMBUS_SMC_0_S0_SDA TRUE EDP_PANEL_PWR_OR_PSR_EN TRUE DP_INT_AUX_P TRUE DP_INT_AUX_N TRUE DP_INT_ML_P<0> TRUE DP_INT_ML_N<0> TRUE DP_INT_ML_P<1> TRUE DP_INT_ML_N<1> TRUE DP_INT_ML_P<2> TRUE DP_INT_ML_N<2> TRUE TRUE DP_INT_ML_P<3> DP_INT_ML_N<3> TRUE

2 TP needed

TRUE TRUE

TRUE

58 62 66

TRUE

58 62 66

TRUE

62

TRUE TRUE TRUE 15 62

TRUE 13 62

TRUE

TRUE 62

TRUE 62 74

TRUE

PP3V42_G3H PP5V_S0 LPC_CLK24M_LPCPLUS LPC_AD<0> LPC_AD<2> LPC_AD<1> LPC_AD<3>

65 68 17 30 33 34 36 37 38 39 45 51 52 61 16 17 32 41 44 45 53 54 58 60 61 65 68 17 45 72 14 36 45 72 14 36 45 72

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0> TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0> TBT_B_D2R_C_P<1> TBT_B_D2R_C_N<1> TBT_B_D2R_P<0> TBT_B_D2R_N<0> TBT_B_D2R_P<1> TBT_B_D2R_N<1>

XDP_LPCPLUS_GPIO LPCPLUS_RESET_L SMC_TDO

23 26 74

TRUE

23 26 74

TRUE

23 26 74

TRUE 23 27 74

TRUE

23 27 74

TRUE 27 74

TRUE

27 74

TRUE

27 74

SMC_TX_L

TRUE 62 74

TRUE 62 74

TRUE

LPC_FRAME_L SPIROM_USE_MLB PM_CLKRUN_L

23 27 74

TRUE TRUE TRUE

FW_PWR_EN FW_PME_L ENET_MEDIA_SENSE

23 27 74

TRUE 23 27 74

TRUE 23 27 74

14 36 45 72

15 16 45 18 45 36 37 45

TRUE TRUE TRUE

PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_R2D_P PCIE_AP_R2D_N

14 63 68 70 63 70 63 70

68

68

14 36 45 72

68

15 45 72 13 36 45 68

68

15 36 45

68

13 36 45

68

36 37 45 68 36 37 45 68

37 45

15 15

ODD_PWR_EN_L ENET_LOW_PWR AUD_IP_PERIPHERAL_DET AUD_I2C_INT_L AUD_IPHS_SWITCH_EN ENETSD_CLKREQ_L

14 63 68 70

36 37 45

36 37 38 45 52

15

TRUE

14 36 45 72

68

LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_ROMBOOT

63 64 74

27 74

TRUE

NC_XDP_PCH_HOOK4 NC_XDP_PCH_HOOK5 TP_XDP_PCH_OBSFN_B<0> NC_XDP_PCH_OBSFN_B<1> TP_XDP_PCH_OBSFN_A<0> NC_XDP_PCH_OBSFN_A<1> TP_XDP_PCH_OBSFN_D<0> NC_XDP_PCH_OBSFN_D<1> NC_XDP_PCH_TRST_L

62 74

TRUE

(Nets with offpages not used on this project) HDD_PWR_EN 15 WOL_EN 14 BT_PWRRST_L 15

63 64 74

TRUE TRUE

62 74

TRUE

63 64 74

TRUE

27 74

62 74 62 74

Unused nets with offpage

63 64 74

TRUE

TRUE TRUE

TRUE

62 74

TRUE

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N HDMI_IG_DATA_C_P<2..0> HDMI_IG_DATA_C_N<2..0>

27 74

TRUE

68

62 74

B

23 26 74

TRUE

62 74

TRUE

TRUE

34 36 37

TRUE 36 39 62 76

71

GND

SMC_ONOFF_L

36 39 62 76

71

GND GND

13 17 36 72

J6100 (LPC + SPI CONN)

51 52

J6601 (2 MIC CONN) TRUE

J8300 (EDP CONN) PP5VR3V3_SW_LCD

13 36 45 68

48 50 77

TRUE

J7050 (MAIN BATT CONN) PPVBAT_G3H_CONN TRUE TRUE SMBUS_SMC_5_G3_SCL TRUE SMBUS_SMC_5_G3_SDA

PM_CLKRUN_L PM_SYSRST_L

TBT_A_D2R_P<1> TBT_A_D2R_N<1> TBT_A_D2R_P<0> TBT_A_D2R_N<0>

NC_1V05_S0_PCH_VCCAPLLEXP NC_AUD_CODEC_MICBIAS NC_AUD_MIC_INRP NC_AUD_MIC_INRN

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_XDP_PCH_HOOK4 NC_XDP_PCH_HOOK5 NC_XDP_PCH_OBSFN_B<0> NC_XDP_PCH_OBSFN_B<1> NC_XDP_PCH_OBSFN_A<0> NC_XDP_PCH_OBSFN_A<1> NC_XDP_PCH_OBSFN_D<0> NC_XDP_PCH_OBSFN_D<1> NC_XDP_PCH_TRST_L

NC_1V05_S0_PCH_VCCAPLLEXP TRUE MAKE_BASE=TRUE NC_AUD_CODEC_MICBIAS TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_AUD_MIC_INRP NC_AUD_MIC_INRN

68 68

13 13 13 13 13 12

68

68

A

SYNC_MASTER=J44


PAGE TITLE 68 68

Functional / ICT Test DRAWING NUMBER

Apple Inc.

68 68

68 68

R

SIZE

D

REVISION


BRANCH


PAGE

104 OF 120

8

7

6

5

4

3

2

1

J44 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO

BOARD LAYERS

BOARD UNITS ALLEGRO (MIL or MM) VERSION

BOARD AREAS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

N O_ TY PE ,B GA ,P 65 BG A, BG A_ ME M

MM

1 6. 5 TABLE_PHYSICAL_RULE_HEAD

ALLOW ROUTE ON LAYER?

PHYSICAL_RULE_SET

LAYER

DEFAULT

*

Y

=45_OHM_SE

=45_OHM_SE

STANDARD

*

Y

=DEFAULT

=DEFAULT

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

10 MM

0 MM

0 MM

TABLE_PHYSICAL_RULE_ITEM


10 MM

=DEFAULT

=DEFAULT

D

D TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

NET_SPACING_TYPE1

NET_SPACING_TYPE2

SPACING_RULE_SET

*

*

BGA

P072_SPACE

*

*

P65BGA

P075_SPACE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

5 0_ OH M_ SE

TO P, BO TT OM

Y

0 .0 95 M M

0 .0 95 M M

5 0_OH M_SE

*

Y

0. 066 MM

0.0 66 M M



PHYSICAL_RULE_SET

LAYER

45_OHM_SE

TOP,BOTTOM


=STA NDAR D

=STA NDAR D

= STAN DARD TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD


Y

0.116 MM

0.116 MM

Y

0.083 MM

0.083 MM

*

LAYER

SPACING_RULE_SET

LINE-TO-LINE

SPACING

WEIGHT TABLE_SPACING_RULE_ITEM


45_OHM_SE

=STANDARD

=STANDARD

=STANDARD

DEFAULT

*

0.1 MM

?

STANDARD

*

=DEFAULT

?

P072_SPACE

*

0.071 MM

?

P075_SPACE

*

0.075 MM

TABLE_SPACING_RULE_ITEM


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP



4 0_ OH M_ SE

TO P, BO TT OM

Y

0 .1 45 M M

0 .0 95 M M


?


4 0_OH M_SE

*

Y ALLOW ROUTE ON LAYER?

0. 102 MM

0.0 90 M M

=STA NDAR D

=STA NDAR D


PHYSICAL_RULE_SET

LAYER

37_OHM_SE

TOP,BOTTOM

Y

0.165 MM

0.095 MM

37_OHM_SE

*

Y

0.118 MM

0.090 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH




C

=STANDARD

=STANDARD

=STANDARD TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



2 7P 4_ OH M_ SE T OP ,B OT TO M

Y

0 .2 65 M M

0 .0 95 M M

C

Stackup-Defined Spacing Rules Note: Outer dielectric is 0.058 mm nominal, Inner dielectric is 0.053 mm nominal.


2 7P4_O HM_S E

*

Y

0. 186 MM

0.0 90 M M

=STA NDAR D

=STA NDAR D


PHYSICAL_RULE_SET

LAYER

72_OHM_DIFF

*


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

TABLE_SPACING_RULE_HEAD

LAYER

SPACING_RULE_SET

LINE-TO-LINE

SPACING


N

=ST ANDA RD

=STA NDAR D

=STA NDAR D

=STA NDARD

= STAN DARD


1:1_SPACING

0.1 MM

*

?


72_OHM_DIFF

Y

0.105 MM

0.105 MM

0.120 MM

0.120 MM

72_OHM_DIFF ISL2,ISL11

Y

0.105 MM

0.105 MM

0.120 MM

0.120 MM

72_OHM_DIFF TOP,BOTTOM

Y

0.146 MM

0.146 MM

0.120 MM

0.120 MM

ISL3,ISL4,ISL9,ISL10



LAYER

SPACING_RULE_SET

LINE-TO-LINE

SPACING



1x_DIELECTRIC T OP ,B OT TO M

0 .0 58 M M

?

1x_DIELECTRIC


0.053 MM

?

1X_DIELECTRIC

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

0.101 MM

?



PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

=STANDARD

=STANDARD



80_OHM_DIFF

*

N

=STANDARD


=STANDARD TABLE_PHYSICAL_RULE_ITEM

80_OHM_DIFF

Y

0.092 MM

0.092 MM

0.120 MM

0.120 MM


Y

0.092 MM

0.092 MM

0.120 MM

0.120 MM


Y

0.125 MM

0.125 MM

0.155 MM

0.155 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH





PHYSICAL_RULE_SET

LAYER


MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP TABLE_PHYSICAL_ASSIGNMENT_HEAD


B

8 5_OHM _DIF F

*

N

=ST ANDA RD

=STA NDAR D

85_OHM_DIFF


Y

0.080 MM


Y


Y

=STA NDAR D

=STA NDARD

= STAN DARD

0.080 MM

0.120 MM

0.120 MM

0.080 MM

0.080 MM

0.120 MM

0.120 MM

0.105 MM

0.105 MM

0.125 MM

0.125 MM


NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

B

TABLE_PHYSICAL_ASSIGNMENT_ITEM

*

P65BGA

P65_BGA




PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



9 0_ OH M_ DI FF

*

N

= ST AN DA RD

= ST AN DA RD

Y

0.078 MM


Y


Y

= ST AN DA RD

= ST AN DA RD

= ST AN DA RD

0.078 MM

0.200 MM

0.200 MM

0.078 MM

0.078 MM

0.200 MM

0.200 MM

0.101 MM

0.101 MM

0.180 MM

0.180 MM


90_OHM_DIFF





PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



A

P65_BGA

*

Y

0.071MM

0.071MM

0.075MM

0.126MM TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

1TO1_DIFFPAIR

*


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



Y

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.1 MM

A



PCB Rule Definitions DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

110 OF 120

8

7

6

5

CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


CPU_45S

*

=45_OHM_SE

4

3

CPU Signal Properties

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=45_OHM_SE

=45_OHM_SE

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

ELECTRICAL CONST SET

2

1

PCI Express Properties

NET TYPE PHYSICAL SPACING


NET TYPE PH YSI CAL SP ACI NG


=45_OHM_SE

=STANDARD

=STANDARD TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

*

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

7 MIL

7 MIL


SPACING_RULE_SET

LAYER

LINE-TO-LINE


WEIGHT

SPACING

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT


D

CPU_VCCSENSE

*

25 MIL


?

CPU_08MIL

*

0.203 MM

? TABLE_SPACING_RULE_ITEM

CPU_12MIL

*

0.305 MM


CPU_18MIL

0.457 MM

*


CPU_25MIL

0.635 MM

*

?

PCI Express Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET


LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

XDP_CPU_TCK PCH_JTAGX XDP_PCH_TCK XDP_CPU_TDO XDP_PCH_TDO XDP_CPU_TDI XDP_PCH_TDI XDP_CPU_TMS XDP_PCH_TMS XDP_TRST_L XDP_CPUPCH_TRST_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_TCK0 XDP_TCK0 XDP_TCK1 XDP_TDO XDP_TDO XDP_TDI XDP_TDI XDP_TMS XDP_TMS X DP _T RS T_ L XDP_TRST_L X DP _P RD Y_ L X DP _P RE Q_ L

CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S C PU _4 5S CPU_45S C PU _4 5S C PU _4 5S

CPU_18MIL CPU_18MIL CPU_18MIL

C PU _V CC ST_ PW RG D CPU_VCCST_PWRGD CPU_BPM CPU_BPM_TP

CPU_45S CPU_45S C P U_ 4 5S CPU_45S

C PU_ 08M IL CPU_08MIL C P U_ 0 8M I L

CPU_RCOMP_SM CPU_RCOMP_EDP CPU_RCOMP_OPI

CPU_27P4S CPU_27P4S CPU_27P4S


CPU_SM_RCOMP<2..0> MCP_EDP_RCOMP CPU_OPI_RCOMP


CPU_PROCHOT_L CPU_PROCHOT_R_L CPU_CATERR_L

CPU_VCCST_PWRGD XDP_CPU_VCCST_PWRGD XDP_BPM_L<1..0> XDP_BPM_L<7..2>

6 16 12 16 12 16

6 16 12 16

6 16 12 16

6 16 12 16 16

*

CLK_PCIE_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

6 16

8 16 17 16


SPACING_RULE_SET

LAYER

LINE-TO-LINE

WEIGHT

SPACING

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


PCIE_2SAME

*

=3X_DIELECTRIC


?

PCIE_2SAME

TOP,BOTTOM =4X_DIELECTRIC


C

P CI E_ TX RX

*

= 6X _D IE LE CT RI C

PCIE_TXRX



*

=4X_DIELECTRIC

?

PCIE_2CLK

*

=7X_DIELECTRIC

?

6 5 6

=7X_DIELECTRIC

?


?

PCIE_2CLK

TOP,BOTTOM=10X_DIELECTRIC

?



PCIECLK_2OTHER TOP,BOTTOM=10X_DIELECTRIC TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

PCIE_*

*

AREA_TYPE

SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

*

PCIE_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_*

=SAME

*

PCIE_*

CLK_*

*

P CI E_ 2C LK

CLK_PCIE

*

*

PCIECLK_2OTHER

6 6 36

?

PCIE_2OTHER


*

6 36 37 53



PCIECLK_2OTHER

CPU_45S CPU_45S CPU_45S

PCIE_2SAME TABLE_SPACING_ASSIGNMENT_ITEM

?

CPU_VIDALERT CPU_VIDALERT CPU_VIDSCLK CPU_VIDSCLK CPU_VIDSOUT CPU_VIDSOUT CPU_PECI CPU_PECI CPU_PECI_SMC CPU_PECI_SMC

CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S

CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL CPU_18MIL

CPU_VIDALERT_L CPU_VIDALERT_R_L CPU_VIDSCLK CPU_VIDSCLK_R CPU_VIDSOUT CPU_VIDSOUT_R CPU_PECI CPU_PECI_R SMC_PECI_L SMC_PECI_L_R

8 53 8 8 53

*

8 6 37

B

A

*_TX

*

PCIE_TBT_D2R_0 PCIE_TBT_D2R_0 PCIE_TBT_D2R_0 PCIE_TBT_D2R_0 P CI E_ TB T_ D2 R P CI E_ TB T_ D2 R PCIE_TBT_D2R P CI E_ TB T_ D2 R P CI E_ TB T_ R2 D PCIE_TBT_R2D PCIE_TBT_R2D P CI E_ TB T_ R2 D

PCIE_85D P C IE _ 85 D PCIE_85D P C IE _ 85 D P CI E_ 85 D P CI E_ 85 D PCIE_85D P CI E_ 85 D P CI E_ 85 D P C IE _ 85 D P C IE _ 85 D P CI E_ 85 D

PCIE_RX P C IE _ RX PCIE_RX P C IE _ RX P CI E_ RX P CI E_ RX PCIE_RX P CI E_ RX P CI E_ TX P C IE _ TX P C IE _ TX P CI E_ TX

PCIE_TBT_D2R_P<0> PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_C_P<0> PCIE_TBT_D2R_C_N<0> PCIE_TBT_D2R_P<3..1> PCIE_TBT_D2R_N<3..1> PCIE_TBT_D2R_C_P<3..1> PCIE_TBT_D2R_C_N<3..1> PCIE_TBT_R2D_P<3..0> PCIE_TBT_R2D_N<3..0> PCIE_TBT_R2D_C_P<3..0> PCIE_TBT_R2D_C_N<3..0>

P CI E_ AP _R 2D P CI E_ AP _R 2D P CI E_ AP _R 2D P CI E_ AP _R 2D

P CI E_ 85 D P CI E_ 85 D P CI E_ 85 D P CI E_ 85 D

P CI E_ TX P CI E_ TX P CI E_ TX P CI E_ TX

PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N

P CI E_ AP _D 2R P CI E_ AP _D 2R

P CI E_ 85 D P CI E_ 85 D

P CI E_ RX P CI E_ RX


PCIE_CLK100M_AP CLK_PCIE_85D PCIE_CLK100M_AP CLK_PCIE_85D PCIE_CLK100M_AP CLK_PCIE_85D PCIE_CLK100M_AP CLK_PCIE_85D PCIE_CLK100M_CAM CLK_PCIE_85D PCIE_CLK100M_CAM CLK_PCIE_85D PCIE_CLK100M_CAM CLK_PCIE_85D PCIE_CLK100M_CAM CLK_PCIE_85D PCIE_CLK100M_SSD CLK_PCIE_85D PCIE_CLK100M_SSD CLK_PCIE_85D PCIE_CLK100M_TBT CLK_PCIE_85D PCIE_CLK100M_TBT CLK_PCIE_85D

CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_CAMERA_P PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_C_P PCIE_CLK100M_CAMERA_C_N PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N PCIE_CLK100M_TBT_P PCIE_CLK100M_TBT_N

PCIE_CAMERA_D2R PCIE_CAMERA_D2R P C IE _ CA M ER A _D 2 R PCIE_CAMERA_D2R PCIE_CAMERA_R2D PCIE_CAMERA_R2D PCIE_CAMERA_R2D P C IE _ CA M ER A _R 2 D

PCIE_RX P C IE _ RX P C IE _ RX PCIE_RX P C IE _ TX PCIE_TX P C IE _ TX P C IE _ TX

PCIE_CAMERA_D2R_P PCIE_CAMERA_D2R_N PCIE_CAMERA_D2R_C_P PCIE_CAMERA_D2R_C_N PCIE_CAMERA_R2D_P PCIE_CAMERA_R2D_N PCIE_CAMERA_R2D_C_P PCIE_CAMERA_R2D_C_N

12 30 68 12 30 68 30 68 30 68

14 23 68 14 23 68 23 23 14 23 68 14 23 68 23 68 23 68 23 68 23 68 14 23 68 14 23 68

CPU_CFG<19..11> CPU_CFG<10..8> CPU_CFG<7..5> CPU_CFG<4> CPU_CFG<3> CPU_CFG<2> CPU_CFG<1..0>

CPU_MEM_RESET

CPU_45S

CPU_08MIL

MEM_RESET_L

C P U_ V CC S EN S E C P U_ V CC S EN S E

C P U_ 2 7P 4 S C P U_ 2 7P 4 S

C P U _V C CS E NS E C P U _V C CS E NS E

CPU_VCCSENSE_P CPU_VCCSENSE_N

14 63 68 14 63 68

14 63 68 14 63 68

37

P CI E_ TX RX CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S CPU_45S C PU _4 5S

63 68

36 37

P CI E_ TX RX

CPU_CFG CPU_CFG_PD CPU_CFG CPU_CFG_PD CPU_CFG_3 CPU_CFG C PU _C FG _P D

C

63 68

36 37


PCIE_RX

PCIE_SSD_R2D_C_P<3..0> PCIE_SSD_R2D_C_N<3..0> PCIE_SSD_R2D_P<3..0> PCIE_SSD_R2D_N<3..0>

12 30 68

8 53


*_RX

PCIE_TX PCIE_TX PCIE_TX P C IE _ TX

12 30 68

8


PCIE_TX

PCIE_85D PCIE_85D PCIE_85D P C IE _ 85 D

D

12 30 68


?

PCIE_2OTHER

WEIGHT

CPU_PROCHOT CPU_PROCHOT CPU_CATERR

PCIE_SSD_R2D PCIE_SSD_R2D PCIE_SSD_R2D PCIE_SSD_R2D

12 30 68

6 16

=85_OHM_DIFF TABLE_SPACING_RULE_HEAD

PCIE_SSD_D2R_P<3..1> PCIE_SSD_D2R_N<3..1> PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0>

6 16

=85_OHM_DIFF

=85_OHM_DIFF

PCIE_RX PCIE_RX P C IE _ RX P C IE _ RX

6 16


=85_OHM_DIFF

PCIE_85D PCIE_85D P C IE _ 85 D P C IE _ 85 D

6 12 16


PCIE_85D

PCIE_SSD_D2R PCIE_SSD_D2R PCIE_SSD_D2R_PP PCIE_SSD_D2R_PP

6 16 6 16 6 16 6 16 6 16

63 63 12 63 68 12 63 68 12 32 68 12 32 68 31 32 31 32 12 30 68 12 30 68 12 23 68 12 23 68

6 16 6 16

20 21 22

8 53 9 53

PCIE_85D P C IE _ 85 D P C IE _ 85 D PCIE_85D P C IE _ 85 D PCIE_85D P C IE _ 85 D P C IE _ 85 D

14 32 68 14 32 68 31 32

B

31 32 31 32 31 32 14 32 14 32

A

SYNC_MASTER=J44


PAGE TITLE

CPU & PCIe Constraints DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

111 OF 120

8

7

6

5

USB 2 Interface Constraints

4


PHYSICAL_RULE_SET

LAYER

PCH_USB_RBIAS

*


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD

=STANDARD

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP



=STANDARD

=STANDARD

=STANDARD

=STANDARD USB_BT USB_BT USB_BT USB_BT


USB_85D

*

SPACING_RULE_SET

LAYER

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF


D

LINE-TO-LINE

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

USB

*

=4X_DIELECTRIC

?

*

= 6X _D IE LE CT RI C

?

USB

T O P, BO T TO M = 6 X_ D IE L EC TR I C

?

USB_RBIAS

TOP,BOTTOM=10X_DIELECTRIC

?


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



USB3_85D

*

SPACING_RULE_SET

LAYER

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF


LINE-TO-LINE


WEIGHT

SPACING

LAYER

SPACING_RULE_SET

LINE-TO-LINE

WEIGHT

SPACING


USB3_2SAME

*

=3X_DIELECTRIC

?

USB3_TXRX

*

=6X_DIELECTRIC

?


U SB 3_ 2S AM E

TOP,BOTTOM = 4x _D IE LE CT RI C

?


?



USB3_TXRX TABLE_SPACING_RULE_ITEM

USB3_2OTHER

*

=4X_DIELECTRIC

U SB U SB USB U SB

USB_BT_P USB_BT_N USB_BT_CONN_P USB_BT_CONN_N

14 29 14 29 29 63 29 63

D

USB 3 Interface Constraints LAYER

U SB _8 5D U SB _8 5D USB_85D U SB _8 5D


USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTA USB_EXTB USB_EXTB USB_TPAD USB_TPAD USB_TPAD USB_TPAD

USB_85D USB_85D D E FA U LT D E FA U LT USB_85D USB_85D USB_85D U SB _8 5D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D U SB _8 5D

USB USB D E FA U LT D E FA U LT USB USB USB U SB USB USB USB USB USB USB USB U SB

USB_EXTA_P USB_EXTA_N SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB2_EXTA_MUXED_F_P USB2_EXTA_MUXED_F_N USB_LT1_P USB_LT1_N USB_EXTB_P USB_EXTB_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N

USB3_EXTA_D2R USB3_EXTA_D2R USB3_EXTA_R2D USB3_EXTA_R2D USB3_EXTA_R2D USB3_EXTA_R2D USB3_EXTB_D2R USB3_EXTB_D2R USB3_EXTB_R2D USB3_EXTB_R2D

U S B_ 8 5D USB_85D USB_85D U S B_ 8 5D U S B_ 8 5D U S B_ 8 5D USB_85D USB_85D U S B_ 8 5D U S B_ 8 5D

U S B3 _ RX USB3_RX USB3_TX U S B3 _ TX U S B3 _ TX U S B3 _ TX USB3_RX USB3_RX U S B3 _ TX U S B3 _ TX

USB3_EXTA_D2R_P USB3_EXTA_D2R_N USB3_EXTA_R2D_P USB3_EXTA_R2D_N USB3_EXTA_R2D_C_P USB3_EXTA_R2D_C_N USB3_EXTB_D2R_P USB3_EXTB_D2R_N USB3_EXTB_R2D_C_P USB3_EXTB_R2D_C_N

USB3_SD_D2R USB3_SD_D2R USB3_SD_R2D USB3_SD_R2D

USB3_85D USB3_85D USB3_85D USB3_85D

USB3_RX USB3_RX USB3_TX USB3_TX

USB3RPCIE_SD_D2R_P USB3RPCIE_SD_D2R_N USB3RPCIE_SD_R2D_C_P USB3RPCIE_SD_R2D_C_N

USB_NC USB_NC USB_NC USB_NC USB_NC USB_NC USB_NC USB_NC

USB_85D USB_85D USB_85D USB_85D U SB _8 5D U SB _8 5D USB_85D USB_85D

USB USB USB USB U SB U SB USB USB

NC_USB_IRP NC_USB_IRN TP_USB_5P TP_USB_5N NC_USB_SDP NC_USB_SDN NC_USB_CAMERAP NC_USB_CAMERAN

USB_RBIAS

PCH_USB_RBIAS

USB_EXTA USB_EXTA

PHYSICAL_RULE_SET





1

WEIGHT


U SB _R BI AS

2


WEIGHT

SPACING

3

USB Constraints

I330


?

USB3_2OTHER


I331

?

14 33 14 33 33 36 37 33 36 37 33 33 33 33 68 68 14 63 14 63 14 34 14 34 34 34

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE


C

USB3_*

*

*

USB3_2OTHER

USB3_*

=SAME

*

U SB 3_ 2S AM E



USB3_TX

*_RX

*

U SB 3_ TX RX TABLE_SPACING_ASSIGNMENT_ITEM

USB3_RX

*_TX

*

U SB 3_ TX RX

14 33 68

C

14 33 68 33 33 68 14 33 68 14 33 68 14 63 68 14 63 68 14 63 68 14 63 68

System Clock Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET


LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



CLK_25M_45S

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD


SPACING_RULE_SET

LAYER

LINE-TO-LINE

WEIGHT

SPACING


C LK _2 5M

*

= 5x _D IE LE CT RI C

?

14 63 68 14 63 68 14 63 14 63

14 66 14 66 14 14 14 66 14 66 14 66 14 66

B

B SATA Interface Constraints (Not Used)

PCH_USB_RBIAS

PCH_USB_RBIAS

14


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

SATA_85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

SATA_45SE

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

SPACING_RULE_SET

LAYER

LINE-TO-LINE

MAXIMUM NECK LENGTH



=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=45_OHM_SE

=45_OHM_SE

SATA_85D S A TA _ 85 D S A TA _ 85 D S A TA _ 85 D


=45_OHM_SE


WEIGHT

SPACING

*

=3X_DIELECTRIC

?

LAYER

LINE-TO-LINE

SPACING

*

=6X_DIELECTRIC

?

*

=4X_DIELECTRIC

?


NET_SPACING_TYPE1

NET_SPACING_TYPE2

SATA_*

*

AREA_TYPE

?

SATA_TXRX


?

SATA_2OTHER


?


A

SATA_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

SATA_*

=SAME

*

SATA_2SAME TABLE_SPACING_ASSIGNMENT_ITEM

SATA_TX

*_RX

*

SATA_TXRX TABLE_SPACING_ASSIGNMENT_ITEM

SATA_RX

*_TX

*


SYSCLK_CLK25M SYSCLK_CLK25M SYSCLK_CLK25M

CLK_25M_45S CLK_25M_45S CLK_25M_45S

CLK_25M CLK_25M CLK_25M

SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X2 SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAM

CLK_25M_45S CLK_25M_45S CLK_25M_45S CLK_25M_45S CLK_25M_45S CLK_25M_45S

CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M CLK_25M

SYSCLK_CLK25M_CAMERA CLK25M_CAM_CLKP CLK25M_CAM_XTALP_R CLK25M_CAM_XTALP CLK25M_CAM_XTALN CLK25M_CAM_CLKN

17 17 17


*

Notes: This is here to keep the SATA rules.


TOP,BOTTOM =4x_DIELECTRIC


SATA_2OTHER

DUMMY_SATA_D2R_P DUMMY_SATA_D2R_N DUMMY_SATA_R2D_P DUMMY_SATA_R2D_N

WEIGHT

SATA_2SAME


SATA_TXRX

SATA_RX S A TA _ RX S A TA _ TX S A TA _ TX


SPACING_RULE_SET


SATA_2SAME

SATA_TXRX

17 32 31 32

A

32 32 32



USB Constraints

31 32

DRAWING NUMBER

SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT

CLK_25M_45S CLK_25M_45S

CLK_25M CLK_25M

SYSCLK_CLK25M_TBT SYSCLK_CLK25M_TBT_R

Apple Inc.

17 23 23

R

SIZE

D

REVISION


BRANCH


PAGE

112 OF 120

8

7

6

5

LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD


PHYSICAL_RULE_SET

LAYER

LPC_45S

*

=45_OHM_SE

=45_OHM_SE

C LK _L PC _4 5S

*

=45_OHM_SE

= 45 _O HM _S E

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



=45_OHM_SE

=45_OHM_SE

=STANDARD

4

=STANDARD

3


= 45 _O HM _S E

= ST AN DA RD

= ST AN DA RD


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


LPC

*

6 MIL


CLK_LPC

D

*

8 MIL

?

SMBus Interface Constraints PHYSICAL_RULE_SET



LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


=45_OHM_SE

=STANDARD

DIFFPAIR NECK GAP

LPC_AD LPC_AD LPC_CLK24M_SMC LPC_CLK24M_SMC LPC_CLK24M_LPCPLUS L PC _C LK 24 M_ LP CP LUS

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

LPC LPC CLK_LPC C L K_ L PC C L K_ L PC C LK _L PC

SMBUS_PCH SMBUS_PCH SML_PCH_0 SML_PCH_0

SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S

SMB SMB SMB SMB SMB SMB

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK HDA_BIT_CLK HDA_SYNC HDA_SYNC HDA_RST HDA_RST HDA_SDIN HDA_SDIN HDA_SDOUT HDA_SDOUT

HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S HDA_45S

HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 CS4208_HDA_SDOUT0_R HDA_SDOUT HDA_SDOUT_R

SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB SPI_MLB_IO2 SPI_MLB_IO2 SPI_MLB_IO3 SPI_MLB_IO3 SPI_MLB_IO3

SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S SPI_45S

SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI

SPI_ALT_CLK SPI_CLK SPI_CLK_R SPI_MLB_CLK SPI_SMC_CLK SPI_ALT_CS_L SPI_CS0_L SPI_CS0_R_L SPI_MLB_CS_L SPI_SMC_CS_L SPI_ALT_MISO SPI_MISO SPI_MISO_R SPI_MLB_MISO SPI_SMC_MISO SPI_ALT_MOSI SPI_MOSI SPI_MOSI_R SPI_MLB_MOSI SPI_SMC_MOSI SPI_IO<2> SPIROM_WP_L SPI_IO<3> SPIROM_HOLD_L SPIROM_USE_MLB

PCH_RTCX PCH_SRTCRST PCH_RTCRST

PCH_45S P CH _4 5S P CH _4 5S

PCH_15MIL P CH _1 5M IL P CH _1 5M IL

PCH_CLK32K_RTCX1 PCH_SRTCRST_L RTC_RESET_L

PCH_THRMTRIP PCH_THRMTRIP

P CH _4 5S P CH _4 5S

P CH _1 8M IL P CH _1 8M IL

PM_THRMTRIP_L PM_THRMTRIP_R_L

PCH_45S PCH_45S P CH _4 5S PCH_45S P CH _4 5S PCH_45S

PCH_15MIL PCH_15MIL P CH _1 5M IL PCH_15MIL P CH _1 5M IL PCH_15MIL

PCH_INTRUDER_L PCH_INTVRMEN PCH_DSWVRMEN PM_RSMRST_L PM_SYSRST_L XDP_DBRESET_L

PCH_45S PCH_45S P CH _4 5S P CH _4 5S PCH_45S PCH_45S PCH_45S

PCH_15MIL PCH_15MIL P CH _1 5M IL P CH _1 5M IL PCH_15MIL PCH_15MIL PCH_15MIL

PM_PCH_SYS_PWROK XDP_SYS_PWROK SYS_PWROK_R PM_PCH_PWROK PM_S0_PGOOD SMC_DELAYED_PWRGD PM_DSW_PWRGD

P CH _4 5S PCH_45S PCH_45S P CH _4 5S P CH _4 5S PCH_45S

P CH _1 5M IL PCH_15MIL PCH_15MIL P CH _1 5M IL P CH _1 5M IL PCH_15MIL

=STANDARD


LAYER

LINE-TO-LINE

SPACING


SMB

*

= 2 x_ D IE L EC T RI C

?

HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET


LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



HDA_45S

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD

LPC_AD<3..0> LPC_FRAME_L LPC_CLK24M_SMC_R LPC_CLK24M_SMC LPC_CLK24M_LPCPLUS LPC_CLK24M_LPCPLUS_R

LPC_45S LPC_45S CLK_LPC_45S C L K_ L PC _ 45 S C L K_ L PC _ 45 S CLK_LPC_45S


SMB_45S SPACING_RULE_SET

1



= 45 _O HM _S E

2

PCH Net Properties 14 36 45 68 14 36 45 68 12 17 17 36 68 17 45 68 12 17

D

14 16 19 39 63 68 14 16 19 39 63 68 14 39 14 39 14 32 36 39 43 68 76 14 32 36 39 43 68 76

12 47 12 12 47 12 12 12 47 12 47 68 47 12 47 12 17


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


H DA

*

= 2x_ DIEL ECT RIC

?

SPI Interface Constraints PHYSICAL_RULE_SET

LAYER



MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



SPI_45S

C

*

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=45_OHM_SE

=STANDARD

=STANDARD


SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


SPI

*

8 MIL

?

PCH Single Net Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



PCH_ 45S

*

=45_OHM_SE

=45 _OHM _SE

PCH_27P4S

*

=27P4_OHM_SE

=45_ OHM_ SE

=45_O HM_S E

=27P4_OHM_SE

=27P4_OHM_SE

=STA NDAR D

= STAN DARD TABLE_PHYSICAL_RULE_ITEM

=27P4_OHM_SE TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING


PCH_12MIL

*

0.305 MM


PCH_15MIL

*

0.381 MM


PCH_18MIL

*

0.457 MM

?

7 MIL

7 MIL

45 45 14 45 45 36 45 45 45 14 45

C

45 36 45 45 14 45 45 45 36 45 45 45 14 45 45 36 45 14 45 45 14 45 45 15 45 68


PCH_20MIL

B

*

0.508 MM

?

A

PM_PWRBTN_L XDP_CPU_PWRBTN_L PCIE_WAKE_L AP_PCIE_WAKE_L CAM_PCIE_WAKE_L TBT_CIO_PLUG_EVENT_L

B

12 17 12 12

15 37 37

12 12 13 13 61 13 17 36 68 16 17

13 16 17 36 16 17 13 17 17 17 24 25 36 37 13 36

13 16 36 16

A

13 29 31 29 63 31



PCH Constraints

15 18 23

DRAWING NUMBER

PCH_CLK24M_XTAL PCH_CLK24M_XTAL PCH_CLK24M_XTAL PCH_RCOMP_PCIE PCH_RCOMP_OPI PCH_RCOMP_SATA

PCH_45S P CH _4 5S P CH _4 5S PCH_27P4S PCH_27P4S PCH_27P4S

PCH_20MIL P CH _2 0M IL P CH _2 0M IL PCH_12MIL PCH_12MIL PCH_12MIL

PCH_CLK24M_XTALIN PCH_CLK24M_XTALOUT PCH_CLK24M_XTALOUT_R PCH_PCIE_RCOMP PCH_OPI_COMP PCH_SATA_RCOMP

Apple Inc.

12 17 12 17

R 17

14 15

SIZE

D

REVISION


BRANCH


PAGE

113 OF 120

8

7

6

5

Memory Bus Constraints

4

LAYER


M E M _ 4 0S

*

=40_OHM_SE

M E M _ 7 2D

*

=72_OHM_DIFF

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

= 4 0 _ O H M _ SE

=4 0 _ O H M_ SE

= 4 0_ O H M _S E


= S T AN D A RD

DIFFPAIR NECK GAP

=S T A N DA R D

=72_OHM_DIFF

= 72 _ O H M_ D I FF

= 72 _O H M _ DI FF

=72_OHM_DIFF




=72_OHM_DIFF


*

2

1


PHYSICAL_RULE_SET

MEM_45S

3

Memory Net Properties

= 4 5_ O H M _SE

=45_OHM_SE

= =4 45_O 5_ OHM_ HM _SE SE

= =4 45_O 5_ OHM_ HM _SE SE

= S T AN D A RD

= S T A N DA R D


MEM_A_CLK M EM _A _C LK M EM _A _C TL

M E M_ 7 2D M EM _7 2D M EM _4 0S

M E M_ C LK M EM _C LK MEM_CTL

MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CKE<0>

M EM _A _C TL

M EM _4 0S

MEM_CTL

MEM_A_CS_L<0>

7 20 22

MEM_A_ODT0

MEM_40S

MEM_CTL

MEM_A_ODT<0>

20 22

MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQBYTE0 MEM_A_DQBYTE1 MEM_A_DQBYTE2 MEM_A_DQBYTE3 MEM_A_DQBYTE4 MEM_A_DQBYTE5 MEM_A_DQBYTE6 MEM_A_DQBYTE7 MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 M EM EM _A _D _D QS 6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_45S MEM_45S M E M_ 4 5S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D MEM_80D M EM EM _8 0D 0D MEM_80D MEM_80D MEM_80D

MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_DQBYTE_0 MEM_A_DQBYTE_1 M E M_ A _D Q BY T E_ 2 MEM_A_DQBYTE_3 MEM_A_DQBYTE_4 MEM_A_DQBYTE_5 MEM_A_DQBYTE_6 MEM_A_DQBYTE_7 MEM_A_DQS_0 MEM_A_DQS_0 MEM_A_DQS_1 MEM_A_DQS_1 MEM_A_DQS_2 MEM_A_DQS_2 MEM_A_DQS_3 MEM_A_DQS_3 MEM_A_DQS_4 MEM_A_DQS_4 MEM_A_DQS_5 MEM_A_DQS_5 M EM _A _A _D QS QS _6 MEM_A_DQS_6 MEM_A_DQS_7 MEM_A_DQS_7

MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK MEM_B_CLK M EM _B _C TL

MEM_72D MEM_72D M EM _4 0S

MEM_CLK MEM_CLK MEM_CTL

MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CKE<0>

MEM_B_CTL

MEM_40S

MEM_CTL

MEM_B_CS_L<0>

7 21 22

MEM_B_ODT0

MEM_40S

MEM_CTL

MEM_B_ODT<0>

21 22

M EM _B _C MD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD M EM _B _DQ BYT E0 M EM _B _DQ BYT E1 M EM _B _DQ BYT E2 M EM _B _DQ BYT E3 M EM _B _DQ BYT E4 M E M_ B _D Q BY T E5 M E M_ B _D Q BY T E6 M EM _B _DQ BYT E7 MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 M EM EM _B _D _D QS 3 MEM_B_DQS3 MEM_B_DQS4 M EM _B _D QS 4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

M EM _4 0S M E M_ 4 0S M E M_ 4 0S M E M_ 4 0S M E M_ 4 0S MEM_45S MEM_45S MEM_45S MEM_45S MEM_45S M E M_ 4 5S M E M_ 4 5S MEM_45S M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D M EM EM _8 0D 0D M E M_ 8 0D M E M_ 8 0D M EM _8 0D MEM_80D M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D M E M_ 8 0D

M EM _C MD M E M_ C MD M E M_ C MD M E M_ C MD M E M_ C MD M EM _B _D QB YT E_ 0 M EM _B _D QB YT E_ 1 M EM _B _D QB YT E_ 2 M EM _B _D QB YT E_ 3 M EM _B _D QB YT E_ 4 MEM_B_DQBYTE_5 MEM_B_DQBYTE_6 M EM _B _D QB YT E_ 7 M E M_ B _D Q S_ 0 M E M_ B _D Q S_ 0 M E M_ B _D Q S_ 1 M E M_ B _D Q S_ 1 M E M_ B _D Q S_ 2 M E M_ B _D Q S_ 2 M EM _B _B _D QS QS _3 M E M_ B _D Q S_ 3 M E M_ B _D Q S_ 4 MEM_B_DQS_4 MEM_B_DQS_5 M E M_ B _D Q S_ 5 M E M_ B _D Q S_ 6 M E M_ B _D Q S_ 6 M E M_ B _D Q S_ 7 M E M_ B _D Q S_ 7

MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

MEM_PWR MEM_PWR MEM_PWR MEM_PWR

PP1V35_S3 PP1V35_S3_CPUDDR PP0V675_S0_DDRVTT PPVTTDDR_S3

MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL

CPU_DIMMA_VREFDQ CPU_DIMMA_VREFDQ_A_ISOL CPU_DIMMB_VREFDQ CPU_DIMMB_VREFDQ_B_ISOL CPU_DIMM_VREFCA CPU_DIMM_VREFCA_A_ISOL CPU_DIMM_VREFCA_B_ISOL

7 20 22 7 20 22 7 20 22


MEM_80D

*

=80_OHM_DIFF

= 80 80 _O _O HM HM _D _D IF IF F

= 80 80 _O _O HM HM _D _D IF IF F

= 8 0 _O H M _ DI FF

= 80 80 _O _O HM HM _D _D IF IF F

=80_OHM_DIFF

MEM_50S

*

=50_OHM_SE

=50_OH M_SE

=50_OHM_SE

=50_OHM_SE

= S T AN D A RD

= S T A N DA R D

MEM_85D

*

=85_OHM_DIFF

= 85 85 _O _O HM HM _D _D IF IF F

= 85 85 _O _O HM HM _D _D IF IF F

=85_OHM_DIFF

= 85 85 _O _O HM HM _D _D IF IF F

= 85 85 _O _O HM HM _D IF IF F



D

Spacing Rule Sets TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LINE-TO-LINE

LAYER

SPACING


WEIGHT

LAYER

SPACING_RULE_SET

LINE-TO-LINE

SPACING

WEIGHT


MEM_DATA2SELF

*

=2x_DIELECTRIC

?

MEM_DQS2OWNDATA

*

=2x_DIELECTRIC

?


M EM EM _D _D AT AT A2 A2 SE SE LF LF

TOP,BOTTOM

= 5x 5x _D _D IE IE LE LE CT CT RI RI C

?

MEM_DQS2OWNDATA

TOP,BOTTOM

=5x_DIELECTRIC

?




MEM_CMD2CMD

*

MEM_CMD2CTL

*

=2x_DIELECTRIC

?

=2x_DIELECTRIC

?


MEM_CMD2CMD

TOP,BOTTOM

=5x_DIELECTRIC

?

MEM_CMD2CTL

TOP,BOTTOM

=5x_DIELECTRIC

?




MEM_CTL2CTL

=2x_DIELECTRIC

*


MEM_CTL2CTL

?

TOP,BOTTOM

=5x_DIELECTRIC

?


MEM_CLK2CLK

=4x_DIELECTRIC

*


MEM_CLK2CLK

?

TOP,BOTTOM

=8x_DIELECTRIC

?


MEM_2OTHERMEM

=4x_DIELECTRIC

*


MEM_2OTHERMEM

?

TOP,BOTTOM

=8x_DIELECTRIC

?


M EM _2 PW R

*


?

MEM_2GND

*

=2x_DIELECTRIC

?


MEM_2PWR

TOP,BOTTOM

=4x_DIELECTRIC

?

MEM_2GND

TOP,BOTTOM

=4x_DIELECTRIC

?




MEM_2OTHER

*

=6x_DIELECTRIC

?

MEM_ CMD2C M D_BM

*

=2x_DIELECTRIC

?


MEM_2OTHER


?



M EM_CMD2CMD_BM TOP,BOTTOM

=3x_DIELECTRIC

?


MEM_ CMD2C T L_BM

*


?


M EM_CMD2CTL_BM TOP,BOTTOM

=3x_DIELECTRIC

?


MEM_ CTL2C T L_BM

*

=2x_DIELECTRIC

?

M E M _ 1 2 M IL

*

0.305 MM

?


M EM_CTL2CTL_BM TOP,BOTTOM

=3x_DIELECTRIC

?


C Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET


MEM_*_DQBYTE_*

*

*

MEM_2OTHER


M EM _ A _ DQ S_ 0

MEM_A_DQBYTE_0

*

MEM_DQS2OWNDATA

M EM _ A _ DQ S_ 1

MEM_A_DQBYTE_1

*

MEM_DQS2OWNDATA

MEM_A_DQS_2

MEM_A_DQBYTE_2

*

MEM_DQS2OWNDATA


M E M _ * _ D Q S _*

*

*

MEM_CMD

*

*

M E M _ 2O T H E R



MEM_2OTHER

*

*

MEM_2OTHER

MEM_CLK

*

*

MEM_2OTHER

7 20 22 66 7 20 22 66 7 20 22 66 7 20 22 66 7 67 68 7 67 68 7 67 68 7 67 68 7 20 67 68 7 67 68 7 67 68 7 67 68 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67

C

7 20 67 7 20 67 7 67 7 67

7 21 22 7 21 22 7 21 22



MEM_CTL

D

7 20 22 66


MEM_A_DQS_3

MEM_A_DQBYTE_3

*

MEM_DQS2OWNDATA

MEM_A_DQS_4

MEM_A_DQBYTE_4

*

MEM_DQS2OWNDATA




MEM_A_DQS_5

MEM_A_DQBYTE_5

*

MEM_DQS2OWNDATA

MEM_A_DQS_6

MEM_A_DQBYTE_6

*

MEM_DQS2OWNDATA

MEM_A_DQS_7

MEM_A_DQBYTE_7

*

MEM_DQS2OWNDATA

MEM_B_DQS_0

MEM_B_DQBYTE_0

*

MEM_DQS2OWNDATA


NET_SPACING_TYPE1

NET_SPACING_TYPE2

MEM_*_DQBYTE_*

=SAME

AREA_TYPE

SPACING_RULE_SET



*

MEM_DATA2SELF




MEM_B_DQS_1

MEM_B_DQBYTE_1

*

MEM_DQS2OWNDATA


NET_SPACING_TYPE1

NET_SPACING_TYPE2

M EM EM _C _C MD MD

M EM EM _C _C MD MD

AREA_TYPE

SPACING_RULE_SET


MEM_B_DQS_2

MEM_B_DQBYTE_2

*

MEM_DQS2OWNDATA

MEM_B_DQS_3

MEM_B_DQBYTE_3

*

MEM_DQS2OWNDATA


*

MEM_CMD2CMD



MEM_CMD

M E M _ C TL

MEM _CMD2CTL

*


MEM_B_DQS_4

MEM_B_DQBYTE_4

*

MEM_DQS2OWNDATA


M E M _ C TL

MEM_C TL

*

MEM _CTL2CTL


M EM _ B _ DQ S_ 5

MEM_B_DQBYTE_5

*

MEM_DQS2OWNDATA


B

M EM _C LK

M EM _C LK

*

M EM _C _C LK 2C LK


M EM _ B _ DQ S_ 6

MEM_B_DQBYTE_6

*

MEM_DQS2OWNDATA


MEM_*

M E M _*

*

ME MEM_2OTHERMEM

M E M _ C MD

MEM_CMD

BGA_MEM

M E M _C M D 2 CM D _ B M


M EM _ B _ DQ S_ 7

MEM_B_DQBYTE_7

*

MEM_DQS2OWNDATA



M E M _ C MD

M EM EM _C _C TL TL

BG A _ M EM

M EM EM _C _C MD MD 2C 2C TL TL _B _B M TABLE_SPACING_ASSIGNMENT_ITEM

M EM _C TL

M EM _C TL

BGA_MEM

M EM _C TL 2C TL _B M

Haswell ULT Memory Down DDR3L 1x8 Length Matching DDR3 Signal Group

Unit

Min Length

Max Length

CTLmax - CTLmin CTL to CLK CMDi to CMDj CMD to CLK (DQmax - DQmin) per byte (DQS - DQmax) per byte DQS to DQS# DQS to CLK (Rule 1) Max(CLK-DQS) - Min(CLK-DQS) CLK to CLK#

mils mils mils mils mils mils mils mils mils mils

0 CLK - 500 CMDj - 100 CLK - 500 0 -100 -5 CLK - 6500 0 -5

100 CLK + 500 CMDj + 100 CLK + 500 250 150 5 CLK + 500 5500 5

A Memory to Power Spacing


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

I146

7 21 22 66 7 21 22 66 7 21 22 66 7 21 22 66 7 21 22 66 7 67 68 7 67 68 7 67 68 7 67 68 7 21 67 68 7 67 68 7 67 68 7 67 68 7 67

B

7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 67 7 21 67 7 21 67 7 67 7 67

17 19 20 21 22 41 55

65

8 10 41 65 22 55 65 68 55 65 68

7 19 19

7 19 19

19


M E M _ P WR

M E M _*

*

MEM_PWR

*

*

MEM_2PWR TABLE_SPACING_ASSIGNMENT_ITEM

DEFAULT

Memory to GND Spacing TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_12MIL MEM_12MIL MEM_12MIL MEM_12MIL

PP0V675_S3_MEM_VREFDQ_A PP0V675_S3_MEM_VREFDQ_B PP0V675_S3_MEM_VREFCA_A PP0V675_S3_MEM_VREFCA_B

A

7 19 19

SYNC_MASTER=J44


PAGE TITLE

Memory Constraints DRAWING NUMBER

19 20 65

Apple Inc.

19 21 65 19 20 65 19 21 65

R

SIZE

D

REVISION


BRANCH


PAGE

114 OF 120

8

7

6

5

4 ELECTRICAL CONST SET

Thunderbolt SPI Signal Constraints TABLE_PHYSICAL_RULE_HEAD


LAYER

PHYSICAL_RULE_SET

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



T BT BT _S _S PI PI _4 _4 5S 5S

*

= 45 45 _O _O HM HM _S _S E

= 4 5 _ O H M _ SE

=4 5 _ O HM _ SE

= 4 5_ O H M _SE

= S T AN D A RD

=S T A N DA R D


SPACING_RULE_SET

LAYER

TBT_SPI

*

LINE-TO-LINE

WEIGHT

SPACING


D

=2x_DIELECTRIC

?

Thunderbolt & DisplayPort Constraints

I355 I354 TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

T BT BT DP DP _8 _8 5D 5D

*


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

= 85 85 _O _O HM HM _D _D IF IF F

= 85 85 _O _O HM HM _D _D IF IF F

3

MAXIMUM NECK LENGTH

= 85 85 _O _O HM HM _D _D IF IF F


DIFFPAIR NECK GAP

= 85 85 _O _O HM HM _D _D IF IF F

I353 I352

=85_OHM_DIFF


LAYER

SPACING_RULE_SET

LINE-TO-LINE


WEIGHT

SPACING

LAYER

SPACING_RULE_SET

LINE-TO-LINE

SPACING

WEIGHT


TBTDP_2SAME

*

=3X_DIELECTRIC

?

TBTDP_TXRX

*

=6X_DIELECTRIC

?

TBTDP_2OTHER

*

=4X_DIELECTRIC

?


TBTDP_2SAME

TOP,BOTTOM

= =4 4x_D x_ DIEL IE LECT EC TRIC RI C

?


I343 TABLE_SPACING_RULE_ITEM

TBTDP_TXRX

TOP,BOTTOM = =1 10X_ 0X _DIE DIE LEC CT TRIC RI C

?

TOP,BOTTOM

?


I342 I341


T B T DP _ 2 O TH ER

=6X_DIELECTRIC

I340


AREA_TYPE

NET_SPACING_TYPE1

NET_SPACING_TYPE2

TBTDP_*

*

*

TB TBTDP_2OTHER

T B T D P _*

= S AME

*

TB TDP_2SAME

T B T D P _ TX

*_RX

*

TB T D P _ TX R X




TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D

TBTDP_TX TBTDP_TX TBTDP_TX TBTDP_TX

TBT_A_R2D_C_P<1..0> TBT_A_R2D_C_N<1..0> TBT_A_R2D_P<1..0> TBT_A_R2D_N<1..0>

DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_A_LSX_ML DP_TBTPA_ML DP_TBTPA_ML DP_TBTPA_ML DP_TBTPA_ML

DP_85D DP_85D DP_85D D P _8 5 D D P _8 5 D DP_85D DP_85D DP_85D DP_85D DP_85D

DISPLAYPORT DISPLAYPORT DISPLAYPORT D I SP L AY P OR T D I SP L AY P OR T DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DP_TBTPA_ML_C_P<1> DP_TBTPA_ML_C_N<1> DP_TBTPA_ML_P<1> DP_TBTPA_ML_N<1> DP_A_LSX_ML_P<1> DP_A_LSX_ML_N<1> DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3> DP_TBTPA_ML_P<3> DP_TBTPA_ML_N<3>

TBT_A_D2R_0 TBT_A_D2R_0 TBT_A_D2R_0 TBT_A_D2R_0 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1 TBT_A_D2R_1

TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D

TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX

TBT_A_D2R_C_P<0> TBT_A_D2R_C_N<0> TBT_A_D2R_P<0> TBT_A_D2R_N<0> TBT_A_D2R_C_P<1> TBT_A_D2R_C_N<1> TBT_A_D2R_P<1> TBT_A_D2R_N<1> TBT_A_D2R1_AUXDDC_P TBT_A_D2R1_AUXDDC_N

DP_TBTPA_AUXCH DP_TBTPA_AUXCH DP_TBTPA_AUXCH DP_TBTPA_AUXCH

DP_85D DP_85D DP_85D DP_85D

DP_TBTPA_AUXCH_C_P DP_TBTPA_AUXCH_C_N DP_TBTPA_AUXCH_P DP_TBTPA_AUXCH_N

23 26 68 23 26 68 26 68 26 68

23 26 23 26 26

C

*_TX

*

26 26 23 26 23 26 26 26

26 68 26 68 23 26 68 23 26 68 26 68 26 68 23 26 68 23 26 68 26 26

23 26 23 26 26 26

Notes: AUX and DDC was removed from DISPLAYPORT or TBTDP_RX/TX because it’s not high speed, and to save routing space.

TB T D P _ TX R X

DisplayPort & HDMI Constraints LAYER

D P_ P_ 85 85 D

*

=85_OHM_DIFF

H DM DM I_ I_ 85 D

*

=85_OHM_DIFF

SPACING_RULE_SET

LAYER

LINE-TO-LINE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

= 85 85 _O _O HM HM _D _D IF IF F

= 85 85 _O _O HM HM _D _D IF IF F

MAXIMUM NECK LENGTH

= 85 85 _O _O HM HM _D _D IF IF F


DIFFPAIR NECK GAP

= 85 85 _O _O HM HM _D _D IF IF F

=85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM

= 85 85 _O _O HM HM _D _D IF IF F

= 85 85 _O _O HM HM _D _D IF IF F

= 85 85 _O _O HM HM _D _D IF IF F

=8 =8 5_ 5_ OH OH M_ M_ DI DI FF FF

=85_OHM_DIFF


WEIGHT

SPACING


LAYER

SPACING_RULE_SET

LINE-TO-LINE

SPACING

WEIGHT


D P_ 2S AM E

*


?

D P_ 2O TH ER

*


?


D DP P_2S _2 SAME AM E

T TO OP,B P, BOTT OT TOM OM

=4x x_ _DIE DI ELEC LE CTRI TRI C

?

D DP P_2O _2 OTHE THE R


= =6x 6x_D _ DIEL IE LECT EC TRIC RI C

?




*

HDMICLK_2OTHER


?


HDMICLK_2OTHER


= =10 10x x_ _DIE DIE LEC CT TRIC RI C

?


*

HDMICLK_2DPHDMI


?


HDMICLK_2DPHDMI


= =6x 6x_ _D DIEL IE LECT EC TRIC RI C

?


HDMIDATA_2SAME

*


?

HDMIDATA_2OTHER

*


?

HDMIDATA_2SAME

NET_SPACING_TYPE2

H D M I _ D A TA

*

AREA_TYPE


= =4x 4x_ _D DIEL IE LECT EC TRIC RI C

?

TOP,BOTTOM

= =6 6x_D x_ DIEL IE LECT EC TRIC RI C

?

SPACING_RULE_SET

HDMIDATA_2OTHER

NET_SPACING_TYPE2

D I S P L AY PO R T

*

AREA_TYPE

= SA ME

*

HDMIDATA_2SAME

SPACING_RULE_SET

D P _2 O T H ER

T BT DP _T X

*

HDMIDATA_2SAME

DISPLAYPORT

=SAME

*

DP_2SAME TABLE_SPACING_ASSIGNMENT_ITEM

DISPLAYPORT

HD M I _ DA TA

*

DP_2SAME


H DM I_ DA TA

T BT DP _R X

*

H D M I _ C LK

*

*

H DM I_ CL K

H DM I_ DA TA

*

T BT DP _T XR X

I346 I344 I345


DISPLAYPORT

TBTDP_TX

*

DP_2SAME

DISPLAYPORT

TBTDP_RX

*

TBTDP_TXRX


HDMICLK_2OTHER

I347



H DM I_ DA TA

I349


*


H D M I _ D A TA

I348


NET_SPACING_TYPE1


*

I350


HDMIDATA_2OTHER


NET_SPACING_TYPE1

I351





HDMICLK_2DPHDMI TABLE_SPACING_ASSIGNMENT_ITEM

H DM DM I_ I_ CL CL K

D IS IS PL PL AY AY PO PO RT RT

*

HDMICLK_2DPHDMI

H D M I _ C LK

TBTDP_TX

*

HDMICLK_2DPHDMI


DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. DisplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm. SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04. MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES. NET TYPE PHYSICAL SPACING

I338

I336 I337 I335


DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DP_TBTSRC_ML_C_P<3..0> DP_TBTSRC_ML_C_N<3..0> DP_TBTSRC_AUXCH_C_P DP_TBTSRC_AUXCH_C_N

I334 I324

Only used on hosts supporting Thunderbolt video-in

I333

I332 I330

I315 I314 I313 I312

SPI_TBT_CLK SPI_TBT_MOSI SPI_TBT_MISO SPI_TBT_CS_L

TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S TBT_SPI_45S

TBT_SPI TBT_SPI TBT_SPI TBT_SPI

TBT_SPI_CLK TBT_SPI_MOSI TBT_SPI_MISO TBT_SPI_CS_L

DP_HDMI_TBT_ML D P_ HD MI _T BT _M L DP_HDMI_TBT_AUX DP_HDMI_TBT_AUX


DISPLAYPORT D IS PL AY POR T

DP_HDMI_TBT_ML_P<3..0> DP_HDMI_TBT_ML_N<3..0> DP_HDMI_TBT_AUX_P DP_HDMI_TBT_AUX_N

23

I331

23

I328

23

I329

23

I327 I325

64 66

I326

I311 I310

HDMI_CLOCK HDMI_CLOCK HDMI_DATA HDMI_DATA

HDMI_85D HDMI_85D HDMI_85D HDMI_85D

HDMI_CLK HDMI_CLK HDMI_DATA HDMI_DATA

HDMI_IG_CLK_C_P HDMI_IG_CLK_C_N HDMI_IG_DATA_C_P<2..0> HDMI_IG_DATA_C_N<2..0>

TBTDP_TX TBTDP_TX TBTDP_TX T BT DP _T X

DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML DP_B_LSX_ML D P_ P_ TB TP TP B_ ML ML DP_TBTPB_ML DP_TBTPB_ML D P_ P_ TB TP TP B_ ML ML

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D D P_ P_ 85 D DP_85D DP_85D D P_ P_ 85 D

TBT_B_D2R_0 TBT_B_D2R_0 TBT_B_D2R_0 TBT_B_D2R_0 TBT_B_D2R_1 TBT_B_D2R_1 TBT_B_D2R_1 TBT_B_D2R_1 T BT BT _B _D _D 2R _1 _1 T BT BT _B _D _D 2R _1 _1

TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D TBTDP_85D T BT BT DP _8 5D 5D T BT BT DP _8 5D 5D

DP_TBTPB_AUXCH DP_TBTPB_AUXCH DP_TBTPB_AUXCH DP_TBTPB_AUXCH


DP_TBTSNK0_ML DP_TBTSNK0_ML DP_TBTSNK0_ML DP_TBTSNK0_ML DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH

D P _8 5 D D P _8 5 D D P _8 5 D D P _8 5 D DP_85D DP_85D DP_85D DP_85D

D I SP L AY P OR T D I SP L AY P OR T D I SP L AY P OR T D I SP L AY P OR T

DP_TBTSNK1_ML DP_TBTSNK1_ML DP_TBTSNK1_ML DP_TBTSNK1_ML DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH DP_TBTSNK_AUXCH

D P _8 5 D D P _8 5 D D P _8 5 D D P _8 5 D DP_85D DP_85D DP_85D DP_85D

D I SP L AY P OR T D I SP L AY P OR T D I SP L AY P OR T D I SP L AY P OR T

D P_ IN T_ ML D P_ IN T_ ML DP_INT_ML DP_INT_ML DP_INT_AUXCH DP_INT_AUXCH DP_INT_AUXCH DP_INT_AUXCH

D P_ 85 D D P_ 85 D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

D IS PL AY PO RT D IS PL AY PO RT DISPLAYPORT DISPLAYPORT

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT D IS PL PL AY PO PO RT DISPLAYPORT DISPLAYPORT D IS PL PL AY PO PO RT TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX TBTDP_RX T BT BT DP _R X T BT BT DP _R X

TBT_B_R2D_C_P<1..0> TBT_B_R2D_C_N<1..0> TBT_B_R2D_P<1..0> TBT_B_R2D_N<1..0> DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1> DP_TBTPB_ML_P<1> DP_TBTPB_ML_N<1> DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1> DP_TBTPB_ML_C_P<3> DP_TBTPB_ML_C_N<3> DP_TBTPB_ML_P<3> DP_TBTPB_ML_N<3> TBT_B_D2R_C_P<0> TBT_B_D2R_C_N<0> TBT_B_D2R_P<0> TBT_B_D2R_N<0> TBT_B_D2R_C_P<1> TBT_B_D2R_C_N<1> TBT_B_D2R_P<1> TBT_B_D2R_N<1> TBT_B_D2R1_AUXDDC_P TBT_B_D2R1_AUXDDC_N DP_TBTPB_AUXCH_C_P DP_TBTPB_AUXCH_C_N DP_TBTPB_AUXCH_P DP_TBTPB_AUXCH_N

23 27 68 23 27 68 27 68 27 68

23 27 23 27 27 27 27 27 23 27 23 27 27 27

27 68 23 27 68 23 27 68 27 68 27 68 23 27 68 23 27 68 27 27

23 27 27 27

DP_TBTSNK0_ML_C_P<3..0> DP_TBTSNK0_ML_C_N<3..0> DP_TBTSNK0_ML_P<3..0> DP_TBTSNK0_ML_N<3..0> DP_TBTSNK0_AUXCH_C_P DP_TBTSNK0_AUXCH_C_N DP_TBTSNK0_AUXCH_P DP_TBTSNK0_AUXCH_N DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_N<3..0> DP_TBTSNK1_ML_P<3..0> DP_TBTSNK1_ML_N<3..0> DP_TBTSNK1_AUXCH_C_P DP_TBTSNK1_AUXCH_C_N DP_TBTSNK1_AUXCH_P DP_TBTSNK1_AUXCH_N

5 23 5 23 23 23 13 23 13 23 23 23

23 64 23 64 23 23 23 64 23 64 23 23

A


PAGE TITLE

I318

63 64 68

I319

63 64 68

I320

63 64 68

B

23 27

SYNC_MASTER=J44

13 64 66

63 64 68

Only used on dual-port hosts.

27 68

13 64 66

I317

I308

TBTDP_85D TBTDP_85D TBTDP_85D T BT DP _8 5D

64 66

I316

I309

TBT_B_R2D TBT_B_R2D TBT_B_R2D T BT _B _R 2D

Max Length 241.3mm.

I339


A

C



PHYSICAL_RULE_SET


B

D

26


T B T D P _ RX

1


TBT_A_R2D TBT_A_R2D TBT_A_R2D TBT_A_R2D


=85_OHM_DIFF

2

Thunderbolt, DP, HDMI Net Properties

Thunderbolt, DP, HDMI Constraints

I321 I322 I323

DP_INT_ML_C_P<3..0> DP_INT_ML_C_N<3..0> DP_INT_ML_P<3..0> DP_INT_ML_N<3..0> DP_INT_AUXCH_C_P DP_INT_AUXCH_C_N DP_INT_AUX_P DP_INT_AUX_N

5 62

TBT,DP,HDMI Constraints DRAWING NUMBER

5 62

Apple Inc.

62 68 62 68

R 5 62 5 62 62 68 62 68

SIZE

D

REVISION


BRANCH


PAGE

115 OF 120

8

7

6

5

4

3

2

1

Camera Net Properties ELECTRICAL CONST SET

MIPI Interface Constraints


S2_MEM_CLK S2_MEM_CLK

S2_MEM_85D S2_MEM_85D

S2_MEM_CLK S2_MEM_CLK

MEM_CAM_CLK_P MEM_CAM_CLK_N

S2_MEM_CKE S2_MEM_CS S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S 2 _M E M_ D QS 0 S2_MEM_DQS0 S2_MEM_DQS1 S2_MEM_DQS1 S 2_ MEM _DA TA _0 S2_MEM_DATA_1 S2_MEM_A

S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S2_MEM_45S S 2 _M E M_ 8 5D S2_MEM_85D S2_MEM_85D S2_MEM_85D S2_MEM_45S S2_MEM_45S S2_MEM_45S

S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CTRL S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S2_MEM_CMD S 2 _M E M_ D QS 0 S2_MEM_DQS0 S2_MEM_DQS1 S2_MEM_DQS1 S 2_M EM _D ATA 0 S2_MEM_DATA1 S2_MEM_CMD

MEM_CAM_CKE MEM_CAM_CS_L MEM_CAM_ODT MEM_CAM_CAS_L MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2> MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0> MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1> MEM_CAM_DM<0> MEM_CAM_DM<1> MEM_CAM_A<14..0>

S2_MEM_DATA_0 S 2_ MEM _DA TA _1

S2_MEM_45S S2_MEM_45S

S2_MEM_DATA0 S 2_M EM _D ATA 1

MEM_CAM_DQ<7..0> MEM_CAM_DQ<15..8>

MIPI_DATA_S2 M IP I_ I_ DA TA TA _S 2 MIPI_DATA_S2 MIPI_DATA_S2

MIPI_85D M IP I_ I_ 85 D MIPI_85D MIPI_85D

MIPI_DATA M IP IP I_ DA TA TA MIPI_DATA MIPI_DATA

MIPI_DATA_P MIPI_DATA_N MIPI_DATA_CONN_P MIPI_DATA_CONN_N

MIPI_CLK_S2 MIPI_CLK_S2 MIPI_CLK_S2 MIPI_CLK_S2

MIPI_85D MIPI_85D MIPI_85D MIPI_85D

CLK_MIPI CLK_MIPI CLK_MIPI CLK_MIPI

MIPI_CLK_P MIPI_CLK_N MIPI_CLK_CONN_P MIPI_CLK_CONN_N

S2_MEM_PWR S2_MEM_PWR S2_MEM_PWR S2_MEM_PWR

PP1V35_CAM PP0V675_CAM_VREF PP0V675_MEM_CAM_VREFCA PP0V675_MEM_CAM_VREFDQ

31 32 31 32


PHYSICAL_RULE_SET


LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=85_ OHM_ DIFF

= 8 5 _O H M_D IFF

= 85_O HM_DI FF



D

MIPI _85D

*

=85_OHM_DIFF

=85_OHM_DIFF

=8 5_OH M_DIF F


SPACING_RULE_SET

LAYER

LINE-TO-LINE


WEIGHT

SPACING

LAYER

SPACING_RULE_SET

LINE-TO-LINE

WEIGHT

SPACING


MIPI_2OTHER

*

=4X_DIE =4X_DIELECTRIC LECTRIC

?

MIPI_2CLK

*


?

MIPICLK_2OTHER

*


?


MIPI_2OTHER


?

MIPI_2CLK


?


?





MIPICLK_2OTHER TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE


MIPI _DAT A

*

*

MI M I P I _2 O T H E R TABLE_SPACING_ASSIGNMENT_ITEM

M IP I_ I_ DA TA TA

C LK LK _M IP IP I

*

M IP IP I_ 2C LK LK TABLE_SPACING_ASSIGNMENT_ITEM

CLK _MIP I

*

*

MIPICLK_2OTHER

Memory Bus Constraints TABLE_PHYSICAL_RULE_HEAD


PHYSICAL_RULE_SET

LAYER

S 2_ME M_45 S

*

=45_OHM_SE

= 45 _ O HM _SE

=4 5 _ OH M _ SE

= 4 5_ O H M _S E

S 2 _M E M_ 85 85 D

*

=85_OHM_DIFF

= 85 85 _ OH M_ M_ D IF F

= 85 85 _O _O H M_ D IF F

= 8 5_ O HM _D _D I FF

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



=STANDARD

= S T A N D AR D TABLE_PHYSICAL_RULE_ITEM

C

=8 =8 5_ 5_ OH OH M _D I FF


LAYER

LINE-TO-LINE

SPACING

WEIGHT

*


?

LINE-TO-LINE

WEIGHT

SPACING


S2_DATA2SELF TOP,BOTTOM =4x_DIELECTRIC

?


S2_DQS2OWNDATA

*


?

S 2_ 2_ CM CM D2 D2 CM CM D

*


?

S 2_ 2_ CM CM D2 D2 CT CT RL RL

*


?


S2_DQS2OWNDATA TOP,BOTTOM =4x_DIELECTRIC

?



S2_CMD2CMD


S2_CMD2CTRL


*


?


?

*


?

S2_CTRL2CTRL TOP,BOTTOM =4x_DIELECTRIC

*


?

*


?

31 32 31 32 31 32 31 32 31 32 31 32 31 32 31 32

31 32 31 32

31 32 68 31 32 68 32 68 32 68

31 32 68 31 32 68 32 68

C

32 68

I149

31 32 31 32 32 32


S2_2OTHERMEM TOP,BOTTOM =6x_DIELECTRIC


S2MEM_2PWR


?


S 2M 2M EM EM _2 _2 GN GN D

31 32



S 2M 2M EM EM _2 _2 OT OT HE HE R

31 32

?


*

S 2M 2M EM EM _2 _2 PW PW R

31 32



S 2_ 2_ 2O 2O TH TH ER ER ME ME M

31 32

?


S 2_ 2_ CT CT RL RL 2C 2C TR TR L

32 31 32


LAYER

SPACING_RULE_SET


S 2_ 2_ DA DA TA TA 2S 2S EL EL F

D

31 32

= 8 5_ OH OH M _D IF IF F

Spacing Rule Sets SPACING_RULE_SET

31 32


S2MEM_2GND


?



S2MEM_2OTHER TOP,BOTTOM =10x_DIELECTRIC

?

Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

S2 _MEM_ DATA *

*

AREA_TYPE

SPACING_RULE_SET


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

S2_MEM_DQS1

S2_MEM_DATA1

*

S2_DQS2OWNDATA

S2_MEM_DQS0

S2_MEM_DATA0

*

S2_DQS2OWNDATA

SPACING_RULE_SET


*

S 2MEM _2OTH ER



S2 _MEM _DQS *

*

*

S2 S2MEM _2OTH ER



B

S 2 _ M E M _ C MD

*

*

S2 S2MEM _2OTH ER

B


*

*

S2 S2MEM _2OTH ER

S 2 _ M E M _ C LK

*

*

S2 S2MEM _2OTH ER

S 2_ 2_ ME ME M_ M_ DA DA TA TA *

S2 _MEM _CTRL

= SA SA ME ME

*

S 2_ 2_ DA DA TA TA 2S 2S EL EL F




*

S2 _ C MD 2 C M D

S 2 _M EM EM _ CM D

S 2 _ M E M _ C MD

S 2_ 2_ M EM _C _C T RL

*

S 2 _C M D2 CT CT R L

S2_MEM_CTRL

S2_MEM S2_MEM_CTRL

*

S2_CTRL2CTRL

S2_MEM_CMD




S 2_ 2_ ME ME M_ M_ *

S 2_ 2_ ME ME M_ M_ *

*

S 2_ 2_ 2O 2O TH TH ER ER ME ME M

Memory to Power Spacing TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE


S 2_ 2_ ME ME M_ M_ PW PW R

S 2_ 2_ ME ME M_ M_ *

*

S 2M 2M EM EM _2 _2 PW PW R

S 2_ M E M _ PWR

*

*

D E F A UL T


Memory to GND Spacing TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

GND

S2_MEM_*

AREA_TYPE


A

*

S2MEM_2GND

A


S YNC _D AT E= 08 /1 2/ 20 13

Camera Constraints DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

116 OF 120

8

7

6

5

4

3

2

1

SMC SMBus & Charger Net Properties ELECTRICAL CONST SET

D

SMBUS_SMC_2 SMBUS_SMC_2 SMBUS_SMC_1 SMBUS_SMC_1 SMBUS_SMC_0 SMBUS_SMC_0 SMBUS_SMC_5 SMBUS_SMC_5 SMBUS_SMC_3 SMBUS_SMC_3

NET TYPE PHYSICAL SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S SMB_45S

SPACING SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA

34 36 39 68 34 36 39 68 14 32 36 39 43 68 72 14 32 36 39 43 68 72

D

36 39 62 68 36 39 62 68 36 39 51 52 68 36 39 51 52 68 36 39 43 63 36 39 43 63

C

C

B

B

A

A



SMC Constraints DRAWING NUMBER

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

117 OF 120

8

7

6

5

4

3

2

1


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

SENSE_45S

*

=1TO1_DIFFPAIR

=45_OHM_SE

=45_OHM_SE

=45_O HM_S E

0. 1 MM

0.1 MM

THERM_45S

*

=1TO1_DIFFPAIR

=45_OHM_SE

= 45 _O HM _S E

= 45 _O HM _S E

0 .1 M M

0 .1 M M


J44 Specific Net Properties




DIG_AUDIO

*

ANL_AUDIO

*

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR =1TO1_DIFFPAIR =1TO1_DIFFPAIR

0.1 MM

0.1 MM

0.1 MM

0.1 MM

NET TYPE PHYSICAL

J44 Specific Net Properties ELECTRICAL CONST SET

SPACING

NET TYPE P HY SI CA L

S PA CI NG


0.1 MM

=1TO1_DIFFPAIR

0.1 MM

10 MM


ANL_AUDIO_WIDE

*

0.3 MM

=1TO1_DIFFPAIR

0.3 MM

10 MM

0.1 MM

0.1 MM

D TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

WEIGHT

*

=2X_DIELECTRIC

?

THERM

*

=2X_DIELECTRIC

?

AUDIO

*

=2X_DIELECTRIC

?

T HE RM _4 5S T HE RM _4 5S THERM_45S THERM_45S T HE RM _4 5S THERM_45S

T HE RM T HE RM THERM THERM T HE RM THERM

TBTTHMSNS_D1_P TBTTHMSNS_D1_N CPUTHMSNS_D1_P CPUTHMSNS_D1_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N

23 43 43 43 43 43

NET_SPACING_TYPE1

NET_SPACING_TYPE2

CPU_VCCSENSE

GND

AREA_TYPE


*

GND_P2MM


SENSE_DP SENSE_DP

SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE

NC_ISNS_CAMERAP NC_ISNS_CAMERAN ISNS_CPUDDR_P ISNS_CPUDDR_N

SENSE_DP_LCDBKLT SENSE_DP_LCDBKLT SENSE_DP_TBT SENSE_DP_TBT S EN SE _D P S EN SE _D P

SENSE_45S SENSE_45S SENSE_45S SENSE_45S S EN SE _4 5S S EN SE _4 5S

SENSE SENSE SENSE SENSE SENSE SENSE

ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_TBT_P ISNS_TBT_N ISNS_LCDPANEL_P ISNS_LCDPANEL_N

SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S


ISNS_HS_COMPUTING_P ISNS_HS_COMPUTING_N ISNS_HS_OTHER5V_P ISNS_HS_OTHER5V_N ISNS_HS_OTHER3V3_P ISNS_HS_OTHER3V3_N




SPACING_RULE_SET

LAYER

LINE-TO-LINE

SPACING

NET_SPACING_TYPE1

WEIGHT

*

=STANDARD

AREA_TYPE

SPACING_RULE_SET

?

CLK_PCIE

GND

*

GND_P2MM

GND

PCIE_*

*

GND_P2MM

GND

SATA_*

*

GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM

USB


LAYER

LINE-TO-LINE

SPACING

WEIGHT

*

0.20 MM

CLK_PCIE

1000

PHYSICAL_RULE_SET

*

0.20 MM


LAYER

GND_P2MM

SB_POWER

*

PWR_P2MM TABLE_SPACING_ASSIGNMENT_ITEM


PWR_P2MM

*

GND



GND_P2MM

1000

SB_POWER

SATA_*

*

PWR_P2MM

USB

SB_POWER

*

PWR_P2MM


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

MEM_45S OVER RIDE

*

0.070 MM

OVERRI DE

OVERRI DE

O VERRID E

1 00 MIL

OVE RRIDE

OVE RRIDE

OVE RRIDE

41

40 58 40 58 42

OVER RIDE

*

0 .0 90 M M

OVERRI DE

OVERRI DE

O VERRID E

42 62 42 62

40 42 40 42

OVE RRIDE

OVE RRIDE

40 40 40

OVER RIDE OVER RIDE TABLE_PHYSICAL_RULE_ITEM

MEM_72D OVER RIDE

*

0.090 MM

OVERRI DE

OVERRI DE

O VERRID E

OVE RRIDE

OVERRI DE

O VERRID E

OVE RRIDE

100 MIL OVE RRIDE

OVE RRIDE

OVER RIDE

OVE RRIDE

OVER RIDE


MEM_85D OVER RIDE

*

0.090 MM

OVERRI DE

100 MIL OVE RRIDE


PCIE_85D OVER RIDE

*

0.090 MM

OVERRI DE

OVERRI DE

O VERRID E

10 MM

OVE RRIDE

OVE RRIDE

OVE RRIDE

SENSE_DP_CPUVR SENSE_DP_CPUVR SENSE_DP_CPUVR S EN SE _D P_ CP UV R

OVER RIDE TABLE_PHYSICAL_RULE_ITEM

USB_85D

TOP

0.100 MM

500 MIL

CPU_27P4S

BOTTOM

0.230 MM

100 MIL



USB3_85D

T OP

0.100 MM

SENSE_45S SENSE_45S SENSE_45S S EN SE _4 5S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE S EN SE SENSE SENSE SENSE SENSE

CPUVR_ISNS_P CPUVR_ISNS_N CPUVR_ISNS_R_P CPUVR_ISNS_R_N CPUVR_ISNS1_P CPUVR_ISNS1_N CPUVR_ISNS2_P CPUVR_ISNS2_N

41

ISL10 ISL9

41 54 41 54 41 54 41 54

0.090 MM

0.075 MM

0.090 MM TABLE_PHYSICAL_RULE_ITEM

PCIE_85D

ISL10

0.075 MM

0.090 MM

SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP SENSE_DP

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S


ISNS_1V05_S0_P ISNS_1V05_S0_N ISNS_SSD_P ISNS_SSD_N ISNS_TPAD_P ISNS_TPAD_N

41 41

TABLE_PHYSICAL_ASSIGNMENT_HEAD

B

PHYSICAL_RULE_SET

SENSE_DP SENSE_DP SENSE_DP SENSE_DP

S EN SE _4 5S S EN SE _4 5S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

S EN SE S EN SE SENSE SENSE SENSE SENSE

NC_ISNS_DDR_S3P NC_ISNS_DDR_S3N ISNS_PP3V3S0_P ISNS_PP3V3S0_N ISNS_PP5VS0_P ISNS_PP5VS0_N

S E NS E _D P _C P UH I GA I N S E NS E _D P _C P UH I GA I N SENSE_DP_CPUHIGAIN SENSE_DP_CPUHIGAIN

S E NS E _4 5 S S E NS E _4 5 S SENSE_45S SENSE_45S

S E NS E S E NS E SENSE SENSE

ISNS_CPUHIGAIN_P ISNS_CPUHIGAIN_N ISNS_CPUHIGAIN_R_P ISNS_CPUHIGAIN_R_N

SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSI SENSE_DP_CHGR_CSO SENSE_DP_CHGR_CSO SENSE_DP_CHGR_CSO SENSE_DP_CHGR_CSO

SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S SENSE_45S

SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE

CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N


M EM _ 40 S

B G A_ M EM

M EM _ 45 S TABLE_PHYSICAL_ASSIGNMENT_ITEM

M EM _ 72 D

B G A_ M EM

M EM _ 85 D

AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB

ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO ANL_AUDIO

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_LO3_L_P AUD_LO3_L_N AUD_SPKRAMP_LSUBIN_P AUD_SPKRAMP_LSUBIN_N LSUBIN_P LSUBIN_N

AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB AUDIO_DP_AMPSUB



AUD_LO3_R_P AUD_LO3_R_N AUD_SPKRAMP_RSUBIN_P AUD_SPKRAMP_RSUBIN_N RSUBIN_P RSUBIN_N

AUDIO_DP_SPKSUB AUDIO_DP_SPKSUB AUDIO_DP_SPKSUB AUDIO_DP_SPKSUB AUDIO_DP_SPKTWT AUDIO_DP_SPKTWT AUDIO_DP_SPKTWT AUDIO_DP_SPKTWT

DIG_AUDIO DIG_AUDIO DIG_AUDIO DIG_AUDIO D IG _A UD IO DIG_AUDIO D IG _A UD IO D IG _A UD IO

AUDIO AUDIO AUDIO AUDIO A UD IO AUDIO A UD IO A UD IO

SPKRCONN_SL_OUT_P SPKRCONN_SL_OUT_N SPKRCONN_SR_OUT_P SPKRCONN_SR_OUT_N SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N

D

48 48

46 48 46 48 48 48 48 48

46 48 46 48 48 48 48 48

46 48 46 48 48 48 48 48

48 50 68 48 50 68

C

48 50 68 48 50 68 48 50 68 48 50 68 48 50 68 48 50 68

AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC

ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_CH_HS_GND AUD_CONN_HS_MIC_P AUD_CONN_SLEEVE AUD_CONN_SLEEVE_XW AUD_HP_PORT_REFCH AUD_HS_MIC_P CODEC_HS_MIC_P HS_MIC_P

AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC AUDIO_DP_MIC

ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE ANL_AUDIO_WIDE

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUD_CONN_HS_MIC_N AUD_CONN_RING2 AUD_CONN_RING2_XW AUD_HP_PORT_REFUS AUD_HS_MIC_N AUD_US_HS_GND HS_MIC_N CODEC_HS_MIC_N

46 50

50 49 50 46 50 49 50 46 46 49

41 57

Alternate single ended and differential impedances between devices. AREA_TYPE

AUD_LO2_R_P AUD_LO2_R_N AUD_SPKRAMP_RIN_P AUD_SPKRAMP_RIN_N SPKRAMP_RIN_P SPKRAMP_RIN_N

48

41 57

DDR3 Loaded Segment Constraint Relaxations NET_PHYSICAL_TYPE


48

41


DP_85D


46 48

41

500 MIL

0.075 MM

AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT

46 48

41


USB3_85D

AUD_LO2_L_P AUD_LO2_L_N AUD_SPKRAMP_LIN_P AUD_SPKRAMP_LIN_N SPKRAMP_LIN_P SPKRAMP_LIN_N

40

1 00 M IL

OVE RRIDE


42


MEM_40S


41



C

42



SPACING_RULE_SET

42



GND

NET_SPACING_TYPE2

AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT AUDIO_DP_AMPTWT

43



SENSE

THERM_DP_TBT_D1 THERM_DP_TBT_D1 THERM_DP_CPU_D1 THERM_DP_CPU_D1 T HE RM _D P_ CP U_ D2 THERM_DP_CPU_D2

50 49 50 46 50 49 50 46 50 46 49

B

46

41 55 41 55 41 41

PP3V3_S5 PP3V3_S0

SB_POWER SB_POWER

41

8 11 13 15 16 17 18 26

27 29 56 59 60 61 65 68 61 62 64 65 68 8 11 12 13 15 17 18 24 28 30 37 38 39 40 41 42 43 44 46 47 50

41

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout. TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET


LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



MEM_72D

BOTTOM

0.127 MM

6.35 MM TABLE_PHYSICAL_RULE_ITEM

MEM_85D

TOP

0.100 MM

6.35 MM

DP, SATA, HDMI, PCIE CONSTRAINT RELAXATIONS

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM

DP _85D

BGA

P65_BGA TABLE_PHYSICAL_ASSIGNMENT_ITEM

P CI E_ 85 D

B GA

P 65 _B GA

C L K_ P CI E_ 8 5D

B GA

P 65 _ BG A



A

H DM I_ 85 D

B GA

P 65 _B GA

42 43 42 43 42 42

52 52 52 52 52 52 42 52 42 52

GND

GND

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM

S EN SE _4 5S

*

S EN SE _4 5S

T HE RM _4 5S

*

T HE RM _4 5S

D IG _A UD IO

*

D IG _A UD IO

ANL_AUDIO

*

ANL_AUDIO




A


S YNC _D AT E= 08 /1 2/ 20 13

PAGE TITLE

Project Specific Constraints DRAWING NUMBER


1T O1_ DIF FPA IR

*

1T O1_ DIF FPA IR

Apple Inc. R

SIZE

D

REVISION


BRANCH


PAGE

118 OF 120

A1502 820-3476-A

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