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Curriculum Vitae B.KARUN KUMAR Mob: 91-9296151505 D/NO:60-7-2, E-Mail:Karun.kmr2 AT gmail.com MOLLIVARI STREET, NEAR RAMALAYAM, JAGANNAICKPUR, KAKINADA EAST GODAVARI (d.t), Andhra Pradesh, PIN: 533002 Objective: Looking forward for an organization that offers a challenging, stimulating, learning environment to work and provide scope for individual development, which offers attractive prospects for long-term personal development and career growth. Educational Profile: - M.Tech(CSP)(2008-2010):with 61% - B.Tech (ECE) (2004-2008): With 58.60% aggregate. - Intermediate (2002- 2004): Board of Intermediate Education with 72%. - S.S.C (2001 -2002): Board of Secondary Education with 69.16%. Strengths: - Confident and disciplined in all situations. - Highly adaptive to new working environment. - Ability to work with a team having excellent communication skills and dynamic thinking. Technical Skills: Operating System : win 98/XP, MS DOS. Tools& Utilities : MS-office Conceptual Knowledge : Communication systems, Digital Electronics
Extra Activities: - Participated in International Conference on ASECI-2010(AEROSPACE ELECTRONICS, COMMUNICATIONS & INSTRUMENTATION) at VRSEC, Vijayawada. - Participated in Staff Development Program on COMMUNICATIONS and SIGNAL PROCESSING at VRSEC, Vijayawada. Project Experience: M.Tech Project Title "NEW APPRAOCH TO MINIMIZE THE IMPACT OF RESIDUAL MAI IN PROPOSED DETECTOR” B.Tech
Project Title : "IMPLEMENTATION OF REED SOLOMON FORWARD ERROR CORRECTION IMPEG2 TRANSPORT MULTIPLEX” Personal profile: Father’s Name : B.venkateswara rao Date of Birth : 02/17/1987 Marital status : Single Languages Known : English and Telugu Declaration: I here by declare that the above information and particulars are correct to the best of my knowledge. Place: KKD Signature Date: 19-7-2010 ( B. KARUN KUMAR)
Anitha Chandrashekar (M.TECH, VLSI Design and Embedded Systems, 2009-2011 Batch) Contact Address #**, #**, *** ****, **** , Nandakumar Layout, Arehalli, Uttarahalli, Bangalore- 560061. contact no: +91-953******* +91-953******* _________________________________________________________ _______________ Career Objective: To excel the software/hardware professional and hold up a challenging position in corporate world through diligence and dedication and to ensure my highest contribution towards the organization I work with. Educational Qualifications: Examination School/College Board/ University Year of Passing Percentage M.TECH (VLSI (VLSI Design & Embedded Systems) East Point College, Bangalore V.T V.T.U 2011 73% awaited B.E (E&C) City Engineering College, Bangalore V.T V.T.U 2009 63.8% P.U.C (P.C.M.B) Vijaya PU College, Bangalore PU board 2005 64.5%
Project Title : "IMPLEMENTATION OF REED SOLOMON FORWARD ERROR CORRECTION IMPEG2 TRANSPORT MULTIPLEX” Personal profile: Father’s Name : B.venkateswara rao Date of Birth : 02/17/1987 Marital status : Single Languages Known : English and Telugu Declaration: I here by declare that the above information and particulars are correct to the best of my knowledge. Place: KKD Signature Date: 19-7-2010 ( B. KARUN KUMAR)
Anitha Chandrashekar (M.TECH, VLSI Design and Embedded Systems, 2009-2011 Batch) Contact Address #**, #**, *** ****, **** , Nandakumar Layout, Arehalli, Uttarahalli, Bangalore- 560061. contact no: +91-953******* +91-953******* _________________________________________________________ _______________ Career Objective: To excel the software/hardware professional and hold up a challenging position in corporate world through diligence and dedication and to ensure my highest contribution towards the organization I work with. Educational Qualifications: Examination School/College Board/ University Year of Passing Percentage M.TECH (VLSI (VLSI Design & Embedded Systems) East Point College, Bangalore V.T V.T.U 2011 73% awaited B.E (E&C) City Engineering College, Bangalore V.T V.T.U 2009 63.8% P.U.C (P.C.M.B) Vijaya PU College, Bangalore PU board 2005 64.5%
S.S.L.C S.T S.T Thomas English School, Bangalore KSSEEB board. 2003 76% Technical Skills: Languages: Programming in C, C++, VHDL, MATLAB, Other processor languages like 8085, 8086, 8051. Operating Systems: Windows 98/2000/XP. Other Skills: CMOS Design, Design, Digital Design, Design, ASIC, FPGA Design, Design, Embedded systems. Extra-Curricular Activities: Participated in a numerous Science Fairs, Math and General Knowledge competitions at the School & State level from an early age. Participated in numerous college events like collage, dance, painting, organizing events etc. Academic Project(B.E): Project title: Centralized Irrigation System Language of Implementation: Micro controller (89c52) (Assembly level language) Operating System: Windows XP professional. Description: The need for power for power conservation in agriculture for irrigation for irrigation purpose is achieved by using this system which can remotely monitor and control the watering of the land. Centralized irrigation system enables the programming, monitoring, and operation of irrigation systems from a central location. Central control systems are designed to allow a user to control a single site or a set of sites from a single control unit. A central control system can monitor and adapt system operation and irrigation run times in response to conditions in the system or surrounding area. The system will also provide historical data to allow analysis and reporting of what ran when, how much water was used. Academic Project(M.Tech)(under progress): Project title: Design & Implementation of Artificial Neural Network for Image for Image Compression & Decompression
Resources: MATLAB ModelSim Verilog HDL FPGA Personal Profile: Name: Anitha Chandrashekar Sex: Female Marital Status: Single Nationality: Indian Hobbies: Playing carom, chess, Surfing Net, Reading Date of Birth: 12-03-1988 Declaration: I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the for the correctness of the above-mentioned particulars. Place: Bangalore (Anitha Chandrashekar)
Sreenivas Bachch E-mail:
[email protected] Phone: 9901293053
Objectives: To associate myself with an esteemed organization and to accept the challenges in the job by utilizing my education, analytical skills more meaningfully and work hard towards achieving the goals of the organization.
Training: Currently pursuing a PG Diploma Course in VLSI Design from Silicon Labs, Bangalore.
M.E. Project
:
JPEG2000 Encoder Implementation.
In this Dissertation, an implementation for a reconfigurable fully scalable Integer Wavelet Transform (IWT) unit that satisfies the specifications of the JPEG2000 standard has been presented. This project aims to provide modules written in the (VHDL) that can be used to accelerate an existing software implementation implementation of JPEG2000.
Wavelet Transform Encoder Implementation. This project is implementing DWT using Le Gall 5/3 filter bank in VHDL. The filtering process based on the lifting factorization of wavelet filter banks. This is more efficient then conventional approach using convolution. Also, integer arithmetic used, hence no need for precision with more then 8 bits is required.
B.E. Project
:
FFT Implementation Using VHDL.
In this project, an implementation of 8-bit FFT with VHDL and simulated with text of test vectors, the tool we used is ACTIVE HDL v4.2.
Software Exposure
:
Languages : C, C++, Object Oriented Programming Methodology, VHDL and Verilog.
Software/Tools Familiar With: Xilinx ise, Modelsim, Active HDL
Operating Systems : Windows, DOS, knowledge about some basic commands in UNIX.
Academic Details: M.Tech in Electronics & Communication Engineering with an aggregate of 67% from DELHI COLLEGE ENGINEERING (DCE), Delhi, in 2006. B.Tech in Electronics & Communication Engineering with an aggregate of 59.28% from VIJAY RURAL ENGG COLLEGE, J.N.T UNIVERSITY, Nizambad, A.P. in 2003. Intermediate in M.P.C. with an aggregate of 68.7% from VASU JUNIOR COLLEGE, Nizamabad, A.P. in 1998. Secondary School Certificate (S.S.C) with an aggregate of 73.67% from Z.P.P HIGH SCHOOL, Jakran Pally, A.P. in 1996.
Accomplishments : Secured 97.84 percentile in GATE (ECE) - 2004 Secured 1088 rank in State Engineering Entrance
EAMCET-1999.
Extra Curricular Activities: I got 1st prize in essay writing at school competition I was an active participant in Frolic 2003 & 2002.
Hobbies : Listening music, Watching movies and Cooking
Personal Details: Date of Birth: 15th May, 1981
Present Address: #678, Ground Floor, 3rd Cross, 2nd Main, Domlur Layout, Bangalore-560 071
Permanent Address: H. No.7-65, Main road, Post &Mon Jakran Pally, Dist Nizamabad Andhra Pradesh-503175
Phone Number: +91-8463-271421 (Home).
Languages Known: English, Hindi and Telugu.
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vlsi companies in india
RFIC Technologieswww.rficdesign.com Contact Address:
Analog Devices India Pvt Ltd. www.analog.com Alliance Semiconductor (India) Pvt. Ltd. www.alsc.com AMDwww.amd.com Altera Semiconductor Indiawww.altera.com Alliance Semiconductor (India)www.alsc.com Agere Systems India Pvt. Ltd.www.agere.com Applied Materials (I) Pvt. Ltd.www.amat.com ARM Embedded Technologies Pvt.Ltd.www.arm.com Beceem Communications Pvt. Ltd.www.beceem.com Bharat Electronics Limitedwww.bel-india.com Bluespec Incorporatedwww.bluespec.com Broadcom (I) Pvt. Ltd.www.broadcom.com Brooks Automation India (P) Ltd. www.brooks.com Cadence Design Systems (I).www.cadence.com Centillium India Pvt. Ltd. www.centillium.com CG-CoreEI Programmable Solutions.www.cg-coreel.com ChipTest India (P) Ltd www.chiptestinc.com CMC – IDCwww.xilinx.com Cortina Systems www.cortina-systems.com
Cosmic Circuitswww.cosmiccircuits.com Conexant Systems India Pvt. Ltd. www.conexant.com Controlnet (India) Private Ltd www.controlnet.co.in CoWare India Pvt. Ltd.www.coware.com Cypress Semiconductor Technology. www.cypress.com Denali Design Systems Pvt Ltdwww.denali.com D’gipro Systems Pvt. Ltd. www.dgipro-systems.com DigiBee Microsystems India Ltd. www.dgbmicro.com Elven Technologieswww.elventechnologies.com EInfochips Ltd. www.einfochips.com Freescale Semiconductor India. www.freescale.com Future Techno Designs Pvt. Ltd. www.ftdpl.com Genesis Microchip India Pvt. Ltd www.gnss.com Global Edge Software Ltd. www.globaledgesoft.com HCL Technologies Ltd. www.hcltech.com Hellosoft India Pvt. Ltd. www.hyd.hellosoft.com IBM Global Services Pvt. Ltd. www.ibm.com/in Ikanos Communications India www.ikanos.com InfineonTechnologies India. www.infineon.com
InsilicaSemiconductor India. www.insilica.com Intel Technology India Pvt. Ltd www.intel.com Intersil Analog Service Pvt.Ltd www.intersil.com Interra Systems India (P) Ltd.www.interrasystems.com Ittiam Systems Pvt Ltd www.ittiam.com Kasura Technologies www.kasura.com KLA Tencor Software India Pvt.Ltd .www.kla-tencor.com KPIT Cummins Info Systems Limitedwww.kpitcummins.com Larsen & Toubro Limitedwww.ltindia.com LSI Logic India Pvt. Ltd. www.lsil.com Magma Design Automation India www.magma-da.com Maxim India Integrated Circuit Design. www.maxim-ic.com Mentor Graphics (Sales & Services) Pvt. Ltd. www.mentor.com Mindtree Consulting Pvt. Ltd .www.mindtree.com Moschip Semiconductor Technology Ltd. www.moschip.com Moser Baer PV Ltd.www.moserbaer.com National Semiconductor www.national.com NI Systems (India) Pvt. Ltd.www.ni.com/india Novellus Systems (India) Pvt. Ltd. www.novellus.com Nulife Semiconductor India Pvt. Ltd www.nulifetech.com
Nvidia Graphics Pvt. Ltd.www.nvidia.com Open-Silicon Research Pvt. Ltd .www.open-silicon.com Philips Semiconductorswww.philips.com Portal Player Pvt. Ltd.www.portalplayer.com PMC – Sierra India Pvt. Ltd.www.pmc-sierra.com Purple Vision technologies (P) Ltd.www.purplevisiontech.com QualCore Logic Ltd. www.qualcorelogic.com Quicklogic Software (I) Pvt. Ltd. www.quicklogic.com Rambus Chip Technologies (I) Pvt. Ltd. www.rambus.com Redpine Signals Inc. www.redpinesignals.com Samsung India Software Operations Pvt.Ltd www.samsung.com.in Samtel Color Ltd.www.samtelgroup.com SanDisk India Device Design Centre Pvt.Ltd www.sandisk.com Sankalp Semiconductor Pvt. Ltd. www.sankalpsemi.com Sasken Communication Technologies Limited www.sasken.com Satyam Computer Services Ltd. www.satyam.com Skyworks Solutions Inc. www.skyworksinc.com Spel Semiconductor Ltd. www.spel.com Spike Infotech Pvt. Ltd. www.qualcomm.com STMicroelectronics Pvt. Ltd. www.st.com
Synplicity Software India Pvt. Ltd www.synplicity.com Synopsys (India) Pvt. Ltd. www.synopsys.com Tata Consultancy Services www.tcs.com Tektronix India Pvt. Ltd. www.tektronix.com Tensilica Technologies India Pvt. Ltd. www.tensilica.com Tessolve Services Pvt. Ltd. www.tessolve.com Texas Instrumentswww.ti.com Transwitch India Pvt. Ltd. www.transwitch.com TSMC www.tsmc.com United Microelectronics Corporationwww.umc.com Virage Logic Internationalwww.viragelogic.com Wipro Technologieswww.wipro.com VLSI Interview Questions and answers 1. Go through VLSI book from beginning to the end 2. If possible solve all the problems at the end of the chapter 3. Most basic question is draw digital gates using transistors, difference between bipolar and cmos , analog and digital 4. Go through the details on your project 5. Refresh your circuit theory, basic LCR circuit , transfer function , .. 1. before going for these types of interview questions , study any good vlsi book 2. measure your capability by your shelf, you can go to any chapter end questions and see how many quCestions you can solve 3. for experienced professionals prepare one of your projects thoroughly, most common question for vlsi experienced professionals is explain one of the projects ,
remember you have to explain relevant experience which are suitable for the job requirement 4. for fundamentals you may be asked on deep sub micron technology , channel length modulation, mos characteristics, noise , ..
vlsi interview questions and answers 1) Give two ways of converting a two input NAND gate to an inverter 2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt) 3) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? 4) Give a circuit to divide frequency of clock cycle by two 5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) 6) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors) 7) The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? What are the different Adder circuits you studied? 9) Give the truth table for a Half Adder. Give a gate level implementation of the same. 10) Draw a Transmission Gate-based D-Latch. 11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) 12) How do you detect if two 8-bit signals are same? 13) How do you detect a sequence of “1101? arriving serially from a signal line? 14) Design any FSM in VHDL or Verilog
additional questions what is your roles and responsibilities in that project what all cores where present in that chip what is the technology like 130,90,65,45nm
what is the clock-frequency how many clock-domains what is the voltage value what is the macro-count what is the flip-flop count what are the various analog macros how many pads were there what is your skew you had achieved what is your insertion delays what is your pll jitter how did you model your uncertainities or variations how many power-domains were there did you have multi-VDD if you had multi-VDD how did you handle insertion of level-shifters what is the SSN(simultaneous switching noise) pad ratios used in your design. how did you prevented noise in your chip how many placeable instances what is the cell-row utilization is your design pad-limited or core-limited did you multiplexed your pads what type of package wafer bond or flip-chip if flip-chip how did you distributed power bumps any special strategy how many metal layers in your technology did you used in house library or from any vendor what is the die-area of your chip What are the various Design constraints used while performing Synthesis for a design?
Ans: 1. Create the clocks (frequency, duty-cycle). 2. Define the transition-time requirements for the input-ports 3. Specify the load values for the output ports
4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip. 5. Specify the case-setting (in case of a mux) to report the timing to a specific paths. 6. Specify the false-paths in the design 7. Specify the multi-cycle paths in the design. 8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold). 19. Specify few verilog constructs which are not supported by the synthesis tool. What are the various design changes you do to meet design power targets?
Ans: Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd’s, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt’s(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design , clocks consume more amount of power, placing optimal clockgating cells, in the design and controlling them by the module enable’s gives a lot of power-savings. As clock-tree’s always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction. Incorporating Dynamic Voltage and Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the
design specification requirement. Place power-switches, so that the leakage power can be reduced. related information. what is meant by Library Characterizing
Ans: Characterization in terms of delay, power consumption,.. what is meant by wireload model
Ans: In the synthesis tool, in order to model the wires we use a concept called as “Wireload models”, Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for “n” number of fanin then we estimate its delay as say “x” delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available what are the measures to be taken to design for optimized area
Ans: As silicon real-estate is very costly and saving is directly propotional to the company’s revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets. what all will you be thinking while performing floorplan
Ans:
Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usuage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise. what are the measures in the Design taken for Meeting Signal-integrity targets
Ans: As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let’s see now by what are all the measures we can reduce/solve it. As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI. Enable SI aware routing , so that the tool takes care for SI Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other Minimize the parallel run-length wires, by inserting buffers. what are the measures taken in the Design achieving better Yield
Ans: Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge.
Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it. For via-reliability issues, use redundant vias, to reduce the chances for viabreakage. In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories. Optimal placing of de-coupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained. what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions
Ans: Designing for Optimal integration of Analog and Digital As today’s IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists seperate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro’s. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion. what are the steps incorporated for Engineering Change Order[ECO]
Ans: As more and more complex the IC design is , and with lot of first time application , is more prone to
last minute changes, there should be provision in the design-flow to accomodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO). Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved. what are the steps performed to achieve Lithography friendly Design
Ans: Designing for Manufacturability requires validating the design full-filling lithography rules Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets. what does synthesis mean
Ans: Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells..
Verilog interview Question What is Verilog? Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis. The Verilog HDL is an IEEE standard – number 1364. The first version of the IEEE standard for Verilog was published in 1995. A revised version was published in 2001; this is the version used by most Verilog users. The IEEE Verilog standard document is known as the Language Reference Manual, or LRM. This is the complete
authoritative definition of the Verilog HDL. A further revision of the Verilog standard was published in 2005, though it has little extra compared to the 2001 standard. SystemVerilog is a huge set of extensions to Verilog, and was first published as an IEEE standard in 2005. See the appropriate Knowhow section for more details about SystemVerilog. IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C). Note that VHDL is not an abbreviation for Verilog HDL – Verilog and VHDL are two different HDLs. They have more similarities than differences, however. 1) Write a verilog code to swap contents of two registers with and without a temporary register?
With temp reg ; always @ (posedge clock) begin temp=b; b=a; a=temp; end Without temp reg; always @ (posedge clock) begin a <= b; b <= a; end Difference between blocking and non-blocking?
The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in
traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example, the following Verilog program // testing blocking and non-blocking assignment module blocking; reg [0:7] A, B; initial begin: init1 A = 3; #1 A = A + 1; // blocking procedural assignment B = A + 1; $display(“Blocking: A= %b B= %b”, A, B ); A = 3; #1 A <= A + 1; // non-blocking procedural assignment B <= A + 1; #1 $display(“Non-blocking: A= %b B= %b”, A, B ); end endmodule produces the following output: Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100 The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems. blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential Difference between task and function?
Function: A function is unable to enable a task however functions can enable other functions.
A function will carry out its required duty in zero simulation time. ( The program time will not be incremented during the function routine) Within a function, no event, delay or timing control statements are permitted In the invocation of a function their must be at least one argument to be passed. Functions will only return a single value and can not use either output or inout statements. Tasks: Tasks are capable of enabling a function as well as enabling other versions of a Task Tasks also run with a zero simulation however they can if required be executed in a non zero simulation time. Tasks are allowed to contain any of these statements. A task is allowed to use zero or more arguments which are of type output, input or inout. A Task is unable to return a value but has the facility to pass multiple values via the output and inout statements . Difference between inter statement and intra statement delay?
//define register variables reg a, b, c; //intra assignment delays initial begin a = 0; c = 0; b = #5 a + c; //Take value of a and c at the time=0, evaluate //a + c and then wait 5 time units to assign value //to b. end //Equivalent method with temporary variables and regular delay control initial begin
a = 0; c = 0; temp_ac = a + c; #5 b = temp_ac; //Take value of a + c at the current time and //store it in a temporary variable. Even though a and c //might change between 0 and 5, //the value assigned to b at time 5 is unaffected. end Difference between $monitor,$display & $strobe?
These commands have the same syntax, and display text on the screen during simulation. They are much less convenient than waveform display tools like cwaves?. $display and $strobe display once every time they are executed, whereas $monitor displays every time one of its parameters changes. The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit rather than exactly where it is executed. The format string is like that in C/C++, and may contain format characters. Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number instead of the space needed. Append b, h, o to the task name to change default format to binary, octal or hexadecimal. Syntax: $display (“format_string”, par_1, par_2, … ); $strobe (“format_string”, par_1, par_2, … ); $monitor (“format_string”, par_1, par_2, … ); What is difference between Verilog full case and parallel case?
A “full” case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If a case statement does not include a case default and if it is possible to find a binary case expression that does not match any of the defined case items, the case statement is not “full.” A “parallel” case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If it is possible to find a case
expression that would match more than one case item, the matching case items are called “overlapping” case items and the case statement is not “parallel.” What is meant by inferring latches,how to avoid it?
Consider the following : always @(s1 or s0 or i0 or i1 or i2 or i3) case ({s1, s0}) 2′d0 : out = i0; 2′d1 : out = i1; 2′d2 : out = i2; endcase in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified. For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred. The same may be observed in IF statement in case an ELSE IF is not specified. To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided. Tell me how blocking and non blocking statements get executed?
Execution of blocking assignments can be viewed as a one-step process: 1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side expression) of the blocking assignment without interruption from any other Verilog statement. A blocking assignment “blocks” trailing assignments in the same always block from occurring until after the current assignment has been completed Execution of nonblocking assignments can be viewed as a two-step process: 1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update the LHS of nonblocking statements at the end of the time step. What is sensitivity list?
The sensitivity list indicates that when a change occurs to any one of elements in the list change, begin…end statement inside that always block will get executed. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?
Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch. Tell me structure of Verilog code you follow?
A good template for your Verilog file is shown below. // timescale directive tells the simulator the base units and precision of the simulation `timescale 1 ns / 10 ps module name (input and outputs); // parameter declarations parameter parameter_name = parameter value; // Input output declarations input in1; input in2; // single bit inputs output [msb:lsb] out; // a bus output // internal signal register type declaration – register types (only assigned within always statements). reg register variable 1; reg [msb:lsb] register variable 2; // internal signal. net type declaration – (only assigned outside always statements) wire net variable 1; // hierarchy – instantiating another module reference name instance name ( .pin1 (net1), .pin2 (net2), . .pinn (netn) );
// synchronous procedures always @ (posedge clock) begin . end // combinatinal procedures always @ (signal1 or signal2 or signal3) begin . end assign net variable = combinational logic; endmodule Difference between Verilog and vhdl?
Compilation VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it’s own system file in which case separate compilation should not be an issue. Verilog. The Verilog language is still rooted in it’s native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation. Data types VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it’s simplicity. Design reusability VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them. Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive. Can you tell me some of system tasks and their purpose?
$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo. The most useful of these is $display.This can be used for displaying strings, expression or values of variables. Here are some examples of usage. $display(“Hello $display(“Hello oni”); — output: Hello oni $display($time) $display($time) // current simulation time. — output: 460 counter = 4′b10; $display(” The count is %b”, counter); — output: The count is 0010 $reset resets the simulation back to time 0; $stop halts the simulator and puts it in
interactive mode where the user can enter commands; $finish exits the simulator back to the operating system Can you list out some of enhancements in Verilog 2001?
In earlier version of Verilog ,we use ‘or’ to specify more than one element in sensitivity list . In Verilog 2001, we can use comma as shown in the example below. // Verilog 2k example for usage of comma always @ (i1,i2,i3,i4) Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches, Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below module memory ( input r, input wr, input [7:0] data_in, input [3:0] addr, output [7:0] data_out ); Write a Verilog code for synchronous and asynchronous reset?
Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg: always @ (posedge clk ) begin if (reset) . . . end Asynchronous means clock independent so reset must be present in sensitivity list. Eg Always @(posedge clock or posedge reset) begin
if (reset) . . . end
analog IC interview Analog Integrated Circuit Interview question 1) Differentiate between Analog and Digital IC design ? Analog circuit design is different from Digital Circuit design in following aspects: • Layout is critical since the routing should be done according to RF design rules • Layout in digital can be completely automatic which is not the case in analog circuits • Grounding issue is critical in Analog or RFIC compared to Digital IC • Size of analog IC’s are large compared to digital since it comprises of inductors capacitors and resistors where as digital IC’s includes only capacitors and resistors. 2) Which are the various processes used for fabrication of IC’s? The different processes used for fabrication of IC’s are: • GaAs SiGe CMOS BiCMOS_ should know some fundamentals on each process 3) What is the basic purpose of using EM simulation? Basic purpose of EM simulation is to predict the actual behavior of RF Circuits considering all the parasitic and coupling. This is not considered in circuit simulation. 4) List the instruments required for testing RF Modules and IC’s Instruments required for RF testing are: • Spectrum Analyzer • Vector Network Analyzer • Noise Figure Meter • Power Meter
5) Which are basic blocks that comprise the RF Transceiver? RF Receiver consists of • Low Noise Amplifier/RF Amplifier • Mixer • Local Oscillator • Demodulator • Automatic Gain controller • Automatic Frequency controller. • Filters • Switch RF Transmitter consists of • RF power amplifier • Modulator • Carrier Oscillator • PLL • Filters • Switch 6) What is the basic function of a power amplifier? The main function of RF power amplifier is to boost the power level of a Signal so that it can travel a significant distance. Power amplifiers are required in all the transmitters 7) What is the basic function of a low noise amplifier? The main function of Low Noise Amplifier is to amplify the weakest possible Signal with Noise Figure as low as possible during reception and to improve the sensitivity and dynamic range of a receiver. 8) What is the basic function of a Mixer? Frequency translation is the key role of Mixer. Output contains the sum or difference of two frequencies i.e. RF frequency and LO(Local Oscillator) Some Good Books: • CMOS Circuit design, layout and simulation, R Jacob Baker, Harry W. Li and David
E. Boyce. • Analog Integrated Circuit Design, David Johns, Ken Martin, • CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, • Design of analog CMOS Integrated Circuits, Behzad Razavi, • RF Microelectronics, Razavi • RF microelectronics Thomas Lee • Any Digital books may be rabey Typical questions 1 Gain, (how to improve gain?) 2 Bandwidth, (how to improve bandwidth?) 3 Feedback,(Stability is a must ask question! Know pole, zero, gain and phase margin!) 4 Slew rate,(How to improve slew rate?) 5 Offset,(how to eliminate offset? Chopper stabilized circuits, auto zero) ? Noise,(what is thermal, flick, shot noise? Or noises of MOSFET? (How to reduce noise) 6 Compensation (what is Miller, lead and Lag compensation? 7 Layout (centroid, interdigital) (how to improve the match of current mirror, differential pairs?, Same surroundings(dummy transistors) and Common-centroid geometry (fingers, interdigitated fingers, what is the purpose of breaking into fingers? 8 Thermal resistance (basic calculation). 9 Filter 10 Oscillator 11 Peak detector 12 Frequency divider 13 Bandgap Reference 14 PLL and its functions
asic interview 4
application specific integrated circuit interview questions and answers 66) What is the purpose of minimum area design rules? 67) What is the purpose of end overlap rules? 6Cool What is the phenomenon of latch-up? Why is it a serious concern in CMOS layout design? 69) Describe six different layout strategies that are commonly used to minimize the possibility of latch-up. 70) Why is it wise to plan designs to make it easier to change details later? 71) What is meant by metal strap programmability and via programmability? Give one example where each techniques is commonly used. 72) What is the difference between test pads and probe pads? 73) Dan Clein advocates the use of contact and via cells, which is not a common design practice. What are his reasons? 74) In which situation should one avoid using the minimum allowed feature sizes allowed by the design rules? 75) What fundamental factors limits the speed with which detected design errors can be corrected? 76) When floor planning a chip at the start of the IC layout process, what are the main goals in deciding how to arrange the major blocks in the design? power line, noise, clock tree? !
77) How is block floor planning different from chip floor planning? 78 What is a silicon compiler? 79) What is the difference between a channel router and a maze router? Which type of router will tend to produce higher utilization factors? 80) What is a chip assembly tool? What kind of routing should a chip assembly tool provide to have maximum flexibility? 81) At IBM, it has been found to be advantageous to sacrifice performance when migrating a chip design in one process into a second process. Process migration is facilitated by the use of “migratable design rules”. What is the major benefit that can be obtained by such rules to offset the loss in potential chip performance? 82) At IBM a design methodology has been developed that makes the layout of standard cells very similar to that of gate array cells. What is the potential benefit of intermixing such cells in the same chip design? 83) In its ASIC design flow, IBM uses a formal verification tool that performs a technique called Boolean equivalence checking. What is the primary potential benefit of using formal verification methods in design verification? What is the conventional way of verifying the equivalence of different implementations of the same function? 84) IBM has standardized its logic design on the use of pulse-triggered latches, whereas the rest of the industry has tended to adopted design based on edgetriggered flip-flops. What is the strategy that IBM has adopted to be able to accommodate designers from other companies who wish to have ASICs fabricated through IBM? 85) Why are terminator cells sometimes used when clock trees are inserted into a block of placed standard cells?
86) When constructing a clock tree with distributed buffers, why is it very desirable to keep the buffers lightly loaded near the root of the clock distribution tree? Why can leaf nodes of the clock tree can be loaded more heavily? Why does one aim to have a balanced clock tree? 87) What is the difference between two- and three-dimensional analysis of interconnect capacitance. 8Cool Guard bands are usually built into the timing estimates employed by logic synthesis, cell placers, and other CAD tools. What is lost when the guard bands are relatively large? What could be gained if the timing estimates could be made more accurate? 89) Full 3-D capacitance calculations are generally extremely timing consuming. How can the technique of tunneling be used to make such calculations efficient enough to use in large IC designs? 89) The output of a 3-D field solver is a charge distribution over the signal net under consideration, and a charge distribution over the surrounding passive nets. Generally the signal net is assumed to be at a potential of 1 volt while the other nets are held at 0 volts. How can the signal net’s self-capacitance and coupling capacitance then be computed? 90) Moore’s Law predicts a doubling in the number of transistors per chip every two to three years. The major factor supporting Moore’s Law is improvements in lithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore’s Law to hold? Even if physical factors allow for further increases in per-chip component density, what other factors could slow or even stop Moore’s Law in practice? 91) What is meant by the term “dual damascene process”?
How has the availability of this type of process simplified the creation of multiple interconnected metal layers? 92) In processes that have multiple layers of metal interconnect, why is it common to make the upper wires thicker than the lower layers? (The use of fat wires is sometimes called “reverse scaling”.) In which situations would one be willing to use reverse scaling and hence appear to throw away the possible advantages of thinner wires? 93) What are some of the important reasons why DRAM technology has been a pioneer for semiconductor technology advances? 94) Briefly explain what are planar DRAM cells, trench capacitor DRAM cells, and stacked capacitor DRAM cells. Which type of cell is becoming dominant in embedded DRAMs? Why is this so? 95) There are numerous technological challenges and additional costs with embedded DRAM. Describe three of the main potential advantages that could be gained with embedded DRAM. What are characteristics of an application that could benefit from using embedded DRAM? 96) What are the three most common process solutions to providing embedded DRAM? Discuss some of the important trade-offs that must be made when selecting a process strategy for embedded DRAM.
asic interview 3
application specific integrated circuit interview questions and answers 41) Why is the pad ring provided with power supply connections that are separate from those of the core design? 42) What are so-called friendly cells in a DRAM core design? Why and where these cells included in a memory design? 43) Why are metal straps used along with polysilicon wordlines in memory designs? 44) Why are wordline driver circuits very long and narrow? 45) Describe some of the alignment keys that are included in IC layouts. 46) Why is the power supply interconnect layout layout planned out before other elements? Similarly, why are busses, differential signals, and shielded signals routed before other general signals? 47) What are the root and resistance styles of power supply layout? 4Cool What are some of the main reasons why clock skew minimization is such a major design challenge? 49) What are the major advantages and disadvantages of using a single clock tree conductor driven by one big buffer? 50) In ASIC design flows, why are clock trees inserted after the logic cells have been placed? In such clock trees, how is clock skew minimized at the leaves of the tree? 51) What is a routing channel?
Why are routing channels used in IC layouts? 52) Why is the estimated area for routing channels increased by 10% during early stages of layout planning? 53) When routing a signal interconnect, why is it desirable to minimize layer changes through vias? 54) Interconnect resistance is usually minimized in IC layouts. Give at least four situations where a deliberably large, but controlled, resistance is usually required? 55) Why should minimum-width paths be avoided in the design of deliberate resistances? 56) Usually one wishes to minimize the capacitance of electrical nodes in an IC design. Give four examples of circuits where one would wish a larger, but controlled, capacitance at a node? 57) The capacitance on a node is the sum of several components. What is meant by fringe capacitance? How does reducing the width of a conductor affect the fringe capacitance? 5Cool How can the parasitic capacitance between two signal nodes possibly cause the signal transition on one of the nodes to be unexpectedly sped up? 59) How can a layout designer help ensure that the propagation delay along two conductors is very similar? By running the two traces side by side and making them of equal length. 60) List four situations where it may be desirable to have 45 degree corners in the interconnect. 61) Explain what is meant by electromigration. What are some possible consequences of unexpectedly high electromigration?
How is electromigration controlled in IC layout design? 62) Why are wide metal conductors, such as those in the power rings, provided with slits? What constraints must be followed when positioning these slits? 63) When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other? 64) Why would a DRAM layout be verified against two or more different sets of design rules? 65) What is the antenna effect, and how can it cause problems in an IC design? What are two layout techniques that can be used to reduce vulnerability to the antenna effect?
asic interview 2
did you had any rectilinear macros if so any thing special you did during floor-plan did your chip had multi-vt flow , yes or no if multi-vt how did you managed using it in synthesis what is the extraction process what are the various IO’s like PCI/SPI/SDIO/USB/…. how many STA modes did you had did you run functional STA and Test STA did you balance test clocks did you chip test works on atspeed or low speed what is your scan-shift frequency how many test-modes do you have do you test analog macros during test do you have jtag mode how many plls do you have
do you have fractional pll’s as well do you have DSP in your chip what are the various protocols used in your chip what is the maximum bus frequency in your chip do you have multiple masters and multiple slaves accessing your chip bus how did your bus arbitration logic work 21) Define what is meant by the terms design rules checking, layout versus schematic, and electrical rules check? Are all three procedures required in every chip design? 22) What is meant by the term “porosity”? Why is it desirable for a cell or macro to have high porosity? 23) What are the main differences in priorities between microprocessor design, ASIC design, and memory design? How are those differences reflected in the corresponding design flows? 24) What is an “application-specific memory”, according to Clein? What are some specific examples of this part type? 25) What is the difference between a soft IP block (soft core) and a hard IP block (hard core)? Softcore - most flexible - exist either as a gate-netlist or RTL. Hardcare - best for plug and play - less portable and less flexible. - physical manifestations of the IP design.
26) In ASIC design, what are the main advantages of expressing the design using a hardware description language, such as VHDL or Verilog? The main reason for using high level hardware design like VHDL or Verilog is easy generating hundred of million gate counts chip better than schematic entry design. 27) Why are memory layouts designed primarily from the bottom up, instead of from the top down, like other ICs? With respect to a memory layout, what is meant by “array efficiency”? 29) What is “pitch-limited layout”? What are some of the major circuits in a memory layout that must meet pitch-limited constraints? 30) What are some of the typical kinds of cells that one would expect to find in a library of standard cells? 31) The layout of standard cells is constrained to simplify the job of place & route tools. Give several examples of these constraints. 32) Why did older cell libraries include so-called feed through cells? Why are such cells no longer required in cell libraries for modern processes? 33) What is electro migration? How does electro migration affect the design of a standard cell based design? 34) What is a gate array? Why are main advantages of using gate arrays to implement an IC? What are some of the main disadvantages, with respect to custom design or standard cell based design?
35) Why might one want to use some gate array based design inside an otherwise custom IC design, according to Clein’s experience? 36) What are some of the major similarities and differences of standard cells and datapath cells? 37) How is the problem of driving a clock node different from that of designing a regular signal node? What are the key goals when laying out a clock node? What is a “pad frame”? What are “staggered” pads? 39) Why are 90 degree corners usually avoided in the layout of pad cells? 40) In the layout of output pad driver transistors, why is the gate length often lengthened at both ends of the gate?
vlsi interview 3
Logic design questions, memory Interview question
1. Multiples of 5 detector on an infinite width shift register. Also multiples of 6 detector. 2. Divide by 2, Divide by 3 circuit with equal duty cycle. 3. Frequency multipliers. Delay the clock using multiphase DLL, pll etc , and then use XORs. 4. Edge detectors. 5. Given Two 4 bit nos A= 1001
B = 1100 HOW DO YOU XOR them using minimum number of gates? How do you nand them? How do your or them? (Hint: 4:1 Muxes) 6. How many 4:1 mux do you need to design a 8:1 mux? 7. Traffic Light controller State Machine (Highway/Farmway intersection). 8. D-Word, Q-word? 9. Size of the biggest design you have done. Did u have multiple clock domains? How was clock-crossing accomplished. Synchronizers, metastability, determinism? 10.Define Moore, Mealy state machines. Which ones are good for timing? 11.IScan, Bscan? Provide example applications. How do u make reset controllable from toplevel. 12.Design a FSM to detect 10110. What is the minimum # of flops required? 13.Prime # detector 14.Prime # counter 15.Digital one shot (merging pulses to one pulse). 16.Pulse clipper (or a return to zero ) circuit. Design a clock to pulse circuit in Verilog / hardware gates. 17. Design a simple circuit based on combinational logic to double the output frequency. 18.Implement comparator that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < B, A = B. (Reduce the equations using Karnaugh Map) Do it two ways: - using combinational logic; - using multiplexers. Write HDL code for your schematic at RTL and gate level.
19.What types of flip-flops do you know? 20. Implement D- latch from - RS flip flop; - multiplexer. 21. How to convert D-latch into JK-latch and JK-latch into Dlatch? 22. You have two counters to 16, built from negedge D- FF . First circuit is synchronous and second is “ripple” (cascading). Which circuit has a less propagation delay? 23. What is the difference between flip-flop and latch? Write an HDL code for their behavioral models. 24. What is the max clock frequency the circuit can handle ? T_setup= 6nS T_hold = 2nS T_propagation = 10nS 25. To enter the office people have to pass through the corridor. Once someone gets into the office the light turns on. It goes off when none is present in the room. There are two registration sensors in the corridor. Build a state machine diagram and design a circuit to control the light. 26. Design a 2bit up/down counter with clear using gates. (No verilog or vhdl) 27. We have a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order). How big the fifo needs to be to avoid data over/underrun. 28. Design a state-machine (or draw a state-diagram) to give an output ’1′ when the # of A’s are even and # of B’s are odd. The input
is in the form of a serial-stream (one-bit per clock cycle). The inputs could be of the type A, B or C. At any given clock cycle, the output is a ’1′, provided the # of A’s are even and # of B’s are odd. At any given clock cycle, the output is a ’0′, if the above condition is not satisfied. 29. To detect the sequence “abca” when the inputs can be a b c d. 30. Given a function whose inputs are dependent on its outputs. Design a sequential circuit. 31. Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1. 32. Minimize: S= A’ + AB 33. Given a boolean equation draw the transistor level circuit. 34. What is the function of a D-flipflop, whose inverted outputs are connected to its input? 35.Sender sends data at the rate of 80 words / 100 clocks Receiver can consume at the rate of 8 words / 10 clocks Calculate the depth of FIFO so that no data is dropped. Assumptions: There is no feedback or handshake mechanism. Occurrence of data in that time period is guaranteed but exact place in those clock cycles is indeterminate. 36.Optical sensors A and B are positioned at 90 degrees to each other as shown in Figure. Half od the disc is white and remaining is black. When black portion is under sensor it generates logic 0 and logic 1 when white portion is under sensor. Design Direction finder block using digital components (flip flops and gates) to indicate speed. Logic 0 for clockwise and Logic 1 for counter clockwise. Cannot assume any fixed position for start. 37.Will this design work satisfactorily? Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns. After reset A = 0, B = 1
38. How to synchronize control signals and data between two different clock domains? 39.Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads. 40. In what cases do you need to double clock a signal before presenting it to a synchronous state machine? 41. How many bit combinations are there in a byte? 42. What are the different Adder circuits you studied? 43. Give the truth table for a Half Adder. Give a gate level implementation of the same. 44.Convert 65(Hex) to Binary 45.Convert a number to its two’s compliment and back. 46.What is the 1′s and 2′s complement of the decimal number 25. 47.VHDL/Verilog sensitivity list? Any other techniques to accomplish the same thing? 48.Difference between signal/variable. 49.Karnaugh Map. Given an equation (eg: X + X’Y) reduce. do you have soft resets do you synchronous your resets or not do you have latches in your chip how many power domains do you have what is the supply pad voltage do you used diodes to eliminate ESD how many layers do you do power-routing what is the layers you use for clock-routing do you do anything special for special nets in routing phase
did you do routing timing driven or not did you enable signal integrity while routing did you validate SI based STA using PT-SI or some other tool what is the extra margin di dyou kept during synthesis phase how many ECO’s do you faced to close the timing or functional verification do you used to run formal verification to validate the handover RTL and netlist are fine did you checked antenna violation did you qualify your chip with GLS(gate level simulation) what is the package frame number how did you performed timing budgetting anything special you did to increase the yield how did you estimate your power-strips and meshes widths do you have different analog ground and digital ground if so for any reason or not do you short analog and digital grounds what is the type of mbist controllers you used did you run capture mode simulations do you used any test-compression logic in your chip what is your fanout tree count
vlsi interview 4
VLSI Interview question what is the difference between mealy and moore state-machines
Ans: In the mealy state machine we can calculate the next state and output both from the input and state. But in the moore state machine we can calculate only next state but not output from the input and state and the output is issued according to next state. How to solve setup & Hold violations in the design
Ans: To solve setup violation 1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx] 3. Tweak launch-flop to have better slew at the clock pin, thiswill make CK->Q of launch flop to be fast there by helping fixing setup violations 4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews) To solve Hold Violations 1. Adding delay/buffer[as buffer offers lesser delay, we go for spl Delay cells whose functionality Y=A, but with more delay] 2. Making the launch flop clock reaching delayed 3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip] What is antenna Violation & ways to prevent it
Ans: During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transistor gate connected to these long metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation. The ways to prevent is , by making jogging the metal line, which is atleast one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called accumulative antenna effect. Another way of preventing is adding reverse Diodes at the gates what is tie-high and tie-low cells and where it is used
Ans: Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to
power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high…(so tie high is a power supply cell)…while the cells which wants Vss connects itself to Tie-low. what is the difference between latches and flip-flops based designs
Ans: Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. What is High-Vt and Low-Vt cells.
Ans: Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices which have less delay but leakage is high. The thereshold(t) vloltage dictates the transistor switching speed , it matters how much minimum threshold voltage applied can make the transistor switching to active state which results to how fast we can switch the trasistor. disadvantage is it needs to maintain the transistor in a minimum subthreshold voltage level to make ir switch fast so it leads to leakage of current inturn loss of power. What is LEF mean?
Ans: LEF is an ASCII data format from Cadence Design inc, to describe a standard cell library. It includes the design rules for routing and the Abstract layout of the cells. LEF file contains the following, Technology: layer, design rules, via-definitions, metal-capacitance
Site : Site extension Macros : cell descriptions, cell dimensions, layout of pins and blockages, capacitances what is DEF mean?
Ans: DEF is an ASCII data format from Cadence Design inc., to describe Design related information.
vlsi interview 7
VLSI Interview question what is meant by Library Characterizing
Ans: Characterization in terms of delay, power consumption,.. what is meant by wireload model
Ans: In the synthesis tool, in order to model the wires we use a concept called as “Wireload models”, Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for “n” number of fanin then we estimate its delay as say “x” delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available what are the measures to be taken to design for optimized area
Ans:
As silicon real-estate is very costly and saving is directly propotional to the company’s revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets. what all will you be thinking while performing floorplan
Ans: Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usuage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise. what are the measures in the Design taken for Meeting Signal-integrity targets
Ans: As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let’s see now by what are all the measures we can reduce/solve it. As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts. Shield the nets with power-nets for high frequency signal nets to prevent from SI.
Enable SI aware routing , so that the tool takes care for SI Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements Route signals on different layers orthogonal to each other Minimize the parallel run-length wires, by inserting buffers. what are the measures taken in the Design achieving better Yield
Ans: Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge. Create more powerful stringent runset files with pessimistic spacing/short rules. Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it. For via-reliability issues, use redundant vias, to reduce the chances for viabreakage. In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories. Optimal placing of de-coupling capacitances, reduces the power-surges. Doubling the width of the non-critical nets, clock-nets can increase the yield parameter. Ensure that the poly-orientation are maintained. what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions
Ans: Designing for Optimal integration of Analog and Digital As today’s IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists seperate ground for digital and analog ground to reduce the
noise. Place appropriate guard-rings around the analog-macro’s. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion. what are the steps incorporated for Engineering Change Order[ECO]
Ans: As more and more complex the IC design is , and with lot of first time application , is more prone to last minute changes, there should be provision in the design-flow to accomodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO). Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved. what are the steps performed to achieve Lithography friendly Design
Ans: Designing for Manufacturability requires validating the design full-filling lithography rules Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets. what does synthesis mean
Ans: Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells.. What are the various ways to reduce Clock Insertion Delay in the Design
Ans:
1. Number of Clock sinks 2. Balancing two different clock frequencies 3. Placement of clock sinks. 4. Placement of Clock gating cells 5. Clock tree buffers/inverters drive strength’s 6. Clock Transition 7. placement of Clockgating cells and the clock sinks 8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockgates) … what are the various functional verification methodologies
Ans: TLM(Transaction Level Modelling) Linting RTL Simulation ( Enivronment involving : stimulus generators, monitors, response checkers, transactors) Gate level Simulation Mixed-signal simulations Regression What does formal verification mean?
Ans: Formal verification uses Mathematical techniquest by prooving the design through assertions or properties. Correctness of the design can be achieved through assertions with out the necessity for simulations. The methods of formal verification are 1. Equivalence checking In this method of checking the designs are compared based on mathematical equations and compared whether they are equal or not . Original RTL vs Modified RTL RTL vs Netlist Golden Netlist vs Modified/Edited Netlist
Synthesis Netlist vs Place and route Netlist Remember : Formal verification doesnt check for functionality of the RTL code. It will be only checking the equivalence. 2. Model checking Property specification languages like PSL or SVA, are formally analyzed to see if they are always true for a design. This can exhaustively prove if a property is correct, but does tend to suffer from state-space explosion: the time to analyse a design is directly propotional to the amount of states.
vlsi interview 5
VLSI Interview question answers Steps involved in designing an optimal padring
Ans: 1. Make sure you have corner-pads, across all the corners of the padring, This is mainly to have the power-continuity as well as the resistance is less 2. Ensure that the Padring ful-fills the ESD requirement, Identifyh the powerdomains, split the domains, Ensure common ground across all the domains. 3. Ensure the padring has ful-filled the SSN(Simultaneous Switching Noise) requirement. 4. Placing Transfer-cell Pads in the cross power-domains, for different height pads, to have rail connectivity. 5. Ensure that the design has sufficient core power-pads. 6. Choose the Drive-strenght of the pads based on the current requirements, timing. 7. Ensure that there is seperate analog ground and power pads. 8. A No-Connection Pad is used to fill out the pad-frame if there is no requirement for I/O’s.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with un-connected inputs, as they consume power if the inputs float.
9. Ensure that oscillator-pads are used for clock inputs. 10. In-case if the design requirement for source synchronous circuits, make sure that the clock and data pads are of same drive-strength. 11. Breaker-pads are used to break the power-ring, and to isolate the powerstructure across the pads. 12. Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the maximum current provided at the pin. 13. In case if required , place pads with capacitance. What is metastability and steps to prevent it.
Ans: Metastability is an unknown state it is neither Zero nor One.Metastability happens for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously. Steps to prevent Metastability. 1. Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the metastable event. 2. Use synchronizers between cross-clocking domains to reduce the possibility from metastability. 3. Using Faster flip-flops (which has narrower Metastable Window). 12. what is local-skew, global-skew,useful-skew mean?
Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path. Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain. Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design. what is meant by virtual clock definition and why do i need it?
Ans: Virtual clock is mainly used to model the I/O timing specification. Based on what clock the output/input pads are passing the data. What are the various timing-paths which i should take care in my STA runs?
Ans: 1. Timing path starting from an input-port and ending at the output port(purely combinational path). 2. Timing path starting from an input-port and ending at the register. 3. Timing path starting from an Register and ending at the output-port. 4. Timing path starting from an register and ending at the register. What are the various components of Leakage-power?
Ans: 1. sub-threshold leakage,….think of ths answer What are the various yield-losses in the design?
Ans: The yield loss in the design is characterized by
1. Functional yield losses, mainly caused by spot defects , especially (shorts & opens) 2. Parametric yield losses, due to process variations.
electronics interview Electronics interview question •What is meant by D-FF? •What is the basic difference between Latches and Flip flops? •What is a multiplexer? •How can you convert an SR Flip-flop to a JK Flip-flop? •How can you convert an JK Flip-flop to a D Flip-flop? •What is Race-around problem? How can you rectify it? •Which semiconductor device is used as a voltage regulator and why? •What do you mean by an ideal voltage source? •What do you mean by zener breakdown and avalanche breakdown? •What are the different types of filters? •What is the need of filtering ideal response of filters and actual response of filters? •What is sampling theorem? •What is impulse response?
•Explain the advantages and disadvantages of FIR filters compared to IIR counterparts. •What is CMRR? Explain briefly. •What do you mean by half-duplex and full-duplex communication? Explain briefly. •Which range of signals are used for terrestrial transmission? •What is the need for modulation? •Which type of modulation is used in TV transmission? •Why we use vestigial side band (VSB-C3F) transmission for picture? •When transmitting digital signals is it necessary to transmit some harmonics in addition to fundamental frequency? •For asynchronous transmission, is it necessary to supply some synchronizing pulses additionally or to supply or to supply start and stop bit? •BPFSK is more efficient than BFSK in presence of noise. Why? •What is meant by pre-emphasis and de-emphasis? •What do you mean by 3 dB cutoff frequency? Why is it 3 dB, not 1 dB? •What do you mean by ASCII, EBCDIC?
vlsi interview question 2
1. Explain how a MOSFET works, should explain in drawing of cross section of mosfet in cmos process
2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation 3. Explain the various MOSFET Capacitances & their significance 4. Draw a CMOS Inverter. Explain its transfer characteristics 5. Explain sizing of the inverter 6. How do you size NMOS and PMOS transistors to increase the threshold voltage? 7. What is Noise Margin? Explain the procedure to determine Noise Margin 8. Give the expression for CMOS switching power dissipation 9. What is Body Effect? 10. Describe the various effects of scaling 11. Give the expression for calculating Delay in CMOS circuit 12. What happens to delay if you increase load capacitance? 13. What happens to delay if we include a resistance at the output of a CMOS circuit? 14. What are the limitations in increasing the power supply to reduce delay? 15. How does Resistance of the metal lines vary with increasing thickness and increasing length? 16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
17. What happens if we increase the number of contacts or via from one metal layer to the next? 18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times 19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 20. Draw the stick diagram of a NOR gate. Optimize it 21. For CMOS logic, give the various techniques you know to minimize power consumption 22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus 23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? 25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) 26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram 27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate? 28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 29. Draw a 6-T SRAM Cell and explain the Read and Write operations 30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
31. What happens if we use an Inverter instead of the Differential Sense Amplifier? 32. Draw the SRAM Write Circuitry 33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? 34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance? 35. What’s the critical path in a SRAM? 36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? 37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers 38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 39. How can you model a SRAM at RTL Level? 40. What’s the difference between Testing & Verification? 41. For an AND-OR implementation of a two input Mux, how do you test for StuckAt-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) 42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
asic interview 1
application specific integrated circuit interview questions and answers 1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signals, while NMOS networks are used to product low (0) signals? PMOS is used to drive ‘high’ because of the threshold voltage-effectThe same is true for NMOS to drive ‘low’.A NMOS device cant drive a full ’1′ and PMOS cant drive full ’0′ Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing 2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean? The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)If given only one number it’s the width combined with a default length 3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four? To limit the height of the stack. As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be. 4) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero? Cool What is a transmission gate, and what is it used for typically? Why are transmission gates made with both PMOS and NMOS transistors?
9) What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal’s path? 10) What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal? 11) What is the difference between a mask layer and a drawn layer in an IC layout? Why do layout designers usually only specify drawn layers? 12) In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each? A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped, however, it’s off grid with 45 degree angle. Polygon is always on-grid, unless it’s a copy and flip. However, polygon is hard to edit and work with. 13) What is the difference between a contact and a via? What is a “stacked” via process? Via: a contact between two conductive layers. Contact:Opening in an insulating film to allow contact to an underlying electronic device. The placement of vias directly over the contacts or other,lower vias is known as stacked via. 14) Why is it that NMOS transistors can be created directly in a P-type substrate, whereas PMOS transistors must be created in an N-type well? 15) Why must transistors be provided with “bulk” connections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why?
To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules? What is their major purpose? How are design rules created? 17) What are width rules, space rules, and overlap rules? 18) What is a “vertical connection diagram”? What is it used for? vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes. 19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why? 20) What are the major advantages of hierarchical IC design? Concurrent design • Design reuse • Predictable schedules
vlsi interview question 1
1. What happens if Vds is increased over saturation? 2. In the I-V characteristics curve, why is the saturation curve flat or constant? 3. What happens if a resistor is added in series with the drain in a mos transistor?
4. What are the different regions of operation in a mos transistor? 5. What are the effects of the output characteristics for a change in the beta (ß) 6. value? 7. What is the effect of body bias? 8. What is hot electron effect and how can it be eliminated? 9. What is latchup problem and how can it be eliminated? 10. What is channel length modulation? 11. What is the effect of temperature on threshold voltage? 12. What is the effect of temperature on mobility? 13. What are the different types of scaling? 14. What is stage ratio? 15. What is charge sharing on a bus? 16. What is electron migration and how can it be eliminated? 17. Can both pmos and nmos transistors pass good 1 and good 0? Explain. 18. Why is only nmos used in pass transistor logic? 19. What are the different methodologies used to reduce the charge sharing in 20. dynamic logic? 21. What are setup and hold time violations? How can they be eliminated?
22. Explain the operation of basic sram and dram. 23. Of Read and Write operations, which ones take more time? Explain. 24. What is meant by clock race? 25. What is meant by single phase and double phase clocking? 26. If given a choice between NAND and NOR gates, which one would you pick? Explain. 27. What are stuck-at faults? 28. What is meant by ATPG? 29. What is meant by noise margin in an inverter? How can you overcome it? 30. Why is size of pmos transistor chosen to be close to three times of an nmos 31. transistor? 32. Explain the origin of the various capacitances in the mos transistor and the 33. physical reasoning behind it. 34. Why should the number of CMOS transistors that are connected in series be 35. reduced? 36. What is charge sharing between bus and memory element? 37. What is crosstalk and how can it be avoided? 38. Two inverters are connected in series. The widths of pmos and nmos transistors of 39. the second inverter are 100 and 50 respectively. If the fan-out is assumed to be 3, 40. what would be the widths of the transistors in the first inverter?
41. In the above situation, what would be the widths of the transistors if the first 42. inverter is replaced by NAND and NOR gates? 43. What is the difference between a latch and flip-flop? Give examples of the 44. applications of each. 45. Realize an XOR gate using NAND gate. 46. What are the advantages and disadvantages of Bi-CMOS process? 47. Draw an XOR gate with using minimal number of transistors and explain the 48. operation. 49. What are the critical parameters in a latch and flip-flop? 50. What is the significance of sense amplifier in an SRAM? 51. Explain Domino logic. 52. What are the differences between PALs, PLAs, FPGAs, ASICs and PLDs? 53. What are the advantages of depletion mode devices over the enhancement mode 54. devices? 55. How can the rise and fall times in an inverter be equated? 56. What is meant by leakage current? 57. Realize an OR gate using NAND gate. 58. Realize an NAND gate using a 2:1 multiplexer. 59. Realize an NOR gate using a 2:1 multiplexer. 60. Draw the layout of a simple inverter. 61. What are the substrates of pmos and nmos transistors connected to and explain the 62. results if the connections are interchanged with the other. 63. What are repeaters in VLSI design? 64. What is meant by tunneling problem?
65. What is meant by negative biased instability and how can it be avoided? 66. What is Elmore delay algorithm? 67. What are false and multi cycle paths? 68. What is meant by metastability? 69. What are the various factors that need to be considered while choosing a 70. technology library for a design? 71. What is meant by clock skew and how can it be avoided? 72. When stated as 0.13µm CMOS technology, what does 0.13 represent? 73. What is the effect of Vdd on delay? 74. What are the various limitations in changing the voltage for less delay? 75. What is the difference between testing and verification? 76. While trying to drive a huge load, driver circuits are designed with number of 77. stages with a gradual increase in sizes. Why is this done so? What not use just one 78. big driver gate? 79. What is the effect of increase in the number of contacts and vias in the 80. interconnect layers? 81. How does the resistance of the metal layer vary with increasing thickness and 82. increasing length? 83. What is the effect of delay, rise and fall times with increase in load capacitance? 84. In a simple inverter circuit, if the pmos in the Pull-Up Network is replaced by an 85. nmos and if the nmos in the Pull-Down Network is replaced by a pmos transistor, 86. will the design work as an non-inverting buffer?
Justify your answer.
analog IC Interview 2 Analog Integrated Circuit techniques These analog design techniques are also useful for interview preparation 1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is low. 2. Present art of analog design still uses the transistor in the saturation region. So one should always keep Vgs of the Transistor 30% above the Vt. 3. One should always split the big transistor into small transistors having width or length feature size <= 15um. 4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systamatic Offset in the circuit. 5. One should make all the required pins in the schmetic before generating the layout view. All IO pins should be a metal2 pins whereas Vdd and Ground should be metal1 pins. 6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the trasistor can be anything between Vt(Typical) 20%. So we check our circuit for the extreme cases i.e. Vt + 20%, Vt 20%. A transistor having Vt 20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It's just a way to di erentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are stis.ed with the circuit performance with typical models than we check it in di erent process corners, to take the process variation into
account. Vt is just one example of the process variation there are others parameter too. 7. Its thumb rule that poly resistance has a 20% process variation whereas well resistance has got 10%. But the poly resistance has got lower temperature coe.cent and lower Sheet Resistance than well resistance. So we choose the resistance type depending upon the requirments. Poly Capacitance has got a process variation of 10%. 8. One should also check the circuit performance with the temperature variation. We usuly do it for the range of -40C to 85C. 9. One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells. 10. In Layout, all transistors should be placed in one direction, to provide the same environment to all the transistors. 11. One should place all transistor in layout with a due care to the pinposition before start routing them. 12. One should always use the Metal 1 for horizontal routing and Metal 2 for the vertical routing as far as possible. 13. One should never use POLY as routing layer when the interconnects carries a current. One can have a short gate connection using poly. 14. One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance. 15. Current in all the transistor and resistor part should ow in the same direction. 16. One should do the Power(Vdd & Gnd) routing in top layer metal (metal5 only). Because Top layer metals are usually thicker and wider and so has low resistance. 17. One should always merge drain and source of transistor (of same type) connected together.
18. To minimize the process variation in the Resistor value one should always take the resistor's width three to four times of the default value. we do it to decrease the value of dR/dL 19. One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing. 20. One should always make a Common Centroid structure for the matched transistor in the layout. .Each di erential pair transistor should be divide into four transistors and should be placed in two rows common centroid structure. .One may use the the linear common centroid structure for the current mirror circuit. 21. It's advisiable to put a dummy layers around the resistance and the capacitance to avoid the erosion at the time of etching. 22. One should always have a Guard Ring arround the di erential pair. 23. Always put a Guard Ring arround the N-well and P-well. 24. Thumb rule for the metal current density is 0:8mA=.m. It's larger for the top most metal layer. 25. To avoid the Latchup, one should always make the PN junction reverse biased i.e. In NWELL should be connected to positive power supply(Vdd) and PWELL should be connected to negative power supply( Gnd). Designers do it to make the leakage current small. 26. It's always a good practice to use a infotext layer to put the name of the device on the top of it in layout and have a netname for every nets in schematic. Designer should put the pin name on the top of the pin with same metaltxt layer because hercuels takes the netname from metaltxt only whereas Diva takes from the pinname. 27. Cadence SPICE simulator take vdd! & gnd! as a global Vdd and Gnd net i.e. any net ending with ' !' is ocnsidered as a global net..
Common Note : The basic principle is same , but for some notes vary from company to company
methods available to the designer to reduce power consumption in a circuit. The common methods include: Simplifying the complexity of the circuit Taking conventional architectures and converting them into designs that consume less power Gearing the integrated circuit technology towards low power performance by using, for instance, high Vt processes Decreasing transistor dimensions together with lowering the supply voltage Before delving into power reduction techniques for high speed serial interfaces, consider the case of an operational amplifier as the techniques applied here are pertinent to many other circuit examples. (And also because I know a lot about op-amp design!) a. The power consumption of the operational amplifier can be reduced by use of an architecture with only a single (differential) stage. This will reduce the current consumption of the device. However, a method of maximizing the gain, whilst preserving an acceptable bandwidth and slew rate are now required in the single gain stage. b. The output stage could be designed to provide sufficient output drive while quiescently consuming as little power as possible. c. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This is achieved by reducing the internal stage currents by programming an external current in the form of a resistor outside the integrated circuit. Speed, voltage noise and junction leakage will now become major considerations for the designer as these parameters are affected by the value of the bias current programmed. d. Two important factors that determine the maximum power dissipation in an integrated circuit are the technology used for the design and the type of application. A particular application for CMOS op-amps could be low power switched capacitor filters. If a lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there are two important requirements in the op-amp design. First there must be enough current to charge the compensation capacitor and load capacitor in the
required time. Second there must be enough current in the second gain stage transistor to maintain a phase margin of 45º to avoid ringing and degradation of the settling time. If the output current of this circuit is less than the quiescent bias current then this is known as a Class A circuit. There’s a nice write-up in Gray and Meyer. e. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class AB and dynamic op-amps. The Class AB output stage is designed to be biased at small currents so quiescent power dissipation is correspondingly lower. f. The basic two-stage differential input op-amp can be designed in the subthreshold current region to minimize the current consumption. The next posting will describe techniques to save power in high speed serial interfaces both in active and sleep/low-power modes.
interview question
VLSI Interview question , asic interview question, discussion Why must transistors be provided with “bulk” connections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why? To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules? What is their major purpose? How are design rules created? 17) What are width rules, space rules, and overlap rules? 18) What is a “vertical connection diagram”? What is it used for?
vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes. 19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why?
interview question 3
1. Are you familiar with the term MESI? 2. Are you familiar with the term snooping? 3. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads. 4. In what cases do you need to double clock a signal before presenting it to a synchronous state machine? 5. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem? 6. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation? 7. Explain the operation considering a two processor computer system with a cache for each processor. 8. What are the main issues associated with multiprocessor caches and how might you solve it? 9. Explain the difference between write through and write back cache. 10. What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++? 11. Have you studied busses? What types? 12. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ? 13. How many bit combinations are there in a byte? 14. What is the difference between = and == in C?
interview question 4
1. Are you familiar with the term MESI? 2. Are you familiar with the term snooping? 3. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads. 4. In what cases do you need to double clock a signal before presenting it to a synchronous state machine? 5. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem? 6. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation? 7. Explain the operation considering a two processor computer system with a cache for each processor. 8. What are the main issues associated with multiprocessor caches and how might you solve it? 9. Explain the difference between write through and write back cache. 10. What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++? 11. Have you studied busses? What types? 12. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ? 13. How many bit combinations are there in a byte? 14. What is the difference between = and == in C?
interview question 5
• When will you use a latch and a flipflop in a sequential design? • Design a 1-bit fulladder using a decoder and 2 “or” gates? • You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of
20Mhz or reduce the power supply of 5Volts and why? • In a SRAM circuit, how do you design the precharge and how do you size it? • In a PLL, what elements(like XOR gates or Flipflops) can be used to design the phase detector? 1. Give two ways of converting a two input NAND gate to an inverter 2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt) 3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? 4. Give a circuit to divide frequency of clock cycle by two 5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) 6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors) 7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? 8. What are the different Adder circuits you studied? 9. Give the truth table for a Half Adder. Give a gate level implementation of the same. 10. Draw a Transmission Gate-based D-Latch. 11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) 12. How do you detect if two 8-bit signals are same? 13. How do you detect a sequence of “1101″ arriving serially from a signal line? 14. Design any FSM in VHDL or Verilog. 15. Explain RC circuit’s charging and discharging. 16. Explain the working of a binary counter. 17. Describe how you would reverse a singly linked list.
asic interview question
I think there is no or small difference between asic interview and vlsi interview, some vlsi interview questions I am posting, which I have collected 1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signals, while NMOS networks are used to product low (0) signals? PMOS is used to drive ‘high’ because of the threshold voltage-effectThe same is true for NMOS to drive ‘low’.A NMOS device cant drive a full ‘1′ and PMOS cant drive full ‘0′ Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS gives you a defined rail to rail swing 2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean? The numbers you see there are usually the width and the length of the devices (channel dimensions drawn in the layout)If given only one number it’s the width combined with a default length 3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four? To limit the height of the stack. As we all know, the number of transistor in the stack is usually equal to the number of input. The higher the stack the slower it will be. 4) What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero? Cool What is a transmission gate, and what is it used for typically? Why are transmission gates made with both PMOS and NMOS transistors? 9) What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal’s path? 10) What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal? 11) What is the difference between a mask layer and a drawn layer in an IC layout? Why do layout designers usually only specify drawn layers? 12) In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each? A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshaped,
however, it’s off grid with 45 degree angle. Polygon is always on-grid, unless it’s a copy and flip. However, polygon is hard to edit and work with. 13) What is the difference between a contact and a via? What is a “stacked” via process? Via: a contact between two conductive layers. Contact:Opening in an insulating film to allow contact to an underlying electronic device. The placement of vias directly over the contacts or other,lower vias is known as stacked via. 14) Why is it that NMOS transistors can be created directly in a P-type substrate, whereas PMOS transistors must be created in an N-type well? 15) Why must transistors be provided with “bulk” connections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why? To make the parasitic diodes reverse biased.p type substrstrate is generally connected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules? What is their major purpose? How are design rules created? 17) What are width rules, space rules, and overlap rules? 18) What is a “vertical connection diagram”? What is it used for? vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex processses, such as DRAM processes. 19) The routing strategies for the power grid and global signals are usually defined at the start of planning a new chip floorplan. Why? 20) What are the major advantages of hierarchical IC design? Concurrent design • Design reuse • Predictable schedules
interview question 6 Some interview questions 1) Give two ways of converting a two input NAND gate to an inverter 2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt) 3) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? 4) Give a circuit to divide frequency of clock cycle by two 5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) 6) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors) 7) The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? What are the different Adder circuits you studied? 9) Give the truth table for a Half Adder. Give a gate level implementation of the same. 10) Draw a Transmission Gate-based D-Latch. 11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) 12) How do you detect if two 8-bit signals are same? 13) How do you detect a sequence of “1101? arriving serially from a signal line? 14) Design any FSM in VHDL or Verilog
vlsi Interview question what is your roles and responsibilities in that project what all cores where present in that chip what is the technology like 130,90,65,45nm what is the clock-frequency how many clock-domains
what is the voltage value what is the macro-count what is the flip-flop count what are the various analog macros how many pads were there what is your skew you had achieved what is your insertion delays what is your pll jitter how did you model your uncertainities or variations how many power-domains were there did you have multi-VDD if you had multi-VDD how did you handle insertion of level-shifters what is the SSN(simultaneous switching noise) pad ratios used in your design. how did you prevented noise in your chip how many placeable instances what is the cell-row utilization is your design pad-limited or core-limited did you multiplexed your pads what type of package wafer bond or flip-chip if flip-chip how did you distributed power bumps any special strategy how many metal layers in your technology did you used in house library or from any vendor what is the die-area of your chip vlsi interview questions, asic interview questions ,
interview question 7
Most common question is draw basic digital gates using transistor. as an expert of vlsi , I will tell that go through vlsi book, any book is fine, solve as many questions it will enhance your skill and bring more confidence on vlsi interview. What is antenna Violation & ways to prevent it Ans:
During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transistor gate connected to these long metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation. The ways to prevent is , by making jogging the metal line, which is atleast one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called accumulative antenna effect. Another way of preventing is adding reverse Diodes at the gates what is tie-high and tie-low cells and where it is used Ans: Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In deep sub micron processes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high…(so tie high is a power supply cell)…while the cells which wants Vss connects itself to Tie-low. what is the difference between latches and flip-flops based designs Ans: Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flop based design is that latch allowes time borrowing which a tradition flop does not. That makes latch based design more efficient. But at the same time, latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex.
