Microprocessors
238
Programmable Interval Timer 8253/8254
Example 2: Write a program to generate a square wave of 1KHz frequency on OUT 1 pin of 8253/54. Assume CLK1 frequency is 1MHz and address for control register = 0BH, counter 1 = 09H and counter 2 = 0AH. Sol. : To get square wave mode 3 is selected count should be
1 MHz MHz 1 KHz KHz
= 1000
Control word : D7
D6
SC1
SC2
0
1
D5
D4
RW1 RW0 1
1
D3
D2
D1
D0
M2
M1
M0
BCD
0
1
1
1
=
7 7H
Source program MOV MOV
AL,7 AL,77H 7H
OUT
0B 0BH,AL
MOV
AL AL,00H
OUT OUT
09H, 09H,AL AL
MOV
AL AL,10
OUT OUT
09H, 09H,AL AL
;
Lo Loads
co control
;
the the
;
lo l oads
lo lower
;
Lo Loads
hi higher
cont contro rol l
wo word
(7 (77H)
in in
regi regist ster er. . by b yte
by byte
(0 ( 00)
of of
(1 (10)
th t he
of of
9.7 Interfacing of 8253/54 with 8086 9.7.1 With 8-Bit Address
D0
D0
D7
D7
A1
A0
A2
A1
CLK0 GATE0 OUT0 CLK1 GATE1
M/IO RD A0 WR
IOR
IOW
RD
OUT1
WR
CLK2 GATE2 8253/54
OUT 2
A3 A4 A5
CS
A6 A7
Fig. 9.12 Interfacing of 8253/54 with 8-bit address
th the
co c ount
co count
Microprocessors
239
Programmable Interval Timer 8253/8254
We know that, 8253/54 has two address and eight data lines. Therefore, it is necessary to interface lower byte of demultiplexed data bus to 8253/54. The address lines A1 and A2 are connected to the the address lines of 8253/54. The 8253/54 IC decodes A1 and A2 lines internally to select one of its ports or control register. The remaining address lines (A7-A3) can be used to generate chip select signal. Fig. 9.12 (see Fig. on previous page) shows the interfacing of 8253/54 with 8086. Address Map : Ports / control Register
Address lines
Address
A7 A6 A5 A4 A3 A2 A1 A0 Counter 0
0
0
0
0
0
0
0
0
00H
Counter 1
0
0
0
0
0
0
1
0
02H
Counter 2
0
0
0
0
0
1
0
0
04H
Control Register
0
0
0
0
0
1
1
0
06H
9.7.2 With 16-Bit Address Fig. 9.13 shows the interfacing of 8253/54 with 8086 with 16-bit address. Here RD and WR signals are activated when M/IO signal is low, indicating I/O bus cycle. To get absolute address, all remaining address lines (A3 - A15) are used to decode the address for 8253/54. CLK0
D0
D0
D7
D7
A1
A0
A2
A1
CLK1
RD
OUT1
WR
CLK2
GATE0 OUT0
GATE1
M/IO RD A0 WR
IOR
IOW
8253/54
GATE2 OUT2
A3 A4 A5 A6 A7 A8 A9
CS
A10 A11 A12 A13 A14 A15
Fig. 9.13 Interfacing 8253/54 with 16-bit address
Microprocessors
240
Programmable Interval Timer 8253/8254
Note : When 16-bit address is used it is necessary to use indirect addressing mode to access 8253/8254. Address Map : Ports/Control
Address lines
Address
Register
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Counter 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000H
Counter 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0002H
Counter 2
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0004H
Control Register
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0006H
9.8 Interfacing of 8253/54 with 8088 9.8.1 With 8-Bit Address We know that, 8253/54 has two address and eight data lines. Therefore, it is necessary to interface lower byte of demultiplexed data bus to 8253/54. The address lines A0 and A1 are connected to the address lines of 8253/54. The 8253/54 IC decodes A0 and A1 lines internally to select one of its ports or control register. The remaining address lines (A7-A2) can be used to generate chip select signal. Fig. 9.14 shows the interfacing of 8253/54 with 8086.
RD
D0
D0
D7
D7
A0
A0
A1
A1
CLK0 GATE0 OUT0 CLK1 GATE1
RD
OUT1
WR
CLK2
IO/M
GATE2
WR
8253/54
A2 A3 A4 A5
CS
A6 A7
Fig. 9.14 Interfacing of 8253/54 with 8-bit address
OUT 2
Microprocessors
241
Programmable Interval Timer 8253/8254
Address map : Ports / control register
Address lines
Address
A7 A6 A5 A4 A3 A2 A1 A0 Counter 0
0
0
0
0
0
0
0
0
00H
Counter 1
0
0
0
0
0
0
0
1
01H
Counter 2
0
0
0
0
0
0
1
0
02H
Control Register
0
0
0
0
0
0
1
1
03H
9.8.2 With 16-Bit Address Fig. 9.15 shows the interfacing of 8253/54 with 8086 with 16-bit address. Here RD and WR signals are activated when IO/M signal is high, indicating I/O bus cycle. To get absolute address, all remaining address lines (A2 - A15) are used to decode the address for 8253/54.
RD
CLK0
D0
D0
D7
D7
A0
A0
A1
A1
CLK1
RD
OUT1
WR
CLK2
GATE0 OUT0
GATE1
IO/M WR
8253/54
GATE2 OUT2
A2 A3 A4 A5 A6 A7 A8 A9
CS
A10 A11 A12 A13 A14 A15
Fig. 9.15 Interfacing of 8253/54 with 8-bit address
Note : When 16-bit address is used it is necessary to use indirect addressing mode to access 8253/8254.
Microprocessors
242
Programmable Interval Timer 8253/8254
Address map : Ports/Control
Address lines
Address
Register
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Counter 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000H
Counter 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0001H
Counter 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0002H
Control Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0003H
9.9 Interfacing 8253/54 to 8086 in Memory Mapped I/O In this type of I/O interfacing the 8086 uses 20 address lines to identify an I/O device, an I/O device is connected as if it is a memory register. The 8086 uses same control signals and instructions to access I/O as those of memory. Fig. 9.16 shows the interfacing of 8253/54 with 8086 in memory mapped I/O technique. Here RD and WR signals are activated when M/IO signal is high, indicating memory bus cycle. The A 1 - A 2 address lines are used by 8253/54 for internal decoding. To get absolute address, all remaining address lines (A 3 - A 19 ) are used to decode the address for 8255. Other signal connections are same as in I/O mapped I/O.
RD A0
D0
D0
D7
D7
A0
A0
A1
A1
CLK0 GATE0 OUT0 CLK1 GATE1 OUT1
RD
M/IO WR WR
8253/54
CLK2 GATE2 OUT2
CS
A3 A4 A5 A6 A7 A8 A9 A
10
A11 A12 A13 A14 A15 A16 A17 A18 A19
Fig. 9.16 Interfacing 8253/54 with 8086 in memory mapped I/O
Microprocessors
243
Programmable Interval Timer 8253/8254
I/O map : Register A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
A7
A6 A 5 A4
A3 A2 A1 A0
Address
Counter 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000H
Counter 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0002H
Counter 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0004H
Control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0006H
register
9.10 Interfacing 8253/54 to 8088 in Memory Mapped I/O Here, IO/M signal of 8088 is used to indicate memory bus cycle. When this signal low 8253/54 is activated, for read or write bus cycle. Address lines A 0 - A 1 are used for internal decoding of 8253/54 and remaining address lines (A 2 - A 19 ) are used to generate chip select signal for 8253/54 to get absolute address. CLK0
D0
D0
D7
D7
A0
A0
A1
A1
CLK1
RD
OUT1
RD
GATE 0 OUT0
GATE 1
IO/M CLK2
WR WR
GATE 2
8253/54
OUT2 CS
A2 A3 A4 A5 A6 A7 A8 A9 A A A A A A 10 11 12 13 14 15
Fig. 9.17 Interfacing 8253/54 with 8088 in memory mapped I/O
I/O map : Register A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
A7
A6 A 5 A4
A3 A2 A1 A0
Address
Counter 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000H
Counter 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0001H
Counter 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0002H
Control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0003H
register
Microprocessors
244
Programmable Interval Timer 8253/8254
9.11 Applications 9.11.1 Pre-Settable Alarm System Program Statement : Design a pre-settable alarm system using 8253/54 timer. Use thumbwheel switches to accept 4 digit value in seconds. Alarm should last for 5 seconds. Do not use interrupt. Sol. : Fig. 9.18 shows the 8086 microprocessor based pre-settable alarm system. Thumbwheel switches are interfaced through 8255 ports. Timing parameters are derived from the 8253/54. 74LS138 decoder is used to generate chip select signals for 8253/54 and 8255. One more 74LS138 decoder is used to generate IOR, IOW, MEMR, and MEMW signals. A0 A2 A1
A15
A2 A1
D0 D7 M/IO RD
IOR
A0 IOW
WR
Reset out
D7 D0
A1 A0
8253/54
CS
G2
RD WR Reset
8255
PA7 PA4 PA3 PA0 PB7 PB4
G0
G1
O1
A1 A0
PC0
CS
PB3 PB0
C0
C2 O2
D7 D0
RD WR
O0
VCC
A3
A
A4
B
A5
C
A6
G1
A7
G2
VCC
Y0 3:8 Decoder
Y1
CLK1 10 kHz R
CLK generator
230 V AC
Alarm
Fig. 9.18 Pre-settable alarm system
Counter 0 of 8253/54 is programmed in mode 0 to give the pre-settable time period and counter 2 is programmed in mode 0 to give delay of 5 seconds. As we know, clock input for 8253/54 is 10 kHZ count required to get 1 second time interval is
Microprocessors
245
Count =
Programmable Interval Timer 8253/8254
1 sec Required Period = = 10000 = 1 Clock Period 100 s
10
4
= 2710H
This count value is loaded in the count register of the counter 1 and counter 1 is programmed in mode 2 to generate square wave with frequency 1 Hz. The output of counter 1 is fed to the clock input of counter 0 and counter 2. To read four digit of count, we need four thumbwheels. One thumbwheel switch can be interfaced using four input lines. So to interface four thumbwheels we need 16 lines. The IC 8255 is used to interface these thumbwheel switches. Two thumbewheel switches are connected to port A and other two are connected to port B. Address Map : Ports / Control Register
Address lines
Address
A7 A6 A5 A4 A3 A2 A1 A0 Counter 0
0
0
0
0
0
0
0
0
00H
Counter 1
0
0
0
0
0
0
1
0
02H
Counter 2
0
0
0
0
0
1
0
0
04H
Control register
0
0
0
0
0
1
1
0
06H
Port A
0
0
0
0
1
0
0
0
08H
Port B
0
0
0
0
1
0
1
0
0AH
Port C
0
0
0
0
1
1
0
0
0CH
Control register
0
0
0
0
1
1
1
0
0EH
Control Word to Read/Write value in count register of counter 0 of 8253/54 D7
D6
SC1
SC2
0
0
D5
D4
RW1 RW0 1
D0 =1 D1, D2, D3 = 000 D4, D5 = 11 D6, D7 = 00
1
D3
D2
D1
D0
M2
M1
M0
BCD
0
0
0
1
=
31H
BCD Count Mode : Square wave rate generator Read/ Write lower byte first and then higher byte. Counter 0
Control Word to Read/Write value in count register of counter 1 of 8253/54 D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC2
RW1
RW0
M2
M1
M0
BCD
0
1
1
1
0
0
0
1
=
71H
Microprocessors
246
D0 D1, D2, D3 D4, D5 D6, D7
= = = =
1 000 11 01
Programmable Interval Timer 8253/8254
BCD Count Mode : Square wave rate generator Read/Write lower byte first and then higher byte. Counter 1
Control Word to latch value in count register of counter 0 of 8253/54 D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC2
RW1
RW0
M2
M1
M0
BCD
0
0
0
0
0
0
0
1
D0 D1, D2, D3 D4, D5 D6, D7
= = = =
=
01H
1 BCD Count 000 Mode : Square wave rate generator 00 Read/ Write lower byte first and then higher byte. 00 Counter 0
Control Word to latch value in count register of counter 1 of 8253/54 D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC2
RW1
RW0
M2
M1
M0
BCD
0
1
0
0
0
0
0
1
=
41H
D0 = 1 BCD Count D1, D2, D3 = 000 Mode : Square wave rate generator D4, D5 = 00 Read/ Write lower byte first and then higher byte. D6, D7 = 01 Counter 1 Control Word to initialise 8255 : Port A = I/P, Port B =I/P, Port C = O/P
BSR/IO 1
MODE A 0
0
PA 1
PCH MODE B PB 0
0
PCL
1
0
= 92H
Program: MOV
AL,92H
;
Load
OUT
0EH,AL
;
Initialise
;
word
;
address
AL,08H
;
Get
BL,AL
;
Store
;
the
count
;
Get
the
;
Store
START: IN MOV
IN MOV
AL,0AH BH,AL
control
at
the
word
8255
in
by
accumulator
sending
control
the of
control
lower
the
the
two
lower
higher
register digit two
two
higher
digit
digit
two
of
of
digit
the
count
of
the of
count
Microprocessors
BACK:
MOV
AL,31H
OUT
06,AL
MOV
AL,BL
OUT
00,AL
MOV
AL,BH
OUT
00,AL
MOV
AL,01H
OUT
06,AL
247
Programmable Interval Timer 8253/8254
;
the
count
;
Loads
;
register
;
load
;
of
;
Loads
lower
;
Loads
higher
;
Loads
control
;
register
;
latch
;
register
control
word
(31H)
in
the
control
to
16-bit
counter
count
in
the
count
register
0
byte
of
byte
the
of
word
count.
the
count.
(01H)
in
the
control
to
16-bit
count
of
the
counter
IN
AL,00H
;
Get
lower
CMP
AL,00H
;
Compare
JNZ
BACK
;
Repeat
IN
AL,00H
;
Get
CMP
AL,00H
;
Compare
JNZ
BACK
;
Repeat
MOV
AL,01H
;
Load
bit
OUT
0CH,AL
;
Send
it
CALL DELAY
;
Wait
for
5
MOV
AL,00H
;
Load
bit
pattern
OUT
0CH,AL
;
Send
it
JMP
START
;
Repeat
with
the
two
with
count
0 digits
two
of
the
count
digits
of
the
count
zero
pattern
to
the
zero
higher
to
in
Port
to
run
Alarm
C
Seconds
Port
to
stop
Alarm
C
Delay Routine :
This delay routine gives a delay of 5 seconds. Counter1 of 8253/54 is used to give delay of 1 second. As output of counter1 is used as a clock for counter2, the count in the counter2 acts as a multiplying factor. Therefore, by loading 05H in the count register of counter2 we get a delay of 5 (5 1) seconds. MOV
AL,71H
OUT
06,AL
;
Loads
control
;
control
word
(71H)in
the
register.
MOV
AL,10H
OUT
02,AL
;
Loads
lower
MOV
AL,27H
;
Loads
higher
byte byte
of of
the the
count. count.
Microprocessors
BACK:
248
Programmable Interval Timer 8253/8254
OUT
02H
MOV
AL,B1H
OUT
06H,AL
MOV
AL,05H
OUT
04,AL
;
Loads
lower
MOV
AL,00H
;
Loads
higher
OUT
04,AL
MOV
AL,81H
OUT
06,AL
;
Loads
control
;
control
;
to
;
register
;
counter
AL,04H
;
Get
CMP
AL,00
;
Compare
JNZ
BACK
;
If
IN
AL,04H
;
Get
CMP
AL,00
;
Compare
JNZ
BACK
;
If
;
Return
RET
byte
the
of
word
count.
the
(81H)
count.
in
the
16-bit
count
in
the
count
of 2
the
lower with
not
zero,
the
not
of
register
latch
IN
byte
two
zero, to
of
the
count
00H Repeat
higher with
digits
two
digits
of
the
count
00H Repeat
main
program
9.11.2 DC Motor Speed and Direction Control Let us see the application of 8254 timer as a DC motor speed controller. Fig. 9.19 shows the schematic diagram of the DC motor and its associated driver circuitry. As shown in the Fig .9.19 driver circuitry consists of IC 8254, a flip-flop, buffers and transistors. ( See Fig on next page) When flip-flop outputs are : Q = 0 and Q = 1, inverters 1 and 3 give output logic 0 and inverters 2 and 4 give output logic 1. As a result, transistors Q 1 and Q4 turn ON and transistors Q2 and Q3 turn OFF. Due to this VCC, supply is applied to the positive lead of the DC motor and ground is applied to the negative lead of the DC motor. This connection causes DC motor to rotate in the forward direction. When flip-flop outputs are : Q = 1 and Q = 0, the conditions of transistors are reversed and DC motor rotate in the reverse direction. Thus the direction of motor can be controlled by changing state of the flip-flop. If the duty cycle of the flip-flop output is kept 50%, then motor current is positive and negative for equal amount of time. If flip-flop output is varied with enough frequency then due to inertia of motor, motor will not rotate at all. But it will exhibit
Microprocessors
249
6 0 4 7
2
V 2 1 +
Q +
Q
6 0 4 7
4
2
Q
M
Programmable Interval Timer 8253/8254
s r o t r e v n i r o t c e l l o c n e p O 6 0 4 7
4
–
1
Q
3
*
6 0 4 7
3 6 0 4 7
1
Q
t e s e r P
Q
r a e l C
K L C
J
K
K 0 1
C C
V
0
1
0
0
1
K G T K G T L U L U C O C O
) z H M 8 ( K C O L C
7
0
7
D D
R O I
2
K G T L U C O
R W A
D R
0
D D
2
1
W O I
A
1
0
1
A
A
2
4 5 2 8 S C
2
D
A
I D O / R M A
R 0
W
0
Y
3
E
C
4
D 1
B
A A A
O
E
8 3 1 4 7
R 2
C G G G
5
A
6
A
7
r e m i t 4 5 2 8 e h t g n i s u l o r t n o c n o i t c e r i d d n a d e e p s r o t o m C D 9 1 . 9 . g i F
Microprocessors
250
Programmable Interval Timer 8253/8254
some holding torque because of the current flowing through it. Fig. 9.20 shows some timing diagrams and their effects on the speed and direction of the motor. 25600
CLR
Preset
Q
12800
(a) No rotation 25600
CLR
Preset
Q
2560
(b) High speed rotation in the reverse direction
25600
CLR
Preset
Q
23040
(c) High speed rotation in the forward direction
Fig. 9.20
Microprocessors
251
Programmable Interval Timer 8253/8254
The variable duty cycle is achieved by programming two counters, counter 0 and counter 1 of 8254. The counter 0 and counter 1 are both programmed to divide the input clock by 25,600. The duty cycle now can be changed by changing the point at which counter 0 is started in relationship to counter 1. The clock input is divided by each counter by 25,600. This produces the basic operating frequency for the motor and as 25,600 is divisible by 256 a short program given below allows 256 different speeds. ;
Procedure
to
control
;
Addresses
for
;
Counter
0
:
80H
;
Counter
1
:
82H
;
Counter
2
:
84H
;
Counter
3
:
86H
;
Control
word
8254
AGAIN:
EQU
are
and
direction
AX
PUSH
BX
0
:
00110100
B,
counter
1
:
01110100
B
;
save
register
;
Multiply
by
result
BL,100
MUL
BL
MOV
BX,AX
MOV
AX,COUNT
;
Subtract
SUB
AX,BX
;
multiplication
MOV
BX,AX
MOV
AL,01110100B
;
OUT
86H,AL
;
MOV
AX,COUNT
;
OUT
82H,AL
;
register
MOV
AL,AH
;
Count
=
OUT
82H,AL
;
25600
]
MOV
AL,11000010B
;
OUT
82H,AL
;
to
;
Read
back
Read
the
IN
CMP
[
Load for
[
[
Load
Send
1
Count
AL,82H
;
of
;
counter
1
;
Compare
it
1
command
latch
;
]
with
the
AH,AL
COUNT
word
counter
[
AX,BX
of
from
counter
;
AL,AH
100
control
AL,82H
XCHG
motor
:
MOV
MOV
DC
25600
PUSH
IN
of
for counter
; COUNT
speed
the
word
count
command
using
]
] with
calculated
Microprocessors
252 ; JB
AGAIN
Programmable Interval Timer 8253/8254
count
;
If [
not
equal
MOV
AL,00110100B
;
Load
OUT
86H,AL
;
MOV
AX,COUNT
;
control
OUT
80H,AL
;
register
MOV
AL,AH
;
count
=
OUT
80H,AL
;
25600
]
POP
BX
;
POP
AX
Counter [
Load
Restore
read
1
again
word
for
]
counter
0
with
registers
RET
As shown in the program, value passed in AL register decides the direction and speed of the DC motor. If value in AL is 80H then motor does not rotate. However, when value in AL approaches 00H, the motor rotates with increase in speed in forward direction. On the other hand, when value in AL approaches FFH, the motor rotates with increase in speed in reverse direction. The time interval between counter 1 and 0 is calculated in terms of count. This is accomplished by multiplying value in AL by 100 and then subtracting it from 25600. This is required because the counters are down-counters that count from the programmed count to 0, before restarting. Initially, counter 1 is started with count 25600. It is read and compared with the calculated cound until it is equal. Once it reaches to the calculated count, counter 0 is started with count 25600. From this point forward, both counters continue generating clear and preset pulses until the procedure is called again to adjust the speed and direction of the DC motor.
Review Questions 1. What is the necessity of the programmable interval timer? 2. List the features of any programmable interval timer. 3. List the differences between 8253 and 8254. 4. Draw and explain the functional block diagram of IC 8253/54. 5. Illustrate different modes of operations of 8253/54. 6. Give the control word format for 8253/54. 7. Using IC 8253, realise a square wave generator with 1 msec period if the input frequency to 8253 is 1MHz. 8. Design a monostable multivibrator to obtain a pulse width of 5 msec with 8253 using an external clock of 100 kHz.
Microprocessors
253
Programmable Interval Timer 8253/8254
University Questions 1. Explain the working of 8254 with block diagram. (VTU : Sept. 2000) 2. Write a short note on : D.C. motor speed control using microprocessor. (VTU : Sept. 2000) 3. The 8254 timer/counter is a 24 pin chip with the following pins. Show how it can be connected to 8088 (in I/O mapped I/O) to have the counter address located at 00H, 01H, 02H and the control word register addressed located at 03H. Data lines
8
rd , wr , cs
3
3 sets of (CLK, gate, out pins)
3 3= 9
A1 , A0
2
V CC, GND
2 ------24 -------
Total
(VTU: August 2001) qqq
