80286
References
Advanced Microprocessors and Peripherals : A K Ray (Chapter 9: page 444)
The Intel Microprocessors: Barry B Brey
References
Advanced Microprocessors and Peripherals : A K Ray (Chapter 9: page 444)
The Intel Microprocessors: Barry B Brey
80286
The second generation of 16-bit micro processors
Released in 1982 by Intel
68
First microprocessor with memory management management and protection a bilities
It has 24-bit address bus
pin IC
Able to address 16MB of memory and 1GB of virtual memory
versions of 80286 are available that r un on 12.5 MHz, 10 MHz and 8 MHz clock frequencies
Upwardly compati ble with the instr uction set of 8086
First CPU to incorporate the integrated memory management unit(MMU)
Functions of MMU:
Various
Memory Management
Data protection or Unauthorized access prevention
First processor that s upport virtual memory
Virtual
Memory can address
1 GB
of virtual memory
80286
The concept of virt ual memory is implemented using physical memory that the CPU can directly access and secondary memory that is used as a storage for data and program
Virtual
memory doesn¶t exist physically in a system
The program may be divided into a set of segments
At any instant, a segment portion of act ual program required for execution at that instant, exists in the physical memory at the time of execution
The segments of the program which have been already exec uted or are not req uired for execution at that instant, are availa ble in the secondary memory
Whenever
the portion of a program is required for execution by the CPU, it is fetched from the secondary memory and placed in the physical memory. This is called as swapping in of the program
A portion of the program or important partial results required for f urther execution, may be saved back on secondary storage to make the physical memory free for f urther execution of another required portion of the program . This is called as swapping out of the program
Swapping
In (Swapping)
Secondary
memory
Swapping
Out (Un Swapping) Secondary
memory
80286-
Internal Architecture
80286
Register Organisation
contains almost the same set of registers as in 8086 80286
Eight 16 bit
general purpose registers (AX, BX,
CX, DX, BP, SP, SI, DI)
Four 16 bit segment registers
Status and control registers (Flag Resgister)
Instr uction Pointer
Register Organisation
80286-
AH
AL
BH
BL
CH
CL
CS
DH
DL
DS
BP SI DI
SS ES
SP
General
purpose registers
Segment Registers
80286
Internal Block Diagram
Contains 4 f unctional parts:
1)
Address Unit(AU)
2)
Bus Unit (BU)
3)
Instr uction Unit (IU)
4) Execution Unit (EU)
80286
Internal Block Diagram
Address Unit(AU) :
Responsi ble for calculating the physical address of instr uctions and data that the CPU wants to access Address lines derived by this unit may be used to address different peripherals
Bus Unit (BU) :
Physical address computed by AU is handed over to BU
BU transmit this physical address over the address bus A0 ± A23
BU fetch instr uction bytes from memory
When
This task is done by the prefetcher module in the Bus Unit
one instr uction is getting exec uted, the subsequent instr uction is prefetched, decoded and kept ready for exec ution (instr uction pipelining)
These fetched instr ctions are arranged in a
6
Instruction Unit (IU) :
IU accepts instr uctions from the prefetch queue and an instr uction decoder decodes them one by one
The decoded instr uctions are stored in a decoded instr uction queue
Execution
Output
Unit (EU) :
of decoding circ uit drives a control circ uit
in EU
It is responsible for executing the instr uctions received frm the decoded instr uction queue
EU
contains the register bank and ALU
ALU is the heart of EU, which carries o ut all the arithmetic and logical operations and sends the results either over the data bus or back to the register bank
80286
± Operating Modes
Operating Modes
80286
works in two operating mode
Real Address Mode
Protected Virtual Address Mode
Real Addressing Mode
Just
act as a fast
Instr uction set is upward compatible with that of 8086
80286
Lines A20- A23 are not used
8086.
only address 1Mbytes of physical memory using A0- A19 in Real address mode
Real Addressing Mode ± Address Calculation
The 80286 reserves two fixed areas of physical memory for
System Initialization (FFFF0H to FFFFFH)
Interr upt Vector Table (00000H to
003FFH)
Protected Virtual Address Mode (PVAM)
The first processor to support the concepts of virtual memory
Swapping and Unswapping
Able to address
1 GB
of virtual memory
Large programs are divided into smaller segments which are arranged in appropriate sequence and are swapped in or out of primary memory as per the req uirements, for the complete execution of program
A data str ucture called descr iptor is associated with this segment, which contains the information regarding the segment
A set of such descriptors arranged in a proper sequence describes the complete program
How it works?
Descr iptors
Descr iptors
Large programs are divided into smaller segments which are arranged in appropriate sequence and are swapped in or out of primary memory as per the req uirements, for the complete execution of program
A data str ucture called descr iptor is associated with this segment, which contains the information regarding the segment
A set of such descriptors arranged in a proper sequence describes the complete program
It carry all relevant information regarding a segment and its access rights.
The descriptor segment, like
contains
information
Segment base address
Segment limit
Segment type
Privilege level
Segment availability in physical memory
Descriptor type
Segment use by another task
of
a
The set of descriptors is called as descr iptor table
Descr iptor Types
Types of descriptors:
Segment Descriptors
System Control Descriptors
Segment
Descr iptors
For code, stack and data segments
Code segment descriptors are refer code segment
used
to
Data segment descriptors are refer data segment
used
to
Contains
16 bit
segment limit
24 bit
segment base address
8 bit
Remaining 16 bits are reserved by Intel for f uture use and compatibility with f uture processors
access byte rights
INTEL RESERVED P
DPL
S
TYPE BASE(0-15) LIMIT(0-15)
A BASE(16-23)
8 bit P
access byte rights (Refer Page: 458 ) DPL
S
E
TYPE
A
P (Present)
Used to indicate whether segment is available in physical memory
P=1 Segment is mapped into physical memory
P=0 No mapping to physical memory
DPL (Descriptor Privilege Level)
Defines the range of privilege level
S (Segment Descriptor)
S=1 Code/Data/Stack Descriptor
E (Executable)
Used to distinguish between code & data segments
E=0
Data Segment
E=1
Code Segment
A (Accessed)
A indicates whether it is accessed previo usly or not
System Segment Descriptors
Used by 80286 to store system data and execution state of a task (for multitasking systems)
System segment descriptors are of 7 types
The types
The types 4-7 are called gate descr iptors
1-3
are called system descr iptors
System Descriptors
This descriptor contains
16-bit
segment limit
24-bit
segment base address
Access byte right contains
P-bit
2-bit
S-bit(0)
type field
Last word of the descriptor is reserved by the Intel.
DPL
Type 1 ± Available Task State Segment(TSS)
Type 2- Local descriptor table Type 3- B sy Task State Segment
Gate
Descriptors
The gate descriptors control the access to entry points of the code to be executed
Contains the information regarding
The destination of the control transfer
Required stack manipulations
Whether
it is present in the physical memory
or not
Privilege level
Type
Gate
descriptors provide mechanism to keep track of source and destination of control transfer .
Hence CPU can perform protection checks and controls the entry points of the destination code
There are four types of gate descriptors
Call gate
Task gate
Interr upt gate
Trap gate
Call gates are used to alter the privilege
Task gates are used to switch from one task to another .
Interr upt and trap gates are used to specify the corresponding routines.
Refer Gate Descriptor format (page: 4 60)
Descriptors
Segment Descriptors
System Control Descriptors
Code Segment descriptors Data Segment descriptors Stack Segment descriptors
System
Descr iptors Type 1
Gate Descr iptors Call Gate Task Gate
Type 2 Interrupt Gate Type 3
Trap Gate
Segment
Descr iptor Cache
registers
The concept of caching was introd uced in 80286
Caching is a method to minimize the time required for fetching the freq uently required descriptor information from the memory
Caching is the process of maintaining the most frequently required data for execution in a high speed memory called cache memory
6-byte
segment descriptor cache register is assigned to each of the fo ur segments A segment descriptor is a utomatically loaded in a segment descriptor cache register, whenever the associated segment register is loaded
Once
a cache register is loaded, all the information regarding the segment is o btained from the cache register instead of referring to the main memory for the descriptor again and again
These cache registers are not availa ble for programming
Program/Visible Segment Selectors CS DS SS ES 15
0
Segment Registers (loaded by program)
Program Invisible Access Rights
47
Segment Size
Segment Physical Base Address
40
30
Segment Descriptor Cache Registers (Automatically loaded by CPU)
16
15
0
Selector
Fields
In protected mode the contents of segment register is called selectors
16-bit
RPL (Requested Privilege Level), refers the privilege of that segment.
TI- Table Indicator TI=0 : GDT TI=1: LDT
Index ± Descriptor base
Descr iptor Tables
The array of descriptors is called as descr iptor table
Upper 13bits of selector field points to a particular entry in the descriptor table
Descr iptor Table Types
Local Descriptor Table (LDT)
Global
Interr upt Descriptor Table (IDT)
Descriptor Table (GDT)
Local and Global Descr iptor Table
A Global Descriptor Ta ble (GDT) contains global descriptors common common for all the tasks
A Local Descriptor Ta ble (LDT) contains descriptor specific specific to a partic ular task
All the tasks may have their private LDTs
A segment cannot be accessed, if its descriptor does not exist in either LDT or GDT.
LGDT (Load Global Descriptor Table) and LLDT (Load Local Descriptor Ta ble) Instr uctions are used to load the base and limit fields of GDT and LDT
Interrupt Descr iptor Table
IDT is used to store interr upt gates and trap gates
LIDT instr uction is used to Load Interr upt Descriptor table.
Pr ivilege
PRIVILEGE
Supports four level hierarchical privilege mechanism to control the access to descriptors and hence to the corresponding segments of the task .
Level 0 is the highest privilege level
Level 3 is the lowest privilege level .
Pr ivilege Types
Task Privilege
Descriptor Privilege
Selector Privilege
Task Pr ivilege
Each
task assigned a privilege level, which indicate the priority or privilege of that task
Any one of the fo ur privilege level may used to execute a task
The task privilege level at that instant is called the current privilege level (CPL)
The CPL is defined by the lower order 2-bits of CS register for an exec utable segment.
Once
CPL is selected, it cannot be changed during the execution normally in a single code segment
It can only changed by transferring the control, using gate descriptors, to a new segment
A task executing at level 0, the most privileged level, can access all the data segment defined in GDT and LDT of the task
A task executing at level 3, the least privileged level, will have the most limited access to data and other descriptors
Descr iptor Pr ivilege
The descriptor privilege is specified by the DPL field of the access rights byte.
The DPL specifies the least privilege level that may be used to refer the descriptor .
Selector
Pr ivilege
This privilege is specified by the RPL field of the segment register (selector) A selector may use a less tr usted privilege than the current privilege level for f urther use.
This is called the effective privilege level (EPL) of the task .
RPL is used to ensure that the pointer parameter passed to a more privileged proced ure are not given the access of data at privilege higher than the caller routine.
Protection
Protection
The 80286 supports the following three basic mechanism to provide protection
1.
Restricted use of segments: The segment usages are restricted by classifying the corresponding descriptors under LDT and GDT.
2.
Restricted access to Segment: This is accomplished using descriptor usages limitations and the r ules of privilege check, ie DPL,CPL
Protection . Privileged Instr uctions or Operations:
3
These are to be executed or carried o ut at certain privilege levels determined by CPL and I/O privilege level (IOPL) as defined by flag register .
80287
Math Coprocessor
Numeric data coprocessor specially designed to operate with 80286
80287
80287
adds nearly 70 more instr uctions to the instr uction set of 80286 offers an instr uction set that supports integer, floating point, BCD, trigonometric and logarithmic calculations
Q uestions?
