SECOND ORDER EFFECTS IN MOSFETS
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Contents Channel
Length Modulation / Velocity Saturation
Threshold Thresho ld Vt
Voltage
Variation:
SCE / RSCE NCE / RNCE Body bias Leakage current mechanisms in MS!ETs "N #unction re$erse bias leakage Subthreshold leakage %ate o&ide tunneling 'n#ection o( hot carrier )rain 'nduced barrier Lo*ering+)'BL, %ate induced drain leakage+%')L, "unchthrough
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Contents Channel
Length Modulation / Velocity Saturation
Threshold Thresho ld Vt
Voltage
Variation:
SCE / RSCE NCE / RNCE Body bias Leakage current mechanisms in MS!ETs "N #unction re$erse bias leakage Subthreshold leakage %ate o&ide tunneling 'n#ection o( hot carrier )rain 'nduced barrier Lo*ering+)'BL, %ate induced drain leakage+%')L, "unchthrough
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Channel Length Modulation -ctual
Length o( channel decreases decreases *ith increase in V . DS Result in non ero I D / V DS
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Channel Length Modulation The
resultant e&0ression (or I D is I D = K
4here5
*e ha$e
= Thus
W V GS−V T 6 2 V DS 123 L
L L
the modulation 0arameter has higher $alue (or short channels.
E((ect
mirror
o( channel length modulation can be obser$ed as in the sim0le current VDD ID1
M2 M1
VGS
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26 V GS = 2 6 V DS2 I D1 I D2
ID2 VDS2
R OUT =
2
I D2 4
Velocity Saturation higher V DS $elocity o( charge carrier saturates. The results in linear de0endence o( the drain current on V − V GS T The $alue o( transconductance+g , becomes constant m -t
Thus
the Value o( V)S-T7 V%S8 VT
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Threshold Voltage Threshold
Voltage:
The $alue o( gate to source $oltage re9uired to cause sur(ace in$ersion (or channel (ormation is called threshold $oltage.
Com0onents
o( Threshold Voltage:
The *ork (unction di((erence b/* gate and channel + ɸMS,
The com0onent o( gate $oltage to change the sur(ace 0otential +6 ɸF,
%ate $oltage com0onent to o((set the de0letion region charge + B,.
The $oltage com0onent to o((set the (i&ed charges in the gate o&ide and in silicon o&ide +o&, V th= MS 6 F − Sankalp Semiconductor Confidential
QB C OX
−
Q OX C OX !
Threshold Voltage
#%,&
#t$#%$&'Depletion(
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Vt variation in an MOS There
are $arious trends seen in threshold $oltage $ariation *ith scaling o( MS transistors. Various secondary e((ects leading to Vt $ariation in MS!ETs can be: Body Bias Short Channel e((ect+SCE, )'BL Re$erse short channel e((ect+RSCE, Narro* channel e((ect+NCE, Re$erse narro* channel e((ect+RNCE, VDD ID2
ID1
M2 M1
I D2
VDS
I D1
6
=
V GS−V T1
V GS−V T2 6
VGS
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Body bias Body
bias or back gate e((ect is the name gi$en to the change in threshold $oltage *ith change in the $oltage Vsb. !or a NMS *e ha$e.
4here5 VTN is the threshold $oltage *ith substrate bias. VT is threshold $oltage *ith substrate bias ero. ; is the body e((ect 0arameter. 6< is the sur(ace 0otential 0arameter.
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Short channel effect (SCE) 't
is 0henomenon in scaled transistors *hereby threshold $oltage o( a de$ice reduces *ith decrease in L. This de0endence o( Vt on length o( the de$ice is because o( the 0rotrusion o( source and drain regions. "art o( the channel is already de0leted because o( source and drain #unction de0letion.
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Drain nduced Barrier Lo!ering
)'BL is the 0henomena *hich results in reduced threshold $oltage and hence higher subthreshold current.
The reduction in threshold is due to the band bending caused by )rain to source $oltage.
=
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"everse short channel effect To
reduce short channel e((ects5 de0letion region *idths need to be reduced. !or this channels are highly do0ed near the source and drain terminals +halo do0ing,. 'n short channels halo do0ing o( source and drain o$erla0s. Threshold $oltage is high as channel do0ing is higher.
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#arro! channel effect Narro*
channel e((ect is 0henomenon by $irtue o( *hich5 Vt increases as channel *idth is reduced. NCE is more 0rominent in LCS. 'n LCS gate MS!ET5 e&istence o( (ringing (ield causes the gate induced de0letion region to s0read5 thus higher Vt.
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"everse #arro! channel effect "rominent
in Shallo* trench isolation+ST', MS!ETS. )e0letion layer cannot s0read under the isolation o&ide. So5 no increase in Vt. 68) (ield induced edge (ringing e((ect at the gate edge makes (ormation o( in$ersion layer at the edges becomes easier. Vt thus reduces
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Lea$age %echanis%s Leakage
Currents result in higher 0o*er consum0tion Various Leakage current mechanisms in MS!ETs are: "N #unction re$erse bias leakage Subthreshold leakage %ate o&ide tunneling 'n#ection o( hot carrier %ate induced drain leakage+%')L, "unchthrough
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'unction reverse bias lea$age )rain
and source di((usion regions (orm a re$ersed biased diode *ith substrate. Re$erse biased current has t*o com0onent: Minority carrier di((usion near the edge o( the de0letion region. Electron8hole 0air generation in the de0letion region. '( both " and N side are hea$ily do0ed the BTBT tunneling dominates the 0n #unction leakage.
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!ig: BTBT tunneling 1!
Subthreshold Lea$age Subthreshold
or *eak in$ersion conduction current is a mechanism o( current leakage in subthreshold gate bias region. 'n *eak in$ersion region minority carrier concentration is not ero. Subthreshold leakage current $aries e&0onentially *ith Vgs. The subthreshold current is due to di((usion.
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ate Oide Tunneling 4ith
scaling o&ide thickness is also reduced. The high electric (ield cou0led *ith lo* o&ide thickness results in tunneling o( electrons (rom substrate to gate. There may be t*o ty0es o( tunneling 0ossible: !o*ler?Nordheim +!N, tunneling )irect tunneling.
!ig: !N tunneling Sankalp Semiconductor Confidential
!ig:)irect Tunneling 1-
n'ection of *ot Carriers 'n
short channel transistors electric (ield is $ery high. Electrons or holes can gain su((icient energy (rom the electric (ield to cross the inter(ace 0otential barrier and enter into the o&ide layer The in#ection (rom Si to Si is more likely (or electrons than holes.
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ate nduced Drain Lea$age Seen
*hen gate is biased (or accumulation in the substrate. )ue to accumulation5 de0letion layer at the sur(ace to be much narro*er than else*here. 4hen the negati$e gate bias is large5 the n@ drain region under the gate can be de0leted or e$en in$erted This causes more cro*ding and hence e((ects like a$alanche multi0lication and BTBT. Thinner %ate5>igher V))5 Moderately do0ed )rain has more %')L.
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&unchthrough 'n
Short channel de$ices the source and drain de0letion regions e&tend into the channel. 'ncrease in re$erse bias also 0ushes the de0letion regions closer. "unchthrough occurs *hen both the de0letion regions touch each other. E$en i( the channel is hea$ily do0ed5 0unchthrough may occur belo* it. )ue to 0unchthrough subthreshold current increases
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Lea$age reduction techni+ues
!ig:-s0ects o( *ell engineering (or leakage reduction
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Lea$age reduction techni+ues Constant
,ield Scaling Reduce $oltages and dimensions by same (actor A+2, . Constant (ield assures higher reliability. "etrograde -ell Channels ha$e nonuni(orm $ertical do0ing 0ro(ile. Lo*er sur(ace concentration5(or higher sur(ace mobility. >ighly do0ed subsur(ace to a$oid 0unchthrough. *alo do.ing/ Non ni(orm channel do0ing in lateral direction. Substrate is highly do0ed at source and drain #unctions. Reduces de0letion *idth in the drain8substrate and source8substrate regions. Reduces )'BL5"unchthrough Enhances BTBT and %')L.
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Lea$age reduction techni+ues Constant
,ield Scaling )rain e&tended by adding a dri(t region *ith similar do0ing bet*een drain and the intended channel. Tra0s the ma#ority o( the lateral electric (ield5limiting the hot carrier e((ect to this region5instead o( the channel. This im0ro$es the V DS breakdo*n $oltage. 'ncreases the channel resistance.
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"eferences 123 Sung8Mo Aang5 Dusu( Leblebici5 Cmos )igital Circuits.Reading5Tata Mcgra* >ills5 6F5 ch. F5 00. 2G?2H.
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'ntegrated
2
T/ank 0ou
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2!
C5 S6IDES
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EB diagra% V 0 1 -ssum0tions:
"8ty0e Substrate. ϕMIϕSi +4ork (unction o( metal J Semiconductor are Same, No Tra00ed Charges in &ide.
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EB diagra% V21 -ccumulation:
E! Kgoes up in the metal .
-n electric (ield is obser$ed in the o&ide Concentration o( holes increases at the sur(ace.
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Eb diagra% V31 )e0letion:
E! o( the metal Kgoes dow
Because o( 0ositi$e $oltage at gate5 e9ui$alent negati$e charge is obser$ed at o&ide8semiconductor inter(ace. Negati$e charge is due to the de0letion o( holes.
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EB diagra% V331 'n$ersion5Strong
'n$ersion: E! o( the metal K goes !u"the" dow Number o( electrons at sur(ace e&ceeds the number o( holes at sur(ace+'n$ersion, Concentration o( electrons at sur(ace e9uals concentration o( holes in substrate+Strong in$ersion, Condition (or strong in$ersion ϕSI6ϕ!.Semiconductor is n8ty0e at the sur(ace
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Beyond strong inversion 4hen
*e (urther increase $oltage at the gate: Electrons at sur(ace mo$e into conduction band. Results in the (ormation o( a conducting channel
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Threshold Voltage e.ression
V th= 6 F − Sankalp Semiconductor Confidential
QB C OX 33
EB for ϕMS≠1 and 4O5≠1 4hen
*e (urther increase $oltage at the gate: Sur(ace may get in$erted *ith V %I To achie$e !lat band condition e9ui$alent $oltage is to be a00lied at gate This is kno*n as the !lat band $oltage
V th= MS 6 F −
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QB C OX
−
Q OX C OX
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D"6# e5TE#DED MOS (DEMOS)
ESD 6&&LC6TO# &"OBLEMS
At lower technologies say in 180nm (gate oxide thickness !nm" the #oltage re$%irement is still the same as in higher technologies& 'laming is not allowed to ower s%ly so as to re#ent the )ail*sa)e ro+lem&
(DE#MOS)
T*E SOL7TO# (DEMOS)
A
drain is created within a well o) same tye doant +%t the density is )ar less& ,he increase in the drain*s%+strate -%nction area and the red%ced n%m+er o) doants o) drain allow increment in the -%nction +reakdown #oltage& ,his ermits high #oltage oerations on the mos and re#ents the drain )rom #oltage exc%rsions in a+sence o) a clam&
T*E SOL7TO# Contd8
A
great ad#antage with D.M/S is that they allow )a+rication o) #ery thin gate oxide& As there is a less doed well s%rro%nding the act%al drain hence the act%al seen #oltage at the drain decreases and so does the electric )ield& ,his red%ces the creation o) hot carriers which a))ects the gate oxide thickness& ence mos with lesser Vth can +e easily )a+ricated&