CONFERENCE PROGRAM & EXHIBIT GUIDE WWW.DAC.COM
JUNE 1 - 5, 2014 MOSCONE CENTER SAN FRANCISCO, CA
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Upgradee Your Design & Verificat Upgrad erification ion with
There’s formal . . . and then there’s . . . Formal
JASPER Formal
Learn how
can help you at: Booth #2033 FORMAL
www.jasper-da.com
Jasper Design Automation | 707 California Street | Mountain View, CA 94041 | 1.650.966.0200
GENERAL CHAIR WELCOME Welcome to the new DAC, better than t han ever! Dear Colleagues,
It is a great pleasure to welcome you all to the 51 st Design Automation Conference, here in beautiful San Francisco. With fifty Design Automation Conferences behind us, the 51 st DAC brings recent design automation technological advances to the exhibit floor, cutting-edge research and industry presentations, timely education and training sessions, and great networking opportunities. Our industry is more vibrant than ever before. As reported by the EDA Consortium, 2013 was a record year with $6.9 billion in revenue, reflecting 16 consecutive quarters of positive growth in the EDA industry while employing almost 30,000 professionals. I am delighted that you will have a first-hand experience interacting with other professionals and viewing state-of-the-art tools and solutions on the exhibit floor. The 51st DAC features a lively exhibition showcasing over 200 companies, including the largest EDA vendors, IP providers, ESS suppliers and significant foundries in today’s industry. The exhibition will serve as a convenient one-stop-shop for all elements of the design ecosystem. To capitalize on this momentum and further advance the various industry directions, DAC has been been re-organized. DAC now offers six vertical tracks. The Electronic Design Automation (EDA) track provides familiar offerings such as SoC design, low power techniques, physical design and manufacturability, 3-D integration, integrity and reliability analysis, synthesis and verification, and design with emerging technologies. The Embedded Systems and Software (ESS) track continues to focus on tools and methodologies to support specification, analysis, optimization and verification of embedded software, middleware and OS, embedded architectures and platforms, I/O management for embedded devices, and embedded memory design. Automotive otive track is a new, unique forum addressing design automation tools and methodologies to enable automotive The Autom electronics designers and integrators to meet unprecedented challenges and demands. The Security track highlights the emergence of security and trust as important dimensions of hardware and embedded systems design, dimensions that must be considered side-by-side with power, performance, and reliability. The Intellectual Property (IP) (IP) track provides IP creators and users an open forum to exchange information on products, tools and methodologies to create, incorporate and validate IP IP.. With the Design track, we continue with our efforts from prior years years to showcase design experiences. The Designer and IP tracks are held on the exhibition exhi bition floor. For each track, the technical program is jam packed with outstanding keynotes, submitted research presentations, tutorials, panels, and invited special sessions. This year, the Technical Technical Program Committee accepted 22% of 782 submitted manuscripts. We continue with the Short KeYnotes (SKY talks) and the Work-In-Progress (WIP) poster session. We also bring short Visionary Talks, delivered by prominent executives from our community, which will be held during the same plenary sessions as the keynotes. The submitted presentations are short, 15-minute slots with a poster session afterwards for in-depth, face-to-face discussions. On Thursday, we offer high-quality training sessions with expert trainers from Doulos. The Management Day program on Monday allows managers and designers to hear experienced senior managers share challenges and expertise in management, economics and design optimization. All in all, DAC brings you 140 technical presentations. DAC includes 7 workshops presented on Sunday and Thursday. Thursday. We also have a record number of 11 different tutorials, repeated multiple times throughout the day on Monday. DAC brings six colocated conferences that complement the DAC program including ESLsyn, IWLS, SLIP, CELUG, IBIS Summit, and the CRAW/CDC Workshop on Diversity in Design Automation. I invite you to browse through the technical program to learn program details. I would like to recognize the enormous efforts of our dedicated volunteers, including the ones that served on the various DAC committees, who worked tirelessly to bring the 51 st DAC to life. Enjoy all what the 51 st DAC brings you – the exhibits, the technical presentations, the training sessions, and the networking opportunities.
Soha Hassoun
TABLE OF CONTENTS General Chair’s Welcome ....................................................................................................................... 3 Sponsors ................................................................................................................................................. 5 Important Information ............................................................................................................................ 6 Networking Receptions .......................................................................................................................... 7 Workshops.........................................................................................................................................8-13 Monday Morning Keynote.................................................................................................................... 15 Monday Afternoon Keynote ................................................................................................................. 16 IP Track ............................................................................................................................................17-18 Tutorials ...........................................................................................................................................19-22 Management Day ................................................................................................................................. 23 Tuesday Dual Keynote ......................................................................................................................... 24 Tuesday Sessions ............................................................................................................................25-37 Wednesday Keynote ............................................................................................................................ 38 Wednesday Sessions ......................................................................................................................39-51 Work-in-Progress (WIP) and Networking Reception .....................................................................52-57 Thursday Keynote ................................................................................................................................ 58 Thursday Sessions ..........................................................................................................................59-68 DAC Insights ......................................................................................................................................... 69 Thursday is Training Day .................................................................................................................70-71 Colocated Conferences ..................................................................................................................73-74 Additional Meetings ........................................................................................................................75-77 Pavilion Panels ................................................................................................................................81-84 Platinum, Gold & Silver Sponsors ........................................................................................................ 86 Exhibitor List ....................................................................................................................................88-89 Exclusive Sponsorships ....................................................................................................................... 90 Exhibiting Companies ...................................................................................................................92-104 Supplemental Listing.......................................................................................................................... 104 Committees & Organizers ...........................................................................................................108-113
CONFERENCE SPONSORS
ACM ACM, the Association for Computing Machinery, is the world’s largest educational and scientific computing society, uniting computing educators, researchers and professionals to inspire dialogue, share resources and address the field’s challenges. ACM strengthens the computing profession’s collective voice through strong leadership, promotion of the highest standards, and recognition of technical excellence. ACM supports the professional growth of its members by providing opportunities for life-long learning, career development, and professional networking, see: www.acm.org.
ACM/SIGDA The ACM Special Interest Group on Design Automation has a long history of supporting conferences and the EDA profession. In addition to sponsoring DAC, SIGDA sponsors ICCAD, DATE, and ASP-DAC, plus approximately 15 smaller symposia and workshops. SIGDA provides a broad array of additional resources to our members, to students and professors, and to the EDA profession in general. SIGDA organizes the University Booth and Ph.D. Forum at DAC, and the CADathlon at ICCAD, and also funds various scholarships and awards. Other benefits provided to SIGDA members include the SIGDA’s E-Newsletter containing information on upcoming conferences and funding opportunities, SIGDA News highlighting most relevant events in EDA and semiconductor industry, and the “What is...?” column that brings to the attention of EDA professionals the most recent topics of interest in design automation. For further information on SIGDA’s programs and resources, see www.sigda.org.
IEEE/COUNCIL ON ELECTRONIC DESIGN AUTOMATION The IEEE is the world’s leading professional association for the advancement of technology, with 430,000 members across 160 countries. The IEEE Council on Electronic Design Automation (CEDA) provides a single focal point for all EDA activities across six major IEEE societies (Circuits & Systems, Computer, Electron Devices, Solid State Circuits, Antennas & Propagation, and Microwave Theory & Techniques). The Council sponsors or co-sponsors over a dozen key EDA conferences, including the Design Automation Conference (DAC), and the International Conference on Computer Aided Design (ICCAD), Design Automation and Test in Europe (DATE) and the Asia South Pacific Design Automation Conference (ASPDAC). The Council also publishes the IEEE Transactions on CAD, as well as the IEEE Embedded Systems Letters, and sponsors active technical committees like the DATC and CANDE. Since its founding, the Council has expanded its support of emerging areas within EDA such as nanoscale systems, sponsored new initiatives including the Distinguished Speaker Series and is increasing recognition of members of the EDA profession via awards such as the A. Richard Newton Award, Phil Kaufmann Award, and Early Career Award. The Council welcomes new volunteers and local chapters. For more information on CEDA, visit: www.ieee-ceda.org.
EDA CONSORTIUM The EDA Consortium (EDAC) is the international association of companies that provide tools and services enabling engineers to create the world’s electronic products. EDAC addresses issues that are common to its members and the community they serve. Recent accomplishments include simplification of international EDA export regulation, coordinating software anti-piracy efforts, a quarterly Market Statistics Service (MSS) report, and publication of an industry Operating Systems Roadmap. Companies that become EDAC members are eligible for a 10% discount on DAC Exhibit Booth and Suite Space. Contact the EDA Consortium today about sponsorship and membership opportunities. For more information on the EDA Consortium, visit: www.edac.org.
IMPORTANT INFORMATION EXHIBIT HOURS
STAY CONNECTED
LOCATION: SOUTH HALL HOURS: Monday, June 2 Tuesday, June 3 Wednesday, June 4
WIRELESS INTERNET 9:00am - 6:00pm 9:00am - 6:00pm 9:00am - 6:00pm
“BIRDS-OF-A-FEATHER” MEETINGS
REGISTRATION HOURS LOCATION: SOUTH LOBBY HOURS: Thursday, May 29 - Sunday, June 1 Monday, June 2 - Thursday, June 5
Moscone Center offers complimentary wireless internet throughout the facility.
8:00am – 6:00pm 7:00am – 6:00pm
Sponsored By:
DAC will provide conference rooms for informal groups to discuss items of common technical interest. These very informal, non-commercial meetings, held after hours, are referred to as “Birds-of-a-Feather” (BOF). All BOF meetings are held at the Moscone Center, Tuesday, June 3 from 7:00 - 8:30pm. To arrange a BOF meeting, please contact
[email protected]. An LCD projector and screen will be provided.
ONLINE PROCEEDINGS
FIRST AID ROOM
DAC Proceedings and tutorials will be delivered electronically online via a username and password.
First Aid Room is located across from Room 106.
To access: http://proceedings.dac.com Username = Email address Password = Registration ID (on your badge)
A nurse will be on duty at all times while meetings and exhibits are open.
Please refer to your registration receipt to be reminded of what package and associated les you are eligible to view.
DAC MOBILE APP
Non-emergency: 415-974-4092 Emergency: 511 Help may be reached 24 hours a day from any house phone within the Moscone Center at extension 511.
DAC BUSSING Again this year, DAC is providing bus transportation from San Jose to the South Lobby of the Moscone Center. The buses will run Monday, June 2 - Wednesday, June 4. Parking at the bus pick-up locations will be free. Pick-up and departure times are listed below. SEMI 3081 Zanker Road San Jose, CA 95113
INFORMATION DESK The Information Desk is located in the South Lobby of the Moscone Center.
i
Pick-up times from San Jose to the Moscone Center (APPROXIMATELY 1 HOUR RIDE):
7:45am, 8:30am, 9:00am
Departure times from the Moscone center to San Jose: 5:00pm, 6:30pm, 7:00pm
JOIN YOUR FRIENDS & COLLEAGUES DAC Networking Opportunities! WELCOME RECEPTION
Auto Village Reception
SUNDAY, JUNE 1 INTERCONTINENTAL HOTEL 5:30 - 7:00pm
Hosted By:
MONDAY, JUNE 2 BOOTH 603 5:00 - 6:00pm
MONDAY, JUNE 2
TUESDAY, JUNE 3
ESPLANADE FOYER 6:00 - 7:00pm
ESPLANADE FOYER 6:00 - 7:00pm Sponsored By:
Sponsored By:
Book Signing! Daniel Nenni Semiwiki.com
R
THE DESIGN VERIFICATION COMPANY
WEDNESDAY, JUNE 4 ESPLANADE FOYER 6:00 - 7:00pm
Paul McLellan Semiwiki.com
THURSDAY, JUNE 5 ESPLANADE FOYER 5:00 - 6:30pm
SUNDAY, JUNE 1 SUN
SPECIAL REGISTRATION REQUIRED.
1 - DAC WORKSHOP ON MULTI-PROCESSOR PLATFORMS FOR LOW POWER REAL-TIME EMBEDDED APPLICATIONS Room: 309
Time: 1:00 - 5:00pm
Organizers: Luciano Lavagno - Politecnico di Torino, IT Albert Cohen - Ecole Normale Superieure, Paris, FR
In the last few years, multiprocessors have penetrated the embedded market. Several platform providers (e.g. Qualcomm, NVidia, TI, STM, to name but a few) now propose multicore architectures with scalable performance. These architectures are able to cope with the rising processing needs, while keeping power consumption under control. They provide developers with a lot of exibility and offer efcient power monitoring and control features. However these evolutions help sustain the electronic system market growth at the expense of software development cost. This is because concurrent programming is inherently more difcult than sequential programming, and it is less widely taught n universities.
Track: Embedded Systems
Embedded System Design
This workshop is organized by the FP7 PHARAON project consortium. The project, which is co-funded by the European Commission, is aimed at reducing mapping complexity, increasing performance and reducing power consumption for multi-core platforms. It will cover the following topics: Multi-Processor platforms as innovation drivers for security and safetyapplications: What are the technical requirements to be solved Deploying Multiprocessor Technologies in Mainstream Development Cycles: Design Challenges and Opportunities for Automotive OEMs Modeling and Mapping Medical Imaging Applications to Heterogeneous Hardware
Building, programming, and validating low-power It is widely reported that the cost of developing the support software libraries heterogeneous multi-core image processors that need to be shipped with a new hardware platform is approaching and may soon exceed the hardware design costs. A signicant portion of Advanced semiconductor technologies enabling high this cost is due to the above-mentioned difculty of concurrent multicore performance energy efcient MPSoCs programming. Hardware architectures evolve faster than software tools, and the specication and mapping of applications onto new multicore Software driven power management analysis with virtual platforms architectures, especially heterogeneous ones, becomes more complex. Energy efciency of exible precision-timed processors. Managing voltage and frequency in the presence of rapidly varying computational loads and real-time deadlines can be overwhelming. It can lead to under-exploiting the power saving opportunities, and even to Speakers: resounding battery life problems. Bernard Candaele - Thales, Gennevilliers, FR Paolo Giusto - General Motors Company, Palo Alto, CA In summary, the lack of efcient concurrent software development tools and of platform abstraction middleware hinders adoption of new Ahmed Jerraya - Univ. Grenoble Alpes, CEA, LETI, architectures and increases software development costs. The electronic MINATEC Campus, Grenoble, France industry therefore has to face a new challenge by introducing efcient Menno Lindwer - Intel Corp., Eindhoven, NL Louis-Noel Pouchet - Univ. of California, Los Angel es, CA tools capable to assist designers in these tasks. The main objective of Yosinori Watanabe - Cadence Design Systems, Inc., San Jose, CA this workshop is to bring together key players from both industry and Michael Zimmer - Univ. of Califor nia, Berkeley, CA academia, to discuss the challenges and outline possible solutions, while verifying their applicability to real systems.
SPECIAL REGISTRATION REQUIRED.
SUNDAY, JUNE 1
2 - DAC WORKSHOP ON COMPUTING IN HETEROGENEOUS, AUTONOMOUS ‘N’ GOAL-ORIENTED ENVIRONMENTS Room: 304
Time: 9:00am - 5:30pm
Organizer: Marco D. Santambrogio - Politecnico di Milano, IT
As the push for parallelism continues to increase the number of cores on a chip, system design has become incredibly complex; optimizing for performance and power efciency is now nearly impossible for the application programmer. To assist the programmer, a variety of techniques for optimizing performance and power at runtime have been developed, but many employ the use of speculative threads or performance counters. These approaches result in stolen cycles, or the use of an extra core, and such expensive penalties can greatly reduce the potential gains. Within this context imagine a revolutionary computing system that can observe its own execution and optimize its behavior around a user’s or application’s needs. Imagine a programming capability by which users can specify their desired goals rather than how to perform a task, along with constraints in terms of an energy budget, a time constraint, or simply a preference for an approximate answer over an exact answer. Imagine further a computing system that performs better according to a user’s preferred goal the longer it runs an application. Such an architecture will enable, for example, a handheld radio or a cell phone that can run cooler the longer the connection time. Or, a system that can perform reliably and continuously in a range of environments by tolerating hard and transient failures through self healing.
Track: Embedded Systems
SUN
Emerging Technologies
Self-aware computer systems are the key technology to succeed in doing this. They will be able to congure, heal, optimize, improve interaction and protect themselves without the need for human intervention, exploiting abilities that allow them to automatically nd the best way to accomplish a given goal with the resources at hand. Within this context, imagine a revolutionary computing system that can observe its own execution and optimize its behavior around the external environment, user’s and application’s needs. The Self-Aware computing research leverages the new balance of resources to improve performance, utilization, reliability and programmability. Within this context, the proposed workshop is intended to present innovative works describing: - Self-aware Operating Systems - Autonomous self-aware computer architecture - Adaptive algorithm and distributed self-training algorithms - Biologically inspired systems Speakers: Ayse K. Coskun - Boston Univ., Boston, MA Simone Campanoni - Harvard Univ., Cambridge, MA John Kubiatowicz - Univ. of California, Berkeley, CA Hank Hoffman - Univ. of Chicago, IL Alessandro Nacci - Politecnico di Milano, IT
SUNDAY, JUNE 1 SUN
SPECIAL REGISTRATION REQUIRED.
3 - RACES: DAC WORKSHOP ON RECONFIGURABLE COMPUTING FOR EMBEDDED SYSTEMS Room: 307
Time: 8:00am - 4:00pm
Organizer: Christian Pilato - Columbia Univ., New York, NY Extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the c ustomer’s needs and market and technology trends. While adaptability of soft ware components is straightforward, products include hardware accelerators –for reasons of performance and power efciency- that also need to adapt to the new requirements. Hardware solutions can achieve high performance, and software solutions can easily adapt to the new set of threats, but neither can achieve exibility and high performance at the same time. Recongurable logic allows the denition of new functions to be dened in hardware units, combining hardware speed and efciency, with ability to adapt and cope in a cost effective way with expanding functionality, changing environmental requirements, improvements in system features, changing protocols and data-coding standards, etc. However, designing, implementing and verifying recongurable hardware systems is harder compared to static ones.
This workshop aims at bringing together experts to discuss current technologies and trends in the recongurable computing area. This workshop tends to focus on different topics/objectives of the design of computing systems: 1. To include recongurability as an explicit design concept: Current tools seem to lack a framework for system design where run-time adaptability, provided by dynamic hardware reconguration, becomes pivotal to computing system design. In this workshop we present cutting-edge research aiming at developing techniques and tools that analyze the structure and performance of the application, map it according to the capabilities of the underlying implementation platform, and provide a dynamically recongurable system implementation. 2. To effectively analyze and verify such recongurable systems: In order to guarantee that the nal implementation corresponds to the application requirements and system specications, we must have automated
Track: Embedded Systems
Synthesis/FPGAs
analysis, synthesis and verication algorithms. To validate the dynamic aspects of reconguration behavior, we will explore/present different design validation approaches such as simulation, hardware emulation and formal verication 3. To provide efcient and developer/user transparent runtime support for partial and dynamic reconguration: Assuming a partially recongurable system – either with a single or multiple FPGAs – we have to develop a runtime system that can efciently handle the online scheduling and placement of recongurable system components, using dynamically adaptive schemes to optimize the system operation based on different functional and non-functional requirements dened by the user or the earlier tool-chain.
To support the above, the architecture has to expose some light-weight system monitors and control hooks to the runtime system. This will be one of the research challenges that will be investigated by our speakers during the workshop. DAC has always been on the leading edge of new technologies working towards presenting breaking through research. In line with this observation this workshop will bring together researchers and industry for a wide ranging discussion on how recongurable computing has been around for a while and nally, nowadays, can be considered a mature technology to be effectively used. Speakers: Michael Flynn - Stanford Univ., Stanford, CA Georgi Gaydadjiev - Chalmers Univ. of Technology, Gothenburg, SE Wayne Luk - Imperial College London, GB Dionisios Pnevmatikatos FORTH Institute of Computer Science, Heraklion, GR Dirk D. Stroobandt - Ghent Univ., Ghent, BE
SPECIAL REGISTRATION REQUIRED.
SUNDAY, JUNE 1
4 - DAC WORKSHOP ON ALTERNATIVE COMPUTING IN THE NANOSCALE ERA Room: 305
Time: 8:00am - 6:00pm
Track: EDA
General Interest
SUN
Organizers: Noel Menezes - Intel Corp., Portland, OR Rasit O. Topaloglu - IBM Corp., Hopewell Junction, NY Naveen Verma - Princeton Univ., Princeton, NJ
however broader benets are also possible. In brain-inspired computing, as an example, while substantial background including the decades of research in neural networks exists, recent advancements focus on general-purpose computing and emerging machine-learning methods.
“Error is viewed, not as an extraneous and misdirected or misdirecting accident, but as an essential part of the process…. Our present treatment of error is unsatisfactory and ad hoc.” -J. von Neumann (1956).
While it is possible to study these computing models independent of technology or applications, designing new computing models in a way that is explicitly driven by these upcoming applications and emerging technologies would lead to more systematic advances. Further, it will also enable directed efforts on the technological and application levels that are inuenced by these computing models. With these goals, we are holding a DAC Workshop where researchers from alternative computing, system design, and novel technology research areas can attend, share their insights, and exchange ideas towards the common goal of improving system design in the nanoscale era.
Well before 1956, John von Neumann recognized and voiced repeatedly his conviction that handling errors is a critical aspect of computing. For over 50 years, the eld of computing has relied on powerful methods such as defect minimization, design margining, abstraction, redundancy, backtracking, and virtualization at the technology, circuits, architecture, and software levels to avoid errors and exploit the scaling enabled by Moore’s Law. However a drastic shift in the computing model may be due as traditional technology scaling itself poses risks to the continued advancement of computers; the memory gap is becoming more and more important, power is continuing to be a limiting factor, and variation- and reliability-induced errors in nanoscale technologies are getting more difcult to contain. Recent research has been looking into new computing models as a solution. These have particular relevance in the context of emerging applications, which are rapidly gaining prominence. Instead of focusing on exact computations from traditional input sources, more diverse inputs sources, often based on ensembles (of sensors, users, other computers), are enabling probabilistic or approximate models for computing towards high-level inferences. These models have several implications, such as reduced power or latency, particularly when they are considered in the context of emerging technologies. Generally speaking, such computing models have so far been shown to be applicable only in specic cases,
Speakers: Rodrigo Alvarez-Icaza - IBM Corp., San Jose, CA Kwabena Boahen - Stanford Univ., Stanford, CA Pradeep Dubey - Intel Corp., Hillsboro, OR Hadi Esmaeilzadeh - Georgia Institute of Technology, Atlanta, GA Sharad Malik - Princeton Univ., Princeton, NJ Vikash K. Mansinghka - Massachusetts Institute of Technology, Cambridge, MA Subhasish Mitra - Stanford Univ., Stanford, CA Michael Orshansky - Univ. of Texas at Austin, TX Jan Rabaey - Univ. of Californi a, Berkeley, CA Naresh Shanbhag - Univ. of Illinois at Urbana-Champaign, IL Ian Young - Intel Corp., Hillsboro, OR
SUNDAY, JUNE 1 SUN
SPECIAL REGISTRATION REQUIRED.
5 - SEAK: DAC WORKSHOP ON SUITE OF EMBEDDED APPLICATIONS AND KERNELS Room: 310
Time: 8:30am - 5:30pm
Track: Embedded Systems
Organizers: Joseph Cross - Defense Advanced Research Projects Agency, Arlington, VA Adolfy Hoisie - Pacific Northwest National Lab, Richland, WA Darren Kerbyson - Pacific Northwest National Lab, Richland, WA Antonino Tumeo - Pacific Northwest National Lab, Richland, WA
Evaluating, benchmarking and classifying embedded systems are challenging tasks. By denition, an embedded system is application specic. Furthermore, an embedded system is designed to t within certain constraints dictated by their target application areas. Aspects such as power consumption, real time awareness, reliability, accuracy of the computation, cost, device and physical size are all metrics under which an embedded system can be classied and that have a direct inuence on the overall system performance. All these contrasting metrics dene how well an embedded system can address its target application. An additional challenge derives from the fact that modern embedded systems are composed of a multitude of heterogeneous processing elements and components. They include general-purpose processors, digital signal processors, graphic processors, application specic accelerators, recongurable logic and more. These components can be either off-the-shelf or custom designed. Embedded systems often present disparate types of memory hierarchies. Also the software toolchain, which includes compilers, synthesizers and optimization tools, may have signicant impacts on the metrics. This workshop is related to a new DARPA initiative in this arena called SEAK (Suite of Embedded Applications and Kernels), whose goal is to dene a new, open suite of benchmarks, together with a novel methodology to evaluate in terms of performance and power end-to-end embedded systems for DOD’s application areas. The workshop aims to involve, from the very early stages of SEAK, the benchmarking, simulation and modeling community to devise novel systematic approaches to evaluate and classify embedded systems, with a particular focus on the power/performance tradeoffs. Its objective is to provide a forum for discussing methodologies and approaches to evaluate embedded systems, including appropriate metrics, benchmarks applications, microbenchmarks, power/performance instrumentation. Areas of particular interest for this assembly are research topics that identify and analyze novel ideas rather than providing incremental advances on the following themes: - Benchmark and micro-benchmark creation, analysis, and evaluation issues - Characterization of relevant workloads for embedded systems Modeling of application and system behavior
Embedded System Methodologies
- Tools for analyzing power and energy with different granularities and scope from hardware (e.g. component, core, system) or software views (e.g. threads, tasks, processes, etc) or both (end-to-end systems) - Denition, identication of metrics that determine the suitability of an embedded system for its target applications, and their collection methodologies
- Characterization of current state-of-the art embedded systems in terms of power and performance This full day workshop will involve invited talks, a session with selected posters and a closing panel. Invited talks include a keynote from DARPA, stakeholders of SEAK and teams responsible of other benchmarking initiatives. A session will introduce of a proposed methodology and benchmark suite from the SEAK team at PNNL. The workshop will host a session of rapid-re talks from embedded system vendors and design automation companies. Posters will be chosen through a peer-reviewed selection of short position papers from academia and industry on the topics of evaluation, characterization, benchmarking and modeling of embedded systems or their components for power and performance.
The panel will involve key people from the previous sections, ideally closing the day-long discussions. Speakers: Jeff Bier - Berkeley Design Technology, Inc., Berkeley, CA Sek Chai - SRI International, New York, NY Joseph Cross - Defense Advanced Research Projects Agency, Arlington, VA Adolfy Hoisie - Pacific Northwest National Lab, Richland, WA Darren Kerbyson - Pacific Northwest National Lab, Richland, WA Richard Lethin - Reservoir Labs, Inc., New York, NY Markus Levy - The Embedded Microprocessor Benchmark Consortium, El Dorado Hills, CA Albert Reuther - Massachusetts Institute of Technology, Lincoln Laboratory, Lexington, MA Jeffrey Smith - BAE Systems, Inc., Arlington, VA
SPECIAL REGISTRATION REQUIRED.
SUNDAY, JUNE 1
7 - IP WORKSHOP: DRIVING QUALITY TO THE DESKTOP OF THE DAC ENGINEER Room: 202
Time: 1:00 - 5:00pm
Organizer: McKenzie Mortensen - IPextreme, Campbell, CA This workshop will demonstrate a complete ow, using de facto industry standards, for designing, packaging, and integrating semiconductor IP, insuring that quality metrics are observed and preserved throughout the ow to the DAC engineer’s desktop. A variety of leading companies will be part of the workshop, each presenting how their individual products work together in a cohesive fashion for the benet of the SoC designer.
Track: IP
Designer/IP Track
The IP Workshop will realistically showcase how engineers from different companies use their proprietary tools and technology to work together. The result of this collaboration is the creation of high quality, rst-timecorrect products. Because the ow delves into a number of areas in the design and use of semiconductor IP, the workshop’s appeal and relevance is wide. There will be ample time provided for open discussion throughout the workshop—audience members are encouraged to ask questions and share their thoughts and impressions at each stage of the ow. The workshop will conclude with a roundtable session with the presenters.
The companies and their contributions to the workshop are as follows: TSMC will discuss the TSMC 9000™ quality standards and explain how they are benecial for both IP providers and IP consumers.
Atrenta will demonstrate the use of SpyGlass® and its IP Kit™ for the analysis of IP against a set of standard quality metrics. Sonics will demonstrate the creation of congurable IP and the manner in which it is validated and checked against quality metrics using the TSMC Soft IP Kit 2.0 ow.
IPextreme will demonstrate the use of Xena™ for storing and managing completed IP products and will also showcase how users can congure IP on-the-y and re-verify the quality metrics produced from SpyGlass® in the Cloud.
SUN
Speakers: Robert Beanland - Atrenta Inc., San Jose, CA Steve Chen Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW Michael Cizi - IPextreme, Munich, DE Lluis Paris Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA Amit Goldie - Atrenta Inc., Noida, India Warren Savage - IPextreme, Campbell, CA Ivan Svestka - Sonics, Inc., Milpitas, CA
