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Pipelining and Parallel Processing Shao-Yi Chien
Introduction
Pipelining and parallel are the most important design techniques in VLSI DSP systems
Make use of the inherent parallel property of DSP algorithms
Pipelining: different function units working in parallel
Parallel: duplicated function units working in parallel
DSP in VLSI Design
Shao-Yi Chien
An Example: Car Production Line Cost: 1 Throughput: 1/mT Latency: mT
mT m T T mT mT
Cost: >1 Throughput: 1/T Latency: >mT
T
n
Cost: >n Throughput: (1/mT)*n Latency: >mT
mT DSP in VLSI Design
Shao-Yi Chien
Throughput: how many cars produced in one hour Latency : how long will it take to produce one car
Pipelining of Digital Filters (1/3)
FIR filter
Critical path: TM+2T A
DSP in VLSI Design
Shao-Yi Chien
Pipelining of Digital Filters (2/3)
Pipelined FIR filter
T sample DSP in VLSI Design
≥ T M + T A
f sample Shao-Yi Chien
≤
1
T M + T A
Pipelining of Digital Filters (3/3)
Schedule
DSP in VLSI Design
Shao-Yi Chien
Pipeline
Can reduce the critical path to increase the working frequency and sample rate
TM+2T ATM+T A
DSP in VLSI Design
Shao-Yi Chien
Drawbacks of Pipelining
Increasing latency (in cycle)
For M-level pipelined system, the number of delay elements in any path from input to output is (M-1) greater than the origin one
Increase the number of latches (registers)
DSP in VLSI Design
Shao-Yi Chien
How to Do Pipelining?
Put pipelining latches across any feed-forward cuts cutset et of the the grap graph h Cutset A cutset is a set of edges of a graph such that if these edges are removed from the graph, the graph becomes disjoint
Feed-forward cutset
The data move in the forward direction on all the edges of the cutset
DSP in VLSI Design
Shao-Yi Chien
How to Do Pipelining? Feed-forward cutset
DSP in VLSI Design
Shao-Yi Chien
Example
In the SFG in Fig. (a), all the computation time for each node is 1 u.t. (a) Calculate the critical path (b) The critical path is reduced to 2 u.t. by inserting 3 extra delay elements. Is it a valid pipelining?
DSP in VLSI Design
Shao-Yi Chien
Answer
(a) The critical path is A3 A5 A4 A6, 4 u.t.
(b) No, it is not a valid pipelining. Fig. (c) is the corrected one
DSP in VLSI Design
Shao-Yi Chien
Fine-Grain Pipelining
Critical path (TM=10, T A=2) TM+2T A=14 TM+T A=12 TM1=6 or TM2+T A=6
DSP in VLSI Design
Shao-Yi Chien
Notes for Pipelining (1/2)
Pipelining is a very simple design technique which can maintain the input output data configuration and sampling frequency Tclk=Tsample Supported in many EDA tools Still has some limitations Pipeline bubbles Has some problems for recursive system Introduces large hardware cost for 2-D or 3-D data Communication bound
DSP in VLSI Design
Shao-Yi Chien
Notes for Pipelining (2/2)
Effective pipelining
Put pipelining registers on the critical path
Balance pipelining
10(2+8): critical path=8
10(5+5): critical path=5
DSP in VLSI Design
Shao-Yi Chien
Parallel of Digital Filters (1/5)
Single-input single-output (SISO) system
Multiple-input multiple-output (MIMO) system 3-Parallel System!
DSP in VLSI Design
Shao-Yi Chien
Parallel of Digital Filters (2/5)
Parallel processing, block processing
Block size (L): the number of data to be processed at the same time
Block delay (L-slow) A latch is equivalent to L clock cycles at the sample rate
DSP in VLSI Design
Shao-Yi Chien
Parallel of Digital Filters (3/5)
The critical path is the same
Tclk is not equal to Tsample
L-slow
DSP in VLSI Design
Shao-Yi Chien
Parallel of Digital Filters (4/5)
Whole system
DSP in VLSI Design
Shao-Yi Chien
Parallel of Digital Filters (5/5)
Serial-to-parallel converter
DSP in VLSI Design
Parallel-to-serial converter
Shao-Yi Chien
Parallel Processing v.s. Pipelining
Parallel processing is superior than pipelining processing for the I/O bottleneck (communication bounded)
Pipelining only can increase the clock rate
System clock rate = sample rate for pipelining system
Use parallel processing can further lower the required working frequency
DSP in VLSI Design
Shao-Yi Chien
Pipelining-Parallel Architecture
DSP in VLSI Design
Shao-Yi Chien
Notes for Parallel Processing
The input/output data access scheme should be carefully designed, it will cost a lot sometimes
Tclk>Tsample, f clk
Large hardware cost
Combine with pipelining processing
DSP in VLSI Design
Shao-Yi Chien
Low Power Issues Pipelining and parallel processing are also beneficial for low power design Propagation delay
Power consumption Assume the sampling frequency is the same
DSP in VLSI Design
Shao-Yi Chien
Pipelining for Low Power (1/2)
For M-level pipelining
Critical path is reduced to 1/M
The capacitance is also reduced to C charge/M
The supply voltage can be reduced to propagation delay remains unchanged
DSP in VLSI Design
Shao-Yi Chien
, and the
Pipelining for Low Power (2/2)
Power consumption:
How about the parameter
?
Solve this equation to get
DSP in VLSI Design
Shao-Yi Chien
Example
Parameters
TM=10 u.t. T A=2 u.t. Tm1=6 u.t. Tm2=4 u.t. CM=5C A Vt=0.6V Normal Vcc=5V
(a) New supply voltage? (b) Power saving percentage?
DSP in VLSI Design
Shao-Yi Chien
Answer (a) Origin system: Pipelined system: Invalid value, less than threshold voltage
(b)
DSP in VLSI Design
Shao-Yi Chien
Parallel Processing for Low Power (1/2)
For L-parallel system
Clock period: TseqLTseq
Ccharge remains unchanged
CtotolLCtotal
Have more time to charge the capacitance, the supply voltage can be lower
DSP in VLSI Design
Shao-Yi Chien
Parallel Processing for Low Power (2/2)
Power consumption
To derive the parameter
DSP in VLSI Design
Shao-Yi Chien
Example
Parameters
TM=8 u.t. T A=1 u.t. Tsample=9 u.t. CM=8C A Vt=0.45V Normal Vcc=3.3V
(a) New supply voltage? (b) Power saving percentage?
