Bu ildi Buil ding ng a Sys yste temV mVe eri rilo log g Uni niv v er sa sall Ve Ver i fi fic c ati tion on Com ompo pone nent nt wi with th th the e In c i s i v e Pl an -t o -Cl o s u r e Methodology Ses s i o n 2.12 David Lon Long, g, Joh John n Aynsley Ayn sley
Bu ildi Buil ding ng a Sys yste temV mVe eri rilo log g Uni niversa versall Ve Veri rifi fica cati tion on Com Compo pone nent nt CONTENTS
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Introduction
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The Verification Plan
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Assertions, Coverage and Constraints SystemVerilog Testbench Architecture
SystemVerilog for Verification •
SystemVerilog has verification features not found in VHDL or Verilog:
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Assertions and a temporal sequence language Functional coverage Constrained random test vectors Dynamic creation of transaction objects Extensible classes for verification components and transactions Features to avoid simulation races between test bench and DUT
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But can be a steep learning curve for RTL/HDL designers
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Some sort of framework for block-level test benches would help …
Incisive Plan-to-Closure Methodology •
URM (Universal Reuse Methodology) / “Design Team Verification”
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Module-Based with Classes URM
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SystemVerilog verification environment
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Classes for transaction objects
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Does not require expertise in OOP (polymorphism, virtual methods, etc)
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Guidelines to create reusable Universal Verification Components (UVCs)
Our experience of actually getting this to work ...
System to be Verified • •
Bus-based sub-system with CPU CPU, Serial IO and arbiter are RTL SystemVerilog
module module rom rom Bus
module module sram sram module module cpu cpu
module module bus_arbiter bus_arbiter module module serial_io serial_io
UVC used with Verification Plan •
Identify key requirements and verification strategy for each requirement before starting to develop testbench!
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Assertion-Based Verification - uses SystemVerilog pr oper t y to continuously check design behaviour, e.g. interface protocol Fol ust Fol ll ow owii ng ng aa w wrr ii tt ee tt her her ee m m ust not not be be aa rr ead ead ff or or at at ll east east 1 1 cl cl ock ock cycl cycl e. e. The The one one
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w wrr ii tt ee cl cl ock ock
enabl enabl es es shoul shoul d d each each st st ay ay hi hi gh gh ff or or onl onl yy cycl cycl ee
Coverage-Driven Verification - uses SystemVerilog cover gr oup to record how many times a condition has been met For p For w war ard d and and backw backwar ar d d jj um um p oper oper at at ii ons ons ff or or ever ever yy st st ep ep ii n n tt he he rr ange ange 1 1 tt oo 15 15 shoul shoul d d be be exer exer ci ci sed. sed.
The Verification Process
Specification Specification
Verification Verification Plan Plan Management (prioritisation, resource utilisation) RTL RTL Design Design Features Features Assertions Assertions
Measure
Coverage Coverage Model Model
Tests Tests
Run
Verification Verification Environment Environment
From Features to Tests Features • •
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The The NBG NBG output output pin pin will will reflect reflect the the status of the status of the internal internal FAIL FAIL register register bit bit A A checksum checksum calculated calculated using using the CCITT-16 the CCITT-16 polynomial polynomial is is appended appended
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program program test1; test1; random_seed random_seed == ... ... verif_env(bus_if) verif_env(bus_if)
covergroup covergroup ... ... covergroup... covergroup... covergroup... covergroup... covergroup covergroup
cover cover ... ... cover ... cover ...
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Back-annotate coverage
Tests
Coverage Model
Tests inspired by features program program test2; test2; constraint constraint {{ ... ... }} verif_env(bus_if) verif_env(bus_if)
5: 5: ifif (en) (en) 5: 5: qq <= <= d; d; 0: 0: else else
Features grouped by specification, implementation, and functionality Many-to-many mapping between features and coverage points
URM Testbench Structure Top
Test program initial
Test definition Sequence task calls
env
Bus Slave UVC Bus Master UVC Master Agent Sequence driver
Config Protocol check Coverage collector Monitor
BFM interface
Environment contains multiple UVC modules Protocol-specific "Interface UVCs" built from 1 or more agents
Monitor BFM module
DUT interface
Interface encapsulates bus signals
Agent in SystemVerilog URM Same architecture as eRM
Master Agent Sequence driver
Config
Module containing "standard" tasks Class object
Protocol check Coverage collector
Monitor
BFM interface
Standardized task calls
Monitor BFM module
DUT interface
Task calls, events
Sequence Pushes Transactions module module ex_s ex_seq_dr eq_dr ii ver ver _m _m ( ex_bf m m_i _i ff bf bf m m_i _i ff ); ( ex_bf );
Sequence driver
ex_ bf m ex_bf m__tt rr ans_ ans_cc cur cur _t _ t rr ans; ans; Template for new transactions task si m mpl pl e e (( ... task si ... ); );
ex_bf ex_ bf m m_t _ t rr ans_ ans_cc t rr ans; ans; BFM interface
trans trans = = new new cur_trans; cur_trans; assert(trans.randomize()); assert(trans.randomize());
BFM module
bf bf m m_i _i ff .. put put (( trans trans ); ); endtask Independent endtask :: si si m mpl pl e e Independent of BFM details task scenar ii o_x o_x (( ... task scenar ... ); );
DUT interface DUT
... ...
si si m mpl pl e e (( .. .. .. ));;
Sequence built from other sequences
Transaction Class class class ex_bf ex_ bf m m__tt rr ans_ ans_c; c; rand ex_bf bf m m_t _ t rr ans_ ans_ss t x; x; rand ex_
Transaction data struct
ex_bfm_trans_c ex_bfm_trans_c
tx
...
min_delay
1
max_delay
15
enable_ delay_ constraint
1
tx_delay_ range
int int m mii n_del n_ del ay; ay; int max_ ax_del del ay; ay; int m
Control
bit enabl e_del e_del ay_const ay_const rr ai ai nt nt ;; bit enabl constraint constraint tt x_ x_del del ay_ ay_rr ange ange {{ if enabl e_ e_del del ay_ ay_const const rr ai ai nt nt )) if ( (enabl
Constraint
tt x. inside{[m ]};; x. del del ay ay inside{[ mii n_del n_ del ay: ay: m max_del ax_del ay ay]} } }
...
function function new(); new();
m del ay mii n_ n_del ay = = 1; 1; ... ... endclass: ex_bf m m tt rr ans_ ans cc endclass: ex_bf
Constructor
Derived Transaction Class class t rr ans_c; der ii ved_t ved_t rr ans_ ans_cc extends ex_bf m m__t ans_ c; class der extends ex_bf constraint x_del del ay_odd ay_ odd {{ constraint tt x_ if if ( (enabl enabl e_del e_ del ay_ ay_const const rr ai ai nt nt ))
Additional constraint
tt x. x. del del ay ay[[0 0]] == 1; == 1; } } function function new(); new(); super.new(); super.new(); ... ... task si m mpl pl e e (( ... task si ... ); );
Calls base class constructor
Handle can point to derived class
ex_ ex_bf bf m m__tt rr ans_ ans_cc tt rr ans; ans; trans trans == new cur _t _t rr ans; ans; new cur assert( trans. randomize()) assert(trans. randomize());;
Shallow copy
The BFM Interface interface interface ex_bf ex_bf m m__ii f f ;;
ex_ t rr ans_ ex_bf bf m m__t ans_ss tt rr ans; ans; Sequence driver
Standardised access to any BFM copied from URM library task put task automatic automatic put ( c TT ); ex_bf m m__tt rr ans_ ans_c ( input input ex_bf );
BFM interface
endtask endtask task task automatic automatic get get ( ex_bf m m_t _ t rr ans_ ans_cc T ); ( output output ex_bf ); . .
BFM module
DUT interface DUT
. .
. .
endtask endtask task done task automatic automatic done ( c TT ); ( input input ex_bf ); ex_bf m m_t _ t rr ans_ ans_c . .
. .
. .
. .
. .
. .
endtask endtask
BFM Pulls Transactions module module ex_bf ex_bf m m_m _ m ((
Sequence driver
BFM interface
BFM module
ex_bf ex_bf m m_i _i ff bf bf m m_i _i ff ,, cl kk ,, input input wire wire DUT_ DUT_cl ... ... ); );
Interface DUT signals
ex_ bf m t rr ans_ ex_bf m__t ans_cc tt rr ans; ans; initial initial forever forever begin begin Blocking bf bf m m_i _i ff .. get get (( trans trans ); ); dr ); dr ii ve_t ve_t rr ansact ansact ii on on(( trans trans );
bf bf m m__ii f f ..done done(( trans trans ); ); end end DUT interface DUT
task dr ii ve_t ve_t rr ansact ansact ii on on task dr ( ex_bf m m_ tt rr ans_ ans cc TT ); ( input input ex_bf );
Monitor Detects Bus Activity module ex_bus_ bus_m mon_m on_m (( module ex_ input input wire wire DUT_cl DUT_cl kk ,,
... ... ); );
m __w wrr ii tt e: cover property property ( ( mem em e: cover @(posedge DUT_cl kk)) @(posedge DUT_cl first_match( first_match(
Monitor
bus_i bus_i ff .. w wrr ##1[1:$] ##1[1:$]
bus_ bus_ii ff .. w wack ack )) ) ) cover ...);; cover _m _ mem em_w _ wrr ((bus_i bus_i ff .. addr addr ,, ...) Called when sequence matches DUT interface DUT
property property af af tt er er __w we; e; @ (( posedge @ bus_ i ff .. cl cl k) k) disable posedge bus_i disable iff iff
(( bus_ bus_ii ff .. rr eset eset )) bus_i bus_i ff .. w we e |=> |=> (( ! b s_i f !b if
)
Functional Coverage • •
Coverage points do not reveal how conditions are met SystemVerilog cover gr oup can record sampled value occurrence in bi ns and cross-coverage between cover poi nt pairs to measure “Functional” coverage
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Performed by coverage collector module
Writing to Coverage Collector module ex_bus_m bus_ mon_m on_m (( module ex_ input input wire wire DUT_cl DUT_ cl kk ,,
... ... ); );
ex_ ();; ex_tt rr ans ans_f _f ii ff o o tt xx() Coverage Collector
Interface "channel"
ex_cov_col ));; ex_cov_col ll ect ect or or _m _m c1 c1((.. tt rr ans ans((tt xx)) Called when sequence matches
Monitor
function function void void cover (...); cover _m _ mem em_w _ wrr (...); m t rr ans_ mem em__t ans_tt tt dat dat a a;; ... ...
tt x. ); x. put put ((tdata tdata); DUT interface DUT
endfunction endfunction ... ...
Call interface method
The Coverage Collector module ex_cov_col ll ect ect or or _m _m (( module ex_cov_col ex_t ); ex_t rr ans_f ans_f ii ff o o tt rr ans ans);
addr addr _t _ t addr addr __cp; cp; m cp; .. .. .. mode_t ode_ t rr w w__cp; Coverage Collector
Monitor
Mirror registers
mem covergroup covergroup cov_ cov_m em__acc; acc; m coverpoint addr mon_ on_addr addr :: coverpoint addr __cp cp bins al ll [] 0::15 15]] }; bins al [] = = { { [ [0 }; ignore_bins ignore_bins bad bad == {{0, 0, 5, 5, 8 8}};;
{ { } }
.. .. .. m cross m mem em__w w:: cross mon_addr on_addr ,, m mon_r on_r w w;; endgroup endgroup
cov_ mem cov_m em__acc acc m mem em_c _ c == new new;; DUT interface DUT
always always begin begin .. .. ..
tt rr ans ans.. get get (( tt x) x) ;;
Blocking
Instance
program vs. module SystemVerilog pr ogr am-level code:
Test program initial
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pr ogr am Randomization, classes Postponed sampling and updating Dynamic creation of objects
Master Agent Sequence driver
Config
SystemVerilog modul e-level code: Protocol check Coverage collector Monitor
BFM interface Monitor BFM module
DUT interface
• modul e, i nt er f ace • Verilog simulation semantics • Static object hierarchy
Test Configuration and Control program esst _ p ( ) ; program tte initial initial begin begin randcase randcase
60: 60: begin begin der Transaction template der ii ved_t ved_t rr ans_c ans_c tt ;; tt == new new;; env. env. m mast ast er er .. a0. a0. seq_i seq_i nst nst .. set set _gener _gener at at ed_t ed_t rr ans( ans( tt )) ;; end end
Sequence generator
40: 40: begin begin .. .. ..
Alternative test cases
endcase endcase start_test(); start_test();
.. .. .. # #100; 100;
URM Package methods
Conclusions •
Testbench architecture consists of modules plus a program
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Test program can pass randomized transactions to sequence driver Does not require expertise in object-oriented programming
Test program is compact and easy to modify
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DUT, BFM and sequence driver are independent
Classes used for transactions only
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Coding style similar to Verilog and VHDL
Uses "standard" infrastructure provided by UVCs
Assertions check protocol throughout simulation
